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1/*
2 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
3 * JZ4740 platform PWM support
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * You should have received a copy of the GNU General Public License along
11 * with this program; if not, write to the Free Software Foundation, Inc.,
12 * 675 Mass Ave, Cambridge, MA 02139, USA.
13 *
14 */
15
16#include <linux/clk.h>
17#include <linux/err.h>
18#include <linux/gpio.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/of_device.h>
22#include <linux/platform_device.h>
23#include <linux/pwm.h>
24
25#include <asm/mach-jz4740/timer.h>
26
27#define NUM_PWM 8
28
29struct jz4740_pwm_chip {
30 struct pwm_chip chip;
31 struct clk *clk;
32};
33
34static inline struct jz4740_pwm_chip *to_jz4740(struct pwm_chip *chip)
35{
36 return container_of(chip, struct jz4740_pwm_chip, chip);
37}
38
39static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
40{
41 /*
42 * Timers 0 and 1 are used for system tasks, so they are unavailable
43 * for use as PWMs.
44 */
45 if (pwm->hwpwm < 2)
46 return -EBUSY;
47
48 jz4740_timer_start(pwm->hwpwm);
49
50 return 0;
51}
52
53static void jz4740_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
54{
55 jz4740_timer_set_ctrl(pwm->hwpwm, 0);
56
57 jz4740_timer_stop(pwm->hwpwm);
58}
59
60static int jz4740_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
61{
62 uint32_t ctrl = jz4740_timer_get_ctrl(pwm->pwm);
63
64 ctrl |= JZ_TIMER_CTRL_PWM_ENABLE;
65 jz4740_timer_set_ctrl(pwm->hwpwm, ctrl);
66 jz4740_timer_enable(pwm->hwpwm);
67
68 return 0;
69}
70
71static void jz4740_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
72{
73 uint32_t ctrl = jz4740_timer_get_ctrl(pwm->hwpwm);
74
75 /* Disable PWM output.
76 * In TCU2 mode (channel 1/2 on JZ4750+), this must be done before the
77 * counter is stopped, while in TCU1 mode the order does not matter.
78 */
79 ctrl &= ~JZ_TIMER_CTRL_PWM_ENABLE;
80 jz4740_timer_set_ctrl(pwm->hwpwm, ctrl);
81
82 /* Stop counter */
83 jz4740_timer_disable(pwm->hwpwm);
84}
85
86static int jz4740_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
87 int duty_ns, int period_ns)
88{
89 struct jz4740_pwm_chip *jz4740 = to_jz4740(pwm->chip);
90 unsigned long long tmp;
91 unsigned long period, duty;
92 unsigned int prescaler = 0;
93 uint16_t ctrl;
94 bool is_enabled;
95
96 tmp = (unsigned long long)clk_get_rate(jz4740->clk) * period_ns;
97 do_div(tmp, 1000000000);
98 period = tmp;
99
100 while (period > 0xffff && prescaler < 6) {
101 period >>= 2;
102 ++prescaler;
103 }
104
105 if (prescaler == 6)
106 return -EINVAL;
107
108 tmp = (unsigned long long)period * duty_ns;
109 do_div(tmp, period_ns);
110 duty = period - tmp;
111
112 if (duty >= period)
113 duty = period - 1;
114
115 is_enabled = jz4740_timer_is_enabled(pwm->hwpwm);
116 if (is_enabled)
117 jz4740_pwm_disable(chip, pwm);
118
119 jz4740_timer_set_count(pwm->hwpwm, 0);
120 jz4740_timer_set_duty(pwm->hwpwm, duty);
121 jz4740_timer_set_period(pwm->hwpwm, period);
122
123 ctrl = JZ_TIMER_CTRL_PRESCALER(prescaler) | JZ_TIMER_CTRL_SRC_EXT |
124 JZ_TIMER_CTRL_PWM_ABBRUPT_SHUTDOWN;
125
126 jz4740_timer_set_ctrl(pwm->hwpwm, ctrl);
127
128 if (is_enabled)
129 jz4740_pwm_enable(chip, pwm);
130
131 return 0;
132}
133
134static int jz4740_pwm_set_polarity(struct pwm_chip *chip,
135 struct pwm_device *pwm, enum pwm_polarity polarity)
136{
137 uint32_t ctrl = jz4740_timer_get_ctrl(pwm->pwm);
138
139 switch (polarity) {
140 case PWM_POLARITY_NORMAL:
141 ctrl &= ~JZ_TIMER_CTRL_PWM_ACTIVE_LOW;
142 break;
143 case PWM_POLARITY_INVERSED:
144 ctrl |= JZ_TIMER_CTRL_PWM_ACTIVE_LOW;
145 break;
146 }
147
148 jz4740_timer_set_ctrl(pwm->hwpwm, ctrl);
149 return 0;
150}
151
152static const struct pwm_ops jz4740_pwm_ops = {
153 .request = jz4740_pwm_request,
154 .free = jz4740_pwm_free,
155 .config = jz4740_pwm_config,
156 .set_polarity = jz4740_pwm_set_polarity,
157 .enable = jz4740_pwm_enable,
158 .disable = jz4740_pwm_disable,
159 .owner = THIS_MODULE,
160};
161
162static int jz4740_pwm_probe(struct platform_device *pdev)
163{
164 struct jz4740_pwm_chip *jz4740;
165
166 jz4740 = devm_kzalloc(&pdev->dev, sizeof(*jz4740), GFP_KERNEL);
167 if (!jz4740)
168 return -ENOMEM;
169
170 jz4740->clk = devm_clk_get(&pdev->dev, "ext");
171 if (IS_ERR(jz4740->clk))
172 return PTR_ERR(jz4740->clk);
173
174 jz4740->chip.dev = &pdev->dev;
175 jz4740->chip.ops = &jz4740_pwm_ops;
176 jz4740->chip.npwm = NUM_PWM;
177 jz4740->chip.base = -1;
178 jz4740->chip.of_xlate = of_pwm_xlate_with_flags;
179 jz4740->chip.of_pwm_n_cells = 3;
180
181 platform_set_drvdata(pdev, jz4740);
182
183 return pwmchip_add(&jz4740->chip);
184}
185
186static int jz4740_pwm_remove(struct platform_device *pdev)
187{
188 struct jz4740_pwm_chip *jz4740 = platform_get_drvdata(pdev);
189
190 return pwmchip_remove(&jz4740->chip);
191}
192
193#ifdef CONFIG_OF
194static const struct of_device_id jz4740_pwm_dt_ids[] = {
195 { .compatible = "ingenic,jz4740-pwm", },
196 { .compatible = "ingenic,jz4770-pwm", },
197 { .compatible = "ingenic,jz4780-pwm", },
198 {},
199};
200MODULE_DEVICE_TABLE(of, jz4740_pwm_dt_ids);
201#endif
202
203static struct platform_driver jz4740_pwm_driver = {
204 .driver = {
205 .name = "jz4740-pwm",
206 .of_match_table = of_match_ptr(jz4740_pwm_dt_ids),
207 },
208 .probe = jz4740_pwm_probe,
209 .remove = jz4740_pwm_remove,
210};
211module_platform_driver(jz4740_pwm_driver);
212
213MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
214MODULE_DESCRIPTION("Ingenic JZ4740 PWM driver");
215MODULE_ALIAS("platform:jz4740-pwm");
216MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
4 * JZ4740 platform PWM support
5 *
6 * Limitations:
7 * - The .apply callback doesn't complete the currently running period before
8 * reconfiguring the hardware.
9 */
10
11#include <linux/clk.h>
12#include <linux/err.h>
13#include <linux/gpio.h>
14#include <linux/kernel.h>
15#include <linux/mfd/ingenic-tcu.h>
16#include <linux/mfd/syscon.h>
17#include <linux/module.h>
18#include <linux/of_device.h>
19#include <linux/platform_device.h>
20#include <linux/pwm.h>
21#include <linux/regmap.h>
22
23struct soc_info {
24 unsigned int num_pwms;
25};
26
27struct jz4740_pwm_chip {
28 struct pwm_chip chip;
29 struct regmap *map;
30};
31
32static inline struct jz4740_pwm_chip *to_jz4740(struct pwm_chip *chip)
33{
34 return container_of(chip, struct jz4740_pwm_chip, chip);
35}
36
37static bool jz4740_pwm_can_use_chn(struct jz4740_pwm_chip *jz,
38 unsigned int channel)
39{
40 /* Enable all TCU channels for PWM use by default except channels 0/1 */
41 u32 pwm_channels_mask = GENMASK(jz->chip.npwm - 1, 2);
42
43 device_property_read_u32(jz->chip.dev->parent,
44 "ingenic,pwm-channels-mask",
45 &pwm_channels_mask);
46
47 return !!(pwm_channels_mask & BIT(channel));
48}
49
50static int jz4740_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
51{
52 struct jz4740_pwm_chip *jz = to_jz4740(chip);
53 struct clk *clk;
54 char name[16];
55 int err;
56
57 if (!jz4740_pwm_can_use_chn(jz, pwm->hwpwm))
58 return -EBUSY;
59
60 snprintf(name, sizeof(name), "timer%u", pwm->hwpwm);
61
62 clk = clk_get(chip->dev, name);
63 if (IS_ERR(clk)) {
64 if (PTR_ERR(clk) != -EPROBE_DEFER)
65 dev_err(chip->dev, "Failed to get clock: %pe", clk);
66
67 return PTR_ERR(clk);
68 }
69
70 err = clk_prepare_enable(clk);
71 if (err < 0) {
72 clk_put(clk);
73 return err;
74 }
75
76 pwm_set_chip_data(pwm, clk);
77
78 return 0;
79}
80
81static void jz4740_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
82{
83 struct clk *clk = pwm_get_chip_data(pwm);
84
85 clk_disable_unprepare(clk);
86 clk_put(clk);
87}
88
89static int jz4740_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
90{
91 struct jz4740_pwm_chip *jz = to_jz4740(chip);
92
93 /* Enable PWM output */
94 regmap_update_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm),
95 TCU_TCSR_PWM_EN, TCU_TCSR_PWM_EN);
96
97 /* Start counter */
98 regmap_write(jz->map, TCU_REG_TESR, BIT(pwm->hwpwm));
99
100 return 0;
101}
102
103static void jz4740_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
104{
105 struct jz4740_pwm_chip *jz = to_jz4740(chip);
106
107 /*
108 * Set duty > period. This trick allows the TCU channels in TCU2 mode to
109 * properly return to their init level.
110 */
111 regmap_write(jz->map, TCU_REG_TDHRc(pwm->hwpwm), 0xffff);
112 regmap_write(jz->map, TCU_REG_TDFRc(pwm->hwpwm), 0x0);
113
114 /*
115 * Disable PWM output.
116 * In TCU2 mode (channel 1/2 on JZ4750+), this must be done before the
117 * counter is stopped, while in TCU1 mode the order does not matter.
118 */
119 regmap_update_bits(jz->map, TCU_REG_TCSRc(pwm->hwpwm),
120 TCU_TCSR_PWM_EN, 0);
121
122 /* Stop counter */
123 regmap_write(jz->map, TCU_REG_TECR, BIT(pwm->hwpwm));
124}
125
126static int jz4740_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
127 const struct pwm_state *state)
128{
129 struct jz4740_pwm_chip *jz4740 = to_jz4740(pwm->chip);
130 unsigned long long tmp = 0xffffull * NSEC_PER_SEC;
131 struct clk *clk = pwm_get_chip_data(pwm);
132 unsigned long period, duty;
133 long rate;
134 int err;
135
136 /*
137 * Limit the clock to a maximum rate that still gives us a period value
138 * which fits in 16 bits.
139 */
140 do_div(tmp, state->period);
141
142 /*
143 * /!\ IMPORTANT NOTE:
144 * -------------------
145 * This code relies on the fact that clk_round_rate() will always round
146 * down, which is not a valid assumption given by the clk API, but only
147 * happens to be true with the clk drivers used for Ingenic SoCs.
148 *
149 * Right now, there is no alternative as the clk API does not have a
150 * round-down function (and won't have one for a while), but if it ever
151 * comes to light, a round-down function should be used instead.
152 */
153 rate = clk_round_rate(clk, tmp);
154 if (rate < 0) {
155 dev_err(chip->dev, "Unable to round rate: %ld", rate);
156 return rate;
157 }
158
159 /* Calculate period value */
160 tmp = (unsigned long long)rate * state->period;
161 do_div(tmp, NSEC_PER_SEC);
162 period = tmp;
163
164 /* Calculate duty value */
165 tmp = (unsigned long long)rate * state->duty_cycle;
166 do_div(tmp, NSEC_PER_SEC);
167 duty = tmp;
168
169 if (duty >= period)
170 duty = period - 1;
171
172 jz4740_pwm_disable(chip, pwm);
173
174 err = clk_set_rate(clk, rate);
175 if (err) {
176 dev_err(chip->dev, "Unable to set rate: %d", err);
177 return err;
178 }
179
180 /* Reset counter to 0 */
181 regmap_write(jz4740->map, TCU_REG_TCNTc(pwm->hwpwm), 0);
182
183 /* Set duty */
184 regmap_write(jz4740->map, TCU_REG_TDHRc(pwm->hwpwm), duty);
185
186 /* Set period */
187 regmap_write(jz4740->map, TCU_REG_TDFRc(pwm->hwpwm), period);
188
189 /* Set abrupt shutdown */
190 regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm),
191 TCU_TCSR_PWM_SD, TCU_TCSR_PWM_SD);
192
193 /*
194 * Set polarity.
195 *
196 * The PWM starts in inactive state until the internal timer reaches the
197 * duty value, then becomes active until the timer reaches the period
198 * value. In theory, we should then use (period - duty) as the real duty
199 * value, as a high duty value would otherwise result in the PWM pin
200 * being inactive most of the time.
201 *
202 * Here, we don't do that, and instead invert the polarity of the PWM
203 * when it is active. This trick makes the PWM start with its active
204 * state instead of its inactive state.
205 */
206 if ((state->polarity == PWM_POLARITY_NORMAL) ^ state->enabled)
207 regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm),
208 TCU_TCSR_PWM_INITL_HIGH, 0);
209 else
210 regmap_update_bits(jz4740->map, TCU_REG_TCSRc(pwm->hwpwm),
211 TCU_TCSR_PWM_INITL_HIGH,
212 TCU_TCSR_PWM_INITL_HIGH);
213
214 if (state->enabled)
215 jz4740_pwm_enable(chip, pwm);
216
217 return 0;
218}
219
220static const struct pwm_ops jz4740_pwm_ops = {
221 .request = jz4740_pwm_request,
222 .free = jz4740_pwm_free,
223 .apply = jz4740_pwm_apply,
224 .owner = THIS_MODULE,
225};
226
227static int jz4740_pwm_probe(struct platform_device *pdev)
228{
229 struct device *dev = &pdev->dev;
230 struct jz4740_pwm_chip *jz4740;
231 const struct soc_info *info;
232
233 info = device_get_match_data(dev);
234 if (!info)
235 return -EINVAL;
236
237 jz4740 = devm_kzalloc(dev, sizeof(*jz4740), GFP_KERNEL);
238 if (!jz4740)
239 return -ENOMEM;
240
241 jz4740->map = device_node_to_regmap(dev->parent->of_node);
242 if (IS_ERR(jz4740->map)) {
243 dev_err(dev, "regmap not found: %ld\n", PTR_ERR(jz4740->map));
244 return PTR_ERR(jz4740->map);
245 }
246
247 jz4740->chip.dev = dev;
248 jz4740->chip.ops = &jz4740_pwm_ops;
249 jz4740->chip.npwm = info->num_pwms;
250 jz4740->chip.base = -1;
251 jz4740->chip.of_xlate = of_pwm_xlate_with_flags;
252 jz4740->chip.of_pwm_n_cells = 3;
253
254 platform_set_drvdata(pdev, jz4740);
255
256 return pwmchip_add(&jz4740->chip);
257}
258
259static int jz4740_pwm_remove(struct platform_device *pdev)
260{
261 struct jz4740_pwm_chip *jz4740 = platform_get_drvdata(pdev);
262
263 return pwmchip_remove(&jz4740->chip);
264}
265
266static const struct soc_info __maybe_unused jz4740_soc_info = {
267 .num_pwms = 8,
268};
269
270static const struct soc_info __maybe_unused jz4725b_soc_info = {
271 .num_pwms = 6,
272};
273
274#ifdef CONFIG_OF
275static const struct of_device_id jz4740_pwm_dt_ids[] = {
276 { .compatible = "ingenic,jz4740-pwm", .data = &jz4740_soc_info },
277 { .compatible = "ingenic,jz4725b-pwm", .data = &jz4725b_soc_info },
278 {},
279};
280MODULE_DEVICE_TABLE(of, jz4740_pwm_dt_ids);
281#endif
282
283static struct platform_driver jz4740_pwm_driver = {
284 .driver = {
285 .name = "jz4740-pwm",
286 .of_match_table = of_match_ptr(jz4740_pwm_dt_ids),
287 },
288 .probe = jz4740_pwm_probe,
289 .remove = jz4740_pwm_remove,
290};
291module_platform_driver(jz4740_pwm_driver);
292
293MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
294MODULE_DESCRIPTION("Ingenic JZ4740 PWM driver");
295MODULE_ALIAS("platform:jz4740-pwm");
296MODULE_LICENSE("GPL");