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1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "amdgpu.h"
25#include "amdgpu_ih.h"
26#include "amdgpu_gfx.h"
27#include "amdgpu_ucode.h"
28#include "clearstate_si.h"
29#include "bif/bif_3_0_d.h"
30#include "bif/bif_3_0_sh_mask.h"
31#include "oss/oss_1_0_d.h"
32#include "oss/oss_1_0_sh_mask.h"
33#include "gca/gfx_6_0_d.h"
34#include "gca/gfx_6_0_sh_mask.h"
35#include "gmc/gmc_6_0_d.h"
36#include "gmc/gmc_6_0_sh_mask.h"
37#include "dce/dce_6_0_d.h"
38#include "dce/dce_6_0_sh_mask.h"
39#include "gca/gfx_7_2_enum.h"
40#include "si_enums.h"
41#include "si.h"
42
43static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
44static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
45static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev);
46
47MODULE_FIRMWARE("radeon/tahiti_pfp.bin");
48MODULE_FIRMWARE("radeon/tahiti_me.bin");
49MODULE_FIRMWARE("radeon/tahiti_ce.bin");
50MODULE_FIRMWARE("radeon/tahiti_rlc.bin");
51
52MODULE_FIRMWARE("radeon/pitcairn_pfp.bin");
53MODULE_FIRMWARE("radeon/pitcairn_me.bin");
54MODULE_FIRMWARE("radeon/pitcairn_ce.bin");
55MODULE_FIRMWARE("radeon/pitcairn_rlc.bin");
56
57MODULE_FIRMWARE("radeon/verde_pfp.bin");
58MODULE_FIRMWARE("radeon/verde_me.bin");
59MODULE_FIRMWARE("radeon/verde_ce.bin");
60MODULE_FIRMWARE("radeon/verde_rlc.bin");
61
62MODULE_FIRMWARE("radeon/oland_pfp.bin");
63MODULE_FIRMWARE("radeon/oland_me.bin");
64MODULE_FIRMWARE("radeon/oland_ce.bin");
65MODULE_FIRMWARE("radeon/oland_rlc.bin");
66
67MODULE_FIRMWARE("radeon/hainan_pfp.bin");
68MODULE_FIRMWARE("radeon/hainan_me.bin");
69MODULE_FIRMWARE("radeon/hainan_ce.bin");
70MODULE_FIRMWARE("radeon/hainan_rlc.bin");
71
72static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
73static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
74//static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev);
75static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
76
77#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
78#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
79#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
80#define MICRO_TILE_MODE(x) ((x) << 0)
81#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
82#define BANK_WIDTH(x) ((x) << 14)
83#define BANK_HEIGHT(x) ((x) << 16)
84#define MACRO_TILE_ASPECT(x) ((x) << 18)
85#define NUM_BANKS(x) ((x) << 20)
86
87static const u32 verde_rlc_save_restore_register_list[] =
88{
89 (0x8000 << 16) | (0x98f4 >> 2),
90 0x00000000,
91 (0x8040 << 16) | (0x98f4 >> 2),
92 0x00000000,
93 (0x8000 << 16) | (0xe80 >> 2),
94 0x00000000,
95 (0x8040 << 16) | (0xe80 >> 2),
96 0x00000000,
97 (0x8000 << 16) | (0x89bc >> 2),
98 0x00000000,
99 (0x8040 << 16) | (0x89bc >> 2),
100 0x00000000,
101 (0x8000 << 16) | (0x8c1c >> 2),
102 0x00000000,
103 (0x8040 << 16) | (0x8c1c >> 2),
104 0x00000000,
105 (0x9c00 << 16) | (0x98f0 >> 2),
106 0x00000000,
107 (0x9c00 << 16) | (0xe7c >> 2),
108 0x00000000,
109 (0x8000 << 16) | (0x9148 >> 2),
110 0x00000000,
111 (0x8040 << 16) | (0x9148 >> 2),
112 0x00000000,
113 (0x9c00 << 16) | (0x9150 >> 2),
114 0x00000000,
115 (0x9c00 << 16) | (0x897c >> 2),
116 0x00000000,
117 (0x9c00 << 16) | (0x8d8c >> 2),
118 0x00000000,
119 (0x9c00 << 16) | (0xac54 >> 2),
120 0X00000000,
121 0x3,
122 (0x9c00 << 16) | (0x98f8 >> 2),
123 0x00000000,
124 (0x9c00 << 16) | (0x9910 >> 2),
125 0x00000000,
126 (0x9c00 << 16) | (0x9914 >> 2),
127 0x00000000,
128 (0x9c00 << 16) | (0x9918 >> 2),
129 0x00000000,
130 (0x9c00 << 16) | (0x991c >> 2),
131 0x00000000,
132 (0x9c00 << 16) | (0x9920 >> 2),
133 0x00000000,
134 (0x9c00 << 16) | (0x9924 >> 2),
135 0x00000000,
136 (0x9c00 << 16) | (0x9928 >> 2),
137 0x00000000,
138 (0x9c00 << 16) | (0x992c >> 2),
139 0x00000000,
140 (0x9c00 << 16) | (0x9930 >> 2),
141 0x00000000,
142 (0x9c00 << 16) | (0x9934 >> 2),
143 0x00000000,
144 (0x9c00 << 16) | (0x9938 >> 2),
145 0x00000000,
146 (0x9c00 << 16) | (0x993c >> 2),
147 0x00000000,
148 (0x9c00 << 16) | (0x9940 >> 2),
149 0x00000000,
150 (0x9c00 << 16) | (0x9944 >> 2),
151 0x00000000,
152 (0x9c00 << 16) | (0x9948 >> 2),
153 0x00000000,
154 (0x9c00 << 16) | (0x994c >> 2),
155 0x00000000,
156 (0x9c00 << 16) | (0x9950 >> 2),
157 0x00000000,
158 (0x9c00 << 16) | (0x9954 >> 2),
159 0x00000000,
160 (0x9c00 << 16) | (0x9958 >> 2),
161 0x00000000,
162 (0x9c00 << 16) | (0x995c >> 2),
163 0x00000000,
164 (0x9c00 << 16) | (0x9960 >> 2),
165 0x00000000,
166 (0x9c00 << 16) | (0x9964 >> 2),
167 0x00000000,
168 (0x9c00 << 16) | (0x9968 >> 2),
169 0x00000000,
170 (0x9c00 << 16) | (0x996c >> 2),
171 0x00000000,
172 (0x9c00 << 16) | (0x9970 >> 2),
173 0x00000000,
174 (0x9c00 << 16) | (0x9974 >> 2),
175 0x00000000,
176 (0x9c00 << 16) | (0x9978 >> 2),
177 0x00000000,
178 (0x9c00 << 16) | (0x997c >> 2),
179 0x00000000,
180 (0x9c00 << 16) | (0x9980 >> 2),
181 0x00000000,
182 (0x9c00 << 16) | (0x9984 >> 2),
183 0x00000000,
184 (0x9c00 << 16) | (0x9988 >> 2),
185 0x00000000,
186 (0x9c00 << 16) | (0x998c >> 2),
187 0x00000000,
188 (0x9c00 << 16) | (0x8c00 >> 2),
189 0x00000000,
190 (0x9c00 << 16) | (0x8c14 >> 2),
191 0x00000000,
192 (0x9c00 << 16) | (0x8c04 >> 2),
193 0x00000000,
194 (0x9c00 << 16) | (0x8c08 >> 2),
195 0x00000000,
196 (0x8000 << 16) | (0x9b7c >> 2),
197 0x00000000,
198 (0x8040 << 16) | (0x9b7c >> 2),
199 0x00000000,
200 (0x8000 << 16) | (0xe84 >> 2),
201 0x00000000,
202 (0x8040 << 16) | (0xe84 >> 2),
203 0x00000000,
204 (0x8000 << 16) | (0x89c0 >> 2),
205 0x00000000,
206 (0x8040 << 16) | (0x89c0 >> 2),
207 0x00000000,
208 (0x8000 << 16) | (0x914c >> 2),
209 0x00000000,
210 (0x8040 << 16) | (0x914c >> 2),
211 0x00000000,
212 (0x8000 << 16) | (0x8c20 >> 2),
213 0x00000000,
214 (0x8040 << 16) | (0x8c20 >> 2),
215 0x00000000,
216 (0x8000 << 16) | (0x9354 >> 2),
217 0x00000000,
218 (0x8040 << 16) | (0x9354 >> 2),
219 0x00000000,
220 (0x9c00 << 16) | (0x9060 >> 2),
221 0x00000000,
222 (0x9c00 << 16) | (0x9364 >> 2),
223 0x00000000,
224 (0x9c00 << 16) | (0x9100 >> 2),
225 0x00000000,
226 (0x9c00 << 16) | (0x913c >> 2),
227 0x00000000,
228 (0x8000 << 16) | (0x90e0 >> 2),
229 0x00000000,
230 (0x8000 << 16) | (0x90e4 >> 2),
231 0x00000000,
232 (0x8000 << 16) | (0x90e8 >> 2),
233 0x00000000,
234 (0x8040 << 16) | (0x90e0 >> 2),
235 0x00000000,
236 (0x8040 << 16) | (0x90e4 >> 2),
237 0x00000000,
238 (0x8040 << 16) | (0x90e8 >> 2),
239 0x00000000,
240 (0x9c00 << 16) | (0x8bcc >> 2),
241 0x00000000,
242 (0x9c00 << 16) | (0x8b24 >> 2),
243 0x00000000,
244 (0x9c00 << 16) | (0x88c4 >> 2),
245 0x00000000,
246 (0x9c00 << 16) | (0x8e50 >> 2),
247 0x00000000,
248 (0x9c00 << 16) | (0x8c0c >> 2),
249 0x00000000,
250 (0x9c00 << 16) | (0x8e58 >> 2),
251 0x00000000,
252 (0x9c00 << 16) | (0x8e5c >> 2),
253 0x00000000,
254 (0x9c00 << 16) | (0x9508 >> 2),
255 0x00000000,
256 (0x9c00 << 16) | (0x950c >> 2),
257 0x00000000,
258 (0x9c00 << 16) | (0x9494 >> 2),
259 0x00000000,
260 (0x9c00 << 16) | (0xac0c >> 2),
261 0x00000000,
262 (0x9c00 << 16) | (0xac10 >> 2),
263 0x00000000,
264 (0x9c00 << 16) | (0xac14 >> 2),
265 0x00000000,
266 (0x9c00 << 16) | (0xae00 >> 2),
267 0x00000000,
268 (0x9c00 << 16) | (0xac08 >> 2),
269 0x00000000,
270 (0x9c00 << 16) | (0x88d4 >> 2),
271 0x00000000,
272 (0x9c00 << 16) | (0x88c8 >> 2),
273 0x00000000,
274 (0x9c00 << 16) | (0x88cc >> 2),
275 0x00000000,
276 (0x9c00 << 16) | (0x89b0 >> 2),
277 0x00000000,
278 (0x9c00 << 16) | (0x8b10 >> 2),
279 0x00000000,
280 (0x9c00 << 16) | (0x8a14 >> 2),
281 0x00000000,
282 (0x9c00 << 16) | (0x9830 >> 2),
283 0x00000000,
284 (0x9c00 << 16) | (0x9834 >> 2),
285 0x00000000,
286 (0x9c00 << 16) | (0x9838 >> 2),
287 0x00000000,
288 (0x9c00 << 16) | (0x9a10 >> 2),
289 0x00000000,
290 (0x8000 << 16) | (0x9870 >> 2),
291 0x00000000,
292 (0x8000 << 16) | (0x9874 >> 2),
293 0x00000000,
294 (0x8001 << 16) | (0x9870 >> 2),
295 0x00000000,
296 (0x8001 << 16) | (0x9874 >> 2),
297 0x00000000,
298 (0x8040 << 16) | (0x9870 >> 2),
299 0x00000000,
300 (0x8040 << 16) | (0x9874 >> 2),
301 0x00000000,
302 (0x8041 << 16) | (0x9870 >> 2),
303 0x00000000,
304 (0x8041 << 16) | (0x9874 >> 2),
305 0x00000000,
306 0x00000000
307};
308
309static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
310{
311 const char *chip_name;
312 char fw_name[30];
313 int err;
314 const struct gfx_firmware_header_v1_0 *cp_hdr;
315 const struct rlc_firmware_header_v1_0 *rlc_hdr;
316
317 DRM_DEBUG("\n");
318
319 switch (adev->asic_type) {
320 case CHIP_TAHITI:
321 chip_name = "tahiti";
322 break;
323 case CHIP_PITCAIRN:
324 chip_name = "pitcairn";
325 break;
326 case CHIP_VERDE:
327 chip_name = "verde";
328 break;
329 case CHIP_OLAND:
330 chip_name = "oland";
331 break;
332 case CHIP_HAINAN:
333 chip_name = "hainan";
334 break;
335 default: BUG();
336 }
337
338 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
339 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
340 if (err)
341 goto out;
342 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
343 if (err)
344 goto out;
345 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
346 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
347 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
348
349 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
350 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
351 if (err)
352 goto out;
353 err = amdgpu_ucode_validate(adev->gfx.me_fw);
354 if (err)
355 goto out;
356 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
357 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
358 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
359
360 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
361 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
362 if (err)
363 goto out;
364 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
365 if (err)
366 goto out;
367 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
368 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
369 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
370
371 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
372 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
373 if (err)
374 goto out;
375 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
376 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
377 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
378 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
379
380out:
381 if (err) {
382 pr_err("gfx6: Failed to load firmware \"%s\"\n", fw_name);
383 release_firmware(adev->gfx.pfp_fw);
384 adev->gfx.pfp_fw = NULL;
385 release_firmware(adev->gfx.me_fw);
386 adev->gfx.me_fw = NULL;
387 release_firmware(adev->gfx.ce_fw);
388 adev->gfx.ce_fw = NULL;
389 release_firmware(adev->gfx.rlc_fw);
390 adev->gfx.rlc_fw = NULL;
391 }
392 return err;
393}
394
395static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
396{
397 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
398 u32 reg_offset, split_equal_to_row_size, *tilemode;
399
400 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array));
401 tilemode = adev->gfx.config.tile_mode_array;
402
403 switch (adev->gfx.config.mem_row_size_in_kb) {
404 case 1:
405 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
406 break;
407 case 2:
408 default:
409 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
410 break;
411 case 4:
412 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
413 break;
414 }
415
416 if (adev->asic_type == CHIP_VERDE) {
417 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
418 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
419 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
420 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
421 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
422 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
423 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
424 NUM_BANKS(ADDR_SURF_16_BANK);
425 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
426 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
427 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
428 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
429 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
430 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
431 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
432 NUM_BANKS(ADDR_SURF_16_BANK);
433 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
434 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
435 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
436 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
437 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
438 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
439 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
440 NUM_BANKS(ADDR_SURF_16_BANK);
441 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
442 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
443 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
444 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
445 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
446 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
447 NUM_BANKS(ADDR_SURF_8_BANK) |
448 TILE_SPLIT(split_equal_to_row_size);
449 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
450 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
451 PIPE_CONFIG(ADDR_SURF_P4_8x16);
452 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
453 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
454 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
455 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
456 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
457 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
458 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
459 NUM_BANKS(ADDR_SURF_4_BANK);
460 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
461 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
462 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
463 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
464 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
465 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
466 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
467 NUM_BANKS(ADDR_SURF_4_BANK);
468 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
469 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
470 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
471 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
472 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
473 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
474 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
475 NUM_BANKS(ADDR_SURF_2_BANK);
476 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
477 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
478 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
479 PIPE_CONFIG(ADDR_SURF_P4_8x16);
480 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
481 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
482 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
483 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
484 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
485 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
486 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
487 NUM_BANKS(ADDR_SURF_16_BANK);
488 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
489 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
490 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
491 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
492 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
493 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
494 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
495 NUM_BANKS(ADDR_SURF_16_BANK);
496 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
497 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
498 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
499 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
500 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
501 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
502 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
503 NUM_BANKS(ADDR_SURF_16_BANK);
504 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
505 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
506 PIPE_CONFIG(ADDR_SURF_P4_8x16);
507 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
508 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
509 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
510 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
511 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
512 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
513 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
514 NUM_BANKS(ADDR_SURF_16_BANK);
515 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
516 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
517 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
518 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
519 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
520 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
521 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
522 NUM_BANKS(ADDR_SURF_16_BANK);
523 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
524 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
525 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
526 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
527 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
528 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
529 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
530 NUM_BANKS(ADDR_SURF_16_BANK);
531 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
532 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
533 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
534 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
535 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
536 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
537 NUM_BANKS(ADDR_SURF_16_BANK) |
538 TILE_SPLIT(split_equal_to_row_size);
539 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
540 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
541 PIPE_CONFIG(ADDR_SURF_P4_8x16);
542 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
543 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
544 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
545 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
547 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
548 NUM_BANKS(ADDR_SURF_16_BANK) |
549 TILE_SPLIT(split_equal_to_row_size);
550 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
551 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
552 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
553 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
554 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
555 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
556 NUM_BANKS(ADDR_SURF_16_BANK) |
557 TILE_SPLIT(split_equal_to_row_size);
558 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
559 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
560 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
561 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
562 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
563 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
564 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
565 NUM_BANKS(ADDR_SURF_8_BANK);
566 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
567 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
568 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
569 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
570 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
571 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
572 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
573 NUM_BANKS(ADDR_SURF_8_BANK);
574 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
575 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
576 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
577 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
578 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
579 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
580 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
581 NUM_BANKS(ADDR_SURF_4_BANK);
582 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
583 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
584 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
585 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
586 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
587 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
588 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
589 NUM_BANKS(ADDR_SURF_4_BANK);
590 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
591 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
592 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
593 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
594 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
595 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
596 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
597 NUM_BANKS(ADDR_SURF_2_BANK);
598 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
599 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
600 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
601 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
602 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
603 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
604 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
605 NUM_BANKS(ADDR_SURF_2_BANK);
606 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
607 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
608 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
609 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
610 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
611 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
612 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
613 NUM_BANKS(ADDR_SURF_2_BANK);
614 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
615 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
616 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
617 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
618 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
619 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
620 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
621 NUM_BANKS(ADDR_SURF_2_BANK);
622 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
623 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
624 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
625 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
626 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
627 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
628 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
629 NUM_BANKS(ADDR_SURF_2_BANK);
630 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
631 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
632 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
633 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
634 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
635 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
636 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
637 NUM_BANKS(ADDR_SURF_2_BANK);
638 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
639 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
640 } else if (adev->asic_type == CHIP_OLAND) {
641 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
642 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
643 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
644 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
645 NUM_BANKS(ADDR_SURF_16_BANK) |
646 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
647 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
648 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
649 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
650 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
651 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
652 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
653 NUM_BANKS(ADDR_SURF_16_BANK) |
654 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
655 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
656 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
657 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
658 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
659 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
660 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
661 NUM_BANKS(ADDR_SURF_16_BANK) |
662 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
663 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
664 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
665 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
666 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
667 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
668 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
669 NUM_BANKS(ADDR_SURF_16_BANK) |
670 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
671 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
672 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
673 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
674 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
675 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
676 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
677 NUM_BANKS(ADDR_SURF_16_BANK) |
678 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
679 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
680 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
681 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
682 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
683 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
684 TILE_SPLIT(split_equal_to_row_size) |
685 NUM_BANKS(ADDR_SURF_16_BANK) |
686 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
687 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
688 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
689 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
690 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
691 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
692 TILE_SPLIT(split_equal_to_row_size) |
693 NUM_BANKS(ADDR_SURF_16_BANK) |
694 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
695 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
696 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
697 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
698 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
699 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
700 TILE_SPLIT(split_equal_to_row_size) |
701 NUM_BANKS(ADDR_SURF_16_BANK) |
702 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
703 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
704 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
705 tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
706 ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
707 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
708 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
709 NUM_BANKS(ADDR_SURF_16_BANK) |
710 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
711 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
712 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
713 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
714 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
715 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
716 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
717 NUM_BANKS(ADDR_SURF_16_BANK) |
718 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
719 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
720 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
721 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
722 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
723 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
724 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
725 NUM_BANKS(ADDR_SURF_16_BANK) |
726 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
727 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
728 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
729 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
730 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
731 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
732 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
733 NUM_BANKS(ADDR_SURF_16_BANK) |
734 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
735 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
736 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
737 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
738 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
739 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
740 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
741 NUM_BANKS(ADDR_SURF_16_BANK) |
742 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
743 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
744 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
745 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
746 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
747 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
748 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
749 NUM_BANKS(ADDR_SURF_16_BANK) |
750 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
751 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
752 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
753 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
754 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
755 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
756 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
757 NUM_BANKS(ADDR_SURF_16_BANK) |
758 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
759 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
760 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
761 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
762 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
763 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
764 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
765 NUM_BANKS(ADDR_SURF_16_BANK) |
766 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
767 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
768 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
769 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
770 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
771 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
772 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
773 NUM_BANKS(ADDR_SURF_16_BANK) |
774 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
775 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
776 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
777 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
778 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
779 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
780 TILE_SPLIT(split_equal_to_row_size) |
781 NUM_BANKS(ADDR_SURF_16_BANK) |
782 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
783 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
784 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
785 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
786 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
787 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
788 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
789 NUM_BANKS(ADDR_SURF_16_BANK) |
790 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
791 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
792 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
793 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
794 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
795 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
796 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
797 NUM_BANKS(ADDR_SURF_16_BANK) |
798 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
799 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
800 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
801 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
802 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
803 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
804 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
805 NUM_BANKS(ADDR_SURF_16_BANK) |
806 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
807 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
808 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
809 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
810 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
811 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
812 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
813 NUM_BANKS(ADDR_SURF_16_BANK) |
814 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
815 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
816 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
817 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
818 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
819 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
820 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
821 NUM_BANKS(ADDR_SURF_8_BANK) |
822 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
823 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
824 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1);
825 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
826 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
827 } else if (adev->asic_type == CHIP_HAINAN) {
828 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
829 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
830 PIPE_CONFIG(ADDR_SURF_P2) |
831 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
832 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
833 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
834 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
835 NUM_BANKS(ADDR_SURF_16_BANK);
836 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
837 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
838 PIPE_CONFIG(ADDR_SURF_P2) |
839 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
840 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
841 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
842 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
843 NUM_BANKS(ADDR_SURF_16_BANK);
844 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
845 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
846 PIPE_CONFIG(ADDR_SURF_P2) |
847 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
848 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
849 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
850 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
851 NUM_BANKS(ADDR_SURF_16_BANK);
852 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
853 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
854 PIPE_CONFIG(ADDR_SURF_P2) |
855 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
856 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
857 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
858 NUM_BANKS(ADDR_SURF_8_BANK) |
859 TILE_SPLIT(split_equal_to_row_size);
860 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
861 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
862 PIPE_CONFIG(ADDR_SURF_P2);
863 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
864 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
865 PIPE_CONFIG(ADDR_SURF_P2) |
866 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
867 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
868 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
869 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
870 NUM_BANKS(ADDR_SURF_8_BANK);
871 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
872 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
873 PIPE_CONFIG(ADDR_SURF_P2) |
874 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
875 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
876 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
877 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
878 NUM_BANKS(ADDR_SURF_8_BANK);
879 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
880 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
881 PIPE_CONFIG(ADDR_SURF_P2) |
882 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
883 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
884 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
885 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
886 NUM_BANKS(ADDR_SURF_4_BANK);
887 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
888 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
889 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
890 PIPE_CONFIG(ADDR_SURF_P2);
891 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
892 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
893 PIPE_CONFIG(ADDR_SURF_P2) |
894 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
895 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
896 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
897 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
898 NUM_BANKS(ADDR_SURF_16_BANK);
899 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
900 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
901 PIPE_CONFIG(ADDR_SURF_P2) |
902 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
903 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
904 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
905 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
906 NUM_BANKS(ADDR_SURF_16_BANK);
907 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
908 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
909 PIPE_CONFIG(ADDR_SURF_P2) |
910 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
911 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
912 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
913 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
914 NUM_BANKS(ADDR_SURF_16_BANK);
915 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
916 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
917 PIPE_CONFIG(ADDR_SURF_P2);
918 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
919 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
920 PIPE_CONFIG(ADDR_SURF_P2) |
921 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
922 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
923 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
924 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
925 NUM_BANKS(ADDR_SURF_16_BANK);
926 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
927 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
928 PIPE_CONFIG(ADDR_SURF_P2) |
929 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
930 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
931 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
932 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
933 NUM_BANKS(ADDR_SURF_16_BANK);
934 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
935 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
936 PIPE_CONFIG(ADDR_SURF_P2) |
937 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
938 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
939 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
940 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
941 NUM_BANKS(ADDR_SURF_16_BANK);
942 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
943 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
944 PIPE_CONFIG(ADDR_SURF_P2) |
945 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
946 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
947 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
948 NUM_BANKS(ADDR_SURF_16_BANK) |
949 TILE_SPLIT(split_equal_to_row_size);
950 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
951 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
952 PIPE_CONFIG(ADDR_SURF_P2);
953 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
954 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
955 PIPE_CONFIG(ADDR_SURF_P2) |
956 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
957 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
958 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
959 NUM_BANKS(ADDR_SURF_16_BANK) |
960 TILE_SPLIT(split_equal_to_row_size);
961 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
962 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
963 PIPE_CONFIG(ADDR_SURF_P2) |
964 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
965 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
966 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
967 NUM_BANKS(ADDR_SURF_16_BANK) |
968 TILE_SPLIT(split_equal_to_row_size);
969 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
970 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
971 PIPE_CONFIG(ADDR_SURF_P2) |
972 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
973 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
974 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
975 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
976 NUM_BANKS(ADDR_SURF_8_BANK);
977 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
978 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
979 PIPE_CONFIG(ADDR_SURF_P2) |
980 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
981 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
982 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
983 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
984 NUM_BANKS(ADDR_SURF_8_BANK);
985 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
986 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
987 PIPE_CONFIG(ADDR_SURF_P2) |
988 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
989 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
990 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
991 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
992 NUM_BANKS(ADDR_SURF_8_BANK);
993 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
994 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
995 PIPE_CONFIG(ADDR_SURF_P2) |
996 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
997 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
998 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
999 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1000 NUM_BANKS(ADDR_SURF_8_BANK);
1001 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1002 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1003 PIPE_CONFIG(ADDR_SURF_P2) |
1004 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1005 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1006 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1007 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1008 NUM_BANKS(ADDR_SURF_4_BANK);
1009 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1010 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1011 PIPE_CONFIG(ADDR_SURF_P2) |
1012 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1013 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1014 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1015 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1016 NUM_BANKS(ADDR_SURF_4_BANK);
1017 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1018 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1019 PIPE_CONFIG(ADDR_SURF_P2) |
1020 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1021 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1022 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1023 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1024 NUM_BANKS(ADDR_SURF_4_BANK);
1025 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1026 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1027 PIPE_CONFIG(ADDR_SURF_P2) |
1028 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1029 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1030 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1031 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1032 NUM_BANKS(ADDR_SURF_4_BANK);
1033 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1034 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1035 PIPE_CONFIG(ADDR_SURF_P2) |
1036 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1037 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1038 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1039 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1040 NUM_BANKS(ADDR_SURF_4_BANK);
1041 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1042 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1043 PIPE_CONFIG(ADDR_SURF_P2) |
1044 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1045 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1046 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1047 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1048 NUM_BANKS(ADDR_SURF_4_BANK);
1049 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1050 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1051 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
1052 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1053 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1054 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1055 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1056 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1057 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1058 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1059 NUM_BANKS(ADDR_SURF_16_BANK);
1060 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1061 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1062 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1063 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1064 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1065 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1066 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1067 NUM_BANKS(ADDR_SURF_16_BANK);
1068 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1069 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1070 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1071 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1072 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1073 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1074 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1075 NUM_BANKS(ADDR_SURF_16_BANK);
1076 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1077 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1078 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1079 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1080 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1081 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1082 NUM_BANKS(ADDR_SURF_4_BANK) |
1083 TILE_SPLIT(split_equal_to_row_size);
1084 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1085 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1086 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1087 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1088 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1089 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1090 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1091 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1092 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1093 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1094 NUM_BANKS(ADDR_SURF_2_BANK);
1095 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1096 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1097 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1098 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1099 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1100 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1101 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1102 NUM_BANKS(ADDR_SURF_2_BANK);
1103 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1104 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1105 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1106 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1107 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1108 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1109 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1110 NUM_BANKS(ADDR_SURF_2_BANK);
1111 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
1112 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1113 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1114 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1115 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1116 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1117 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1118 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1119 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1120 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1121 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1122 NUM_BANKS(ADDR_SURF_16_BANK);
1123 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1124 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1125 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1126 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1127 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1128 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1129 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1130 NUM_BANKS(ADDR_SURF_16_BANK);
1131 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1132 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1133 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1134 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1135 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1136 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1137 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1138 NUM_BANKS(ADDR_SURF_16_BANK);
1139 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1140 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1141 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1142 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1143 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1144 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1145 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1146 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1147 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1148 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1149 NUM_BANKS(ADDR_SURF_16_BANK);
1150 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1151 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1152 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1153 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1154 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1155 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1156 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1157 NUM_BANKS(ADDR_SURF_16_BANK);
1158 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1159 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1160 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1161 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1162 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1163 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1164 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1165 NUM_BANKS(ADDR_SURF_16_BANK);
1166 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1167 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1168 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1169 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1170 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1171 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1172 NUM_BANKS(ADDR_SURF_16_BANK) |
1173 TILE_SPLIT(split_equal_to_row_size);
1174 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1175 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1176 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1177 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1178 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1179 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1180 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1181 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1182 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1183 NUM_BANKS(ADDR_SURF_16_BANK) |
1184 TILE_SPLIT(split_equal_to_row_size);
1185 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1186 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1187 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1188 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1189 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1190 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1191 NUM_BANKS(ADDR_SURF_16_BANK) |
1192 TILE_SPLIT(split_equal_to_row_size);
1193 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1194 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1195 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1196 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1197 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1198 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1199 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1200 NUM_BANKS(ADDR_SURF_4_BANK);
1201 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1202 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1203 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1204 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1205 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1206 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1207 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1208 NUM_BANKS(ADDR_SURF_4_BANK);
1209 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1210 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1211 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1212 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1213 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1214 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1215 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1216 NUM_BANKS(ADDR_SURF_2_BANK);
1217 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1218 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1219 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1220 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1221 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1222 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1223 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1224 NUM_BANKS(ADDR_SURF_2_BANK);
1225 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1226 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1227 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1228 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1229 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1230 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1231 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1232 NUM_BANKS(ADDR_SURF_2_BANK);
1233 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1234 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1235 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1236 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1237 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1238 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1239 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1240 NUM_BANKS(ADDR_SURF_2_BANK);
1241 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1242 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1243 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1244 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1245 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1246 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1247 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1248 NUM_BANKS(ADDR_SURF_2_BANK);
1249 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1250 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1251 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1252 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1253 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1254 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1255 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1256 NUM_BANKS(ADDR_SURF_2_BANK);
1257 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1258 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1259 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1260 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1261 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1262 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1263 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1264 NUM_BANKS(ADDR_SURF_2_BANK);
1265 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1266 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1267 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1268 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1269 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1270 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1271 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1272 NUM_BANKS(ADDR_SURF_2_BANK);
1273 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1274 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1275 } else {
1276 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1277 }
1278}
1279
1280static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1281 u32 sh_num, u32 instance)
1282{
1283 u32 data;
1284
1285 if (instance == 0xffffffff)
1286 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1287 else
1288 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1289
1290 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1291 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1292 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1293 else if (se_num == 0xffffffff)
1294 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1295 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1296 else if (sh_num == 0xffffffff)
1297 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1298 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1299 else
1300 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1301 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1302 WREG32(mmGRBM_GFX_INDEX, data);
1303}
1304
1305static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1306{
1307 u32 data, mask;
1308
1309 data = RREG32(mmCC_RB_BACKEND_DISABLE) |
1310 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1311
1312 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
1313
1314 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/
1315 adev->gfx.config.max_sh_per_se);
1316
1317 return ~data & mask;
1318}
1319
1320static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf)
1321{
1322 switch (adev->asic_type) {
1323 case CHIP_TAHITI:
1324 case CHIP_PITCAIRN:
1325 *rconf |=
1326 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) |
1327 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1328 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1329 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) |
1330 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) |
1331 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) |
1332 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT);
1333 break;
1334 case CHIP_VERDE:
1335 *rconf |=
1336 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1337 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1338 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT);
1339 break;
1340 case CHIP_OLAND:
1341 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT);
1342 break;
1343 case CHIP_HAINAN:
1344 *rconf |= 0x0;
1345 break;
1346 default:
1347 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1348 break;
1349 }
1350}
1351
1352static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1353 u32 raster_config, unsigned rb_mask,
1354 unsigned num_rb)
1355{
1356 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1357 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1358 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1359 unsigned rb_per_se = num_rb / num_se;
1360 unsigned se_mask[4];
1361 unsigned se;
1362
1363 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1364 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1365 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1366 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1367
1368 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1369 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1370 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1371
1372 for (se = 0; se < num_se; se++) {
1373 unsigned raster_config_se = raster_config;
1374 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1375 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1376 int idx = (se / 2) * 2;
1377
1378 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1379 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK;
1380
1381 if (!se_mask[idx])
1382 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1383 else
1384 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1385 }
1386
1387 pkr0_mask &= rb_mask;
1388 pkr1_mask &= rb_mask;
1389 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1390 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK;
1391
1392 if (!pkr0_mask)
1393 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1394 else
1395 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1396 }
1397
1398 if (rb_per_se >= 2) {
1399 unsigned rb0_mask = 1 << (se * rb_per_se);
1400 unsigned rb1_mask = rb0_mask << 1;
1401
1402 rb0_mask &= rb_mask;
1403 rb1_mask &= rb_mask;
1404 if (!rb0_mask || !rb1_mask) {
1405 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK;
1406
1407 if (!rb0_mask)
1408 raster_config_se |=
1409 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1410 else
1411 raster_config_se |=
1412 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1413 }
1414
1415 if (rb_per_se > 2) {
1416 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1417 rb1_mask = rb0_mask << 1;
1418 rb0_mask &= rb_mask;
1419 rb1_mask &= rb_mask;
1420 if (!rb0_mask || !rb1_mask) {
1421 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK;
1422
1423 if (!rb0_mask)
1424 raster_config_se |=
1425 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1426 else
1427 raster_config_se |=
1428 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1429 }
1430 }
1431 }
1432
1433 /* GRBM_GFX_INDEX has a different offset on SI */
1434 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1435 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1436 }
1437
1438 /* GRBM_GFX_INDEX has a different offset on SI */
1439 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1440}
1441
1442static void gfx_v6_0_setup_rb(struct amdgpu_device *adev)
1443{
1444 int i, j;
1445 u32 data;
1446 u32 raster_config = 0;
1447 u32 active_rbs = 0;
1448 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1449 adev->gfx.config.max_sh_per_se;
1450 unsigned num_rb_pipes;
1451
1452 mutex_lock(&adev->grbm_idx_mutex);
1453 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1454 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1455 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1456 data = gfx_v6_0_get_rb_active_bitmap(adev);
1457 active_rbs |= data <<
1458 ((i * adev->gfx.config.max_sh_per_se + j) *
1459 rb_bitmap_width_per_sh);
1460 }
1461 }
1462 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1463
1464 adev->gfx.config.backend_enable_mask = active_rbs;
1465 adev->gfx.config.num_rbs = hweight32(active_rbs);
1466
1467 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1468 adev->gfx.config.max_shader_engines, 16);
1469
1470 gfx_v6_0_raster_config(adev, &raster_config);
1471
1472 if (!adev->gfx.config.backend_enable_mask ||
1473 adev->gfx.config.num_rbs >= num_rb_pipes)
1474 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1475 else
1476 gfx_v6_0_write_harvested_raster_configs(adev, raster_config,
1477 adev->gfx.config.backend_enable_mask,
1478 num_rb_pipes);
1479
1480 /* cache the values for userspace */
1481 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1482 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1483 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1484 adev->gfx.config.rb_config[i][j].rb_backend_disable =
1485 RREG32(mmCC_RB_BACKEND_DISABLE);
1486 adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
1487 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1488 adev->gfx.config.rb_config[i][j].raster_config =
1489 RREG32(mmPA_SC_RASTER_CONFIG);
1490 }
1491 }
1492 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1493 mutex_unlock(&adev->grbm_idx_mutex);
1494}
1495
1496static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
1497 u32 bitmap)
1498{
1499 u32 data;
1500
1501 if (!bitmap)
1502 return;
1503
1504 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
1505 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
1506
1507 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
1508}
1509
1510static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev)
1511{
1512 u32 data, mask;
1513
1514 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
1515 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
1516
1517 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
1518 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
1519}
1520
1521
1522static void gfx_v6_0_setup_spi(struct amdgpu_device *adev)
1523{
1524 int i, j, k;
1525 u32 data, mask;
1526 u32 active_cu = 0;
1527
1528 mutex_lock(&adev->grbm_idx_mutex);
1529 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1530 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1531 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1532 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3);
1533 active_cu = gfx_v6_0_get_cu_enabled(adev);
1534
1535 mask = 1;
1536 for (k = 0; k < 16; k++) {
1537 mask <<= k;
1538 if (active_cu & mask) {
1539 data &= ~mask;
1540 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data);
1541 break;
1542 }
1543 }
1544 }
1545 }
1546 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1547 mutex_unlock(&adev->grbm_idx_mutex);
1548}
1549
1550static void gfx_v6_0_config_init(struct amdgpu_device *adev)
1551{
1552 adev->gfx.config.double_offchip_lds_buf = 0;
1553}
1554
1555static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
1556{
1557 u32 gb_addr_config = 0;
1558 u32 mc_shared_chmap, mc_arb_ramcfg;
1559 u32 sx_debug_1;
1560 u32 hdp_host_path_cntl;
1561 u32 tmp;
1562
1563 switch (adev->asic_type) {
1564 case CHIP_TAHITI:
1565 adev->gfx.config.max_shader_engines = 2;
1566 adev->gfx.config.max_tile_pipes = 12;
1567 adev->gfx.config.max_cu_per_sh = 8;
1568 adev->gfx.config.max_sh_per_se = 2;
1569 adev->gfx.config.max_backends_per_se = 4;
1570 adev->gfx.config.max_texture_channel_caches = 12;
1571 adev->gfx.config.max_gprs = 256;
1572 adev->gfx.config.max_gs_threads = 32;
1573 adev->gfx.config.max_hw_contexts = 8;
1574
1575 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1576 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1577 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1578 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1579 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1580 break;
1581 case CHIP_PITCAIRN:
1582 adev->gfx.config.max_shader_engines = 2;
1583 adev->gfx.config.max_tile_pipes = 8;
1584 adev->gfx.config.max_cu_per_sh = 5;
1585 adev->gfx.config.max_sh_per_se = 2;
1586 adev->gfx.config.max_backends_per_se = 4;
1587 adev->gfx.config.max_texture_channel_caches = 8;
1588 adev->gfx.config.max_gprs = 256;
1589 adev->gfx.config.max_gs_threads = 32;
1590 adev->gfx.config.max_hw_contexts = 8;
1591
1592 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1593 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1594 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1595 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1596 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1597 break;
1598 case CHIP_VERDE:
1599 adev->gfx.config.max_shader_engines = 1;
1600 adev->gfx.config.max_tile_pipes = 4;
1601 adev->gfx.config.max_cu_per_sh = 5;
1602 adev->gfx.config.max_sh_per_se = 2;
1603 adev->gfx.config.max_backends_per_se = 4;
1604 adev->gfx.config.max_texture_channel_caches = 4;
1605 adev->gfx.config.max_gprs = 256;
1606 adev->gfx.config.max_gs_threads = 32;
1607 adev->gfx.config.max_hw_contexts = 8;
1608
1609 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1610 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1611 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1612 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1613 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1614 break;
1615 case CHIP_OLAND:
1616 adev->gfx.config.max_shader_engines = 1;
1617 adev->gfx.config.max_tile_pipes = 4;
1618 adev->gfx.config.max_cu_per_sh = 6;
1619 adev->gfx.config.max_sh_per_se = 1;
1620 adev->gfx.config.max_backends_per_se = 2;
1621 adev->gfx.config.max_texture_channel_caches = 4;
1622 adev->gfx.config.max_gprs = 256;
1623 adev->gfx.config.max_gs_threads = 16;
1624 adev->gfx.config.max_hw_contexts = 8;
1625
1626 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1627 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1628 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1629 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1630 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1631 break;
1632 case CHIP_HAINAN:
1633 adev->gfx.config.max_shader_engines = 1;
1634 adev->gfx.config.max_tile_pipes = 4;
1635 adev->gfx.config.max_cu_per_sh = 5;
1636 adev->gfx.config.max_sh_per_se = 1;
1637 adev->gfx.config.max_backends_per_se = 1;
1638 adev->gfx.config.max_texture_channel_caches = 2;
1639 adev->gfx.config.max_gprs = 256;
1640 adev->gfx.config.max_gs_threads = 16;
1641 adev->gfx.config.max_hw_contexts = 8;
1642
1643 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1644 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1645 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1646 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1647 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
1648 break;
1649 default:
1650 BUG();
1651 break;
1652 }
1653
1654 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1655 WREG32(mmSRBM_INT_CNTL, 1);
1656 WREG32(mmSRBM_INT_ACK, 1);
1657
1658 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
1659
1660 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1661 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1662 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1663
1664 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1665 adev->gfx.config.mem_max_burst_length_bytes = 256;
1666 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
1667 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1668 if (adev->gfx.config.mem_row_size_in_kb > 4)
1669 adev->gfx.config.mem_row_size_in_kb = 4;
1670 adev->gfx.config.shader_engine_tile_size = 32;
1671 adev->gfx.config.num_gpus = 1;
1672 adev->gfx.config.multi_gpu_tile_size = 64;
1673
1674 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
1675 switch (adev->gfx.config.mem_row_size_in_kb) {
1676 case 1:
1677 default:
1678 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1679 break;
1680 case 2:
1681 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1682 break;
1683 case 4:
1684 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1685 break;
1686 }
1687 gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK;
1688 if (adev->gfx.config.max_shader_engines == 2)
1689 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT;
1690 adev->gfx.config.gb_addr_config = gb_addr_config;
1691
1692 WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
1693 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config);
1694 WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
1695 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
1696 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1697 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1698
1699#if 0
1700 if (adev->has_uvd) {
1701 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
1702 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1703 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1704 }
1705#endif
1706 gfx_v6_0_tiling_mode_table_init(adev);
1707
1708 gfx_v6_0_setup_rb(adev);
1709
1710 gfx_v6_0_setup_spi(adev);
1711
1712 gfx_v6_0_get_cu_info(adev);
1713 gfx_v6_0_config_init(adev);
1714
1715 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |
1716 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));
1717 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1718 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1719
1720 sx_debug_1 = RREG32(mmSX_DEBUG_1);
1721 WREG32(mmSX_DEBUG_1, sx_debug_1);
1722
1723 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1724
1725 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1726 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1727 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1728 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1729
1730 WREG32(mmVGT_NUM_INSTANCES, 1);
1731 WREG32(mmCP_PERFMON_CNTL, 0);
1732 WREG32(mmSQ_CONFIG, 0);
1733 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1734 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1735
1736 WREG32(mmVGT_CACHE_INVALIDATION,
1737 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1738 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1739
1740 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1741 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1742
1743 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0);
1744 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0);
1745 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0);
1746 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0);
1747 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0);
1748 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0);
1749 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0);
1750 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0);
1751
1752 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL);
1753 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1754
1755 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1756 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1757
1758 udelay(50);
1759}
1760
1761
1762static void gfx_v6_0_scratch_init(struct amdgpu_device *adev)
1763{
1764 adev->gfx.scratch.num_reg = 8;
1765 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
1766 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
1767}
1768
1769static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
1770{
1771 struct amdgpu_device *adev = ring->adev;
1772 uint32_t scratch;
1773 uint32_t tmp = 0;
1774 unsigned i;
1775 int r;
1776
1777 r = amdgpu_gfx_scratch_get(adev, &scratch);
1778 if (r) {
1779 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
1780 return r;
1781 }
1782 WREG32(scratch, 0xCAFEDEAD);
1783
1784 r = amdgpu_ring_alloc(ring, 3);
1785 if (r) {
1786 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
1787 amdgpu_gfx_scratch_free(adev, scratch);
1788 return r;
1789 }
1790 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1791 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START));
1792 amdgpu_ring_write(ring, 0xDEADBEEF);
1793 amdgpu_ring_commit(ring);
1794
1795 for (i = 0; i < adev->usec_timeout; i++) {
1796 tmp = RREG32(scratch);
1797 if (tmp == 0xDEADBEEF)
1798 break;
1799 DRM_UDELAY(1);
1800 }
1801 if (i < adev->usec_timeout) {
1802 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
1803 } else {
1804 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
1805 ring->idx, scratch, tmp);
1806 r = -EINVAL;
1807 }
1808 amdgpu_gfx_scratch_free(adev, scratch);
1809 return r;
1810}
1811
1812static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
1813{
1814 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
1815 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
1816 EVENT_INDEX(0));
1817}
1818
1819static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1820 u64 seq, unsigned flags)
1821{
1822 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1823 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1824 /* flush read cache over gart */
1825 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1826 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
1827 amdgpu_ring_write(ring, 0);
1828 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1829 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1830 PACKET3_TC_ACTION_ENA |
1831 PACKET3_SH_KCACHE_ACTION_ENA |
1832 PACKET3_SH_ICACHE_ACTION_ENA);
1833 amdgpu_ring_write(ring, 0xFFFFFFFF);
1834 amdgpu_ring_write(ring, 0);
1835 amdgpu_ring_write(ring, 10); /* poll interval */
1836 /* EVENT_WRITE_EOP - flush caches, send int */
1837 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1838 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1839 amdgpu_ring_write(ring, addr & 0xfffffffc);
1840 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1841 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) |
1842 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT));
1843 amdgpu_ring_write(ring, lower_32_bits(seq));
1844 amdgpu_ring_write(ring, upper_32_bits(seq));
1845}
1846
1847static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1848 struct amdgpu_ib *ib,
1849 unsigned vmid, bool ctx_switch)
1850{
1851 u32 header, control = 0;
1852
1853 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
1854 if (ctx_switch) {
1855 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1856 amdgpu_ring_write(ring, 0);
1857 }
1858
1859 if (ib->flags & AMDGPU_IB_FLAG_CE)
1860 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1861 else
1862 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1863
1864 control |= ib->length_dw | (vmid << 24);
1865
1866 amdgpu_ring_write(ring, header);
1867 amdgpu_ring_write(ring,
1868#ifdef __BIG_ENDIAN
1869 (2 << 0) |
1870#endif
1871 (ib->gpu_addr & 0xFFFFFFFC));
1872 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1873 amdgpu_ring_write(ring, control);
1874}
1875
1876/**
1877 * gfx_v6_0_ring_test_ib - basic ring IB test
1878 *
1879 * @ring: amdgpu_ring structure holding ring information
1880 *
1881 * Allocate an IB and execute it on the gfx ring (SI).
1882 * Provides a basic gfx ring test to verify that IBs are working.
1883 * Returns 0 on success, error on failure.
1884 */
1885static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1886{
1887 struct amdgpu_device *adev = ring->adev;
1888 struct amdgpu_ib ib;
1889 struct dma_fence *f = NULL;
1890 uint32_t scratch;
1891 uint32_t tmp = 0;
1892 long r;
1893
1894 r = amdgpu_gfx_scratch_get(adev, &scratch);
1895 if (r) {
1896 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
1897 return r;
1898 }
1899 WREG32(scratch, 0xCAFEDEAD);
1900 memset(&ib, 0, sizeof(ib));
1901 r = amdgpu_ib_get(adev, NULL, 256, &ib);
1902 if (r) {
1903 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1904 goto err1;
1905 }
1906 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1907 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START));
1908 ib.ptr[2] = 0xDEADBEEF;
1909 ib.length_dw = 3;
1910
1911 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1912 if (r)
1913 goto err2;
1914
1915 r = dma_fence_wait_timeout(f, false, timeout);
1916 if (r == 0) {
1917 DRM_ERROR("amdgpu: IB test timed out\n");
1918 r = -ETIMEDOUT;
1919 goto err2;
1920 } else if (r < 0) {
1921 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1922 goto err2;
1923 }
1924 tmp = RREG32(scratch);
1925 if (tmp == 0xDEADBEEF) {
1926 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
1927 r = 0;
1928 } else {
1929 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
1930 scratch, tmp);
1931 r = -EINVAL;
1932 }
1933
1934err2:
1935 amdgpu_ib_free(adev, &ib, NULL);
1936 dma_fence_put(f);
1937err1:
1938 amdgpu_gfx_scratch_free(adev, scratch);
1939 return r;
1940}
1941
1942static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1943{
1944 int i;
1945 if (enable) {
1946 WREG32(mmCP_ME_CNTL, 0);
1947 } else {
1948 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK |
1949 CP_ME_CNTL__PFP_HALT_MASK |
1950 CP_ME_CNTL__CE_HALT_MASK));
1951 WREG32(mmSCRATCH_UMSK, 0);
1952 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1953 adev->gfx.gfx_ring[i].ready = false;
1954 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1955 adev->gfx.compute_ring[i].ready = false;
1956 }
1957 udelay(50);
1958}
1959
1960static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1961{
1962 unsigned i;
1963 const struct gfx_firmware_header_v1_0 *pfp_hdr;
1964 const struct gfx_firmware_header_v1_0 *ce_hdr;
1965 const struct gfx_firmware_header_v1_0 *me_hdr;
1966 const __le32 *fw_data;
1967 u32 fw_size;
1968
1969 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1970 return -EINVAL;
1971
1972 gfx_v6_0_cp_gfx_enable(adev, false);
1973 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1974 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1975 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1976
1977 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1978 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1979 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1980
1981 /* PFP */
1982 fw_data = (const __le32 *)
1983 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1984 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
1985 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1986 for (i = 0; i < fw_size; i++)
1987 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
1988 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1989
1990 /* CE */
1991 fw_data = (const __le32 *)
1992 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1993 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
1994 WREG32(mmCP_CE_UCODE_ADDR, 0);
1995 for (i = 0; i < fw_size; i++)
1996 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
1997 WREG32(mmCP_CE_UCODE_ADDR, 0);
1998
1999 /* ME */
2000 fw_data = (const __be32 *)
2001 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2002 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2003 WREG32(mmCP_ME_RAM_WADDR, 0);
2004 for (i = 0; i < fw_size; i++)
2005 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2006 WREG32(mmCP_ME_RAM_WADDR, 0);
2007
2008 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2009 WREG32(mmCP_CE_UCODE_ADDR, 0);
2010 WREG32(mmCP_ME_RAM_WADDR, 0);
2011 WREG32(mmCP_ME_RAM_RADDR, 0);
2012 return 0;
2013}
2014
2015static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev)
2016{
2017 const struct cs_section_def *sect = NULL;
2018 const struct cs_extent_def *ext = NULL;
2019 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2020 int r, i;
2021
2022 r = amdgpu_ring_alloc(ring, 7 + 4);
2023 if (r) {
2024 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2025 return r;
2026 }
2027 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2028 amdgpu_ring_write(ring, 0x1);
2029 amdgpu_ring_write(ring, 0x0);
2030 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1);
2031 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2032 amdgpu_ring_write(ring, 0);
2033 amdgpu_ring_write(ring, 0);
2034
2035 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2036 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2037 amdgpu_ring_write(ring, 0xc000);
2038 amdgpu_ring_write(ring, 0xe000);
2039 amdgpu_ring_commit(ring);
2040
2041 gfx_v6_0_cp_gfx_enable(adev, true);
2042
2043 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10);
2044 if (r) {
2045 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2046 return r;
2047 }
2048
2049 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2050 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2051
2052 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2053 for (ext = sect->section; ext->extent != NULL; ++ext) {
2054 if (sect->id == SECT_CONTEXT) {
2055 amdgpu_ring_write(ring,
2056 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2057 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2058 for (i = 0; i < ext->reg_count; i++)
2059 amdgpu_ring_write(ring, ext->extent[i]);
2060 }
2061 }
2062 }
2063
2064 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2065 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2066
2067 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2068 amdgpu_ring_write(ring, 0);
2069
2070 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2071 amdgpu_ring_write(ring, 0x00000316);
2072 amdgpu_ring_write(ring, 0x0000000e);
2073 amdgpu_ring_write(ring, 0x00000010);
2074
2075 amdgpu_ring_commit(ring);
2076
2077 return 0;
2078}
2079
2080static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
2081{
2082 struct amdgpu_ring *ring;
2083 u32 tmp;
2084 u32 rb_bufsz;
2085 int r;
2086 u64 rptr_addr;
2087
2088 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2089 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2090
2091 /* Set the write pointer delay */
2092 WREG32(mmCP_RB_WPTR_DELAY, 0);
2093
2094 WREG32(mmCP_DEBUG, 0);
2095 WREG32(mmSCRATCH_ADDR, 0);
2096
2097 /* ring 0 - compute and gfx */
2098 /* Set ring buffer size */
2099 ring = &adev->gfx.gfx_ring[0];
2100 rb_bufsz = order_base_2(ring->ring_size / 8);
2101 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2102
2103#ifdef __BIG_ENDIAN
2104 tmp |= BUF_SWAP_32BIT;
2105#endif
2106 WREG32(mmCP_RB0_CNTL, tmp);
2107
2108 /* Initialize the ring buffer's read and write pointers */
2109 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2110 ring->wptr = 0;
2111 WREG32(mmCP_RB0_WPTR, ring->wptr);
2112
2113 /* set the wb address whether it's enabled or not */
2114 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2115 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2116 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2117
2118 WREG32(mmSCRATCH_UMSK, 0);
2119
2120 mdelay(1);
2121 WREG32(mmCP_RB0_CNTL, tmp);
2122
2123 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8);
2124
2125 /* start the rings */
2126 gfx_v6_0_cp_gfx_start(adev);
2127 ring->ready = true;
2128 r = amdgpu_ring_test_ring(ring);
2129 if (r) {
2130 ring->ready = false;
2131 return r;
2132 }
2133
2134 return 0;
2135}
2136
2137static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
2138{
2139 return ring->adev->wb.wb[ring->rptr_offs];
2140}
2141
2142static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
2143{
2144 struct amdgpu_device *adev = ring->adev;
2145
2146 if (ring == &adev->gfx.gfx_ring[0])
2147 return RREG32(mmCP_RB0_WPTR);
2148 else if (ring == &adev->gfx.compute_ring[0])
2149 return RREG32(mmCP_RB1_WPTR);
2150 else if (ring == &adev->gfx.compute_ring[1])
2151 return RREG32(mmCP_RB2_WPTR);
2152 else
2153 BUG();
2154}
2155
2156static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2157{
2158 struct amdgpu_device *adev = ring->adev;
2159
2160 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2161 (void)RREG32(mmCP_RB0_WPTR);
2162}
2163
2164static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2165{
2166 struct amdgpu_device *adev = ring->adev;
2167
2168 if (ring == &adev->gfx.compute_ring[0]) {
2169 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2170 (void)RREG32(mmCP_RB1_WPTR);
2171 } else if (ring == &adev->gfx.compute_ring[1]) {
2172 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr));
2173 (void)RREG32(mmCP_RB2_WPTR);
2174 } else {
2175 BUG();
2176 }
2177
2178}
2179
2180static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
2181{
2182 struct amdgpu_ring *ring;
2183 u32 tmp;
2184 u32 rb_bufsz;
2185 int i, r;
2186 u64 rptr_addr;
2187
2188 /* ring1 - compute only */
2189 /* Set ring buffer size */
2190
2191 ring = &adev->gfx.compute_ring[0];
2192 rb_bufsz = order_base_2(ring->ring_size / 8);
2193 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2194#ifdef __BIG_ENDIAN
2195 tmp |= BUF_SWAP_32BIT;
2196#endif
2197 WREG32(mmCP_RB1_CNTL, tmp);
2198
2199 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK);
2200 ring->wptr = 0;
2201 WREG32(mmCP_RB1_WPTR, ring->wptr);
2202
2203 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2204 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2205 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2206
2207 mdelay(1);
2208 WREG32(mmCP_RB1_CNTL, tmp);
2209 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8);
2210
2211 ring = &adev->gfx.compute_ring[1];
2212 rb_bufsz = order_base_2(ring->ring_size / 8);
2213 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2214#ifdef __BIG_ENDIAN
2215 tmp |= BUF_SWAP_32BIT;
2216#endif
2217 WREG32(mmCP_RB2_CNTL, tmp);
2218
2219 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK);
2220 ring->wptr = 0;
2221 WREG32(mmCP_RB2_WPTR, ring->wptr);
2222 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2223 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
2224 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2225
2226 mdelay(1);
2227 WREG32(mmCP_RB2_CNTL, tmp);
2228 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8);
2229
2230 adev->gfx.compute_ring[0].ready = false;
2231 adev->gfx.compute_ring[1].ready = false;
2232
2233 for (i = 0; i < 2; i++) {
2234 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[i]);
2235 if (r)
2236 return r;
2237 adev->gfx.compute_ring[i].ready = true;
2238 }
2239
2240 return 0;
2241}
2242
2243static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
2244{
2245 gfx_v6_0_cp_gfx_enable(adev, enable);
2246}
2247
2248static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
2249{
2250 return gfx_v6_0_cp_gfx_load_microcode(adev);
2251}
2252
2253static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2254 bool enable)
2255{
2256 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2257 u32 mask;
2258 int i;
2259
2260 if (enable)
2261 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2262 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2263 else
2264 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2265 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2266 WREG32(mmCP_INT_CNTL_RING0, tmp);
2267
2268 if (!enable) {
2269 /* read a gfx register */
2270 tmp = RREG32(mmDB_DEPTH_INFO);
2271
2272 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
2273 for (i = 0; i < adev->usec_timeout; i++) {
2274 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
2275 break;
2276 udelay(1);
2277 }
2278 }
2279}
2280
2281static int gfx_v6_0_cp_resume(struct amdgpu_device *adev)
2282{
2283 int r;
2284
2285 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2286
2287 r = gfx_v6_0_cp_load_microcode(adev);
2288 if (r)
2289 return r;
2290
2291 r = gfx_v6_0_cp_gfx_resume(adev);
2292 if (r)
2293 return r;
2294 r = gfx_v6_0_cp_compute_resume(adev);
2295 if (r)
2296 return r;
2297
2298 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2299
2300 return 0;
2301}
2302
2303static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2304{
2305 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2306 uint32_t seq = ring->fence_drv.sync_seq;
2307 uint64_t addr = ring->fence_drv.gpu_addr;
2308
2309 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2310 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
2311 WAIT_REG_MEM_FUNCTION(3) | /* equal */
2312 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
2313 amdgpu_ring_write(ring, addr & 0xfffffffc);
2314 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
2315 amdgpu_ring_write(ring, seq);
2316 amdgpu_ring_write(ring, 0xffffffff);
2317 amdgpu_ring_write(ring, 4); /* poll interval */
2318
2319 if (usepfp) {
2320 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2321 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2322 amdgpu_ring_write(ring, 0);
2323 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2324 amdgpu_ring_write(ring, 0);
2325 }
2326}
2327
2328static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2329 unsigned vmid, uint64_t pd_addr)
2330{
2331 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2332
2333 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
2334
2335 /* wait for the invalidate to complete */
2336 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2337 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
2338 WAIT_REG_MEM_ENGINE(0))); /* me */
2339 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
2340 amdgpu_ring_write(ring, 0);
2341 amdgpu_ring_write(ring, 0); /* ref */
2342 amdgpu_ring_write(ring, 0); /* mask */
2343 amdgpu_ring_write(ring, 0x20); /* poll interval */
2344
2345 if (usepfp) {
2346 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2347 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2348 amdgpu_ring_write(ring, 0x0);
2349
2350 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2351 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2352 amdgpu_ring_write(ring, 0);
2353 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2354 amdgpu_ring_write(ring, 0);
2355 }
2356}
2357
2358static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
2359 uint32_t reg, uint32_t val)
2360{
2361 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2362
2363 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2364 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
2365 WRITE_DATA_DST_SEL(0)));
2366 amdgpu_ring_write(ring, reg);
2367 amdgpu_ring_write(ring, 0);
2368 amdgpu_ring_write(ring, val);
2369}
2370
2371static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev)
2372{
2373 amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, NULL, NULL);
2374 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL);
2375 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL);
2376}
2377
2378static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2379{
2380 const u32 *src_ptr;
2381 volatile u32 *dst_ptr;
2382 u32 dws, i;
2383 u64 reg_list_mc_addr;
2384 const struct cs_section_def *cs_data;
2385 int r;
2386
2387 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list;
2388 adev->gfx.rlc.reg_list_size =
2389 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
2390
2391 adev->gfx.rlc.cs_data = si_cs_data;
2392 src_ptr = adev->gfx.rlc.reg_list;
2393 dws = adev->gfx.rlc.reg_list_size;
2394 cs_data = adev->gfx.rlc.cs_data;
2395
2396 if (src_ptr) {
2397 /* save restore block */
2398 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
2399 AMDGPU_GEM_DOMAIN_VRAM,
2400 &adev->gfx.rlc.save_restore_obj,
2401 &adev->gfx.rlc.save_restore_gpu_addr,
2402 (void **)&adev->gfx.rlc.sr_ptr);
2403 if (r) {
2404 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n",
2405 r);
2406 gfx_v6_0_rlc_fini(adev);
2407 return r;
2408 }
2409
2410 /* write the sr buffer */
2411 dst_ptr = adev->gfx.rlc.sr_ptr;
2412 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
2413 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
2414
2415 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
2416 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2417 }
2418
2419 if (cs_data) {
2420 /* clear state block */
2421 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev);
2422 dws = adev->gfx.rlc.clear_state_size + (256 / 4);
2423
2424 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
2425 AMDGPU_GEM_DOMAIN_VRAM,
2426 &adev->gfx.rlc.clear_state_obj,
2427 &adev->gfx.rlc.clear_state_gpu_addr,
2428 (void **)&adev->gfx.rlc.cs_ptr);
2429 if (r) {
2430 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
2431 gfx_v6_0_rlc_fini(adev);
2432 return r;
2433 }
2434
2435 /* set up the cs buffer */
2436 dst_ptr = adev->gfx.rlc.cs_ptr;
2437 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256;
2438 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));
2439 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
2440 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size);
2441 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]);
2442 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
2443 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2444 }
2445
2446 return 0;
2447}
2448
2449static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
2450{
2451 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
2452
2453 if (!enable) {
2454 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2455 WREG32(mmSPI_LB_CU_MASK, 0x00ff);
2456 }
2457}
2458
2459static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2460{
2461 int i;
2462
2463 for (i = 0; i < adev->usec_timeout; i++) {
2464 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0)
2465 break;
2466 udelay(1);
2467 }
2468
2469 for (i = 0; i < adev->usec_timeout; i++) {
2470 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0)
2471 break;
2472 udelay(1);
2473 }
2474}
2475
2476static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
2477{
2478 u32 tmp;
2479
2480 tmp = RREG32(mmRLC_CNTL);
2481 if (tmp != rlc)
2482 WREG32(mmRLC_CNTL, rlc);
2483}
2484
2485static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2486{
2487 u32 data, orig;
2488
2489 orig = data = RREG32(mmRLC_CNTL);
2490
2491 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2492 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
2493 WREG32(mmRLC_CNTL, data);
2494
2495 gfx_v6_0_wait_for_rlc_serdes(adev);
2496 }
2497
2498 return orig;
2499}
2500
2501static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2502{
2503 WREG32(mmRLC_CNTL, 0);
2504
2505 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2506 gfx_v6_0_wait_for_rlc_serdes(adev);
2507}
2508
2509static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2510{
2511 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
2512
2513 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2514
2515 udelay(50);
2516}
2517
2518static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev)
2519{
2520 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2521 udelay(50);
2522 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2523 udelay(50);
2524}
2525
2526static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev)
2527{
2528 u32 tmp;
2529
2530 /* Enable LBPW only for DDR3 */
2531 tmp = RREG32(mmMC_SEQ_MISC0);
2532 if ((tmp & 0xF0000000) == 0xB0000000)
2533 return true;
2534 return false;
2535}
2536
2537static void gfx_v6_0_init_cg(struct amdgpu_device *adev)
2538{
2539}
2540
2541static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2542{
2543 u32 i;
2544 const struct rlc_firmware_header_v1_0 *hdr;
2545 const __le32 *fw_data;
2546 u32 fw_size;
2547
2548
2549 if (!adev->gfx.rlc_fw)
2550 return -EINVAL;
2551
2552 gfx_v6_0_rlc_stop(adev);
2553 gfx_v6_0_rlc_reset(adev);
2554 gfx_v6_0_init_pg(adev);
2555 gfx_v6_0_init_cg(adev);
2556
2557 WREG32(mmRLC_RL_BASE, 0);
2558 WREG32(mmRLC_RL_SIZE, 0);
2559 WREG32(mmRLC_LB_CNTL, 0);
2560 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff);
2561 WREG32(mmRLC_LB_CNTR_INIT, 0);
2562 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
2563
2564 WREG32(mmRLC_MC_CNTL, 0);
2565 WREG32(mmRLC_UCODE_CNTL, 0);
2566
2567 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
2568 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2569 fw_data = (const __le32 *)
2570 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2571
2572 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2573
2574 for (i = 0; i < fw_size; i++) {
2575 WREG32(mmRLC_UCODE_ADDR, i);
2576 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++));
2577 }
2578 WREG32(mmRLC_UCODE_ADDR, 0);
2579
2580 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
2581 gfx_v6_0_rlc_start(adev);
2582
2583 return 0;
2584}
2585
2586static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
2587{
2588 u32 data, orig, tmp;
2589
2590 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
2591
2592 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2593 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2594
2595 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080);
2596
2597 tmp = gfx_v6_0_halt_rlc(adev);
2598
2599 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2600 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2601 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff);
2602
2603 gfx_v6_0_wait_for_rlc_serdes(adev);
2604 gfx_v6_0_update_rlc(adev, tmp);
2605
2606 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff);
2607
2608 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2609 } else {
2610 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2611
2612 RREG32(mmCB_CGTT_SCLK_CTRL);
2613 RREG32(mmCB_CGTT_SCLK_CTRL);
2614 RREG32(mmCB_CGTT_SCLK_CTRL);
2615 RREG32(mmCB_CGTT_SCLK_CTRL);
2616
2617 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2618 }
2619
2620 if (orig != data)
2621 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
2622
2623}
2624
2625static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
2626{
2627
2628 u32 data, orig, tmp = 0;
2629
2630 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2631 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2632 data = 0x96940200;
2633 if (orig != data)
2634 WREG32(mmCGTS_SM_CTRL_REG, data);
2635
2636 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2637 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
2638 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2639 if (orig != data)
2640 WREG32(mmCP_MEM_SLP_CNTL, data);
2641 }
2642
2643 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2644 data &= 0xffffffc0;
2645 if (orig != data)
2646 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2647
2648 tmp = gfx_v6_0_halt_rlc(adev);
2649
2650 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2651 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2652 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff);
2653
2654 gfx_v6_0_update_rlc(adev, tmp);
2655 } else {
2656 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2657 data |= 0x00000003;
2658 if (orig != data)
2659 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2660
2661 data = RREG32(mmCP_MEM_SLP_CNTL);
2662 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2663 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2664 WREG32(mmCP_MEM_SLP_CNTL, data);
2665 }
2666 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2667 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK;
2668 if (orig != data)
2669 WREG32(mmCGTS_SM_CTRL_REG, data);
2670
2671 tmp = gfx_v6_0_halt_rlc(adev);
2672
2673 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2674 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2675 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff);
2676
2677 gfx_v6_0_update_rlc(adev, tmp);
2678 }
2679}
2680/*
2681static void gfx_v6_0_update_cg(struct amdgpu_device *adev,
2682 bool enable)
2683{
2684 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2685 if (enable) {
2686 gfx_v6_0_enable_mgcg(adev, true);
2687 gfx_v6_0_enable_cgcg(adev, true);
2688 } else {
2689 gfx_v6_0_enable_cgcg(adev, false);
2690 gfx_v6_0_enable_mgcg(adev, false);
2691 }
2692 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2693}
2694*/
2695
2696static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
2697 bool enable)
2698{
2699}
2700
2701static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
2702 bool enable)
2703{
2704}
2705
2706static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
2707{
2708 u32 data, orig;
2709
2710 orig = data = RREG32(mmRLC_PG_CNTL);
2711 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
2712 data &= ~0x8000;
2713 else
2714 data |= 0x8000;
2715 if (orig != data)
2716 WREG32(mmRLC_PG_CNTL, data);
2717}
2718
2719static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
2720{
2721}
2722/*
2723static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev)
2724{
2725 const __le32 *fw_data;
2726 volatile u32 *dst_ptr;
2727 int me, i, max_me = 4;
2728 u32 bo_offset = 0;
2729 u32 table_offset, table_size;
2730
2731 if (adev->asic_type == CHIP_KAVERI)
2732 max_me = 5;
2733
2734 if (adev->gfx.rlc.cp_table_ptr == NULL)
2735 return;
2736
2737 dst_ptr = adev->gfx.rlc.cp_table_ptr;
2738 for (me = 0; me < max_me; me++) {
2739 if (me == 0) {
2740 const struct gfx_firmware_header_v1_0 *hdr =
2741 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2742 fw_data = (const __le32 *)
2743 (adev->gfx.ce_fw->data +
2744 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2745 table_offset = le32_to_cpu(hdr->jt_offset);
2746 table_size = le32_to_cpu(hdr->jt_size);
2747 } else if (me == 1) {
2748 const struct gfx_firmware_header_v1_0 *hdr =
2749 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2750 fw_data = (const __le32 *)
2751 (adev->gfx.pfp_fw->data +
2752 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2753 table_offset = le32_to_cpu(hdr->jt_offset);
2754 table_size = le32_to_cpu(hdr->jt_size);
2755 } else if (me == 2) {
2756 const struct gfx_firmware_header_v1_0 *hdr =
2757 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2758 fw_data = (const __le32 *)
2759 (adev->gfx.me_fw->data +
2760 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2761 table_offset = le32_to_cpu(hdr->jt_offset);
2762 table_size = le32_to_cpu(hdr->jt_size);
2763 } else if (me == 3) {
2764 const struct gfx_firmware_header_v1_0 *hdr =
2765 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2766 fw_data = (const __le32 *)
2767 (adev->gfx.mec_fw->data +
2768 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2769 table_offset = le32_to_cpu(hdr->jt_offset);
2770 table_size = le32_to_cpu(hdr->jt_size);
2771 } else {
2772 const struct gfx_firmware_header_v1_0 *hdr =
2773 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2774 fw_data = (const __le32 *)
2775 (adev->gfx.mec2_fw->data +
2776 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2777 table_offset = le32_to_cpu(hdr->jt_offset);
2778 table_size = le32_to_cpu(hdr->jt_size);
2779 }
2780
2781 for (i = 0; i < table_size; i ++) {
2782 dst_ptr[bo_offset + i] =
2783 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
2784 }
2785
2786 bo_offset += table_size;
2787 }
2788}
2789*/
2790static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev,
2791 bool enable)
2792{
2793 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2794 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10));
2795 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1);
2796 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1);
2797 } else {
2798 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0);
2799 (void)RREG32(mmDB_RENDER_CONTROL);
2800 }
2801}
2802
2803static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev)
2804{
2805 u32 tmp;
2806
2807 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
2808
2809 tmp = RREG32(mmRLC_MAX_PG_CU);
2810 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
2811 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
2812 WREG32(mmRLC_MAX_PG_CU, tmp);
2813}
2814
2815static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
2816 bool enable)
2817{
2818 u32 data, orig;
2819
2820 orig = data = RREG32(mmRLC_PG_CNTL);
2821 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
2822 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2823 else
2824 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2825 if (orig != data)
2826 WREG32(mmRLC_PG_CNTL, data);
2827}
2828
2829static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
2830 bool enable)
2831{
2832 u32 data, orig;
2833
2834 orig = data = RREG32(mmRLC_PG_CNTL);
2835 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
2836 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2837 else
2838 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2839 if (orig != data)
2840 WREG32(mmRLC_PG_CNTL, data);
2841}
2842
2843static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev)
2844{
2845 u32 tmp;
2846
2847 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2848 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1);
2849 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2850
2851 tmp = RREG32(mmRLC_AUTO_PG_CTRL);
2852 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2853 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2854 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK;
2855 WREG32(mmRLC_AUTO_PG_CTRL, tmp);
2856}
2857
2858static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
2859{
2860 gfx_v6_0_enable_gfx_cgpg(adev, enable);
2861 gfx_v6_0_enable_gfx_static_mgpg(adev, enable);
2862 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable);
2863}
2864
2865static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev)
2866{
2867 u32 count = 0;
2868 const struct cs_section_def *sect = NULL;
2869 const struct cs_extent_def *ext = NULL;
2870
2871 if (adev->gfx.rlc.cs_data == NULL)
2872 return 0;
2873
2874 /* begin clear state */
2875 count += 2;
2876 /* context control state */
2877 count += 3;
2878
2879 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2880 for (ext = sect->section; ext->extent != NULL; ++ext) {
2881 if (sect->id == SECT_CONTEXT)
2882 count += 2 + ext->reg_count;
2883 else
2884 return 0;
2885 }
2886 }
2887 /* pa_sc_raster_config */
2888 count += 3;
2889 /* end clear state */
2890 count += 2;
2891 /* clear state */
2892 count += 2;
2893
2894 return count;
2895}
2896
2897static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
2898 volatile u32 *buffer)
2899{
2900 u32 count = 0, i;
2901 const struct cs_section_def *sect = NULL;
2902 const struct cs_extent_def *ext = NULL;
2903
2904 if (adev->gfx.rlc.cs_data == NULL)
2905 return;
2906 if (buffer == NULL)
2907 return;
2908
2909 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2910 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2911 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2912 buffer[count++] = cpu_to_le32(0x80000000);
2913 buffer[count++] = cpu_to_le32(0x80000000);
2914
2915 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2916 for (ext = sect->section; ext->extent != NULL; ++ext) {
2917 if (sect->id == SECT_CONTEXT) {
2918 buffer[count++] =
2919 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2920 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
2921 for (i = 0; i < ext->reg_count; i++)
2922 buffer[count++] = cpu_to_le32(ext->extent[i]);
2923 } else {
2924 return;
2925 }
2926 }
2927 }
2928
2929 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2930 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2931 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);
2932
2933 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2934 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
2935
2936 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
2937 buffer[count++] = cpu_to_le32(0);
2938}
2939
2940static void gfx_v6_0_init_pg(struct amdgpu_device *adev)
2941{
2942 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2943 AMD_PG_SUPPORT_GFX_SMG |
2944 AMD_PG_SUPPORT_GFX_DMG |
2945 AMD_PG_SUPPORT_CP |
2946 AMD_PG_SUPPORT_GDS |
2947 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2948 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true);
2949 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true);
2950 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2951 gfx_v6_0_init_gfx_cgpg(adev);
2952 gfx_v6_0_enable_cp_pg(adev, true);
2953 gfx_v6_0_enable_gds_pg(adev, true);
2954 } else {
2955 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2956 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2957
2958 }
2959 gfx_v6_0_init_ao_cu_mask(adev);
2960 gfx_v6_0_update_gfx_pg(adev, true);
2961 } else {
2962
2963 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2964 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2965 }
2966}
2967
2968static void gfx_v6_0_fini_pg(struct amdgpu_device *adev)
2969{
2970 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2971 AMD_PG_SUPPORT_GFX_SMG |
2972 AMD_PG_SUPPORT_GFX_DMG |
2973 AMD_PG_SUPPORT_CP |
2974 AMD_PG_SUPPORT_GDS |
2975 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2976 gfx_v6_0_update_gfx_pg(adev, false);
2977 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2978 gfx_v6_0_enable_cp_pg(adev, false);
2979 gfx_v6_0_enable_gds_pg(adev, false);
2980 }
2981 }
2982}
2983
2984static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2985{
2986 uint64_t clock;
2987
2988 mutex_lock(&adev->gfx.gpu_clock_mutex);
2989 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
2990 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
2991 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
2992 mutex_unlock(&adev->gfx.gpu_clock_mutex);
2993 return clock;
2994}
2995
2996static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2997{
2998 if (flags & AMDGPU_HAVE_CTX_SWITCH)
2999 gfx_v6_0_ring_emit_vgt_flush(ring);
3000 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3001 amdgpu_ring_write(ring, 0x80000000);
3002 amdgpu_ring_write(ring, 0);
3003}
3004
3005
3006static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
3007{
3008 WREG32(mmSQ_IND_INDEX,
3009 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
3010 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
3011 (address << SQ_IND_INDEX__INDEX__SHIFT) |
3012 (SQ_IND_INDEX__FORCE_READ_MASK));
3013 return RREG32(mmSQ_IND_DATA);
3014}
3015
3016static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
3017 uint32_t wave, uint32_t thread,
3018 uint32_t regno, uint32_t num, uint32_t *out)
3019{
3020 WREG32(mmSQ_IND_INDEX,
3021 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
3022 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
3023 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
3024 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
3025 (SQ_IND_INDEX__FORCE_READ_MASK) |
3026 (SQ_IND_INDEX__AUTO_INCR_MASK));
3027 while (num--)
3028 *(out++) = RREG32(mmSQ_IND_DATA);
3029}
3030
3031static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
3032{
3033 /* type 0 wave data */
3034 dst[(*no_fields)++] = 0;
3035 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
3036 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
3037 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
3038 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
3039 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
3040 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
3041 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
3042 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
3043 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
3044 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
3045 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
3046 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
3047 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
3048 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
3049 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
3050 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
3051 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
3052 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
3053}
3054
3055static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
3056 uint32_t wave, uint32_t start,
3057 uint32_t size, uint32_t *dst)
3058{
3059 wave_read_regs(
3060 adev, simd, wave, 0,
3061 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
3062}
3063
3064static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev,
3065 u32 me, u32 pipe, u32 q)
3066{
3067 DRM_INFO("Not implemented\n");
3068}
3069
3070static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
3071 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
3072 .select_se_sh = &gfx_v6_0_select_se_sh,
3073 .read_wave_data = &gfx_v6_0_read_wave_data,
3074 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs,
3075 .select_me_pipe_q = &gfx_v6_0_select_me_pipe_q
3076};
3077
3078static int gfx_v6_0_early_init(void *handle)
3079{
3080 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3081
3082 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
3083 adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS;
3084 adev->gfx.funcs = &gfx_v6_0_gfx_funcs;
3085 gfx_v6_0_set_ring_funcs(adev);
3086 gfx_v6_0_set_irq_funcs(adev);
3087
3088 return 0;
3089}
3090
3091static int gfx_v6_0_sw_init(void *handle)
3092{
3093 struct amdgpu_ring *ring;
3094 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3095 int i, r;
3096
3097 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
3098 if (r)
3099 return r;
3100
3101 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq);
3102 if (r)
3103 return r;
3104
3105 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq);
3106 if (r)
3107 return r;
3108
3109 gfx_v6_0_scratch_init(adev);
3110
3111 r = gfx_v6_0_init_microcode(adev);
3112 if (r) {
3113 DRM_ERROR("Failed to load gfx firmware!\n");
3114 return r;
3115 }
3116
3117 r = gfx_v6_0_rlc_init(adev);
3118 if (r) {
3119 DRM_ERROR("Failed to init rlc BOs!\n");
3120 return r;
3121 }
3122
3123 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3124 ring = &adev->gfx.gfx_ring[i];
3125 ring->ring_obj = NULL;
3126 sprintf(ring->name, "gfx");
3127 r = amdgpu_ring_init(adev, ring, 1024,
3128 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
3129 if (r)
3130 return r;
3131 }
3132
3133 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3134 unsigned irq_type;
3135
3136 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
3137 DRM_ERROR("Too many (%d) compute rings!\n", i);
3138 break;
3139 }
3140 ring = &adev->gfx.compute_ring[i];
3141 ring->ring_obj = NULL;
3142 ring->use_doorbell = false;
3143 ring->doorbell_index = 0;
3144 ring->me = 1;
3145 ring->pipe = i;
3146 ring->queue = i;
3147 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
3148 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
3149 r = amdgpu_ring_init(adev, ring, 1024,
3150 &adev->gfx.eop_irq, irq_type);
3151 if (r)
3152 return r;
3153 }
3154
3155 return r;
3156}
3157
3158static int gfx_v6_0_sw_fini(void *handle)
3159{
3160 int i;
3161 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3162
3163 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3164 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
3165 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3166 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
3167
3168 gfx_v6_0_rlc_fini(adev);
3169
3170 return 0;
3171}
3172
3173static int gfx_v6_0_hw_init(void *handle)
3174{
3175 int r;
3176 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3177
3178 gfx_v6_0_gpu_init(adev);
3179
3180 r = gfx_v6_0_rlc_resume(adev);
3181 if (r)
3182 return r;
3183
3184 r = gfx_v6_0_cp_resume(adev);
3185 if (r)
3186 return r;
3187
3188 adev->gfx.ce_ram_size = 0x8000;
3189
3190 return r;
3191}
3192
3193static int gfx_v6_0_hw_fini(void *handle)
3194{
3195 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3196
3197 gfx_v6_0_cp_enable(adev, false);
3198 gfx_v6_0_rlc_stop(adev);
3199 gfx_v6_0_fini_pg(adev);
3200
3201 return 0;
3202}
3203
3204static int gfx_v6_0_suspend(void *handle)
3205{
3206 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3207
3208 return gfx_v6_0_hw_fini(adev);
3209}
3210
3211static int gfx_v6_0_resume(void *handle)
3212{
3213 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3214
3215 return gfx_v6_0_hw_init(adev);
3216}
3217
3218static bool gfx_v6_0_is_idle(void *handle)
3219{
3220 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3221
3222 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
3223 return false;
3224 else
3225 return true;
3226}
3227
3228static int gfx_v6_0_wait_for_idle(void *handle)
3229{
3230 unsigned i;
3231 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3232
3233 for (i = 0; i < adev->usec_timeout; i++) {
3234 if (gfx_v6_0_is_idle(handle))
3235 return 0;
3236 udelay(1);
3237 }
3238 return -ETIMEDOUT;
3239}
3240
3241static int gfx_v6_0_soft_reset(void *handle)
3242{
3243 return 0;
3244}
3245
3246static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3247 enum amdgpu_interrupt_state state)
3248{
3249 u32 cp_int_cntl;
3250
3251 switch (state) {
3252 case AMDGPU_IRQ_STATE_DISABLE:
3253 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3254 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3255 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3256 break;
3257 case AMDGPU_IRQ_STATE_ENABLE:
3258 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3259 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3260 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3261 break;
3262 default:
3263 break;
3264 }
3265}
3266
3267static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3268 int ring,
3269 enum amdgpu_interrupt_state state)
3270{
3271 u32 cp_int_cntl;
3272 switch (state){
3273 case AMDGPU_IRQ_STATE_DISABLE:
3274 if (ring == 0) {
3275 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3276 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3277 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3278 break;
3279 } else {
3280 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3281 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3282 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3283 break;
3284
3285 }
3286 case AMDGPU_IRQ_STATE_ENABLE:
3287 if (ring == 0) {
3288 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3289 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3290 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3291 break;
3292 } else {
3293 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3294 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3295 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3296 break;
3297
3298 }
3299
3300 default:
3301 BUG();
3302 break;
3303
3304 }
3305}
3306
3307static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3308 struct amdgpu_irq_src *src,
3309 unsigned type,
3310 enum amdgpu_interrupt_state state)
3311{
3312 u32 cp_int_cntl;
3313
3314 switch (state) {
3315 case AMDGPU_IRQ_STATE_DISABLE:
3316 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3317 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3318 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3319 break;
3320 case AMDGPU_IRQ_STATE_ENABLE:
3321 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3322 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3323 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3324 break;
3325 default:
3326 break;
3327 }
3328
3329 return 0;
3330}
3331
3332static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3333 struct amdgpu_irq_src *src,
3334 unsigned type,
3335 enum amdgpu_interrupt_state state)
3336{
3337 u32 cp_int_cntl;
3338
3339 switch (state) {
3340 case AMDGPU_IRQ_STATE_DISABLE:
3341 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3342 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3343 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3344 break;
3345 case AMDGPU_IRQ_STATE_ENABLE:
3346 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3347 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3348 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3349 break;
3350 default:
3351 break;
3352 }
3353
3354 return 0;
3355}
3356
3357static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3358 struct amdgpu_irq_src *src,
3359 unsigned type,
3360 enum amdgpu_interrupt_state state)
3361{
3362 switch (type) {
3363 case AMDGPU_CP_IRQ_GFX_EOP:
3364 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state);
3365 break;
3366 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3367 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state);
3368 break;
3369 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3370 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state);
3371 break;
3372 default:
3373 break;
3374 }
3375 return 0;
3376}
3377
3378static int gfx_v6_0_eop_irq(struct amdgpu_device *adev,
3379 struct amdgpu_irq_src *source,
3380 struct amdgpu_iv_entry *entry)
3381{
3382 switch (entry->ring_id) {
3383 case 0:
3384 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3385 break;
3386 case 1:
3387 case 2:
3388 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]);
3389 break;
3390 default:
3391 break;
3392 }
3393 return 0;
3394}
3395
3396static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev,
3397 struct amdgpu_irq_src *source,
3398 struct amdgpu_iv_entry *entry)
3399{
3400 DRM_ERROR("Illegal register access in command stream\n");
3401 schedule_work(&adev->reset_work);
3402 return 0;
3403}
3404
3405static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev,
3406 struct amdgpu_irq_src *source,
3407 struct amdgpu_iv_entry *entry)
3408{
3409 DRM_ERROR("Illegal instruction in command stream\n");
3410 schedule_work(&adev->reset_work);
3411 return 0;
3412}
3413
3414static int gfx_v6_0_set_clockgating_state(void *handle,
3415 enum amd_clockgating_state state)
3416{
3417 bool gate = false;
3418 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3419
3420 if (state == AMD_CG_STATE_GATE)
3421 gate = true;
3422
3423 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
3424 if (gate) {
3425 gfx_v6_0_enable_mgcg(adev, true);
3426 gfx_v6_0_enable_cgcg(adev, true);
3427 } else {
3428 gfx_v6_0_enable_cgcg(adev, false);
3429 gfx_v6_0_enable_mgcg(adev, false);
3430 }
3431 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
3432
3433 return 0;
3434}
3435
3436static int gfx_v6_0_set_powergating_state(void *handle,
3437 enum amd_powergating_state state)
3438{
3439 bool gate = false;
3440 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3441
3442 if (state == AMD_PG_STATE_GATE)
3443 gate = true;
3444
3445 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3446 AMD_PG_SUPPORT_GFX_SMG |
3447 AMD_PG_SUPPORT_GFX_DMG |
3448 AMD_PG_SUPPORT_CP |
3449 AMD_PG_SUPPORT_GDS |
3450 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3451 gfx_v6_0_update_gfx_pg(adev, gate);
3452 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3453 gfx_v6_0_enable_cp_pg(adev, gate);
3454 gfx_v6_0_enable_gds_pg(adev, gate);
3455 }
3456 }
3457
3458 return 0;
3459}
3460
3461static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
3462 .name = "gfx_v6_0",
3463 .early_init = gfx_v6_0_early_init,
3464 .late_init = NULL,
3465 .sw_init = gfx_v6_0_sw_init,
3466 .sw_fini = gfx_v6_0_sw_fini,
3467 .hw_init = gfx_v6_0_hw_init,
3468 .hw_fini = gfx_v6_0_hw_fini,
3469 .suspend = gfx_v6_0_suspend,
3470 .resume = gfx_v6_0_resume,
3471 .is_idle = gfx_v6_0_is_idle,
3472 .wait_for_idle = gfx_v6_0_wait_for_idle,
3473 .soft_reset = gfx_v6_0_soft_reset,
3474 .set_clockgating_state = gfx_v6_0_set_clockgating_state,
3475 .set_powergating_state = gfx_v6_0_set_powergating_state,
3476};
3477
3478static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
3479 .type = AMDGPU_RING_TYPE_GFX,
3480 .align_mask = 0xff,
3481 .nop = 0x80000000,
3482 .support_64bit_ptrs = false,
3483 .get_rptr = gfx_v6_0_ring_get_rptr,
3484 .get_wptr = gfx_v6_0_ring_get_wptr,
3485 .set_wptr = gfx_v6_0_ring_set_wptr_gfx,
3486 .emit_frame_size =
3487 5 + 5 + /* hdp flush / invalidate */
3488 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3489 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
3490 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
3491 3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */
3492 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3493 .emit_ib = gfx_v6_0_ring_emit_ib,
3494 .emit_fence = gfx_v6_0_ring_emit_fence,
3495 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3496 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3497 .test_ring = gfx_v6_0_ring_test_ring,
3498 .test_ib = gfx_v6_0_ring_test_ib,
3499 .insert_nop = amdgpu_ring_insert_nop,
3500 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
3501 .emit_wreg = gfx_v6_0_ring_emit_wreg,
3502};
3503
3504static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
3505 .type = AMDGPU_RING_TYPE_COMPUTE,
3506 .align_mask = 0xff,
3507 .nop = 0x80000000,
3508 .get_rptr = gfx_v6_0_ring_get_rptr,
3509 .get_wptr = gfx_v6_0_ring_get_wptr,
3510 .set_wptr = gfx_v6_0_ring_set_wptr_compute,
3511 .emit_frame_size =
3512 5 + 5 + /* hdp flush / invalidate */
3513 7 + /* gfx_v6_0_ring_emit_pipeline_sync */
3514 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */
3515 14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3516 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3517 .emit_ib = gfx_v6_0_ring_emit_ib,
3518 .emit_fence = gfx_v6_0_ring_emit_fence,
3519 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3520 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3521 .test_ring = gfx_v6_0_ring_test_ring,
3522 .test_ib = gfx_v6_0_ring_test_ib,
3523 .insert_nop = amdgpu_ring_insert_nop,
3524 .emit_wreg = gfx_v6_0_ring_emit_wreg,
3525};
3526
3527static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)
3528{
3529 int i;
3530
3531 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3532 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx;
3533 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3534 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute;
3535}
3536
3537static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = {
3538 .set = gfx_v6_0_set_eop_interrupt_state,
3539 .process = gfx_v6_0_eop_irq,
3540};
3541
3542static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = {
3543 .set = gfx_v6_0_set_priv_reg_fault_state,
3544 .process = gfx_v6_0_priv_reg_irq,
3545};
3546
3547static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = {
3548 .set = gfx_v6_0_set_priv_inst_fault_state,
3549 .process = gfx_v6_0_priv_inst_irq,
3550};
3551
3552static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3553{
3554 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3555 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs;
3556
3557 adev->gfx.priv_reg_irq.num_types = 1;
3558 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs;
3559
3560 adev->gfx.priv_inst_irq.num_types = 1;
3561 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs;
3562}
3563
3564static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
3565{
3566 int i, j, k, counter, active_cu_number = 0;
3567 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3568 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
3569 unsigned disable_masks[4 * 2];
3570 u32 ao_cu_num;
3571
3572 if (adev->flags & AMD_IS_APU)
3573 ao_cu_num = 2;
3574 else
3575 ao_cu_num = adev->gfx.config.max_cu_per_sh;
3576
3577 memset(cu_info, 0, sizeof(*cu_info));
3578
3579 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
3580
3581 mutex_lock(&adev->grbm_idx_mutex);
3582 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3583 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3584 mask = 1;
3585 ao_bitmap = 0;
3586 counter = 0;
3587 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
3588 if (i < 4 && j < 2)
3589 gfx_v6_0_set_user_cu_inactive_bitmap(
3590 adev, disable_masks[i * 2 + j]);
3591 bitmap = gfx_v6_0_get_cu_enabled(adev);
3592 cu_info->bitmap[i][j] = bitmap;
3593
3594 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
3595 if (bitmap & mask) {
3596 if (counter < ao_cu_num)
3597 ao_bitmap |= mask;
3598 counter ++;
3599 }
3600 mask <<= 1;
3601 }
3602 active_cu_number += counter;
3603 if (i < 2 && j < 2)
3604 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3605 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
3606 }
3607 }
3608
3609 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3610 mutex_unlock(&adev->grbm_idx_mutex);
3611
3612 cu_info->number = active_cu_number;
3613 cu_info->ao_cu_mask = ao_cu_mask;
3614}
3615
3616const struct amdgpu_ip_block_version gfx_v6_0_ip_block =
3617{
3618 .type = AMD_IP_BLOCK_TYPE_GFX,
3619 .major = 6,
3620 .minor = 0,
3621 .rev = 0,
3622 .funcs = &gfx_v6_0_ip_funcs,
3623};
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/module.h>
25
26#include "amdgpu.h"
27#include "amdgpu_ih.h"
28#include "amdgpu_gfx.h"
29#include "amdgpu_ucode.h"
30#include "clearstate_si.h"
31#include "bif/bif_3_0_d.h"
32#include "bif/bif_3_0_sh_mask.h"
33#include "oss/oss_1_0_d.h"
34#include "oss/oss_1_0_sh_mask.h"
35#include "gca/gfx_6_0_d.h"
36#include "gca/gfx_6_0_sh_mask.h"
37#include "gmc/gmc_6_0_d.h"
38#include "gmc/gmc_6_0_sh_mask.h"
39#include "dce/dce_6_0_d.h"
40#include "dce/dce_6_0_sh_mask.h"
41#include "gca/gfx_7_2_enum.h"
42#include "si_enums.h"
43#include "si.h"
44
45static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
46static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
47static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev);
48
49MODULE_FIRMWARE("amdgpu/tahiti_pfp.bin");
50MODULE_FIRMWARE("amdgpu/tahiti_me.bin");
51MODULE_FIRMWARE("amdgpu/tahiti_ce.bin");
52MODULE_FIRMWARE("amdgpu/tahiti_rlc.bin");
53
54MODULE_FIRMWARE("amdgpu/pitcairn_pfp.bin");
55MODULE_FIRMWARE("amdgpu/pitcairn_me.bin");
56MODULE_FIRMWARE("amdgpu/pitcairn_ce.bin");
57MODULE_FIRMWARE("amdgpu/pitcairn_rlc.bin");
58
59MODULE_FIRMWARE("amdgpu/verde_pfp.bin");
60MODULE_FIRMWARE("amdgpu/verde_me.bin");
61MODULE_FIRMWARE("amdgpu/verde_ce.bin");
62MODULE_FIRMWARE("amdgpu/verde_rlc.bin");
63
64MODULE_FIRMWARE("amdgpu/oland_pfp.bin");
65MODULE_FIRMWARE("amdgpu/oland_me.bin");
66MODULE_FIRMWARE("amdgpu/oland_ce.bin");
67MODULE_FIRMWARE("amdgpu/oland_rlc.bin");
68
69MODULE_FIRMWARE("amdgpu/hainan_pfp.bin");
70MODULE_FIRMWARE("amdgpu/hainan_me.bin");
71MODULE_FIRMWARE("amdgpu/hainan_ce.bin");
72MODULE_FIRMWARE("amdgpu/hainan_rlc.bin");
73
74static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
75static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
76//static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev);
77static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
78
79#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
80#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
81#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
82#define MICRO_TILE_MODE(x) ((x) << 0)
83#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
84#define BANK_WIDTH(x) ((x) << 14)
85#define BANK_HEIGHT(x) ((x) << 16)
86#define MACRO_TILE_ASPECT(x) ((x) << 18)
87#define NUM_BANKS(x) ((x) << 20)
88
89static const u32 verde_rlc_save_restore_register_list[] =
90{
91 (0x8000 << 16) | (0x98f4 >> 2),
92 0x00000000,
93 (0x8040 << 16) | (0x98f4 >> 2),
94 0x00000000,
95 (0x8000 << 16) | (0xe80 >> 2),
96 0x00000000,
97 (0x8040 << 16) | (0xe80 >> 2),
98 0x00000000,
99 (0x8000 << 16) | (0x89bc >> 2),
100 0x00000000,
101 (0x8040 << 16) | (0x89bc >> 2),
102 0x00000000,
103 (0x8000 << 16) | (0x8c1c >> 2),
104 0x00000000,
105 (0x8040 << 16) | (0x8c1c >> 2),
106 0x00000000,
107 (0x9c00 << 16) | (0x98f0 >> 2),
108 0x00000000,
109 (0x9c00 << 16) | (0xe7c >> 2),
110 0x00000000,
111 (0x8000 << 16) | (0x9148 >> 2),
112 0x00000000,
113 (0x8040 << 16) | (0x9148 >> 2),
114 0x00000000,
115 (0x9c00 << 16) | (0x9150 >> 2),
116 0x00000000,
117 (0x9c00 << 16) | (0x897c >> 2),
118 0x00000000,
119 (0x9c00 << 16) | (0x8d8c >> 2),
120 0x00000000,
121 (0x9c00 << 16) | (0xac54 >> 2),
122 0X00000000,
123 0x3,
124 (0x9c00 << 16) | (0x98f8 >> 2),
125 0x00000000,
126 (0x9c00 << 16) | (0x9910 >> 2),
127 0x00000000,
128 (0x9c00 << 16) | (0x9914 >> 2),
129 0x00000000,
130 (0x9c00 << 16) | (0x9918 >> 2),
131 0x00000000,
132 (0x9c00 << 16) | (0x991c >> 2),
133 0x00000000,
134 (0x9c00 << 16) | (0x9920 >> 2),
135 0x00000000,
136 (0x9c00 << 16) | (0x9924 >> 2),
137 0x00000000,
138 (0x9c00 << 16) | (0x9928 >> 2),
139 0x00000000,
140 (0x9c00 << 16) | (0x992c >> 2),
141 0x00000000,
142 (0x9c00 << 16) | (0x9930 >> 2),
143 0x00000000,
144 (0x9c00 << 16) | (0x9934 >> 2),
145 0x00000000,
146 (0x9c00 << 16) | (0x9938 >> 2),
147 0x00000000,
148 (0x9c00 << 16) | (0x993c >> 2),
149 0x00000000,
150 (0x9c00 << 16) | (0x9940 >> 2),
151 0x00000000,
152 (0x9c00 << 16) | (0x9944 >> 2),
153 0x00000000,
154 (0x9c00 << 16) | (0x9948 >> 2),
155 0x00000000,
156 (0x9c00 << 16) | (0x994c >> 2),
157 0x00000000,
158 (0x9c00 << 16) | (0x9950 >> 2),
159 0x00000000,
160 (0x9c00 << 16) | (0x9954 >> 2),
161 0x00000000,
162 (0x9c00 << 16) | (0x9958 >> 2),
163 0x00000000,
164 (0x9c00 << 16) | (0x995c >> 2),
165 0x00000000,
166 (0x9c00 << 16) | (0x9960 >> 2),
167 0x00000000,
168 (0x9c00 << 16) | (0x9964 >> 2),
169 0x00000000,
170 (0x9c00 << 16) | (0x9968 >> 2),
171 0x00000000,
172 (0x9c00 << 16) | (0x996c >> 2),
173 0x00000000,
174 (0x9c00 << 16) | (0x9970 >> 2),
175 0x00000000,
176 (0x9c00 << 16) | (0x9974 >> 2),
177 0x00000000,
178 (0x9c00 << 16) | (0x9978 >> 2),
179 0x00000000,
180 (0x9c00 << 16) | (0x997c >> 2),
181 0x00000000,
182 (0x9c00 << 16) | (0x9980 >> 2),
183 0x00000000,
184 (0x9c00 << 16) | (0x9984 >> 2),
185 0x00000000,
186 (0x9c00 << 16) | (0x9988 >> 2),
187 0x00000000,
188 (0x9c00 << 16) | (0x998c >> 2),
189 0x00000000,
190 (0x9c00 << 16) | (0x8c00 >> 2),
191 0x00000000,
192 (0x9c00 << 16) | (0x8c14 >> 2),
193 0x00000000,
194 (0x9c00 << 16) | (0x8c04 >> 2),
195 0x00000000,
196 (0x9c00 << 16) | (0x8c08 >> 2),
197 0x00000000,
198 (0x8000 << 16) | (0x9b7c >> 2),
199 0x00000000,
200 (0x8040 << 16) | (0x9b7c >> 2),
201 0x00000000,
202 (0x8000 << 16) | (0xe84 >> 2),
203 0x00000000,
204 (0x8040 << 16) | (0xe84 >> 2),
205 0x00000000,
206 (0x8000 << 16) | (0x89c0 >> 2),
207 0x00000000,
208 (0x8040 << 16) | (0x89c0 >> 2),
209 0x00000000,
210 (0x8000 << 16) | (0x914c >> 2),
211 0x00000000,
212 (0x8040 << 16) | (0x914c >> 2),
213 0x00000000,
214 (0x8000 << 16) | (0x8c20 >> 2),
215 0x00000000,
216 (0x8040 << 16) | (0x8c20 >> 2),
217 0x00000000,
218 (0x8000 << 16) | (0x9354 >> 2),
219 0x00000000,
220 (0x8040 << 16) | (0x9354 >> 2),
221 0x00000000,
222 (0x9c00 << 16) | (0x9060 >> 2),
223 0x00000000,
224 (0x9c00 << 16) | (0x9364 >> 2),
225 0x00000000,
226 (0x9c00 << 16) | (0x9100 >> 2),
227 0x00000000,
228 (0x9c00 << 16) | (0x913c >> 2),
229 0x00000000,
230 (0x8000 << 16) | (0x90e0 >> 2),
231 0x00000000,
232 (0x8000 << 16) | (0x90e4 >> 2),
233 0x00000000,
234 (0x8000 << 16) | (0x90e8 >> 2),
235 0x00000000,
236 (0x8040 << 16) | (0x90e0 >> 2),
237 0x00000000,
238 (0x8040 << 16) | (0x90e4 >> 2),
239 0x00000000,
240 (0x8040 << 16) | (0x90e8 >> 2),
241 0x00000000,
242 (0x9c00 << 16) | (0x8bcc >> 2),
243 0x00000000,
244 (0x9c00 << 16) | (0x8b24 >> 2),
245 0x00000000,
246 (0x9c00 << 16) | (0x88c4 >> 2),
247 0x00000000,
248 (0x9c00 << 16) | (0x8e50 >> 2),
249 0x00000000,
250 (0x9c00 << 16) | (0x8c0c >> 2),
251 0x00000000,
252 (0x9c00 << 16) | (0x8e58 >> 2),
253 0x00000000,
254 (0x9c00 << 16) | (0x8e5c >> 2),
255 0x00000000,
256 (0x9c00 << 16) | (0x9508 >> 2),
257 0x00000000,
258 (0x9c00 << 16) | (0x950c >> 2),
259 0x00000000,
260 (0x9c00 << 16) | (0x9494 >> 2),
261 0x00000000,
262 (0x9c00 << 16) | (0xac0c >> 2),
263 0x00000000,
264 (0x9c00 << 16) | (0xac10 >> 2),
265 0x00000000,
266 (0x9c00 << 16) | (0xac14 >> 2),
267 0x00000000,
268 (0x9c00 << 16) | (0xae00 >> 2),
269 0x00000000,
270 (0x9c00 << 16) | (0xac08 >> 2),
271 0x00000000,
272 (0x9c00 << 16) | (0x88d4 >> 2),
273 0x00000000,
274 (0x9c00 << 16) | (0x88c8 >> 2),
275 0x00000000,
276 (0x9c00 << 16) | (0x88cc >> 2),
277 0x00000000,
278 (0x9c00 << 16) | (0x89b0 >> 2),
279 0x00000000,
280 (0x9c00 << 16) | (0x8b10 >> 2),
281 0x00000000,
282 (0x9c00 << 16) | (0x8a14 >> 2),
283 0x00000000,
284 (0x9c00 << 16) | (0x9830 >> 2),
285 0x00000000,
286 (0x9c00 << 16) | (0x9834 >> 2),
287 0x00000000,
288 (0x9c00 << 16) | (0x9838 >> 2),
289 0x00000000,
290 (0x9c00 << 16) | (0x9a10 >> 2),
291 0x00000000,
292 (0x8000 << 16) | (0x9870 >> 2),
293 0x00000000,
294 (0x8000 << 16) | (0x9874 >> 2),
295 0x00000000,
296 (0x8001 << 16) | (0x9870 >> 2),
297 0x00000000,
298 (0x8001 << 16) | (0x9874 >> 2),
299 0x00000000,
300 (0x8040 << 16) | (0x9870 >> 2),
301 0x00000000,
302 (0x8040 << 16) | (0x9874 >> 2),
303 0x00000000,
304 (0x8041 << 16) | (0x9870 >> 2),
305 0x00000000,
306 (0x8041 << 16) | (0x9874 >> 2),
307 0x00000000,
308 0x00000000
309};
310
311static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
312{
313 const char *chip_name;
314 char fw_name[30];
315 int err;
316 const struct gfx_firmware_header_v1_0 *cp_hdr;
317 const struct rlc_firmware_header_v1_0 *rlc_hdr;
318
319 DRM_DEBUG("\n");
320
321 switch (adev->asic_type) {
322 case CHIP_TAHITI:
323 chip_name = "tahiti";
324 break;
325 case CHIP_PITCAIRN:
326 chip_name = "pitcairn";
327 break;
328 case CHIP_VERDE:
329 chip_name = "verde";
330 break;
331 case CHIP_OLAND:
332 chip_name = "oland";
333 break;
334 case CHIP_HAINAN:
335 chip_name = "hainan";
336 break;
337 default: BUG();
338 }
339
340 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
341 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);
342 if (err)
343 goto out;
344 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
345 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
346 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
347
348 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
349 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);
350 if (err)
351 goto out;
352 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
353 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
354 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
355
356 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
357 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw, fw_name);
358 if (err)
359 goto out;
360 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
361 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
362 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
363
364 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
365 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name);
366 if (err)
367 goto out;
368 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
369 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
370 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
371
372out:
373 if (err) {
374 pr_err("gfx6: Failed to load firmware \"%s\"\n", fw_name);
375 amdgpu_ucode_release(&adev->gfx.pfp_fw);
376 amdgpu_ucode_release(&adev->gfx.me_fw);
377 amdgpu_ucode_release(&adev->gfx.ce_fw);
378 amdgpu_ucode_release(&adev->gfx.rlc_fw);
379 }
380 return err;
381}
382
383static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
384{
385 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
386 u32 reg_offset, split_equal_to_row_size, *tilemode;
387
388 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array));
389 tilemode = adev->gfx.config.tile_mode_array;
390
391 switch (adev->gfx.config.mem_row_size_in_kb) {
392 case 1:
393 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
394 break;
395 case 2:
396 default:
397 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
398 break;
399 case 4:
400 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
401 break;
402 }
403
404 if (adev->asic_type == CHIP_VERDE) {
405 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
406 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
407 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
408 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
409 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
410 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
411 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
412 NUM_BANKS(ADDR_SURF_16_BANK);
413 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
414 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
415 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
416 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
417 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
418 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
419 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
420 NUM_BANKS(ADDR_SURF_16_BANK);
421 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
422 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
423 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
424 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
425 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
426 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
427 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
428 NUM_BANKS(ADDR_SURF_16_BANK);
429 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
430 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
431 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
432 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
433 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
434 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
435 NUM_BANKS(ADDR_SURF_8_BANK) |
436 TILE_SPLIT(split_equal_to_row_size);
437 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
438 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
439 PIPE_CONFIG(ADDR_SURF_P4_8x16);
440 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
441 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
442 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
443 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
444 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
445 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
446 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
447 NUM_BANKS(ADDR_SURF_4_BANK);
448 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
449 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
450 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
451 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
452 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
453 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
454 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
455 NUM_BANKS(ADDR_SURF_4_BANK);
456 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
457 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
458 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
459 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
460 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
461 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
462 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
463 NUM_BANKS(ADDR_SURF_2_BANK);
464 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
465 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
466 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
467 PIPE_CONFIG(ADDR_SURF_P4_8x16);
468 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
469 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
470 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
471 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
472 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
473 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
474 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
475 NUM_BANKS(ADDR_SURF_16_BANK);
476 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
477 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
478 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
479 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
480 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
481 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
482 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
483 NUM_BANKS(ADDR_SURF_16_BANK);
484 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
485 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
486 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
487 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
488 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
489 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
490 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
491 NUM_BANKS(ADDR_SURF_16_BANK);
492 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
493 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
494 PIPE_CONFIG(ADDR_SURF_P4_8x16);
495 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
496 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
497 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
498 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
499 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
500 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
501 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
502 NUM_BANKS(ADDR_SURF_16_BANK);
503 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
504 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
505 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
506 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
507 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
508 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
509 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
510 NUM_BANKS(ADDR_SURF_16_BANK);
511 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
512 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
513 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
514 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
515 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
516 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
517 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
518 NUM_BANKS(ADDR_SURF_16_BANK);
519 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
520 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
521 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
522 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
523 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
524 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
525 NUM_BANKS(ADDR_SURF_16_BANK) |
526 TILE_SPLIT(split_equal_to_row_size);
527 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
528 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
529 PIPE_CONFIG(ADDR_SURF_P4_8x16);
530 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
531 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
532 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
533 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
534 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
535 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
536 NUM_BANKS(ADDR_SURF_16_BANK) |
537 TILE_SPLIT(split_equal_to_row_size);
538 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
539 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
540 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
541 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
542 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
543 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
544 NUM_BANKS(ADDR_SURF_16_BANK) |
545 TILE_SPLIT(split_equal_to_row_size);
546 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
547 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
548 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
549 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
550 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
551 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
552 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
553 NUM_BANKS(ADDR_SURF_8_BANK);
554 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
555 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
556 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
557 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
558 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
559 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
560 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
561 NUM_BANKS(ADDR_SURF_8_BANK);
562 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
563 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
564 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
565 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
566 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
567 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
568 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
569 NUM_BANKS(ADDR_SURF_4_BANK);
570 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
571 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
572 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
573 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
574 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
575 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
576 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
577 NUM_BANKS(ADDR_SURF_4_BANK);
578 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
579 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
580 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
581 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
582 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
583 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
584 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
585 NUM_BANKS(ADDR_SURF_2_BANK);
586 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
587 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
588 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
589 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
590 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
591 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
592 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
593 NUM_BANKS(ADDR_SURF_2_BANK);
594 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
595 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
596 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
597 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
598 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
599 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
600 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
601 NUM_BANKS(ADDR_SURF_2_BANK);
602 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
603 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
604 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
605 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
606 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
607 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
608 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
609 NUM_BANKS(ADDR_SURF_2_BANK);
610 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
611 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
612 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
613 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
614 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
615 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
616 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
617 NUM_BANKS(ADDR_SURF_2_BANK);
618 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
619 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
620 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
621 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
622 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
623 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
624 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
625 NUM_BANKS(ADDR_SURF_2_BANK);
626 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
627 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
628 } else if (adev->asic_type == CHIP_OLAND) {
629 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
630 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
631 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
632 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
633 NUM_BANKS(ADDR_SURF_16_BANK) |
634 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
635 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
636 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
637 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
638 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
639 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
640 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
641 NUM_BANKS(ADDR_SURF_16_BANK) |
642 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
643 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
644 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
645 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
646 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
647 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
648 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
649 NUM_BANKS(ADDR_SURF_16_BANK) |
650 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
651 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
652 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
653 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
654 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
655 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
656 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
657 NUM_BANKS(ADDR_SURF_16_BANK) |
658 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
659 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
660 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
661 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
662 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
663 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
664 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
665 NUM_BANKS(ADDR_SURF_16_BANK) |
666 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
667 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
668 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
669 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
670 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
671 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
672 TILE_SPLIT(split_equal_to_row_size) |
673 NUM_BANKS(ADDR_SURF_16_BANK) |
674 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
675 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
676 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
677 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
678 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
679 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
680 TILE_SPLIT(split_equal_to_row_size) |
681 NUM_BANKS(ADDR_SURF_16_BANK) |
682 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
683 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
684 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
685 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
686 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
687 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
688 TILE_SPLIT(split_equal_to_row_size) |
689 NUM_BANKS(ADDR_SURF_16_BANK) |
690 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
691 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
692 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
693 tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
694 ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
695 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
696 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
697 NUM_BANKS(ADDR_SURF_16_BANK) |
698 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
699 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
700 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
701 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
702 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
703 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
704 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
705 NUM_BANKS(ADDR_SURF_16_BANK) |
706 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
707 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
708 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
709 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
710 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
711 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
712 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
713 NUM_BANKS(ADDR_SURF_16_BANK) |
714 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
715 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
716 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
717 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
718 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
719 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
720 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
721 NUM_BANKS(ADDR_SURF_16_BANK) |
722 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
723 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
724 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
725 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
726 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
727 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
728 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
729 NUM_BANKS(ADDR_SURF_16_BANK) |
730 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
731 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
732 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
733 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
734 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
735 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
736 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
737 NUM_BANKS(ADDR_SURF_16_BANK) |
738 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
739 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
740 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
741 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
742 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
743 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
744 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
745 NUM_BANKS(ADDR_SURF_16_BANK) |
746 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
747 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
748 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
749 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
750 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
751 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
752 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
753 NUM_BANKS(ADDR_SURF_16_BANK) |
754 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
755 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
756 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
757 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
758 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
759 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
760 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
761 NUM_BANKS(ADDR_SURF_16_BANK) |
762 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
763 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
764 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
765 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
766 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
767 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
768 TILE_SPLIT(split_equal_to_row_size) |
769 NUM_BANKS(ADDR_SURF_16_BANK) |
770 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
771 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
772 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
773 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
774 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
775 PIPE_CONFIG(ADDR_SURF_P4_8x16);
776 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
777 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
778 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
779 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
780 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
781 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
782 NUM_BANKS(ADDR_SURF_16_BANK) |
783 TILE_SPLIT(split_equal_to_row_size);
784 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
785 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
786 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
787 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
788 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
789 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
790 NUM_BANKS(ADDR_SURF_16_BANK) |
791 TILE_SPLIT(split_equal_to_row_size);
792 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
793 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
794 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
795 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
796 NUM_BANKS(ADDR_SURF_16_BANK) |
797 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
798 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
799 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
800 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
801 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
802 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
803 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
804 NUM_BANKS(ADDR_SURF_16_BANK) |
805 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
806 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
807 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
808 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
809 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
810 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
811 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
812 NUM_BANKS(ADDR_SURF_16_BANK) |
813 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
814 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
815 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
816 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
817 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
818 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
819 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
820 NUM_BANKS(ADDR_SURF_16_BANK) |
821 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
822 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
823 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
824 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
825 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
826 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
827 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
828 NUM_BANKS(ADDR_SURF_8_BANK) |
829 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
830 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
831 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1);
832 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
833 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
834 } else if (adev->asic_type == CHIP_HAINAN) {
835 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
836 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
837 PIPE_CONFIG(ADDR_SURF_P2) |
838 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
839 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
840 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
841 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
842 NUM_BANKS(ADDR_SURF_16_BANK);
843 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
844 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
845 PIPE_CONFIG(ADDR_SURF_P2) |
846 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
847 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
848 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
849 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
850 NUM_BANKS(ADDR_SURF_16_BANK);
851 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
852 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
853 PIPE_CONFIG(ADDR_SURF_P2) |
854 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
855 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
856 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
857 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
858 NUM_BANKS(ADDR_SURF_16_BANK);
859 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
860 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
861 PIPE_CONFIG(ADDR_SURF_P2) |
862 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
863 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
864 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
865 NUM_BANKS(ADDR_SURF_8_BANK) |
866 TILE_SPLIT(split_equal_to_row_size);
867 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
868 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
869 PIPE_CONFIG(ADDR_SURF_P2);
870 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
871 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
872 PIPE_CONFIG(ADDR_SURF_P2) |
873 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
874 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
875 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
876 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
877 NUM_BANKS(ADDR_SURF_8_BANK);
878 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
879 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
880 PIPE_CONFIG(ADDR_SURF_P2) |
881 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
882 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
883 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
884 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
885 NUM_BANKS(ADDR_SURF_8_BANK);
886 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
887 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
888 PIPE_CONFIG(ADDR_SURF_P2) |
889 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
890 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
891 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
892 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
893 NUM_BANKS(ADDR_SURF_4_BANK);
894 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
895 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
896 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
897 PIPE_CONFIG(ADDR_SURF_P2);
898 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
899 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
900 PIPE_CONFIG(ADDR_SURF_P2) |
901 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
902 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
903 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
904 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
905 NUM_BANKS(ADDR_SURF_16_BANK);
906 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
907 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
908 PIPE_CONFIG(ADDR_SURF_P2) |
909 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
910 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
911 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
912 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
913 NUM_BANKS(ADDR_SURF_16_BANK);
914 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
915 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
916 PIPE_CONFIG(ADDR_SURF_P2) |
917 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
918 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
919 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
920 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
921 NUM_BANKS(ADDR_SURF_16_BANK);
922 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
923 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
924 PIPE_CONFIG(ADDR_SURF_P2);
925 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
926 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
927 PIPE_CONFIG(ADDR_SURF_P2) |
928 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
929 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
930 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
931 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
932 NUM_BANKS(ADDR_SURF_16_BANK);
933 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
934 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
935 PIPE_CONFIG(ADDR_SURF_P2) |
936 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
937 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
938 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
939 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
940 NUM_BANKS(ADDR_SURF_16_BANK);
941 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
942 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
943 PIPE_CONFIG(ADDR_SURF_P2) |
944 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
945 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
946 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
947 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
948 NUM_BANKS(ADDR_SURF_16_BANK);
949 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
950 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
951 PIPE_CONFIG(ADDR_SURF_P2) |
952 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
953 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
954 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
955 NUM_BANKS(ADDR_SURF_16_BANK) |
956 TILE_SPLIT(split_equal_to_row_size);
957 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
958 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
959 PIPE_CONFIG(ADDR_SURF_P2);
960 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
961 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
962 PIPE_CONFIG(ADDR_SURF_P2) |
963 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
964 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
965 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
966 NUM_BANKS(ADDR_SURF_16_BANK) |
967 TILE_SPLIT(split_equal_to_row_size);
968 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
969 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
970 PIPE_CONFIG(ADDR_SURF_P2) |
971 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
972 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
973 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
974 NUM_BANKS(ADDR_SURF_16_BANK) |
975 TILE_SPLIT(split_equal_to_row_size);
976 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
977 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
978 PIPE_CONFIG(ADDR_SURF_P2) |
979 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
980 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
981 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
982 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
983 NUM_BANKS(ADDR_SURF_8_BANK);
984 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
985 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
986 PIPE_CONFIG(ADDR_SURF_P2) |
987 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
988 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
989 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
990 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
991 NUM_BANKS(ADDR_SURF_8_BANK);
992 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
993 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
994 PIPE_CONFIG(ADDR_SURF_P2) |
995 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
996 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
997 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
998 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
999 NUM_BANKS(ADDR_SURF_8_BANK);
1000 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1001 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1002 PIPE_CONFIG(ADDR_SURF_P2) |
1003 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1004 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1005 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1006 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1007 NUM_BANKS(ADDR_SURF_8_BANK);
1008 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1009 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1010 PIPE_CONFIG(ADDR_SURF_P2) |
1011 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1012 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1013 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1014 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1015 NUM_BANKS(ADDR_SURF_4_BANK);
1016 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1017 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1018 PIPE_CONFIG(ADDR_SURF_P2) |
1019 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1020 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1021 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1022 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1023 NUM_BANKS(ADDR_SURF_4_BANK);
1024 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1025 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1026 PIPE_CONFIG(ADDR_SURF_P2) |
1027 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1028 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1029 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1030 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1031 NUM_BANKS(ADDR_SURF_4_BANK);
1032 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1033 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1034 PIPE_CONFIG(ADDR_SURF_P2) |
1035 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1036 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1037 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1038 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1039 NUM_BANKS(ADDR_SURF_4_BANK);
1040 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1041 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1042 PIPE_CONFIG(ADDR_SURF_P2) |
1043 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1044 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1045 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1046 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1047 NUM_BANKS(ADDR_SURF_4_BANK);
1048 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1049 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1050 PIPE_CONFIG(ADDR_SURF_P2) |
1051 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1052 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1053 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1054 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1055 NUM_BANKS(ADDR_SURF_4_BANK);
1056 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1057 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1058 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
1059 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1060 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1061 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1062 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1063 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1064 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1065 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1066 NUM_BANKS(ADDR_SURF_16_BANK);
1067 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1068 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1069 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1070 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1071 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1072 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1073 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1074 NUM_BANKS(ADDR_SURF_16_BANK);
1075 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1076 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1077 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1078 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1079 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1080 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1081 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1082 NUM_BANKS(ADDR_SURF_16_BANK);
1083 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1084 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1085 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1086 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1087 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1088 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1089 NUM_BANKS(ADDR_SURF_4_BANK) |
1090 TILE_SPLIT(split_equal_to_row_size);
1091 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1092 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1093 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1094 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1095 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1096 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1097 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1098 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1099 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1100 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1101 NUM_BANKS(ADDR_SURF_2_BANK);
1102 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1103 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1104 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1105 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1106 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1107 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1108 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1109 NUM_BANKS(ADDR_SURF_2_BANK);
1110 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1111 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1112 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1113 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1114 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1115 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1116 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1117 NUM_BANKS(ADDR_SURF_2_BANK);
1118 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
1119 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1120 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1121 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1122 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1123 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1124 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1125 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1126 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1127 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1128 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1129 NUM_BANKS(ADDR_SURF_16_BANK);
1130 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1131 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1132 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1133 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1134 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1135 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1136 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1137 NUM_BANKS(ADDR_SURF_16_BANK);
1138 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1139 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1140 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1141 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1142 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1143 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1144 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1145 NUM_BANKS(ADDR_SURF_16_BANK);
1146 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1147 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1148 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1149 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1150 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1151 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1152 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1153 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1154 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1155 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1156 NUM_BANKS(ADDR_SURF_16_BANK);
1157 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1158 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1159 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1160 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1161 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1162 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1163 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1164 NUM_BANKS(ADDR_SURF_16_BANK);
1165 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1166 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1167 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1168 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1169 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1170 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1171 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1172 NUM_BANKS(ADDR_SURF_16_BANK);
1173 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1174 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1175 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1176 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1177 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1178 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1179 NUM_BANKS(ADDR_SURF_16_BANK) |
1180 TILE_SPLIT(split_equal_to_row_size);
1181 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1182 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1183 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1184 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1185 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1186 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1187 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1188 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1189 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1190 NUM_BANKS(ADDR_SURF_16_BANK) |
1191 TILE_SPLIT(split_equal_to_row_size);
1192 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1193 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1194 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1195 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1196 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1197 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1198 NUM_BANKS(ADDR_SURF_16_BANK) |
1199 TILE_SPLIT(split_equal_to_row_size);
1200 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1201 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1202 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1203 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1204 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1205 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1206 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1207 NUM_BANKS(ADDR_SURF_4_BANK);
1208 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1209 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1210 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1211 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1212 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1213 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1214 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1215 NUM_BANKS(ADDR_SURF_4_BANK);
1216 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1217 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1218 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1219 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1220 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1221 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1222 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1223 NUM_BANKS(ADDR_SURF_2_BANK);
1224 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1225 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1226 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1227 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1228 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1229 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1230 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1231 NUM_BANKS(ADDR_SURF_2_BANK);
1232 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1233 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1234 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1235 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1236 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1237 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1238 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1239 NUM_BANKS(ADDR_SURF_2_BANK);
1240 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1241 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1242 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1243 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1244 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1245 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1246 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1247 NUM_BANKS(ADDR_SURF_2_BANK);
1248 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1249 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1250 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1251 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1252 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1253 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1254 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1255 NUM_BANKS(ADDR_SURF_2_BANK);
1256 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1257 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1258 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1259 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1260 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1261 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1262 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1263 NUM_BANKS(ADDR_SURF_2_BANK);
1264 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1265 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1266 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1267 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1268 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1269 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1270 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1271 NUM_BANKS(ADDR_SURF_2_BANK);
1272 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1273 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1274 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1275 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1276 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1277 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1278 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1279 NUM_BANKS(ADDR_SURF_2_BANK);
1280 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1281 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1282 } else {
1283 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1284 }
1285}
1286
1287static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1288 u32 sh_num, u32 instance, int xcc_id)
1289{
1290 u32 data;
1291
1292 if (instance == 0xffffffff)
1293 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1294 else
1295 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1296
1297 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1298 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1299 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1300 else if (se_num == 0xffffffff)
1301 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1302 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1303 else if (sh_num == 0xffffffff)
1304 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1305 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1306 else
1307 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1308 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1309 WREG32(mmGRBM_GFX_INDEX, data);
1310}
1311
1312static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1313{
1314 u32 data, mask;
1315
1316 data = RREG32(mmCC_RB_BACKEND_DISABLE) |
1317 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1318
1319 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
1320
1321 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/
1322 adev->gfx.config.max_sh_per_se);
1323
1324 return ~data & mask;
1325}
1326
1327static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf)
1328{
1329 switch (adev->asic_type) {
1330 case CHIP_TAHITI:
1331 case CHIP_PITCAIRN:
1332 *rconf |=
1333 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) |
1334 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1335 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1336 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) |
1337 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) |
1338 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) |
1339 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT);
1340 break;
1341 case CHIP_VERDE:
1342 *rconf |=
1343 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1344 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1345 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT);
1346 break;
1347 case CHIP_OLAND:
1348 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT);
1349 break;
1350 case CHIP_HAINAN:
1351 *rconf |= 0x0;
1352 break;
1353 default:
1354 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1355 break;
1356 }
1357}
1358
1359static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1360 u32 raster_config, unsigned rb_mask,
1361 unsigned num_rb)
1362{
1363 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1364 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1365 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1366 unsigned rb_per_se = num_rb / num_se;
1367 unsigned se_mask[4];
1368 unsigned se;
1369
1370 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1371 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1372 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1373 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1374
1375 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1376 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1377 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1378
1379 for (se = 0; se < num_se; se++) {
1380 unsigned raster_config_se = raster_config;
1381 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1382 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1383 int idx = (se / 2) * 2;
1384
1385 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1386 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK;
1387
1388 if (!se_mask[idx])
1389 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1390 else
1391 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1392 }
1393
1394 pkr0_mask &= rb_mask;
1395 pkr1_mask &= rb_mask;
1396 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1397 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK;
1398
1399 if (!pkr0_mask)
1400 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1401 else
1402 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1403 }
1404
1405 if (rb_per_se >= 2) {
1406 unsigned rb0_mask = 1 << (se * rb_per_se);
1407 unsigned rb1_mask = rb0_mask << 1;
1408
1409 rb0_mask &= rb_mask;
1410 rb1_mask &= rb_mask;
1411 if (!rb0_mask || !rb1_mask) {
1412 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK;
1413
1414 if (!rb0_mask)
1415 raster_config_se |=
1416 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1417 else
1418 raster_config_se |=
1419 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1420 }
1421
1422 if (rb_per_se > 2) {
1423 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1424 rb1_mask = rb0_mask << 1;
1425 rb0_mask &= rb_mask;
1426 rb1_mask &= rb_mask;
1427 if (!rb0_mask || !rb1_mask) {
1428 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK;
1429
1430 if (!rb0_mask)
1431 raster_config_se |=
1432 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1433 else
1434 raster_config_se |=
1435 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1436 }
1437 }
1438 }
1439
1440 /* GRBM_GFX_INDEX has a different offset on SI */
1441 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff, 0);
1442 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1443 }
1444
1445 /* GRBM_GFX_INDEX has a different offset on SI */
1446 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
1447}
1448
1449static void gfx_v6_0_setup_rb(struct amdgpu_device *adev)
1450{
1451 int i, j;
1452 u32 data;
1453 u32 raster_config = 0;
1454 u32 active_rbs = 0;
1455 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1456 adev->gfx.config.max_sh_per_se;
1457 unsigned num_rb_pipes;
1458
1459 mutex_lock(&adev->grbm_idx_mutex);
1460 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1461 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1462 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0);
1463 data = gfx_v6_0_get_rb_active_bitmap(adev);
1464 active_rbs |= data <<
1465 ((i * adev->gfx.config.max_sh_per_se + j) *
1466 rb_bitmap_width_per_sh);
1467 }
1468 }
1469 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
1470
1471 adev->gfx.config.backend_enable_mask = active_rbs;
1472 adev->gfx.config.num_rbs = hweight32(active_rbs);
1473
1474 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1475 adev->gfx.config.max_shader_engines, 16);
1476
1477 gfx_v6_0_raster_config(adev, &raster_config);
1478
1479 if (!adev->gfx.config.backend_enable_mask ||
1480 adev->gfx.config.num_rbs >= num_rb_pipes)
1481 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1482 else
1483 gfx_v6_0_write_harvested_raster_configs(adev, raster_config,
1484 adev->gfx.config.backend_enable_mask,
1485 num_rb_pipes);
1486
1487 /* cache the values for userspace */
1488 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1489 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1490 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0);
1491 adev->gfx.config.rb_config[i][j].rb_backend_disable =
1492 RREG32(mmCC_RB_BACKEND_DISABLE);
1493 adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
1494 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1495 adev->gfx.config.rb_config[i][j].raster_config =
1496 RREG32(mmPA_SC_RASTER_CONFIG);
1497 }
1498 }
1499 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
1500 mutex_unlock(&adev->grbm_idx_mutex);
1501}
1502
1503static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
1504 u32 bitmap)
1505{
1506 u32 data;
1507
1508 if (!bitmap)
1509 return;
1510
1511 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
1512 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
1513
1514 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
1515}
1516
1517static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev)
1518{
1519 u32 data, mask;
1520
1521 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
1522 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
1523
1524 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
1525 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
1526}
1527
1528
1529static void gfx_v6_0_setup_spi(struct amdgpu_device *adev)
1530{
1531 int i, j, k;
1532 u32 data, mask;
1533 u32 active_cu = 0;
1534
1535 mutex_lock(&adev->grbm_idx_mutex);
1536 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1537 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1538 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0);
1539 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3);
1540 active_cu = gfx_v6_0_get_cu_enabled(adev);
1541
1542 mask = 1;
1543 for (k = 0; k < 16; k++) {
1544 mask <<= k;
1545 if (active_cu & mask) {
1546 data &= ~mask;
1547 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data);
1548 break;
1549 }
1550 }
1551 }
1552 }
1553 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
1554 mutex_unlock(&adev->grbm_idx_mutex);
1555}
1556
1557static void gfx_v6_0_config_init(struct amdgpu_device *adev)
1558{
1559 adev->gfx.config.double_offchip_lds_buf = 0;
1560}
1561
1562static void gfx_v6_0_constants_init(struct amdgpu_device *adev)
1563{
1564 u32 gb_addr_config = 0;
1565 u32 mc_arb_ramcfg;
1566 u32 sx_debug_1;
1567 u32 hdp_host_path_cntl;
1568 u32 tmp;
1569
1570 switch (adev->asic_type) {
1571 case CHIP_TAHITI:
1572 adev->gfx.config.max_shader_engines = 2;
1573 adev->gfx.config.max_tile_pipes = 12;
1574 adev->gfx.config.max_cu_per_sh = 8;
1575 adev->gfx.config.max_sh_per_se = 2;
1576 adev->gfx.config.max_backends_per_se = 4;
1577 adev->gfx.config.max_texture_channel_caches = 12;
1578 adev->gfx.config.max_gprs = 256;
1579 adev->gfx.config.max_gs_threads = 32;
1580 adev->gfx.config.max_hw_contexts = 8;
1581
1582 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1583 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1584 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1585 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1586 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1587 break;
1588 case CHIP_PITCAIRN:
1589 adev->gfx.config.max_shader_engines = 2;
1590 adev->gfx.config.max_tile_pipes = 8;
1591 adev->gfx.config.max_cu_per_sh = 5;
1592 adev->gfx.config.max_sh_per_se = 2;
1593 adev->gfx.config.max_backends_per_se = 4;
1594 adev->gfx.config.max_texture_channel_caches = 8;
1595 adev->gfx.config.max_gprs = 256;
1596 adev->gfx.config.max_gs_threads = 32;
1597 adev->gfx.config.max_hw_contexts = 8;
1598
1599 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1600 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1601 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1602 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1603 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1604 break;
1605 case CHIP_VERDE:
1606 adev->gfx.config.max_shader_engines = 1;
1607 adev->gfx.config.max_tile_pipes = 4;
1608 adev->gfx.config.max_cu_per_sh = 5;
1609 adev->gfx.config.max_sh_per_se = 2;
1610 adev->gfx.config.max_backends_per_se = 4;
1611 adev->gfx.config.max_texture_channel_caches = 4;
1612 adev->gfx.config.max_gprs = 256;
1613 adev->gfx.config.max_gs_threads = 32;
1614 adev->gfx.config.max_hw_contexts = 8;
1615
1616 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1617 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1618 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1619 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1620 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1621 break;
1622 case CHIP_OLAND:
1623 adev->gfx.config.max_shader_engines = 1;
1624 adev->gfx.config.max_tile_pipes = 4;
1625 adev->gfx.config.max_cu_per_sh = 6;
1626 adev->gfx.config.max_sh_per_se = 1;
1627 adev->gfx.config.max_backends_per_se = 2;
1628 adev->gfx.config.max_texture_channel_caches = 4;
1629 adev->gfx.config.max_gprs = 256;
1630 adev->gfx.config.max_gs_threads = 16;
1631 adev->gfx.config.max_hw_contexts = 8;
1632
1633 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1634 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1635 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1636 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1637 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1638 break;
1639 case CHIP_HAINAN:
1640 adev->gfx.config.max_shader_engines = 1;
1641 adev->gfx.config.max_tile_pipes = 4;
1642 adev->gfx.config.max_cu_per_sh = 5;
1643 adev->gfx.config.max_sh_per_se = 1;
1644 adev->gfx.config.max_backends_per_se = 1;
1645 adev->gfx.config.max_texture_channel_caches = 2;
1646 adev->gfx.config.max_gprs = 256;
1647 adev->gfx.config.max_gs_threads = 16;
1648 adev->gfx.config.max_hw_contexts = 8;
1649
1650 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1651 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1652 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1653 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1654 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
1655 break;
1656 default:
1657 BUG();
1658 break;
1659 }
1660
1661 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1662 WREG32(mmSRBM_INT_CNTL, 1);
1663 WREG32(mmSRBM_INT_ACK, 1);
1664
1665 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
1666
1667 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1668 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1669
1670 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1671 adev->gfx.config.mem_max_burst_length_bytes = 256;
1672 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
1673 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1674 if (adev->gfx.config.mem_row_size_in_kb > 4)
1675 adev->gfx.config.mem_row_size_in_kb = 4;
1676 adev->gfx.config.shader_engine_tile_size = 32;
1677 adev->gfx.config.num_gpus = 1;
1678 adev->gfx.config.multi_gpu_tile_size = 64;
1679
1680 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
1681 switch (adev->gfx.config.mem_row_size_in_kb) {
1682 case 1:
1683 default:
1684 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1685 break;
1686 case 2:
1687 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1688 break;
1689 case 4:
1690 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1691 break;
1692 }
1693 gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK;
1694 if (adev->gfx.config.max_shader_engines == 2)
1695 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT;
1696 adev->gfx.config.gb_addr_config = gb_addr_config;
1697
1698 WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
1699 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config);
1700 WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
1701 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
1702 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1703 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1704
1705#if 0
1706 if (adev->has_uvd) {
1707 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
1708 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1709 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1710 }
1711#endif
1712 gfx_v6_0_tiling_mode_table_init(adev);
1713
1714 gfx_v6_0_setup_rb(adev);
1715
1716 gfx_v6_0_setup_spi(adev);
1717
1718 gfx_v6_0_get_cu_info(adev);
1719 gfx_v6_0_config_init(adev);
1720
1721 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |
1722 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));
1723 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1724 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1725
1726 sx_debug_1 = RREG32(mmSX_DEBUG_1);
1727 WREG32(mmSX_DEBUG_1, sx_debug_1);
1728
1729 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1730
1731 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1732 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1733 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1734 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1735
1736 WREG32(mmVGT_NUM_INSTANCES, 1);
1737 WREG32(mmCP_PERFMON_CNTL, 0);
1738 WREG32(mmSQ_CONFIG, 0);
1739 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1740 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1741
1742 WREG32(mmVGT_CACHE_INVALIDATION,
1743 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1744 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1745
1746 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1747 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1748
1749 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0);
1750 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0);
1751 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0);
1752 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0);
1753 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0);
1754 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0);
1755 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0);
1756 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0);
1757
1758 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL);
1759 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1760
1761 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1762 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1763
1764 udelay(50);
1765}
1766
1767static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
1768{
1769 struct amdgpu_device *adev = ring->adev;
1770 uint32_t tmp = 0;
1771 unsigned i;
1772 int r;
1773
1774 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
1775
1776 r = amdgpu_ring_alloc(ring, 3);
1777 if (r)
1778 return r;
1779
1780 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1781 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START);
1782 amdgpu_ring_write(ring, 0xDEADBEEF);
1783 amdgpu_ring_commit(ring);
1784
1785 for (i = 0; i < adev->usec_timeout; i++) {
1786 tmp = RREG32(mmSCRATCH_REG0);
1787 if (tmp == 0xDEADBEEF)
1788 break;
1789 udelay(1);
1790 }
1791
1792 if (i >= adev->usec_timeout)
1793 r = -ETIMEDOUT;
1794 return r;
1795}
1796
1797static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
1798{
1799 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
1800 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
1801 EVENT_INDEX(0));
1802}
1803
1804static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1805 u64 seq, unsigned flags)
1806{
1807 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1808 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1809 /* flush read cache over gart */
1810 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1811 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
1812 amdgpu_ring_write(ring, 0);
1813 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1814 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1815 PACKET3_TC_ACTION_ENA |
1816 PACKET3_SH_KCACHE_ACTION_ENA |
1817 PACKET3_SH_ICACHE_ACTION_ENA);
1818 amdgpu_ring_write(ring, 0xFFFFFFFF);
1819 amdgpu_ring_write(ring, 0);
1820 amdgpu_ring_write(ring, 10); /* poll interval */
1821 /* EVENT_WRITE_EOP - flush caches, send int */
1822 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1823 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1824 amdgpu_ring_write(ring, addr & 0xfffffffc);
1825 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1826 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) |
1827 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT));
1828 amdgpu_ring_write(ring, lower_32_bits(seq));
1829 amdgpu_ring_write(ring, upper_32_bits(seq));
1830}
1831
1832static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1833 struct amdgpu_job *job,
1834 struct amdgpu_ib *ib,
1835 uint32_t flags)
1836{
1837 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1838 u32 header, control = 0;
1839
1840 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
1841 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
1842 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1843 amdgpu_ring_write(ring, 0);
1844 }
1845
1846 if (ib->flags & AMDGPU_IB_FLAG_CE)
1847 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1848 else
1849 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1850
1851 control |= ib->length_dw | (vmid << 24);
1852
1853 amdgpu_ring_write(ring, header);
1854 amdgpu_ring_write(ring,
1855#ifdef __BIG_ENDIAN
1856 (2 << 0) |
1857#endif
1858 (ib->gpu_addr & 0xFFFFFFFC));
1859 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1860 amdgpu_ring_write(ring, control);
1861}
1862
1863/**
1864 * gfx_v6_0_ring_test_ib - basic ring IB test
1865 *
1866 * @ring: amdgpu_ring structure holding ring information
1867 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1868 *
1869 * Allocate an IB and execute it on the gfx ring (SI).
1870 * Provides a basic gfx ring test to verify that IBs are working.
1871 * Returns 0 on success, error on failure.
1872 */
1873static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1874{
1875 struct amdgpu_device *adev = ring->adev;
1876 struct dma_fence *f = NULL;
1877 struct amdgpu_ib ib;
1878 uint32_t tmp = 0;
1879 long r;
1880
1881 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
1882 memset(&ib, 0, sizeof(ib));
1883 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
1884 if (r)
1885 return r;
1886
1887 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1888 ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START;
1889 ib.ptr[2] = 0xDEADBEEF;
1890 ib.length_dw = 3;
1891
1892 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1893 if (r)
1894 goto error;
1895
1896 r = dma_fence_wait_timeout(f, false, timeout);
1897 if (r == 0) {
1898 r = -ETIMEDOUT;
1899 goto error;
1900 } else if (r < 0) {
1901 goto error;
1902 }
1903 tmp = RREG32(mmSCRATCH_REG0);
1904 if (tmp == 0xDEADBEEF)
1905 r = 0;
1906 else
1907 r = -EINVAL;
1908
1909error:
1910 amdgpu_ib_free(adev, &ib, NULL);
1911 dma_fence_put(f);
1912 return r;
1913}
1914
1915static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1916{
1917 if (enable) {
1918 WREG32(mmCP_ME_CNTL, 0);
1919 } else {
1920 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK |
1921 CP_ME_CNTL__PFP_HALT_MASK |
1922 CP_ME_CNTL__CE_HALT_MASK));
1923 WREG32(mmSCRATCH_UMSK, 0);
1924 }
1925 udelay(50);
1926}
1927
1928static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1929{
1930 unsigned i;
1931 const struct gfx_firmware_header_v1_0 *pfp_hdr;
1932 const struct gfx_firmware_header_v1_0 *ce_hdr;
1933 const struct gfx_firmware_header_v1_0 *me_hdr;
1934 const __le32 *fw_data;
1935 u32 fw_size;
1936
1937 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1938 return -EINVAL;
1939
1940 gfx_v6_0_cp_gfx_enable(adev, false);
1941 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1942 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1943 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1944
1945 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1946 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1947 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1948
1949 /* PFP */
1950 fw_data = (const __le32 *)
1951 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1952 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
1953 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1954 for (i = 0; i < fw_size; i++)
1955 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
1956 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1957
1958 /* CE */
1959 fw_data = (const __le32 *)
1960 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1961 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
1962 WREG32(mmCP_CE_UCODE_ADDR, 0);
1963 for (i = 0; i < fw_size; i++)
1964 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
1965 WREG32(mmCP_CE_UCODE_ADDR, 0);
1966
1967 /* ME */
1968 fw_data = (const __be32 *)
1969 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
1970 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
1971 WREG32(mmCP_ME_RAM_WADDR, 0);
1972 for (i = 0; i < fw_size; i++)
1973 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
1974 WREG32(mmCP_ME_RAM_WADDR, 0);
1975
1976 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1977 WREG32(mmCP_CE_UCODE_ADDR, 0);
1978 WREG32(mmCP_ME_RAM_WADDR, 0);
1979 WREG32(mmCP_ME_RAM_RADDR, 0);
1980 return 0;
1981}
1982
1983static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev)
1984{
1985 const struct cs_section_def *sect = NULL;
1986 const struct cs_extent_def *ext = NULL;
1987 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1988 int r, i;
1989
1990 r = amdgpu_ring_alloc(ring, 7 + 4);
1991 if (r) {
1992 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
1993 return r;
1994 }
1995 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1996 amdgpu_ring_write(ring, 0x1);
1997 amdgpu_ring_write(ring, 0x0);
1998 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1);
1999 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2000 amdgpu_ring_write(ring, 0);
2001 amdgpu_ring_write(ring, 0);
2002
2003 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2004 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2005 amdgpu_ring_write(ring, 0xc000);
2006 amdgpu_ring_write(ring, 0xe000);
2007 amdgpu_ring_commit(ring);
2008
2009 gfx_v6_0_cp_gfx_enable(adev, true);
2010
2011 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10);
2012 if (r) {
2013 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2014 return r;
2015 }
2016
2017 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2018 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2019
2020 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2021 for (ext = sect->section; ext->extent != NULL; ++ext) {
2022 if (sect->id == SECT_CONTEXT) {
2023 amdgpu_ring_write(ring,
2024 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2025 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2026 for (i = 0; i < ext->reg_count; i++)
2027 amdgpu_ring_write(ring, ext->extent[i]);
2028 }
2029 }
2030 }
2031
2032 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2033 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2034
2035 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2036 amdgpu_ring_write(ring, 0);
2037
2038 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2039 amdgpu_ring_write(ring, 0x00000316);
2040 amdgpu_ring_write(ring, 0x0000000e);
2041 amdgpu_ring_write(ring, 0x00000010);
2042
2043 amdgpu_ring_commit(ring);
2044
2045 return 0;
2046}
2047
2048static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
2049{
2050 struct amdgpu_ring *ring;
2051 u32 tmp;
2052 u32 rb_bufsz;
2053 int r;
2054 u64 rptr_addr;
2055
2056 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2057 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2058
2059 /* Set the write pointer delay */
2060 WREG32(mmCP_RB_WPTR_DELAY, 0);
2061
2062 WREG32(mmCP_DEBUG, 0);
2063 WREG32(mmSCRATCH_ADDR, 0);
2064
2065 /* ring 0 - compute and gfx */
2066 /* Set ring buffer size */
2067 ring = &adev->gfx.gfx_ring[0];
2068 rb_bufsz = order_base_2(ring->ring_size / 8);
2069 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2070
2071#ifdef __BIG_ENDIAN
2072 tmp |= BUF_SWAP_32BIT;
2073#endif
2074 WREG32(mmCP_RB0_CNTL, tmp);
2075
2076 /* Initialize the ring buffer's read and write pointers */
2077 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2078 ring->wptr = 0;
2079 WREG32(mmCP_RB0_WPTR, ring->wptr);
2080
2081 /* set the wb address whether it's enabled or not */
2082 rptr_addr = ring->rptr_gpu_addr;
2083 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2084 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2085
2086 WREG32(mmSCRATCH_UMSK, 0);
2087
2088 mdelay(1);
2089 WREG32(mmCP_RB0_CNTL, tmp);
2090
2091 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8);
2092
2093 /* start the rings */
2094 gfx_v6_0_cp_gfx_start(adev);
2095 r = amdgpu_ring_test_helper(ring);
2096 if (r)
2097 return r;
2098
2099 return 0;
2100}
2101
2102static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
2103{
2104 return *ring->rptr_cpu_addr;
2105}
2106
2107static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
2108{
2109 struct amdgpu_device *adev = ring->adev;
2110
2111 if (ring == &adev->gfx.gfx_ring[0])
2112 return RREG32(mmCP_RB0_WPTR);
2113 else if (ring == &adev->gfx.compute_ring[0])
2114 return RREG32(mmCP_RB1_WPTR);
2115 else if (ring == &adev->gfx.compute_ring[1])
2116 return RREG32(mmCP_RB2_WPTR);
2117 else
2118 BUG();
2119}
2120
2121static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2122{
2123 struct amdgpu_device *adev = ring->adev;
2124
2125 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2126 (void)RREG32(mmCP_RB0_WPTR);
2127}
2128
2129static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2130{
2131 struct amdgpu_device *adev = ring->adev;
2132
2133 if (ring == &adev->gfx.compute_ring[0]) {
2134 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2135 (void)RREG32(mmCP_RB1_WPTR);
2136 } else if (ring == &adev->gfx.compute_ring[1]) {
2137 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr));
2138 (void)RREG32(mmCP_RB2_WPTR);
2139 } else {
2140 BUG();
2141 }
2142
2143}
2144
2145static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
2146{
2147 struct amdgpu_ring *ring;
2148 u32 tmp;
2149 u32 rb_bufsz;
2150 int i, r;
2151 u64 rptr_addr;
2152
2153 /* ring1 - compute only */
2154 /* Set ring buffer size */
2155
2156 ring = &adev->gfx.compute_ring[0];
2157 rb_bufsz = order_base_2(ring->ring_size / 8);
2158 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2159#ifdef __BIG_ENDIAN
2160 tmp |= BUF_SWAP_32BIT;
2161#endif
2162 WREG32(mmCP_RB1_CNTL, tmp);
2163
2164 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK);
2165 ring->wptr = 0;
2166 WREG32(mmCP_RB1_WPTR, ring->wptr);
2167
2168 rptr_addr = ring->rptr_gpu_addr;
2169 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2170 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2171
2172 mdelay(1);
2173 WREG32(mmCP_RB1_CNTL, tmp);
2174 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8);
2175
2176 ring = &adev->gfx.compute_ring[1];
2177 rb_bufsz = order_base_2(ring->ring_size / 8);
2178 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2179#ifdef __BIG_ENDIAN
2180 tmp |= BUF_SWAP_32BIT;
2181#endif
2182 WREG32(mmCP_RB2_CNTL, tmp);
2183
2184 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK);
2185 ring->wptr = 0;
2186 WREG32(mmCP_RB2_WPTR, ring->wptr);
2187 rptr_addr = ring->rptr_gpu_addr;
2188 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
2189 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2190
2191 mdelay(1);
2192 WREG32(mmCP_RB2_CNTL, tmp);
2193 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8);
2194
2195
2196 for (i = 0; i < 2; i++) {
2197 r = amdgpu_ring_test_helper(&adev->gfx.compute_ring[i]);
2198 if (r)
2199 return r;
2200 }
2201
2202 return 0;
2203}
2204
2205static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
2206{
2207 gfx_v6_0_cp_gfx_enable(adev, enable);
2208}
2209
2210static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
2211{
2212 return gfx_v6_0_cp_gfx_load_microcode(adev);
2213}
2214
2215static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2216 bool enable)
2217{
2218 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2219 u32 mask;
2220 int i;
2221
2222 if (enable)
2223 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2224 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2225 else
2226 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2227 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2228 WREG32(mmCP_INT_CNTL_RING0, tmp);
2229
2230 if (!enable) {
2231 /* read a gfx register */
2232 tmp = RREG32(mmDB_DEPTH_INFO);
2233
2234 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
2235 for (i = 0; i < adev->usec_timeout; i++) {
2236 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
2237 break;
2238 udelay(1);
2239 }
2240 }
2241}
2242
2243static int gfx_v6_0_cp_resume(struct amdgpu_device *adev)
2244{
2245 int r;
2246
2247 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2248
2249 r = gfx_v6_0_cp_load_microcode(adev);
2250 if (r)
2251 return r;
2252
2253 r = gfx_v6_0_cp_gfx_resume(adev);
2254 if (r)
2255 return r;
2256 r = gfx_v6_0_cp_compute_resume(adev);
2257 if (r)
2258 return r;
2259
2260 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2261
2262 return 0;
2263}
2264
2265static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2266{
2267 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2268 uint32_t seq = ring->fence_drv.sync_seq;
2269 uint64_t addr = ring->fence_drv.gpu_addr;
2270
2271 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2272 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
2273 WAIT_REG_MEM_FUNCTION(3) | /* equal */
2274 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
2275 amdgpu_ring_write(ring, addr & 0xfffffffc);
2276 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
2277 amdgpu_ring_write(ring, seq);
2278 amdgpu_ring_write(ring, 0xffffffff);
2279 amdgpu_ring_write(ring, 4); /* poll interval */
2280
2281 if (usepfp) {
2282 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2283 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2284 amdgpu_ring_write(ring, 0);
2285 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2286 amdgpu_ring_write(ring, 0);
2287 }
2288}
2289
2290static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2291 unsigned vmid, uint64_t pd_addr)
2292{
2293 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2294
2295 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
2296
2297 /* wait for the invalidate to complete */
2298 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2299 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
2300 WAIT_REG_MEM_ENGINE(0))); /* me */
2301 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
2302 amdgpu_ring_write(ring, 0);
2303 amdgpu_ring_write(ring, 0); /* ref */
2304 amdgpu_ring_write(ring, 0); /* mask */
2305 amdgpu_ring_write(ring, 0x20); /* poll interval */
2306
2307 if (usepfp) {
2308 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2309 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2310 amdgpu_ring_write(ring, 0x0);
2311
2312 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2313 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2314 amdgpu_ring_write(ring, 0);
2315 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2316 amdgpu_ring_write(ring, 0);
2317 }
2318}
2319
2320static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
2321 uint32_t reg, uint32_t val)
2322{
2323 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2324
2325 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2326 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
2327 WRITE_DATA_DST_SEL(0)));
2328 amdgpu_ring_write(ring, reg);
2329 amdgpu_ring_write(ring, 0);
2330 amdgpu_ring_write(ring, val);
2331}
2332
2333static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2334{
2335 const u32 *src_ptr;
2336 volatile u32 *dst_ptr;
2337 u32 dws;
2338 u64 reg_list_mc_addr;
2339 const struct cs_section_def *cs_data;
2340 int r;
2341
2342 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list;
2343 adev->gfx.rlc.reg_list_size =
2344 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
2345
2346 adev->gfx.rlc.cs_data = si_cs_data;
2347 src_ptr = adev->gfx.rlc.reg_list;
2348 dws = adev->gfx.rlc.reg_list_size;
2349 cs_data = adev->gfx.rlc.cs_data;
2350
2351 if (src_ptr) {
2352 /* init save restore block */
2353 r = amdgpu_gfx_rlc_init_sr(adev, dws);
2354 if (r)
2355 return r;
2356 }
2357
2358 if (cs_data) {
2359 /* clear state block */
2360 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev);
2361 dws = adev->gfx.rlc.clear_state_size + (256 / 4);
2362
2363 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
2364 AMDGPU_GEM_DOMAIN_VRAM |
2365 AMDGPU_GEM_DOMAIN_GTT,
2366 &adev->gfx.rlc.clear_state_obj,
2367 &adev->gfx.rlc.clear_state_gpu_addr,
2368 (void **)&adev->gfx.rlc.cs_ptr);
2369 if (r) {
2370 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
2371 amdgpu_gfx_rlc_fini(adev);
2372 return r;
2373 }
2374
2375 /* set up the cs buffer */
2376 dst_ptr = adev->gfx.rlc.cs_ptr;
2377 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256;
2378 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));
2379 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
2380 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size);
2381 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]);
2382 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
2383 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2384 }
2385
2386 return 0;
2387}
2388
2389static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
2390{
2391 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
2392
2393 if (!enable) {
2394 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
2395 WREG32(mmSPI_LB_CU_MASK, 0x00ff);
2396 }
2397}
2398
2399static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2400{
2401 int i;
2402
2403 for (i = 0; i < adev->usec_timeout; i++) {
2404 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0)
2405 break;
2406 udelay(1);
2407 }
2408
2409 for (i = 0; i < adev->usec_timeout; i++) {
2410 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0)
2411 break;
2412 udelay(1);
2413 }
2414}
2415
2416static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
2417{
2418 u32 tmp;
2419
2420 tmp = RREG32(mmRLC_CNTL);
2421 if (tmp != rlc)
2422 WREG32(mmRLC_CNTL, rlc);
2423}
2424
2425static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2426{
2427 u32 data, orig;
2428
2429 orig = data = RREG32(mmRLC_CNTL);
2430
2431 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2432 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
2433 WREG32(mmRLC_CNTL, data);
2434
2435 gfx_v6_0_wait_for_rlc_serdes(adev);
2436 }
2437
2438 return orig;
2439}
2440
2441static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2442{
2443 WREG32(mmRLC_CNTL, 0);
2444
2445 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2446 gfx_v6_0_wait_for_rlc_serdes(adev);
2447}
2448
2449static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2450{
2451 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
2452
2453 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2454
2455 udelay(50);
2456}
2457
2458static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev)
2459{
2460 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2461 udelay(50);
2462 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2463 udelay(50);
2464}
2465
2466static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev)
2467{
2468 u32 tmp;
2469
2470 /* Enable LBPW only for DDR3 */
2471 tmp = RREG32(mmMC_SEQ_MISC0);
2472 if ((tmp & 0xF0000000) == 0xB0000000)
2473 return true;
2474 return false;
2475}
2476
2477static void gfx_v6_0_init_cg(struct amdgpu_device *adev)
2478{
2479}
2480
2481static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2482{
2483 u32 i;
2484 const struct rlc_firmware_header_v1_0 *hdr;
2485 const __le32 *fw_data;
2486 u32 fw_size;
2487
2488
2489 if (!adev->gfx.rlc_fw)
2490 return -EINVAL;
2491
2492 adev->gfx.rlc.funcs->stop(adev);
2493 adev->gfx.rlc.funcs->reset(adev);
2494 gfx_v6_0_init_pg(adev);
2495 gfx_v6_0_init_cg(adev);
2496
2497 WREG32(mmRLC_RL_BASE, 0);
2498 WREG32(mmRLC_RL_SIZE, 0);
2499 WREG32(mmRLC_LB_CNTL, 0);
2500 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff);
2501 WREG32(mmRLC_LB_CNTR_INIT, 0);
2502 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
2503
2504 WREG32(mmRLC_MC_CNTL, 0);
2505 WREG32(mmRLC_UCODE_CNTL, 0);
2506
2507 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
2508 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2509 fw_data = (const __le32 *)
2510 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2511
2512 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2513
2514 for (i = 0; i < fw_size; i++) {
2515 WREG32(mmRLC_UCODE_ADDR, i);
2516 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++));
2517 }
2518 WREG32(mmRLC_UCODE_ADDR, 0);
2519
2520 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
2521 adev->gfx.rlc.funcs->start(adev);
2522
2523 return 0;
2524}
2525
2526static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
2527{
2528 u32 data, orig, tmp;
2529
2530 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
2531
2532 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2533 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2534
2535 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080);
2536
2537 tmp = gfx_v6_0_halt_rlc(adev);
2538
2539 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2540 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2541 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff);
2542
2543 gfx_v6_0_wait_for_rlc_serdes(adev);
2544 gfx_v6_0_update_rlc(adev, tmp);
2545
2546 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff);
2547
2548 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2549 } else {
2550 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2551
2552 RREG32(mmCB_CGTT_SCLK_CTRL);
2553 RREG32(mmCB_CGTT_SCLK_CTRL);
2554 RREG32(mmCB_CGTT_SCLK_CTRL);
2555 RREG32(mmCB_CGTT_SCLK_CTRL);
2556
2557 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2558 }
2559
2560 if (orig != data)
2561 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
2562
2563}
2564
2565static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
2566{
2567
2568 u32 data, orig, tmp = 0;
2569
2570 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2571 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2572 data = 0x96940200;
2573 if (orig != data)
2574 WREG32(mmCGTS_SM_CTRL_REG, data);
2575
2576 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2577 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
2578 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2579 if (orig != data)
2580 WREG32(mmCP_MEM_SLP_CNTL, data);
2581 }
2582
2583 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2584 data &= 0xffffffc0;
2585 if (orig != data)
2586 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2587
2588 tmp = gfx_v6_0_halt_rlc(adev);
2589
2590 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2591 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2592 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff);
2593
2594 gfx_v6_0_update_rlc(adev, tmp);
2595 } else {
2596 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2597 data |= 0x00000003;
2598 if (orig != data)
2599 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2600
2601 data = RREG32(mmCP_MEM_SLP_CNTL);
2602 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2603 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2604 WREG32(mmCP_MEM_SLP_CNTL, data);
2605 }
2606 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2607 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK;
2608 if (orig != data)
2609 WREG32(mmCGTS_SM_CTRL_REG, data);
2610
2611 tmp = gfx_v6_0_halt_rlc(adev);
2612
2613 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2614 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2615 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff);
2616
2617 gfx_v6_0_update_rlc(adev, tmp);
2618 }
2619}
2620/*
2621static void gfx_v6_0_update_cg(struct amdgpu_device *adev,
2622 bool enable)
2623{
2624 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2625 if (enable) {
2626 gfx_v6_0_enable_mgcg(adev, true);
2627 gfx_v6_0_enable_cgcg(adev, true);
2628 } else {
2629 gfx_v6_0_enable_cgcg(adev, false);
2630 gfx_v6_0_enable_mgcg(adev, false);
2631 }
2632 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2633}
2634*/
2635
2636static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
2637 bool enable)
2638{
2639}
2640
2641static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
2642 bool enable)
2643{
2644}
2645
2646static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
2647{
2648 u32 data, orig;
2649
2650 orig = data = RREG32(mmRLC_PG_CNTL);
2651 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
2652 data &= ~0x8000;
2653 else
2654 data |= 0x8000;
2655 if (orig != data)
2656 WREG32(mmRLC_PG_CNTL, data);
2657}
2658
2659static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
2660{
2661}
2662/*
2663static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev)
2664{
2665 const __le32 *fw_data;
2666 volatile u32 *dst_ptr;
2667 int me, i, max_me = 4;
2668 u32 bo_offset = 0;
2669 u32 table_offset, table_size;
2670
2671 if (adev->asic_type == CHIP_KAVERI)
2672 max_me = 5;
2673
2674 if (adev->gfx.rlc.cp_table_ptr == NULL)
2675 return;
2676
2677 dst_ptr = adev->gfx.rlc.cp_table_ptr;
2678 for (me = 0; me < max_me; me++) {
2679 if (me == 0) {
2680 const struct gfx_firmware_header_v1_0 *hdr =
2681 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2682 fw_data = (const __le32 *)
2683 (adev->gfx.ce_fw->data +
2684 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2685 table_offset = le32_to_cpu(hdr->jt_offset);
2686 table_size = le32_to_cpu(hdr->jt_size);
2687 } else if (me == 1) {
2688 const struct gfx_firmware_header_v1_0 *hdr =
2689 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2690 fw_data = (const __le32 *)
2691 (adev->gfx.pfp_fw->data +
2692 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2693 table_offset = le32_to_cpu(hdr->jt_offset);
2694 table_size = le32_to_cpu(hdr->jt_size);
2695 } else if (me == 2) {
2696 const struct gfx_firmware_header_v1_0 *hdr =
2697 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2698 fw_data = (const __le32 *)
2699 (adev->gfx.me_fw->data +
2700 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2701 table_offset = le32_to_cpu(hdr->jt_offset);
2702 table_size = le32_to_cpu(hdr->jt_size);
2703 } else if (me == 3) {
2704 const struct gfx_firmware_header_v1_0 *hdr =
2705 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2706 fw_data = (const __le32 *)
2707 (adev->gfx.mec_fw->data +
2708 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2709 table_offset = le32_to_cpu(hdr->jt_offset);
2710 table_size = le32_to_cpu(hdr->jt_size);
2711 } else {
2712 const struct gfx_firmware_header_v1_0 *hdr =
2713 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2714 fw_data = (const __le32 *)
2715 (adev->gfx.mec2_fw->data +
2716 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2717 table_offset = le32_to_cpu(hdr->jt_offset);
2718 table_size = le32_to_cpu(hdr->jt_size);
2719 }
2720
2721 for (i = 0; i < table_size; i ++) {
2722 dst_ptr[bo_offset + i] =
2723 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
2724 }
2725
2726 bo_offset += table_size;
2727 }
2728}
2729*/
2730static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev,
2731 bool enable)
2732{
2733 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2734 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10));
2735 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1);
2736 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1);
2737 } else {
2738 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0);
2739 (void)RREG32(mmDB_RENDER_CONTROL);
2740 }
2741}
2742
2743static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev)
2744{
2745 u32 tmp;
2746
2747 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
2748
2749 tmp = RREG32(mmRLC_MAX_PG_CU);
2750 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
2751 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
2752 WREG32(mmRLC_MAX_PG_CU, tmp);
2753}
2754
2755static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
2756 bool enable)
2757{
2758 u32 data, orig;
2759
2760 orig = data = RREG32(mmRLC_PG_CNTL);
2761 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
2762 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2763 else
2764 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2765 if (orig != data)
2766 WREG32(mmRLC_PG_CNTL, data);
2767}
2768
2769static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
2770 bool enable)
2771{
2772 u32 data, orig;
2773
2774 orig = data = RREG32(mmRLC_PG_CNTL);
2775 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
2776 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2777 else
2778 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2779 if (orig != data)
2780 WREG32(mmRLC_PG_CNTL, data);
2781}
2782
2783static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev)
2784{
2785 u32 tmp;
2786
2787 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2788 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1);
2789 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2790
2791 tmp = RREG32(mmRLC_AUTO_PG_CTRL);
2792 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2793 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2794 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK;
2795 WREG32(mmRLC_AUTO_PG_CTRL, tmp);
2796}
2797
2798static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
2799{
2800 gfx_v6_0_enable_gfx_cgpg(adev, enable);
2801 gfx_v6_0_enable_gfx_static_mgpg(adev, enable);
2802 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable);
2803}
2804
2805static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev)
2806{
2807 u32 count = 0;
2808 const struct cs_section_def *sect = NULL;
2809 const struct cs_extent_def *ext = NULL;
2810
2811 if (adev->gfx.rlc.cs_data == NULL)
2812 return 0;
2813
2814 /* begin clear state */
2815 count += 2;
2816 /* context control state */
2817 count += 3;
2818
2819 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2820 for (ext = sect->section; ext->extent != NULL; ++ext) {
2821 if (sect->id == SECT_CONTEXT)
2822 count += 2 + ext->reg_count;
2823 else
2824 return 0;
2825 }
2826 }
2827 /* pa_sc_raster_config */
2828 count += 3;
2829 /* end clear state */
2830 count += 2;
2831 /* clear state */
2832 count += 2;
2833
2834 return count;
2835}
2836
2837static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
2838 volatile u32 *buffer)
2839{
2840 u32 count = 0, i;
2841 const struct cs_section_def *sect = NULL;
2842 const struct cs_extent_def *ext = NULL;
2843
2844 if (adev->gfx.rlc.cs_data == NULL)
2845 return;
2846 if (buffer == NULL)
2847 return;
2848
2849 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2850 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2851 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2852 buffer[count++] = cpu_to_le32(0x80000000);
2853 buffer[count++] = cpu_to_le32(0x80000000);
2854
2855 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2856 for (ext = sect->section; ext->extent != NULL; ++ext) {
2857 if (sect->id == SECT_CONTEXT) {
2858 buffer[count++] =
2859 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2860 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
2861 for (i = 0; i < ext->reg_count; i++)
2862 buffer[count++] = cpu_to_le32(ext->extent[i]);
2863 } else {
2864 return;
2865 }
2866 }
2867 }
2868
2869 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2870 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2871 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);
2872
2873 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2874 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
2875
2876 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
2877 buffer[count++] = cpu_to_le32(0);
2878}
2879
2880static void gfx_v6_0_init_pg(struct amdgpu_device *adev)
2881{
2882 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2883 AMD_PG_SUPPORT_GFX_SMG |
2884 AMD_PG_SUPPORT_GFX_DMG |
2885 AMD_PG_SUPPORT_CP |
2886 AMD_PG_SUPPORT_GDS |
2887 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2888 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true);
2889 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true);
2890 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2891 gfx_v6_0_init_gfx_cgpg(adev);
2892 gfx_v6_0_enable_cp_pg(adev, true);
2893 gfx_v6_0_enable_gds_pg(adev, true);
2894 } else {
2895 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2896 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2897
2898 }
2899 gfx_v6_0_init_ao_cu_mask(adev);
2900 gfx_v6_0_update_gfx_pg(adev, true);
2901 } else {
2902
2903 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2904 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2905 }
2906}
2907
2908static void gfx_v6_0_fini_pg(struct amdgpu_device *adev)
2909{
2910 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2911 AMD_PG_SUPPORT_GFX_SMG |
2912 AMD_PG_SUPPORT_GFX_DMG |
2913 AMD_PG_SUPPORT_CP |
2914 AMD_PG_SUPPORT_GDS |
2915 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2916 gfx_v6_0_update_gfx_pg(adev, false);
2917 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2918 gfx_v6_0_enable_cp_pg(adev, false);
2919 gfx_v6_0_enable_gds_pg(adev, false);
2920 }
2921 }
2922}
2923
2924static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2925{
2926 uint64_t clock;
2927
2928 mutex_lock(&adev->gfx.gpu_clock_mutex);
2929 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
2930 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
2931 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
2932 mutex_unlock(&adev->gfx.gpu_clock_mutex);
2933 return clock;
2934}
2935
2936static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2937{
2938 if (flags & AMDGPU_HAVE_CTX_SWITCH)
2939 gfx_v6_0_ring_emit_vgt_flush(ring);
2940 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2941 amdgpu_ring_write(ring, 0x80000000);
2942 amdgpu_ring_write(ring, 0);
2943}
2944
2945
2946static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
2947{
2948 WREG32(mmSQ_IND_INDEX,
2949 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
2950 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
2951 (address << SQ_IND_INDEX__INDEX__SHIFT) |
2952 (SQ_IND_INDEX__FORCE_READ_MASK));
2953 return RREG32(mmSQ_IND_DATA);
2954}
2955
2956static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
2957 uint32_t wave, uint32_t thread,
2958 uint32_t regno, uint32_t num, uint32_t *out)
2959{
2960 WREG32(mmSQ_IND_INDEX,
2961 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
2962 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
2963 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
2964 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
2965 (SQ_IND_INDEX__FORCE_READ_MASK) |
2966 (SQ_IND_INDEX__AUTO_INCR_MASK));
2967 while (num--)
2968 *(out++) = RREG32(mmSQ_IND_DATA);
2969}
2970
2971static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
2972{
2973 /* type 0 wave data */
2974 dst[(*no_fields)++] = 0;
2975 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
2976 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
2977 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
2978 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
2979 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
2980 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
2981 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
2982 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
2983 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
2984 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
2985 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
2986 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
2987 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
2988 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
2989 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
2990 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
2991 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
2992 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
2993 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE);
2994}
2995
2996static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
2997 uint32_t wave, uint32_t start,
2998 uint32_t size, uint32_t *dst)
2999{
3000 wave_read_regs(
3001 adev, simd, wave, 0,
3002 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
3003}
3004
3005static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev,
3006 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
3007{
3008 DRM_INFO("Not implemented\n");
3009}
3010
3011static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
3012 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
3013 .select_se_sh = &gfx_v6_0_select_se_sh,
3014 .read_wave_data = &gfx_v6_0_read_wave_data,
3015 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs,
3016 .select_me_pipe_q = &gfx_v6_0_select_me_pipe_q
3017};
3018
3019static const struct amdgpu_rlc_funcs gfx_v6_0_rlc_funcs = {
3020 .init = gfx_v6_0_rlc_init,
3021 .resume = gfx_v6_0_rlc_resume,
3022 .stop = gfx_v6_0_rlc_stop,
3023 .reset = gfx_v6_0_rlc_reset,
3024 .start = gfx_v6_0_rlc_start
3025};
3026
3027static int gfx_v6_0_early_init(void *handle)
3028{
3029 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3030
3031 adev->gfx.xcc_mask = 1;
3032 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
3033 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
3034 GFX6_NUM_COMPUTE_RINGS);
3035 adev->gfx.funcs = &gfx_v6_0_gfx_funcs;
3036 adev->gfx.rlc.funcs = &gfx_v6_0_rlc_funcs;
3037 gfx_v6_0_set_ring_funcs(adev);
3038 gfx_v6_0_set_irq_funcs(adev);
3039
3040 return 0;
3041}
3042
3043static int gfx_v6_0_sw_init(void *handle)
3044{
3045 struct amdgpu_ring *ring;
3046 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3047 int i, r;
3048
3049 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
3050 if (r)
3051 return r;
3052
3053 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq);
3054 if (r)
3055 return r;
3056
3057 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq);
3058 if (r)
3059 return r;
3060
3061 r = gfx_v6_0_init_microcode(adev);
3062 if (r) {
3063 DRM_ERROR("Failed to load gfx firmware!\n");
3064 return r;
3065 }
3066
3067 r = adev->gfx.rlc.funcs->init(adev);
3068 if (r) {
3069 DRM_ERROR("Failed to init rlc BOs!\n");
3070 return r;
3071 }
3072
3073 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3074 ring = &adev->gfx.gfx_ring[i];
3075 ring->ring_obj = NULL;
3076 sprintf(ring->name, "gfx");
3077 r = amdgpu_ring_init(adev, ring, 2048,
3078 &adev->gfx.eop_irq,
3079 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP,
3080 AMDGPU_RING_PRIO_DEFAULT, NULL);
3081 if (r)
3082 return r;
3083 }
3084
3085 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3086 unsigned irq_type;
3087
3088 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
3089 DRM_ERROR("Too many (%d) compute rings!\n", i);
3090 break;
3091 }
3092 ring = &adev->gfx.compute_ring[i];
3093 ring->ring_obj = NULL;
3094 ring->use_doorbell = false;
3095 ring->doorbell_index = 0;
3096 ring->me = 1;
3097 ring->pipe = i;
3098 ring->queue = i;
3099 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
3100 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
3101 r = amdgpu_ring_init(adev, ring, 1024,
3102 &adev->gfx.eop_irq, irq_type,
3103 AMDGPU_RING_PRIO_DEFAULT, NULL);
3104 if (r)
3105 return r;
3106 }
3107
3108 return r;
3109}
3110
3111static int gfx_v6_0_sw_fini(void *handle)
3112{
3113 int i;
3114 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3115
3116 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3117 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
3118 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3119 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
3120
3121 amdgpu_gfx_rlc_fini(adev);
3122
3123 return 0;
3124}
3125
3126static int gfx_v6_0_hw_init(void *handle)
3127{
3128 int r;
3129 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3130
3131 gfx_v6_0_constants_init(adev);
3132
3133 r = adev->gfx.rlc.funcs->resume(adev);
3134 if (r)
3135 return r;
3136
3137 r = gfx_v6_0_cp_resume(adev);
3138 if (r)
3139 return r;
3140
3141 adev->gfx.ce_ram_size = 0x8000;
3142
3143 return r;
3144}
3145
3146static int gfx_v6_0_hw_fini(void *handle)
3147{
3148 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3149
3150 gfx_v6_0_cp_enable(adev, false);
3151 adev->gfx.rlc.funcs->stop(adev);
3152 gfx_v6_0_fini_pg(adev);
3153
3154 return 0;
3155}
3156
3157static int gfx_v6_0_suspend(void *handle)
3158{
3159 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3160
3161 return gfx_v6_0_hw_fini(adev);
3162}
3163
3164static int gfx_v6_0_resume(void *handle)
3165{
3166 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3167
3168 return gfx_v6_0_hw_init(adev);
3169}
3170
3171static bool gfx_v6_0_is_idle(void *handle)
3172{
3173 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3174
3175 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
3176 return false;
3177 else
3178 return true;
3179}
3180
3181static int gfx_v6_0_wait_for_idle(void *handle)
3182{
3183 unsigned i;
3184 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3185
3186 for (i = 0; i < adev->usec_timeout; i++) {
3187 if (gfx_v6_0_is_idle(handle))
3188 return 0;
3189 udelay(1);
3190 }
3191 return -ETIMEDOUT;
3192}
3193
3194static int gfx_v6_0_soft_reset(void *handle)
3195{
3196 return 0;
3197}
3198
3199static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3200 enum amdgpu_interrupt_state state)
3201{
3202 u32 cp_int_cntl;
3203
3204 switch (state) {
3205 case AMDGPU_IRQ_STATE_DISABLE:
3206 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3207 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3208 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3209 break;
3210 case AMDGPU_IRQ_STATE_ENABLE:
3211 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3212 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3213 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3214 break;
3215 default:
3216 break;
3217 }
3218}
3219
3220static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3221 int ring,
3222 enum amdgpu_interrupt_state state)
3223{
3224 u32 cp_int_cntl;
3225 switch (state){
3226 case AMDGPU_IRQ_STATE_DISABLE:
3227 if (ring == 0) {
3228 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3229 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3230 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3231 break;
3232 } else {
3233 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3234 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3235 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3236 break;
3237
3238 }
3239 case AMDGPU_IRQ_STATE_ENABLE:
3240 if (ring == 0) {
3241 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3242 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3243 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3244 break;
3245 } else {
3246 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3247 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3248 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3249 break;
3250
3251 }
3252
3253 default:
3254 BUG();
3255 break;
3256
3257 }
3258}
3259
3260static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3261 struct amdgpu_irq_src *src,
3262 unsigned type,
3263 enum amdgpu_interrupt_state state)
3264{
3265 u32 cp_int_cntl;
3266
3267 switch (state) {
3268 case AMDGPU_IRQ_STATE_DISABLE:
3269 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3270 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3271 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3272 break;
3273 case AMDGPU_IRQ_STATE_ENABLE:
3274 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3275 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3276 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3277 break;
3278 default:
3279 break;
3280 }
3281
3282 return 0;
3283}
3284
3285static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3286 struct amdgpu_irq_src *src,
3287 unsigned type,
3288 enum amdgpu_interrupt_state state)
3289{
3290 u32 cp_int_cntl;
3291
3292 switch (state) {
3293 case AMDGPU_IRQ_STATE_DISABLE:
3294 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3295 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3296 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3297 break;
3298 case AMDGPU_IRQ_STATE_ENABLE:
3299 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3300 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3301 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3302 break;
3303 default:
3304 break;
3305 }
3306
3307 return 0;
3308}
3309
3310static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3311 struct amdgpu_irq_src *src,
3312 unsigned type,
3313 enum amdgpu_interrupt_state state)
3314{
3315 switch (type) {
3316 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
3317 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state);
3318 break;
3319 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3320 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state);
3321 break;
3322 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3323 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state);
3324 break;
3325 default:
3326 break;
3327 }
3328 return 0;
3329}
3330
3331static int gfx_v6_0_eop_irq(struct amdgpu_device *adev,
3332 struct amdgpu_irq_src *source,
3333 struct amdgpu_iv_entry *entry)
3334{
3335 switch (entry->ring_id) {
3336 case 0:
3337 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3338 break;
3339 case 1:
3340 case 2:
3341 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]);
3342 break;
3343 default:
3344 break;
3345 }
3346 return 0;
3347}
3348
3349static void gfx_v6_0_fault(struct amdgpu_device *adev,
3350 struct amdgpu_iv_entry *entry)
3351{
3352 struct amdgpu_ring *ring;
3353
3354 switch (entry->ring_id) {
3355 case 0:
3356 ring = &adev->gfx.gfx_ring[0];
3357 break;
3358 case 1:
3359 case 2:
3360 ring = &adev->gfx.compute_ring[entry->ring_id - 1];
3361 break;
3362 default:
3363 return;
3364 }
3365 drm_sched_fault(&ring->sched);
3366}
3367
3368static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev,
3369 struct amdgpu_irq_src *source,
3370 struct amdgpu_iv_entry *entry)
3371{
3372 DRM_ERROR("Illegal register access in command stream\n");
3373 gfx_v6_0_fault(adev, entry);
3374 return 0;
3375}
3376
3377static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev,
3378 struct amdgpu_irq_src *source,
3379 struct amdgpu_iv_entry *entry)
3380{
3381 DRM_ERROR("Illegal instruction in command stream\n");
3382 gfx_v6_0_fault(adev, entry);
3383 return 0;
3384}
3385
3386static int gfx_v6_0_set_clockgating_state(void *handle,
3387 enum amd_clockgating_state state)
3388{
3389 bool gate = false;
3390 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3391
3392 if (state == AMD_CG_STATE_GATE)
3393 gate = true;
3394
3395 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
3396 if (gate) {
3397 gfx_v6_0_enable_mgcg(adev, true);
3398 gfx_v6_0_enable_cgcg(adev, true);
3399 } else {
3400 gfx_v6_0_enable_cgcg(adev, false);
3401 gfx_v6_0_enable_mgcg(adev, false);
3402 }
3403 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
3404
3405 return 0;
3406}
3407
3408static int gfx_v6_0_set_powergating_state(void *handle,
3409 enum amd_powergating_state state)
3410{
3411 bool gate = false;
3412 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3413
3414 if (state == AMD_PG_STATE_GATE)
3415 gate = true;
3416
3417 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3418 AMD_PG_SUPPORT_GFX_SMG |
3419 AMD_PG_SUPPORT_GFX_DMG |
3420 AMD_PG_SUPPORT_CP |
3421 AMD_PG_SUPPORT_GDS |
3422 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3423 gfx_v6_0_update_gfx_pg(adev, gate);
3424 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3425 gfx_v6_0_enable_cp_pg(adev, gate);
3426 gfx_v6_0_enable_gds_pg(adev, gate);
3427 }
3428 }
3429
3430 return 0;
3431}
3432
3433static void gfx_v6_0_emit_mem_sync(struct amdgpu_ring *ring)
3434{
3435 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3436 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
3437 PACKET3_TC_ACTION_ENA |
3438 PACKET3_SH_KCACHE_ACTION_ENA |
3439 PACKET3_SH_ICACHE_ACTION_ENA); /* CP_COHER_CNTL */
3440 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
3441 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
3442 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */
3443}
3444
3445static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
3446 .name = "gfx_v6_0",
3447 .early_init = gfx_v6_0_early_init,
3448 .late_init = NULL,
3449 .sw_init = gfx_v6_0_sw_init,
3450 .sw_fini = gfx_v6_0_sw_fini,
3451 .hw_init = gfx_v6_0_hw_init,
3452 .hw_fini = gfx_v6_0_hw_fini,
3453 .suspend = gfx_v6_0_suspend,
3454 .resume = gfx_v6_0_resume,
3455 .is_idle = gfx_v6_0_is_idle,
3456 .wait_for_idle = gfx_v6_0_wait_for_idle,
3457 .soft_reset = gfx_v6_0_soft_reset,
3458 .set_clockgating_state = gfx_v6_0_set_clockgating_state,
3459 .set_powergating_state = gfx_v6_0_set_powergating_state,
3460};
3461
3462static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
3463 .type = AMDGPU_RING_TYPE_GFX,
3464 .align_mask = 0xff,
3465 .nop = 0x80000000,
3466 .support_64bit_ptrs = false,
3467 .get_rptr = gfx_v6_0_ring_get_rptr,
3468 .get_wptr = gfx_v6_0_ring_get_wptr,
3469 .set_wptr = gfx_v6_0_ring_set_wptr_gfx,
3470 .emit_frame_size =
3471 5 + 5 + /* hdp flush / invalidate */
3472 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3473 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
3474 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
3475 3 + 2 + /* gfx_v6_ring_emit_cntxcntl including vgt flush */
3476 5, /* SURFACE_SYNC */
3477 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3478 .emit_ib = gfx_v6_0_ring_emit_ib,
3479 .emit_fence = gfx_v6_0_ring_emit_fence,
3480 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3481 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3482 .test_ring = gfx_v6_0_ring_test_ring,
3483 .test_ib = gfx_v6_0_ring_test_ib,
3484 .insert_nop = amdgpu_ring_insert_nop,
3485 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
3486 .emit_wreg = gfx_v6_0_ring_emit_wreg,
3487 .emit_mem_sync = gfx_v6_0_emit_mem_sync,
3488};
3489
3490static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
3491 .type = AMDGPU_RING_TYPE_COMPUTE,
3492 .align_mask = 0xff,
3493 .nop = 0x80000000,
3494 .get_rptr = gfx_v6_0_ring_get_rptr,
3495 .get_wptr = gfx_v6_0_ring_get_wptr,
3496 .set_wptr = gfx_v6_0_ring_set_wptr_compute,
3497 .emit_frame_size =
3498 5 + 5 + /* hdp flush / invalidate */
3499 7 + /* gfx_v6_0_ring_emit_pipeline_sync */
3500 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */
3501 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3502 5, /* SURFACE_SYNC */
3503 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3504 .emit_ib = gfx_v6_0_ring_emit_ib,
3505 .emit_fence = gfx_v6_0_ring_emit_fence,
3506 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3507 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3508 .test_ring = gfx_v6_0_ring_test_ring,
3509 .test_ib = gfx_v6_0_ring_test_ib,
3510 .insert_nop = amdgpu_ring_insert_nop,
3511 .emit_wreg = gfx_v6_0_ring_emit_wreg,
3512 .emit_mem_sync = gfx_v6_0_emit_mem_sync,
3513};
3514
3515static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)
3516{
3517 int i;
3518
3519 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3520 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx;
3521 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3522 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute;
3523}
3524
3525static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = {
3526 .set = gfx_v6_0_set_eop_interrupt_state,
3527 .process = gfx_v6_0_eop_irq,
3528};
3529
3530static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = {
3531 .set = gfx_v6_0_set_priv_reg_fault_state,
3532 .process = gfx_v6_0_priv_reg_irq,
3533};
3534
3535static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = {
3536 .set = gfx_v6_0_set_priv_inst_fault_state,
3537 .process = gfx_v6_0_priv_inst_irq,
3538};
3539
3540static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3541{
3542 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3543 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs;
3544
3545 adev->gfx.priv_reg_irq.num_types = 1;
3546 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs;
3547
3548 adev->gfx.priv_inst_irq.num_types = 1;
3549 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs;
3550}
3551
3552static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
3553{
3554 int i, j, k, counter, active_cu_number = 0;
3555 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3556 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
3557 unsigned disable_masks[4 * 2];
3558 u32 ao_cu_num;
3559
3560 if (adev->flags & AMD_IS_APU)
3561 ao_cu_num = 2;
3562 else
3563 ao_cu_num = adev->gfx.config.max_cu_per_sh;
3564
3565 memset(cu_info, 0, sizeof(*cu_info));
3566
3567 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
3568
3569 mutex_lock(&adev->grbm_idx_mutex);
3570 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3571 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3572 mask = 1;
3573 ao_bitmap = 0;
3574 counter = 0;
3575 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0);
3576 if (i < 4 && j < 2)
3577 gfx_v6_0_set_user_cu_inactive_bitmap(
3578 adev, disable_masks[i * 2 + j]);
3579 bitmap = gfx_v6_0_get_cu_enabled(adev);
3580 cu_info->bitmap[0][i][j] = bitmap;
3581
3582 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
3583 if (bitmap & mask) {
3584 if (counter < ao_cu_num)
3585 ao_bitmap |= mask;
3586 counter ++;
3587 }
3588 mask <<= 1;
3589 }
3590 active_cu_number += counter;
3591 if (i < 2 && j < 2)
3592 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3593 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
3594 }
3595 }
3596
3597 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
3598 mutex_unlock(&adev->grbm_idx_mutex);
3599
3600 cu_info->number = active_cu_number;
3601 cu_info->ao_cu_mask = ao_cu_mask;
3602}
3603
3604const struct amdgpu_ip_block_version gfx_v6_0_ip_block =
3605{
3606 .type = AMD_IP_BLOCK_TYPE_GFX,
3607 .major = 6,
3608 .minor = 0,
3609 .rev = 0,
3610 .funcs = &gfx_v6_0_ip_funcs,
3611};