Loading...
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include "amdgpu.h"
25#include "amdgpu_ih.h"
26#include "amdgpu_gfx.h"
27#include "amdgpu_ucode.h"
28#include "clearstate_si.h"
29#include "bif/bif_3_0_d.h"
30#include "bif/bif_3_0_sh_mask.h"
31#include "oss/oss_1_0_d.h"
32#include "oss/oss_1_0_sh_mask.h"
33#include "gca/gfx_6_0_d.h"
34#include "gca/gfx_6_0_sh_mask.h"
35#include "gmc/gmc_6_0_d.h"
36#include "gmc/gmc_6_0_sh_mask.h"
37#include "dce/dce_6_0_d.h"
38#include "dce/dce_6_0_sh_mask.h"
39#include "gca/gfx_7_2_enum.h"
40#include "si_enums.h"
41#include "si.h"
42
43static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
44static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
45static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev);
46
47MODULE_FIRMWARE("radeon/tahiti_pfp.bin");
48MODULE_FIRMWARE("radeon/tahiti_me.bin");
49MODULE_FIRMWARE("radeon/tahiti_ce.bin");
50MODULE_FIRMWARE("radeon/tahiti_rlc.bin");
51
52MODULE_FIRMWARE("radeon/pitcairn_pfp.bin");
53MODULE_FIRMWARE("radeon/pitcairn_me.bin");
54MODULE_FIRMWARE("radeon/pitcairn_ce.bin");
55MODULE_FIRMWARE("radeon/pitcairn_rlc.bin");
56
57MODULE_FIRMWARE("radeon/verde_pfp.bin");
58MODULE_FIRMWARE("radeon/verde_me.bin");
59MODULE_FIRMWARE("radeon/verde_ce.bin");
60MODULE_FIRMWARE("radeon/verde_rlc.bin");
61
62MODULE_FIRMWARE("radeon/oland_pfp.bin");
63MODULE_FIRMWARE("radeon/oland_me.bin");
64MODULE_FIRMWARE("radeon/oland_ce.bin");
65MODULE_FIRMWARE("radeon/oland_rlc.bin");
66
67MODULE_FIRMWARE("radeon/hainan_pfp.bin");
68MODULE_FIRMWARE("radeon/hainan_me.bin");
69MODULE_FIRMWARE("radeon/hainan_ce.bin");
70MODULE_FIRMWARE("radeon/hainan_rlc.bin");
71
72static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
73static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
74//static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev);
75static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
76
77#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
78#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
79#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
80#define MICRO_TILE_MODE(x) ((x) << 0)
81#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
82#define BANK_WIDTH(x) ((x) << 14)
83#define BANK_HEIGHT(x) ((x) << 16)
84#define MACRO_TILE_ASPECT(x) ((x) << 18)
85#define NUM_BANKS(x) ((x) << 20)
86
87static const u32 verde_rlc_save_restore_register_list[] =
88{
89 (0x8000 << 16) | (0x98f4 >> 2),
90 0x00000000,
91 (0x8040 << 16) | (0x98f4 >> 2),
92 0x00000000,
93 (0x8000 << 16) | (0xe80 >> 2),
94 0x00000000,
95 (0x8040 << 16) | (0xe80 >> 2),
96 0x00000000,
97 (0x8000 << 16) | (0x89bc >> 2),
98 0x00000000,
99 (0x8040 << 16) | (0x89bc >> 2),
100 0x00000000,
101 (0x8000 << 16) | (0x8c1c >> 2),
102 0x00000000,
103 (0x8040 << 16) | (0x8c1c >> 2),
104 0x00000000,
105 (0x9c00 << 16) | (0x98f0 >> 2),
106 0x00000000,
107 (0x9c00 << 16) | (0xe7c >> 2),
108 0x00000000,
109 (0x8000 << 16) | (0x9148 >> 2),
110 0x00000000,
111 (0x8040 << 16) | (0x9148 >> 2),
112 0x00000000,
113 (0x9c00 << 16) | (0x9150 >> 2),
114 0x00000000,
115 (0x9c00 << 16) | (0x897c >> 2),
116 0x00000000,
117 (0x9c00 << 16) | (0x8d8c >> 2),
118 0x00000000,
119 (0x9c00 << 16) | (0xac54 >> 2),
120 0X00000000,
121 0x3,
122 (0x9c00 << 16) | (0x98f8 >> 2),
123 0x00000000,
124 (0x9c00 << 16) | (0x9910 >> 2),
125 0x00000000,
126 (0x9c00 << 16) | (0x9914 >> 2),
127 0x00000000,
128 (0x9c00 << 16) | (0x9918 >> 2),
129 0x00000000,
130 (0x9c00 << 16) | (0x991c >> 2),
131 0x00000000,
132 (0x9c00 << 16) | (0x9920 >> 2),
133 0x00000000,
134 (0x9c00 << 16) | (0x9924 >> 2),
135 0x00000000,
136 (0x9c00 << 16) | (0x9928 >> 2),
137 0x00000000,
138 (0x9c00 << 16) | (0x992c >> 2),
139 0x00000000,
140 (0x9c00 << 16) | (0x9930 >> 2),
141 0x00000000,
142 (0x9c00 << 16) | (0x9934 >> 2),
143 0x00000000,
144 (0x9c00 << 16) | (0x9938 >> 2),
145 0x00000000,
146 (0x9c00 << 16) | (0x993c >> 2),
147 0x00000000,
148 (0x9c00 << 16) | (0x9940 >> 2),
149 0x00000000,
150 (0x9c00 << 16) | (0x9944 >> 2),
151 0x00000000,
152 (0x9c00 << 16) | (0x9948 >> 2),
153 0x00000000,
154 (0x9c00 << 16) | (0x994c >> 2),
155 0x00000000,
156 (0x9c00 << 16) | (0x9950 >> 2),
157 0x00000000,
158 (0x9c00 << 16) | (0x9954 >> 2),
159 0x00000000,
160 (0x9c00 << 16) | (0x9958 >> 2),
161 0x00000000,
162 (0x9c00 << 16) | (0x995c >> 2),
163 0x00000000,
164 (0x9c00 << 16) | (0x9960 >> 2),
165 0x00000000,
166 (0x9c00 << 16) | (0x9964 >> 2),
167 0x00000000,
168 (0x9c00 << 16) | (0x9968 >> 2),
169 0x00000000,
170 (0x9c00 << 16) | (0x996c >> 2),
171 0x00000000,
172 (0x9c00 << 16) | (0x9970 >> 2),
173 0x00000000,
174 (0x9c00 << 16) | (0x9974 >> 2),
175 0x00000000,
176 (0x9c00 << 16) | (0x9978 >> 2),
177 0x00000000,
178 (0x9c00 << 16) | (0x997c >> 2),
179 0x00000000,
180 (0x9c00 << 16) | (0x9980 >> 2),
181 0x00000000,
182 (0x9c00 << 16) | (0x9984 >> 2),
183 0x00000000,
184 (0x9c00 << 16) | (0x9988 >> 2),
185 0x00000000,
186 (0x9c00 << 16) | (0x998c >> 2),
187 0x00000000,
188 (0x9c00 << 16) | (0x8c00 >> 2),
189 0x00000000,
190 (0x9c00 << 16) | (0x8c14 >> 2),
191 0x00000000,
192 (0x9c00 << 16) | (0x8c04 >> 2),
193 0x00000000,
194 (0x9c00 << 16) | (0x8c08 >> 2),
195 0x00000000,
196 (0x8000 << 16) | (0x9b7c >> 2),
197 0x00000000,
198 (0x8040 << 16) | (0x9b7c >> 2),
199 0x00000000,
200 (0x8000 << 16) | (0xe84 >> 2),
201 0x00000000,
202 (0x8040 << 16) | (0xe84 >> 2),
203 0x00000000,
204 (0x8000 << 16) | (0x89c0 >> 2),
205 0x00000000,
206 (0x8040 << 16) | (0x89c0 >> 2),
207 0x00000000,
208 (0x8000 << 16) | (0x914c >> 2),
209 0x00000000,
210 (0x8040 << 16) | (0x914c >> 2),
211 0x00000000,
212 (0x8000 << 16) | (0x8c20 >> 2),
213 0x00000000,
214 (0x8040 << 16) | (0x8c20 >> 2),
215 0x00000000,
216 (0x8000 << 16) | (0x9354 >> 2),
217 0x00000000,
218 (0x8040 << 16) | (0x9354 >> 2),
219 0x00000000,
220 (0x9c00 << 16) | (0x9060 >> 2),
221 0x00000000,
222 (0x9c00 << 16) | (0x9364 >> 2),
223 0x00000000,
224 (0x9c00 << 16) | (0x9100 >> 2),
225 0x00000000,
226 (0x9c00 << 16) | (0x913c >> 2),
227 0x00000000,
228 (0x8000 << 16) | (0x90e0 >> 2),
229 0x00000000,
230 (0x8000 << 16) | (0x90e4 >> 2),
231 0x00000000,
232 (0x8000 << 16) | (0x90e8 >> 2),
233 0x00000000,
234 (0x8040 << 16) | (0x90e0 >> 2),
235 0x00000000,
236 (0x8040 << 16) | (0x90e4 >> 2),
237 0x00000000,
238 (0x8040 << 16) | (0x90e8 >> 2),
239 0x00000000,
240 (0x9c00 << 16) | (0x8bcc >> 2),
241 0x00000000,
242 (0x9c00 << 16) | (0x8b24 >> 2),
243 0x00000000,
244 (0x9c00 << 16) | (0x88c4 >> 2),
245 0x00000000,
246 (0x9c00 << 16) | (0x8e50 >> 2),
247 0x00000000,
248 (0x9c00 << 16) | (0x8c0c >> 2),
249 0x00000000,
250 (0x9c00 << 16) | (0x8e58 >> 2),
251 0x00000000,
252 (0x9c00 << 16) | (0x8e5c >> 2),
253 0x00000000,
254 (0x9c00 << 16) | (0x9508 >> 2),
255 0x00000000,
256 (0x9c00 << 16) | (0x950c >> 2),
257 0x00000000,
258 (0x9c00 << 16) | (0x9494 >> 2),
259 0x00000000,
260 (0x9c00 << 16) | (0xac0c >> 2),
261 0x00000000,
262 (0x9c00 << 16) | (0xac10 >> 2),
263 0x00000000,
264 (0x9c00 << 16) | (0xac14 >> 2),
265 0x00000000,
266 (0x9c00 << 16) | (0xae00 >> 2),
267 0x00000000,
268 (0x9c00 << 16) | (0xac08 >> 2),
269 0x00000000,
270 (0x9c00 << 16) | (0x88d4 >> 2),
271 0x00000000,
272 (0x9c00 << 16) | (0x88c8 >> 2),
273 0x00000000,
274 (0x9c00 << 16) | (0x88cc >> 2),
275 0x00000000,
276 (0x9c00 << 16) | (0x89b0 >> 2),
277 0x00000000,
278 (0x9c00 << 16) | (0x8b10 >> 2),
279 0x00000000,
280 (0x9c00 << 16) | (0x8a14 >> 2),
281 0x00000000,
282 (0x9c00 << 16) | (0x9830 >> 2),
283 0x00000000,
284 (0x9c00 << 16) | (0x9834 >> 2),
285 0x00000000,
286 (0x9c00 << 16) | (0x9838 >> 2),
287 0x00000000,
288 (0x9c00 << 16) | (0x9a10 >> 2),
289 0x00000000,
290 (0x8000 << 16) | (0x9870 >> 2),
291 0x00000000,
292 (0x8000 << 16) | (0x9874 >> 2),
293 0x00000000,
294 (0x8001 << 16) | (0x9870 >> 2),
295 0x00000000,
296 (0x8001 << 16) | (0x9874 >> 2),
297 0x00000000,
298 (0x8040 << 16) | (0x9870 >> 2),
299 0x00000000,
300 (0x8040 << 16) | (0x9874 >> 2),
301 0x00000000,
302 (0x8041 << 16) | (0x9870 >> 2),
303 0x00000000,
304 (0x8041 << 16) | (0x9874 >> 2),
305 0x00000000,
306 0x00000000
307};
308
309static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
310{
311 const char *chip_name;
312 char fw_name[30];
313 int err;
314 const struct gfx_firmware_header_v1_0 *cp_hdr;
315 const struct rlc_firmware_header_v1_0 *rlc_hdr;
316
317 DRM_DEBUG("\n");
318
319 switch (adev->asic_type) {
320 case CHIP_TAHITI:
321 chip_name = "tahiti";
322 break;
323 case CHIP_PITCAIRN:
324 chip_name = "pitcairn";
325 break;
326 case CHIP_VERDE:
327 chip_name = "verde";
328 break;
329 case CHIP_OLAND:
330 chip_name = "oland";
331 break;
332 case CHIP_HAINAN:
333 chip_name = "hainan";
334 break;
335 default: BUG();
336 }
337
338 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
339 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
340 if (err)
341 goto out;
342 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
343 if (err)
344 goto out;
345 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
346 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
347 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
348
349 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
350 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
351 if (err)
352 goto out;
353 err = amdgpu_ucode_validate(adev->gfx.me_fw);
354 if (err)
355 goto out;
356 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
357 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
358 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
359
360 snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
361 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
362 if (err)
363 goto out;
364 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
365 if (err)
366 goto out;
367 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
368 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
369 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
370
371 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
372 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
373 if (err)
374 goto out;
375 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
376 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
377 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
378 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
379
380out:
381 if (err) {
382 pr_err("gfx6: Failed to load firmware \"%s\"\n", fw_name);
383 release_firmware(adev->gfx.pfp_fw);
384 adev->gfx.pfp_fw = NULL;
385 release_firmware(adev->gfx.me_fw);
386 adev->gfx.me_fw = NULL;
387 release_firmware(adev->gfx.ce_fw);
388 adev->gfx.ce_fw = NULL;
389 release_firmware(adev->gfx.rlc_fw);
390 adev->gfx.rlc_fw = NULL;
391 }
392 return err;
393}
394
395static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
396{
397 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
398 u32 reg_offset, split_equal_to_row_size, *tilemode;
399
400 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array));
401 tilemode = adev->gfx.config.tile_mode_array;
402
403 switch (adev->gfx.config.mem_row_size_in_kb) {
404 case 1:
405 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
406 break;
407 case 2:
408 default:
409 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
410 break;
411 case 4:
412 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
413 break;
414 }
415
416 if (adev->asic_type == CHIP_VERDE) {
417 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
418 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
419 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
420 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
421 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
422 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
423 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
424 NUM_BANKS(ADDR_SURF_16_BANK);
425 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
426 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
427 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
428 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
429 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
430 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
431 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
432 NUM_BANKS(ADDR_SURF_16_BANK);
433 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
434 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
435 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
436 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
437 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
438 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
439 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
440 NUM_BANKS(ADDR_SURF_16_BANK);
441 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
442 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
443 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
444 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
445 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
446 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
447 NUM_BANKS(ADDR_SURF_8_BANK) |
448 TILE_SPLIT(split_equal_to_row_size);
449 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
450 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
451 PIPE_CONFIG(ADDR_SURF_P4_8x16);
452 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
453 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
454 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
455 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
456 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
457 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
458 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
459 NUM_BANKS(ADDR_SURF_4_BANK);
460 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
461 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
462 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
463 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
464 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
465 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
466 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
467 NUM_BANKS(ADDR_SURF_4_BANK);
468 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
469 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
470 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
471 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
472 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
473 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
474 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
475 NUM_BANKS(ADDR_SURF_2_BANK);
476 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
477 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
478 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
479 PIPE_CONFIG(ADDR_SURF_P4_8x16);
480 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
481 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
482 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
483 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
484 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
485 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
486 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
487 NUM_BANKS(ADDR_SURF_16_BANK);
488 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
489 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
490 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
491 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
492 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
493 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
494 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
495 NUM_BANKS(ADDR_SURF_16_BANK);
496 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
497 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
498 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
499 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
500 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
501 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
502 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
503 NUM_BANKS(ADDR_SURF_16_BANK);
504 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
505 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
506 PIPE_CONFIG(ADDR_SURF_P4_8x16);
507 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
508 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
509 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
510 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
511 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
512 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
513 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
514 NUM_BANKS(ADDR_SURF_16_BANK);
515 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
516 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
517 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
518 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
519 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
520 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
521 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
522 NUM_BANKS(ADDR_SURF_16_BANK);
523 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
524 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
525 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
526 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
527 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
528 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
529 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
530 NUM_BANKS(ADDR_SURF_16_BANK);
531 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
532 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
533 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
534 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
535 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
536 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
537 NUM_BANKS(ADDR_SURF_16_BANK) |
538 TILE_SPLIT(split_equal_to_row_size);
539 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
540 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
541 PIPE_CONFIG(ADDR_SURF_P4_8x16);
542 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
543 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
544 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
545 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
546 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
547 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
548 NUM_BANKS(ADDR_SURF_16_BANK) |
549 TILE_SPLIT(split_equal_to_row_size);
550 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
551 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
552 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
553 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
554 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
555 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
556 NUM_BANKS(ADDR_SURF_16_BANK) |
557 TILE_SPLIT(split_equal_to_row_size);
558 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
559 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
560 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
561 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
562 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
563 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
564 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
565 NUM_BANKS(ADDR_SURF_8_BANK);
566 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
567 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
568 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
569 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
570 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
571 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
572 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
573 NUM_BANKS(ADDR_SURF_8_BANK);
574 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
575 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
576 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
577 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
578 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
579 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
580 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
581 NUM_BANKS(ADDR_SURF_4_BANK);
582 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
583 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
584 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
585 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
586 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
587 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
588 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
589 NUM_BANKS(ADDR_SURF_4_BANK);
590 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
591 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
592 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
593 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
594 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
595 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
596 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
597 NUM_BANKS(ADDR_SURF_2_BANK);
598 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
599 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
600 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
601 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
602 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
603 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
604 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
605 NUM_BANKS(ADDR_SURF_2_BANK);
606 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
607 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
608 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
609 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
610 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
611 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
612 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
613 NUM_BANKS(ADDR_SURF_2_BANK);
614 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
615 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
616 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
617 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
618 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
619 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
620 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
621 NUM_BANKS(ADDR_SURF_2_BANK);
622 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
623 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
624 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
625 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
626 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
627 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
628 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
629 NUM_BANKS(ADDR_SURF_2_BANK);
630 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
631 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
632 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
633 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
634 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
635 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
636 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
637 NUM_BANKS(ADDR_SURF_2_BANK);
638 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
639 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
640 } else if (adev->asic_type == CHIP_OLAND) {
641 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
642 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
643 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
644 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
645 NUM_BANKS(ADDR_SURF_16_BANK) |
646 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
647 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
648 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
649 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
650 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
651 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
652 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
653 NUM_BANKS(ADDR_SURF_16_BANK) |
654 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
655 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
656 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
657 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
658 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
659 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
660 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
661 NUM_BANKS(ADDR_SURF_16_BANK) |
662 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
663 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
664 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
665 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
666 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
667 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
668 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
669 NUM_BANKS(ADDR_SURF_16_BANK) |
670 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
671 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
672 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
673 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
674 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
675 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
676 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
677 NUM_BANKS(ADDR_SURF_16_BANK) |
678 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
679 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
680 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
681 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
682 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
683 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
684 TILE_SPLIT(split_equal_to_row_size) |
685 NUM_BANKS(ADDR_SURF_16_BANK) |
686 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
687 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
688 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
689 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
690 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
691 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
692 TILE_SPLIT(split_equal_to_row_size) |
693 NUM_BANKS(ADDR_SURF_16_BANK) |
694 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
695 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
696 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
697 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
698 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
699 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
700 TILE_SPLIT(split_equal_to_row_size) |
701 NUM_BANKS(ADDR_SURF_16_BANK) |
702 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
703 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
704 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
705 tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
706 ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
707 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
708 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
709 NUM_BANKS(ADDR_SURF_16_BANK) |
710 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
711 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
712 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
713 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
714 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
715 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
716 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
717 NUM_BANKS(ADDR_SURF_16_BANK) |
718 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
719 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
720 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
721 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
722 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
723 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
724 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
725 NUM_BANKS(ADDR_SURF_16_BANK) |
726 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
727 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
728 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
729 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
730 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
731 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
732 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
733 NUM_BANKS(ADDR_SURF_16_BANK) |
734 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
735 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
736 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
737 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
738 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
739 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
740 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
741 NUM_BANKS(ADDR_SURF_16_BANK) |
742 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
743 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
744 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
745 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
746 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
747 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
748 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
749 NUM_BANKS(ADDR_SURF_16_BANK) |
750 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
751 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
752 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
753 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
754 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
755 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
756 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
757 NUM_BANKS(ADDR_SURF_16_BANK) |
758 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
759 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
760 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
761 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
762 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
763 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
764 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
765 NUM_BANKS(ADDR_SURF_16_BANK) |
766 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
767 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
768 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
769 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
770 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
771 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
772 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
773 NUM_BANKS(ADDR_SURF_16_BANK) |
774 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
775 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
776 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
777 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
778 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
779 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
780 TILE_SPLIT(split_equal_to_row_size) |
781 NUM_BANKS(ADDR_SURF_16_BANK) |
782 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
783 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
784 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
785 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
786 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
787 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
788 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
789 NUM_BANKS(ADDR_SURF_16_BANK) |
790 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
791 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
792 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
793 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
794 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
795 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
796 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
797 NUM_BANKS(ADDR_SURF_16_BANK) |
798 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
799 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
800 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
801 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
802 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
803 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
804 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
805 NUM_BANKS(ADDR_SURF_16_BANK) |
806 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
807 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
808 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
809 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
810 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
811 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
812 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
813 NUM_BANKS(ADDR_SURF_16_BANK) |
814 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
815 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
816 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
817 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
818 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
819 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
820 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
821 NUM_BANKS(ADDR_SURF_8_BANK) |
822 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
823 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
824 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1);
825 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
826 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
827 } else if (adev->asic_type == CHIP_HAINAN) {
828 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
829 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
830 PIPE_CONFIG(ADDR_SURF_P2) |
831 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
832 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
833 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
834 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
835 NUM_BANKS(ADDR_SURF_16_BANK);
836 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
837 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
838 PIPE_CONFIG(ADDR_SURF_P2) |
839 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
840 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
841 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
842 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
843 NUM_BANKS(ADDR_SURF_16_BANK);
844 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
845 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
846 PIPE_CONFIG(ADDR_SURF_P2) |
847 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
848 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
849 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
850 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
851 NUM_BANKS(ADDR_SURF_16_BANK);
852 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
853 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
854 PIPE_CONFIG(ADDR_SURF_P2) |
855 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
856 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
857 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
858 NUM_BANKS(ADDR_SURF_8_BANK) |
859 TILE_SPLIT(split_equal_to_row_size);
860 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
861 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
862 PIPE_CONFIG(ADDR_SURF_P2);
863 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
864 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
865 PIPE_CONFIG(ADDR_SURF_P2) |
866 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
867 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
868 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
869 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
870 NUM_BANKS(ADDR_SURF_8_BANK);
871 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
872 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
873 PIPE_CONFIG(ADDR_SURF_P2) |
874 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
875 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
876 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
877 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
878 NUM_BANKS(ADDR_SURF_8_BANK);
879 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
880 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
881 PIPE_CONFIG(ADDR_SURF_P2) |
882 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
883 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
884 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
885 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
886 NUM_BANKS(ADDR_SURF_4_BANK);
887 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
888 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
889 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
890 PIPE_CONFIG(ADDR_SURF_P2);
891 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
892 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
893 PIPE_CONFIG(ADDR_SURF_P2) |
894 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
895 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
896 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
897 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
898 NUM_BANKS(ADDR_SURF_16_BANK);
899 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
900 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
901 PIPE_CONFIG(ADDR_SURF_P2) |
902 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
903 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
904 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
905 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
906 NUM_BANKS(ADDR_SURF_16_BANK);
907 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
908 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
909 PIPE_CONFIG(ADDR_SURF_P2) |
910 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
911 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
912 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
913 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
914 NUM_BANKS(ADDR_SURF_16_BANK);
915 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
916 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
917 PIPE_CONFIG(ADDR_SURF_P2);
918 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
919 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
920 PIPE_CONFIG(ADDR_SURF_P2) |
921 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
922 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
923 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
924 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
925 NUM_BANKS(ADDR_SURF_16_BANK);
926 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
927 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
928 PIPE_CONFIG(ADDR_SURF_P2) |
929 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
930 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
931 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
932 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
933 NUM_BANKS(ADDR_SURF_16_BANK);
934 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
935 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
936 PIPE_CONFIG(ADDR_SURF_P2) |
937 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
938 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
939 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
940 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
941 NUM_BANKS(ADDR_SURF_16_BANK);
942 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
943 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
944 PIPE_CONFIG(ADDR_SURF_P2) |
945 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
946 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
947 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
948 NUM_BANKS(ADDR_SURF_16_BANK) |
949 TILE_SPLIT(split_equal_to_row_size);
950 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
951 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
952 PIPE_CONFIG(ADDR_SURF_P2);
953 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
954 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
955 PIPE_CONFIG(ADDR_SURF_P2) |
956 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
957 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
958 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
959 NUM_BANKS(ADDR_SURF_16_BANK) |
960 TILE_SPLIT(split_equal_to_row_size);
961 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
962 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
963 PIPE_CONFIG(ADDR_SURF_P2) |
964 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
965 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
966 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
967 NUM_BANKS(ADDR_SURF_16_BANK) |
968 TILE_SPLIT(split_equal_to_row_size);
969 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
970 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
971 PIPE_CONFIG(ADDR_SURF_P2) |
972 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
973 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
974 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
975 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
976 NUM_BANKS(ADDR_SURF_8_BANK);
977 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
978 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
979 PIPE_CONFIG(ADDR_SURF_P2) |
980 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
981 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
982 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
983 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
984 NUM_BANKS(ADDR_SURF_8_BANK);
985 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
986 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
987 PIPE_CONFIG(ADDR_SURF_P2) |
988 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
989 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
990 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
991 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
992 NUM_BANKS(ADDR_SURF_8_BANK);
993 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
994 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
995 PIPE_CONFIG(ADDR_SURF_P2) |
996 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
997 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
998 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
999 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1000 NUM_BANKS(ADDR_SURF_8_BANK);
1001 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1002 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1003 PIPE_CONFIG(ADDR_SURF_P2) |
1004 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1005 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1006 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1007 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1008 NUM_BANKS(ADDR_SURF_4_BANK);
1009 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1010 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1011 PIPE_CONFIG(ADDR_SURF_P2) |
1012 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1013 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1014 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1015 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1016 NUM_BANKS(ADDR_SURF_4_BANK);
1017 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1018 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1019 PIPE_CONFIG(ADDR_SURF_P2) |
1020 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1021 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1022 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1023 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1024 NUM_BANKS(ADDR_SURF_4_BANK);
1025 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1026 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1027 PIPE_CONFIG(ADDR_SURF_P2) |
1028 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1029 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1030 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1031 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1032 NUM_BANKS(ADDR_SURF_4_BANK);
1033 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1034 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1035 PIPE_CONFIG(ADDR_SURF_P2) |
1036 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1037 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1038 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1039 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1040 NUM_BANKS(ADDR_SURF_4_BANK);
1041 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1042 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1043 PIPE_CONFIG(ADDR_SURF_P2) |
1044 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1045 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1046 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1047 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1048 NUM_BANKS(ADDR_SURF_4_BANK);
1049 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1050 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1051 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
1052 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1053 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1054 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1055 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1056 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1057 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1058 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1059 NUM_BANKS(ADDR_SURF_16_BANK);
1060 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1061 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1062 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1063 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1064 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1065 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1066 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1067 NUM_BANKS(ADDR_SURF_16_BANK);
1068 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1069 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1070 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1071 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1072 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1073 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1074 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1075 NUM_BANKS(ADDR_SURF_16_BANK);
1076 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1077 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1078 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1079 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1080 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1081 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1082 NUM_BANKS(ADDR_SURF_4_BANK) |
1083 TILE_SPLIT(split_equal_to_row_size);
1084 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1085 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1086 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1087 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1088 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1089 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1090 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1091 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1092 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1093 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1094 NUM_BANKS(ADDR_SURF_2_BANK);
1095 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1096 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1097 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1098 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1099 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1100 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1101 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1102 NUM_BANKS(ADDR_SURF_2_BANK);
1103 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1104 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1105 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1106 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1107 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1108 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1109 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1110 NUM_BANKS(ADDR_SURF_2_BANK);
1111 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
1112 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1113 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1114 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1115 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1116 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1117 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1118 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1119 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1120 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1121 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1122 NUM_BANKS(ADDR_SURF_16_BANK);
1123 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1124 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1125 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1126 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1127 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1128 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1129 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1130 NUM_BANKS(ADDR_SURF_16_BANK);
1131 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1132 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1133 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1134 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1135 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1136 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1137 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1138 NUM_BANKS(ADDR_SURF_16_BANK);
1139 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1140 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1141 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1142 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1143 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1144 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1145 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1146 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1147 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1148 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1149 NUM_BANKS(ADDR_SURF_16_BANK);
1150 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1151 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1152 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1153 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1154 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1155 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1156 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1157 NUM_BANKS(ADDR_SURF_16_BANK);
1158 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1159 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1160 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1161 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1162 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1163 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1164 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1165 NUM_BANKS(ADDR_SURF_16_BANK);
1166 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1167 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1168 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1169 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1170 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1171 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1172 NUM_BANKS(ADDR_SURF_16_BANK) |
1173 TILE_SPLIT(split_equal_to_row_size);
1174 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1175 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1176 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1177 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1178 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1179 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1180 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1181 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1182 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1183 NUM_BANKS(ADDR_SURF_16_BANK) |
1184 TILE_SPLIT(split_equal_to_row_size);
1185 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1186 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1187 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1188 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1189 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1190 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1191 NUM_BANKS(ADDR_SURF_16_BANK) |
1192 TILE_SPLIT(split_equal_to_row_size);
1193 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1194 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1195 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1196 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1197 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1198 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1199 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1200 NUM_BANKS(ADDR_SURF_4_BANK);
1201 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1202 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1203 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1204 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1205 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1206 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1207 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1208 NUM_BANKS(ADDR_SURF_4_BANK);
1209 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1210 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1211 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1212 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1213 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1214 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1215 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1216 NUM_BANKS(ADDR_SURF_2_BANK);
1217 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1218 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1219 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1220 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1221 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1222 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1223 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1224 NUM_BANKS(ADDR_SURF_2_BANK);
1225 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1226 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1227 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1228 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1229 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1230 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1231 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1232 NUM_BANKS(ADDR_SURF_2_BANK);
1233 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1234 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1235 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1236 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1237 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1238 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1239 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1240 NUM_BANKS(ADDR_SURF_2_BANK);
1241 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1242 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1243 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1244 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1245 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1246 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1247 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1248 NUM_BANKS(ADDR_SURF_2_BANK);
1249 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1250 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1251 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1252 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1253 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1254 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1255 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1256 NUM_BANKS(ADDR_SURF_2_BANK);
1257 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1258 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1259 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1260 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1261 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1262 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1263 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1264 NUM_BANKS(ADDR_SURF_2_BANK);
1265 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1266 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1267 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1268 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1269 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1270 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1271 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1272 NUM_BANKS(ADDR_SURF_2_BANK);
1273 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1274 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1275 } else {
1276 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1277 }
1278}
1279
1280static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1281 u32 sh_num, u32 instance)
1282{
1283 u32 data;
1284
1285 if (instance == 0xffffffff)
1286 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1287 else
1288 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1289
1290 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1291 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1292 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1293 else if (se_num == 0xffffffff)
1294 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1295 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1296 else if (sh_num == 0xffffffff)
1297 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1298 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1299 else
1300 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1301 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1302 WREG32(mmGRBM_GFX_INDEX, data);
1303}
1304
1305static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1306{
1307 u32 data, mask;
1308
1309 data = RREG32(mmCC_RB_BACKEND_DISABLE) |
1310 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1311
1312 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
1313
1314 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/
1315 adev->gfx.config.max_sh_per_se);
1316
1317 return ~data & mask;
1318}
1319
1320static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf)
1321{
1322 switch (adev->asic_type) {
1323 case CHIP_TAHITI:
1324 case CHIP_PITCAIRN:
1325 *rconf |=
1326 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) |
1327 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1328 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1329 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) |
1330 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) |
1331 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) |
1332 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT);
1333 break;
1334 case CHIP_VERDE:
1335 *rconf |=
1336 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1337 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1338 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT);
1339 break;
1340 case CHIP_OLAND:
1341 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT);
1342 break;
1343 case CHIP_HAINAN:
1344 *rconf |= 0x0;
1345 break;
1346 default:
1347 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1348 break;
1349 }
1350}
1351
1352static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1353 u32 raster_config, unsigned rb_mask,
1354 unsigned num_rb)
1355{
1356 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1357 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1358 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1359 unsigned rb_per_se = num_rb / num_se;
1360 unsigned se_mask[4];
1361 unsigned se;
1362
1363 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1364 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1365 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1366 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1367
1368 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1369 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1370 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1371
1372 for (se = 0; se < num_se; se++) {
1373 unsigned raster_config_se = raster_config;
1374 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1375 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1376 int idx = (se / 2) * 2;
1377
1378 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1379 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK;
1380
1381 if (!se_mask[idx])
1382 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1383 else
1384 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1385 }
1386
1387 pkr0_mask &= rb_mask;
1388 pkr1_mask &= rb_mask;
1389 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1390 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK;
1391
1392 if (!pkr0_mask)
1393 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1394 else
1395 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1396 }
1397
1398 if (rb_per_se >= 2) {
1399 unsigned rb0_mask = 1 << (se * rb_per_se);
1400 unsigned rb1_mask = rb0_mask << 1;
1401
1402 rb0_mask &= rb_mask;
1403 rb1_mask &= rb_mask;
1404 if (!rb0_mask || !rb1_mask) {
1405 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK;
1406
1407 if (!rb0_mask)
1408 raster_config_se |=
1409 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1410 else
1411 raster_config_se |=
1412 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1413 }
1414
1415 if (rb_per_se > 2) {
1416 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1417 rb1_mask = rb0_mask << 1;
1418 rb0_mask &= rb_mask;
1419 rb1_mask &= rb_mask;
1420 if (!rb0_mask || !rb1_mask) {
1421 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK;
1422
1423 if (!rb0_mask)
1424 raster_config_se |=
1425 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1426 else
1427 raster_config_se |=
1428 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1429 }
1430 }
1431 }
1432
1433 /* GRBM_GFX_INDEX has a different offset on SI */
1434 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff);
1435 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1436 }
1437
1438 /* GRBM_GFX_INDEX has a different offset on SI */
1439 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1440}
1441
1442static void gfx_v6_0_setup_rb(struct amdgpu_device *adev)
1443{
1444 int i, j;
1445 u32 data;
1446 u32 raster_config = 0;
1447 u32 active_rbs = 0;
1448 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1449 adev->gfx.config.max_sh_per_se;
1450 unsigned num_rb_pipes;
1451
1452 mutex_lock(&adev->grbm_idx_mutex);
1453 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1454 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1455 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1456 data = gfx_v6_0_get_rb_active_bitmap(adev);
1457 active_rbs |= data <<
1458 ((i * adev->gfx.config.max_sh_per_se + j) *
1459 rb_bitmap_width_per_sh);
1460 }
1461 }
1462 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1463
1464 adev->gfx.config.backend_enable_mask = active_rbs;
1465 adev->gfx.config.num_rbs = hweight32(active_rbs);
1466
1467 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1468 adev->gfx.config.max_shader_engines, 16);
1469
1470 gfx_v6_0_raster_config(adev, &raster_config);
1471
1472 if (!adev->gfx.config.backend_enable_mask ||
1473 adev->gfx.config.num_rbs >= num_rb_pipes)
1474 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1475 else
1476 gfx_v6_0_write_harvested_raster_configs(adev, raster_config,
1477 adev->gfx.config.backend_enable_mask,
1478 num_rb_pipes);
1479
1480 /* cache the values for userspace */
1481 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1482 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1483 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1484 adev->gfx.config.rb_config[i][j].rb_backend_disable =
1485 RREG32(mmCC_RB_BACKEND_DISABLE);
1486 adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
1487 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1488 adev->gfx.config.rb_config[i][j].raster_config =
1489 RREG32(mmPA_SC_RASTER_CONFIG);
1490 }
1491 }
1492 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1493 mutex_unlock(&adev->grbm_idx_mutex);
1494}
1495
1496static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
1497 u32 bitmap)
1498{
1499 u32 data;
1500
1501 if (!bitmap)
1502 return;
1503
1504 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
1505 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
1506
1507 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
1508}
1509
1510static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev)
1511{
1512 u32 data, mask;
1513
1514 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
1515 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
1516
1517 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
1518 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
1519}
1520
1521
1522static void gfx_v6_0_setup_spi(struct amdgpu_device *adev)
1523{
1524 int i, j, k;
1525 u32 data, mask;
1526 u32 active_cu = 0;
1527
1528 mutex_lock(&adev->grbm_idx_mutex);
1529 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1530 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1531 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
1532 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3);
1533 active_cu = gfx_v6_0_get_cu_enabled(adev);
1534
1535 mask = 1;
1536 for (k = 0; k < 16; k++) {
1537 mask <<= k;
1538 if (active_cu & mask) {
1539 data &= ~mask;
1540 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data);
1541 break;
1542 }
1543 }
1544 }
1545 }
1546 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1547 mutex_unlock(&adev->grbm_idx_mutex);
1548}
1549
1550static void gfx_v6_0_config_init(struct amdgpu_device *adev)
1551{
1552 adev->gfx.config.double_offchip_lds_buf = 0;
1553}
1554
1555static void gfx_v6_0_gpu_init(struct amdgpu_device *adev)
1556{
1557 u32 gb_addr_config = 0;
1558 u32 mc_shared_chmap, mc_arb_ramcfg;
1559 u32 sx_debug_1;
1560 u32 hdp_host_path_cntl;
1561 u32 tmp;
1562
1563 switch (adev->asic_type) {
1564 case CHIP_TAHITI:
1565 adev->gfx.config.max_shader_engines = 2;
1566 adev->gfx.config.max_tile_pipes = 12;
1567 adev->gfx.config.max_cu_per_sh = 8;
1568 adev->gfx.config.max_sh_per_se = 2;
1569 adev->gfx.config.max_backends_per_se = 4;
1570 adev->gfx.config.max_texture_channel_caches = 12;
1571 adev->gfx.config.max_gprs = 256;
1572 adev->gfx.config.max_gs_threads = 32;
1573 adev->gfx.config.max_hw_contexts = 8;
1574
1575 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1576 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1577 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1578 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1579 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1580 break;
1581 case CHIP_PITCAIRN:
1582 adev->gfx.config.max_shader_engines = 2;
1583 adev->gfx.config.max_tile_pipes = 8;
1584 adev->gfx.config.max_cu_per_sh = 5;
1585 adev->gfx.config.max_sh_per_se = 2;
1586 adev->gfx.config.max_backends_per_se = 4;
1587 adev->gfx.config.max_texture_channel_caches = 8;
1588 adev->gfx.config.max_gprs = 256;
1589 adev->gfx.config.max_gs_threads = 32;
1590 adev->gfx.config.max_hw_contexts = 8;
1591
1592 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1593 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1594 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1595 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1596 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1597 break;
1598 case CHIP_VERDE:
1599 adev->gfx.config.max_shader_engines = 1;
1600 adev->gfx.config.max_tile_pipes = 4;
1601 adev->gfx.config.max_cu_per_sh = 5;
1602 adev->gfx.config.max_sh_per_se = 2;
1603 adev->gfx.config.max_backends_per_se = 4;
1604 adev->gfx.config.max_texture_channel_caches = 4;
1605 adev->gfx.config.max_gprs = 256;
1606 adev->gfx.config.max_gs_threads = 32;
1607 adev->gfx.config.max_hw_contexts = 8;
1608
1609 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1610 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1611 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1612 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1613 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1614 break;
1615 case CHIP_OLAND:
1616 adev->gfx.config.max_shader_engines = 1;
1617 adev->gfx.config.max_tile_pipes = 4;
1618 adev->gfx.config.max_cu_per_sh = 6;
1619 adev->gfx.config.max_sh_per_se = 1;
1620 adev->gfx.config.max_backends_per_se = 2;
1621 adev->gfx.config.max_texture_channel_caches = 4;
1622 adev->gfx.config.max_gprs = 256;
1623 adev->gfx.config.max_gs_threads = 16;
1624 adev->gfx.config.max_hw_contexts = 8;
1625
1626 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1627 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1628 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1629 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1630 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1631 break;
1632 case CHIP_HAINAN:
1633 adev->gfx.config.max_shader_engines = 1;
1634 adev->gfx.config.max_tile_pipes = 4;
1635 adev->gfx.config.max_cu_per_sh = 5;
1636 adev->gfx.config.max_sh_per_se = 1;
1637 adev->gfx.config.max_backends_per_se = 1;
1638 adev->gfx.config.max_texture_channel_caches = 2;
1639 adev->gfx.config.max_gprs = 256;
1640 adev->gfx.config.max_gs_threads = 16;
1641 adev->gfx.config.max_hw_contexts = 8;
1642
1643 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1644 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1645 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1646 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1647 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
1648 break;
1649 default:
1650 BUG();
1651 break;
1652 }
1653
1654 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1655 WREG32(mmSRBM_INT_CNTL, 1);
1656 WREG32(mmSRBM_INT_ACK, 1);
1657
1658 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
1659
1660 mc_shared_chmap = RREG32(mmMC_SHARED_CHMAP);
1661 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1662 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1663
1664 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1665 adev->gfx.config.mem_max_burst_length_bytes = 256;
1666 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
1667 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1668 if (adev->gfx.config.mem_row_size_in_kb > 4)
1669 adev->gfx.config.mem_row_size_in_kb = 4;
1670 adev->gfx.config.shader_engine_tile_size = 32;
1671 adev->gfx.config.num_gpus = 1;
1672 adev->gfx.config.multi_gpu_tile_size = 64;
1673
1674 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
1675 switch (adev->gfx.config.mem_row_size_in_kb) {
1676 case 1:
1677 default:
1678 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1679 break;
1680 case 2:
1681 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1682 break;
1683 case 4:
1684 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1685 break;
1686 }
1687 gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK;
1688 if (adev->gfx.config.max_shader_engines == 2)
1689 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT;
1690 adev->gfx.config.gb_addr_config = gb_addr_config;
1691
1692 WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
1693 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config);
1694 WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
1695 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
1696 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1697 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1698
1699#if 0
1700 if (adev->has_uvd) {
1701 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
1702 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1703 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1704 }
1705#endif
1706 gfx_v6_0_tiling_mode_table_init(adev);
1707
1708 gfx_v6_0_setup_rb(adev);
1709
1710 gfx_v6_0_setup_spi(adev);
1711
1712 gfx_v6_0_get_cu_info(adev);
1713 gfx_v6_0_config_init(adev);
1714
1715 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |
1716 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));
1717 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1718 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1719
1720 sx_debug_1 = RREG32(mmSX_DEBUG_1);
1721 WREG32(mmSX_DEBUG_1, sx_debug_1);
1722
1723 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1724
1725 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1726 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1727 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1728 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1729
1730 WREG32(mmVGT_NUM_INSTANCES, 1);
1731 WREG32(mmCP_PERFMON_CNTL, 0);
1732 WREG32(mmSQ_CONFIG, 0);
1733 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1734 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1735
1736 WREG32(mmVGT_CACHE_INVALIDATION,
1737 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1738 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1739
1740 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1741 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1742
1743 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0);
1744 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0);
1745 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0);
1746 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0);
1747 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0);
1748 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0);
1749 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0);
1750 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0);
1751
1752 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL);
1753 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1754
1755 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1756 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1757
1758 udelay(50);
1759}
1760
1761
1762static void gfx_v6_0_scratch_init(struct amdgpu_device *adev)
1763{
1764 adev->gfx.scratch.num_reg = 8;
1765 adev->gfx.scratch.reg_base = mmSCRATCH_REG0;
1766 adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
1767}
1768
1769static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
1770{
1771 struct amdgpu_device *adev = ring->adev;
1772 uint32_t scratch;
1773 uint32_t tmp = 0;
1774 unsigned i;
1775 int r;
1776
1777 r = amdgpu_gfx_scratch_get(adev, &scratch);
1778 if (r) {
1779 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
1780 return r;
1781 }
1782 WREG32(scratch, 0xCAFEDEAD);
1783
1784 r = amdgpu_ring_alloc(ring, 3);
1785 if (r) {
1786 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n", ring->idx, r);
1787 amdgpu_gfx_scratch_free(adev, scratch);
1788 return r;
1789 }
1790 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1791 amdgpu_ring_write(ring, (scratch - PACKET3_SET_CONFIG_REG_START));
1792 amdgpu_ring_write(ring, 0xDEADBEEF);
1793 amdgpu_ring_commit(ring);
1794
1795 for (i = 0; i < adev->usec_timeout; i++) {
1796 tmp = RREG32(scratch);
1797 if (tmp == 0xDEADBEEF)
1798 break;
1799 DRM_UDELAY(1);
1800 }
1801 if (i < adev->usec_timeout) {
1802 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
1803 } else {
1804 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
1805 ring->idx, scratch, tmp);
1806 r = -EINVAL;
1807 }
1808 amdgpu_gfx_scratch_free(adev, scratch);
1809 return r;
1810}
1811
1812static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
1813{
1814 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
1815 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
1816 EVENT_INDEX(0));
1817}
1818
1819static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1820 u64 seq, unsigned flags)
1821{
1822 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1823 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1824 /* flush read cache over gart */
1825 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1826 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
1827 amdgpu_ring_write(ring, 0);
1828 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1829 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1830 PACKET3_TC_ACTION_ENA |
1831 PACKET3_SH_KCACHE_ACTION_ENA |
1832 PACKET3_SH_ICACHE_ACTION_ENA);
1833 amdgpu_ring_write(ring, 0xFFFFFFFF);
1834 amdgpu_ring_write(ring, 0);
1835 amdgpu_ring_write(ring, 10); /* poll interval */
1836 /* EVENT_WRITE_EOP - flush caches, send int */
1837 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1838 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1839 amdgpu_ring_write(ring, addr & 0xfffffffc);
1840 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1841 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) |
1842 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT));
1843 amdgpu_ring_write(ring, lower_32_bits(seq));
1844 amdgpu_ring_write(ring, upper_32_bits(seq));
1845}
1846
1847static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1848 struct amdgpu_ib *ib,
1849 unsigned vmid, bool ctx_switch)
1850{
1851 u32 header, control = 0;
1852
1853 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
1854 if (ctx_switch) {
1855 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1856 amdgpu_ring_write(ring, 0);
1857 }
1858
1859 if (ib->flags & AMDGPU_IB_FLAG_CE)
1860 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1861 else
1862 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1863
1864 control |= ib->length_dw | (vmid << 24);
1865
1866 amdgpu_ring_write(ring, header);
1867 amdgpu_ring_write(ring,
1868#ifdef __BIG_ENDIAN
1869 (2 << 0) |
1870#endif
1871 (ib->gpu_addr & 0xFFFFFFFC));
1872 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1873 amdgpu_ring_write(ring, control);
1874}
1875
1876/**
1877 * gfx_v6_0_ring_test_ib - basic ring IB test
1878 *
1879 * @ring: amdgpu_ring structure holding ring information
1880 *
1881 * Allocate an IB and execute it on the gfx ring (SI).
1882 * Provides a basic gfx ring test to verify that IBs are working.
1883 * Returns 0 on success, error on failure.
1884 */
1885static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1886{
1887 struct amdgpu_device *adev = ring->adev;
1888 struct amdgpu_ib ib;
1889 struct dma_fence *f = NULL;
1890 uint32_t scratch;
1891 uint32_t tmp = 0;
1892 long r;
1893
1894 r = amdgpu_gfx_scratch_get(adev, &scratch);
1895 if (r) {
1896 DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
1897 return r;
1898 }
1899 WREG32(scratch, 0xCAFEDEAD);
1900 memset(&ib, 0, sizeof(ib));
1901 r = amdgpu_ib_get(adev, NULL, 256, &ib);
1902 if (r) {
1903 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
1904 goto err1;
1905 }
1906 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1907 ib.ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_START));
1908 ib.ptr[2] = 0xDEADBEEF;
1909 ib.length_dw = 3;
1910
1911 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1912 if (r)
1913 goto err2;
1914
1915 r = dma_fence_wait_timeout(f, false, timeout);
1916 if (r == 0) {
1917 DRM_ERROR("amdgpu: IB test timed out\n");
1918 r = -ETIMEDOUT;
1919 goto err2;
1920 } else if (r < 0) {
1921 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
1922 goto err2;
1923 }
1924 tmp = RREG32(scratch);
1925 if (tmp == 0xDEADBEEF) {
1926 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
1927 r = 0;
1928 } else {
1929 DRM_ERROR("amdgpu: ib test failed (scratch(0x%04X)=0x%08X)\n",
1930 scratch, tmp);
1931 r = -EINVAL;
1932 }
1933
1934err2:
1935 amdgpu_ib_free(adev, &ib, NULL);
1936 dma_fence_put(f);
1937err1:
1938 amdgpu_gfx_scratch_free(adev, scratch);
1939 return r;
1940}
1941
1942static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1943{
1944 int i;
1945 if (enable) {
1946 WREG32(mmCP_ME_CNTL, 0);
1947 } else {
1948 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK |
1949 CP_ME_CNTL__PFP_HALT_MASK |
1950 CP_ME_CNTL__CE_HALT_MASK));
1951 WREG32(mmSCRATCH_UMSK, 0);
1952 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1953 adev->gfx.gfx_ring[i].ready = false;
1954 for (i = 0; i < adev->gfx.num_compute_rings; i++)
1955 adev->gfx.compute_ring[i].ready = false;
1956 }
1957 udelay(50);
1958}
1959
1960static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1961{
1962 unsigned i;
1963 const struct gfx_firmware_header_v1_0 *pfp_hdr;
1964 const struct gfx_firmware_header_v1_0 *ce_hdr;
1965 const struct gfx_firmware_header_v1_0 *me_hdr;
1966 const __le32 *fw_data;
1967 u32 fw_size;
1968
1969 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1970 return -EINVAL;
1971
1972 gfx_v6_0_cp_gfx_enable(adev, false);
1973 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1974 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1975 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1976
1977 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1978 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1979 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1980
1981 /* PFP */
1982 fw_data = (const __le32 *)
1983 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1984 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
1985 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1986 for (i = 0; i < fw_size; i++)
1987 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
1988 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1989
1990 /* CE */
1991 fw_data = (const __le32 *)
1992 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1993 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
1994 WREG32(mmCP_CE_UCODE_ADDR, 0);
1995 for (i = 0; i < fw_size; i++)
1996 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
1997 WREG32(mmCP_CE_UCODE_ADDR, 0);
1998
1999 /* ME */
2000 fw_data = (const __be32 *)
2001 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2002 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2003 WREG32(mmCP_ME_RAM_WADDR, 0);
2004 for (i = 0; i < fw_size; i++)
2005 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2006 WREG32(mmCP_ME_RAM_WADDR, 0);
2007
2008 WREG32(mmCP_PFP_UCODE_ADDR, 0);
2009 WREG32(mmCP_CE_UCODE_ADDR, 0);
2010 WREG32(mmCP_ME_RAM_WADDR, 0);
2011 WREG32(mmCP_ME_RAM_RADDR, 0);
2012 return 0;
2013}
2014
2015static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev)
2016{
2017 const struct cs_section_def *sect = NULL;
2018 const struct cs_extent_def *ext = NULL;
2019 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2020 int r, i;
2021
2022 r = amdgpu_ring_alloc(ring, 7 + 4);
2023 if (r) {
2024 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2025 return r;
2026 }
2027 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
2028 amdgpu_ring_write(ring, 0x1);
2029 amdgpu_ring_write(ring, 0x0);
2030 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1);
2031 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2032 amdgpu_ring_write(ring, 0);
2033 amdgpu_ring_write(ring, 0);
2034
2035 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2036 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2037 amdgpu_ring_write(ring, 0xc000);
2038 amdgpu_ring_write(ring, 0xe000);
2039 amdgpu_ring_commit(ring);
2040
2041 gfx_v6_0_cp_gfx_enable(adev, true);
2042
2043 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10);
2044 if (r) {
2045 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2046 return r;
2047 }
2048
2049 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2050 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2051
2052 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2053 for (ext = sect->section; ext->extent != NULL; ++ext) {
2054 if (sect->id == SECT_CONTEXT) {
2055 amdgpu_ring_write(ring,
2056 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2057 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2058 for (i = 0; i < ext->reg_count; i++)
2059 amdgpu_ring_write(ring, ext->extent[i]);
2060 }
2061 }
2062 }
2063
2064 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2065 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2066
2067 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2068 amdgpu_ring_write(ring, 0);
2069
2070 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2071 amdgpu_ring_write(ring, 0x00000316);
2072 amdgpu_ring_write(ring, 0x0000000e);
2073 amdgpu_ring_write(ring, 0x00000010);
2074
2075 amdgpu_ring_commit(ring);
2076
2077 return 0;
2078}
2079
2080static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
2081{
2082 struct amdgpu_ring *ring;
2083 u32 tmp;
2084 u32 rb_bufsz;
2085 int r;
2086 u64 rptr_addr;
2087
2088 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2089 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2090
2091 /* Set the write pointer delay */
2092 WREG32(mmCP_RB_WPTR_DELAY, 0);
2093
2094 WREG32(mmCP_DEBUG, 0);
2095 WREG32(mmSCRATCH_ADDR, 0);
2096
2097 /* ring 0 - compute and gfx */
2098 /* Set ring buffer size */
2099 ring = &adev->gfx.gfx_ring[0];
2100 rb_bufsz = order_base_2(ring->ring_size / 8);
2101 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2102
2103#ifdef __BIG_ENDIAN
2104 tmp |= BUF_SWAP_32BIT;
2105#endif
2106 WREG32(mmCP_RB0_CNTL, tmp);
2107
2108 /* Initialize the ring buffer's read and write pointers */
2109 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2110 ring->wptr = 0;
2111 WREG32(mmCP_RB0_WPTR, ring->wptr);
2112
2113 /* set the wb address whether it's enabled or not */
2114 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2115 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2116 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2117
2118 WREG32(mmSCRATCH_UMSK, 0);
2119
2120 mdelay(1);
2121 WREG32(mmCP_RB0_CNTL, tmp);
2122
2123 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8);
2124
2125 /* start the rings */
2126 gfx_v6_0_cp_gfx_start(adev);
2127 ring->ready = true;
2128 r = amdgpu_ring_test_ring(ring);
2129 if (r) {
2130 ring->ready = false;
2131 return r;
2132 }
2133
2134 return 0;
2135}
2136
2137static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
2138{
2139 return ring->adev->wb.wb[ring->rptr_offs];
2140}
2141
2142static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
2143{
2144 struct amdgpu_device *adev = ring->adev;
2145
2146 if (ring == &adev->gfx.gfx_ring[0])
2147 return RREG32(mmCP_RB0_WPTR);
2148 else if (ring == &adev->gfx.compute_ring[0])
2149 return RREG32(mmCP_RB1_WPTR);
2150 else if (ring == &adev->gfx.compute_ring[1])
2151 return RREG32(mmCP_RB2_WPTR);
2152 else
2153 BUG();
2154}
2155
2156static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2157{
2158 struct amdgpu_device *adev = ring->adev;
2159
2160 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2161 (void)RREG32(mmCP_RB0_WPTR);
2162}
2163
2164static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2165{
2166 struct amdgpu_device *adev = ring->adev;
2167
2168 if (ring == &adev->gfx.compute_ring[0]) {
2169 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2170 (void)RREG32(mmCP_RB1_WPTR);
2171 } else if (ring == &adev->gfx.compute_ring[1]) {
2172 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr));
2173 (void)RREG32(mmCP_RB2_WPTR);
2174 } else {
2175 BUG();
2176 }
2177
2178}
2179
2180static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
2181{
2182 struct amdgpu_ring *ring;
2183 u32 tmp;
2184 u32 rb_bufsz;
2185 int i, r;
2186 u64 rptr_addr;
2187
2188 /* ring1 - compute only */
2189 /* Set ring buffer size */
2190
2191 ring = &adev->gfx.compute_ring[0];
2192 rb_bufsz = order_base_2(ring->ring_size / 8);
2193 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2194#ifdef __BIG_ENDIAN
2195 tmp |= BUF_SWAP_32BIT;
2196#endif
2197 WREG32(mmCP_RB1_CNTL, tmp);
2198
2199 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK);
2200 ring->wptr = 0;
2201 WREG32(mmCP_RB1_WPTR, ring->wptr);
2202
2203 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2204 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2205 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2206
2207 mdelay(1);
2208 WREG32(mmCP_RB1_CNTL, tmp);
2209 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8);
2210
2211 ring = &adev->gfx.compute_ring[1];
2212 rb_bufsz = order_base_2(ring->ring_size / 8);
2213 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2214#ifdef __BIG_ENDIAN
2215 tmp |= BUF_SWAP_32BIT;
2216#endif
2217 WREG32(mmCP_RB2_CNTL, tmp);
2218
2219 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK);
2220 ring->wptr = 0;
2221 WREG32(mmCP_RB2_WPTR, ring->wptr);
2222 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2223 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
2224 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2225
2226 mdelay(1);
2227 WREG32(mmCP_RB2_CNTL, tmp);
2228 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8);
2229
2230 adev->gfx.compute_ring[0].ready = false;
2231 adev->gfx.compute_ring[1].ready = false;
2232
2233 for (i = 0; i < 2; i++) {
2234 r = amdgpu_ring_test_ring(&adev->gfx.compute_ring[i]);
2235 if (r)
2236 return r;
2237 adev->gfx.compute_ring[i].ready = true;
2238 }
2239
2240 return 0;
2241}
2242
2243static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
2244{
2245 gfx_v6_0_cp_gfx_enable(adev, enable);
2246}
2247
2248static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
2249{
2250 return gfx_v6_0_cp_gfx_load_microcode(adev);
2251}
2252
2253static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2254 bool enable)
2255{
2256 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2257 u32 mask;
2258 int i;
2259
2260 if (enable)
2261 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2262 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2263 else
2264 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2265 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2266 WREG32(mmCP_INT_CNTL_RING0, tmp);
2267
2268 if (!enable) {
2269 /* read a gfx register */
2270 tmp = RREG32(mmDB_DEPTH_INFO);
2271
2272 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
2273 for (i = 0; i < adev->usec_timeout; i++) {
2274 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
2275 break;
2276 udelay(1);
2277 }
2278 }
2279}
2280
2281static int gfx_v6_0_cp_resume(struct amdgpu_device *adev)
2282{
2283 int r;
2284
2285 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2286
2287 r = gfx_v6_0_cp_load_microcode(adev);
2288 if (r)
2289 return r;
2290
2291 r = gfx_v6_0_cp_gfx_resume(adev);
2292 if (r)
2293 return r;
2294 r = gfx_v6_0_cp_compute_resume(adev);
2295 if (r)
2296 return r;
2297
2298 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2299
2300 return 0;
2301}
2302
2303static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2304{
2305 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2306 uint32_t seq = ring->fence_drv.sync_seq;
2307 uint64_t addr = ring->fence_drv.gpu_addr;
2308
2309 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2310 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
2311 WAIT_REG_MEM_FUNCTION(3) | /* equal */
2312 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
2313 amdgpu_ring_write(ring, addr & 0xfffffffc);
2314 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
2315 amdgpu_ring_write(ring, seq);
2316 amdgpu_ring_write(ring, 0xffffffff);
2317 amdgpu_ring_write(ring, 4); /* poll interval */
2318
2319 if (usepfp) {
2320 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2321 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2322 amdgpu_ring_write(ring, 0);
2323 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2324 amdgpu_ring_write(ring, 0);
2325 }
2326}
2327
2328static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2329 unsigned vmid, uint64_t pd_addr)
2330{
2331 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2332
2333 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
2334
2335 /* wait for the invalidate to complete */
2336 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2337 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
2338 WAIT_REG_MEM_ENGINE(0))); /* me */
2339 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
2340 amdgpu_ring_write(ring, 0);
2341 amdgpu_ring_write(ring, 0); /* ref */
2342 amdgpu_ring_write(ring, 0); /* mask */
2343 amdgpu_ring_write(ring, 0x20); /* poll interval */
2344
2345 if (usepfp) {
2346 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2347 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2348 amdgpu_ring_write(ring, 0x0);
2349
2350 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2351 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2352 amdgpu_ring_write(ring, 0);
2353 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2354 amdgpu_ring_write(ring, 0);
2355 }
2356}
2357
2358static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
2359 uint32_t reg, uint32_t val)
2360{
2361 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2362
2363 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2364 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
2365 WRITE_DATA_DST_SEL(0)));
2366 amdgpu_ring_write(ring, reg);
2367 amdgpu_ring_write(ring, 0);
2368 amdgpu_ring_write(ring, val);
2369}
2370
2371static void gfx_v6_0_rlc_fini(struct amdgpu_device *adev)
2372{
2373 amdgpu_bo_free_kernel(&adev->gfx.rlc.save_restore_obj, NULL, NULL);
2374 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, NULL, NULL);
2375 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, NULL, NULL);
2376}
2377
2378static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2379{
2380 const u32 *src_ptr;
2381 volatile u32 *dst_ptr;
2382 u32 dws, i;
2383 u64 reg_list_mc_addr;
2384 const struct cs_section_def *cs_data;
2385 int r;
2386
2387 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list;
2388 adev->gfx.rlc.reg_list_size =
2389 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
2390
2391 adev->gfx.rlc.cs_data = si_cs_data;
2392 src_ptr = adev->gfx.rlc.reg_list;
2393 dws = adev->gfx.rlc.reg_list_size;
2394 cs_data = adev->gfx.rlc.cs_data;
2395
2396 if (src_ptr) {
2397 /* save restore block */
2398 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
2399 AMDGPU_GEM_DOMAIN_VRAM,
2400 &adev->gfx.rlc.save_restore_obj,
2401 &adev->gfx.rlc.save_restore_gpu_addr,
2402 (void **)&adev->gfx.rlc.sr_ptr);
2403 if (r) {
2404 dev_warn(adev->dev, "(%d) create RLC sr bo failed\n",
2405 r);
2406 gfx_v6_0_rlc_fini(adev);
2407 return r;
2408 }
2409
2410 /* write the sr buffer */
2411 dst_ptr = adev->gfx.rlc.sr_ptr;
2412 for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)
2413 dst_ptr[i] = cpu_to_le32(src_ptr[i]);
2414
2415 amdgpu_bo_kunmap(adev->gfx.rlc.save_restore_obj);
2416 amdgpu_bo_unreserve(adev->gfx.rlc.save_restore_obj);
2417 }
2418
2419 if (cs_data) {
2420 /* clear state block */
2421 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev);
2422 dws = adev->gfx.rlc.clear_state_size + (256 / 4);
2423
2424 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
2425 AMDGPU_GEM_DOMAIN_VRAM,
2426 &adev->gfx.rlc.clear_state_obj,
2427 &adev->gfx.rlc.clear_state_gpu_addr,
2428 (void **)&adev->gfx.rlc.cs_ptr);
2429 if (r) {
2430 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
2431 gfx_v6_0_rlc_fini(adev);
2432 return r;
2433 }
2434
2435 /* set up the cs buffer */
2436 dst_ptr = adev->gfx.rlc.cs_ptr;
2437 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256;
2438 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));
2439 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
2440 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size);
2441 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]);
2442 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
2443 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2444 }
2445
2446 return 0;
2447}
2448
2449static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
2450{
2451 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
2452
2453 if (!enable) {
2454 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
2455 WREG32(mmSPI_LB_CU_MASK, 0x00ff);
2456 }
2457}
2458
2459static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2460{
2461 int i;
2462
2463 for (i = 0; i < adev->usec_timeout; i++) {
2464 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0)
2465 break;
2466 udelay(1);
2467 }
2468
2469 for (i = 0; i < adev->usec_timeout; i++) {
2470 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0)
2471 break;
2472 udelay(1);
2473 }
2474}
2475
2476static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
2477{
2478 u32 tmp;
2479
2480 tmp = RREG32(mmRLC_CNTL);
2481 if (tmp != rlc)
2482 WREG32(mmRLC_CNTL, rlc);
2483}
2484
2485static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2486{
2487 u32 data, orig;
2488
2489 orig = data = RREG32(mmRLC_CNTL);
2490
2491 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2492 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
2493 WREG32(mmRLC_CNTL, data);
2494
2495 gfx_v6_0_wait_for_rlc_serdes(adev);
2496 }
2497
2498 return orig;
2499}
2500
2501static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2502{
2503 WREG32(mmRLC_CNTL, 0);
2504
2505 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2506 gfx_v6_0_wait_for_rlc_serdes(adev);
2507}
2508
2509static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2510{
2511 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
2512
2513 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2514
2515 udelay(50);
2516}
2517
2518static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev)
2519{
2520 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2521 udelay(50);
2522 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2523 udelay(50);
2524}
2525
2526static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev)
2527{
2528 u32 tmp;
2529
2530 /* Enable LBPW only for DDR3 */
2531 tmp = RREG32(mmMC_SEQ_MISC0);
2532 if ((tmp & 0xF0000000) == 0xB0000000)
2533 return true;
2534 return false;
2535}
2536
2537static void gfx_v6_0_init_cg(struct amdgpu_device *adev)
2538{
2539}
2540
2541static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2542{
2543 u32 i;
2544 const struct rlc_firmware_header_v1_0 *hdr;
2545 const __le32 *fw_data;
2546 u32 fw_size;
2547
2548
2549 if (!adev->gfx.rlc_fw)
2550 return -EINVAL;
2551
2552 gfx_v6_0_rlc_stop(adev);
2553 gfx_v6_0_rlc_reset(adev);
2554 gfx_v6_0_init_pg(adev);
2555 gfx_v6_0_init_cg(adev);
2556
2557 WREG32(mmRLC_RL_BASE, 0);
2558 WREG32(mmRLC_RL_SIZE, 0);
2559 WREG32(mmRLC_LB_CNTL, 0);
2560 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff);
2561 WREG32(mmRLC_LB_CNTR_INIT, 0);
2562 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
2563
2564 WREG32(mmRLC_MC_CNTL, 0);
2565 WREG32(mmRLC_UCODE_CNTL, 0);
2566
2567 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
2568 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2569 fw_data = (const __le32 *)
2570 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2571
2572 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2573
2574 for (i = 0; i < fw_size; i++) {
2575 WREG32(mmRLC_UCODE_ADDR, i);
2576 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++));
2577 }
2578 WREG32(mmRLC_UCODE_ADDR, 0);
2579
2580 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
2581 gfx_v6_0_rlc_start(adev);
2582
2583 return 0;
2584}
2585
2586static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
2587{
2588 u32 data, orig, tmp;
2589
2590 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
2591
2592 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2593 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2594
2595 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080);
2596
2597 tmp = gfx_v6_0_halt_rlc(adev);
2598
2599 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2600 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2601 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff);
2602
2603 gfx_v6_0_wait_for_rlc_serdes(adev);
2604 gfx_v6_0_update_rlc(adev, tmp);
2605
2606 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff);
2607
2608 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2609 } else {
2610 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2611
2612 RREG32(mmCB_CGTT_SCLK_CTRL);
2613 RREG32(mmCB_CGTT_SCLK_CTRL);
2614 RREG32(mmCB_CGTT_SCLK_CTRL);
2615 RREG32(mmCB_CGTT_SCLK_CTRL);
2616
2617 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2618 }
2619
2620 if (orig != data)
2621 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
2622
2623}
2624
2625static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
2626{
2627
2628 u32 data, orig, tmp = 0;
2629
2630 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2631 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2632 data = 0x96940200;
2633 if (orig != data)
2634 WREG32(mmCGTS_SM_CTRL_REG, data);
2635
2636 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2637 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
2638 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2639 if (orig != data)
2640 WREG32(mmCP_MEM_SLP_CNTL, data);
2641 }
2642
2643 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2644 data &= 0xffffffc0;
2645 if (orig != data)
2646 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2647
2648 tmp = gfx_v6_0_halt_rlc(adev);
2649
2650 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2651 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2652 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff);
2653
2654 gfx_v6_0_update_rlc(adev, tmp);
2655 } else {
2656 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2657 data |= 0x00000003;
2658 if (orig != data)
2659 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2660
2661 data = RREG32(mmCP_MEM_SLP_CNTL);
2662 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2663 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2664 WREG32(mmCP_MEM_SLP_CNTL, data);
2665 }
2666 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2667 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK;
2668 if (orig != data)
2669 WREG32(mmCGTS_SM_CTRL_REG, data);
2670
2671 tmp = gfx_v6_0_halt_rlc(adev);
2672
2673 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2674 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2675 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff);
2676
2677 gfx_v6_0_update_rlc(adev, tmp);
2678 }
2679}
2680/*
2681static void gfx_v6_0_update_cg(struct amdgpu_device *adev,
2682 bool enable)
2683{
2684 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2685 if (enable) {
2686 gfx_v6_0_enable_mgcg(adev, true);
2687 gfx_v6_0_enable_cgcg(adev, true);
2688 } else {
2689 gfx_v6_0_enable_cgcg(adev, false);
2690 gfx_v6_0_enable_mgcg(adev, false);
2691 }
2692 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2693}
2694*/
2695
2696static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
2697 bool enable)
2698{
2699}
2700
2701static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
2702 bool enable)
2703{
2704}
2705
2706static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
2707{
2708 u32 data, orig;
2709
2710 orig = data = RREG32(mmRLC_PG_CNTL);
2711 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
2712 data &= ~0x8000;
2713 else
2714 data |= 0x8000;
2715 if (orig != data)
2716 WREG32(mmRLC_PG_CNTL, data);
2717}
2718
2719static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
2720{
2721}
2722/*
2723static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev)
2724{
2725 const __le32 *fw_data;
2726 volatile u32 *dst_ptr;
2727 int me, i, max_me = 4;
2728 u32 bo_offset = 0;
2729 u32 table_offset, table_size;
2730
2731 if (adev->asic_type == CHIP_KAVERI)
2732 max_me = 5;
2733
2734 if (adev->gfx.rlc.cp_table_ptr == NULL)
2735 return;
2736
2737 dst_ptr = adev->gfx.rlc.cp_table_ptr;
2738 for (me = 0; me < max_me; me++) {
2739 if (me == 0) {
2740 const struct gfx_firmware_header_v1_0 *hdr =
2741 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2742 fw_data = (const __le32 *)
2743 (adev->gfx.ce_fw->data +
2744 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2745 table_offset = le32_to_cpu(hdr->jt_offset);
2746 table_size = le32_to_cpu(hdr->jt_size);
2747 } else if (me == 1) {
2748 const struct gfx_firmware_header_v1_0 *hdr =
2749 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2750 fw_data = (const __le32 *)
2751 (adev->gfx.pfp_fw->data +
2752 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2753 table_offset = le32_to_cpu(hdr->jt_offset);
2754 table_size = le32_to_cpu(hdr->jt_size);
2755 } else if (me == 2) {
2756 const struct gfx_firmware_header_v1_0 *hdr =
2757 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2758 fw_data = (const __le32 *)
2759 (adev->gfx.me_fw->data +
2760 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2761 table_offset = le32_to_cpu(hdr->jt_offset);
2762 table_size = le32_to_cpu(hdr->jt_size);
2763 } else if (me == 3) {
2764 const struct gfx_firmware_header_v1_0 *hdr =
2765 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2766 fw_data = (const __le32 *)
2767 (adev->gfx.mec_fw->data +
2768 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2769 table_offset = le32_to_cpu(hdr->jt_offset);
2770 table_size = le32_to_cpu(hdr->jt_size);
2771 } else {
2772 const struct gfx_firmware_header_v1_0 *hdr =
2773 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2774 fw_data = (const __le32 *)
2775 (adev->gfx.mec2_fw->data +
2776 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2777 table_offset = le32_to_cpu(hdr->jt_offset);
2778 table_size = le32_to_cpu(hdr->jt_size);
2779 }
2780
2781 for (i = 0; i < table_size; i ++) {
2782 dst_ptr[bo_offset + i] =
2783 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
2784 }
2785
2786 bo_offset += table_size;
2787 }
2788}
2789*/
2790static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev,
2791 bool enable)
2792{
2793 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2794 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10));
2795 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1);
2796 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1);
2797 } else {
2798 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0);
2799 (void)RREG32(mmDB_RENDER_CONTROL);
2800 }
2801}
2802
2803static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev)
2804{
2805 u32 tmp;
2806
2807 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
2808
2809 tmp = RREG32(mmRLC_MAX_PG_CU);
2810 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
2811 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
2812 WREG32(mmRLC_MAX_PG_CU, tmp);
2813}
2814
2815static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
2816 bool enable)
2817{
2818 u32 data, orig;
2819
2820 orig = data = RREG32(mmRLC_PG_CNTL);
2821 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
2822 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2823 else
2824 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2825 if (orig != data)
2826 WREG32(mmRLC_PG_CNTL, data);
2827}
2828
2829static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
2830 bool enable)
2831{
2832 u32 data, orig;
2833
2834 orig = data = RREG32(mmRLC_PG_CNTL);
2835 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
2836 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2837 else
2838 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2839 if (orig != data)
2840 WREG32(mmRLC_PG_CNTL, data);
2841}
2842
2843static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev)
2844{
2845 u32 tmp;
2846
2847 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2848 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1);
2849 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2850
2851 tmp = RREG32(mmRLC_AUTO_PG_CTRL);
2852 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2853 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2854 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK;
2855 WREG32(mmRLC_AUTO_PG_CTRL, tmp);
2856}
2857
2858static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
2859{
2860 gfx_v6_0_enable_gfx_cgpg(adev, enable);
2861 gfx_v6_0_enable_gfx_static_mgpg(adev, enable);
2862 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable);
2863}
2864
2865static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev)
2866{
2867 u32 count = 0;
2868 const struct cs_section_def *sect = NULL;
2869 const struct cs_extent_def *ext = NULL;
2870
2871 if (adev->gfx.rlc.cs_data == NULL)
2872 return 0;
2873
2874 /* begin clear state */
2875 count += 2;
2876 /* context control state */
2877 count += 3;
2878
2879 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2880 for (ext = sect->section; ext->extent != NULL; ++ext) {
2881 if (sect->id == SECT_CONTEXT)
2882 count += 2 + ext->reg_count;
2883 else
2884 return 0;
2885 }
2886 }
2887 /* pa_sc_raster_config */
2888 count += 3;
2889 /* end clear state */
2890 count += 2;
2891 /* clear state */
2892 count += 2;
2893
2894 return count;
2895}
2896
2897static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
2898 volatile u32 *buffer)
2899{
2900 u32 count = 0, i;
2901 const struct cs_section_def *sect = NULL;
2902 const struct cs_extent_def *ext = NULL;
2903
2904 if (adev->gfx.rlc.cs_data == NULL)
2905 return;
2906 if (buffer == NULL)
2907 return;
2908
2909 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2910 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2911 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2912 buffer[count++] = cpu_to_le32(0x80000000);
2913 buffer[count++] = cpu_to_le32(0x80000000);
2914
2915 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2916 for (ext = sect->section; ext->extent != NULL; ++ext) {
2917 if (sect->id == SECT_CONTEXT) {
2918 buffer[count++] =
2919 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2920 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
2921 for (i = 0; i < ext->reg_count; i++)
2922 buffer[count++] = cpu_to_le32(ext->extent[i]);
2923 } else {
2924 return;
2925 }
2926 }
2927 }
2928
2929 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2930 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2931 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);
2932
2933 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2934 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
2935
2936 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
2937 buffer[count++] = cpu_to_le32(0);
2938}
2939
2940static void gfx_v6_0_init_pg(struct amdgpu_device *adev)
2941{
2942 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2943 AMD_PG_SUPPORT_GFX_SMG |
2944 AMD_PG_SUPPORT_GFX_DMG |
2945 AMD_PG_SUPPORT_CP |
2946 AMD_PG_SUPPORT_GDS |
2947 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2948 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true);
2949 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true);
2950 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2951 gfx_v6_0_init_gfx_cgpg(adev);
2952 gfx_v6_0_enable_cp_pg(adev, true);
2953 gfx_v6_0_enable_gds_pg(adev, true);
2954 } else {
2955 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2956 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2957
2958 }
2959 gfx_v6_0_init_ao_cu_mask(adev);
2960 gfx_v6_0_update_gfx_pg(adev, true);
2961 } else {
2962
2963 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2964 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2965 }
2966}
2967
2968static void gfx_v6_0_fini_pg(struct amdgpu_device *adev)
2969{
2970 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2971 AMD_PG_SUPPORT_GFX_SMG |
2972 AMD_PG_SUPPORT_GFX_DMG |
2973 AMD_PG_SUPPORT_CP |
2974 AMD_PG_SUPPORT_GDS |
2975 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2976 gfx_v6_0_update_gfx_pg(adev, false);
2977 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2978 gfx_v6_0_enable_cp_pg(adev, false);
2979 gfx_v6_0_enable_gds_pg(adev, false);
2980 }
2981 }
2982}
2983
2984static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2985{
2986 uint64_t clock;
2987
2988 mutex_lock(&adev->gfx.gpu_clock_mutex);
2989 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
2990 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
2991 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
2992 mutex_unlock(&adev->gfx.gpu_clock_mutex);
2993 return clock;
2994}
2995
2996static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2997{
2998 if (flags & AMDGPU_HAVE_CTX_SWITCH)
2999 gfx_v6_0_ring_emit_vgt_flush(ring);
3000 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3001 amdgpu_ring_write(ring, 0x80000000);
3002 amdgpu_ring_write(ring, 0);
3003}
3004
3005
3006static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
3007{
3008 WREG32(mmSQ_IND_INDEX,
3009 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
3010 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
3011 (address << SQ_IND_INDEX__INDEX__SHIFT) |
3012 (SQ_IND_INDEX__FORCE_READ_MASK));
3013 return RREG32(mmSQ_IND_DATA);
3014}
3015
3016static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
3017 uint32_t wave, uint32_t thread,
3018 uint32_t regno, uint32_t num, uint32_t *out)
3019{
3020 WREG32(mmSQ_IND_INDEX,
3021 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
3022 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
3023 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
3024 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
3025 (SQ_IND_INDEX__FORCE_READ_MASK) |
3026 (SQ_IND_INDEX__AUTO_INCR_MASK));
3027 while (num--)
3028 *(out++) = RREG32(mmSQ_IND_DATA);
3029}
3030
3031static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
3032{
3033 /* type 0 wave data */
3034 dst[(*no_fields)++] = 0;
3035 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
3036 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
3037 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
3038 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
3039 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
3040 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
3041 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
3042 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
3043 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
3044 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
3045 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
3046 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
3047 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
3048 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
3049 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
3050 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
3051 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
3052 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
3053}
3054
3055static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
3056 uint32_t wave, uint32_t start,
3057 uint32_t size, uint32_t *dst)
3058{
3059 wave_read_regs(
3060 adev, simd, wave, 0,
3061 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
3062}
3063
3064static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev,
3065 u32 me, u32 pipe, u32 q)
3066{
3067 DRM_INFO("Not implemented\n");
3068}
3069
3070static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
3071 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
3072 .select_se_sh = &gfx_v6_0_select_se_sh,
3073 .read_wave_data = &gfx_v6_0_read_wave_data,
3074 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs,
3075 .select_me_pipe_q = &gfx_v6_0_select_me_pipe_q
3076};
3077
3078static int gfx_v6_0_early_init(void *handle)
3079{
3080 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3081
3082 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
3083 adev->gfx.num_compute_rings = GFX6_NUM_COMPUTE_RINGS;
3084 adev->gfx.funcs = &gfx_v6_0_gfx_funcs;
3085 gfx_v6_0_set_ring_funcs(adev);
3086 gfx_v6_0_set_irq_funcs(adev);
3087
3088 return 0;
3089}
3090
3091static int gfx_v6_0_sw_init(void *handle)
3092{
3093 struct amdgpu_ring *ring;
3094 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3095 int i, r;
3096
3097 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
3098 if (r)
3099 return r;
3100
3101 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq);
3102 if (r)
3103 return r;
3104
3105 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq);
3106 if (r)
3107 return r;
3108
3109 gfx_v6_0_scratch_init(adev);
3110
3111 r = gfx_v6_0_init_microcode(adev);
3112 if (r) {
3113 DRM_ERROR("Failed to load gfx firmware!\n");
3114 return r;
3115 }
3116
3117 r = gfx_v6_0_rlc_init(adev);
3118 if (r) {
3119 DRM_ERROR("Failed to init rlc BOs!\n");
3120 return r;
3121 }
3122
3123 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3124 ring = &adev->gfx.gfx_ring[i];
3125 ring->ring_obj = NULL;
3126 sprintf(ring->name, "gfx");
3127 r = amdgpu_ring_init(adev, ring, 1024,
3128 &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
3129 if (r)
3130 return r;
3131 }
3132
3133 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3134 unsigned irq_type;
3135
3136 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
3137 DRM_ERROR("Too many (%d) compute rings!\n", i);
3138 break;
3139 }
3140 ring = &adev->gfx.compute_ring[i];
3141 ring->ring_obj = NULL;
3142 ring->use_doorbell = false;
3143 ring->doorbell_index = 0;
3144 ring->me = 1;
3145 ring->pipe = i;
3146 ring->queue = i;
3147 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
3148 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
3149 r = amdgpu_ring_init(adev, ring, 1024,
3150 &adev->gfx.eop_irq, irq_type);
3151 if (r)
3152 return r;
3153 }
3154
3155 return r;
3156}
3157
3158static int gfx_v6_0_sw_fini(void *handle)
3159{
3160 int i;
3161 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3162
3163 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3164 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
3165 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3166 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
3167
3168 gfx_v6_0_rlc_fini(adev);
3169
3170 return 0;
3171}
3172
3173static int gfx_v6_0_hw_init(void *handle)
3174{
3175 int r;
3176 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3177
3178 gfx_v6_0_gpu_init(adev);
3179
3180 r = gfx_v6_0_rlc_resume(adev);
3181 if (r)
3182 return r;
3183
3184 r = gfx_v6_0_cp_resume(adev);
3185 if (r)
3186 return r;
3187
3188 adev->gfx.ce_ram_size = 0x8000;
3189
3190 return r;
3191}
3192
3193static int gfx_v6_0_hw_fini(void *handle)
3194{
3195 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3196
3197 gfx_v6_0_cp_enable(adev, false);
3198 gfx_v6_0_rlc_stop(adev);
3199 gfx_v6_0_fini_pg(adev);
3200
3201 return 0;
3202}
3203
3204static int gfx_v6_0_suspend(void *handle)
3205{
3206 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3207
3208 return gfx_v6_0_hw_fini(adev);
3209}
3210
3211static int gfx_v6_0_resume(void *handle)
3212{
3213 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3214
3215 return gfx_v6_0_hw_init(adev);
3216}
3217
3218static bool gfx_v6_0_is_idle(void *handle)
3219{
3220 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3221
3222 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
3223 return false;
3224 else
3225 return true;
3226}
3227
3228static int gfx_v6_0_wait_for_idle(void *handle)
3229{
3230 unsigned i;
3231 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3232
3233 for (i = 0; i < adev->usec_timeout; i++) {
3234 if (gfx_v6_0_is_idle(handle))
3235 return 0;
3236 udelay(1);
3237 }
3238 return -ETIMEDOUT;
3239}
3240
3241static int gfx_v6_0_soft_reset(void *handle)
3242{
3243 return 0;
3244}
3245
3246static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3247 enum amdgpu_interrupt_state state)
3248{
3249 u32 cp_int_cntl;
3250
3251 switch (state) {
3252 case AMDGPU_IRQ_STATE_DISABLE:
3253 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3254 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3255 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3256 break;
3257 case AMDGPU_IRQ_STATE_ENABLE:
3258 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3259 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3260 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3261 break;
3262 default:
3263 break;
3264 }
3265}
3266
3267static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3268 int ring,
3269 enum amdgpu_interrupt_state state)
3270{
3271 u32 cp_int_cntl;
3272 switch (state){
3273 case AMDGPU_IRQ_STATE_DISABLE:
3274 if (ring == 0) {
3275 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3276 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3277 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3278 break;
3279 } else {
3280 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3281 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3282 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3283 break;
3284
3285 }
3286 case AMDGPU_IRQ_STATE_ENABLE:
3287 if (ring == 0) {
3288 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3289 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3290 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3291 break;
3292 } else {
3293 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3294 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3295 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3296 break;
3297
3298 }
3299
3300 default:
3301 BUG();
3302 break;
3303
3304 }
3305}
3306
3307static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3308 struct amdgpu_irq_src *src,
3309 unsigned type,
3310 enum amdgpu_interrupt_state state)
3311{
3312 u32 cp_int_cntl;
3313
3314 switch (state) {
3315 case AMDGPU_IRQ_STATE_DISABLE:
3316 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3317 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3318 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3319 break;
3320 case AMDGPU_IRQ_STATE_ENABLE:
3321 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3322 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3323 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3324 break;
3325 default:
3326 break;
3327 }
3328
3329 return 0;
3330}
3331
3332static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3333 struct amdgpu_irq_src *src,
3334 unsigned type,
3335 enum amdgpu_interrupt_state state)
3336{
3337 u32 cp_int_cntl;
3338
3339 switch (state) {
3340 case AMDGPU_IRQ_STATE_DISABLE:
3341 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3342 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3343 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3344 break;
3345 case AMDGPU_IRQ_STATE_ENABLE:
3346 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3347 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3348 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3349 break;
3350 default:
3351 break;
3352 }
3353
3354 return 0;
3355}
3356
3357static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3358 struct amdgpu_irq_src *src,
3359 unsigned type,
3360 enum amdgpu_interrupt_state state)
3361{
3362 switch (type) {
3363 case AMDGPU_CP_IRQ_GFX_EOP:
3364 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state);
3365 break;
3366 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3367 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state);
3368 break;
3369 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3370 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state);
3371 break;
3372 default:
3373 break;
3374 }
3375 return 0;
3376}
3377
3378static int gfx_v6_0_eop_irq(struct amdgpu_device *adev,
3379 struct amdgpu_irq_src *source,
3380 struct amdgpu_iv_entry *entry)
3381{
3382 switch (entry->ring_id) {
3383 case 0:
3384 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3385 break;
3386 case 1:
3387 case 2:
3388 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]);
3389 break;
3390 default:
3391 break;
3392 }
3393 return 0;
3394}
3395
3396static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev,
3397 struct amdgpu_irq_src *source,
3398 struct amdgpu_iv_entry *entry)
3399{
3400 DRM_ERROR("Illegal register access in command stream\n");
3401 schedule_work(&adev->reset_work);
3402 return 0;
3403}
3404
3405static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev,
3406 struct amdgpu_irq_src *source,
3407 struct amdgpu_iv_entry *entry)
3408{
3409 DRM_ERROR("Illegal instruction in command stream\n");
3410 schedule_work(&adev->reset_work);
3411 return 0;
3412}
3413
3414static int gfx_v6_0_set_clockgating_state(void *handle,
3415 enum amd_clockgating_state state)
3416{
3417 bool gate = false;
3418 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3419
3420 if (state == AMD_CG_STATE_GATE)
3421 gate = true;
3422
3423 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
3424 if (gate) {
3425 gfx_v6_0_enable_mgcg(adev, true);
3426 gfx_v6_0_enable_cgcg(adev, true);
3427 } else {
3428 gfx_v6_0_enable_cgcg(adev, false);
3429 gfx_v6_0_enable_mgcg(adev, false);
3430 }
3431 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
3432
3433 return 0;
3434}
3435
3436static int gfx_v6_0_set_powergating_state(void *handle,
3437 enum amd_powergating_state state)
3438{
3439 bool gate = false;
3440 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3441
3442 if (state == AMD_PG_STATE_GATE)
3443 gate = true;
3444
3445 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3446 AMD_PG_SUPPORT_GFX_SMG |
3447 AMD_PG_SUPPORT_GFX_DMG |
3448 AMD_PG_SUPPORT_CP |
3449 AMD_PG_SUPPORT_GDS |
3450 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3451 gfx_v6_0_update_gfx_pg(adev, gate);
3452 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3453 gfx_v6_0_enable_cp_pg(adev, gate);
3454 gfx_v6_0_enable_gds_pg(adev, gate);
3455 }
3456 }
3457
3458 return 0;
3459}
3460
3461static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
3462 .name = "gfx_v6_0",
3463 .early_init = gfx_v6_0_early_init,
3464 .late_init = NULL,
3465 .sw_init = gfx_v6_0_sw_init,
3466 .sw_fini = gfx_v6_0_sw_fini,
3467 .hw_init = gfx_v6_0_hw_init,
3468 .hw_fini = gfx_v6_0_hw_fini,
3469 .suspend = gfx_v6_0_suspend,
3470 .resume = gfx_v6_0_resume,
3471 .is_idle = gfx_v6_0_is_idle,
3472 .wait_for_idle = gfx_v6_0_wait_for_idle,
3473 .soft_reset = gfx_v6_0_soft_reset,
3474 .set_clockgating_state = gfx_v6_0_set_clockgating_state,
3475 .set_powergating_state = gfx_v6_0_set_powergating_state,
3476};
3477
3478static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
3479 .type = AMDGPU_RING_TYPE_GFX,
3480 .align_mask = 0xff,
3481 .nop = 0x80000000,
3482 .support_64bit_ptrs = false,
3483 .get_rptr = gfx_v6_0_ring_get_rptr,
3484 .get_wptr = gfx_v6_0_ring_get_wptr,
3485 .set_wptr = gfx_v6_0_ring_set_wptr_gfx,
3486 .emit_frame_size =
3487 5 + 5 + /* hdp flush / invalidate */
3488 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3489 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
3490 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
3491 3 + 2, /* gfx_v6_ring_emit_cntxcntl including vgt flush */
3492 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3493 .emit_ib = gfx_v6_0_ring_emit_ib,
3494 .emit_fence = gfx_v6_0_ring_emit_fence,
3495 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3496 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3497 .test_ring = gfx_v6_0_ring_test_ring,
3498 .test_ib = gfx_v6_0_ring_test_ib,
3499 .insert_nop = amdgpu_ring_insert_nop,
3500 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
3501 .emit_wreg = gfx_v6_0_ring_emit_wreg,
3502};
3503
3504static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
3505 .type = AMDGPU_RING_TYPE_COMPUTE,
3506 .align_mask = 0xff,
3507 .nop = 0x80000000,
3508 .get_rptr = gfx_v6_0_ring_get_rptr,
3509 .get_wptr = gfx_v6_0_ring_get_wptr,
3510 .set_wptr = gfx_v6_0_ring_set_wptr_compute,
3511 .emit_frame_size =
3512 5 + 5 + /* hdp flush / invalidate */
3513 7 + /* gfx_v6_0_ring_emit_pipeline_sync */
3514 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */
3515 14 + 14 + 14, /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3516 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3517 .emit_ib = gfx_v6_0_ring_emit_ib,
3518 .emit_fence = gfx_v6_0_ring_emit_fence,
3519 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3520 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3521 .test_ring = gfx_v6_0_ring_test_ring,
3522 .test_ib = gfx_v6_0_ring_test_ib,
3523 .insert_nop = amdgpu_ring_insert_nop,
3524 .emit_wreg = gfx_v6_0_ring_emit_wreg,
3525};
3526
3527static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)
3528{
3529 int i;
3530
3531 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3532 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx;
3533 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3534 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute;
3535}
3536
3537static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = {
3538 .set = gfx_v6_0_set_eop_interrupt_state,
3539 .process = gfx_v6_0_eop_irq,
3540};
3541
3542static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = {
3543 .set = gfx_v6_0_set_priv_reg_fault_state,
3544 .process = gfx_v6_0_priv_reg_irq,
3545};
3546
3547static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = {
3548 .set = gfx_v6_0_set_priv_inst_fault_state,
3549 .process = gfx_v6_0_priv_inst_irq,
3550};
3551
3552static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3553{
3554 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3555 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs;
3556
3557 adev->gfx.priv_reg_irq.num_types = 1;
3558 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs;
3559
3560 adev->gfx.priv_inst_irq.num_types = 1;
3561 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs;
3562}
3563
3564static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
3565{
3566 int i, j, k, counter, active_cu_number = 0;
3567 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3568 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
3569 unsigned disable_masks[4 * 2];
3570 u32 ao_cu_num;
3571
3572 if (adev->flags & AMD_IS_APU)
3573 ao_cu_num = 2;
3574 else
3575 ao_cu_num = adev->gfx.config.max_cu_per_sh;
3576
3577 memset(cu_info, 0, sizeof(*cu_info));
3578
3579 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
3580
3581 mutex_lock(&adev->grbm_idx_mutex);
3582 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3583 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3584 mask = 1;
3585 ao_bitmap = 0;
3586 counter = 0;
3587 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
3588 if (i < 4 && j < 2)
3589 gfx_v6_0_set_user_cu_inactive_bitmap(
3590 adev, disable_masks[i * 2 + j]);
3591 bitmap = gfx_v6_0_get_cu_enabled(adev);
3592 cu_info->bitmap[i][j] = bitmap;
3593
3594 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
3595 if (bitmap & mask) {
3596 if (counter < ao_cu_num)
3597 ao_bitmap |= mask;
3598 counter ++;
3599 }
3600 mask <<= 1;
3601 }
3602 active_cu_number += counter;
3603 if (i < 2 && j < 2)
3604 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3605 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
3606 }
3607 }
3608
3609 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
3610 mutex_unlock(&adev->grbm_idx_mutex);
3611
3612 cu_info->number = active_cu_number;
3613 cu_info->ao_cu_mask = ao_cu_mask;
3614}
3615
3616const struct amdgpu_ip_block_version gfx_v6_0_ip_block =
3617{
3618 .type = AMD_IP_BLOCK_TYPE_GFX,
3619 .major = 6,
3620 .minor = 0,
3621 .rev = 0,
3622 .funcs = &gfx_v6_0_ip_funcs,
3623};
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <linux/firmware.h>
24#include <linux/module.h>
25
26#include "amdgpu.h"
27#include "amdgpu_ih.h"
28#include "amdgpu_gfx.h"
29#include "amdgpu_ucode.h"
30#include "clearstate_si.h"
31#include "bif/bif_3_0_d.h"
32#include "bif/bif_3_0_sh_mask.h"
33#include "oss/oss_1_0_d.h"
34#include "oss/oss_1_0_sh_mask.h"
35#include "gca/gfx_6_0_d.h"
36#include "gca/gfx_6_0_sh_mask.h"
37#include "gmc/gmc_6_0_d.h"
38#include "gmc/gmc_6_0_sh_mask.h"
39#include "dce/dce_6_0_d.h"
40#include "dce/dce_6_0_sh_mask.h"
41#include "gca/gfx_7_2_enum.h"
42#include "si_enums.h"
43#include "si.h"
44
45static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev);
46static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev);
47static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev);
48
49MODULE_FIRMWARE("amdgpu/tahiti_pfp.bin");
50MODULE_FIRMWARE("amdgpu/tahiti_me.bin");
51MODULE_FIRMWARE("amdgpu/tahiti_ce.bin");
52MODULE_FIRMWARE("amdgpu/tahiti_rlc.bin");
53
54MODULE_FIRMWARE("amdgpu/pitcairn_pfp.bin");
55MODULE_FIRMWARE("amdgpu/pitcairn_me.bin");
56MODULE_FIRMWARE("amdgpu/pitcairn_ce.bin");
57MODULE_FIRMWARE("amdgpu/pitcairn_rlc.bin");
58
59MODULE_FIRMWARE("amdgpu/verde_pfp.bin");
60MODULE_FIRMWARE("amdgpu/verde_me.bin");
61MODULE_FIRMWARE("amdgpu/verde_ce.bin");
62MODULE_FIRMWARE("amdgpu/verde_rlc.bin");
63
64MODULE_FIRMWARE("amdgpu/oland_pfp.bin");
65MODULE_FIRMWARE("amdgpu/oland_me.bin");
66MODULE_FIRMWARE("amdgpu/oland_ce.bin");
67MODULE_FIRMWARE("amdgpu/oland_rlc.bin");
68
69MODULE_FIRMWARE("amdgpu/hainan_pfp.bin");
70MODULE_FIRMWARE("amdgpu/hainan_me.bin");
71MODULE_FIRMWARE("amdgpu/hainan_ce.bin");
72MODULE_FIRMWARE("amdgpu/hainan_rlc.bin");
73
74static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev);
75static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev, volatile u32 *buffer);
76//static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev);
77static void gfx_v6_0_init_pg(struct amdgpu_device *adev);
78
79#define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT)
80#define PIPE_CONFIG(x) ((x) << GB_TILE_MODE0__PIPE_CONFIG__SHIFT)
81#define TILE_SPLIT(x) ((x) << GB_TILE_MODE0__TILE_SPLIT__SHIFT)
82#define MICRO_TILE_MODE(x) ((x) << 0)
83#define SAMPLE_SPLIT(x) ((x) << GB_TILE_MODE0__SAMPLE_SPLIT__SHIFT)
84#define BANK_WIDTH(x) ((x) << 14)
85#define BANK_HEIGHT(x) ((x) << 16)
86#define MACRO_TILE_ASPECT(x) ((x) << 18)
87#define NUM_BANKS(x) ((x) << 20)
88
89static const u32 verde_rlc_save_restore_register_list[] =
90{
91 (0x8000 << 16) | (0x98f4 >> 2),
92 0x00000000,
93 (0x8040 << 16) | (0x98f4 >> 2),
94 0x00000000,
95 (0x8000 << 16) | (0xe80 >> 2),
96 0x00000000,
97 (0x8040 << 16) | (0xe80 >> 2),
98 0x00000000,
99 (0x8000 << 16) | (0x89bc >> 2),
100 0x00000000,
101 (0x8040 << 16) | (0x89bc >> 2),
102 0x00000000,
103 (0x8000 << 16) | (0x8c1c >> 2),
104 0x00000000,
105 (0x8040 << 16) | (0x8c1c >> 2),
106 0x00000000,
107 (0x9c00 << 16) | (0x98f0 >> 2),
108 0x00000000,
109 (0x9c00 << 16) | (0xe7c >> 2),
110 0x00000000,
111 (0x8000 << 16) | (0x9148 >> 2),
112 0x00000000,
113 (0x8040 << 16) | (0x9148 >> 2),
114 0x00000000,
115 (0x9c00 << 16) | (0x9150 >> 2),
116 0x00000000,
117 (0x9c00 << 16) | (0x897c >> 2),
118 0x00000000,
119 (0x9c00 << 16) | (0x8d8c >> 2),
120 0x00000000,
121 (0x9c00 << 16) | (0xac54 >> 2),
122 0X00000000,
123 0x3,
124 (0x9c00 << 16) | (0x98f8 >> 2),
125 0x00000000,
126 (0x9c00 << 16) | (0x9910 >> 2),
127 0x00000000,
128 (0x9c00 << 16) | (0x9914 >> 2),
129 0x00000000,
130 (0x9c00 << 16) | (0x9918 >> 2),
131 0x00000000,
132 (0x9c00 << 16) | (0x991c >> 2),
133 0x00000000,
134 (0x9c00 << 16) | (0x9920 >> 2),
135 0x00000000,
136 (0x9c00 << 16) | (0x9924 >> 2),
137 0x00000000,
138 (0x9c00 << 16) | (0x9928 >> 2),
139 0x00000000,
140 (0x9c00 << 16) | (0x992c >> 2),
141 0x00000000,
142 (0x9c00 << 16) | (0x9930 >> 2),
143 0x00000000,
144 (0x9c00 << 16) | (0x9934 >> 2),
145 0x00000000,
146 (0x9c00 << 16) | (0x9938 >> 2),
147 0x00000000,
148 (0x9c00 << 16) | (0x993c >> 2),
149 0x00000000,
150 (0x9c00 << 16) | (0x9940 >> 2),
151 0x00000000,
152 (0x9c00 << 16) | (0x9944 >> 2),
153 0x00000000,
154 (0x9c00 << 16) | (0x9948 >> 2),
155 0x00000000,
156 (0x9c00 << 16) | (0x994c >> 2),
157 0x00000000,
158 (0x9c00 << 16) | (0x9950 >> 2),
159 0x00000000,
160 (0x9c00 << 16) | (0x9954 >> 2),
161 0x00000000,
162 (0x9c00 << 16) | (0x9958 >> 2),
163 0x00000000,
164 (0x9c00 << 16) | (0x995c >> 2),
165 0x00000000,
166 (0x9c00 << 16) | (0x9960 >> 2),
167 0x00000000,
168 (0x9c00 << 16) | (0x9964 >> 2),
169 0x00000000,
170 (0x9c00 << 16) | (0x9968 >> 2),
171 0x00000000,
172 (0x9c00 << 16) | (0x996c >> 2),
173 0x00000000,
174 (0x9c00 << 16) | (0x9970 >> 2),
175 0x00000000,
176 (0x9c00 << 16) | (0x9974 >> 2),
177 0x00000000,
178 (0x9c00 << 16) | (0x9978 >> 2),
179 0x00000000,
180 (0x9c00 << 16) | (0x997c >> 2),
181 0x00000000,
182 (0x9c00 << 16) | (0x9980 >> 2),
183 0x00000000,
184 (0x9c00 << 16) | (0x9984 >> 2),
185 0x00000000,
186 (0x9c00 << 16) | (0x9988 >> 2),
187 0x00000000,
188 (0x9c00 << 16) | (0x998c >> 2),
189 0x00000000,
190 (0x9c00 << 16) | (0x8c00 >> 2),
191 0x00000000,
192 (0x9c00 << 16) | (0x8c14 >> 2),
193 0x00000000,
194 (0x9c00 << 16) | (0x8c04 >> 2),
195 0x00000000,
196 (0x9c00 << 16) | (0x8c08 >> 2),
197 0x00000000,
198 (0x8000 << 16) | (0x9b7c >> 2),
199 0x00000000,
200 (0x8040 << 16) | (0x9b7c >> 2),
201 0x00000000,
202 (0x8000 << 16) | (0xe84 >> 2),
203 0x00000000,
204 (0x8040 << 16) | (0xe84 >> 2),
205 0x00000000,
206 (0x8000 << 16) | (0x89c0 >> 2),
207 0x00000000,
208 (0x8040 << 16) | (0x89c0 >> 2),
209 0x00000000,
210 (0x8000 << 16) | (0x914c >> 2),
211 0x00000000,
212 (0x8040 << 16) | (0x914c >> 2),
213 0x00000000,
214 (0x8000 << 16) | (0x8c20 >> 2),
215 0x00000000,
216 (0x8040 << 16) | (0x8c20 >> 2),
217 0x00000000,
218 (0x8000 << 16) | (0x9354 >> 2),
219 0x00000000,
220 (0x8040 << 16) | (0x9354 >> 2),
221 0x00000000,
222 (0x9c00 << 16) | (0x9060 >> 2),
223 0x00000000,
224 (0x9c00 << 16) | (0x9364 >> 2),
225 0x00000000,
226 (0x9c00 << 16) | (0x9100 >> 2),
227 0x00000000,
228 (0x9c00 << 16) | (0x913c >> 2),
229 0x00000000,
230 (0x8000 << 16) | (0x90e0 >> 2),
231 0x00000000,
232 (0x8000 << 16) | (0x90e4 >> 2),
233 0x00000000,
234 (0x8000 << 16) | (0x90e8 >> 2),
235 0x00000000,
236 (0x8040 << 16) | (0x90e0 >> 2),
237 0x00000000,
238 (0x8040 << 16) | (0x90e4 >> 2),
239 0x00000000,
240 (0x8040 << 16) | (0x90e8 >> 2),
241 0x00000000,
242 (0x9c00 << 16) | (0x8bcc >> 2),
243 0x00000000,
244 (0x9c00 << 16) | (0x8b24 >> 2),
245 0x00000000,
246 (0x9c00 << 16) | (0x88c4 >> 2),
247 0x00000000,
248 (0x9c00 << 16) | (0x8e50 >> 2),
249 0x00000000,
250 (0x9c00 << 16) | (0x8c0c >> 2),
251 0x00000000,
252 (0x9c00 << 16) | (0x8e58 >> 2),
253 0x00000000,
254 (0x9c00 << 16) | (0x8e5c >> 2),
255 0x00000000,
256 (0x9c00 << 16) | (0x9508 >> 2),
257 0x00000000,
258 (0x9c00 << 16) | (0x950c >> 2),
259 0x00000000,
260 (0x9c00 << 16) | (0x9494 >> 2),
261 0x00000000,
262 (0x9c00 << 16) | (0xac0c >> 2),
263 0x00000000,
264 (0x9c00 << 16) | (0xac10 >> 2),
265 0x00000000,
266 (0x9c00 << 16) | (0xac14 >> 2),
267 0x00000000,
268 (0x9c00 << 16) | (0xae00 >> 2),
269 0x00000000,
270 (0x9c00 << 16) | (0xac08 >> 2),
271 0x00000000,
272 (0x9c00 << 16) | (0x88d4 >> 2),
273 0x00000000,
274 (0x9c00 << 16) | (0x88c8 >> 2),
275 0x00000000,
276 (0x9c00 << 16) | (0x88cc >> 2),
277 0x00000000,
278 (0x9c00 << 16) | (0x89b0 >> 2),
279 0x00000000,
280 (0x9c00 << 16) | (0x8b10 >> 2),
281 0x00000000,
282 (0x9c00 << 16) | (0x8a14 >> 2),
283 0x00000000,
284 (0x9c00 << 16) | (0x9830 >> 2),
285 0x00000000,
286 (0x9c00 << 16) | (0x9834 >> 2),
287 0x00000000,
288 (0x9c00 << 16) | (0x9838 >> 2),
289 0x00000000,
290 (0x9c00 << 16) | (0x9a10 >> 2),
291 0x00000000,
292 (0x8000 << 16) | (0x9870 >> 2),
293 0x00000000,
294 (0x8000 << 16) | (0x9874 >> 2),
295 0x00000000,
296 (0x8001 << 16) | (0x9870 >> 2),
297 0x00000000,
298 (0x8001 << 16) | (0x9874 >> 2),
299 0x00000000,
300 (0x8040 << 16) | (0x9870 >> 2),
301 0x00000000,
302 (0x8040 << 16) | (0x9874 >> 2),
303 0x00000000,
304 (0x8041 << 16) | (0x9870 >> 2),
305 0x00000000,
306 (0x8041 << 16) | (0x9874 >> 2),
307 0x00000000,
308 0x00000000
309};
310
311static int gfx_v6_0_init_microcode(struct amdgpu_device *adev)
312{
313 const char *chip_name;
314 int err;
315 const struct gfx_firmware_header_v1_0 *cp_hdr;
316 const struct rlc_firmware_header_v1_0 *rlc_hdr;
317
318 DRM_DEBUG("\n");
319
320 switch (adev->asic_type) {
321 case CHIP_TAHITI:
322 chip_name = "tahiti";
323 break;
324 case CHIP_PITCAIRN:
325 chip_name = "pitcairn";
326 break;
327 case CHIP_VERDE:
328 chip_name = "verde";
329 break;
330 case CHIP_OLAND:
331 chip_name = "oland";
332 break;
333 case CHIP_HAINAN:
334 chip_name = "hainan";
335 break;
336 default: BUG();
337 }
338
339 err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw,
340 "amdgpu/%s_pfp.bin", chip_name);
341 if (err)
342 goto out;
343 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
344 adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
345 adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
346
347 err = amdgpu_ucode_request(adev, &adev->gfx.me_fw,
348 "amdgpu/%s_me.bin", chip_name);
349 if (err)
350 goto out;
351 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
352 adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
353 adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
354
355 err = amdgpu_ucode_request(adev, &adev->gfx.ce_fw,
356 "amdgpu/%s_ce.bin", chip_name);
357 if (err)
358 goto out;
359 cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
360 adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
361 adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
362
363 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
364 "amdgpu/%s_rlc.bin", chip_name);
365 if (err)
366 goto out;
367 rlc_hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
368 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
369 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
370
371out:
372 if (err) {
373 pr_err("gfx6: Failed to load firmware %s gfx firmware\n", chip_name);
374 amdgpu_ucode_release(&adev->gfx.pfp_fw);
375 amdgpu_ucode_release(&adev->gfx.me_fw);
376 amdgpu_ucode_release(&adev->gfx.ce_fw);
377 amdgpu_ucode_release(&adev->gfx.rlc_fw);
378 }
379 return err;
380}
381
382static void gfx_v6_0_tiling_mode_table_init(struct amdgpu_device *adev)
383{
384 const u32 num_tile_mode_states = ARRAY_SIZE(adev->gfx.config.tile_mode_array);
385 u32 reg_offset, split_equal_to_row_size, *tilemode;
386
387 memset(adev->gfx.config.tile_mode_array, 0, sizeof(adev->gfx.config.tile_mode_array));
388 tilemode = adev->gfx.config.tile_mode_array;
389
390 switch (adev->gfx.config.mem_row_size_in_kb) {
391 case 1:
392 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
393 break;
394 case 2:
395 default:
396 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
397 break;
398 case 4:
399 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
400 break;
401 }
402
403 if (adev->asic_type == CHIP_VERDE) {
404 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
405 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
406 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
407 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
408 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
409 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
410 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
411 NUM_BANKS(ADDR_SURF_16_BANK);
412 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
413 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
414 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
415 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
416 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
417 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
418 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
419 NUM_BANKS(ADDR_SURF_16_BANK);
420 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
421 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
422 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
423 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
424 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
425 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
426 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
427 NUM_BANKS(ADDR_SURF_16_BANK);
428 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
429 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
430 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
431 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
432 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
433 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
434 NUM_BANKS(ADDR_SURF_8_BANK) |
435 TILE_SPLIT(split_equal_to_row_size);
436 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
437 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
438 PIPE_CONFIG(ADDR_SURF_P4_8x16);
439 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
440 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
441 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
442 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
443 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
444 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
445 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
446 NUM_BANKS(ADDR_SURF_4_BANK);
447 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
448 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
449 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
450 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
451 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
452 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
453 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
454 NUM_BANKS(ADDR_SURF_4_BANK);
455 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
456 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
457 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
458 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
459 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
460 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
461 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
462 NUM_BANKS(ADDR_SURF_2_BANK);
463 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
464 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
465 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
466 PIPE_CONFIG(ADDR_SURF_P4_8x16);
467 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
468 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
469 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
470 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
471 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
472 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
473 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
474 NUM_BANKS(ADDR_SURF_16_BANK);
475 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
476 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
477 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
478 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
479 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
480 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
481 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
482 NUM_BANKS(ADDR_SURF_16_BANK);
483 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
484 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
485 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
486 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
487 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
488 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
489 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
490 NUM_BANKS(ADDR_SURF_16_BANK);
491 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
492 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
493 PIPE_CONFIG(ADDR_SURF_P4_8x16);
494 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
495 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
496 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
497 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
498 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
499 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
500 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
501 NUM_BANKS(ADDR_SURF_16_BANK);
502 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
503 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
504 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
505 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
506 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
507 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
508 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
509 NUM_BANKS(ADDR_SURF_16_BANK);
510 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
511 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
512 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
513 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
514 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
515 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
516 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
517 NUM_BANKS(ADDR_SURF_16_BANK);
518 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
519 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
520 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
521 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
522 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
523 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
524 NUM_BANKS(ADDR_SURF_16_BANK) |
525 TILE_SPLIT(split_equal_to_row_size);
526 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
527 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
528 PIPE_CONFIG(ADDR_SURF_P4_8x16);
529 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
530 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
531 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
532 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
533 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
534 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
535 NUM_BANKS(ADDR_SURF_16_BANK) |
536 TILE_SPLIT(split_equal_to_row_size);
537 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
538 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
539 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
540 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
541 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
542 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
543 NUM_BANKS(ADDR_SURF_16_BANK) |
544 TILE_SPLIT(split_equal_to_row_size);
545 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
546 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
547 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
548 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
549 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
550 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
551 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
552 NUM_BANKS(ADDR_SURF_8_BANK);
553 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
554 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
555 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
556 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
557 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
558 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
559 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
560 NUM_BANKS(ADDR_SURF_8_BANK);
561 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
562 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
563 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
564 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
565 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
566 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
567 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
568 NUM_BANKS(ADDR_SURF_4_BANK);
569 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
570 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
571 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
572 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
573 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
574 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
575 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
576 NUM_BANKS(ADDR_SURF_4_BANK);
577 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
578 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
579 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
580 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
581 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
582 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
583 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
584 NUM_BANKS(ADDR_SURF_2_BANK);
585 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
586 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
587 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
588 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
589 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
590 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
591 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
592 NUM_BANKS(ADDR_SURF_2_BANK);
593 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
594 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
595 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
596 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
597 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
598 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
599 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
600 NUM_BANKS(ADDR_SURF_2_BANK);
601 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
602 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
603 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
604 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
605 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
606 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
607 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
608 NUM_BANKS(ADDR_SURF_2_BANK);
609 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
610 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
611 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
612 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
613 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
614 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
615 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
616 NUM_BANKS(ADDR_SURF_2_BANK);
617 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
618 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
619 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
620 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
621 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
622 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
623 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
624 NUM_BANKS(ADDR_SURF_2_BANK);
625 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
626 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
627 } else if (adev->asic_type == CHIP_OLAND) {
628 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
629 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
630 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
631 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
632 NUM_BANKS(ADDR_SURF_16_BANK) |
633 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
634 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
635 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
636 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
637 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
638 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
639 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
640 NUM_BANKS(ADDR_SURF_16_BANK) |
641 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
642 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
643 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
644 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
645 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
646 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
647 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
648 NUM_BANKS(ADDR_SURF_16_BANK) |
649 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
650 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
651 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
652 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
653 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
654 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
655 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
656 NUM_BANKS(ADDR_SURF_16_BANK) |
657 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
658 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
659 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
660 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
661 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
662 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
663 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
664 NUM_BANKS(ADDR_SURF_16_BANK) |
665 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
666 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
667 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
668 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
669 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
670 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
671 TILE_SPLIT(split_equal_to_row_size) |
672 NUM_BANKS(ADDR_SURF_16_BANK) |
673 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
674 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
675 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
676 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
677 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
678 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
679 TILE_SPLIT(split_equal_to_row_size) |
680 NUM_BANKS(ADDR_SURF_16_BANK) |
681 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
682 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
683 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
684 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
685 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
686 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
687 TILE_SPLIT(split_equal_to_row_size) |
688 NUM_BANKS(ADDR_SURF_16_BANK) |
689 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
690 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
691 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
692 tilemode[8] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
693 ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
694 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
695 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
696 NUM_BANKS(ADDR_SURF_16_BANK) |
697 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
698 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
699 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
700 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
701 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
702 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
703 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
704 NUM_BANKS(ADDR_SURF_16_BANK) |
705 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
706 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
707 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
708 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
709 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
710 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
711 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
712 NUM_BANKS(ADDR_SURF_16_BANK) |
713 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
714 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
715 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
716 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
717 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
718 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
719 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
720 NUM_BANKS(ADDR_SURF_16_BANK) |
721 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
722 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
723 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
724 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
725 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
726 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
727 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
728 NUM_BANKS(ADDR_SURF_16_BANK) |
729 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
730 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
731 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
732 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
733 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
734 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
735 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
736 NUM_BANKS(ADDR_SURF_16_BANK) |
737 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
738 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
739 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
740 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
741 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
742 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
743 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
744 NUM_BANKS(ADDR_SURF_16_BANK) |
745 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
746 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
747 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
748 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
749 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
750 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
751 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
752 NUM_BANKS(ADDR_SURF_16_BANK) |
753 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
754 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
755 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
756 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
757 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
758 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
759 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
760 NUM_BANKS(ADDR_SURF_16_BANK) |
761 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
762 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
763 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
764 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
765 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
766 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
767 TILE_SPLIT(split_equal_to_row_size) |
768 NUM_BANKS(ADDR_SURF_16_BANK) |
769 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
770 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
771 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
772 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
773 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
774 PIPE_CONFIG(ADDR_SURF_P4_8x16);
775 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
776 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
777 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
778 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
779 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
780 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
781 NUM_BANKS(ADDR_SURF_16_BANK) |
782 TILE_SPLIT(split_equal_to_row_size);
783 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
784 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
785 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
786 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
787 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
788 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
789 NUM_BANKS(ADDR_SURF_16_BANK) |
790 TILE_SPLIT(split_equal_to_row_size);
791 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
792 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
793 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
794 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
795 NUM_BANKS(ADDR_SURF_16_BANK) |
796 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
797 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
798 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
799 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
800 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
801 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
802 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
803 NUM_BANKS(ADDR_SURF_16_BANK) |
804 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
805 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
806 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4);
807 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
808 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
809 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
810 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
811 NUM_BANKS(ADDR_SURF_16_BANK) |
812 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
813 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
814 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
815 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
816 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
817 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
818 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
819 NUM_BANKS(ADDR_SURF_16_BANK) |
820 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
821 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
822 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2);
823 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
824 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
825 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
826 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
827 NUM_BANKS(ADDR_SURF_8_BANK) |
828 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
829 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
830 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1);
831 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
832 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
833 } else if (adev->asic_type == CHIP_HAINAN) {
834 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
835 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
836 PIPE_CONFIG(ADDR_SURF_P2) |
837 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
838 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
839 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
840 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
841 NUM_BANKS(ADDR_SURF_16_BANK);
842 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
843 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
844 PIPE_CONFIG(ADDR_SURF_P2) |
845 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
846 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
847 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
848 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
849 NUM_BANKS(ADDR_SURF_16_BANK);
850 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
851 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
852 PIPE_CONFIG(ADDR_SURF_P2) |
853 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
854 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
855 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
856 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
857 NUM_BANKS(ADDR_SURF_16_BANK);
858 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
859 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
860 PIPE_CONFIG(ADDR_SURF_P2) |
861 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
862 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
863 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
864 NUM_BANKS(ADDR_SURF_8_BANK) |
865 TILE_SPLIT(split_equal_to_row_size);
866 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
867 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
868 PIPE_CONFIG(ADDR_SURF_P2);
869 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
870 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
871 PIPE_CONFIG(ADDR_SURF_P2) |
872 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
873 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
874 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
875 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
876 NUM_BANKS(ADDR_SURF_8_BANK);
877 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
878 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
879 PIPE_CONFIG(ADDR_SURF_P2) |
880 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
881 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
882 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
883 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
884 NUM_BANKS(ADDR_SURF_8_BANK);
885 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
886 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
887 PIPE_CONFIG(ADDR_SURF_P2) |
888 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
889 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
890 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
891 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
892 NUM_BANKS(ADDR_SURF_4_BANK);
893 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
894 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
895 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
896 PIPE_CONFIG(ADDR_SURF_P2);
897 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
898 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
899 PIPE_CONFIG(ADDR_SURF_P2) |
900 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
901 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
902 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
903 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
904 NUM_BANKS(ADDR_SURF_16_BANK);
905 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
906 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
907 PIPE_CONFIG(ADDR_SURF_P2) |
908 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
909 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
910 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
911 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
912 NUM_BANKS(ADDR_SURF_16_BANK);
913 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
914 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
915 PIPE_CONFIG(ADDR_SURF_P2) |
916 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
917 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
918 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
919 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
920 NUM_BANKS(ADDR_SURF_16_BANK);
921 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
922 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
923 PIPE_CONFIG(ADDR_SURF_P2);
924 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
925 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
926 PIPE_CONFIG(ADDR_SURF_P2) |
927 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
928 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
929 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
930 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
931 NUM_BANKS(ADDR_SURF_16_BANK);
932 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
933 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
934 PIPE_CONFIG(ADDR_SURF_P2) |
935 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
936 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
937 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
938 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
939 NUM_BANKS(ADDR_SURF_16_BANK);
940 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
941 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
942 PIPE_CONFIG(ADDR_SURF_P2) |
943 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
944 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
945 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
946 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
947 NUM_BANKS(ADDR_SURF_16_BANK);
948 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
949 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
950 PIPE_CONFIG(ADDR_SURF_P2) |
951 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
952 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
953 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
954 NUM_BANKS(ADDR_SURF_16_BANK) |
955 TILE_SPLIT(split_equal_to_row_size);
956 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
957 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
958 PIPE_CONFIG(ADDR_SURF_P2);
959 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
960 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
961 PIPE_CONFIG(ADDR_SURF_P2) |
962 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
963 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
964 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
965 NUM_BANKS(ADDR_SURF_16_BANK) |
966 TILE_SPLIT(split_equal_to_row_size);
967 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
968 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
969 PIPE_CONFIG(ADDR_SURF_P2) |
970 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
971 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
972 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
973 NUM_BANKS(ADDR_SURF_16_BANK) |
974 TILE_SPLIT(split_equal_to_row_size);
975 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
976 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
977 PIPE_CONFIG(ADDR_SURF_P2) |
978 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
979 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
980 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
981 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
982 NUM_BANKS(ADDR_SURF_8_BANK);
983 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
984 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
985 PIPE_CONFIG(ADDR_SURF_P2) |
986 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
987 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
988 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
989 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
990 NUM_BANKS(ADDR_SURF_8_BANK);
991 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
992 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
993 PIPE_CONFIG(ADDR_SURF_P2) |
994 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
995 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
996 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
997 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
998 NUM_BANKS(ADDR_SURF_8_BANK);
999 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1000 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1001 PIPE_CONFIG(ADDR_SURF_P2) |
1002 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1003 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1004 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1005 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1006 NUM_BANKS(ADDR_SURF_8_BANK);
1007 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1008 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1009 PIPE_CONFIG(ADDR_SURF_P2) |
1010 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1011 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1012 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1013 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1014 NUM_BANKS(ADDR_SURF_4_BANK);
1015 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1016 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1017 PIPE_CONFIG(ADDR_SURF_P2) |
1018 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1019 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1020 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1021 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1022 NUM_BANKS(ADDR_SURF_4_BANK);
1023 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1024 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1025 PIPE_CONFIG(ADDR_SURF_P2) |
1026 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1027 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1028 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1029 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1030 NUM_BANKS(ADDR_SURF_4_BANK);
1031 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1032 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1033 PIPE_CONFIG(ADDR_SURF_P2) |
1034 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1035 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1036 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1037 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1038 NUM_BANKS(ADDR_SURF_4_BANK);
1039 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1040 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1041 PIPE_CONFIG(ADDR_SURF_P2) |
1042 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1043 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1044 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1045 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1046 NUM_BANKS(ADDR_SURF_4_BANK);
1047 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1048 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1049 PIPE_CONFIG(ADDR_SURF_P2) |
1050 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1051 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1052 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1053 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1054 NUM_BANKS(ADDR_SURF_4_BANK);
1055 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1056 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1057 } else if ((adev->asic_type == CHIP_TAHITI) || (adev->asic_type == CHIP_PITCAIRN)) {
1058 tilemode[0] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1059 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1060 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1061 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
1062 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1063 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1064 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1065 NUM_BANKS(ADDR_SURF_16_BANK);
1066 tilemode[1] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1067 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1068 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1069 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
1070 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1071 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1072 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1073 NUM_BANKS(ADDR_SURF_16_BANK);
1074 tilemode[2] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1075 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1076 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1077 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1078 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1079 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1080 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1081 NUM_BANKS(ADDR_SURF_16_BANK);
1082 tilemode[3] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1083 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1084 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1085 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1086 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1087 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1088 NUM_BANKS(ADDR_SURF_4_BANK) |
1089 TILE_SPLIT(split_equal_to_row_size);
1090 tilemode[4] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1091 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1092 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1093 tilemode[5] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1094 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1095 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1096 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1097 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1098 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1099 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1100 NUM_BANKS(ADDR_SURF_2_BANK);
1101 tilemode[6] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1102 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1103 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1104 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1105 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1106 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1107 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1108 NUM_BANKS(ADDR_SURF_2_BANK);
1109 tilemode[7] = MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
1110 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1111 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1112 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1113 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1114 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1115 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1116 NUM_BANKS(ADDR_SURF_2_BANK);
1117 tilemode[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
1118 tilemode[9] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1119 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1120 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1121 tilemode[10] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1122 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1123 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1124 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1125 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1126 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1127 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1128 NUM_BANKS(ADDR_SURF_16_BANK);
1129 tilemode[11] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1130 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1131 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1132 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1133 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1134 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1135 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1136 NUM_BANKS(ADDR_SURF_16_BANK);
1137 tilemode[12] = MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
1138 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1139 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1140 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1141 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1142 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1143 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1144 NUM_BANKS(ADDR_SURF_16_BANK);
1145 tilemode[13] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1146 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1147 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1148 tilemode[14] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1149 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1150 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1151 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1152 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1153 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1154 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1155 NUM_BANKS(ADDR_SURF_16_BANK);
1156 tilemode[15] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1157 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1158 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1159 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1160 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1161 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1162 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1163 NUM_BANKS(ADDR_SURF_16_BANK);
1164 tilemode[16] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1165 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1166 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1167 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1168 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1169 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1170 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1171 NUM_BANKS(ADDR_SURF_16_BANK);
1172 tilemode[17] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1173 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1174 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1175 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1176 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1177 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1178 NUM_BANKS(ADDR_SURF_16_BANK) |
1179 TILE_SPLIT(split_equal_to_row_size);
1180 tilemode[18] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1181 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
1182 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16);
1183 tilemode[19] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1184 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
1185 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1186 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1187 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1188 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1189 NUM_BANKS(ADDR_SURF_16_BANK) |
1190 TILE_SPLIT(split_equal_to_row_size);
1191 tilemode[20] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1192 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
1193 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1194 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1195 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1196 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1197 NUM_BANKS(ADDR_SURF_16_BANK) |
1198 TILE_SPLIT(split_equal_to_row_size);
1199 tilemode[21] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1200 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1201 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1202 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1203 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1204 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1205 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1206 NUM_BANKS(ADDR_SURF_4_BANK);
1207 tilemode[22] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1208 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1209 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1210 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1211 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1212 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1213 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1214 NUM_BANKS(ADDR_SURF_4_BANK);
1215 tilemode[23] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1216 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1217 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1218 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
1219 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1220 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1221 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1222 NUM_BANKS(ADDR_SURF_2_BANK);
1223 tilemode[24] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1224 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1225 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
1226 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
1227 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1228 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1229 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1230 NUM_BANKS(ADDR_SURF_2_BANK);
1231 tilemode[25] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1232 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1233 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1234 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1235 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1236 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1237 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1238 NUM_BANKS(ADDR_SURF_2_BANK);
1239 tilemode[26] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1240 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1241 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1242 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1243 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1244 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1245 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1246 NUM_BANKS(ADDR_SURF_2_BANK);
1247 tilemode[27] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1248 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1249 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1250 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1251 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1252 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1253 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1254 NUM_BANKS(ADDR_SURF_2_BANK);
1255 tilemode[28] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1256 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1257 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1258 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1259 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1260 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1261 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1262 NUM_BANKS(ADDR_SURF_2_BANK);
1263 tilemode[29] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1264 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1265 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1266 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
1267 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1268 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1269 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1270 NUM_BANKS(ADDR_SURF_2_BANK);
1271 tilemode[30] = MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
1272 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1273 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
1274 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
1275 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1276 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1277 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
1278 NUM_BANKS(ADDR_SURF_2_BANK);
1279 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
1280 WREG32(mmGB_TILE_MODE0 + reg_offset, tilemode[reg_offset]);
1281 } else {
1282 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1283 }
1284}
1285
1286static void gfx_v6_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1287 u32 sh_num, u32 instance, int xcc_id)
1288{
1289 u32 data;
1290
1291 if (instance == 0xffffffff)
1292 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1293 else
1294 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1295
1296 if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1297 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1298 GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK;
1299 else if (se_num == 0xffffffff)
1300 data |= GRBM_GFX_INDEX__SE_BROADCAST_WRITES_MASK |
1301 (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT);
1302 else if (sh_num == 0xffffffff)
1303 data |= GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK |
1304 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1305 else
1306 data |= (sh_num << GRBM_GFX_INDEX__SH_INDEX__SHIFT) |
1307 (se_num << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
1308 WREG32(mmGRBM_GFX_INDEX, data);
1309}
1310
1311static u32 gfx_v6_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1312{
1313 u32 data, mask;
1314
1315 data = RREG32(mmCC_RB_BACKEND_DISABLE) |
1316 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1317
1318 data = REG_GET_FIELD(data, GC_USER_RB_BACKEND_DISABLE, BACKEND_DISABLE);
1319
1320 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se/
1321 adev->gfx.config.max_sh_per_se);
1322
1323 return ~data & mask;
1324}
1325
1326static void gfx_v6_0_raster_config(struct amdgpu_device *adev, u32 *rconf)
1327{
1328 switch (adev->asic_type) {
1329 case CHIP_TAHITI:
1330 case CHIP_PITCAIRN:
1331 *rconf |=
1332 (2 << PA_SC_RASTER_CONFIG__RB_XSEL2__SHIFT) |
1333 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1334 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1335 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT) |
1336 (2 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT) |
1337 (2 << PA_SC_RASTER_CONFIG__SE_XSEL__SHIFT) |
1338 (2 << PA_SC_RASTER_CONFIG__SE_YSEL__SHIFT);
1339 break;
1340 case CHIP_VERDE:
1341 *rconf |=
1342 (1 << PA_SC_RASTER_CONFIG__RB_XSEL__SHIFT) |
1343 (2 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT) |
1344 (1 << PA_SC_RASTER_CONFIG__PKR_YSEL__SHIFT);
1345 break;
1346 case CHIP_OLAND:
1347 *rconf |= (1 << PA_SC_RASTER_CONFIG__RB_YSEL__SHIFT);
1348 break;
1349 case CHIP_HAINAN:
1350 *rconf |= 0x0;
1351 break;
1352 default:
1353 DRM_ERROR("unknown asic: 0x%x\n", adev->asic_type);
1354 break;
1355 }
1356}
1357
1358static void gfx_v6_0_write_harvested_raster_configs(struct amdgpu_device *adev,
1359 u32 raster_config, unsigned rb_mask,
1360 unsigned num_rb)
1361{
1362 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1);
1363 unsigned num_se = max_t(unsigned, adev->gfx.config.max_shader_engines, 1);
1364 unsigned rb_per_pkr = min_t(unsigned, num_rb / num_se / sh_per_se, 2);
1365 unsigned rb_per_se = num_rb / num_se;
1366 unsigned se_mask[4];
1367 unsigned se;
1368
1369 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
1370 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
1371 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
1372 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
1373
1374 WARN_ON(!(num_se == 1 || num_se == 2 || num_se == 4));
1375 WARN_ON(!(sh_per_se == 1 || sh_per_se == 2));
1376 WARN_ON(!(rb_per_pkr == 1 || rb_per_pkr == 2));
1377
1378 for (se = 0; se < num_se; se++) {
1379 unsigned raster_config_se = raster_config;
1380 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
1381 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
1382 int idx = (se / 2) * 2;
1383
1384 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
1385 raster_config_se &= ~PA_SC_RASTER_CONFIG__SE_MAP_MASK;
1386
1387 if (!se_mask[idx])
1388 raster_config_se |= RASTER_CONFIG_SE_MAP_3 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1389 else
1390 raster_config_se |= RASTER_CONFIG_SE_MAP_0 << PA_SC_RASTER_CONFIG__SE_MAP__SHIFT;
1391 }
1392
1393 pkr0_mask &= rb_mask;
1394 pkr1_mask &= rb_mask;
1395 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
1396 raster_config_se &= ~PA_SC_RASTER_CONFIG__PKR_MAP_MASK;
1397
1398 if (!pkr0_mask)
1399 raster_config_se |= RASTER_CONFIG_PKR_MAP_3 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1400 else
1401 raster_config_se |= RASTER_CONFIG_PKR_MAP_0 << PA_SC_RASTER_CONFIG__PKR_MAP__SHIFT;
1402 }
1403
1404 if (rb_per_se >= 2) {
1405 unsigned rb0_mask = 1 << (se * rb_per_se);
1406 unsigned rb1_mask = rb0_mask << 1;
1407
1408 rb0_mask &= rb_mask;
1409 rb1_mask &= rb_mask;
1410 if (!rb0_mask || !rb1_mask) {
1411 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR0_MASK;
1412
1413 if (!rb0_mask)
1414 raster_config_se |=
1415 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1416 else
1417 raster_config_se |=
1418 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR0__SHIFT;
1419 }
1420
1421 if (rb_per_se > 2) {
1422 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
1423 rb1_mask = rb0_mask << 1;
1424 rb0_mask &= rb_mask;
1425 rb1_mask &= rb_mask;
1426 if (!rb0_mask || !rb1_mask) {
1427 raster_config_se &= ~PA_SC_RASTER_CONFIG__RB_MAP_PKR1_MASK;
1428
1429 if (!rb0_mask)
1430 raster_config_se |=
1431 RASTER_CONFIG_RB_MAP_3 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1432 else
1433 raster_config_se |=
1434 RASTER_CONFIG_RB_MAP_0 << PA_SC_RASTER_CONFIG__RB_MAP_PKR1__SHIFT;
1435 }
1436 }
1437 }
1438
1439 /* GRBM_GFX_INDEX has a different offset on SI */
1440 gfx_v6_0_select_se_sh(adev, se, 0xffffffff, 0xffffffff, 0);
1441 WREG32(mmPA_SC_RASTER_CONFIG, raster_config_se);
1442 }
1443
1444 /* GRBM_GFX_INDEX has a different offset on SI */
1445 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
1446}
1447
1448static void gfx_v6_0_setup_rb(struct amdgpu_device *adev)
1449{
1450 int i, j;
1451 u32 data;
1452 u32 raster_config = 0;
1453 u32 active_rbs = 0;
1454 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1455 adev->gfx.config.max_sh_per_se;
1456 unsigned num_rb_pipes;
1457
1458 mutex_lock(&adev->grbm_idx_mutex);
1459 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1460 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1461 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0);
1462 data = gfx_v6_0_get_rb_active_bitmap(adev);
1463 active_rbs |= data <<
1464 ((i * adev->gfx.config.max_sh_per_se + j) *
1465 rb_bitmap_width_per_sh);
1466 }
1467 }
1468 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
1469
1470 adev->gfx.config.backend_enable_mask = active_rbs;
1471 adev->gfx.config.num_rbs = hweight32(active_rbs);
1472
1473 num_rb_pipes = min_t(unsigned, adev->gfx.config.max_backends_per_se *
1474 adev->gfx.config.max_shader_engines, 16);
1475
1476 gfx_v6_0_raster_config(adev, &raster_config);
1477
1478 if (!adev->gfx.config.backend_enable_mask ||
1479 adev->gfx.config.num_rbs >= num_rb_pipes)
1480 WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
1481 else
1482 gfx_v6_0_write_harvested_raster_configs(adev, raster_config,
1483 adev->gfx.config.backend_enable_mask,
1484 num_rb_pipes);
1485
1486 /* cache the values for userspace */
1487 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1488 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1489 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0);
1490 adev->gfx.config.rb_config[i][j].rb_backend_disable =
1491 RREG32(mmCC_RB_BACKEND_DISABLE);
1492 adev->gfx.config.rb_config[i][j].user_rb_backend_disable =
1493 RREG32(mmGC_USER_RB_BACKEND_DISABLE);
1494 adev->gfx.config.rb_config[i][j].raster_config =
1495 RREG32(mmPA_SC_RASTER_CONFIG);
1496 }
1497 }
1498 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
1499 mutex_unlock(&adev->grbm_idx_mutex);
1500}
1501
1502static void gfx_v6_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
1503 u32 bitmap)
1504{
1505 u32 data;
1506
1507 if (!bitmap)
1508 return;
1509
1510 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
1511 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
1512
1513 WREG32(mmGC_USER_SHADER_ARRAY_CONFIG, data);
1514}
1515
1516static u32 gfx_v6_0_get_cu_enabled(struct amdgpu_device *adev)
1517{
1518 u32 data, mask;
1519
1520 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
1521 RREG32(mmGC_USER_SHADER_ARRAY_CONFIG);
1522
1523 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
1524 return ~REG_GET_FIELD(data, CC_GC_SHADER_ARRAY_CONFIG, INACTIVE_CUS) & mask;
1525}
1526
1527
1528static void gfx_v6_0_setup_spi(struct amdgpu_device *adev)
1529{
1530 int i, j, k;
1531 u32 data, mask;
1532 u32 active_cu = 0;
1533
1534 mutex_lock(&adev->grbm_idx_mutex);
1535 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1536 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1537 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0);
1538 data = RREG32(mmSPI_STATIC_THREAD_MGMT_3);
1539 active_cu = gfx_v6_0_get_cu_enabled(adev);
1540
1541 mask = 1;
1542 for (k = 0; k < 16; k++) {
1543 mask <<= k;
1544 if (active_cu & mask) {
1545 data &= ~mask;
1546 WREG32(mmSPI_STATIC_THREAD_MGMT_3, data);
1547 break;
1548 }
1549 }
1550 }
1551 }
1552 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
1553 mutex_unlock(&adev->grbm_idx_mutex);
1554}
1555
1556static void gfx_v6_0_config_init(struct amdgpu_device *adev)
1557{
1558 adev->gfx.config.double_offchip_lds_buf = 0;
1559}
1560
1561static void gfx_v6_0_constants_init(struct amdgpu_device *adev)
1562{
1563 u32 gb_addr_config = 0;
1564 u32 mc_arb_ramcfg;
1565 u32 sx_debug_1;
1566 u32 hdp_host_path_cntl;
1567 u32 tmp;
1568
1569 switch (adev->asic_type) {
1570 case CHIP_TAHITI:
1571 adev->gfx.config.max_shader_engines = 2;
1572 adev->gfx.config.max_tile_pipes = 12;
1573 adev->gfx.config.max_cu_per_sh = 8;
1574 adev->gfx.config.max_sh_per_se = 2;
1575 adev->gfx.config.max_backends_per_se = 4;
1576 adev->gfx.config.max_texture_channel_caches = 12;
1577 adev->gfx.config.max_gprs = 256;
1578 adev->gfx.config.max_gs_threads = 32;
1579 adev->gfx.config.max_hw_contexts = 8;
1580
1581 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1582 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1583 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1584 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1585 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1586 break;
1587 case CHIP_PITCAIRN:
1588 adev->gfx.config.max_shader_engines = 2;
1589 adev->gfx.config.max_tile_pipes = 8;
1590 adev->gfx.config.max_cu_per_sh = 5;
1591 adev->gfx.config.max_sh_per_se = 2;
1592 adev->gfx.config.max_backends_per_se = 4;
1593 adev->gfx.config.max_texture_channel_caches = 8;
1594 adev->gfx.config.max_gprs = 256;
1595 adev->gfx.config.max_gs_threads = 32;
1596 adev->gfx.config.max_hw_contexts = 8;
1597
1598 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1599 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1600 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1601 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1602 gb_addr_config = TAHITI_GB_ADDR_CONFIG_GOLDEN;
1603 break;
1604 case CHIP_VERDE:
1605 adev->gfx.config.max_shader_engines = 1;
1606 adev->gfx.config.max_tile_pipes = 4;
1607 adev->gfx.config.max_cu_per_sh = 5;
1608 adev->gfx.config.max_sh_per_se = 2;
1609 adev->gfx.config.max_backends_per_se = 4;
1610 adev->gfx.config.max_texture_channel_caches = 4;
1611 adev->gfx.config.max_gprs = 256;
1612 adev->gfx.config.max_gs_threads = 32;
1613 adev->gfx.config.max_hw_contexts = 8;
1614
1615 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1616 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1617 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1618 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1619 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1620 break;
1621 case CHIP_OLAND:
1622 adev->gfx.config.max_shader_engines = 1;
1623 adev->gfx.config.max_tile_pipes = 4;
1624 adev->gfx.config.max_cu_per_sh = 6;
1625 adev->gfx.config.max_sh_per_se = 1;
1626 adev->gfx.config.max_backends_per_se = 2;
1627 adev->gfx.config.max_texture_channel_caches = 4;
1628 adev->gfx.config.max_gprs = 256;
1629 adev->gfx.config.max_gs_threads = 16;
1630 adev->gfx.config.max_hw_contexts = 8;
1631
1632 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1633 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1634 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1635 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1636 gb_addr_config = VERDE_GB_ADDR_CONFIG_GOLDEN;
1637 break;
1638 case CHIP_HAINAN:
1639 adev->gfx.config.max_shader_engines = 1;
1640 adev->gfx.config.max_tile_pipes = 4;
1641 adev->gfx.config.max_cu_per_sh = 5;
1642 adev->gfx.config.max_sh_per_se = 1;
1643 adev->gfx.config.max_backends_per_se = 1;
1644 adev->gfx.config.max_texture_channel_caches = 2;
1645 adev->gfx.config.max_gprs = 256;
1646 adev->gfx.config.max_gs_threads = 16;
1647 adev->gfx.config.max_hw_contexts = 8;
1648
1649 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1650 adev->gfx.config.sc_prim_fifo_size_backend = 0x40;
1651 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1652 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130;
1653 gb_addr_config = HAINAN_GB_ADDR_CONFIG_GOLDEN;
1654 break;
1655 default:
1656 BUG();
1657 break;
1658 }
1659
1660 WREG32(mmGRBM_CNTL, (0xff << GRBM_CNTL__READ_TIMEOUT__SHIFT));
1661 WREG32(mmSRBM_INT_CNTL, 1);
1662 WREG32(mmSRBM_INT_ACK, 1);
1663
1664 WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
1665
1666 adev->gfx.config.mc_arb_ramcfg = RREG32(mmMC_ARB_RAMCFG);
1667 mc_arb_ramcfg = adev->gfx.config.mc_arb_ramcfg;
1668
1669 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes;
1670 adev->gfx.config.mem_max_burst_length_bytes = 256;
1671 tmp = (mc_arb_ramcfg & MC_ARB_RAMCFG__NOOFCOLS_MASK) >> MC_ARB_RAMCFG__NOOFCOLS__SHIFT;
1672 adev->gfx.config.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1673 if (adev->gfx.config.mem_row_size_in_kb > 4)
1674 adev->gfx.config.mem_row_size_in_kb = 4;
1675 adev->gfx.config.shader_engine_tile_size = 32;
1676 adev->gfx.config.num_gpus = 1;
1677 adev->gfx.config.multi_gpu_tile_size = 64;
1678
1679 gb_addr_config &= ~GB_ADDR_CONFIG__ROW_SIZE_MASK;
1680 switch (adev->gfx.config.mem_row_size_in_kb) {
1681 case 1:
1682 default:
1683 gb_addr_config |= 0 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1684 break;
1685 case 2:
1686 gb_addr_config |= 1 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1687 break;
1688 case 4:
1689 gb_addr_config |= 2 << GB_ADDR_CONFIG__ROW_SIZE__SHIFT;
1690 break;
1691 }
1692 gb_addr_config &= ~GB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK;
1693 if (adev->gfx.config.max_shader_engines == 2)
1694 gb_addr_config |= 1 << GB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT;
1695 adev->gfx.config.gb_addr_config = gb_addr_config;
1696
1697 WREG32(mmGB_ADDR_CONFIG, gb_addr_config);
1698 WREG32(mmDMIF_ADDR_CONFIG, gb_addr_config);
1699 WREG32(mmDMIF_ADDR_CALC, gb_addr_config);
1700 WREG32(mmHDP_ADDR_CONFIG, gb_addr_config);
1701 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1702 WREG32(mmDMA_TILING_CONFIG + DMA1_REGISTER_OFFSET, gb_addr_config);
1703
1704#if 0
1705 if (adev->has_uvd) {
1706 WREG32(mmUVD_UDEC_ADDR_CONFIG, gb_addr_config);
1707 WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, gb_addr_config);
1708 WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, gb_addr_config);
1709 }
1710#endif
1711 gfx_v6_0_tiling_mode_table_init(adev);
1712
1713 gfx_v6_0_setup_rb(adev);
1714
1715 gfx_v6_0_setup_spi(adev);
1716
1717 gfx_v6_0_get_cu_info(adev);
1718 gfx_v6_0_config_init(adev);
1719
1720 WREG32(mmCP_QUEUE_THRESHOLDS, ((0x16 << CP_QUEUE_THRESHOLDS__ROQ_IB1_START__SHIFT) |
1721 (0x2b << CP_QUEUE_THRESHOLDS__ROQ_IB2_START__SHIFT)));
1722 WREG32(mmCP_MEQ_THRESHOLDS, (0x30 << CP_MEQ_THRESHOLDS__MEQ1_START__SHIFT) |
1723 (0x60 << CP_MEQ_THRESHOLDS__MEQ2_START__SHIFT));
1724
1725 sx_debug_1 = RREG32(mmSX_DEBUG_1);
1726 WREG32(mmSX_DEBUG_1, sx_debug_1);
1727
1728 WREG32(mmSPI_CONFIG_CNTL_1, (4 << SPI_CONFIG_CNTL_1__VTX_DONE_DELAY__SHIFT));
1729
1730 WREG32(mmPA_SC_FIFO_SIZE, ((adev->gfx.config.sc_prim_fifo_size_frontend << PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1731 (adev->gfx.config.sc_prim_fifo_size_backend << PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1732 (adev->gfx.config.sc_hiz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1733 (adev->gfx.config.sc_earlyz_tile_fifo_size << PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT)));
1734
1735 WREG32(mmVGT_NUM_INSTANCES, 1);
1736 WREG32(mmCP_PERFMON_CNTL, 0);
1737 WREG32(mmSQ_CONFIG, 0);
1738 WREG32(mmPA_SC_FORCE_EOV_MAX_CNTS, ((4095 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_CLK_CNT__SHIFT) |
1739 (255 << PA_SC_FORCE_EOV_MAX_CNTS__FORCE_EOV_MAX_REZ_CNT__SHIFT)));
1740
1741 WREG32(mmVGT_CACHE_INVALIDATION,
1742 (VC_AND_TC << VGT_CACHE_INVALIDATION__CACHE_INVALIDATION__SHIFT) |
1743 (ES_AND_GS_AUTO << VGT_CACHE_INVALIDATION__AUTO_INVLD_EN__SHIFT));
1744
1745 WREG32(mmVGT_GS_VERTEX_REUSE, 16);
1746 WREG32(mmPA_SC_LINE_STIPPLE_STATE, 0);
1747
1748 WREG32(mmCB_PERFCOUNTER0_SELECT0, 0);
1749 WREG32(mmCB_PERFCOUNTER0_SELECT1, 0);
1750 WREG32(mmCB_PERFCOUNTER1_SELECT0, 0);
1751 WREG32(mmCB_PERFCOUNTER1_SELECT1, 0);
1752 WREG32(mmCB_PERFCOUNTER2_SELECT0, 0);
1753 WREG32(mmCB_PERFCOUNTER2_SELECT1, 0);
1754 WREG32(mmCB_PERFCOUNTER3_SELECT0, 0);
1755 WREG32(mmCB_PERFCOUNTER3_SELECT1, 0);
1756
1757 hdp_host_path_cntl = RREG32(mmHDP_HOST_PATH_CNTL);
1758 WREG32(mmHDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1759
1760 WREG32(mmPA_CL_ENHANCE, PA_CL_ENHANCE__CLIP_VTX_REORDER_ENA_MASK |
1761 (3 << PA_CL_ENHANCE__NUM_CLIP_SEQ__SHIFT));
1762
1763 udelay(50);
1764}
1765
1766static int gfx_v6_0_ring_test_ring(struct amdgpu_ring *ring)
1767{
1768 struct amdgpu_device *adev = ring->adev;
1769 uint32_t tmp = 0;
1770 unsigned i;
1771 int r;
1772
1773 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
1774
1775 r = amdgpu_ring_alloc(ring, 3);
1776 if (r)
1777 return r;
1778
1779 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1780 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START);
1781 amdgpu_ring_write(ring, 0xDEADBEEF);
1782 amdgpu_ring_commit(ring);
1783
1784 for (i = 0; i < adev->usec_timeout; i++) {
1785 tmp = RREG32(mmSCRATCH_REG0);
1786 if (tmp == 0xDEADBEEF)
1787 break;
1788 udelay(1);
1789 }
1790
1791 if (i >= adev->usec_timeout)
1792 r = -ETIMEDOUT;
1793 return r;
1794}
1795
1796static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring)
1797{
1798 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0));
1799 amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) |
1800 EVENT_INDEX(0));
1801}
1802
1803static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1804 u64 seq, unsigned flags)
1805{
1806 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
1807 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
1808 /* flush read cache over gart */
1809 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1810 amdgpu_ring_write(ring, (mmCP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START));
1811 amdgpu_ring_write(ring, 0);
1812 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
1813 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
1814 PACKET3_TC_ACTION_ENA |
1815 PACKET3_SH_KCACHE_ACTION_ENA |
1816 PACKET3_SH_ICACHE_ACTION_ENA);
1817 amdgpu_ring_write(ring, 0xFFFFFFFF);
1818 amdgpu_ring_write(ring, 0);
1819 amdgpu_ring_write(ring, 10); /* poll interval */
1820 /* EVENT_WRITE_EOP - flush caches, send int */
1821 amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1822 amdgpu_ring_write(ring, EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5));
1823 amdgpu_ring_write(ring, addr & 0xfffffffc);
1824 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) |
1825 ((write64bit ? 2 : 1) << CP_EOP_DONE_DATA_CNTL__DATA_SEL__SHIFT) |
1826 ((int_sel ? 2 : 0) << CP_EOP_DONE_DATA_CNTL__INT_SEL__SHIFT));
1827 amdgpu_ring_write(ring, lower_32_bits(seq));
1828 amdgpu_ring_write(ring, upper_32_bits(seq));
1829}
1830
1831static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
1832 struct amdgpu_job *job,
1833 struct amdgpu_ib *ib,
1834 uint32_t flags)
1835{
1836 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1837 u32 header, control = 0;
1838
1839 /* insert SWITCH_BUFFER packet before first IB in the ring frame */
1840 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
1841 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1842 amdgpu_ring_write(ring, 0);
1843 }
1844
1845 if (ib->flags & AMDGPU_IB_FLAG_CE)
1846 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1847 else
1848 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1849
1850 control |= ib->length_dw | (vmid << 24);
1851
1852 amdgpu_ring_write(ring, header);
1853 amdgpu_ring_write(ring,
1854#ifdef __BIG_ENDIAN
1855 (2 << 0) |
1856#endif
1857 (ib->gpu_addr & 0xFFFFFFFC));
1858 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1859 amdgpu_ring_write(ring, control);
1860}
1861
1862/**
1863 * gfx_v6_0_ring_test_ib - basic ring IB test
1864 *
1865 * @ring: amdgpu_ring structure holding ring information
1866 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
1867 *
1868 * Allocate an IB and execute it on the gfx ring (SI).
1869 * Provides a basic gfx ring test to verify that IBs are working.
1870 * Returns 0 on success, error on failure.
1871 */
1872static int gfx_v6_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
1873{
1874 struct amdgpu_device *adev = ring->adev;
1875 struct dma_fence *f = NULL;
1876 struct amdgpu_ib ib;
1877 uint32_t tmp = 0;
1878 long r;
1879
1880 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD);
1881 memset(&ib, 0, sizeof(ib));
1882 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
1883 if (r)
1884 return r;
1885
1886 ib.ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1887 ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START;
1888 ib.ptr[2] = 0xDEADBEEF;
1889 ib.length_dw = 3;
1890
1891 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
1892 if (r)
1893 goto error;
1894
1895 r = dma_fence_wait_timeout(f, false, timeout);
1896 if (r == 0) {
1897 r = -ETIMEDOUT;
1898 goto error;
1899 } else if (r < 0) {
1900 goto error;
1901 }
1902 tmp = RREG32(mmSCRATCH_REG0);
1903 if (tmp == 0xDEADBEEF)
1904 r = 0;
1905 else
1906 r = -EINVAL;
1907
1908error:
1909 amdgpu_ib_free(adev, &ib, NULL);
1910 dma_fence_put(f);
1911 return r;
1912}
1913
1914static void gfx_v6_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
1915{
1916 if (enable) {
1917 WREG32(mmCP_ME_CNTL, 0);
1918 } else {
1919 WREG32(mmCP_ME_CNTL, (CP_ME_CNTL__ME_HALT_MASK |
1920 CP_ME_CNTL__PFP_HALT_MASK |
1921 CP_ME_CNTL__CE_HALT_MASK));
1922 WREG32(mmSCRATCH_UMSK, 0);
1923 }
1924 udelay(50);
1925}
1926
1927static int gfx_v6_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
1928{
1929 unsigned i;
1930 const struct gfx_firmware_header_v1_0 *pfp_hdr;
1931 const struct gfx_firmware_header_v1_0 *ce_hdr;
1932 const struct gfx_firmware_header_v1_0 *me_hdr;
1933 const __le32 *fw_data;
1934 u32 fw_size;
1935
1936 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
1937 return -EINVAL;
1938
1939 gfx_v6_0_cp_gfx_enable(adev, false);
1940 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
1941 ce_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
1942 me_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
1943
1944 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
1945 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
1946 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
1947
1948 /* PFP */
1949 fw_data = (const __le32 *)
1950 (adev->gfx.pfp_fw->data + le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
1951 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
1952 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1953 for (i = 0; i < fw_size; i++)
1954 WREG32(mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
1955 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1956
1957 /* CE */
1958 fw_data = (const __le32 *)
1959 (adev->gfx.ce_fw->data + le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
1960 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
1961 WREG32(mmCP_CE_UCODE_ADDR, 0);
1962 for (i = 0; i < fw_size; i++)
1963 WREG32(mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
1964 WREG32(mmCP_CE_UCODE_ADDR, 0);
1965
1966 /* ME */
1967 fw_data = (const __be32 *)
1968 (adev->gfx.me_fw->data + le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
1969 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
1970 WREG32(mmCP_ME_RAM_WADDR, 0);
1971 for (i = 0; i < fw_size; i++)
1972 WREG32(mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
1973 WREG32(mmCP_ME_RAM_WADDR, 0);
1974
1975 WREG32(mmCP_PFP_UCODE_ADDR, 0);
1976 WREG32(mmCP_CE_UCODE_ADDR, 0);
1977 WREG32(mmCP_ME_RAM_WADDR, 0);
1978 WREG32(mmCP_ME_RAM_RADDR, 0);
1979 return 0;
1980}
1981
1982static int gfx_v6_0_cp_gfx_start(struct amdgpu_device *adev)
1983{
1984 const struct cs_section_def *sect = NULL;
1985 const struct cs_extent_def *ext = NULL;
1986 struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1987 int r, i;
1988
1989 r = amdgpu_ring_alloc(ring, 7 + 4);
1990 if (r) {
1991 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
1992 return r;
1993 }
1994 amdgpu_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1995 amdgpu_ring_write(ring, 0x1);
1996 amdgpu_ring_write(ring, 0x0);
1997 amdgpu_ring_write(ring, adev->gfx.config.max_hw_contexts - 1);
1998 amdgpu_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1999 amdgpu_ring_write(ring, 0);
2000 amdgpu_ring_write(ring, 0);
2001
2002 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2003 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2004 amdgpu_ring_write(ring, 0xc000);
2005 amdgpu_ring_write(ring, 0xe000);
2006 amdgpu_ring_commit(ring);
2007
2008 gfx_v6_0_cp_gfx_enable(adev, true);
2009
2010 r = amdgpu_ring_alloc(ring, gfx_v6_0_get_csb_size(adev) + 10);
2011 if (r) {
2012 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2013 return r;
2014 }
2015
2016 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2017 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2018
2019 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2020 for (ext = sect->section; ext->extent != NULL; ++ext) {
2021 if (sect->id == SECT_CONTEXT) {
2022 amdgpu_ring_write(ring,
2023 PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2024 amdgpu_ring_write(ring, ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2025 for (i = 0; i < ext->reg_count; i++)
2026 amdgpu_ring_write(ring, ext->extent[i]);
2027 }
2028 }
2029 }
2030
2031 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2032 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2033
2034 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2035 amdgpu_ring_write(ring, 0);
2036
2037 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
2038 amdgpu_ring_write(ring, 0x00000316);
2039 amdgpu_ring_write(ring, 0x0000000e);
2040 amdgpu_ring_write(ring, 0x00000010);
2041
2042 amdgpu_ring_commit(ring);
2043
2044 return 0;
2045}
2046
2047static int gfx_v6_0_cp_gfx_resume(struct amdgpu_device *adev)
2048{
2049 struct amdgpu_ring *ring;
2050 u32 tmp;
2051 u32 rb_bufsz;
2052 int r;
2053 u64 rptr_addr;
2054
2055 WREG32(mmCP_SEM_WAIT_TIMER, 0x0);
2056 WREG32(mmCP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
2057
2058 /* Set the write pointer delay */
2059 WREG32(mmCP_RB_WPTR_DELAY, 0);
2060
2061 WREG32(mmCP_DEBUG, 0);
2062 WREG32(mmSCRATCH_ADDR, 0);
2063
2064 /* ring 0 - compute and gfx */
2065 /* Set ring buffer size */
2066 ring = &adev->gfx.gfx_ring[0];
2067 rb_bufsz = order_base_2(ring->ring_size / 8);
2068 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2069
2070#ifdef __BIG_ENDIAN
2071 tmp |= BUF_SWAP_32BIT;
2072#endif
2073 WREG32(mmCP_RB0_CNTL, tmp);
2074
2075 /* Initialize the ring buffer's read and write pointers */
2076 WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK);
2077 ring->wptr = 0;
2078 WREG32(mmCP_RB0_WPTR, ring->wptr);
2079
2080 /* set the wb address whether it's enabled or not */
2081 rptr_addr = ring->rptr_gpu_addr;
2082 WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2083 WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2084
2085 WREG32(mmSCRATCH_UMSK, 0);
2086
2087 mdelay(1);
2088 WREG32(mmCP_RB0_CNTL, tmp);
2089
2090 WREG32(mmCP_RB0_BASE, ring->gpu_addr >> 8);
2091
2092 /* start the rings */
2093 gfx_v6_0_cp_gfx_start(adev);
2094 r = amdgpu_ring_test_helper(ring);
2095 if (r)
2096 return r;
2097
2098 return 0;
2099}
2100
2101static u64 gfx_v6_0_ring_get_rptr(struct amdgpu_ring *ring)
2102{
2103 return *ring->rptr_cpu_addr;
2104}
2105
2106static u64 gfx_v6_0_ring_get_wptr(struct amdgpu_ring *ring)
2107{
2108 struct amdgpu_device *adev = ring->adev;
2109
2110 if (ring == &adev->gfx.gfx_ring[0])
2111 return RREG32(mmCP_RB0_WPTR);
2112 else if (ring == &adev->gfx.compute_ring[0])
2113 return RREG32(mmCP_RB1_WPTR);
2114 else if (ring == &adev->gfx.compute_ring[1])
2115 return RREG32(mmCP_RB2_WPTR);
2116 else
2117 BUG();
2118}
2119
2120static void gfx_v6_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
2121{
2122 struct amdgpu_device *adev = ring->adev;
2123
2124 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2125 (void)RREG32(mmCP_RB0_WPTR);
2126}
2127
2128static void gfx_v6_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
2129{
2130 struct amdgpu_device *adev = ring->adev;
2131
2132 if (ring == &adev->gfx.compute_ring[0]) {
2133 WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
2134 (void)RREG32(mmCP_RB1_WPTR);
2135 } else if (ring == &adev->gfx.compute_ring[1]) {
2136 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr));
2137 (void)RREG32(mmCP_RB2_WPTR);
2138 } else {
2139 BUG();
2140 }
2141
2142}
2143
2144static int gfx_v6_0_cp_compute_resume(struct amdgpu_device *adev)
2145{
2146 struct amdgpu_ring *ring;
2147 u32 tmp;
2148 u32 rb_bufsz;
2149 int i, r;
2150 u64 rptr_addr;
2151
2152 /* ring1 - compute only */
2153 /* Set ring buffer size */
2154
2155 ring = &adev->gfx.compute_ring[0];
2156 rb_bufsz = order_base_2(ring->ring_size / 8);
2157 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2158#ifdef __BIG_ENDIAN
2159 tmp |= BUF_SWAP_32BIT;
2160#endif
2161 WREG32(mmCP_RB1_CNTL, tmp);
2162
2163 WREG32(mmCP_RB1_CNTL, tmp | CP_RB1_CNTL__RB_RPTR_WR_ENA_MASK);
2164 ring->wptr = 0;
2165 WREG32(mmCP_RB1_WPTR, ring->wptr);
2166
2167 rptr_addr = ring->rptr_gpu_addr;
2168 WREG32(mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
2169 WREG32(mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2170
2171 mdelay(1);
2172 WREG32(mmCP_RB1_CNTL, tmp);
2173 WREG32(mmCP_RB1_BASE, ring->gpu_addr >> 8);
2174
2175 ring = &adev->gfx.compute_ring[1];
2176 rb_bufsz = order_base_2(ring->ring_size / 8);
2177 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2178#ifdef __BIG_ENDIAN
2179 tmp |= BUF_SWAP_32BIT;
2180#endif
2181 WREG32(mmCP_RB2_CNTL, tmp);
2182
2183 WREG32(mmCP_RB2_CNTL, tmp | CP_RB2_CNTL__RB_RPTR_WR_ENA_MASK);
2184 ring->wptr = 0;
2185 WREG32(mmCP_RB2_WPTR, ring->wptr);
2186 rptr_addr = ring->rptr_gpu_addr;
2187 WREG32(mmCP_RB2_RPTR_ADDR, lower_32_bits(rptr_addr));
2188 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
2189
2190 mdelay(1);
2191 WREG32(mmCP_RB2_CNTL, tmp);
2192 WREG32(mmCP_RB2_BASE, ring->gpu_addr >> 8);
2193
2194
2195 for (i = 0; i < 2; i++) {
2196 r = amdgpu_ring_test_helper(&adev->gfx.compute_ring[i]);
2197 if (r)
2198 return r;
2199 }
2200
2201 return 0;
2202}
2203
2204static void gfx_v6_0_cp_enable(struct amdgpu_device *adev, bool enable)
2205{
2206 gfx_v6_0_cp_gfx_enable(adev, enable);
2207}
2208
2209static int gfx_v6_0_cp_load_microcode(struct amdgpu_device *adev)
2210{
2211 return gfx_v6_0_cp_gfx_load_microcode(adev);
2212}
2213
2214static void gfx_v6_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
2215 bool enable)
2216{
2217 u32 tmp = RREG32(mmCP_INT_CNTL_RING0);
2218 u32 mask;
2219 int i;
2220
2221 if (enable)
2222 tmp |= (CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2223 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2224 else
2225 tmp &= ~(CP_INT_CNTL__CNTX_BUSY_INT_ENABLE_MASK |
2226 CP_INT_CNTL__CNTX_EMPTY_INT_ENABLE_MASK);
2227 WREG32(mmCP_INT_CNTL_RING0, tmp);
2228
2229 if (!enable) {
2230 /* read a gfx register */
2231 tmp = RREG32(mmDB_DEPTH_INFO);
2232
2233 mask = RLC_BUSY_STATUS | GFX_POWER_STATUS | GFX_CLOCK_STATUS | GFX_LS_STATUS;
2234 for (i = 0; i < adev->usec_timeout; i++) {
2235 if ((RREG32(mmRLC_STAT) & mask) == (GFX_CLOCK_STATUS | GFX_POWER_STATUS))
2236 break;
2237 udelay(1);
2238 }
2239 }
2240}
2241
2242static int gfx_v6_0_cp_resume(struct amdgpu_device *adev)
2243{
2244 int r;
2245
2246 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2247
2248 r = gfx_v6_0_cp_load_microcode(adev);
2249 if (r)
2250 return r;
2251
2252 r = gfx_v6_0_cp_gfx_resume(adev);
2253 if (r)
2254 return r;
2255 r = gfx_v6_0_cp_compute_resume(adev);
2256 if (r)
2257 return r;
2258
2259 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2260
2261 return 0;
2262}
2263
2264static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
2265{
2266 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2267 uint32_t seq = ring->fence_drv.sync_seq;
2268 uint64_t addr = ring->fence_drv.gpu_addr;
2269
2270 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2271 amdgpu_ring_write(ring, (WAIT_REG_MEM_MEM_SPACE(1) | /* memory */
2272 WAIT_REG_MEM_FUNCTION(3) | /* equal */
2273 WAIT_REG_MEM_ENGINE(usepfp))); /* pfp or me */
2274 amdgpu_ring_write(ring, addr & 0xfffffffc);
2275 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
2276 amdgpu_ring_write(ring, seq);
2277 amdgpu_ring_write(ring, 0xffffffff);
2278 amdgpu_ring_write(ring, 4); /* poll interval */
2279
2280 if (usepfp) {
2281 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2282 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2283 amdgpu_ring_write(ring, 0);
2284 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2285 amdgpu_ring_write(ring, 0);
2286 }
2287}
2288
2289static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
2290 unsigned vmid, uint64_t pd_addr)
2291{
2292 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2293
2294 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
2295
2296 /* wait for the invalidate to complete */
2297 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
2298 amdgpu_ring_write(ring, (WAIT_REG_MEM_FUNCTION(0) | /* always */
2299 WAIT_REG_MEM_ENGINE(0))); /* me */
2300 amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
2301 amdgpu_ring_write(ring, 0);
2302 amdgpu_ring_write(ring, 0); /* ref */
2303 amdgpu_ring_write(ring, 0); /* mask */
2304 amdgpu_ring_write(ring, 0x20); /* poll interval */
2305
2306 if (usepfp) {
2307 /* sync PFP to ME, otherwise we might get invalid PFP reads */
2308 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
2309 amdgpu_ring_write(ring, 0x0);
2310
2311 /* synce CE with ME to prevent CE fetch CEIB before context switch done */
2312 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2313 amdgpu_ring_write(ring, 0);
2314 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
2315 amdgpu_ring_write(ring, 0);
2316 }
2317}
2318
2319static void gfx_v6_0_ring_emit_wreg(struct amdgpu_ring *ring,
2320 uint32_t reg, uint32_t val)
2321{
2322 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
2323
2324 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
2325 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
2326 WRITE_DATA_DST_SEL(0)));
2327 amdgpu_ring_write(ring, reg);
2328 amdgpu_ring_write(ring, 0);
2329 amdgpu_ring_write(ring, val);
2330}
2331
2332static int gfx_v6_0_rlc_init(struct amdgpu_device *adev)
2333{
2334 const u32 *src_ptr;
2335 volatile u32 *dst_ptr;
2336 u32 dws;
2337 u64 reg_list_mc_addr;
2338 const struct cs_section_def *cs_data;
2339 int r;
2340
2341 adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list;
2342 adev->gfx.rlc.reg_list_size =
2343 (u32)ARRAY_SIZE(verde_rlc_save_restore_register_list);
2344
2345 adev->gfx.rlc.cs_data = si_cs_data;
2346 src_ptr = adev->gfx.rlc.reg_list;
2347 dws = adev->gfx.rlc.reg_list_size;
2348 cs_data = adev->gfx.rlc.cs_data;
2349
2350 if (src_ptr) {
2351 /* init save restore block */
2352 r = amdgpu_gfx_rlc_init_sr(adev, dws);
2353 if (r)
2354 return r;
2355 }
2356
2357 if (cs_data) {
2358 /* clear state block */
2359 adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev);
2360 dws = adev->gfx.rlc.clear_state_size + (256 / 4);
2361
2362 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
2363 AMDGPU_GEM_DOMAIN_VRAM |
2364 AMDGPU_GEM_DOMAIN_GTT,
2365 &adev->gfx.rlc.clear_state_obj,
2366 &adev->gfx.rlc.clear_state_gpu_addr,
2367 (void **)&adev->gfx.rlc.cs_ptr);
2368 if (r) {
2369 dev_warn(adev->dev, "(%d) create RLC c bo failed\n", r);
2370 amdgpu_gfx_rlc_fini(adev);
2371 return r;
2372 }
2373
2374 /* set up the cs buffer */
2375 dst_ptr = adev->gfx.rlc.cs_ptr;
2376 reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256;
2377 dst_ptr[0] = cpu_to_le32(upper_32_bits(reg_list_mc_addr));
2378 dst_ptr[1] = cpu_to_le32(lower_32_bits(reg_list_mc_addr));
2379 dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size);
2380 gfx_v6_0_get_csb_buffer(adev, &dst_ptr[(256/4)]);
2381 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
2382 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
2383 }
2384
2385 return 0;
2386}
2387
2388static void gfx_v6_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
2389{
2390 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
2391
2392 if (!enable) {
2393 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
2394 WREG32(mmSPI_LB_CU_MASK, 0x00ff);
2395 }
2396}
2397
2398static void gfx_v6_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
2399{
2400 int i;
2401
2402 for (i = 0; i < adev->usec_timeout; i++) {
2403 if (RREG32(mmRLC_SERDES_MASTER_BUSY_0) == 0)
2404 break;
2405 udelay(1);
2406 }
2407
2408 for (i = 0; i < adev->usec_timeout; i++) {
2409 if (RREG32(mmRLC_SERDES_MASTER_BUSY_1) == 0)
2410 break;
2411 udelay(1);
2412 }
2413}
2414
2415static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)
2416{
2417 u32 tmp;
2418
2419 tmp = RREG32(mmRLC_CNTL);
2420 if (tmp != rlc)
2421 WREG32(mmRLC_CNTL, rlc);
2422}
2423
2424static u32 gfx_v6_0_halt_rlc(struct amdgpu_device *adev)
2425{
2426 u32 data, orig;
2427
2428 orig = data = RREG32(mmRLC_CNTL);
2429
2430 if (data & RLC_CNTL__RLC_ENABLE_F32_MASK) {
2431 data &= ~RLC_CNTL__RLC_ENABLE_F32_MASK;
2432 WREG32(mmRLC_CNTL, data);
2433
2434 gfx_v6_0_wait_for_rlc_serdes(adev);
2435 }
2436
2437 return orig;
2438}
2439
2440static void gfx_v6_0_rlc_stop(struct amdgpu_device *adev)
2441{
2442 WREG32(mmRLC_CNTL, 0);
2443
2444 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2445 gfx_v6_0_wait_for_rlc_serdes(adev);
2446}
2447
2448static void gfx_v6_0_rlc_start(struct amdgpu_device *adev)
2449{
2450 WREG32(mmRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
2451
2452 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2453
2454 udelay(50);
2455}
2456
2457static void gfx_v6_0_rlc_reset(struct amdgpu_device *adev)
2458{
2459 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2460 udelay(50);
2461 WREG32_FIELD(GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2462 udelay(50);
2463}
2464
2465static bool gfx_v6_0_lbpw_supported(struct amdgpu_device *adev)
2466{
2467 u32 tmp;
2468
2469 /* Enable LBPW only for DDR3 */
2470 tmp = RREG32(mmMC_SEQ_MISC0);
2471 if ((tmp & 0xF0000000) == 0xB0000000)
2472 return true;
2473 return false;
2474}
2475
2476static void gfx_v6_0_init_cg(struct amdgpu_device *adev)
2477{
2478}
2479
2480static int gfx_v6_0_rlc_resume(struct amdgpu_device *adev)
2481{
2482 u32 i;
2483 const struct rlc_firmware_header_v1_0 *hdr;
2484 const __le32 *fw_data;
2485 u32 fw_size;
2486
2487
2488 if (!adev->gfx.rlc_fw)
2489 return -EINVAL;
2490
2491 adev->gfx.rlc.funcs->stop(adev);
2492 adev->gfx.rlc.funcs->reset(adev);
2493 gfx_v6_0_init_pg(adev);
2494 gfx_v6_0_init_cg(adev);
2495
2496 WREG32(mmRLC_RL_BASE, 0);
2497 WREG32(mmRLC_RL_SIZE, 0);
2498 WREG32(mmRLC_LB_CNTL, 0);
2499 WREG32(mmRLC_LB_CNTR_MAX, 0xffffffff);
2500 WREG32(mmRLC_LB_CNTR_INIT, 0);
2501 WREG32(mmRLC_LB_INIT_CU_MASK, 0xffffffff);
2502
2503 WREG32(mmRLC_MC_CNTL, 0);
2504 WREG32(mmRLC_UCODE_CNTL, 0);
2505
2506 hdr = (const struct rlc_firmware_header_v1_0 *)adev->gfx.rlc_fw->data;
2507 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2508 fw_data = (const __le32 *)
2509 (adev->gfx.rlc_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2510
2511 amdgpu_ucode_print_rlc_hdr(&hdr->header);
2512
2513 for (i = 0; i < fw_size; i++) {
2514 WREG32(mmRLC_UCODE_ADDR, i);
2515 WREG32(mmRLC_UCODE_DATA, le32_to_cpup(fw_data++));
2516 }
2517 WREG32(mmRLC_UCODE_ADDR, 0);
2518
2519 gfx_v6_0_enable_lbpw(adev, gfx_v6_0_lbpw_supported(adev));
2520 adev->gfx.rlc.funcs->start(adev);
2521
2522 return 0;
2523}
2524
2525static void gfx_v6_0_enable_cgcg(struct amdgpu_device *adev, bool enable)
2526{
2527 u32 data, orig, tmp;
2528
2529 orig = data = RREG32(mmRLC_CGCG_CGLS_CTRL);
2530
2531 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
2532 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2533
2534 WREG32(mmRLC_GCPM_GENERAL_3, 0x00000080);
2535
2536 tmp = gfx_v6_0_halt_rlc(adev);
2537
2538 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2539 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2540 WREG32(mmRLC_SERDES_WR_CTRL, 0x00b000ff);
2541
2542 gfx_v6_0_wait_for_rlc_serdes(adev);
2543 gfx_v6_0_update_rlc(adev, tmp);
2544
2545 WREG32(mmRLC_SERDES_WR_CTRL, 0x007000ff);
2546
2547 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
2548 } else {
2549 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2550
2551 RREG32(mmCB_CGTT_SCLK_CTRL);
2552 RREG32(mmCB_CGTT_SCLK_CTRL);
2553 RREG32(mmCB_CGTT_SCLK_CTRL);
2554 RREG32(mmCB_CGTT_SCLK_CTRL);
2555
2556 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
2557 }
2558
2559 if (orig != data)
2560 WREG32(mmRLC_CGCG_CGLS_CTRL, data);
2561
2562}
2563
2564static void gfx_v6_0_enable_mgcg(struct amdgpu_device *adev, bool enable)
2565{
2566
2567 u32 data, orig, tmp = 0;
2568
2569 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
2570 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2571 data = 0x96940200;
2572 if (orig != data)
2573 WREG32(mmCGTS_SM_CTRL_REG, data);
2574
2575 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
2576 orig = data = RREG32(mmCP_MEM_SLP_CNTL);
2577 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2578 if (orig != data)
2579 WREG32(mmCP_MEM_SLP_CNTL, data);
2580 }
2581
2582 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2583 data &= 0xffffffc0;
2584 if (orig != data)
2585 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2586
2587 tmp = gfx_v6_0_halt_rlc(adev);
2588
2589 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2590 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2591 WREG32(mmRLC_SERDES_WR_CTRL, 0x00d000ff);
2592
2593 gfx_v6_0_update_rlc(adev, tmp);
2594 } else {
2595 orig = data = RREG32(mmRLC_CGTT_MGCG_OVERRIDE);
2596 data |= 0x00000003;
2597 if (orig != data)
2598 WREG32(mmRLC_CGTT_MGCG_OVERRIDE, data);
2599
2600 data = RREG32(mmCP_MEM_SLP_CNTL);
2601 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
2602 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
2603 WREG32(mmCP_MEM_SLP_CNTL, data);
2604 }
2605 orig = data = RREG32(mmCGTS_SM_CTRL_REG);
2606 data |= CGTS_SM_CTRL_REG__LS_OVERRIDE_MASK | CGTS_SM_CTRL_REG__OVERRIDE_MASK;
2607 if (orig != data)
2608 WREG32(mmCGTS_SM_CTRL_REG, data);
2609
2610 tmp = gfx_v6_0_halt_rlc(adev);
2611
2612 WREG32(mmRLC_SERDES_WR_MASTER_MASK_0, 0xffffffff);
2613 WREG32(mmRLC_SERDES_WR_MASTER_MASK_1, 0xffffffff);
2614 WREG32(mmRLC_SERDES_WR_CTRL, 0x00e000ff);
2615
2616 gfx_v6_0_update_rlc(adev, tmp);
2617 }
2618}
2619/*
2620static void gfx_v6_0_update_cg(struct amdgpu_device *adev,
2621 bool enable)
2622{
2623 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
2624 if (enable) {
2625 gfx_v6_0_enable_mgcg(adev, true);
2626 gfx_v6_0_enable_cgcg(adev, true);
2627 } else {
2628 gfx_v6_0_enable_cgcg(adev, false);
2629 gfx_v6_0_enable_mgcg(adev, false);
2630 }
2631 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
2632}
2633*/
2634
2635static void gfx_v6_0_enable_sclk_slowdown_on_pu(struct amdgpu_device *adev,
2636 bool enable)
2637{
2638}
2639
2640static void gfx_v6_0_enable_sclk_slowdown_on_pd(struct amdgpu_device *adev,
2641 bool enable)
2642{
2643}
2644
2645static void gfx_v6_0_enable_cp_pg(struct amdgpu_device *adev, bool enable)
2646{
2647 u32 data, orig;
2648
2649 orig = data = RREG32(mmRLC_PG_CNTL);
2650 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_CP))
2651 data &= ~0x8000;
2652 else
2653 data |= 0x8000;
2654 if (orig != data)
2655 WREG32(mmRLC_PG_CNTL, data);
2656}
2657
2658static void gfx_v6_0_enable_gds_pg(struct amdgpu_device *adev, bool enable)
2659{
2660}
2661/*
2662static void gfx_v6_0_init_cp_pg_table(struct amdgpu_device *adev)
2663{
2664 const __le32 *fw_data;
2665 volatile u32 *dst_ptr;
2666 int me, i, max_me = 4;
2667 u32 bo_offset = 0;
2668 u32 table_offset, table_size;
2669
2670 if (adev->asic_type == CHIP_KAVERI)
2671 max_me = 5;
2672
2673 if (adev->gfx.rlc.cp_table_ptr == NULL)
2674 return;
2675
2676 dst_ptr = adev->gfx.rlc.cp_table_ptr;
2677 for (me = 0; me < max_me; me++) {
2678 if (me == 0) {
2679 const struct gfx_firmware_header_v1_0 *hdr =
2680 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
2681 fw_data = (const __le32 *)
2682 (adev->gfx.ce_fw->data +
2683 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2684 table_offset = le32_to_cpu(hdr->jt_offset);
2685 table_size = le32_to_cpu(hdr->jt_size);
2686 } else if (me == 1) {
2687 const struct gfx_firmware_header_v1_0 *hdr =
2688 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
2689 fw_data = (const __le32 *)
2690 (adev->gfx.pfp_fw->data +
2691 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2692 table_offset = le32_to_cpu(hdr->jt_offset);
2693 table_size = le32_to_cpu(hdr->jt_size);
2694 } else if (me == 2) {
2695 const struct gfx_firmware_header_v1_0 *hdr =
2696 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
2697 fw_data = (const __le32 *)
2698 (adev->gfx.me_fw->data +
2699 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2700 table_offset = le32_to_cpu(hdr->jt_offset);
2701 table_size = le32_to_cpu(hdr->jt_size);
2702 } else if (me == 3) {
2703 const struct gfx_firmware_header_v1_0 *hdr =
2704 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2705 fw_data = (const __le32 *)
2706 (adev->gfx.mec_fw->data +
2707 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2708 table_offset = le32_to_cpu(hdr->jt_offset);
2709 table_size = le32_to_cpu(hdr->jt_size);
2710 } else {
2711 const struct gfx_firmware_header_v1_0 *hdr =
2712 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
2713 fw_data = (const __le32 *)
2714 (adev->gfx.mec2_fw->data +
2715 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2716 table_offset = le32_to_cpu(hdr->jt_offset);
2717 table_size = le32_to_cpu(hdr->jt_size);
2718 }
2719
2720 for (i = 0; i < table_size; i ++) {
2721 dst_ptr[bo_offset + i] =
2722 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
2723 }
2724
2725 bo_offset += table_size;
2726 }
2727}
2728*/
2729static void gfx_v6_0_enable_gfx_cgpg(struct amdgpu_device *adev,
2730 bool enable)
2731{
2732 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2733 WREG32(mmRLC_TTOP_D, RLC_PUD(0x10) | RLC_PDD(0x10) | RLC_TTPD(0x10) | RLC_MSD(0x10));
2734 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_ENABLE, 1);
2735 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 1);
2736 } else {
2737 WREG32_FIELD(RLC_AUTO_PG_CTRL, AUTO_PG_EN, 0);
2738 (void)RREG32(mmDB_RENDER_CONTROL);
2739 }
2740}
2741
2742static void gfx_v6_0_init_ao_cu_mask(struct amdgpu_device *adev)
2743{
2744 u32 tmp;
2745
2746 WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
2747
2748 tmp = RREG32(mmRLC_MAX_PG_CU);
2749 tmp &= ~RLC_MAX_PG_CU__MAX_POWERED_UP_CU_MASK;
2750 tmp |= (adev->gfx.cu_info.number << RLC_MAX_PG_CU__MAX_POWERED_UP_CU__SHIFT);
2751 WREG32(mmRLC_MAX_PG_CU, tmp);
2752}
2753
2754static void gfx_v6_0_enable_gfx_static_mgpg(struct amdgpu_device *adev,
2755 bool enable)
2756{
2757 u32 data, orig;
2758
2759 orig = data = RREG32(mmRLC_PG_CNTL);
2760 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG))
2761 data |= RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2762 else
2763 data &= ~RLC_PG_CNTL__STATIC_PER_CU_PG_ENABLE_MASK;
2764 if (orig != data)
2765 WREG32(mmRLC_PG_CNTL, data);
2766}
2767
2768static void gfx_v6_0_enable_gfx_dynamic_mgpg(struct amdgpu_device *adev,
2769 bool enable)
2770{
2771 u32 data, orig;
2772
2773 orig = data = RREG32(mmRLC_PG_CNTL);
2774 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG))
2775 data |= RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2776 else
2777 data &= ~RLC_PG_CNTL__DYN_PER_CU_PG_ENABLE_MASK;
2778 if (orig != data)
2779 WREG32(mmRLC_PG_CNTL, data);
2780}
2781
2782static void gfx_v6_0_init_gfx_cgpg(struct amdgpu_device *adev)
2783{
2784 u32 tmp;
2785
2786 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2787 WREG32_FIELD(RLC_PG_CNTL, GFX_POWER_GATING_SRC, 1);
2788 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2789
2790 tmp = RREG32(mmRLC_AUTO_PG_CTRL);
2791 tmp &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2792 tmp |= (0x700 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2793 tmp &= ~RLC_AUTO_PG_CTRL__PG_AFTER_GRBM_REG_SAVE_THRESHOLD_MASK;
2794 WREG32(mmRLC_AUTO_PG_CTRL, tmp);
2795}
2796
2797static void gfx_v6_0_update_gfx_pg(struct amdgpu_device *adev, bool enable)
2798{
2799 gfx_v6_0_enable_gfx_cgpg(adev, enable);
2800 gfx_v6_0_enable_gfx_static_mgpg(adev, enable);
2801 gfx_v6_0_enable_gfx_dynamic_mgpg(adev, enable);
2802}
2803
2804static u32 gfx_v6_0_get_csb_size(struct amdgpu_device *adev)
2805{
2806 u32 count = 0;
2807 const struct cs_section_def *sect = NULL;
2808 const struct cs_extent_def *ext = NULL;
2809
2810 if (adev->gfx.rlc.cs_data == NULL)
2811 return 0;
2812
2813 /* begin clear state */
2814 count += 2;
2815 /* context control state */
2816 count += 3;
2817
2818 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2819 for (ext = sect->section; ext->extent != NULL; ++ext) {
2820 if (sect->id == SECT_CONTEXT)
2821 count += 2 + ext->reg_count;
2822 else
2823 return 0;
2824 }
2825 }
2826 /* pa_sc_raster_config */
2827 count += 3;
2828 /* end clear state */
2829 count += 2;
2830 /* clear state */
2831 count += 2;
2832
2833 return count;
2834}
2835
2836static void gfx_v6_0_get_csb_buffer(struct amdgpu_device *adev,
2837 volatile u32 *buffer)
2838{
2839 u32 count = 0, i;
2840 const struct cs_section_def *sect = NULL;
2841 const struct cs_extent_def *ext = NULL;
2842
2843 if (adev->gfx.rlc.cs_data == NULL)
2844 return;
2845 if (buffer == NULL)
2846 return;
2847
2848 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2849 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2850 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2851 buffer[count++] = cpu_to_le32(0x80000000);
2852 buffer[count++] = cpu_to_le32(0x80000000);
2853
2854 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
2855 for (ext = sect->section; ext->extent != NULL; ++ext) {
2856 if (sect->id == SECT_CONTEXT) {
2857 buffer[count++] =
2858 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
2859 buffer[count++] = cpu_to_le32(ext->reg_index - 0xa000);
2860 for (i = 0; i < ext->reg_count; i++)
2861 buffer[count++] = cpu_to_le32(ext->extent[i]);
2862 } else {
2863 return;
2864 }
2865 }
2866 }
2867
2868 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
2869 buffer[count++] = cpu_to_le32(mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START);
2870 buffer[count++] = cpu_to_le32(adev->gfx.config.rb_config[0][0].raster_config);
2871
2872 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2873 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
2874
2875 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
2876 buffer[count++] = cpu_to_le32(0);
2877}
2878
2879static void gfx_v6_0_init_pg(struct amdgpu_device *adev)
2880{
2881 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2882 AMD_PG_SUPPORT_GFX_SMG |
2883 AMD_PG_SUPPORT_GFX_DMG |
2884 AMD_PG_SUPPORT_CP |
2885 AMD_PG_SUPPORT_GDS |
2886 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2887 gfx_v6_0_enable_sclk_slowdown_on_pu(adev, true);
2888 gfx_v6_0_enable_sclk_slowdown_on_pd(adev, true);
2889 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2890 gfx_v6_0_init_gfx_cgpg(adev);
2891 gfx_v6_0_enable_cp_pg(adev, true);
2892 gfx_v6_0_enable_gds_pg(adev, true);
2893 } else {
2894 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2895 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2896
2897 }
2898 gfx_v6_0_init_ao_cu_mask(adev);
2899 gfx_v6_0_update_gfx_pg(adev, true);
2900 } else {
2901
2902 WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);
2903 WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);
2904 }
2905}
2906
2907static void gfx_v6_0_fini_pg(struct amdgpu_device *adev)
2908{
2909 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2910 AMD_PG_SUPPORT_GFX_SMG |
2911 AMD_PG_SUPPORT_GFX_DMG |
2912 AMD_PG_SUPPORT_CP |
2913 AMD_PG_SUPPORT_GDS |
2914 AMD_PG_SUPPORT_RLC_SMU_HS)) {
2915 gfx_v6_0_update_gfx_pg(adev, false);
2916 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
2917 gfx_v6_0_enable_cp_pg(adev, false);
2918 gfx_v6_0_enable_gds_pg(adev, false);
2919 }
2920 }
2921}
2922
2923static uint64_t gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev)
2924{
2925 uint64_t clock;
2926
2927 mutex_lock(&adev->gfx.gpu_clock_mutex);
2928 WREG32(mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
2929 clock = (uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_LSB) |
2930 ((uint64_t)RREG32(mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
2931 mutex_unlock(&adev->gfx.gpu_clock_mutex);
2932 return clock;
2933}
2934
2935static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
2936{
2937 if (flags & AMDGPU_HAVE_CTX_SWITCH)
2938 gfx_v6_0_ring_emit_vgt_flush(ring);
2939 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2940 amdgpu_ring_write(ring, 0x80000000);
2941 amdgpu_ring_write(ring, 0);
2942}
2943
2944
2945static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
2946{
2947 WREG32(mmSQ_IND_INDEX,
2948 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
2949 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
2950 (address << SQ_IND_INDEX__INDEX__SHIFT) |
2951 (SQ_IND_INDEX__FORCE_READ_MASK));
2952 return RREG32(mmSQ_IND_DATA);
2953}
2954
2955static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
2956 uint32_t wave, uint32_t thread,
2957 uint32_t regno, uint32_t num, uint32_t *out)
2958{
2959 WREG32(mmSQ_IND_INDEX,
2960 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
2961 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
2962 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
2963 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
2964 (SQ_IND_INDEX__FORCE_READ_MASK) |
2965 (SQ_IND_INDEX__AUTO_INCR_MASK));
2966 while (num--)
2967 *(out++) = RREG32(mmSQ_IND_DATA);
2968}
2969
2970static void gfx_v6_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
2971{
2972 /* type 0 wave data */
2973 dst[(*no_fields)++] = 0;
2974 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
2975 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
2976 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
2977 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
2978 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
2979 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
2980 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
2981 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
2982 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
2983 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
2984 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
2985 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
2986 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_LO);
2987 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TBA_HI);
2988 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_LO);
2989 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TMA_HI);
2990 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
2991 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
2992 dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_MODE);
2993}
2994
2995static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
2996 uint32_t wave, uint32_t start,
2997 uint32_t size, uint32_t *dst)
2998{
2999 wave_read_regs(
3000 adev, simd, wave, 0,
3001 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
3002}
3003
3004static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev,
3005 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
3006{
3007 DRM_INFO("Not implemented\n");
3008}
3009
3010static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
3011 .get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
3012 .select_se_sh = &gfx_v6_0_select_se_sh,
3013 .read_wave_data = &gfx_v6_0_read_wave_data,
3014 .read_wave_sgprs = &gfx_v6_0_read_wave_sgprs,
3015 .select_me_pipe_q = &gfx_v6_0_select_me_pipe_q
3016};
3017
3018static const struct amdgpu_rlc_funcs gfx_v6_0_rlc_funcs = {
3019 .init = gfx_v6_0_rlc_init,
3020 .resume = gfx_v6_0_rlc_resume,
3021 .stop = gfx_v6_0_rlc_stop,
3022 .reset = gfx_v6_0_rlc_reset,
3023 .start = gfx_v6_0_rlc_start
3024};
3025
3026static int gfx_v6_0_early_init(struct amdgpu_ip_block *ip_block)
3027{
3028 struct amdgpu_device *adev = ip_block->adev;
3029
3030 adev->gfx.xcc_mask = 1;
3031 adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS;
3032 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
3033 GFX6_NUM_COMPUTE_RINGS);
3034 adev->gfx.funcs = &gfx_v6_0_gfx_funcs;
3035 adev->gfx.rlc.funcs = &gfx_v6_0_rlc_funcs;
3036 gfx_v6_0_set_ring_funcs(adev);
3037 gfx_v6_0_set_irq_funcs(adev);
3038
3039 return 0;
3040}
3041
3042static int gfx_v6_0_sw_init(struct amdgpu_ip_block *ip_block)
3043{
3044 struct amdgpu_ring *ring;
3045 struct amdgpu_device *adev = ip_block->adev;
3046 int i, r;
3047
3048 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
3049 if (r)
3050 return r;
3051
3052 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq);
3053 if (r)
3054 return r;
3055
3056 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq);
3057 if (r)
3058 return r;
3059
3060 r = gfx_v6_0_init_microcode(adev);
3061 if (r) {
3062 DRM_ERROR("Failed to load gfx firmware!\n");
3063 return r;
3064 }
3065
3066 r = adev->gfx.rlc.funcs->init(adev);
3067 if (r) {
3068 DRM_ERROR("Failed to init rlc BOs!\n");
3069 return r;
3070 }
3071
3072 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3073 ring = &adev->gfx.gfx_ring[i];
3074 ring->ring_obj = NULL;
3075 sprintf(ring->name, "gfx");
3076 r = amdgpu_ring_init(adev, ring, 2048,
3077 &adev->gfx.eop_irq,
3078 AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP,
3079 AMDGPU_RING_PRIO_DEFAULT, NULL);
3080 if (r)
3081 return r;
3082 }
3083
3084 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3085 unsigned irq_type;
3086
3087 if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
3088 DRM_ERROR("Too many (%d) compute rings!\n", i);
3089 break;
3090 }
3091 ring = &adev->gfx.compute_ring[i];
3092 ring->ring_obj = NULL;
3093 ring->use_doorbell = false;
3094 ring->doorbell_index = 0;
3095 ring->me = 1;
3096 ring->pipe = i;
3097 ring->queue = i;
3098 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
3099 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
3100 r = amdgpu_ring_init(adev, ring, 1024,
3101 &adev->gfx.eop_irq, irq_type,
3102 AMDGPU_RING_PRIO_DEFAULT, NULL);
3103 if (r)
3104 return r;
3105 }
3106
3107 return r;
3108}
3109
3110static int gfx_v6_0_sw_fini(struct amdgpu_ip_block *ip_block)
3111{
3112 int i;
3113 struct amdgpu_device *adev = ip_block->adev;
3114
3115 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3116 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
3117 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3118 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
3119
3120 amdgpu_gfx_rlc_fini(adev);
3121
3122 return 0;
3123}
3124
3125static int gfx_v6_0_hw_init(struct amdgpu_ip_block *ip_block)
3126{
3127 int r;
3128 struct amdgpu_device *adev = ip_block->adev;
3129
3130 gfx_v6_0_constants_init(adev);
3131
3132 r = adev->gfx.rlc.funcs->resume(adev);
3133 if (r)
3134 return r;
3135
3136 r = gfx_v6_0_cp_resume(adev);
3137 if (r)
3138 return r;
3139
3140 adev->gfx.ce_ram_size = 0x8000;
3141
3142 return r;
3143}
3144
3145static int gfx_v6_0_hw_fini(struct amdgpu_ip_block *ip_block)
3146{
3147 struct amdgpu_device *adev = ip_block->adev;
3148
3149 gfx_v6_0_cp_enable(adev, false);
3150 adev->gfx.rlc.funcs->stop(adev);
3151 gfx_v6_0_fini_pg(adev);
3152
3153 return 0;
3154}
3155
3156static int gfx_v6_0_suspend(struct amdgpu_ip_block *ip_block)
3157{
3158 return gfx_v6_0_hw_fini(ip_block);
3159}
3160
3161static int gfx_v6_0_resume(struct amdgpu_ip_block *ip_block)
3162{
3163 return gfx_v6_0_hw_init(ip_block);
3164}
3165
3166static bool gfx_v6_0_is_idle(void *handle)
3167{
3168 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3169
3170 if (RREG32(mmGRBM_STATUS) & GRBM_STATUS__GUI_ACTIVE_MASK)
3171 return false;
3172 else
3173 return true;
3174}
3175
3176static int gfx_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
3177{
3178 unsigned i;
3179 struct amdgpu_device *adev = ip_block->adev;
3180
3181 for (i = 0; i < adev->usec_timeout; i++) {
3182 if (gfx_v6_0_is_idle(adev))
3183 return 0;
3184 udelay(1);
3185 }
3186 return -ETIMEDOUT;
3187}
3188
3189static void gfx_v6_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
3190 enum amdgpu_interrupt_state state)
3191{
3192 u32 cp_int_cntl;
3193
3194 switch (state) {
3195 case AMDGPU_IRQ_STATE_DISABLE:
3196 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3197 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3198 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3199 break;
3200 case AMDGPU_IRQ_STATE_ENABLE:
3201 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3202 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK;
3203 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3204 break;
3205 default:
3206 break;
3207 }
3208}
3209
3210static void gfx_v6_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
3211 int ring,
3212 enum amdgpu_interrupt_state state)
3213{
3214 u32 cp_int_cntl;
3215 switch (state){
3216 case AMDGPU_IRQ_STATE_DISABLE:
3217 if (ring == 0) {
3218 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3219 cp_int_cntl &= ~CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3220 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3221 break;
3222 } else {
3223 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3224 cp_int_cntl &= ~CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3225 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3226 break;
3227
3228 }
3229 case AMDGPU_IRQ_STATE_ENABLE:
3230 if (ring == 0) {
3231 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1);
3232 cp_int_cntl |= CP_INT_CNTL_RING1__TIME_STAMP_INT_ENABLE_MASK;
3233 WREG32(mmCP_INT_CNTL_RING1, cp_int_cntl);
3234 break;
3235 } else {
3236 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING2);
3237 cp_int_cntl |= CP_INT_CNTL_RING2__TIME_STAMP_INT_ENABLE_MASK;
3238 WREG32(mmCP_INT_CNTL_RING2, cp_int_cntl);
3239 break;
3240
3241 }
3242
3243 default:
3244 BUG();
3245 break;
3246
3247 }
3248}
3249
3250static int gfx_v6_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
3251 struct amdgpu_irq_src *src,
3252 unsigned type,
3253 enum amdgpu_interrupt_state state)
3254{
3255 u32 cp_int_cntl;
3256
3257 switch (state) {
3258 case AMDGPU_IRQ_STATE_DISABLE:
3259 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3260 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3261 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3262 break;
3263 case AMDGPU_IRQ_STATE_ENABLE:
3264 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3265 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_REG_INT_ENABLE_MASK;
3266 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3267 break;
3268 default:
3269 break;
3270 }
3271
3272 return 0;
3273}
3274
3275static int gfx_v6_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
3276 struct amdgpu_irq_src *src,
3277 unsigned type,
3278 enum amdgpu_interrupt_state state)
3279{
3280 u32 cp_int_cntl;
3281
3282 switch (state) {
3283 case AMDGPU_IRQ_STATE_DISABLE:
3284 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3285 cp_int_cntl &= ~CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3286 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3287 break;
3288 case AMDGPU_IRQ_STATE_ENABLE:
3289 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
3290 cp_int_cntl |= CP_INT_CNTL_RING0__PRIV_INSTR_INT_ENABLE_MASK;
3291 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
3292 break;
3293 default:
3294 break;
3295 }
3296
3297 return 0;
3298}
3299
3300static int gfx_v6_0_set_eop_interrupt_state(struct amdgpu_device *adev,
3301 struct amdgpu_irq_src *src,
3302 unsigned type,
3303 enum amdgpu_interrupt_state state)
3304{
3305 switch (type) {
3306 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
3307 gfx_v6_0_set_gfx_eop_interrupt_state(adev, state);
3308 break;
3309 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
3310 gfx_v6_0_set_compute_eop_interrupt_state(adev, 0, state);
3311 break;
3312 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
3313 gfx_v6_0_set_compute_eop_interrupt_state(adev, 1, state);
3314 break;
3315 default:
3316 break;
3317 }
3318 return 0;
3319}
3320
3321static int gfx_v6_0_eop_irq(struct amdgpu_device *adev,
3322 struct amdgpu_irq_src *source,
3323 struct amdgpu_iv_entry *entry)
3324{
3325 switch (entry->ring_id) {
3326 case 0:
3327 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
3328 break;
3329 case 1:
3330 case 2:
3331 amdgpu_fence_process(&adev->gfx.compute_ring[entry->ring_id - 1]);
3332 break;
3333 default:
3334 break;
3335 }
3336 return 0;
3337}
3338
3339static void gfx_v6_0_fault(struct amdgpu_device *adev,
3340 struct amdgpu_iv_entry *entry)
3341{
3342 struct amdgpu_ring *ring;
3343
3344 switch (entry->ring_id) {
3345 case 0:
3346 ring = &adev->gfx.gfx_ring[0];
3347 break;
3348 case 1:
3349 case 2:
3350 ring = &adev->gfx.compute_ring[entry->ring_id - 1];
3351 break;
3352 default:
3353 return;
3354 }
3355 drm_sched_fault(&ring->sched);
3356}
3357
3358static int gfx_v6_0_priv_reg_irq(struct amdgpu_device *adev,
3359 struct amdgpu_irq_src *source,
3360 struct amdgpu_iv_entry *entry)
3361{
3362 DRM_ERROR("Illegal register access in command stream\n");
3363 gfx_v6_0_fault(adev, entry);
3364 return 0;
3365}
3366
3367static int gfx_v6_0_priv_inst_irq(struct amdgpu_device *adev,
3368 struct amdgpu_irq_src *source,
3369 struct amdgpu_iv_entry *entry)
3370{
3371 DRM_ERROR("Illegal instruction in command stream\n");
3372 gfx_v6_0_fault(adev, entry);
3373 return 0;
3374}
3375
3376static int gfx_v6_0_set_clockgating_state(void *handle,
3377 enum amd_clockgating_state state)
3378{
3379 bool gate = false;
3380 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3381
3382 if (state == AMD_CG_STATE_GATE)
3383 gate = true;
3384
3385 gfx_v6_0_enable_gui_idle_interrupt(adev, false);
3386 if (gate) {
3387 gfx_v6_0_enable_mgcg(adev, true);
3388 gfx_v6_0_enable_cgcg(adev, true);
3389 } else {
3390 gfx_v6_0_enable_cgcg(adev, false);
3391 gfx_v6_0_enable_mgcg(adev, false);
3392 }
3393 gfx_v6_0_enable_gui_idle_interrupt(adev, true);
3394
3395 return 0;
3396}
3397
3398static int gfx_v6_0_set_powergating_state(void *handle,
3399 enum amd_powergating_state state)
3400{
3401 bool gate = false;
3402 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3403
3404 if (state == AMD_PG_STATE_GATE)
3405 gate = true;
3406
3407 if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
3408 AMD_PG_SUPPORT_GFX_SMG |
3409 AMD_PG_SUPPORT_GFX_DMG |
3410 AMD_PG_SUPPORT_CP |
3411 AMD_PG_SUPPORT_GDS |
3412 AMD_PG_SUPPORT_RLC_SMU_HS)) {
3413 gfx_v6_0_update_gfx_pg(adev, gate);
3414 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) {
3415 gfx_v6_0_enable_cp_pg(adev, gate);
3416 gfx_v6_0_enable_gds_pg(adev, gate);
3417 }
3418 }
3419
3420 return 0;
3421}
3422
3423static void gfx_v6_0_emit_mem_sync(struct amdgpu_ring *ring)
3424{
3425 amdgpu_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
3426 amdgpu_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
3427 PACKET3_TC_ACTION_ENA |
3428 PACKET3_SH_KCACHE_ACTION_ENA |
3429 PACKET3_SH_ICACHE_ACTION_ENA); /* CP_COHER_CNTL */
3430 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
3431 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
3432 amdgpu_ring_write(ring, 0x0000000A); /* poll interval */
3433}
3434
3435static const struct amd_ip_funcs gfx_v6_0_ip_funcs = {
3436 .name = "gfx_v6_0",
3437 .early_init = gfx_v6_0_early_init,
3438 .sw_init = gfx_v6_0_sw_init,
3439 .sw_fini = gfx_v6_0_sw_fini,
3440 .hw_init = gfx_v6_0_hw_init,
3441 .hw_fini = gfx_v6_0_hw_fini,
3442 .suspend = gfx_v6_0_suspend,
3443 .resume = gfx_v6_0_resume,
3444 .is_idle = gfx_v6_0_is_idle,
3445 .wait_for_idle = gfx_v6_0_wait_for_idle,
3446 .set_clockgating_state = gfx_v6_0_set_clockgating_state,
3447 .set_powergating_state = gfx_v6_0_set_powergating_state,
3448};
3449
3450static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
3451 .type = AMDGPU_RING_TYPE_GFX,
3452 .align_mask = 0xff,
3453 .nop = 0x80000000,
3454 .support_64bit_ptrs = false,
3455 .get_rptr = gfx_v6_0_ring_get_rptr,
3456 .get_wptr = gfx_v6_0_ring_get_wptr,
3457 .set_wptr = gfx_v6_0_ring_set_wptr_gfx,
3458 .emit_frame_size =
3459 5 + 5 + /* hdp flush / invalidate */
3460 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3461 7 + 4 + /* gfx_v6_0_ring_emit_pipeline_sync */
3462 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + 6 + /* gfx_v6_0_ring_emit_vm_flush */
3463 3 + 2 + /* gfx_v6_ring_emit_cntxcntl including vgt flush */
3464 5, /* SURFACE_SYNC */
3465 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3466 .emit_ib = gfx_v6_0_ring_emit_ib,
3467 .emit_fence = gfx_v6_0_ring_emit_fence,
3468 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3469 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3470 .test_ring = gfx_v6_0_ring_test_ring,
3471 .test_ib = gfx_v6_0_ring_test_ib,
3472 .insert_nop = amdgpu_ring_insert_nop,
3473 .emit_cntxcntl = gfx_v6_ring_emit_cntxcntl,
3474 .emit_wreg = gfx_v6_0_ring_emit_wreg,
3475 .emit_mem_sync = gfx_v6_0_emit_mem_sync,
3476};
3477
3478static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
3479 .type = AMDGPU_RING_TYPE_COMPUTE,
3480 .align_mask = 0xff,
3481 .nop = 0x80000000,
3482 .get_rptr = gfx_v6_0_ring_get_rptr,
3483 .get_wptr = gfx_v6_0_ring_get_wptr,
3484 .set_wptr = gfx_v6_0_ring_set_wptr_compute,
3485 .emit_frame_size =
3486 5 + 5 + /* hdp flush / invalidate */
3487 7 + /* gfx_v6_0_ring_emit_pipeline_sync */
3488 SI_FLUSH_GPU_TLB_NUM_WREG * 5 + 7 + /* gfx_v6_0_ring_emit_vm_flush */
3489 14 + 14 + 14 + /* gfx_v6_0_ring_emit_fence x3 for user fence, vm fence */
3490 5, /* SURFACE_SYNC */
3491 .emit_ib_size = 6, /* gfx_v6_0_ring_emit_ib */
3492 .emit_ib = gfx_v6_0_ring_emit_ib,
3493 .emit_fence = gfx_v6_0_ring_emit_fence,
3494 .emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
3495 .emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
3496 .test_ring = gfx_v6_0_ring_test_ring,
3497 .test_ib = gfx_v6_0_ring_test_ib,
3498 .insert_nop = amdgpu_ring_insert_nop,
3499 .emit_wreg = gfx_v6_0_ring_emit_wreg,
3500 .emit_mem_sync = gfx_v6_0_emit_mem_sync,
3501};
3502
3503static void gfx_v6_0_set_ring_funcs(struct amdgpu_device *adev)
3504{
3505 int i;
3506
3507 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
3508 adev->gfx.gfx_ring[i].funcs = &gfx_v6_0_ring_funcs_gfx;
3509 for (i = 0; i < adev->gfx.num_compute_rings; i++)
3510 adev->gfx.compute_ring[i].funcs = &gfx_v6_0_ring_funcs_compute;
3511}
3512
3513static const struct amdgpu_irq_src_funcs gfx_v6_0_eop_irq_funcs = {
3514 .set = gfx_v6_0_set_eop_interrupt_state,
3515 .process = gfx_v6_0_eop_irq,
3516};
3517
3518static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_reg_irq_funcs = {
3519 .set = gfx_v6_0_set_priv_reg_fault_state,
3520 .process = gfx_v6_0_priv_reg_irq,
3521};
3522
3523static const struct amdgpu_irq_src_funcs gfx_v6_0_priv_inst_irq_funcs = {
3524 .set = gfx_v6_0_set_priv_inst_fault_state,
3525 .process = gfx_v6_0_priv_inst_irq,
3526};
3527
3528static void gfx_v6_0_set_irq_funcs(struct amdgpu_device *adev)
3529{
3530 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
3531 adev->gfx.eop_irq.funcs = &gfx_v6_0_eop_irq_funcs;
3532
3533 adev->gfx.priv_reg_irq.num_types = 1;
3534 adev->gfx.priv_reg_irq.funcs = &gfx_v6_0_priv_reg_irq_funcs;
3535
3536 adev->gfx.priv_inst_irq.num_types = 1;
3537 adev->gfx.priv_inst_irq.funcs = &gfx_v6_0_priv_inst_irq_funcs;
3538}
3539
3540static void gfx_v6_0_get_cu_info(struct amdgpu_device *adev)
3541{
3542 int i, j, k, counter, active_cu_number = 0;
3543 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
3544 struct amdgpu_cu_info *cu_info = &adev->gfx.cu_info;
3545 unsigned disable_masks[4 * 2];
3546 u32 ao_cu_num;
3547
3548 if (adev->flags & AMD_IS_APU)
3549 ao_cu_num = 2;
3550 else
3551 ao_cu_num = adev->gfx.config.max_cu_per_sh;
3552
3553 memset(cu_info, 0, sizeof(*cu_info));
3554
3555 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
3556
3557 mutex_lock(&adev->grbm_idx_mutex);
3558 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
3559 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
3560 mask = 1;
3561 ao_bitmap = 0;
3562 counter = 0;
3563 gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff, 0);
3564 if (i < 4 && j < 2)
3565 gfx_v6_0_set_user_cu_inactive_bitmap(
3566 adev, disable_masks[i * 2 + j]);
3567 bitmap = gfx_v6_0_get_cu_enabled(adev);
3568 cu_info->bitmap[0][i][j] = bitmap;
3569
3570 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
3571 if (bitmap & mask) {
3572 if (counter < ao_cu_num)
3573 ao_bitmap |= mask;
3574 counter ++;
3575 }
3576 mask <<= 1;
3577 }
3578 active_cu_number += counter;
3579 if (i < 2 && j < 2)
3580 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
3581 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
3582 }
3583 }
3584
3585 gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
3586 mutex_unlock(&adev->grbm_idx_mutex);
3587
3588 cu_info->number = active_cu_number;
3589 cu_info->ao_cu_mask = ao_cu_mask;
3590}
3591
3592const struct amdgpu_ip_block_version gfx_v6_0_ip_block =
3593{
3594 .type = AMD_IP_BLOCK_TYPE_GFX,
3595 .major = 6,
3596 .minor = 0,
3597 .rev = 0,
3598 .funcs = &gfx_v6_0_ip_funcs,
3599};