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1/*
2 * drivers/net/phy/broadcom.c
3 *
4 * Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet
5 * transceivers.
6 *
7 * Copyright (c) 2006 Maciej W. Rozycki
8 *
9 * Inspired by code written by Amy Fong.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 */
16
17#include "bcm-phy-lib.h"
18#include <linux/module.h>
19#include <linux/phy.h>
20#include <linux/brcmphy.h>
21#include <linux/of.h>
22
23#define BRCM_PHY_MODEL(phydev) \
24 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
25
26#define BRCM_PHY_REV(phydev) \
27 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
28
29MODULE_DESCRIPTION("Broadcom PHY driver");
30MODULE_AUTHOR("Maciej W. Rozycki");
31MODULE_LICENSE("GPL");
32
33static int bcm54210e_config_init(struct phy_device *phydev)
34{
35 int val;
36
37 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
38 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
39 val |= MII_BCM54XX_AUXCTL_MISC_WREN;
40 bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, val);
41
42 val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
43 val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
44 bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
45
46 if (phydev->dev_flags & PHY_BRCM_EN_MASTER_MODE) {
47 val = phy_read(phydev, MII_CTRL1000);
48 val |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
49 phy_write(phydev, MII_CTRL1000, val);
50 }
51
52 return 0;
53}
54
55static int bcm54612e_config_init(struct phy_device *phydev)
56{
57 /* Clear TX internal delay unless requested. */
58 if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
59 (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
60 /* Disable TXD to GTXCLK clock delay (default set) */
61 /* Bit 9 is the only field in shadow register 00011 */
62 bcm_phy_write_shadow(phydev, 0x03, 0);
63 }
64
65 /* Clear RX internal delay unless requested. */
66 if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
67 (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
68 u16 reg;
69
70 reg = bcm54xx_auxctl_read(phydev,
71 MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
72 /* Disable RXD to RXC delay (default set) */
73 reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
74 /* Clear shadow selector field */
75 reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
76 bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
77 MII_BCM54XX_AUXCTL_MISC_WREN | reg);
78 }
79
80 return 0;
81}
82
83static int bcm5481x_config(struct phy_device *phydev)
84{
85 int rc, val;
86
87 /* handling PHY's internal RX clock delay */
88 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
89 val |= MII_BCM54XX_AUXCTL_MISC_WREN;
90 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
91 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
92 /* Disable RGMII RXC-RXD skew */
93 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
94 }
95 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
96 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
97 /* Enable RGMII RXC-RXD skew */
98 val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
99 }
100 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
101 val);
102 if (rc < 0)
103 return rc;
104
105 /* handling PHY's internal TX clock delay */
106 val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
107 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
108 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
109 /* Disable internal TX clock delay */
110 val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
111 }
112 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
113 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
114 /* Enable internal TX clock delay */
115 val |= BCM54810_SHD_CLK_CTL_GTXCLK_EN;
116 }
117 rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
118 if (rc < 0)
119 return rc;
120
121 return 0;
122}
123
124/* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
125static int bcm50610_a0_workaround(struct phy_device *phydev)
126{
127 int err;
128
129 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH0,
130 MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN |
131 MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF);
132 if (err < 0)
133 return err;
134
135 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH3,
136 MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ);
137 if (err < 0)
138 return err;
139
140 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75,
141 MII_BCM54XX_EXP_EXP75_VDACCTRL);
142 if (err < 0)
143 return err;
144
145 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP96,
146 MII_BCM54XX_EXP_EXP96_MYST);
147 if (err < 0)
148 return err;
149
150 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP97,
151 MII_BCM54XX_EXP_EXP97_MYST);
152
153 return err;
154}
155
156static int bcm54xx_phydsp_config(struct phy_device *phydev)
157{
158 int err, err2;
159
160 /* Enable the SMDSP clock */
161 err = bcm54xx_auxctl_write(phydev,
162 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
163 MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA |
164 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
165 if (err < 0)
166 return err;
167
168 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
169 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) {
170 /* Clear bit 9 to fix a phy interop issue. */
171 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08,
172 MII_BCM54XX_EXP_EXP08_RJCT_2MHZ);
173 if (err < 0)
174 goto error;
175
176 if (phydev->drv->phy_id == PHY_ID_BCM50610) {
177 err = bcm50610_a0_workaround(phydev);
178 if (err < 0)
179 goto error;
180 }
181 }
182
183 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
184 int val;
185
186 val = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP75);
187 if (val < 0)
188 goto error;
189
190 val |= MII_BCM54XX_EXP_EXP75_CM_OSC;
191 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, val);
192 }
193
194error:
195 /* Disable the SMDSP clock */
196 err2 = bcm54xx_auxctl_write(phydev,
197 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
198 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
199
200 /* Return the first error reported. */
201 return err ? err : err2;
202}
203
204static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
205{
206 u32 orig;
207 int val;
208 bool clk125en = true;
209
210 /* Abort if we are using an untested phy. */
211 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 &&
212 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 &&
213 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M)
214 return;
215
216 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
217 if (val < 0)
218 return;
219
220 orig = val;
221
222 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
223 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
224 BRCM_PHY_REV(phydev) >= 0x3) {
225 /*
226 * Here, bit 0 _disables_ CLK125 when set.
227 * This bit is set by default.
228 */
229 clk125en = false;
230 } else {
231 if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) {
232 /* Here, bit 0 _enables_ CLK125 when set */
233 val &= ~BCM54XX_SHD_SCR3_DEF_CLK125;
234 clk125en = false;
235 }
236 }
237
238 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
239 val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS;
240 else
241 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
242
243 if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY)
244 val |= BCM54XX_SHD_SCR3_TRDDAPD;
245
246 if (orig != val)
247 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
248
249 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);
250 if (val < 0)
251 return;
252
253 orig = val;
254
255 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
256 val |= BCM54XX_SHD_APD_EN;
257 else
258 val &= ~BCM54XX_SHD_APD_EN;
259
260 if (orig != val)
261 bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);
262}
263
264static int bcm54xx_config_init(struct phy_device *phydev)
265{
266 int reg, err, val;
267
268 reg = phy_read(phydev, MII_BCM54XX_ECR);
269 if (reg < 0)
270 return reg;
271
272 /* Mask interrupts globally. */
273 reg |= MII_BCM54XX_ECR_IM;
274 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
275 if (err < 0)
276 return err;
277
278 /* Unmask events we are interested in. */
279 reg = ~(MII_BCM54XX_INT_DUPLEX |
280 MII_BCM54XX_INT_SPEED |
281 MII_BCM54XX_INT_LINK);
282 err = phy_write(phydev, MII_BCM54XX_IMR, reg);
283 if (err < 0)
284 return err;
285
286 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
287 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
288 (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
289 bcm_phy_write_shadow(phydev, BCM54XX_SHD_RGMII_MODE, 0);
290
291 if ((phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) ||
292 (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) ||
293 (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
294 bcm54xx_adjust_rxrefclk(phydev);
295
296 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E) {
297 err = bcm54210e_config_init(phydev);
298 if (err)
299 return err;
300 } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54612E) {
301 err = bcm54612e_config_init(phydev);
302 if (err)
303 return err;
304 } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
305 /* For BCM54810, we need to disable BroadR-Reach function */
306 val = bcm_phy_read_exp(phydev,
307 BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
308 val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
309 err = bcm_phy_write_exp(phydev,
310 BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
311 val);
312 if (err < 0)
313 return err;
314 }
315
316 bcm54xx_phydsp_config(phydev);
317
318 return 0;
319}
320
321static int bcm5482_config_init(struct phy_device *phydev)
322{
323 int err, reg;
324
325 err = bcm54xx_config_init(phydev);
326
327 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
328 /*
329 * Enable secondary SerDes and its use as an LED source
330 */
331 reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_SSD);
332 bcm_phy_write_shadow(phydev, BCM5482_SHD_SSD,
333 reg |
334 BCM5482_SHD_SSD_LEDM |
335 BCM5482_SHD_SSD_EN);
336
337 /*
338 * Enable SGMII slave mode and auto-detection
339 */
340 reg = BCM5482_SSD_SGMII_SLAVE | MII_BCM54XX_EXP_SEL_SSD;
341 err = bcm_phy_read_exp(phydev, reg);
342 if (err < 0)
343 return err;
344 err = bcm_phy_write_exp(phydev, reg, err |
345 BCM5482_SSD_SGMII_SLAVE_EN |
346 BCM5482_SSD_SGMII_SLAVE_AD);
347 if (err < 0)
348 return err;
349
350 /*
351 * Disable secondary SerDes powerdown
352 */
353 reg = BCM5482_SSD_1000BX_CTL | MII_BCM54XX_EXP_SEL_SSD;
354 err = bcm_phy_read_exp(phydev, reg);
355 if (err < 0)
356 return err;
357 err = bcm_phy_write_exp(phydev, reg,
358 err & ~BCM5482_SSD_1000BX_CTL_PWRDOWN);
359 if (err < 0)
360 return err;
361
362 /*
363 * Select 1000BASE-X register set (primary SerDes)
364 */
365 reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_MODE);
366 bcm_phy_write_shadow(phydev, BCM5482_SHD_MODE,
367 reg | BCM5482_SHD_MODE_1000BX);
368
369 /*
370 * LED1=ACTIVITYLED, LED3=LINKSPD[2]
371 * (Use LED1 as secondary SerDes ACTIVITY LED)
372 */
373 bcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1,
374 BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_ACTIVITYLED) |
375 BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_LINKSPD2));
376
377 /*
378 * Auto-negotiation doesn't seem to work quite right
379 * in this mode, so we disable it and force it to the
380 * right speed/duplex setting. Only 'link status'
381 * is important.
382 */
383 phydev->autoneg = AUTONEG_DISABLE;
384 phydev->speed = SPEED_1000;
385 phydev->duplex = DUPLEX_FULL;
386 }
387
388 return err;
389}
390
391static int bcm5482_read_status(struct phy_device *phydev)
392{
393 int err;
394
395 err = genphy_read_status(phydev);
396
397 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
398 /*
399 * Only link status matters for 1000Base-X mode, so force
400 * 1000 Mbit/s full-duplex status
401 */
402 if (phydev->link) {
403 phydev->speed = SPEED_1000;
404 phydev->duplex = DUPLEX_FULL;
405 }
406 }
407
408 return err;
409}
410
411static int bcm5481_config_aneg(struct phy_device *phydev)
412{
413 struct device_node *np = phydev->mdio.dev.of_node;
414 int ret;
415
416 /* Aneg firsly. */
417 ret = genphy_config_aneg(phydev);
418
419 /* Then we can set up the delay. */
420 bcm5481x_config(phydev);
421
422 if (of_property_read_bool(np, "enet-phy-lane-swap")) {
423 /* Lane Swap - Undocumented register...magic! */
424 ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
425 0x11B);
426 if (ret < 0)
427 return ret;
428 }
429
430 return ret;
431}
432
433static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
434{
435 int val;
436
437 val = phy_read(phydev, reg);
438 if (val < 0)
439 return val;
440
441 return phy_write(phydev, reg, val | set);
442}
443
444static int brcm_fet_config_init(struct phy_device *phydev)
445{
446 int reg, err, err2, brcmtest;
447
448 /* Reset the PHY to bring it to a known state. */
449 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
450 if (err < 0)
451 return err;
452
453 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
454 if (reg < 0)
455 return reg;
456
457 /* Unmask events we are interested in and mask interrupts globally. */
458 reg = MII_BRCM_FET_IR_DUPLEX_EN |
459 MII_BRCM_FET_IR_SPEED_EN |
460 MII_BRCM_FET_IR_LINK_EN |
461 MII_BRCM_FET_IR_ENABLE |
462 MII_BRCM_FET_IR_MASK;
463
464 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
465 if (err < 0)
466 return err;
467
468 /* Enable shadow register access */
469 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
470 if (brcmtest < 0)
471 return brcmtest;
472
473 reg = brcmtest | MII_BRCM_FET_BT_SRE;
474
475 err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
476 if (err < 0)
477 return err;
478
479 /* Set the LED mode */
480 reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);
481 if (reg < 0) {
482 err = reg;
483 goto done;
484 }
485
486 reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK;
487 reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1;
488
489 err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);
490 if (err < 0)
491 goto done;
492
493 /* Enable auto MDIX */
494 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,
495 MII_BRCM_FET_SHDW_MC_FAME);
496 if (err < 0)
497 goto done;
498
499 if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) {
500 /* Enable auto power down */
501 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
502 MII_BRCM_FET_SHDW_AS2_APDE);
503 }
504
505done:
506 /* Disable shadow register access */
507 err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
508 if (!err)
509 err = err2;
510
511 return err;
512}
513
514static int brcm_fet_ack_interrupt(struct phy_device *phydev)
515{
516 int reg;
517
518 /* Clear pending interrupts. */
519 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
520 if (reg < 0)
521 return reg;
522
523 return 0;
524}
525
526static int brcm_fet_config_intr(struct phy_device *phydev)
527{
528 int reg, err;
529
530 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
531 if (reg < 0)
532 return reg;
533
534 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
535 reg &= ~MII_BRCM_FET_IR_MASK;
536 else
537 reg |= MII_BRCM_FET_IR_MASK;
538
539 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
540 return err;
541}
542
543struct bcm53xx_phy_priv {
544 u64 *stats;
545};
546
547static int bcm53xx_phy_probe(struct phy_device *phydev)
548{
549 struct bcm53xx_phy_priv *priv;
550
551 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
552 if (!priv)
553 return -ENOMEM;
554
555 phydev->priv = priv;
556
557 priv->stats = devm_kcalloc(&phydev->mdio.dev,
558 bcm_phy_get_sset_count(phydev), sizeof(u64),
559 GFP_KERNEL);
560 if (!priv->stats)
561 return -ENOMEM;
562
563 return 0;
564}
565
566static void bcm53xx_phy_get_stats(struct phy_device *phydev,
567 struct ethtool_stats *stats, u64 *data)
568{
569 struct bcm53xx_phy_priv *priv = phydev->priv;
570
571 bcm_phy_get_stats(phydev, priv->stats, stats, data);
572}
573
574static struct phy_driver broadcom_drivers[] = {
575{
576 .phy_id = PHY_ID_BCM5411,
577 .phy_id_mask = 0xfffffff0,
578 .name = "Broadcom BCM5411",
579 .features = PHY_GBIT_FEATURES,
580 .flags = PHY_HAS_INTERRUPT,
581 .config_init = bcm54xx_config_init,
582 .ack_interrupt = bcm_phy_ack_intr,
583 .config_intr = bcm_phy_config_intr,
584}, {
585 .phy_id = PHY_ID_BCM5421,
586 .phy_id_mask = 0xfffffff0,
587 .name = "Broadcom BCM5421",
588 .features = PHY_GBIT_FEATURES,
589 .flags = PHY_HAS_INTERRUPT,
590 .config_init = bcm54xx_config_init,
591 .ack_interrupt = bcm_phy_ack_intr,
592 .config_intr = bcm_phy_config_intr,
593}, {
594 .phy_id = PHY_ID_BCM54210E,
595 .phy_id_mask = 0xfffffff0,
596 .name = "Broadcom BCM54210E",
597 .features = PHY_GBIT_FEATURES,
598 .flags = PHY_HAS_INTERRUPT,
599 .config_init = bcm54xx_config_init,
600 .ack_interrupt = bcm_phy_ack_intr,
601 .config_intr = bcm_phy_config_intr,
602}, {
603 .phy_id = PHY_ID_BCM5461,
604 .phy_id_mask = 0xfffffff0,
605 .name = "Broadcom BCM5461",
606 .features = PHY_GBIT_FEATURES,
607 .flags = PHY_HAS_INTERRUPT,
608 .config_init = bcm54xx_config_init,
609 .ack_interrupt = bcm_phy_ack_intr,
610 .config_intr = bcm_phy_config_intr,
611}, {
612 .phy_id = PHY_ID_BCM54612E,
613 .phy_id_mask = 0xfffffff0,
614 .name = "Broadcom BCM54612E",
615 .features = PHY_GBIT_FEATURES,
616 .flags = PHY_HAS_INTERRUPT,
617 .config_init = bcm54xx_config_init,
618 .ack_interrupt = bcm_phy_ack_intr,
619 .config_intr = bcm_phy_config_intr,
620}, {
621 .phy_id = PHY_ID_BCM54616S,
622 .phy_id_mask = 0xfffffff0,
623 .name = "Broadcom BCM54616S",
624 .features = PHY_GBIT_FEATURES,
625 .flags = PHY_HAS_INTERRUPT,
626 .config_init = bcm54xx_config_init,
627 .ack_interrupt = bcm_phy_ack_intr,
628 .config_intr = bcm_phy_config_intr,
629}, {
630 .phy_id = PHY_ID_BCM5464,
631 .phy_id_mask = 0xfffffff0,
632 .name = "Broadcom BCM5464",
633 .features = PHY_GBIT_FEATURES,
634 .flags = PHY_HAS_INTERRUPT,
635 .config_init = bcm54xx_config_init,
636 .ack_interrupt = bcm_phy_ack_intr,
637 .config_intr = bcm_phy_config_intr,
638}, {
639 .phy_id = PHY_ID_BCM5481,
640 .phy_id_mask = 0xfffffff0,
641 .name = "Broadcom BCM5481",
642 .features = PHY_GBIT_FEATURES,
643 .flags = PHY_HAS_INTERRUPT,
644 .config_init = bcm54xx_config_init,
645 .config_aneg = bcm5481_config_aneg,
646 .ack_interrupt = bcm_phy_ack_intr,
647 .config_intr = bcm_phy_config_intr,
648}, {
649 .phy_id = PHY_ID_BCM54810,
650 .phy_id_mask = 0xfffffff0,
651 .name = "Broadcom BCM54810",
652 .features = PHY_GBIT_FEATURES,
653 .flags = PHY_HAS_INTERRUPT,
654 .config_init = bcm54xx_config_init,
655 .config_aneg = bcm5481_config_aneg,
656 .ack_interrupt = bcm_phy_ack_intr,
657 .config_intr = bcm_phy_config_intr,
658}, {
659 .phy_id = PHY_ID_BCM5482,
660 .phy_id_mask = 0xfffffff0,
661 .name = "Broadcom BCM5482",
662 .features = PHY_GBIT_FEATURES,
663 .flags = PHY_HAS_INTERRUPT,
664 .config_init = bcm5482_config_init,
665 .read_status = bcm5482_read_status,
666 .ack_interrupt = bcm_phy_ack_intr,
667 .config_intr = bcm_phy_config_intr,
668}, {
669 .phy_id = PHY_ID_BCM50610,
670 .phy_id_mask = 0xfffffff0,
671 .name = "Broadcom BCM50610",
672 .features = PHY_GBIT_FEATURES,
673 .flags = PHY_HAS_INTERRUPT,
674 .config_init = bcm54xx_config_init,
675 .ack_interrupt = bcm_phy_ack_intr,
676 .config_intr = bcm_phy_config_intr,
677}, {
678 .phy_id = PHY_ID_BCM50610M,
679 .phy_id_mask = 0xfffffff0,
680 .name = "Broadcom BCM50610M",
681 .features = PHY_GBIT_FEATURES,
682 .flags = PHY_HAS_INTERRUPT,
683 .config_init = bcm54xx_config_init,
684 .ack_interrupt = bcm_phy_ack_intr,
685 .config_intr = bcm_phy_config_intr,
686}, {
687 .phy_id = PHY_ID_BCM57780,
688 .phy_id_mask = 0xfffffff0,
689 .name = "Broadcom BCM57780",
690 .features = PHY_GBIT_FEATURES,
691 .flags = PHY_HAS_INTERRUPT,
692 .config_init = bcm54xx_config_init,
693 .ack_interrupt = bcm_phy_ack_intr,
694 .config_intr = bcm_phy_config_intr,
695}, {
696 .phy_id = PHY_ID_BCMAC131,
697 .phy_id_mask = 0xfffffff0,
698 .name = "Broadcom BCMAC131",
699 .features = PHY_BASIC_FEATURES,
700 .flags = PHY_HAS_INTERRUPT,
701 .config_init = brcm_fet_config_init,
702 .ack_interrupt = brcm_fet_ack_interrupt,
703 .config_intr = brcm_fet_config_intr,
704}, {
705 .phy_id = PHY_ID_BCM5241,
706 .phy_id_mask = 0xfffffff0,
707 .name = "Broadcom BCM5241",
708 .features = PHY_BASIC_FEATURES,
709 .flags = PHY_HAS_INTERRUPT,
710 .config_init = brcm_fet_config_init,
711 .ack_interrupt = brcm_fet_ack_interrupt,
712 .config_intr = brcm_fet_config_intr,
713}, {
714 .phy_id = PHY_ID_BCM5395,
715 .phy_id_mask = 0xfffffff0,
716 .name = "Broadcom BCM5395",
717 .flags = PHY_IS_INTERNAL,
718 .features = PHY_GBIT_FEATURES,
719 .get_sset_count = bcm_phy_get_sset_count,
720 .get_strings = bcm_phy_get_strings,
721 .get_stats = bcm53xx_phy_get_stats,
722 .probe = bcm53xx_phy_probe,
723}, {
724 .phy_id = PHY_ID_BCM89610,
725 .phy_id_mask = 0xfffffff0,
726 .name = "Broadcom BCM89610",
727 .features = PHY_GBIT_FEATURES,
728 .flags = PHY_HAS_INTERRUPT,
729 .config_init = bcm54xx_config_init,
730 .ack_interrupt = bcm_phy_ack_intr,
731 .config_intr = bcm_phy_config_intr,
732} };
733
734module_phy_driver(broadcom_drivers);
735
736static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
737 { PHY_ID_BCM5411, 0xfffffff0 },
738 { PHY_ID_BCM5421, 0xfffffff0 },
739 { PHY_ID_BCM54210E, 0xfffffff0 },
740 { PHY_ID_BCM5461, 0xfffffff0 },
741 { PHY_ID_BCM54612E, 0xfffffff0 },
742 { PHY_ID_BCM54616S, 0xfffffff0 },
743 { PHY_ID_BCM5464, 0xfffffff0 },
744 { PHY_ID_BCM5481, 0xfffffff0 },
745 { PHY_ID_BCM54810, 0xfffffff0 },
746 { PHY_ID_BCM5482, 0xfffffff0 },
747 { PHY_ID_BCM50610, 0xfffffff0 },
748 { PHY_ID_BCM50610M, 0xfffffff0 },
749 { PHY_ID_BCM57780, 0xfffffff0 },
750 { PHY_ID_BCMAC131, 0xfffffff0 },
751 { PHY_ID_BCM5241, 0xfffffff0 },
752 { PHY_ID_BCM5395, 0xfffffff0 },
753 { PHY_ID_BCM89610, 0xfffffff0 },
754 { }
755};
756
757MODULE_DEVICE_TABLE(mdio, broadcom_tbl);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/broadcom.c
4 *
5 * Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet
6 * transceivers.
7 *
8 * Copyright (c) 2006 Maciej W. Rozycki
9 *
10 * Inspired by code written by Amy Fong.
11 */
12
13#include "bcm-phy-lib.h"
14#include <linux/delay.h>
15#include <linux/module.h>
16#include <linux/phy.h>
17#include <linux/brcmphy.h>
18#include <linux/of.h>
19
20#define BRCM_PHY_MODEL(phydev) \
21 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
22
23#define BRCM_PHY_REV(phydev) \
24 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
25
26MODULE_DESCRIPTION("Broadcom PHY driver");
27MODULE_AUTHOR("Maciej W. Rozycki");
28MODULE_LICENSE("GPL");
29
30struct bcm54xx_phy_priv {
31 u64 *stats;
32 struct bcm_ptp_private *ptp;
33};
34
35static int bcm54xx_config_clock_delay(struct phy_device *phydev)
36{
37 int rc, val;
38
39 /* handling PHY's internal RX clock delay */
40 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
41 val |= MII_BCM54XX_AUXCTL_MISC_WREN;
42 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
43 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
44 /* Disable RGMII RXC-RXD skew */
45 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
46 }
47 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
48 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
49 /* Enable RGMII RXC-RXD skew */
50 val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
51 }
52 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
53 val);
54 if (rc < 0)
55 return rc;
56
57 /* handling PHY's internal TX clock delay */
58 val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
59 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
60 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
61 /* Disable internal TX clock delay */
62 val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
63 }
64 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
65 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
66 /* Enable internal TX clock delay */
67 val |= BCM54810_SHD_CLK_CTL_GTXCLK_EN;
68 }
69 rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
70 if (rc < 0)
71 return rc;
72
73 return 0;
74}
75
76static int bcm54210e_config_init(struct phy_device *phydev)
77{
78 int val;
79
80 bcm54xx_config_clock_delay(phydev);
81
82 if (phydev->dev_flags & PHY_BRCM_EN_MASTER_MODE) {
83 val = phy_read(phydev, MII_CTRL1000);
84 val |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
85 phy_write(phydev, MII_CTRL1000, val);
86 }
87
88 return 0;
89}
90
91static int bcm54612e_config_init(struct phy_device *phydev)
92{
93 int reg;
94
95 bcm54xx_config_clock_delay(phydev);
96
97 /* Enable CLK125 MUX on LED4 if ref clock is enabled. */
98 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {
99 int err;
100
101 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0);
102 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0,
103 BCM54612E_LED4_CLK125OUT_EN | reg);
104
105 if (err < 0)
106 return err;
107 }
108
109 return 0;
110}
111
112static int bcm54616s_config_init(struct phy_device *phydev)
113{
114 int rc, val;
115
116 if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
117 phydev->interface != PHY_INTERFACE_MODE_1000BASEX)
118 return 0;
119
120 /* Ensure proper interface mode is selected. */
121 /* Disable RGMII mode */
122 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
123 if (val < 0)
124 return val;
125 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN;
126 val |= MII_BCM54XX_AUXCTL_MISC_WREN;
127 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
128 val);
129 if (rc < 0)
130 return rc;
131
132 /* Select 1000BASE-X register set (primary SerDes) */
133 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
134 if (val < 0)
135 return val;
136 val |= BCM54XX_SHD_MODE_1000BX;
137 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
138 if (rc < 0)
139 return rc;
140
141 /* Power down SerDes interface */
142 rc = phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN);
143 if (rc < 0)
144 return rc;
145
146 /* Select proper interface mode */
147 val &= ~BCM54XX_SHD_INTF_SEL_MASK;
148 val |= phydev->interface == PHY_INTERFACE_MODE_SGMII ?
149 BCM54XX_SHD_INTF_SEL_SGMII :
150 BCM54XX_SHD_INTF_SEL_GBIC;
151 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
152 if (rc < 0)
153 return rc;
154
155 /* Power up SerDes interface */
156 rc = phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
157 if (rc < 0)
158 return rc;
159
160 /* Select copper register set */
161 val &= ~BCM54XX_SHD_MODE_1000BX;
162 rc = bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE, val);
163 if (rc < 0)
164 return rc;
165
166 /* Power up copper interface */
167 return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN);
168}
169
170/* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
171static int bcm50610_a0_workaround(struct phy_device *phydev)
172{
173 int err;
174
175 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH0,
176 MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN |
177 MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF);
178 if (err < 0)
179 return err;
180
181 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH3,
182 MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ);
183 if (err < 0)
184 return err;
185
186 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75,
187 MII_BCM54XX_EXP_EXP75_VDACCTRL);
188 if (err < 0)
189 return err;
190
191 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP96,
192 MII_BCM54XX_EXP_EXP96_MYST);
193 if (err < 0)
194 return err;
195
196 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP97,
197 MII_BCM54XX_EXP_EXP97_MYST);
198
199 return err;
200}
201
202static int bcm54xx_phydsp_config(struct phy_device *phydev)
203{
204 int err, err2;
205
206 /* Enable the SMDSP clock */
207 err = bcm54xx_auxctl_write(phydev,
208 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
209 MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA |
210 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
211 if (err < 0)
212 return err;
213
214 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
215 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) {
216 /* Clear bit 9 to fix a phy interop issue. */
217 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08,
218 MII_BCM54XX_EXP_EXP08_RJCT_2MHZ);
219 if (err < 0)
220 goto error;
221
222 if (phydev->drv->phy_id == PHY_ID_BCM50610) {
223 err = bcm50610_a0_workaround(phydev);
224 if (err < 0)
225 goto error;
226 }
227 }
228
229 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
230 int val;
231
232 val = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP75);
233 if (val < 0)
234 goto error;
235
236 val |= MII_BCM54XX_EXP_EXP75_CM_OSC;
237 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, val);
238 }
239
240error:
241 /* Disable the SMDSP clock */
242 err2 = bcm54xx_auxctl_write(phydev,
243 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
244 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
245
246 /* Return the first error reported. */
247 return err ? err : err2;
248}
249
250static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
251{
252 u32 orig;
253 int val;
254 bool clk125en = true;
255
256 /* Abort if we are using an untested phy. */
257 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 &&
258 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 &&
259 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M &&
260 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54210E &&
261 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54810 &&
262 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811)
263 return;
264
265 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
266 if (val < 0)
267 return;
268
269 orig = val;
270
271 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
272 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
273 BRCM_PHY_REV(phydev) >= 0x3) {
274 /*
275 * Here, bit 0 _disables_ CLK125 when set.
276 * This bit is set by default.
277 */
278 clk125en = false;
279 } else {
280 if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) {
281 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM54811) {
282 /* Here, bit 0 _enables_ CLK125 when set */
283 val &= ~BCM54XX_SHD_SCR3_DEF_CLK125;
284 }
285 clk125en = false;
286 }
287 }
288
289 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
290 val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS;
291 else
292 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
293
294 if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) {
295 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E ||
296 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810 ||
297 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54811)
298 val |= BCM54XX_SHD_SCR3_RXCTXC_DIS;
299 else
300 val |= BCM54XX_SHD_SCR3_TRDDAPD;
301 }
302
303 if (orig != val)
304 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
305
306 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);
307 if (val < 0)
308 return;
309
310 orig = val;
311
312 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
313 val |= BCM54XX_SHD_APD_EN;
314 else
315 val &= ~BCM54XX_SHD_APD_EN;
316
317 if (orig != val)
318 bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);
319}
320
321static void bcm54xx_ptp_stop(struct phy_device *phydev)
322{
323 struct bcm54xx_phy_priv *priv = phydev->priv;
324
325 if (priv->ptp)
326 bcm_ptp_stop(priv->ptp);
327}
328
329static void bcm54xx_ptp_config_init(struct phy_device *phydev)
330{
331 struct bcm54xx_phy_priv *priv = phydev->priv;
332
333 if (priv->ptp)
334 bcm_ptp_config_init(phydev);
335}
336
337static int bcm54xx_config_init(struct phy_device *phydev)
338{
339 int reg, err, val;
340
341 reg = phy_read(phydev, MII_BCM54XX_ECR);
342 if (reg < 0)
343 return reg;
344
345 /* Mask interrupts globally. */
346 reg |= MII_BCM54XX_ECR_IM;
347 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
348 if (err < 0)
349 return err;
350
351 /* Unmask events we are interested in. */
352 reg = ~(MII_BCM54XX_INT_DUPLEX |
353 MII_BCM54XX_INT_SPEED |
354 MII_BCM54XX_INT_LINK);
355 err = phy_write(phydev, MII_BCM54XX_IMR, reg);
356 if (err < 0)
357 return err;
358
359 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
360 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
361 (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
362 bcm_phy_write_shadow(phydev, BCM54XX_SHD_RGMII_MODE, 0);
363
364 bcm54xx_adjust_rxrefclk(phydev);
365
366 switch (BRCM_PHY_MODEL(phydev)) {
367 case PHY_ID_BCM50610:
368 case PHY_ID_BCM50610M:
369 err = bcm54xx_config_clock_delay(phydev);
370 break;
371 case PHY_ID_BCM54210E:
372 err = bcm54210e_config_init(phydev);
373 break;
374 case PHY_ID_BCM54612E:
375 err = bcm54612e_config_init(phydev);
376 break;
377 case PHY_ID_BCM54616S:
378 err = bcm54616s_config_init(phydev);
379 break;
380 case PHY_ID_BCM54810:
381 /* For BCM54810, we need to disable BroadR-Reach function */
382 val = bcm_phy_read_exp(phydev,
383 BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
384 val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
385 err = bcm_phy_write_exp(phydev,
386 BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
387 val);
388 break;
389 }
390 if (err)
391 return err;
392
393 bcm54xx_phydsp_config(phydev);
394
395 /* For non-SFP setups, encode link speed into LED1 and LED3 pair
396 * (green/amber).
397 * Also flash these two LEDs on activity. This means configuring
398 * them for MULTICOLOR and encoding link/activity into them.
399 * Don't do this for devices on an SFP module, since some of these
400 * use the LED outputs to control the SFP LOS signal, and changing
401 * these settings will cause LOS to malfunction.
402 */
403 if (!phy_on_sfp(phydev)) {
404 val = BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_MULTICOLOR1) |
405 BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_MULTICOLOR1);
406 bcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1, val);
407
408 val = BCM_LED_MULTICOLOR_IN_PHASE |
409 BCM5482_SHD_LEDS1_LED1(BCM_LED_MULTICOLOR_LINK_ACT) |
410 BCM5482_SHD_LEDS1_LED3(BCM_LED_MULTICOLOR_LINK_ACT);
411 bcm_phy_write_exp(phydev, BCM_EXP_MULTICOLOR, val);
412 }
413
414 bcm54xx_ptp_config_init(phydev);
415
416 return 0;
417}
418
419static int bcm54xx_iddq_set(struct phy_device *phydev, bool enable)
420{
421 int ret = 0;
422
423 if (!(phydev->dev_flags & PHY_BRCM_IDDQ_SUSPEND))
424 return ret;
425
426 ret = bcm_phy_read_exp(phydev, BCM54XX_TOP_MISC_IDDQ_CTRL);
427 if (ret < 0)
428 goto out;
429
430 if (enable)
431 ret |= BCM54XX_TOP_MISC_IDDQ_SR | BCM54XX_TOP_MISC_IDDQ_LP;
432 else
433 ret &= ~(BCM54XX_TOP_MISC_IDDQ_SR | BCM54XX_TOP_MISC_IDDQ_LP);
434
435 ret = bcm_phy_write_exp(phydev, BCM54XX_TOP_MISC_IDDQ_CTRL, ret);
436out:
437 return ret;
438}
439
440static int bcm54xx_suspend(struct phy_device *phydev)
441{
442 int ret;
443
444 bcm54xx_ptp_stop(phydev);
445
446 /* We cannot use a read/modify/write here otherwise the PHY gets into
447 * a bad state where its LEDs keep flashing, thus defeating the purpose
448 * of low power mode.
449 */
450 ret = phy_write(phydev, MII_BMCR, BMCR_PDOWN);
451 if (ret < 0)
452 return ret;
453
454 return bcm54xx_iddq_set(phydev, true);
455}
456
457static int bcm54xx_resume(struct phy_device *phydev)
458{
459 int ret;
460
461 ret = bcm54xx_iddq_set(phydev, false);
462 if (ret < 0)
463 return ret;
464
465 /* Writes to register other than BMCR would be ignored
466 * unless we clear the PDOWN bit first
467 */
468 ret = genphy_resume(phydev);
469 if (ret < 0)
470 return ret;
471
472 /* Upon exiting power down, the PHY remains in an internal reset state
473 * for 40us
474 */
475 fsleep(40);
476
477 /* Issue a soft reset after clearing the power down bit
478 * and before doing any other configuration.
479 */
480 if (phydev->dev_flags & PHY_BRCM_IDDQ_SUSPEND) {
481 ret = genphy_soft_reset(phydev);
482 if (ret < 0)
483 return ret;
484 }
485
486 return bcm54xx_config_init(phydev);
487}
488
489static int bcm54811_config_init(struct phy_device *phydev)
490{
491 int err, reg;
492
493 /* Disable BroadR-Reach function. */
494 reg = bcm_phy_read_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
495 reg &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
496 err = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
497 reg);
498 if (err < 0)
499 return err;
500
501 err = bcm54xx_config_init(phydev);
502
503 /* Enable CLK125 MUX on LED4 if ref clock is enabled. */
504 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {
505 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0);
506 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0,
507 BCM54612E_LED4_CLK125OUT_EN | reg);
508 if (err < 0)
509 return err;
510 }
511
512 return err;
513}
514
515static int bcm5481_config_aneg(struct phy_device *phydev)
516{
517 struct device_node *np = phydev->mdio.dev.of_node;
518 int ret;
519
520 /* Aneg firstly. */
521 ret = genphy_config_aneg(phydev);
522
523 /* Then we can set up the delay. */
524 bcm54xx_config_clock_delay(phydev);
525
526 if (of_property_read_bool(np, "enet-phy-lane-swap")) {
527 /* Lane Swap - Undocumented register...magic! */
528 ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
529 0x11B);
530 if (ret < 0)
531 return ret;
532 }
533
534 return ret;
535}
536
537struct bcm54616s_phy_priv {
538 bool mode_1000bx_en;
539};
540
541static int bcm54616s_probe(struct phy_device *phydev)
542{
543 struct bcm54616s_phy_priv *priv;
544 int val;
545
546 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
547 if (!priv)
548 return -ENOMEM;
549
550 phydev->priv = priv;
551
552 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
553 if (val < 0)
554 return val;
555
556 /* The PHY is strapped in RGMII-fiber mode when INTERF_SEL[1:0]
557 * is 01b, and the link between PHY and its link partner can be
558 * either 1000Base-X or 100Base-FX.
559 * RGMII-1000Base-X is properly supported, but RGMII-100Base-FX
560 * support is still missing as of now.
561 */
562 if ((val & BCM54XX_SHD_INTF_SEL_MASK) == BCM54XX_SHD_INTF_SEL_RGMII) {
563 val = bcm_phy_read_shadow(phydev, BCM54616S_SHD_100FX_CTRL);
564 if (val < 0)
565 return val;
566
567 /* Bit 0 of the SerDes 100-FX Control register, when set
568 * to 1, sets the MII/RGMII -> 100BASE-FX configuration.
569 * When this bit is set to 0, it sets the GMII/RGMII ->
570 * 1000BASE-X configuration.
571 */
572 if (!(val & BCM54616S_100FX_MODE))
573 priv->mode_1000bx_en = true;
574
575 phydev->port = PORT_FIBRE;
576 }
577
578 return 0;
579}
580
581static int bcm54616s_config_aneg(struct phy_device *phydev)
582{
583 struct bcm54616s_phy_priv *priv = phydev->priv;
584 int ret;
585
586 /* Aneg firstly. */
587 if (priv->mode_1000bx_en)
588 ret = genphy_c37_config_aneg(phydev);
589 else
590 ret = genphy_config_aneg(phydev);
591
592 /* Then we can set up the delay. */
593 bcm54xx_config_clock_delay(phydev);
594
595 return ret;
596}
597
598static int bcm54616s_read_status(struct phy_device *phydev)
599{
600 struct bcm54616s_phy_priv *priv = phydev->priv;
601 int err;
602
603 if (priv->mode_1000bx_en)
604 err = genphy_c37_read_status(phydev);
605 else
606 err = genphy_read_status(phydev);
607
608 return err;
609}
610
611static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
612{
613 int val;
614
615 val = phy_read(phydev, reg);
616 if (val < 0)
617 return val;
618
619 return phy_write(phydev, reg, val | set);
620}
621
622static int brcm_fet_config_init(struct phy_device *phydev)
623{
624 int reg, err, err2, brcmtest;
625
626 /* Reset the PHY to bring it to a known state. */
627 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
628 if (err < 0)
629 return err;
630
631 /* The datasheet indicates the PHY needs up to 1us to complete a reset,
632 * build some slack here.
633 */
634 usleep_range(1000, 2000);
635
636 /* The PHY requires 65 MDC clock cycles to complete a write operation
637 * and turnaround the line properly.
638 *
639 * We ignore -EIO here as the MDIO controller (e.g.: mdio-bcm-unimac)
640 * may flag the lack of turn-around as a read failure. This is
641 * particularly true with this combination since the MDIO controller
642 * only used 64 MDC cycles. This is not a critical failure in this
643 * specific case and it has no functional impact otherwise, so we let
644 * that one go through. If there is a genuine bus error, the next read
645 * of MII_BRCM_FET_INTREG will error out.
646 */
647 err = phy_read(phydev, MII_BMCR);
648 if (err < 0 && err != -EIO)
649 return err;
650
651 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
652 if (reg < 0)
653 return reg;
654
655 /* Unmask events we are interested in and mask interrupts globally. */
656 reg = MII_BRCM_FET_IR_DUPLEX_EN |
657 MII_BRCM_FET_IR_SPEED_EN |
658 MII_BRCM_FET_IR_LINK_EN |
659 MII_BRCM_FET_IR_ENABLE |
660 MII_BRCM_FET_IR_MASK;
661
662 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
663 if (err < 0)
664 return err;
665
666 /* Enable shadow register access */
667 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
668 if (brcmtest < 0)
669 return brcmtest;
670
671 reg = brcmtest | MII_BRCM_FET_BT_SRE;
672
673 err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
674 if (err < 0)
675 return err;
676
677 /* Set the LED mode */
678 reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);
679 if (reg < 0) {
680 err = reg;
681 goto done;
682 }
683
684 reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK;
685 reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1;
686
687 err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);
688 if (err < 0)
689 goto done;
690
691 /* Enable auto MDIX */
692 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,
693 MII_BRCM_FET_SHDW_MC_FAME);
694 if (err < 0)
695 goto done;
696
697 if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) {
698 /* Enable auto power down */
699 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
700 MII_BRCM_FET_SHDW_AS2_APDE);
701 }
702
703done:
704 /* Disable shadow register access */
705 err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
706 if (!err)
707 err = err2;
708
709 return err;
710}
711
712static int brcm_fet_ack_interrupt(struct phy_device *phydev)
713{
714 int reg;
715
716 /* Clear pending interrupts. */
717 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
718 if (reg < 0)
719 return reg;
720
721 return 0;
722}
723
724static int brcm_fet_config_intr(struct phy_device *phydev)
725{
726 int reg, err;
727
728 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
729 if (reg < 0)
730 return reg;
731
732 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
733 err = brcm_fet_ack_interrupt(phydev);
734 if (err)
735 return err;
736
737 reg &= ~MII_BRCM_FET_IR_MASK;
738 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
739 } else {
740 reg |= MII_BRCM_FET_IR_MASK;
741 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
742 if (err)
743 return err;
744
745 err = brcm_fet_ack_interrupt(phydev);
746 }
747
748 return err;
749}
750
751static irqreturn_t brcm_fet_handle_interrupt(struct phy_device *phydev)
752{
753 int irq_status;
754
755 irq_status = phy_read(phydev, MII_BRCM_FET_INTREG);
756 if (irq_status < 0) {
757 phy_error(phydev);
758 return IRQ_NONE;
759 }
760
761 if (irq_status == 0)
762 return IRQ_NONE;
763
764 phy_trigger_machine(phydev);
765
766 return IRQ_HANDLED;
767}
768
769static int brcm_fet_suspend(struct phy_device *phydev)
770{
771 int reg, err, err2, brcmtest;
772
773 /* We cannot use a read/modify/write here otherwise the PHY continues
774 * to drive LEDs which defeats the purpose of low power mode.
775 */
776 err = phy_write(phydev, MII_BMCR, BMCR_PDOWN);
777 if (err < 0)
778 return err;
779
780 /* Enable shadow register access */
781 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
782 if (brcmtest < 0)
783 return brcmtest;
784
785 reg = brcmtest | MII_BRCM_FET_BT_SRE;
786
787 err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
788 if (err < 0)
789 return err;
790
791 /* Set standby mode */
792 err = phy_modify(phydev, MII_BRCM_FET_SHDW_AUXMODE4,
793 MII_BRCM_FET_SHDW_AM4_STANDBY,
794 MII_BRCM_FET_SHDW_AM4_STANDBY);
795
796 /* Disable shadow register access */
797 err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
798 if (!err)
799 err = err2;
800
801 return err;
802}
803
804static int bcm54xx_phy_probe(struct phy_device *phydev)
805{
806 struct bcm54xx_phy_priv *priv;
807
808 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
809 if (!priv)
810 return -ENOMEM;
811
812 phydev->priv = priv;
813
814 priv->stats = devm_kcalloc(&phydev->mdio.dev,
815 bcm_phy_get_sset_count(phydev), sizeof(u64),
816 GFP_KERNEL);
817 if (!priv->stats)
818 return -ENOMEM;
819
820 priv->ptp = bcm_ptp_probe(phydev);
821 if (IS_ERR(priv->ptp))
822 return PTR_ERR(priv->ptp);
823
824 return 0;
825}
826
827static void bcm54xx_get_stats(struct phy_device *phydev,
828 struct ethtool_stats *stats, u64 *data)
829{
830 struct bcm54xx_phy_priv *priv = phydev->priv;
831
832 bcm_phy_get_stats(phydev, priv->stats, stats, data);
833}
834
835static void bcm54xx_link_change_notify(struct phy_device *phydev)
836{
837 u16 mask = MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE |
838 MII_BCM54XX_EXP_EXP08_FORCE_DAC_WAKE;
839 int ret;
840
841 if (phydev->state != PHY_RUNNING)
842 return;
843
844 /* Don't change the DAC wake settings if auto power down
845 * is not requested.
846 */
847 if (!(phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
848 return;
849
850 ret = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP08);
851 if (ret < 0)
852 return;
853
854 /* Enable/disable 10BaseT auto and forced early DAC wake depending
855 * on the negotiated speed, those settings should only be done
856 * for 10Mbits/sec.
857 */
858 if (phydev->speed == SPEED_10)
859 ret |= mask;
860 else
861 ret &= ~mask;
862 bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08, ret);
863}
864
865static struct phy_driver broadcom_drivers[] = {
866{
867 .phy_id = PHY_ID_BCM5411,
868 .phy_id_mask = 0xfffffff0,
869 .name = "Broadcom BCM5411",
870 /* PHY_GBIT_FEATURES */
871 .get_sset_count = bcm_phy_get_sset_count,
872 .get_strings = bcm_phy_get_strings,
873 .get_stats = bcm54xx_get_stats,
874 .probe = bcm54xx_phy_probe,
875 .config_init = bcm54xx_config_init,
876 .config_intr = bcm_phy_config_intr,
877 .handle_interrupt = bcm_phy_handle_interrupt,
878 .link_change_notify = bcm54xx_link_change_notify,
879}, {
880 .phy_id = PHY_ID_BCM5421,
881 .phy_id_mask = 0xfffffff0,
882 .name = "Broadcom BCM5421",
883 /* PHY_GBIT_FEATURES */
884 .get_sset_count = bcm_phy_get_sset_count,
885 .get_strings = bcm_phy_get_strings,
886 .get_stats = bcm54xx_get_stats,
887 .probe = bcm54xx_phy_probe,
888 .config_init = bcm54xx_config_init,
889 .config_intr = bcm_phy_config_intr,
890 .handle_interrupt = bcm_phy_handle_interrupt,
891 .link_change_notify = bcm54xx_link_change_notify,
892}, {
893 .phy_id = PHY_ID_BCM54210E,
894 .phy_id_mask = 0xfffffff0,
895 .name = "Broadcom BCM54210E",
896 /* PHY_GBIT_FEATURES */
897 .get_sset_count = bcm_phy_get_sset_count,
898 .get_strings = bcm_phy_get_strings,
899 .get_stats = bcm54xx_get_stats,
900 .probe = bcm54xx_phy_probe,
901 .config_init = bcm54xx_config_init,
902 .config_intr = bcm_phy_config_intr,
903 .handle_interrupt = bcm_phy_handle_interrupt,
904 .link_change_notify = bcm54xx_link_change_notify,
905 .suspend = bcm54xx_suspend,
906 .resume = bcm54xx_resume,
907}, {
908 .phy_id = PHY_ID_BCM5461,
909 .phy_id_mask = 0xfffffff0,
910 .name = "Broadcom BCM5461",
911 /* PHY_GBIT_FEATURES */
912 .get_sset_count = bcm_phy_get_sset_count,
913 .get_strings = bcm_phy_get_strings,
914 .get_stats = bcm54xx_get_stats,
915 .probe = bcm54xx_phy_probe,
916 .config_init = bcm54xx_config_init,
917 .config_intr = bcm_phy_config_intr,
918 .handle_interrupt = bcm_phy_handle_interrupt,
919 .link_change_notify = bcm54xx_link_change_notify,
920}, {
921 .phy_id = PHY_ID_BCM54612E,
922 .phy_id_mask = 0xfffffff0,
923 .name = "Broadcom BCM54612E",
924 /* PHY_GBIT_FEATURES */
925 .get_sset_count = bcm_phy_get_sset_count,
926 .get_strings = bcm_phy_get_strings,
927 .get_stats = bcm54xx_get_stats,
928 .probe = bcm54xx_phy_probe,
929 .config_init = bcm54xx_config_init,
930 .config_intr = bcm_phy_config_intr,
931 .handle_interrupt = bcm_phy_handle_interrupt,
932 .link_change_notify = bcm54xx_link_change_notify,
933}, {
934 .phy_id = PHY_ID_BCM54616S,
935 .phy_id_mask = 0xfffffff0,
936 .name = "Broadcom BCM54616S",
937 /* PHY_GBIT_FEATURES */
938 .soft_reset = genphy_soft_reset,
939 .config_init = bcm54xx_config_init,
940 .config_aneg = bcm54616s_config_aneg,
941 .config_intr = bcm_phy_config_intr,
942 .handle_interrupt = bcm_phy_handle_interrupt,
943 .read_status = bcm54616s_read_status,
944 .probe = bcm54616s_probe,
945 .link_change_notify = bcm54xx_link_change_notify,
946}, {
947 .phy_id = PHY_ID_BCM5464,
948 .phy_id_mask = 0xfffffff0,
949 .name = "Broadcom BCM5464",
950 /* PHY_GBIT_FEATURES */
951 .get_sset_count = bcm_phy_get_sset_count,
952 .get_strings = bcm_phy_get_strings,
953 .get_stats = bcm54xx_get_stats,
954 .probe = bcm54xx_phy_probe,
955 .config_init = bcm54xx_config_init,
956 .config_intr = bcm_phy_config_intr,
957 .handle_interrupt = bcm_phy_handle_interrupt,
958 .suspend = genphy_suspend,
959 .resume = genphy_resume,
960 .link_change_notify = bcm54xx_link_change_notify,
961}, {
962 .phy_id = PHY_ID_BCM5481,
963 .phy_id_mask = 0xfffffff0,
964 .name = "Broadcom BCM5481",
965 /* PHY_GBIT_FEATURES */
966 .get_sset_count = bcm_phy_get_sset_count,
967 .get_strings = bcm_phy_get_strings,
968 .get_stats = bcm54xx_get_stats,
969 .probe = bcm54xx_phy_probe,
970 .config_init = bcm54xx_config_init,
971 .config_aneg = bcm5481_config_aneg,
972 .config_intr = bcm_phy_config_intr,
973 .handle_interrupt = bcm_phy_handle_interrupt,
974 .link_change_notify = bcm54xx_link_change_notify,
975}, {
976 .phy_id = PHY_ID_BCM54810,
977 .phy_id_mask = 0xfffffff0,
978 .name = "Broadcom BCM54810",
979 /* PHY_GBIT_FEATURES */
980 .get_sset_count = bcm_phy_get_sset_count,
981 .get_strings = bcm_phy_get_strings,
982 .get_stats = bcm54xx_get_stats,
983 .probe = bcm54xx_phy_probe,
984 .config_init = bcm54xx_config_init,
985 .config_aneg = bcm5481_config_aneg,
986 .config_intr = bcm_phy_config_intr,
987 .handle_interrupt = bcm_phy_handle_interrupt,
988 .suspend = bcm54xx_suspend,
989 .resume = bcm54xx_resume,
990 .link_change_notify = bcm54xx_link_change_notify,
991}, {
992 .phy_id = PHY_ID_BCM54811,
993 .phy_id_mask = 0xfffffff0,
994 .name = "Broadcom BCM54811",
995 /* PHY_GBIT_FEATURES */
996 .get_sset_count = bcm_phy_get_sset_count,
997 .get_strings = bcm_phy_get_strings,
998 .get_stats = bcm54xx_get_stats,
999 .probe = bcm54xx_phy_probe,
1000 .config_init = bcm54811_config_init,
1001 .config_aneg = bcm5481_config_aneg,
1002 .config_intr = bcm_phy_config_intr,
1003 .handle_interrupt = bcm_phy_handle_interrupt,
1004 .suspend = bcm54xx_suspend,
1005 .resume = bcm54xx_resume,
1006 .link_change_notify = bcm54xx_link_change_notify,
1007}, {
1008 .phy_id = PHY_ID_BCM5482,
1009 .phy_id_mask = 0xfffffff0,
1010 .name = "Broadcom BCM5482",
1011 /* PHY_GBIT_FEATURES */
1012 .get_sset_count = bcm_phy_get_sset_count,
1013 .get_strings = bcm_phy_get_strings,
1014 .get_stats = bcm54xx_get_stats,
1015 .probe = bcm54xx_phy_probe,
1016 .config_init = bcm54xx_config_init,
1017 .config_intr = bcm_phy_config_intr,
1018 .handle_interrupt = bcm_phy_handle_interrupt,
1019 .link_change_notify = bcm54xx_link_change_notify,
1020}, {
1021 .phy_id = PHY_ID_BCM50610,
1022 .phy_id_mask = 0xfffffff0,
1023 .name = "Broadcom BCM50610",
1024 /* PHY_GBIT_FEATURES */
1025 .get_sset_count = bcm_phy_get_sset_count,
1026 .get_strings = bcm_phy_get_strings,
1027 .get_stats = bcm54xx_get_stats,
1028 .probe = bcm54xx_phy_probe,
1029 .config_init = bcm54xx_config_init,
1030 .config_intr = bcm_phy_config_intr,
1031 .handle_interrupt = bcm_phy_handle_interrupt,
1032 .link_change_notify = bcm54xx_link_change_notify,
1033 .suspend = bcm54xx_suspend,
1034 .resume = bcm54xx_resume,
1035}, {
1036 .phy_id = PHY_ID_BCM50610M,
1037 .phy_id_mask = 0xfffffff0,
1038 .name = "Broadcom BCM50610M",
1039 /* PHY_GBIT_FEATURES */
1040 .get_sset_count = bcm_phy_get_sset_count,
1041 .get_strings = bcm_phy_get_strings,
1042 .get_stats = bcm54xx_get_stats,
1043 .probe = bcm54xx_phy_probe,
1044 .config_init = bcm54xx_config_init,
1045 .config_intr = bcm_phy_config_intr,
1046 .handle_interrupt = bcm_phy_handle_interrupt,
1047 .link_change_notify = bcm54xx_link_change_notify,
1048 .suspend = bcm54xx_suspend,
1049 .resume = bcm54xx_resume,
1050}, {
1051 .phy_id = PHY_ID_BCM57780,
1052 .phy_id_mask = 0xfffffff0,
1053 .name = "Broadcom BCM57780",
1054 /* PHY_GBIT_FEATURES */
1055 .get_sset_count = bcm_phy_get_sset_count,
1056 .get_strings = bcm_phy_get_strings,
1057 .get_stats = bcm54xx_get_stats,
1058 .probe = bcm54xx_phy_probe,
1059 .config_init = bcm54xx_config_init,
1060 .config_intr = bcm_phy_config_intr,
1061 .handle_interrupt = bcm_phy_handle_interrupt,
1062 .link_change_notify = bcm54xx_link_change_notify,
1063}, {
1064 .phy_id = PHY_ID_BCMAC131,
1065 .phy_id_mask = 0xfffffff0,
1066 .name = "Broadcom BCMAC131",
1067 /* PHY_BASIC_FEATURES */
1068 .config_init = brcm_fet_config_init,
1069 .config_intr = brcm_fet_config_intr,
1070 .handle_interrupt = brcm_fet_handle_interrupt,
1071 .suspend = brcm_fet_suspend,
1072 .resume = brcm_fet_config_init,
1073}, {
1074 .phy_id = PHY_ID_BCM5241,
1075 .phy_id_mask = 0xfffffff0,
1076 .name = "Broadcom BCM5241",
1077 /* PHY_BASIC_FEATURES */
1078 .config_init = brcm_fet_config_init,
1079 .config_intr = brcm_fet_config_intr,
1080 .handle_interrupt = brcm_fet_handle_interrupt,
1081 .suspend = brcm_fet_suspend,
1082 .resume = brcm_fet_config_init,
1083}, {
1084 .phy_id = PHY_ID_BCM5395,
1085 .phy_id_mask = 0xfffffff0,
1086 .name = "Broadcom BCM5395",
1087 .flags = PHY_IS_INTERNAL,
1088 /* PHY_GBIT_FEATURES */
1089 .get_sset_count = bcm_phy_get_sset_count,
1090 .get_strings = bcm_phy_get_strings,
1091 .get_stats = bcm54xx_get_stats,
1092 .probe = bcm54xx_phy_probe,
1093 .link_change_notify = bcm54xx_link_change_notify,
1094}, {
1095 .phy_id = PHY_ID_BCM53125,
1096 .phy_id_mask = 0xfffffff0,
1097 .name = "Broadcom BCM53125",
1098 .flags = PHY_IS_INTERNAL,
1099 /* PHY_GBIT_FEATURES */
1100 .get_sset_count = bcm_phy_get_sset_count,
1101 .get_strings = bcm_phy_get_strings,
1102 .get_stats = bcm54xx_get_stats,
1103 .probe = bcm54xx_phy_probe,
1104 .config_init = bcm54xx_config_init,
1105 .config_intr = bcm_phy_config_intr,
1106 .handle_interrupt = bcm_phy_handle_interrupt,
1107 .link_change_notify = bcm54xx_link_change_notify,
1108}, {
1109 .phy_id = PHY_ID_BCM53128,
1110 .phy_id_mask = 0xfffffff0,
1111 .name = "Broadcom BCM53128",
1112 .flags = PHY_IS_INTERNAL,
1113 /* PHY_GBIT_FEATURES */
1114 .get_sset_count = bcm_phy_get_sset_count,
1115 .get_strings = bcm_phy_get_strings,
1116 .get_stats = bcm54xx_get_stats,
1117 .probe = bcm54xx_phy_probe,
1118 .config_init = bcm54xx_config_init,
1119 .config_intr = bcm_phy_config_intr,
1120 .handle_interrupt = bcm_phy_handle_interrupt,
1121 .link_change_notify = bcm54xx_link_change_notify,
1122}, {
1123 .phy_id = PHY_ID_BCM89610,
1124 .phy_id_mask = 0xfffffff0,
1125 .name = "Broadcom BCM89610",
1126 /* PHY_GBIT_FEATURES */
1127 .get_sset_count = bcm_phy_get_sset_count,
1128 .get_strings = bcm_phy_get_strings,
1129 .get_stats = bcm54xx_get_stats,
1130 .probe = bcm54xx_phy_probe,
1131 .config_init = bcm54xx_config_init,
1132 .config_intr = bcm_phy_config_intr,
1133 .handle_interrupt = bcm_phy_handle_interrupt,
1134 .link_change_notify = bcm54xx_link_change_notify,
1135} };
1136
1137module_phy_driver(broadcom_drivers);
1138
1139static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
1140 { PHY_ID_BCM5411, 0xfffffff0 },
1141 { PHY_ID_BCM5421, 0xfffffff0 },
1142 { PHY_ID_BCM54210E, 0xfffffff0 },
1143 { PHY_ID_BCM5461, 0xfffffff0 },
1144 { PHY_ID_BCM54612E, 0xfffffff0 },
1145 { PHY_ID_BCM54616S, 0xfffffff0 },
1146 { PHY_ID_BCM5464, 0xfffffff0 },
1147 { PHY_ID_BCM5481, 0xfffffff0 },
1148 { PHY_ID_BCM54810, 0xfffffff0 },
1149 { PHY_ID_BCM54811, 0xfffffff0 },
1150 { PHY_ID_BCM5482, 0xfffffff0 },
1151 { PHY_ID_BCM50610, 0xfffffff0 },
1152 { PHY_ID_BCM50610M, 0xfffffff0 },
1153 { PHY_ID_BCM57780, 0xfffffff0 },
1154 { PHY_ID_BCMAC131, 0xfffffff0 },
1155 { PHY_ID_BCM5241, 0xfffffff0 },
1156 { PHY_ID_BCM5395, 0xfffffff0 },
1157 { PHY_ID_BCM53125, 0xfffffff0 },
1158 { PHY_ID_BCM53128, 0xfffffff0 },
1159 { PHY_ID_BCM89610, 0xfffffff0 },
1160 { }
1161};
1162
1163MODULE_DEVICE_TABLE(mdio, broadcom_tbl);