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1/*
2 * drivers/net/phy/broadcom.c
3 *
4 * Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet
5 * transceivers.
6 *
7 * Copyright (c) 2006 Maciej W. Rozycki
8 *
9 * Inspired by code written by Amy Fong.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 */
16
17#include "bcm-phy-lib.h"
18#include <linux/module.h>
19#include <linux/phy.h>
20#include <linux/brcmphy.h>
21#include <linux/of.h>
22
23#define BRCM_PHY_MODEL(phydev) \
24 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
25
26#define BRCM_PHY_REV(phydev) \
27 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
28
29MODULE_DESCRIPTION("Broadcom PHY driver");
30MODULE_AUTHOR("Maciej W. Rozycki");
31MODULE_LICENSE("GPL");
32
33static int bcm54210e_config_init(struct phy_device *phydev)
34{
35 int val;
36
37 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
38 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
39 val |= MII_BCM54XX_AUXCTL_MISC_WREN;
40 bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, val);
41
42 val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
43 val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
44 bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
45
46 if (phydev->dev_flags & PHY_BRCM_EN_MASTER_MODE) {
47 val = phy_read(phydev, MII_CTRL1000);
48 val |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
49 phy_write(phydev, MII_CTRL1000, val);
50 }
51
52 return 0;
53}
54
55static int bcm54612e_config_init(struct phy_device *phydev)
56{
57 /* Clear TX internal delay unless requested. */
58 if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
59 (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
60 /* Disable TXD to GTXCLK clock delay (default set) */
61 /* Bit 9 is the only field in shadow register 00011 */
62 bcm_phy_write_shadow(phydev, 0x03, 0);
63 }
64
65 /* Clear RX internal delay unless requested. */
66 if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
67 (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
68 u16 reg;
69
70 reg = bcm54xx_auxctl_read(phydev,
71 MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
72 /* Disable RXD to RXC delay (default set) */
73 reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
74 /* Clear shadow selector field */
75 reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
76 bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
77 MII_BCM54XX_AUXCTL_MISC_WREN | reg);
78 }
79
80 return 0;
81}
82
83static int bcm5481x_config(struct phy_device *phydev)
84{
85 int rc, val;
86
87 /* handling PHY's internal RX clock delay */
88 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
89 val |= MII_BCM54XX_AUXCTL_MISC_WREN;
90 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
91 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
92 /* Disable RGMII RXC-RXD skew */
93 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
94 }
95 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
96 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
97 /* Enable RGMII RXC-RXD skew */
98 val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
99 }
100 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
101 val);
102 if (rc < 0)
103 return rc;
104
105 /* handling PHY's internal TX clock delay */
106 val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
107 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
108 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
109 /* Disable internal TX clock delay */
110 val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
111 }
112 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
113 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
114 /* Enable internal TX clock delay */
115 val |= BCM54810_SHD_CLK_CTL_GTXCLK_EN;
116 }
117 rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
118 if (rc < 0)
119 return rc;
120
121 return 0;
122}
123
124/* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
125static int bcm50610_a0_workaround(struct phy_device *phydev)
126{
127 int err;
128
129 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH0,
130 MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN |
131 MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF);
132 if (err < 0)
133 return err;
134
135 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH3,
136 MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ);
137 if (err < 0)
138 return err;
139
140 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75,
141 MII_BCM54XX_EXP_EXP75_VDACCTRL);
142 if (err < 0)
143 return err;
144
145 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP96,
146 MII_BCM54XX_EXP_EXP96_MYST);
147 if (err < 0)
148 return err;
149
150 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP97,
151 MII_BCM54XX_EXP_EXP97_MYST);
152
153 return err;
154}
155
156static int bcm54xx_phydsp_config(struct phy_device *phydev)
157{
158 int err, err2;
159
160 /* Enable the SMDSP clock */
161 err = bcm54xx_auxctl_write(phydev,
162 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
163 MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA |
164 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
165 if (err < 0)
166 return err;
167
168 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
169 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) {
170 /* Clear bit 9 to fix a phy interop issue. */
171 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08,
172 MII_BCM54XX_EXP_EXP08_RJCT_2MHZ);
173 if (err < 0)
174 goto error;
175
176 if (phydev->drv->phy_id == PHY_ID_BCM50610) {
177 err = bcm50610_a0_workaround(phydev);
178 if (err < 0)
179 goto error;
180 }
181 }
182
183 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
184 int val;
185
186 val = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP75);
187 if (val < 0)
188 goto error;
189
190 val |= MII_BCM54XX_EXP_EXP75_CM_OSC;
191 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, val);
192 }
193
194error:
195 /* Disable the SMDSP clock */
196 err2 = bcm54xx_auxctl_write(phydev,
197 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
198 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
199
200 /* Return the first error reported. */
201 return err ? err : err2;
202}
203
204static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
205{
206 u32 orig;
207 int val;
208 bool clk125en = true;
209
210 /* Abort if we are using an untested phy. */
211 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 &&
212 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 &&
213 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M)
214 return;
215
216 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
217 if (val < 0)
218 return;
219
220 orig = val;
221
222 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
223 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
224 BRCM_PHY_REV(phydev) >= 0x3) {
225 /*
226 * Here, bit 0 _disables_ CLK125 when set.
227 * This bit is set by default.
228 */
229 clk125en = false;
230 } else {
231 if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) {
232 /* Here, bit 0 _enables_ CLK125 when set */
233 val &= ~BCM54XX_SHD_SCR3_DEF_CLK125;
234 clk125en = false;
235 }
236 }
237
238 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
239 val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS;
240 else
241 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
242
243 if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY)
244 val |= BCM54XX_SHD_SCR3_TRDDAPD;
245
246 if (orig != val)
247 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
248
249 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);
250 if (val < 0)
251 return;
252
253 orig = val;
254
255 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
256 val |= BCM54XX_SHD_APD_EN;
257 else
258 val &= ~BCM54XX_SHD_APD_EN;
259
260 if (orig != val)
261 bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);
262}
263
264static int bcm54xx_config_init(struct phy_device *phydev)
265{
266 int reg, err, val;
267
268 reg = phy_read(phydev, MII_BCM54XX_ECR);
269 if (reg < 0)
270 return reg;
271
272 /* Mask interrupts globally. */
273 reg |= MII_BCM54XX_ECR_IM;
274 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
275 if (err < 0)
276 return err;
277
278 /* Unmask events we are interested in. */
279 reg = ~(MII_BCM54XX_INT_DUPLEX |
280 MII_BCM54XX_INT_SPEED |
281 MII_BCM54XX_INT_LINK);
282 err = phy_write(phydev, MII_BCM54XX_IMR, reg);
283 if (err < 0)
284 return err;
285
286 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
287 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
288 (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
289 bcm_phy_write_shadow(phydev, BCM54XX_SHD_RGMII_MODE, 0);
290
291 if ((phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) ||
292 (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) ||
293 (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
294 bcm54xx_adjust_rxrefclk(phydev);
295
296 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E) {
297 err = bcm54210e_config_init(phydev);
298 if (err)
299 return err;
300 } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54612E) {
301 err = bcm54612e_config_init(phydev);
302 if (err)
303 return err;
304 } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
305 /* For BCM54810, we need to disable BroadR-Reach function */
306 val = bcm_phy_read_exp(phydev,
307 BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
308 val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
309 err = bcm_phy_write_exp(phydev,
310 BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
311 val);
312 if (err < 0)
313 return err;
314 }
315
316 bcm54xx_phydsp_config(phydev);
317
318 return 0;
319}
320
321static int bcm5482_config_init(struct phy_device *phydev)
322{
323 int err, reg;
324
325 err = bcm54xx_config_init(phydev);
326
327 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
328 /*
329 * Enable secondary SerDes and its use as an LED source
330 */
331 reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_SSD);
332 bcm_phy_write_shadow(phydev, BCM5482_SHD_SSD,
333 reg |
334 BCM5482_SHD_SSD_LEDM |
335 BCM5482_SHD_SSD_EN);
336
337 /*
338 * Enable SGMII slave mode and auto-detection
339 */
340 reg = BCM5482_SSD_SGMII_SLAVE | MII_BCM54XX_EXP_SEL_SSD;
341 err = bcm_phy_read_exp(phydev, reg);
342 if (err < 0)
343 return err;
344 err = bcm_phy_write_exp(phydev, reg, err |
345 BCM5482_SSD_SGMII_SLAVE_EN |
346 BCM5482_SSD_SGMII_SLAVE_AD);
347 if (err < 0)
348 return err;
349
350 /*
351 * Disable secondary SerDes powerdown
352 */
353 reg = BCM5482_SSD_1000BX_CTL | MII_BCM54XX_EXP_SEL_SSD;
354 err = bcm_phy_read_exp(phydev, reg);
355 if (err < 0)
356 return err;
357 err = bcm_phy_write_exp(phydev, reg,
358 err & ~BCM5482_SSD_1000BX_CTL_PWRDOWN);
359 if (err < 0)
360 return err;
361
362 /*
363 * Select 1000BASE-X register set (primary SerDes)
364 */
365 reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_MODE);
366 bcm_phy_write_shadow(phydev, BCM5482_SHD_MODE,
367 reg | BCM5482_SHD_MODE_1000BX);
368
369 /*
370 * LED1=ACTIVITYLED, LED3=LINKSPD[2]
371 * (Use LED1 as secondary SerDes ACTIVITY LED)
372 */
373 bcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1,
374 BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_ACTIVITYLED) |
375 BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_LINKSPD2));
376
377 /*
378 * Auto-negotiation doesn't seem to work quite right
379 * in this mode, so we disable it and force it to the
380 * right speed/duplex setting. Only 'link status'
381 * is important.
382 */
383 phydev->autoneg = AUTONEG_DISABLE;
384 phydev->speed = SPEED_1000;
385 phydev->duplex = DUPLEX_FULL;
386 }
387
388 return err;
389}
390
391static int bcm5482_read_status(struct phy_device *phydev)
392{
393 int err;
394
395 err = genphy_read_status(phydev);
396
397 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
398 /*
399 * Only link status matters for 1000Base-X mode, so force
400 * 1000 Mbit/s full-duplex status
401 */
402 if (phydev->link) {
403 phydev->speed = SPEED_1000;
404 phydev->duplex = DUPLEX_FULL;
405 }
406 }
407
408 return err;
409}
410
411static int bcm5481_config_aneg(struct phy_device *phydev)
412{
413 struct device_node *np = phydev->mdio.dev.of_node;
414 int ret;
415
416 /* Aneg firsly. */
417 ret = genphy_config_aneg(phydev);
418
419 /* Then we can set up the delay. */
420 bcm5481x_config(phydev);
421
422 if (of_property_read_bool(np, "enet-phy-lane-swap")) {
423 /* Lane Swap - Undocumented register...magic! */
424 ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
425 0x11B);
426 if (ret < 0)
427 return ret;
428 }
429
430 return ret;
431}
432
433static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
434{
435 int val;
436
437 val = phy_read(phydev, reg);
438 if (val < 0)
439 return val;
440
441 return phy_write(phydev, reg, val | set);
442}
443
444static int brcm_fet_config_init(struct phy_device *phydev)
445{
446 int reg, err, err2, brcmtest;
447
448 /* Reset the PHY to bring it to a known state. */
449 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
450 if (err < 0)
451 return err;
452
453 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
454 if (reg < 0)
455 return reg;
456
457 /* Unmask events we are interested in and mask interrupts globally. */
458 reg = MII_BRCM_FET_IR_DUPLEX_EN |
459 MII_BRCM_FET_IR_SPEED_EN |
460 MII_BRCM_FET_IR_LINK_EN |
461 MII_BRCM_FET_IR_ENABLE |
462 MII_BRCM_FET_IR_MASK;
463
464 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
465 if (err < 0)
466 return err;
467
468 /* Enable shadow register access */
469 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
470 if (brcmtest < 0)
471 return brcmtest;
472
473 reg = brcmtest | MII_BRCM_FET_BT_SRE;
474
475 err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
476 if (err < 0)
477 return err;
478
479 /* Set the LED mode */
480 reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);
481 if (reg < 0) {
482 err = reg;
483 goto done;
484 }
485
486 reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK;
487 reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1;
488
489 err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);
490 if (err < 0)
491 goto done;
492
493 /* Enable auto MDIX */
494 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,
495 MII_BRCM_FET_SHDW_MC_FAME);
496 if (err < 0)
497 goto done;
498
499 if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) {
500 /* Enable auto power down */
501 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
502 MII_BRCM_FET_SHDW_AS2_APDE);
503 }
504
505done:
506 /* Disable shadow register access */
507 err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
508 if (!err)
509 err = err2;
510
511 return err;
512}
513
514static int brcm_fet_ack_interrupt(struct phy_device *phydev)
515{
516 int reg;
517
518 /* Clear pending interrupts. */
519 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
520 if (reg < 0)
521 return reg;
522
523 return 0;
524}
525
526static int brcm_fet_config_intr(struct phy_device *phydev)
527{
528 int reg, err;
529
530 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
531 if (reg < 0)
532 return reg;
533
534 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
535 reg &= ~MII_BRCM_FET_IR_MASK;
536 else
537 reg |= MII_BRCM_FET_IR_MASK;
538
539 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
540 return err;
541}
542
543struct bcm53xx_phy_priv {
544 u64 *stats;
545};
546
547static int bcm53xx_phy_probe(struct phy_device *phydev)
548{
549 struct bcm53xx_phy_priv *priv;
550
551 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
552 if (!priv)
553 return -ENOMEM;
554
555 phydev->priv = priv;
556
557 priv->stats = devm_kcalloc(&phydev->mdio.dev,
558 bcm_phy_get_sset_count(phydev), sizeof(u64),
559 GFP_KERNEL);
560 if (!priv->stats)
561 return -ENOMEM;
562
563 return 0;
564}
565
566static void bcm53xx_phy_get_stats(struct phy_device *phydev,
567 struct ethtool_stats *stats, u64 *data)
568{
569 struct bcm53xx_phy_priv *priv = phydev->priv;
570
571 bcm_phy_get_stats(phydev, priv->stats, stats, data);
572}
573
574static struct phy_driver broadcom_drivers[] = {
575{
576 .phy_id = PHY_ID_BCM5411,
577 .phy_id_mask = 0xfffffff0,
578 .name = "Broadcom BCM5411",
579 .features = PHY_GBIT_FEATURES,
580 .flags = PHY_HAS_INTERRUPT,
581 .config_init = bcm54xx_config_init,
582 .ack_interrupt = bcm_phy_ack_intr,
583 .config_intr = bcm_phy_config_intr,
584}, {
585 .phy_id = PHY_ID_BCM5421,
586 .phy_id_mask = 0xfffffff0,
587 .name = "Broadcom BCM5421",
588 .features = PHY_GBIT_FEATURES,
589 .flags = PHY_HAS_INTERRUPT,
590 .config_init = bcm54xx_config_init,
591 .ack_interrupt = bcm_phy_ack_intr,
592 .config_intr = bcm_phy_config_intr,
593}, {
594 .phy_id = PHY_ID_BCM54210E,
595 .phy_id_mask = 0xfffffff0,
596 .name = "Broadcom BCM54210E",
597 .features = PHY_GBIT_FEATURES,
598 .flags = PHY_HAS_INTERRUPT,
599 .config_init = bcm54xx_config_init,
600 .ack_interrupt = bcm_phy_ack_intr,
601 .config_intr = bcm_phy_config_intr,
602}, {
603 .phy_id = PHY_ID_BCM5461,
604 .phy_id_mask = 0xfffffff0,
605 .name = "Broadcom BCM5461",
606 .features = PHY_GBIT_FEATURES,
607 .flags = PHY_HAS_INTERRUPT,
608 .config_init = bcm54xx_config_init,
609 .ack_interrupt = bcm_phy_ack_intr,
610 .config_intr = bcm_phy_config_intr,
611}, {
612 .phy_id = PHY_ID_BCM54612E,
613 .phy_id_mask = 0xfffffff0,
614 .name = "Broadcom BCM54612E",
615 .features = PHY_GBIT_FEATURES,
616 .flags = PHY_HAS_INTERRUPT,
617 .config_init = bcm54xx_config_init,
618 .ack_interrupt = bcm_phy_ack_intr,
619 .config_intr = bcm_phy_config_intr,
620}, {
621 .phy_id = PHY_ID_BCM54616S,
622 .phy_id_mask = 0xfffffff0,
623 .name = "Broadcom BCM54616S",
624 .features = PHY_GBIT_FEATURES,
625 .flags = PHY_HAS_INTERRUPT,
626 .config_init = bcm54xx_config_init,
627 .ack_interrupt = bcm_phy_ack_intr,
628 .config_intr = bcm_phy_config_intr,
629}, {
630 .phy_id = PHY_ID_BCM5464,
631 .phy_id_mask = 0xfffffff0,
632 .name = "Broadcom BCM5464",
633 .features = PHY_GBIT_FEATURES,
634 .flags = PHY_HAS_INTERRUPT,
635 .config_init = bcm54xx_config_init,
636 .ack_interrupt = bcm_phy_ack_intr,
637 .config_intr = bcm_phy_config_intr,
638}, {
639 .phy_id = PHY_ID_BCM5481,
640 .phy_id_mask = 0xfffffff0,
641 .name = "Broadcom BCM5481",
642 .features = PHY_GBIT_FEATURES,
643 .flags = PHY_HAS_INTERRUPT,
644 .config_init = bcm54xx_config_init,
645 .config_aneg = bcm5481_config_aneg,
646 .ack_interrupt = bcm_phy_ack_intr,
647 .config_intr = bcm_phy_config_intr,
648}, {
649 .phy_id = PHY_ID_BCM54810,
650 .phy_id_mask = 0xfffffff0,
651 .name = "Broadcom BCM54810",
652 .features = PHY_GBIT_FEATURES,
653 .flags = PHY_HAS_INTERRUPT,
654 .config_init = bcm54xx_config_init,
655 .config_aneg = bcm5481_config_aneg,
656 .ack_interrupt = bcm_phy_ack_intr,
657 .config_intr = bcm_phy_config_intr,
658}, {
659 .phy_id = PHY_ID_BCM5482,
660 .phy_id_mask = 0xfffffff0,
661 .name = "Broadcom BCM5482",
662 .features = PHY_GBIT_FEATURES,
663 .flags = PHY_HAS_INTERRUPT,
664 .config_init = bcm5482_config_init,
665 .read_status = bcm5482_read_status,
666 .ack_interrupt = bcm_phy_ack_intr,
667 .config_intr = bcm_phy_config_intr,
668}, {
669 .phy_id = PHY_ID_BCM50610,
670 .phy_id_mask = 0xfffffff0,
671 .name = "Broadcom BCM50610",
672 .features = PHY_GBIT_FEATURES,
673 .flags = PHY_HAS_INTERRUPT,
674 .config_init = bcm54xx_config_init,
675 .ack_interrupt = bcm_phy_ack_intr,
676 .config_intr = bcm_phy_config_intr,
677}, {
678 .phy_id = PHY_ID_BCM50610M,
679 .phy_id_mask = 0xfffffff0,
680 .name = "Broadcom BCM50610M",
681 .features = PHY_GBIT_FEATURES,
682 .flags = PHY_HAS_INTERRUPT,
683 .config_init = bcm54xx_config_init,
684 .ack_interrupt = bcm_phy_ack_intr,
685 .config_intr = bcm_phy_config_intr,
686}, {
687 .phy_id = PHY_ID_BCM57780,
688 .phy_id_mask = 0xfffffff0,
689 .name = "Broadcom BCM57780",
690 .features = PHY_GBIT_FEATURES,
691 .flags = PHY_HAS_INTERRUPT,
692 .config_init = bcm54xx_config_init,
693 .ack_interrupt = bcm_phy_ack_intr,
694 .config_intr = bcm_phy_config_intr,
695}, {
696 .phy_id = PHY_ID_BCMAC131,
697 .phy_id_mask = 0xfffffff0,
698 .name = "Broadcom BCMAC131",
699 .features = PHY_BASIC_FEATURES,
700 .flags = PHY_HAS_INTERRUPT,
701 .config_init = brcm_fet_config_init,
702 .ack_interrupt = brcm_fet_ack_interrupt,
703 .config_intr = brcm_fet_config_intr,
704}, {
705 .phy_id = PHY_ID_BCM5241,
706 .phy_id_mask = 0xfffffff0,
707 .name = "Broadcom BCM5241",
708 .features = PHY_BASIC_FEATURES,
709 .flags = PHY_HAS_INTERRUPT,
710 .config_init = brcm_fet_config_init,
711 .ack_interrupt = brcm_fet_ack_interrupt,
712 .config_intr = brcm_fet_config_intr,
713}, {
714 .phy_id = PHY_ID_BCM5395,
715 .phy_id_mask = 0xfffffff0,
716 .name = "Broadcom BCM5395",
717 .flags = PHY_IS_INTERNAL,
718 .features = PHY_GBIT_FEATURES,
719 .get_sset_count = bcm_phy_get_sset_count,
720 .get_strings = bcm_phy_get_strings,
721 .get_stats = bcm53xx_phy_get_stats,
722 .probe = bcm53xx_phy_probe,
723}, {
724 .phy_id = PHY_ID_BCM89610,
725 .phy_id_mask = 0xfffffff0,
726 .name = "Broadcom BCM89610",
727 .features = PHY_GBIT_FEATURES,
728 .flags = PHY_HAS_INTERRUPT,
729 .config_init = bcm54xx_config_init,
730 .ack_interrupt = bcm_phy_ack_intr,
731 .config_intr = bcm_phy_config_intr,
732} };
733
734module_phy_driver(broadcom_drivers);
735
736static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
737 { PHY_ID_BCM5411, 0xfffffff0 },
738 { PHY_ID_BCM5421, 0xfffffff0 },
739 { PHY_ID_BCM54210E, 0xfffffff0 },
740 { PHY_ID_BCM5461, 0xfffffff0 },
741 { PHY_ID_BCM54612E, 0xfffffff0 },
742 { PHY_ID_BCM54616S, 0xfffffff0 },
743 { PHY_ID_BCM5464, 0xfffffff0 },
744 { PHY_ID_BCM5481, 0xfffffff0 },
745 { PHY_ID_BCM54810, 0xfffffff0 },
746 { PHY_ID_BCM5482, 0xfffffff0 },
747 { PHY_ID_BCM50610, 0xfffffff0 },
748 { PHY_ID_BCM50610M, 0xfffffff0 },
749 { PHY_ID_BCM57780, 0xfffffff0 },
750 { PHY_ID_BCMAC131, 0xfffffff0 },
751 { PHY_ID_BCM5241, 0xfffffff0 },
752 { PHY_ID_BCM5395, 0xfffffff0 },
753 { PHY_ID_BCM89610, 0xfffffff0 },
754 { }
755};
756
757MODULE_DEVICE_TABLE(mdio, broadcom_tbl);
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/broadcom.c
4 *
5 * Broadcom BCM5411, BCM5421 and BCM5461 Gigabit Ethernet
6 * transceivers.
7 *
8 * Copyright (c) 2006 Maciej W. Rozycki
9 *
10 * Inspired by code written by Amy Fong.
11 */
12
13#include "bcm-phy-lib.h"
14#include <linux/module.h>
15#include <linux/phy.h>
16#include <linux/brcmphy.h>
17#include <linux/of.h>
18
19#define BRCM_PHY_MODEL(phydev) \
20 ((phydev)->drv->phy_id & (phydev)->drv->phy_id_mask)
21
22#define BRCM_PHY_REV(phydev) \
23 ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
24
25MODULE_DESCRIPTION("Broadcom PHY driver");
26MODULE_AUTHOR("Maciej W. Rozycki");
27MODULE_LICENSE("GPL");
28
29static int bcm54210e_config_init(struct phy_device *phydev)
30{
31 int val;
32
33 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
34 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
35 val |= MII_BCM54XX_AUXCTL_MISC_WREN;
36 bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC, val);
37
38 val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
39 val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
40 bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
41
42 if (phydev->dev_flags & PHY_BRCM_EN_MASTER_MODE) {
43 val = phy_read(phydev, MII_CTRL1000);
44 val |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
45 phy_write(phydev, MII_CTRL1000, val);
46 }
47
48 return 0;
49}
50
51static int bcm54612e_config_init(struct phy_device *phydev)
52{
53 int reg;
54
55 /* Clear TX internal delay unless requested. */
56 if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
57 (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)) {
58 /* Disable TXD to GTXCLK clock delay (default set) */
59 /* Bit 9 is the only field in shadow register 00011 */
60 bcm_phy_write_shadow(phydev, 0x03, 0);
61 }
62
63 /* Clear RX internal delay unless requested. */
64 if ((phydev->interface != PHY_INTERFACE_MODE_RGMII_ID) &&
65 (phydev->interface != PHY_INTERFACE_MODE_RGMII_RXID)) {
66 reg = bcm54xx_auxctl_read(phydev,
67 MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
68 /* Disable RXD to RXC delay (default set) */
69 reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
70 /* Clear shadow selector field */
71 reg &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MASK;
72 bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
73 MII_BCM54XX_AUXCTL_MISC_WREN | reg);
74 }
75
76 /* Enable CLK125 MUX on LED4 if ref clock is enabled. */
77 if (!(phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED)) {
78 int err;
79
80 reg = bcm_phy_read_exp(phydev, BCM54612E_EXP_SPARE0);
81 err = bcm_phy_write_exp(phydev, BCM54612E_EXP_SPARE0,
82 BCM54612E_LED4_CLK125OUT_EN | reg);
83
84 if (err < 0)
85 return err;
86 }
87
88 return 0;
89}
90
91static int bcm54xx_config_clock_delay(struct phy_device *phydev)
92{
93 int rc, val;
94
95 /* handling PHY's internal RX clock delay */
96 val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
97 val |= MII_BCM54XX_AUXCTL_MISC_WREN;
98 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
99 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
100 /* Disable RGMII RXC-RXD skew */
101 val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
102 }
103 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
104 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
105 /* Enable RGMII RXC-RXD skew */
106 val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN;
107 }
108 rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
109 val);
110 if (rc < 0)
111 return rc;
112
113 /* handling PHY's internal TX clock delay */
114 val = bcm_phy_read_shadow(phydev, BCM54810_SHD_CLK_CTL);
115 if (phydev->interface == PHY_INTERFACE_MODE_RGMII ||
116 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
117 /* Disable internal TX clock delay */
118 val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
119 }
120 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
121 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
122 /* Enable internal TX clock delay */
123 val |= BCM54810_SHD_CLK_CTL_GTXCLK_EN;
124 }
125 rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
126 if (rc < 0)
127 return rc;
128
129 return 0;
130}
131
132/* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
133static int bcm50610_a0_workaround(struct phy_device *phydev)
134{
135 int err;
136
137 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH0,
138 MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN |
139 MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF);
140 if (err < 0)
141 return err;
142
143 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_AADJ1CH3,
144 MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ);
145 if (err < 0)
146 return err;
147
148 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75,
149 MII_BCM54XX_EXP_EXP75_VDACCTRL);
150 if (err < 0)
151 return err;
152
153 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP96,
154 MII_BCM54XX_EXP_EXP96_MYST);
155 if (err < 0)
156 return err;
157
158 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP97,
159 MII_BCM54XX_EXP_EXP97_MYST);
160
161 return err;
162}
163
164static int bcm54xx_phydsp_config(struct phy_device *phydev)
165{
166 int err, err2;
167
168 /* Enable the SMDSP clock */
169 err = bcm54xx_auxctl_write(phydev,
170 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
171 MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA |
172 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
173 if (err < 0)
174 return err;
175
176 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
177 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) {
178 /* Clear bit 9 to fix a phy interop issue. */
179 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP08,
180 MII_BCM54XX_EXP_EXP08_RJCT_2MHZ);
181 if (err < 0)
182 goto error;
183
184 if (phydev->drv->phy_id == PHY_ID_BCM50610) {
185 err = bcm50610_a0_workaround(phydev);
186 if (err < 0)
187 goto error;
188 }
189 }
190
191 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM57780) {
192 int val;
193
194 val = bcm_phy_read_exp(phydev, MII_BCM54XX_EXP_EXP75);
195 if (val < 0)
196 goto error;
197
198 val |= MII_BCM54XX_EXP_EXP75_CM_OSC;
199 err = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_EXP75, val);
200 }
201
202error:
203 /* Disable the SMDSP clock */
204 err2 = bcm54xx_auxctl_write(phydev,
205 MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL,
206 MII_BCM54XX_AUXCTL_ACTL_TX_6DB);
207
208 /* Return the first error reported. */
209 return err ? err : err2;
210}
211
212static void bcm54xx_adjust_rxrefclk(struct phy_device *phydev)
213{
214 u32 orig;
215 int val;
216 bool clk125en = true;
217
218 /* Abort if we are using an untested phy. */
219 if (BRCM_PHY_MODEL(phydev) != PHY_ID_BCM57780 &&
220 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610 &&
221 BRCM_PHY_MODEL(phydev) != PHY_ID_BCM50610M)
222 return;
223
224 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
225 if (val < 0)
226 return;
227
228 orig = val;
229
230 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
231 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
232 BRCM_PHY_REV(phydev) >= 0x3) {
233 /*
234 * Here, bit 0 _disables_ CLK125 when set.
235 * This bit is set by default.
236 */
237 clk125en = false;
238 } else {
239 if (phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) {
240 /* Here, bit 0 _enables_ CLK125 when set */
241 val &= ~BCM54XX_SHD_SCR3_DEF_CLK125;
242 clk125en = false;
243 }
244 }
245
246 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
247 val &= ~BCM54XX_SHD_SCR3_DLLAPD_DIS;
248 else
249 val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
250
251 if (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY)
252 val |= BCM54XX_SHD_SCR3_TRDDAPD;
253
254 if (orig != val)
255 bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
256
257 val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);
258 if (val < 0)
259 return;
260
261 orig = val;
262
263 if (!clk125en || (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
264 val |= BCM54XX_SHD_APD_EN;
265 else
266 val &= ~BCM54XX_SHD_APD_EN;
267
268 if (orig != val)
269 bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);
270}
271
272static int bcm54xx_config_init(struct phy_device *phydev)
273{
274 int reg, err, val;
275
276 reg = phy_read(phydev, MII_BCM54XX_ECR);
277 if (reg < 0)
278 return reg;
279
280 /* Mask interrupts globally. */
281 reg |= MII_BCM54XX_ECR_IM;
282 err = phy_write(phydev, MII_BCM54XX_ECR, reg);
283 if (err < 0)
284 return err;
285
286 /* Unmask events we are interested in. */
287 reg = ~(MII_BCM54XX_INT_DUPLEX |
288 MII_BCM54XX_INT_SPEED |
289 MII_BCM54XX_INT_LINK);
290 err = phy_write(phydev, MII_BCM54XX_IMR, reg);
291 if (err < 0)
292 return err;
293
294 if ((BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610 ||
295 BRCM_PHY_MODEL(phydev) == PHY_ID_BCM50610M) &&
296 (phydev->dev_flags & PHY_BRCM_CLEAR_RGMII_MODE))
297 bcm_phy_write_shadow(phydev, BCM54XX_SHD_RGMII_MODE, 0);
298
299 if ((phydev->dev_flags & PHY_BRCM_RX_REFCLK_UNUSED) ||
300 (phydev->dev_flags & PHY_BRCM_DIS_TXCRXC_NOENRGY) ||
301 (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
302 bcm54xx_adjust_rxrefclk(phydev);
303
304 if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54210E) {
305 err = bcm54210e_config_init(phydev);
306 if (err)
307 return err;
308 } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54612E) {
309 err = bcm54612e_config_init(phydev);
310 if (err)
311 return err;
312 } else if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
313 /* For BCM54810, we need to disable BroadR-Reach function */
314 val = bcm_phy_read_exp(phydev,
315 BCM54810_EXP_BROADREACH_LRE_MISC_CTL);
316 val &= ~BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN;
317 err = bcm_phy_write_exp(phydev,
318 BCM54810_EXP_BROADREACH_LRE_MISC_CTL,
319 val);
320 if (err < 0)
321 return err;
322 }
323
324 bcm54xx_phydsp_config(phydev);
325
326 /* Encode link speed into LED1 and LED3 pair (green/amber).
327 * Also flash these two LEDs on activity. This means configuring
328 * them for MULTICOLOR and encoding link/activity into them.
329 */
330 val = BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_MULTICOLOR1) |
331 BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_MULTICOLOR1);
332 bcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1, val);
333
334 val = BCM_LED_MULTICOLOR_IN_PHASE |
335 BCM5482_SHD_LEDS1_LED1(BCM_LED_MULTICOLOR_LINK_ACT) |
336 BCM5482_SHD_LEDS1_LED3(BCM_LED_MULTICOLOR_LINK_ACT);
337 bcm_phy_write_exp(phydev, BCM_EXP_MULTICOLOR, val);
338
339 return 0;
340}
341
342static int bcm5482_config_init(struct phy_device *phydev)
343{
344 int err, reg;
345
346 err = bcm54xx_config_init(phydev);
347
348 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
349 /*
350 * Enable secondary SerDes and its use as an LED source
351 */
352 reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_SSD);
353 bcm_phy_write_shadow(phydev, BCM5482_SHD_SSD,
354 reg |
355 BCM5482_SHD_SSD_LEDM |
356 BCM5482_SHD_SSD_EN);
357
358 /*
359 * Enable SGMII slave mode and auto-detection
360 */
361 reg = BCM5482_SSD_SGMII_SLAVE | MII_BCM54XX_EXP_SEL_SSD;
362 err = bcm_phy_read_exp(phydev, reg);
363 if (err < 0)
364 return err;
365 err = bcm_phy_write_exp(phydev, reg, err |
366 BCM5482_SSD_SGMII_SLAVE_EN |
367 BCM5482_SSD_SGMII_SLAVE_AD);
368 if (err < 0)
369 return err;
370
371 /*
372 * Disable secondary SerDes powerdown
373 */
374 reg = BCM5482_SSD_1000BX_CTL | MII_BCM54XX_EXP_SEL_SSD;
375 err = bcm_phy_read_exp(phydev, reg);
376 if (err < 0)
377 return err;
378 err = bcm_phy_write_exp(phydev, reg,
379 err & ~BCM5482_SSD_1000BX_CTL_PWRDOWN);
380 if (err < 0)
381 return err;
382
383 /*
384 * Select 1000BASE-X register set (primary SerDes)
385 */
386 reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_MODE);
387 bcm_phy_write_shadow(phydev, BCM5482_SHD_MODE,
388 reg | BCM5482_SHD_MODE_1000BX);
389
390 /*
391 * LED1=ACTIVITYLED, LED3=LINKSPD[2]
392 * (Use LED1 as secondary SerDes ACTIVITY LED)
393 */
394 bcm_phy_write_shadow(phydev, BCM5482_SHD_LEDS1,
395 BCM5482_SHD_LEDS1_LED1(BCM_LED_SRC_ACTIVITYLED) |
396 BCM5482_SHD_LEDS1_LED3(BCM_LED_SRC_LINKSPD2));
397
398 /*
399 * Auto-negotiation doesn't seem to work quite right
400 * in this mode, so we disable it and force it to the
401 * right speed/duplex setting. Only 'link status'
402 * is important.
403 */
404 phydev->autoneg = AUTONEG_DISABLE;
405 phydev->speed = SPEED_1000;
406 phydev->duplex = DUPLEX_FULL;
407 }
408
409 return err;
410}
411
412static int bcm5482_read_status(struct phy_device *phydev)
413{
414 int err;
415
416 err = genphy_read_status(phydev);
417
418 if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX) {
419 /*
420 * Only link status matters for 1000Base-X mode, so force
421 * 1000 Mbit/s full-duplex status
422 */
423 if (phydev->link) {
424 phydev->speed = SPEED_1000;
425 phydev->duplex = DUPLEX_FULL;
426 }
427 }
428
429 return err;
430}
431
432static int bcm5481_config_aneg(struct phy_device *phydev)
433{
434 struct device_node *np = phydev->mdio.dev.of_node;
435 int ret;
436
437 /* Aneg firsly. */
438 ret = genphy_config_aneg(phydev);
439
440 /* Then we can set up the delay. */
441 bcm54xx_config_clock_delay(phydev);
442
443 if (of_property_read_bool(np, "enet-phy-lane-swap")) {
444 /* Lane Swap - Undocumented register...magic! */
445 ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
446 0x11B);
447 if (ret < 0)
448 return ret;
449 }
450
451 return ret;
452}
453
454static int bcm54616s_config_aneg(struct phy_device *phydev)
455{
456 int ret;
457
458 /* Aneg firsly. */
459 ret = genphy_config_aneg(phydev);
460
461 /* Then we can set up the delay. */
462 bcm54xx_config_clock_delay(phydev);
463
464 return ret;
465}
466
467static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
468{
469 int val;
470
471 val = phy_read(phydev, reg);
472 if (val < 0)
473 return val;
474
475 return phy_write(phydev, reg, val | set);
476}
477
478static int brcm_fet_config_init(struct phy_device *phydev)
479{
480 int reg, err, err2, brcmtest;
481
482 /* Reset the PHY to bring it to a known state. */
483 err = phy_write(phydev, MII_BMCR, BMCR_RESET);
484 if (err < 0)
485 return err;
486
487 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
488 if (reg < 0)
489 return reg;
490
491 /* Unmask events we are interested in and mask interrupts globally. */
492 reg = MII_BRCM_FET_IR_DUPLEX_EN |
493 MII_BRCM_FET_IR_SPEED_EN |
494 MII_BRCM_FET_IR_LINK_EN |
495 MII_BRCM_FET_IR_ENABLE |
496 MII_BRCM_FET_IR_MASK;
497
498 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
499 if (err < 0)
500 return err;
501
502 /* Enable shadow register access */
503 brcmtest = phy_read(phydev, MII_BRCM_FET_BRCMTEST);
504 if (brcmtest < 0)
505 return brcmtest;
506
507 reg = brcmtest | MII_BRCM_FET_BT_SRE;
508
509 err = phy_write(phydev, MII_BRCM_FET_BRCMTEST, reg);
510 if (err < 0)
511 return err;
512
513 /* Set the LED mode */
514 reg = phy_read(phydev, MII_BRCM_FET_SHDW_AUXMODE4);
515 if (reg < 0) {
516 err = reg;
517 goto done;
518 }
519
520 reg &= ~MII_BRCM_FET_SHDW_AM4_LED_MASK;
521 reg |= MII_BRCM_FET_SHDW_AM4_LED_MODE1;
522
523 err = phy_write(phydev, MII_BRCM_FET_SHDW_AUXMODE4, reg);
524 if (err < 0)
525 goto done;
526
527 /* Enable auto MDIX */
528 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_MISCCTRL,
529 MII_BRCM_FET_SHDW_MC_FAME);
530 if (err < 0)
531 goto done;
532
533 if (phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE) {
534 /* Enable auto power down */
535 err = brcm_phy_setbits(phydev, MII_BRCM_FET_SHDW_AUXSTAT2,
536 MII_BRCM_FET_SHDW_AS2_APDE);
537 }
538
539done:
540 /* Disable shadow register access */
541 err2 = phy_write(phydev, MII_BRCM_FET_BRCMTEST, brcmtest);
542 if (!err)
543 err = err2;
544
545 return err;
546}
547
548static int brcm_fet_ack_interrupt(struct phy_device *phydev)
549{
550 int reg;
551
552 /* Clear pending interrupts. */
553 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
554 if (reg < 0)
555 return reg;
556
557 return 0;
558}
559
560static int brcm_fet_config_intr(struct phy_device *phydev)
561{
562 int reg, err;
563
564 reg = phy_read(phydev, MII_BRCM_FET_INTREG);
565 if (reg < 0)
566 return reg;
567
568 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
569 reg &= ~MII_BRCM_FET_IR_MASK;
570 else
571 reg |= MII_BRCM_FET_IR_MASK;
572
573 err = phy_write(phydev, MII_BRCM_FET_INTREG, reg);
574 return err;
575}
576
577struct bcm53xx_phy_priv {
578 u64 *stats;
579};
580
581static int bcm53xx_phy_probe(struct phy_device *phydev)
582{
583 struct bcm53xx_phy_priv *priv;
584
585 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
586 if (!priv)
587 return -ENOMEM;
588
589 phydev->priv = priv;
590
591 priv->stats = devm_kcalloc(&phydev->mdio.dev,
592 bcm_phy_get_sset_count(phydev), sizeof(u64),
593 GFP_KERNEL);
594 if (!priv->stats)
595 return -ENOMEM;
596
597 return 0;
598}
599
600static void bcm53xx_phy_get_stats(struct phy_device *phydev,
601 struct ethtool_stats *stats, u64 *data)
602{
603 struct bcm53xx_phy_priv *priv = phydev->priv;
604
605 bcm_phy_get_stats(phydev, priv->stats, stats, data);
606}
607
608static struct phy_driver broadcom_drivers[] = {
609{
610 .phy_id = PHY_ID_BCM5411,
611 .phy_id_mask = 0xfffffff0,
612 .name = "Broadcom BCM5411",
613 /* PHY_GBIT_FEATURES */
614 .config_init = bcm54xx_config_init,
615 .ack_interrupt = bcm_phy_ack_intr,
616 .config_intr = bcm_phy_config_intr,
617}, {
618 .phy_id = PHY_ID_BCM5421,
619 .phy_id_mask = 0xfffffff0,
620 .name = "Broadcom BCM5421",
621 /* PHY_GBIT_FEATURES */
622 .config_init = bcm54xx_config_init,
623 .ack_interrupt = bcm_phy_ack_intr,
624 .config_intr = bcm_phy_config_intr,
625}, {
626 .phy_id = PHY_ID_BCM54210E,
627 .phy_id_mask = 0xfffffff0,
628 .name = "Broadcom BCM54210E",
629 /* PHY_GBIT_FEATURES */
630 .config_init = bcm54xx_config_init,
631 .ack_interrupt = bcm_phy_ack_intr,
632 .config_intr = bcm_phy_config_intr,
633}, {
634 .phy_id = PHY_ID_BCM5461,
635 .phy_id_mask = 0xfffffff0,
636 .name = "Broadcom BCM5461",
637 /* PHY_GBIT_FEATURES */
638 .config_init = bcm54xx_config_init,
639 .ack_interrupt = bcm_phy_ack_intr,
640 .config_intr = bcm_phy_config_intr,
641}, {
642 .phy_id = PHY_ID_BCM54612E,
643 .phy_id_mask = 0xfffffff0,
644 .name = "Broadcom BCM54612E",
645 /* PHY_GBIT_FEATURES */
646 .config_init = bcm54xx_config_init,
647 .ack_interrupt = bcm_phy_ack_intr,
648 .config_intr = bcm_phy_config_intr,
649}, {
650 .phy_id = PHY_ID_BCM54616S,
651 .phy_id_mask = 0xfffffff0,
652 .name = "Broadcom BCM54616S",
653 /* PHY_GBIT_FEATURES */
654 .config_init = bcm54xx_config_init,
655 .config_aneg = bcm54616s_config_aneg,
656 .ack_interrupt = bcm_phy_ack_intr,
657 .config_intr = bcm_phy_config_intr,
658}, {
659 .phy_id = PHY_ID_BCM5464,
660 .phy_id_mask = 0xfffffff0,
661 .name = "Broadcom BCM5464",
662 /* PHY_GBIT_FEATURES */
663 .config_init = bcm54xx_config_init,
664 .ack_interrupt = bcm_phy_ack_intr,
665 .config_intr = bcm_phy_config_intr,
666 .suspend = genphy_suspend,
667 .resume = genphy_resume,
668}, {
669 .phy_id = PHY_ID_BCM5481,
670 .phy_id_mask = 0xfffffff0,
671 .name = "Broadcom BCM5481",
672 /* PHY_GBIT_FEATURES */
673 .config_init = bcm54xx_config_init,
674 .config_aneg = bcm5481_config_aneg,
675 .ack_interrupt = bcm_phy_ack_intr,
676 .config_intr = bcm_phy_config_intr,
677}, {
678 .phy_id = PHY_ID_BCM54810,
679 .phy_id_mask = 0xfffffff0,
680 .name = "Broadcom BCM54810",
681 /* PHY_GBIT_FEATURES */
682 .config_init = bcm54xx_config_init,
683 .config_aneg = bcm5481_config_aneg,
684 .ack_interrupt = bcm_phy_ack_intr,
685 .config_intr = bcm_phy_config_intr,
686}, {
687 .phy_id = PHY_ID_BCM5482,
688 .phy_id_mask = 0xfffffff0,
689 .name = "Broadcom BCM5482",
690 /* PHY_GBIT_FEATURES */
691 .config_init = bcm5482_config_init,
692 .read_status = bcm5482_read_status,
693 .ack_interrupt = bcm_phy_ack_intr,
694 .config_intr = bcm_phy_config_intr,
695}, {
696 .phy_id = PHY_ID_BCM50610,
697 .phy_id_mask = 0xfffffff0,
698 .name = "Broadcom BCM50610",
699 /* PHY_GBIT_FEATURES */
700 .config_init = bcm54xx_config_init,
701 .ack_interrupt = bcm_phy_ack_intr,
702 .config_intr = bcm_phy_config_intr,
703}, {
704 .phy_id = PHY_ID_BCM50610M,
705 .phy_id_mask = 0xfffffff0,
706 .name = "Broadcom BCM50610M",
707 /* PHY_GBIT_FEATURES */
708 .config_init = bcm54xx_config_init,
709 .ack_interrupt = bcm_phy_ack_intr,
710 .config_intr = bcm_phy_config_intr,
711}, {
712 .phy_id = PHY_ID_BCM57780,
713 .phy_id_mask = 0xfffffff0,
714 .name = "Broadcom BCM57780",
715 /* PHY_GBIT_FEATURES */
716 .config_init = bcm54xx_config_init,
717 .ack_interrupt = bcm_phy_ack_intr,
718 .config_intr = bcm_phy_config_intr,
719}, {
720 .phy_id = PHY_ID_BCMAC131,
721 .phy_id_mask = 0xfffffff0,
722 .name = "Broadcom BCMAC131",
723 /* PHY_BASIC_FEATURES */
724 .config_init = brcm_fet_config_init,
725 .ack_interrupt = brcm_fet_ack_interrupt,
726 .config_intr = brcm_fet_config_intr,
727}, {
728 .phy_id = PHY_ID_BCM5241,
729 .phy_id_mask = 0xfffffff0,
730 .name = "Broadcom BCM5241",
731 /* PHY_BASIC_FEATURES */
732 .config_init = brcm_fet_config_init,
733 .ack_interrupt = brcm_fet_ack_interrupt,
734 .config_intr = brcm_fet_config_intr,
735}, {
736 .phy_id = PHY_ID_BCM5395,
737 .phy_id_mask = 0xfffffff0,
738 .name = "Broadcom BCM5395",
739 .flags = PHY_IS_INTERNAL,
740 /* PHY_GBIT_FEATURES */
741 .get_sset_count = bcm_phy_get_sset_count,
742 .get_strings = bcm_phy_get_strings,
743 .get_stats = bcm53xx_phy_get_stats,
744 .probe = bcm53xx_phy_probe,
745}, {
746 .phy_id = PHY_ID_BCM89610,
747 .phy_id_mask = 0xfffffff0,
748 .name = "Broadcom BCM89610",
749 /* PHY_GBIT_FEATURES */
750 .config_init = bcm54xx_config_init,
751 .ack_interrupt = bcm_phy_ack_intr,
752 .config_intr = bcm_phy_config_intr,
753} };
754
755module_phy_driver(broadcom_drivers);
756
757static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
758 { PHY_ID_BCM5411, 0xfffffff0 },
759 { PHY_ID_BCM5421, 0xfffffff0 },
760 { PHY_ID_BCM54210E, 0xfffffff0 },
761 { PHY_ID_BCM5461, 0xfffffff0 },
762 { PHY_ID_BCM54612E, 0xfffffff0 },
763 { PHY_ID_BCM54616S, 0xfffffff0 },
764 { PHY_ID_BCM5464, 0xfffffff0 },
765 { PHY_ID_BCM5481, 0xfffffff0 },
766 { PHY_ID_BCM54810, 0xfffffff0 },
767 { PHY_ID_BCM5482, 0xfffffff0 },
768 { PHY_ID_BCM50610, 0xfffffff0 },
769 { PHY_ID_BCM50610M, 0xfffffff0 },
770 { PHY_ID_BCM57780, 0xfffffff0 },
771 { PHY_ID_BCMAC131, 0xfffffff0 },
772 { PHY_ID_BCM5241, 0xfffffff0 },
773 { PHY_ID_BCM5395, 0xfffffff0 },
774 { PHY_ID_BCM89610, 0xfffffff0 },
775 { }
776};
777
778MODULE_DEVICE_TABLE(mdio, broadcom_tbl);