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1/*
2 * Device Tree Source for OMAP2420 SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include "omap2.dtsi"
12
13/ {
14 compatible = "ti,omap2420", "ti,omap2";
15
16 ocp {
17 l4: l4@48000000 {
18 compatible = "ti,omap2-l4", "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 ranges = <0 0x48000000 0x100000>;
22
23 prcm: prcm@8000 {
24 compatible = "ti,omap2-prcm";
25 reg = <0x8000 0x1000>;
26
27 prcm_clocks: clocks {
28 #address-cells = <1>;
29 #size-cells = <0>;
30 };
31
32 prcm_clockdomains: clockdomains {
33 };
34 };
35
36 scm: scm@0 {
37 compatible = "ti,omap2-scm", "simple-bus";
38 reg = <0x0 0x1000>;
39 #address-cells = <1>;
40 #size-cells = <1>;
41 #pinctrl-cells = <1>;
42 ranges = <0 0x0 0x1000>;
43
44 omap2420_pmx: pinmux@30 {
45 compatible = "ti,omap2420-padconf",
46 "pinctrl-single";
47 reg = <0x30 0x0113>;
48 #address-cells = <1>;
49 #size-cells = <0>;
50 #pinctrl-cells = <1>;
51 pinctrl-single,register-width = <8>;
52 pinctrl-single,function-mask = <0x3f>;
53 };
54
55 scm_conf: scm_conf@270 {
56 compatible = "syscon";
57 reg = <0x270 0x100>;
58 #address-cells = <1>;
59 #size-cells = <1>;
60
61 scm_clocks: clocks {
62 #address-cells = <1>;
63 #size-cells = <0>;
64 };
65 };
66
67 scm_clockdomains: clockdomains {
68 };
69 };
70
71 counter32k: counter@4000 {
72 compatible = "ti,omap-counter32k";
73 reg = <0x4000 0x20>;
74 ti,hwmods = "counter_32k";
75 };
76 };
77
78 gpio1: gpio@48018000 {
79 compatible = "ti,omap2-gpio";
80 reg = <0x48018000 0x200>;
81 interrupts = <29>;
82 ti,hwmods = "gpio1";
83 ti,gpio-always-on;
84 #gpio-cells = <2>;
85 gpio-controller;
86 #interrupt-cells = <2>;
87 interrupt-controller;
88 };
89
90 gpio2: gpio@4801a000 {
91 compatible = "ti,omap2-gpio";
92 reg = <0x4801a000 0x200>;
93 interrupts = <30>;
94 ti,hwmods = "gpio2";
95 ti,gpio-always-on;
96 #gpio-cells = <2>;
97 gpio-controller;
98 #interrupt-cells = <2>;
99 interrupt-controller;
100 };
101
102 gpio3: gpio@4801c000 {
103 compatible = "ti,omap2-gpio";
104 reg = <0x4801c000 0x200>;
105 interrupts = <31>;
106 ti,hwmods = "gpio3";
107 ti,gpio-always-on;
108 #gpio-cells = <2>;
109 gpio-controller;
110 #interrupt-cells = <2>;
111 interrupt-controller;
112 };
113
114 gpio4: gpio@4801e000 {
115 compatible = "ti,omap2-gpio";
116 reg = <0x4801e000 0x200>;
117 interrupts = <32>;
118 ti,hwmods = "gpio4";
119 ti,gpio-always-on;
120 #gpio-cells = <2>;
121 gpio-controller;
122 #interrupt-cells = <2>;
123 interrupt-controller;
124 };
125
126 gpmc: gpmc@6800a000 {
127 compatible = "ti,omap2420-gpmc";
128 reg = <0x6800a000 0x1000>;
129 #address-cells = <2>;
130 #size-cells = <1>;
131 interrupts = <20>;
132 gpmc,num-cs = <8>;
133 gpmc,num-waitpins = <4>;
134 ti,hwmods = "gpmc";
135 interrupt-controller;
136 #interrupt-cells = <2>;
137 gpio-controller;
138 #gpio-cells = <2>;
139 };
140
141 mcbsp1: mcbsp@48074000 {
142 compatible = "ti,omap2420-mcbsp";
143 reg = <0x48074000 0xff>;
144 reg-names = "mpu";
145 interrupts = <59>, /* TX interrupt */
146 <60>; /* RX interrupt */
147 interrupt-names = "tx", "rx";
148 ti,hwmods = "mcbsp1";
149 dmas = <&sdma 31>,
150 <&sdma 32>;
151 dma-names = "tx", "rx";
152 status = "disabled";
153 };
154
155 mcbsp2: mcbsp@48076000 {
156 compatible = "ti,omap2420-mcbsp";
157 reg = <0x48076000 0xff>;
158 reg-names = "mpu";
159 interrupts = <62>, /* TX interrupt */
160 <63>; /* RX interrupt */
161 interrupt-names = "tx", "rx";
162 ti,hwmods = "mcbsp2";
163 dmas = <&sdma 33>,
164 <&sdma 34>;
165 dma-names = "tx", "rx";
166 status = "disabled";
167 };
168
169 msdi1: mmc@4809c000 {
170 compatible = "ti,omap2420-mmc";
171 ti,hwmods = "msdi1";
172 reg = <0x4809c000 0x80>;
173 interrupts = <83>;
174 dmas = <&sdma 61 &sdma 62>;
175 dma-names = "tx", "rx";
176 };
177
178 mailbox: mailbox@48094000 {
179 compatible = "ti,omap2-mailbox";
180 reg = <0x48094000 0x200>;
181 interrupts = <26>, <34>;
182 interrupt-names = "dsp", "iva";
183 ti,hwmods = "mailbox";
184 #mbox-cells = <1>;
185 ti,mbox-num-users = <4>;
186 ti,mbox-num-fifos = <6>;
187 mbox_dsp: dsp {
188 ti,mbox-tx = <0 0 0>;
189 ti,mbox-rx = <1 0 0>;
190 };
191 mbox_iva: iva {
192 ti,mbox-tx = <2 1 3>;
193 ti,mbox-rx = <3 1 3>;
194 };
195 };
196
197 timer1: timer@48028000 {
198 compatible = "ti,omap2420-timer";
199 reg = <0x48028000 0x400>;
200 interrupts = <37>;
201 ti,hwmods = "timer1";
202 ti,timer-alwon;
203 };
204
205 wd_timer2: wdt@48022000 {
206 compatible = "ti,omap2-wdt";
207 ti,hwmods = "wd_timer2";
208 reg = <0x48022000 0x80>;
209 };
210 };
211};
212
213&i2c1 {
214 compatible = "ti,omap2420-i2c";
215};
216
217&i2c2 {
218 compatible = "ti,omap2420-i2c";
219};
220
221/include/ "omap24xx-clocks.dtsi"
222/include/ "omap2420-clocks.dtsi"
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Device Tree Source for OMAP2420 SoC
4 *
5 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
6 */
7
8#include "omap2.dtsi"
9
10/ {
11 compatible = "ti,omap2420", "ti,omap2";
12
13 ocp {
14 l4: l4@48000000 {
15 compatible = "ti,omap2-l4", "simple-bus";
16 #address-cells = <1>;
17 #size-cells = <1>;
18 ranges = <0 0x48000000 0x100000>;
19
20 prcm: prcm@8000 {
21 compatible = "ti,omap2-prcm";
22 reg = <0x8000 0x1000>;
23
24 prcm_clocks: clocks {
25 #address-cells = <1>;
26 #size-cells = <0>;
27 };
28
29 prcm_clockdomains: clockdomains {
30 };
31 };
32
33 scm: scm@0 {
34 compatible = "ti,omap2-scm", "simple-bus";
35 reg = <0x0 0x1000>;
36 #address-cells = <1>;
37 #size-cells = <1>;
38 #pinctrl-cells = <1>;
39 ranges = <0 0x0 0x1000>;
40
41 omap2420_pmx: pinmux@30 {
42 compatible = "ti,omap2420-padconf",
43 "pinctrl-single";
44 reg = <0x30 0x0113>;
45 #address-cells = <1>;
46 #size-cells = <0>;
47 #pinctrl-cells = <1>;
48 pinctrl-single,register-width = <8>;
49 pinctrl-single,function-mask = <0x3f>;
50 };
51
52 scm_conf: scm_conf@270 {
53 compatible = "syscon";
54 reg = <0x270 0x100>;
55 #address-cells = <1>;
56 #size-cells = <1>;
57
58 scm_clocks: clocks {
59 #address-cells = <1>;
60 #size-cells = <0>;
61 };
62 };
63
64 scm_clockdomains: clockdomains {
65 };
66 };
67
68 target-module@4000 {
69 compatible = "ti,sysc-omap2", "ti,sysc";
70 reg = <0x4000 0x4>,
71 <0x4004 0x4>;
72 reg-names = "rev", "sysc";
73 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
74 <SYSC_IDLE_NO>;
75 clocks = <&func_32k_ck>;
76 clock-names = "fck";
77 #address-cells = <1>;
78 #size-cells = <1>;
79 ranges = <0x0 0x4000 0x1000>;
80
81 counter32k: counter@0 {
82 compatible = "ti,omap-counter32k";
83 reg = <0 0x20>;
84 };
85 };
86 };
87
88 gpio1: gpio@48018000 {
89 compatible = "ti,omap2-gpio";
90 reg = <0x48018000 0x200>;
91 interrupts = <29>;
92 ti,hwmods = "gpio1";
93 ti,gpio-always-on;
94 #gpio-cells = <2>;
95 gpio-controller;
96 #interrupt-cells = <2>;
97 interrupt-controller;
98 };
99
100 gpio2: gpio@4801a000 {
101 compatible = "ti,omap2-gpio";
102 reg = <0x4801a000 0x200>;
103 interrupts = <30>;
104 ti,hwmods = "gpio2";
105 ti,gpio-always-on;
106 #gpio-cells = <2>;
107 gpio-controller;
108 #interrupt-cells = <2>;
109 interrupt-controller;
110 };
111
112 gpio3: gpio@4801c000 {
113 compatible = "ti,omap2-gpio";
114 reg = <0x4801c000 0x200>;
115 interrupts = <31>;
116 ti,hwmods = "gpio3";
117 ti,gpio-always-on;
118 #gpio-cells = <2>;
119 gpio-controller;
120 #interrupt-cells = <2>;
121 interrupt-controller;
122 };
123
124 gpio4: gpio@4801e000 {
125 compatible = "ti,omap2-gpio";
126 reg = <0x4801e000 0x200>;
127 interrupts = <32>;
128 ti,hwmods = "gpio4";
129 ti,gpio-always-on;
130 #gpio-cells = <2>;
131 gpio-controller;
132 #interrupt-cells = <2>;
133 interrupt-controller;
134 };
135
136 gpmc: gpmc@6800a000 {
137 compatible = "ti,omap2420-gpmc";
138 reg = <0x6800a000 0x1000>;
139 #address-cells = <2>;
140 #size-cells = <1>;
141 interrupts = <20>;
142 gpmc,num-cs = <8>;
143 gpmc,num-waitpins = <4>;
144 ti,hwmods = "gpmc";
145 interrupt-controller;
146 #interrupt-cells = <2>;
147 gpio-controller;
148 #gpio-cells = <2>;
149 };
150
151 mcbsp1: mcbsp@48074000 {
152 compatible = "ti,omap2420-mcbsp";
153 reg = <0x48074000 0xff>;
154 reg-names = "mpu";
155 interrupts = <59>, /* TX interrupt */
156 <60>; /* RX interrupt */
157 interrupt-names = "tx", "rx";
158 ti,hwmods = "mcbsp1";
159 dmas = <&sdma 31>,
160 <&sdma 32>;
161 dma-names = "tx", "rx";
162 status = "disabled";
163 };
164
165 mcbsp2: mcbsp@48076000 {
166 compatible = "ti,omap2420-mcbsp";
167 reg = <0x48076000 0xff>;
168 reg-names = "mpu";
169 interrupts = <62>, /* TX interrupt */
170 <63>; /* RX interrupt */
171 interrupt-names = "tx", "rx";
172 ti,hwmods = "mcbsp2";
173 dmas = <&sdma 33>,
174 <&sdma 34>;
175 dma-names = "tx", "rx";
176 status = "disabled";
177 };
178
179 msdi1: mmc@4809c000 {
180 compatible = "ti,omap2420-mmc";
181 ti,hwmods = "msdi1";
182 reg = <0x4809c000 0x80>;
183 interrupts = <83>;
184 dmas = <&sdma 61 &sdma 62>;
185 dma-names = "tx", "rx";
186 };
187
188 mailbox: mailbox@48094000 {
189 compatible = "ti,omap2-mailbox";
190 reg = <0x48094000 0x200>;
191 interrupts = <26>, <34>;
192 ti,hwmods = "mailbox";
193 #mbox-cells = <1>;
194 ti,mbox-num-users = <4>;
195 ti,mbox-num-fifos = <6>;
196 mbox_dsp: mbox-dsp {
197 ti,mbox-tx = <0 0 0>;
198 ti,mbox-rx = <1 0 0>;
199 };
200 mbox_iva: mbox-iva {
201 ti,mbox-tx = <2 1 3>;
202 ti,mbox-rx = <3 1 3>;
203 };
204 };
205
206 timer1_target: target-module@48028000 {
207 compatible = "ti,sysc-omap2-timer", "ti,sysc";
208 reg = <0x48028000 0x4>,
209 <0x48028010 0x4>,
210 <0x48028014 0x4>;
211 reg-names = "rev", "sysc", "syss";
212 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
213 SYSC_OMAP2_EMUFREE |
214 SYSC_OMAP2_ENAWAKEUP |
215 SYSC_OMAP2_SOFTRESET |
216 SYSC_OMAP2_AUTOIDLE)>;
217 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
218 <SYSC_IDLE_NO>,
219 <SYSC_IDLE_SMART>;
220 ti,syss-mask = <1>;
221 clocks = <&gpt1_fck>, <&gpt1_ick>;
222 clock-names = "fck", "ick";
223 #address-cells = <1>;
224 #size-cells = <1>;
225 ranges = <0x0 0x48028000 0x1000>;
226
227 timer1: timer@0 {
228 compatible = "ti,omap2420-timer";
229 reg = <0 0x400>;
230 interrupts = <37>;
231 ti,timer-alwon;
232 };
233 };
234
235 wd_timer2: wdt@48022000 {
236 compatible = "ti,omap2-wdt";
237 ti,hwmods = "wd_timer2";
238 reg = <0x48022000 0x80>;
239 };
240 };
241};
242
243&i2c1 {
244 compatible = "ti,omap2420-i2c";
245};
246
247&i2c2 {
248 compatible = "ti,omap2420-i2c";
249};
250
251#include "omap24xx-clocks.dtsi"
252#include "omap2420-clocks.dtsi"
253
254/* Preferred always-on timer for clockevent */
255&timer1_target {
256 ti,no-reset-on-init;
257 ti,no-idle;
258 timer@0 {
259 assigned-clocks = <&gpt1_fck>;
260 assigned-clock-parents = <&func_32k_ck>;
261 };
262};