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1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24#include <linux/kthread.h>
25#include <linux/wait.h>
26#include <linux/sched.h>
27#include <drm/drmP.h>
28#include "amdgpu.h"
29#include "amdgpu_trace.h"
30
31static void amdgpu_job_timedout(struct drm_sched_job *s_job)
32{
33 struct amdgpu_job *job = container_of(s_job, struct amdgpu_job, base);
34
35 DRM_ERROR("ring %s timeout, last signaled seq=%u, last emitted seq=%u\n",
36 job->base.sched->name,
37 atomic_read(&job->ring->fence_drv.last_seq),
38 job->ring->fence_drv.sync_seq);
39
40 amdgpu_device_gpu_recover(job->adev, job, false);
41}
42
43int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
44 struct amdgpu_job **job, struct amdgpu_vm *vm)
45{
46 size_t size = sizeof(struct amdgpu_job);
47
48 if (num_ibs == 0)
49 return -EINVAL;
50
51 size += sizeof(struct amdgpu_ib) * num_ibs;
52
53 *job = kzalloc(size, GFP_KERNEL);
54 if (!*job)
55 return -ENOMEM;
56
57 (*job)->adev = adev;
58 (*job)->vm = vm;
59 (*job)->ibs = (void *)&(*job)[1];
60 (*job)->num_ibs = num_ibs;
61
62 amdgpu_sync_create(&(*job)->sync);
63 amdgpu_sync_create(&(*job)->sched_sync);
64 (*job)->vram_lost_counter = atomic_read(&adev->vram_lost_counter);
65
66 return 0;
67}
68
69int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
70 struct amdgpu_job **job)
71{
72 int r;
73
74 r = amdgpu_job_alloc(adev, 1, job, NULL);
75 if (r)
76 return r;
77
78 r = amdgpu_ib_get(adev, NULL, size, &(*job)->ibs[0]);
79 if (r)
80 kfree(*job);
81 else
82 (*job)->vm_pd_addr = adev->gart.table_addr;
83
84 return r;
85}
86
87void amdgpu_job_free_resources(struct amdgpu_job *job)
88{
89 struct dma_fence *f;
90 unsigned i;
91
92 /* use sched fence if available */
93 f = job->base.s_fence ? &job->base.s_fence->finished : job->fence;
94
95 for (i = 0; i < job->num_ibs; ++i)
96 amdgpu_ib_free(job->adev, &job->ibs[i], f);
97}
98
99static void amdgpu_job_free_cb(struct drm_sched_job *s_job)
100{
101 struct amdgpu_job *job = container_of(s_job, struct amdgpu_job, base);
102
103 amdgpu_ring_priority_put(job->ring, s_job->s_priority);
104 dma_fence_put(job->fence);
105 amdgpu_sync_free(&job->sync);
106 amdgpu_sync_free(&job->sched_sync);
107 kfree(job);
108}
109
110void amdgpu_job_free(struct amdgpu_job *job)
111{
112 amdgpu_job_free_resources(job);
113
114 dma_fence_put(job->fence);
115 amdgpu_sync_free(&job->sync);
116 amdgpu_sync_free(&job->sched_sync);
117 kfree(job);
118}
119
120int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
121 struct drm_sched_entity *entity, void *owner,
122 struct dma_fence **f)
123{
124 int r;
125 job->ring = ring;
126
127 if (!f)
128 return -EINVAL;
129
130 r = drm_sched_job_init(&job->base, &ring->sched, entity, owner);
131 if (r)
132 return r;
133
134 job->owner = owner;
135 job->fence_ctx = entity->fence_context;
136 *f = dma_fence_get(&job->base.s_fence->finished);
137 amdgpu_job_free_resources(job);
138 amdgpu_ring_priority_get(job->ring, job->base.s_priority);
139 drm_sched_entity_push_job(&job->base, entity);
140
141 return 0;
142}
143
144static struct dma_fence *amdgpu_job_dependency(struct drm_sched_job *sched_job,
145 struct drm_sched_entity *s_entity)
146{
147 struct amdgpu_job *job = to_amdgpu_job(sched_job);
148 struct amdgpu_vm *vm = job->vm;
149 bool explicit = false;
150 int r;
151 struct dma_fence *fence = amdgpu_sync_get_fence(&job->sync, &explicit);
152
153 if (fence && explicit) {
154 if (drm_sched_dependency_optimized(fence, s_entity)) {
155 r = amdgpu_sync_fence(job->adev, &job->sched_sync, fence, false);
156 if (r)
157 DRM_ERROR("Error adding fence to sync (%d)\n", r);
158 }
159 }
160
161 while (fence == NULL && vm && !job->vmid) {
162 struct amdgpu_ring *ring = job->ring;
163
164 r = amdgpu_vmid_grab(vm, ring, &job->sync,
165 &job->base.s_fence->finished,
166 job);
167 if (r)
168 DRM_ERROR("Error getting VM ID (%d)\n", r);
169
170 fence = amdgpu_sync_get_fence(&job->sync, NULL);
171 }
172
173 return fence;
174}
175
176static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
177{
178 struct dma_fence *fence = NULL, *finished;
179 struct amdgpu_device *adev;
180 struct amdgpu_job *job;
181 int r;
182
183 if (!sched_job) {
184 DRM_ERROR("job is null\n");
185 return NULL;
186 }
187 job = to_amdgpu_job(sched_job);
188 finished = &job->base.s_fence->finished;
189 adev = job->adev;
190
191 BUG_ON(amdgpu_sync_peek_fence(&job->sync, NULL));
192
193 trace_amdgpu_sched_run_job(job);
194
195 if (job->vram_lost_counter != atomic_read(&adev->vram_lost_counter))
196 dma_fence_set_error(finished, -ECANCELED);/* skip IB as well if VRAM lost */
197
198 if (finished->error < 0) {
199 DRM_INFO("Skip scheduling IBs!\n");
200 } else {
201 r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs, job,
202 &fence);
203 if (r)
204 DRM_ERROR("Error scheduling IBs (%d)\n", r);
205 }
206 /* if gpu reset, hw fence will be replaced here */
207 dma_fence_put(job->fence);
208 job->fence = dma_fence_get(fence);
209
210 amdgpu_job_free_resources(job);
211 return fence;
212}
213
214const struct drm_sched_backend_ops amdgpu_sched_ops = {
215 .dependency = amdgpu_job_dependency,
216 .run_job = amdgpu_job_run,
217 .timedout_job = amdgpu_job_timedout,
218 .free_job = amdgpu_job_free_cb
219};
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24#include <linux/kthread.h>
25#include <linux/wait.h>
26#include <linux/sched.h>
27
28#include <drm/drm_drv.h>
29
30#include "amdgpu.h"
31#include "amdgpu_trace.h"
32#include "amdgpu_reset.h"
33
34static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job)
35{
36 struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched);
37 struct amdgpu_job *job = to_amdgpu_job(s_job);
38 struct amdgpu_task_info ti;
39 struct amdgpu_device *adev = ring->adev;
40 int idx;
41 int r;
42
43 if (!drm_dev_enter(adev_to_drm(adev), &idx)) {
44 DRM_INFO("%s - device unplugged skipping recovery on scheduler:%s",
45 __func__, s_job->sched->name);
46
47 /* Effectively the job is aborted as the device is gone */
48 return DRM_GPU_SCHED_STAT_ENODEV;
49 }
50
51 memset(&ti, 0, sizeof(struct amdgpu_task_info));
52 adev->job_hang = true;
53
54 if (amdgpu_gpu_recovery &&
55 amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) {
56 DRM_ERROR("ring %s timeout, but soft recovered\n",
57 s_job->sched->name);
58 goto exit;
59 }
60
61 amdgpu_vm_get_task_info(ring->adev, job->pasid, &ti);
62 DRM_ERROR("ring %s timeout, signaled seq=%u, emitted seq=%u\n",
63 job->base.sched->name, atomic_read(&ring->fence_drv.last_seq),
64 ring->fence_drv.sync_seq);
65 DRM_ERROR("Process information: process %s pid %d thread %s pid %d\n",
66 ti.process_name, ti.tgid, ti.task_name, ti.pid);
67
68 if (amdgpu_device_should_recover_gpu(ring->adev)) {
69 struct amdgpu_reset_context reset_context;
70 memset(&reset_context, 0, sizeof(reset_context));
71
72 reset_context.method = AMD_RESET_METHOD_NONE;
73 reset_context.reset_req_dev = adev;
74 clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
75
76 r = amdgpu_device_gpu_recover(ring->adev, job, &reset_context);
77 if (r)
78 DRM_ERROR("GPU Recovery Failed: %d\n", r);
79 } else {
80 drm_sched_suspend_timeout(&ring->sched);
81 if (amdgpu_sriov_vf(adev))
82 adev->virt.tdr_debug = true;
83 }
84
85exit:
86 adev->job_hang = false;
87 drm_dev_exit(idx);
88 return DRM_GPU_SCHED_STAT_NOMINAL;
89}
90
91int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm,
92 struct drm_sched_entity *entity, void *owner,
93 unsigned int num_ibs, struct amdgpu_job **job)
94{
95 if (num_ibs == 0)
96 return -EINVAL;
97
98 *job = kzalloc(struct_size(*job, ibs, num_ibs), GFP_KERNEL);
99 if (!*job)
100 return -ENOMEM;
101
102 /*
103 * Initialize the scheduler to at least some ring so that we always
104 * have a pointer to adev.
105 */
106 (*job)->base.sched = &adev->rings[0]->sched;
107 (*job)->vm = vm;
108
109 amdgpu_sync_create(&(*job)->explicit_sync);
110 (*job)->vram_lost_counter = atomic_read(&adev->vram_lost_counter);
111 (*job)->vm_pd_addr = AMDGPU_BO_INVALID_OFFSET;
112
113 if (!entity)
114 return 0;
115
116 return drm_sched_job_init(&(*job)->base, entity, owner);
117}
118
119int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev,
120 struct drm_sched_entity *entity, void *owner,
121 size_t size, enum amdgpu_ib_pool_type pool_type,
122 struct amdgpu_job **job)
123{
124 int r;
125
126 r = amdgpu_job_alloc(adev, NULL, entity, owner, 1, job);
127 if (r)
128 return r;
129
130 (*job)->num_ibs = 1;
131 r = amdgpu_ib_get(adev, NULL, size, pool_type, &(*job)->ibs[0]);
132 if (r) {
133 if (entity)
134 drm_sched_job_cleanup(&(*job)->base);
135 kfree(*job);
136 }
137
138 return r;
139}
140
141void amdgpu_job_set_resources(struct amdgpu_job *job, struct amdgpu_bo *gds,
142 struct amdgpu_bo *gws, struct amdgpu_bo *oa)
143{
144 if (gds) {
145 job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT;
146 job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT;
147 }
148 if (gws) {
149 job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT;
150 job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT;
151 }
152 if (oa) {
153 job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT;
154 job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT;
155 }
156}
157
158void amdgpu_job_free_resources(struct amdgpu_job *job)
159{
160 struct amdgpu_ring *ring = to_amdgpu_ring(job->base.sched);
161 struct dma_fence *f;
162 unsigned i;
163
164 /* Check if any fences where initialized */
165 if (job->base.s_fence && job->base.s_fence->finished.ops)
166 f = &job->base.s_fence->finished;
167 else if (job->hw_fence.ops)
168 f = &job->hw_fence;
169 else
170 f = NULL;
171
172 for (i = 0; i < job->num_ibs; ++i)
173 amdgpu_ib_free(ring->adev, &job->ibs[i], f);
174}
175
176static void amdgpu_job_free_cb(struct drm_sched_job *s_job)
177{
178 struct amdgpu_job *job = to_amdgpu_job(s_job);
179
180 drm_sched_job_cleanup(s_job);
181
182 amdgpu_sync_free(&job->explicit_sync);
183
184 /* only put the hw fence if has embedded fence */
185 if (!job->hw_fence.ops)
186 kfree(job);
187 else
188 dma_fence_put(&job->hw_fence);
189}
190
191void amdgpu_job_set_gang_leader(struct amdgpu_job *job,
192 struct amdgpu_job *leader)
193{
194 struct dma_fence *fence = &leader->base.s_fence->scheduled;
195
196 WARN_ON(job->gang_submit);
197
198 /*
199 * Don't add a reference when we are the gang leader to avoid circle
200 * dependency.
201 */
202 if (job != leader)
203 dma_fence_get(fence);
204 job->gang_submit = fence;
205}
206
207void amdgpu_job_free(struct amdgpu_job *job)
208{
209 if (job->base.entity)
210 drm_sched_job_cleanup(&job->base);
211
212 amdgpu_job_free_resources(job);
213 amdgpu_sync_free(&job->explicit_sync);
214 if (job->gang_submit != &job->base.s_fence->scheduled)
215 dma_fence_put(job->gang_submit);
216
217 if (!job->hw_fence.ops)
218 kfree(job);
219 else
220 dma_fence_put(&job->hw_fence);
221}
222
223struct dma_fence *amdgpu_job_submit(struct amdgpu_job *job)
224{
225 struct dma_fence *f;
226
227 drm_sched_job_arm(&job->base);
228 f = dma_fence_get(&job->base.s_fence->finished);
229 amdgpu_job_free_resources(job);
230 drm_sched_entity_push_job(&job->base);
231
232 return f;
233}
234
235int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring,
236 struct dma_fence **fence)
237{
238 int r;
239
240 job->base.sched = &ring->sched;
241 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job, fence);
242
243 if (r)
244 return r;
245
246 amdgpu_job_free(job);
247 return 0;
248}
249
250static struct dma_fence *
251amdgpu_job_prepare_job(struct drm_sched_job *sched_job,
252 struct drm_sched_entity *s_entity)
253{
254 struct amdgpu_ring *ring = to_amdgpu_ring(s_entity->rq->sched);
255 struct amdgpu_job *job = to_amdgpu_job(sched_job);
256 struct dma_fence *fence = NULL;
257 int r;
258
259 if (!fence && job->gang_submit)
260 fence = amdgpu_device_switch_gang(ring->adev, job->gang_submit);
261
262 while (!fence && job->vm && !job->vmid) {
263 r = amdgpu_vmid_grab(job->vm, ring, job, &fence);
264 if (r)
265 DRM_ERROR("Error getting VM ID (%d)\n", r);
266 }
267
268 return fence;
269}
270
271static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
272{
273 struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched);
274 struct amdgpu_device *adev = ring->adev;
275 struct dma_fence *fence = NULL, *finished;
276 struct amdgpu_job *job;
277 int r = 0;
278
279 job = to_amdgpu_job(sched_job);
280 finished = &job->base.s_fence->finished;
281
282 trace_amdgpu_sched_run_job(job);
283
284 /* Skip job if VRAM is lost and never resubmit gangs */
285 if (job->vram_lost_counter != atomic_read(&adev->vram_lost_counter) ||
286 (job->job_run_counter && job->gang_submit))
287 dma_fence_set_error(finished, -ECANCELED);
288
289 if (finished->error < 0) {
290 DRM_INFO("Skip scheduling IBs!\n");
291 } else {
292 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job,
293 &fence);
294 if (r)
295 DRM_ERROR("Error scheduling IBs (%d)\n", r);
296 }
297
298 job->job_run_counter++;
299 amdgpu_job_free_resources(job);
300
301 fence = r ? ERR_PTR(r) : fence;
302 return fence;
303}
304
305#define to_drm_sched_job(sched_job) \
306 container_of((sched_job), struct drm_sched_job, queue_node)
307
308void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched)
309{
310 struct drm_sched_job *s_job;
311 struct drm_sched_entity *s_entity = NULL;
312 int i;
313
314 /* Signal all jobs not yet scheduled */
315 for (i = DRM_SCHED_PRIORITY_COUNT - 1; i >= DRM_SCHED_PRIORITY_MIN; i--) {
316 struct drm_sched_rq *rq = &sched->sched_rq[i];
317 spin_lock(&rq->lock);
318 list_for_each_entry(s_entity, &rq->entities, list) {
319 while ((s_job = to_drm_sched_job(spsc_queue_pop(&s_entity->job_queue)))) {
320 struct drm_sched_fence *s_fence = s_job->s_fence;
321
322 dma_fence_signal(&s_fence->scheduled);
323 dma_fence_set_error(&s_fence->finished, -EHWPOISON);
324 dma_fence_signal(&s_fence->finished);
325 }
326 }
327 spin_unlock(&rq->lock);
328 }
329
330 /* Signal all jobs already scheduled to HW */
331 list_for_each_entry(s_job, &sched->pending_list, list) {
332 struct drm_sched_fence *s_fence = s_job->s_fence;
333
334 dma_fence_set_error(&s_fence->finished, -EHWPOISON);
335 dma_fence_signal(&s_fence->finished);
336 }
337}
338
339const struct drm_sched_backend_ops amdgpu_sched_ops = {
340 .prepare_job = amdgpu_job_prepare_job,
341 .run_job = amdgpu_job_run,
342 .timedout_job = amdgpu_job_timedout,
343 .free_job = amdgpu_job_free_cb
344};