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1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24#include <linux/kthread.h>
25#include <linux/wait.h>
26#include <linux/sched.h>
27#include <drm/drmP.h>
28#include "amdgpu.h"
29#include "amdgpu_trace.h"
30
31static void amdgpu_job_timedout(struct drm_sched_job *s_job)
32{
33 struct amdgpu_job *job = container_of(s_job, struct amdgpu_job, base);
34
35 DRM_ERROR("ring %s timeout, last signaled seq=%u, last emitted seq=%u\n",
36 job->base.sched->name,
37 atomic_read(&job->ring->fence_drv.last_seq),
38 job->ring->fence_drv.sync_seq);
39
40 amdgpu_device_gpu_recover(job->adev, job, false);
41}
42
43int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
44 struct amdgpu_job **job, struct amdgpu_vm *vm)
45{
46 size_t size = sizeof(struct amdgpu_job);
47
48 if (num_ibs == 0)
49 return -EINVAL;
50
51 size += sizeof(struct amdgpu_ib) * num_ibs;
52
53 *job = kzalloc(size, GFP_KERNEL);
54 if (!*job)
55 return -ENOMEM;
56
57 (*job)->adev = adev;
58 (*job)->vm = vm;
59 (*job)->ibs = (void *)&(*job)[1];
60 (*job)->num_ibs = num_ibs;
61
62 amdgpu_sync_create(&(*job)->sync);
63 amdgpu_sync_create(&(*job)->sched_sync);
64 (*job)->vram_lost_counter = atomic_read(&adev->vram_lost_counter);
65
66 return 0;
67}
68
69int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
70 struct amdgpu_job **job)
71{
72 int r;
73
74 r = amdgpu_job_alloc(adev, 1, job, NULL);
75 if (r)
76 return r;
77
78 r = amdgpu_ib_get(adev, NULL, size, &(*job)->ibs[0]);
79 if (r)
80 kfree(*job);
81 else
82 (*job)->vm_pd_addr = adev->gart.table_addr;
83
84 return r;
85}
86
87void amdgpu_job_free_resources(struct amdgpu_job *job)
88{
89 struct dma_fence *f;
90 unsigned i;
91
92 /* use sched fence if available */
93 f = job->base.s_fence ? &job->base.s_fence->finished : job->fence;
94
95 for (i = 0; i < job->num_ibs; ++i)
96 amdgpu_ib_free(job->adev, &job->ibs[i], f);
97}
98
99static void amdgpu_job_free_cb(struct drm_sched_job *s_job)
100{
101 struct amdgpu_job *job = container_of(s_job, struct amdgpu_job, base);
102
103 amdgpu_ring_priority_put(job->ring, s_job->s_priority);
104 dma_fence_put(job->fence);
105 amdgpu_sync_free(&job->sync);
106 amdgpu_sync_free(&job->sched_sync);
107 kfree(job);
108}
109
110void amdgpu_job_free(struct amdgpu_job *job)
111{
112 amdgpu_job_free_resources(job);
113
114 dma_fence_put(job->fence);
115 amdgpu_sync_free(&job->sync);
116 amdgpu_sync_free(&job->sched_sync);
117 kfree(job);
118}
119
120int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
121 struct drm_sched_entity *entity, void *owner,
122 struct dma_fence **f)
123{
124 int r;
125 job->ring = ring;
126
127 if (!f)
128 return -EINVAL;
129
130 r = drm_sched_job_init(&job->base, &ring->sched, entity, owner);
131 if (r)
132 return r;
133
134 job->owner = owner;
135 job->fence_ctx = entity->fence_context;
136 *f = dma_fence_get(&job->base.s_fence->finished);
137 amdgpu_job_free_resources(job);
138 amdgpu_ring_priority_get(job->ring, job->base.s_priority);
139 drm_sched_entity_push_job(&job->base, entity);
140
141 return 0;
142}
143
144static struct dma_fence *amdgpu_job_dependency(struct drm_sched_job *sched_job,
145 struct drm_sched_entity *s_entity)
146{
147 struct amdgpu_job *job = to_amdgpu_job(sched_job);
148 struct amdgpu_vm *vm = job->vm;
149 bool explicit = false;
150 int r;
151 struct dma_fence *fence = amdgpu_sync_get_fence(&job->sync, &explicit);
152
153 if (fence && explicit) {
154 if (drm_sched_dependency_optimized(fence, s_entity)) {
155 r = amdgpu_sync_fence(job->adev, &job->sched_sync, fence, false);
156 if (r)
157 DRM_ERROR("Error adding fence to sync (%d)\n", r);
158 }
159 }
160
161 while (fence == NULL && vm && !job->vmid) {
162 struct amdgpu_ring *ring = job->ring;
163
164 r = amdgpu_vmid_grab(vm, ring, &job->sync,
165 &job->base.s_fence->finished,
166 job);
167 if (r)
168 DRM_ERROR("Error getting VM ID (%d)\n", r);
169
170 fence = amdgpu_sync_get_fence(&job->sync, NULL);
171 }
172
173 return fence;
174}
175
176static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
177{
178 struct dma_fence *fence = NULL, *finished;
179 struct amdgpu_device *adev;
180 struct amdgpu_job *job;
181 int r;
182
183 if (!sched_job) {
184 DRM_ERROR("job is null\n");
185 return NULL;
186 }
187 job = to_amdgpu_job(sched_job);
188 finished = &job->base.s_fence->finished;
189 adev = job->adev;
190
191 BUG_ON(amdgpu_sync_peek_fence(&job->sync, NULL));
192
193 trace_amdgpu_sched_run_job(job);
194
195 if (job->vram_lost_counter != atomic_read(&adev->vram_lost_counter))
196 dma_fence_set_error(finished, -ECANCELED);/* skip IB as well if VRAM lost */
197
198 if (finished->error < 0) {
199 DRM_INFO("Skip scheduling IBs!\n");
200 } else {
201 r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs, job,
202 &fence);
203 if (r)
204 DRM_ERROR("Error scheduling IBs (%d)\n", r);
205 }
206 /* if gpu reset, hw fence will be replaced here */
207 dma_fence_put(job->fence);
208 job->fence = dma_fence_get(fence);
209
210 amdgpu_job_free_resources(job);
211 return fence;
212}
213
214const struct drm_sched_backend_ops amdgpu_sched_ops = {
215 .dependency = amdgpu_job_dependency,
216 .run_job = amdgpu_job_run,
217 .timedout_job = amdgpu_job_timedout,
218 .free_job = amdgpu_job_free_cb
219};
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 *
23 */
24#include <linux/kthread.h>
25#include <linux/wait.h>
26#include <linux/sched.h>
27
28#include <drm/drm_drv.h>
29
30#include "amdgpu.h"
31#include "amdgpu_trace.h"
32
33static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job)
34{
35 struct amdgpu_ring *ring = to_amdgpu_ring(s_job->sched);
36 struct amdgpu_job *job = to_amdgpu_job(s_job);
37 struct amdgpu_task_info ti;
38 struct amdgpu_device *adev = ring->adev;
39 int idx;
40
41 if (!drm_dev_enter(&adev->ddev, &idx)) {
42 DRM_INFO("%s - device unplugged skipping recovery on scheduler:%s",
43 __func__, s_job->sched->name);
44
45 /* Effectively the job is aborted as the device is gone */
46 return DRM_GPU_SCHED_STAT_ENODEV;
47 }
48
49 memset(&ti, 0, sizeof(struct amdgpu_task_info));
50
51 if (amdgpu_gpu_recovery &&
52 amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) {
53 DRM_ERROR("ring %s timeout, but soft recovered\n",
54 s_job->sched->name);
55 goto exit;
56 }
57
58 amdgpu_vm_get_task_info(ring->adev, job->pasid, &ti);
59 DRM_ERROR("ring %s timeout, signaled seq=%u, emitted seq=%u\n",
60 job->base.sched->name, atomic_read(&ring->fence_drv.last_seq),
61 ring->fence_drv.sync_seq);
62 DRM_ERROR("Process information: process %s pid %d thread %s pid %d\n",
63 ti.process_name, ti.tgid, ti.task_name, ti.pid);
64
65 if (amdgpu_device_should_recover_gpu(ring->adev)) {
66 amdgpu_device_gpu_recover(ring->adev, job);
67 } else {
68 drm_sched_suspend_timeout(&ring->sched);
69 if (amdgpu_sriov_vf(adev))
70 adev->virt.tdr_debug = true;
71 }
72
73exit:
74 drm_dev_exit(idx);
75 return DRM_GPU_SCHED_STAT_NOMINAL;
76}
77
78int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
79 struct amdgpu_job **job, struct amdgpu_vm *vm)
80{
81 size_t size = sizeof(struct amdgpu_job);
82
83 if (num_ibs == 0)
84 return -EINVAL;
85
86 size += sizeof(struct amdgpu_ib) * num_ibs;
87
88 *job = kzalloc(size, GFP_KERNEL);
89 if (!*job)
90 return -ENOMEM;
91
92 /*
93 * Initialize the scheduler to at least some ring so that we always
94 * have a pointer to adev.
95 */
96 (*job)->base.sched = &adev->rings[0]->sched;
97 (*job)->vm = vm;
98 (*job)->ibs = (void *)&(*job)[1];
99 (*job)->num_ibs = num_ibs;
100
101 amdgpu_sync_create(&(*job)->sync);
102 amdgpu_sync_create(&(*job)->sched_sync);
103 (*job)->vram_lost_counter = atomic_read(&adev->vram_lost_counter);
104 (*job)->vm_pd_addr = AMDGPU_BO_INVALID_OFFSET;
105
106 return 0;
107}
108
109int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
110 enum amdgpu_ib_pool_type pool_type,
111 struct amdgpu_job **job)
112{
113 int r;
114
115 r = amdgpu_job_alloc(adev, 1, job, NULL);
116 if (r)
117 return r;
118
119 r = amdgpu_ib_get(adev, NULL, size, pool_type, &(*job)->ibs[0]);
120 if (r)
121 kfree(*job);
122
123 return r;
124}
125
126void amdgpu_job_free_resources(struct amdgpu_job *job)
127{
128 struct amdgpu_ring *ring = to_amdgpu_ring(job->base.sched);
129 struct dma_fence *f;
130 unsigned i;
131
132 /* use sched fence if available */
133 f = job->base.s_fence ? &job->base.s_fence->finished : job->fence;
134
135 for (i = 0; i < job->num_ibs; ++i)
136 amdgpu_ib_free(ring->adev, &job->ibs[i], f);
137}
138
139static void amdgpu_job_free_cb(struct drm_sched_job *s_job)
140{
141 struct amdgpu_job *job = to_amdgpu_job(s_job);
142
143 drm_sched_job_cleanup(s_job);
144
145 dma_fence_put(job->fence);
146 amdgpu_sync_free(&job->sync);
147 amdgpu_sync_free(&job->sched_sync);
148 kfree(job);
149}
150
151void amdgpu_job_free(struct amdgpu_job *job)
152{
153 amdgpu_job_free_resources(job);
154
155 dma_fence_put(job->fence);
156 amdgpu_sync_free(&job->sync);
157 amdgpu_sync_free(&job->sched_sync);
158 kfree(job);
159}
160
161int amdgpu_job_submit(struct amdgpu_job *job, struct drm_sched_entity *entity,
162 void *owner, struct dma_fence **f)
163{
164 int r;
165
166 if (!f)
167 return -EINVAL;
168
169 r = drm_sched_job_init(&job->base, entity, owner);
170 if (r)
171 return r;
172
173 *f = dma_fence_get(&job->base.s_fence->finished);
174 amdgpu_job_free_resources(job);
175 drm_sched_entity_push_job(&job->base, entity);
176
177 return 0;
178}
179
180int amdgpu_job_submit_direct(struct amdgpu_job *job, struct amdgpu_ring *ring,
181 struct dma_fence **fence)
182{
183 int r;
184
185 job->base.sched = &ring->sched;
186 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, NULL, fence);
187 job->fence = dma_fence_get(*fence);
188 if (r)
189 return r;
190
191 amdgpu_job_free(job);
192 return 0;
193}
194
195static struct dma_fence *amdgpu_job_dependency(struct drm_sched_job *sched_job,
196 struct drm_sched_entity *s_entity)
197{
198 struct amdgpu_ring *ring = to_amdgpu_ring(s_entity->rq->sched);
199 struct amdgpu_job *job = to_amdgpu_job(sched_job);
200 struct amdgpu_vm *vm = job->vm;
201 struct dma_fence *fence;
202 int r;
203
204 fence = amdgpu_sync_get_fence(&job->sync);
205 if (fence && drm_sched_dependency_optimized(fence, s_entity)) {
206 r = amdgpu_sync_fence(&job->sched_sync, fence);
207 if (r)
208 DRM_ERROR("Error adding fence (%d)\n", r);
209 }
210
211 while (fence == NULL && vm && !job->vmid) {
212 r = amdgpu_vmid_grab(vm, ring, &job->sync,
213 &job->base.s_fence->finished,
214 job);
215 if (r)
216 DRM_ERROR("Error getting VM ID (%d)\n", r);
217
218 fence = amdgpu_sync_get_fence(&job->sync);
219 }
220
221 return fence;
222}
223
224static struct dma_fence *amdgpu_job_run(struct drm_sched_job *sched_job)
225{
226 struct amdgpu_ring *ring = to_amdgpu_ring(sched_job->sched);
227 struct dma_fence *fence = NULL, *finished;
228 struct amdgpu_job *job;
229 int r = 0;
230
231 job = to_amdgpu_job(sched_job);
232 finished = &job->base.s_fence->finished;
233
234 BUG_ON(amdgpu_sync_peek_fence(&job->sync, NULL));
235
236 trace_amdgpu_sched_run_job(job);
237
238 if (job->vram_lost_counter != atomic_read(&ring->adev->vram_lost_counter))
239 dma_fence_set_error(finished, -ECANCELED);/* skip IB as well if VRAM lost */
240
241 if (finished->error < 0) {
242 DRM_INFO("Skip scheduling IBs!\n");
243 } else {
244 r = amdgpu_ib_schedule(ring, job->num_ibs, job->ibs, job,
245 &fence);
246 if (r)
247 DRM_ERROR("Error scheduling IBs (%d)\n", r);
248 }
249 /* if gpu reset, hw fence will be replaced here */
250 dma_fence_put(job->fence);
251 job->fence = dma_fence_get(fence);
252
253 amdgpu_job_free_resources(job);
254
255 fence = r ? ERR_PTR(r) : fence;
256 return fence;
257}
258
259#define to_drm_sched_job(sched_job) \
260 container_of((sched_job), struct drm_sched_job, queue_node)
261
262void amdgpu_job_stop_all_jobs_on_sched(struct drm_gpu_scheduler *sched)
263{
264 struct drm_sched_job *s_job;
265 struct drm_sched_entity *s_entity = NULL;
266 int i;
267
268 /* Signal all jobs not yet scheduled */
269 for (i = DRM_SCHED_PRIORITY_COUNT - 1; i >= DRM_SCHED_PRIORITY_MIN; i--) {
270 struct drm_sched_rq *rq = &sched->sched_rq[i];
271
272 if (!rq)
273 continue;
274
275 spin_lock(&rq->lock);
276 list_for_each_entry(s_entity, &rq->entities, list) {
277 while ((s_job = to_drm_sched_job(spsc_queue_pop(&s_entity->job_queue)))) {
278 struct drm_sched_fence *s_fence = s_job->s_fence;
279
280 dma_fence_signal(&s_fence->scheduled);
281 dma_fence_set_error(&s_fence->finished, -EHWPOISON);
282 dma_fence_signal(&s_fence->finished);
283 }
284 }
285 spin_unlock(&rq->lock);
286 }
287
288 /* Signal all jobs already scheduled to HW */
289 list_for_each_entry(s_job, &sched->pending_list, list) {
290 struct drm_sched_fence *s_fence = s_job->s_fence;
291
292 dma_fence_set_error(&s_fence->finished, -EHWPOISON);
293 dma_fence_signal(&s_fence->finished);
294 }
295}
296
297const struct drm_sched_backend_ops amdgpu_sched_ops = {
298 .dependency = amdgpu_job_dependency,
299 .run_job = amdgpu_job_run,
300 .timedout_job = amdgpu_job_timedout,
301 .free_job = amdgpu_job_free_cb
302};