Loading...
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 *
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 */
18#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19#define SUPPORT_SYSRQ
20#endif
21
22#undef DEBUG
23
24#include <linux/clk.h>
25#include <linux/console.h>
26#include <linux/ctype.h>
27#include <linux/cpufreq.h>
28#include <linux/delay.h>
29#include <linux/dmaengine.h>
30#include <linux/dma-mapping.h>
31#include <linux/err.h>
32#include <linux/errno.h>
33#include <linux/init.h>
34#include <linux/interrupt.h>
35#include <linux/ioport.h>
36#include <linux/ktime.h>
37#include <linux/major.h>
38#include <linux/module.h>
39#include <linux/mm.h>
40#include <linux/of.h>
41#include <linux/of_device.h>
42#include <linux/platform_device.h>
43#include <linux/pm_runtime.h>
44#include <linux/scatterlist.h>
45#include <linux/serial.h>
46#include <linux/serial_sci.h>
47#include <linux/sh_dma.h>
48#include <linux/slab.h>
49#include <linux/string.h>
50#include <linux/sysrq.h>
51#include <linux/timer.h>
52#include <linux/tty.h>
53#include <linux/tty_flip.h>
54
55#ifdef CONFIG_SUPERH
56#include <asm/sh_bios.h>
57#endif
58
59#include "serial_mctrl_gpio.h"
60#include "sh-sci.h"
61
62/* Offsets into the sci_port->irqs array */
63enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73#define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
79enum SCI_CLKS {
80 SCI_FCK, /* Functional Clock */
81 SCI_SCK, /* Optional External Clock */
82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
84 SCI_NUM_CLKS
85};
86
87/* Bit x set means sampling rate x + 1 is supported */
88#define SCI_SR(x) BIT((x) - 1)
89#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
90
91#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
92 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
93 SCI_SR(19) | SCI_SR(27)
94
95#define min_sr(_port) ffs((_port)->sampling_rate_mask)
96#define max_sr(_port) fls((_port)->sampling_rate_mask)
97
98/* Iterate over all supported sampling rates, from high to low */
99#define for_each_sr(_sr, _port) \
100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
101 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
102
103struct plat_sci_reg {
104 u8 offset, size;
105};
106
107struct sci_port_params {
108 const struct plat_sci_reg regs[SCIx_NR_REGS];
109 unsigned int fifosize;
110 unsigned int overrun_reg;
111 unsigned int overrun_mask;
112 unsigned int sampling_rate_mask;
113 unsigned int error_mask;
114 unsigned int error_clear;
115};
116
117struct sci_port {
118 struct uart_port port;
119
120 /* Platform configuration */
121 const struct sci_port_params *params;
122 const struct plat_sci_port *cfg;
123 unsigned int sampling_rate_mask;
124 resource_size_t reg_size;
125 struct mctrl_gpios *gpios;
126
127 /* Clocks */
128 struct clk *clks[SCI_NUM_CLKS];
129 unsigned long clk_rates[SCI_NUM_CLKS];
130
131 int irqs[SCIx_NR_IRQS];
132 char *irqstr[SCIx_NR_IRQS];
133
134 struct dma_chan *chan_tx;
135 struct dma_chan *chan_rx;
136
137#ifdef CONFIG_SERIAL_SH_SCI_DMA
138 dma_cookie_t cookie_tx;
139 dma_cookie_t cookie_rx[2];
140 dma_cookie_t active_rx;
141 dma_addr_t tx_dma_addr;
142 unsigned int tx_dma_len;
143 struct scatterlist sg_rx[2];
144 void *rx_buf[2];
145 size_t buf_len_rx;
146 struct work_struct work_tx;
147 struct hrtimer rx_timer;
148 unsigned int rx_timeout; /* microseconds */
149#endif
150 unsigned int rx_frame;
151 int rx_trigger;
152 struct timer_list rx_fifo_timer;
153 int rx_fifo_timeout;
154 u16 hscif_tot;
155
156 bool has_rtscts;
157 bool autorts;
158};
159
160#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
161
162static struct sci_port sci_ports[SCI_NPORTS];
163static struct uart_driver sci_uart_driver;
164
165static inline struct sci_port *
166to_sci_port(struct uart_port *uart)
167{
168 return container_of(uart, struct sci_port, port);
169}
170
171static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
172 /*
173 * Common SCI definitions, dependent on the port's regshift
174 * value.
175 */
176 [SCIx_SCI_REGTYPE] = {
177 .regs = {
178 [SCSMR] = { 0x00, 8 },
179 [SCBRR] = { 0x01, 8 },
180 [SCSCR] = { 0x02, 8 },
181 [SCxTDR] = { 0x03, 8 },
182 [SCxSR] = { 0x04, 8 },
183 [SCxRDR] = { 0x05, 8 },
184 },
185 .fifosize = 1,
186 .overrun_reg = SCxSR,
187 .overrun_mask = SCI_ORER,
188 .sampling_rate_mask = SCI_SR(32),
189 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
190 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
191 },
192
193 /*
194 * Common definitions for legacy IrDA ports.
195 */
196 [SCIx_IRDA_REGTYPE] = {
197 .regs = {
198 [SCSMR] = { 0x00, 8 },
199 [SCBRR] = { 0x02, 8 },
200 [SCSCR] = { 0x04, 8 },
201 [SCxTDR] = { 0x06, 8 },
202 [SCxSR] = { 0x08, 16 },
203 [SCxRDR] = { 0x0a, 8 },
204 [SCFCR] = { 0x0c, 8 },
205 [SCFDR] = { 0x0e, 16 },
206 },
207 .fifosize = 1,
208 .overrun_reg = SCxSR,
209 .overrun_mask = SCI_ORER,
210 .sampling_rate_mask = SCI_SR(32),
211 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
212 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
213 },
214
215 /*
216 * Common SCIFA definitions.
217 */
218 [SCIx_SCIFA_REGTYPE] = {
219 .regs = {
220 [SCSMR] = { 0x00, 16 },
221 [SCBRR] = { 0x04, 8 },
222 [SCSCR] = { 0x08, 16 },
223 [SCxTDR] = { 0x20, 8 },
224 [SCxSR] = { 0x14, 16 },
225 [SCxRDR] = { 0x24, 8 },
226 [SCFCR] = { 0x18, 16 },
227 [SCFDR] = { 0x1c, 16 },
228 [SCPCR] = { 0x30, 16 },
229 [SCPDR] = { 0x34, 16 },
230 },
231 .fifosize = 64,
232 .overrun_reg = SCxSR,
233 .overrun_mask = SCIFA_ORER,
234 .sampling_rate_mask = SCI_SR_SCIFAB,
235 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
236 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
237 },
238
239 /*
240 * Common SCIFB definitions.
241 */
242 [SCIx_SCIFB_REGTYPE] = {
243 .regs = {
244 [SCSMR] = { 0x00, 16 },
245 [SCBRR] = { 0x04, 8 },
246 [SCSCR] = { 0x08, 16 },
247 [SCxTDR] = { 0x40, 8 },
248 [SCxSR] = { 0x14, 16 },
249 [SCxRDR] = { 0x60, 8 },
250 [SCFCR] = { 0x18, 16 },
251 [SCTFDR] = { 0x38, 16 },
252 [SCRFDR] = { 0x3c, 16 },
253 [SCPCR] = { 0x30, 16 },
254 [SCPDR] = { 0x34, 16 },
255 },
256 .fifosize = 256,
257 .overrun_reg = SCxSR,
258 .overrun_mask = SCIFA_ORER,
259 .sampling_rate_mask = SCI_SR_SCIFAB,
260 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
261 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
262 },
263
264 /*
265 * Common SH-2(A) SCIF definitions for ports with FIFO data
266 * count registers.
267 */
268 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
269 .regs = {
270 [SCSMR] = { 0x00, 16 },
271 [SCBRR] = { 0x04, 8 },
272 [SCSCR] = { 0x08, 16 },
273 [SCxTDR] = { 0x0c, 8 },
274 [SCxSR] = { 0x10, 16 },
275 [SCxRDR] = { 0x14, 8 },
276 [SCFCR] = { 0x18, 16 },
277 [SCFDR] = { 0x1c, 16 },
278 [SCSPTR] = { 0x20, 16 },
279 [SCLSR] = { 0x24, 16 },
280 },
281 .fifosize = 16,
282 .overrun_reg = SCLSR,
283 .overrun_mask = SCLSR_ORER,
284 .sampling_rate_mask = SCI_SR(32),
285 .error_mask = SCIF_DEFAULT_ERROR_MASK,
286 .error_clear = SCIF_ERROR_CLEAR,
287 },
288
289 /*
290 * Common SH-3 SCIF definitions.
291 */
292 [SCIx_SH3_SCIF_REGTYPE] = {
293 .regs = {
294 [SCSMR] = { 0x00, 8 },
295 [SCBRR] = { 0x02, 8 },
296 [SCSCR] = { 0x04, 8 },
297 [SCxTDR] = { 0x06, 8 },
298 [SCxSR] = { 0x08, 16 },
299 [SCxRDR] = { 0x0a, 8 },
300 [SCFCR] = { 0x0c, 8 },
301 [SCFDR] = { 0x0e, 16 },
302 },
303 .fifosize = 16,
304 .overrun_reg = SCLSR,
305 .overrun_mask = SCLSR_ORER,
306 .sampling_rate_mask = SCI_SR(32),
307 .error_mask = SCIF_DEFAULT_ERROR_MASK,
308 .error_clear = SCIF_ERROR_CLEAR,
309 },
310
311 /*
312 * Common SH-4(A) SCIF(B) definitions.
313 */
314 [SCIx_SH4_SCIF_REGTYPE] = {
315 .regs = {
316 [SCSMR] = { 0x00, 16 },
317 [SCBRR] = { 0x04, 8 },
318 [SCSCR] = { 0x08, 16 },
319 [SCxTDR] = { 0x0c, 8 },
320 [SCxSR] = { 0x10, 16 },
321 [SCxRDR] = { 0x14, 8 },
322 [SCFCR] = { 0x18, 16 },
323 [SCFDR] = { 0x1c, 16 },
324 [SCSPTR] = { 0x20, 16 },
325 [SCLSR] = { 0x24, 16 },
326 },
327 .fifosize = 16,
328 .overrun_reg = SCLSR,
329 .overrun_mask = SCLSR_ORER,
330 .sampling_rate_mask = SCI_SR(32),
331 .error_mask = SCIF_DEFAULT_ERROR_MASK,
332 .error_clear = SCIF_ERROR_CLEAR,
333 },
334
335 /*
336 * Common SCIF definitions for ports with a Baud Rate Generator for
337 * External Clock (BRG).
338 */
339 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
340 .regs = {
341 [SCSMR] = { 0x00, 16 },
342 [SCBRR] = { 0x04, 8 },
343 [SCSCR] = { 0x08, 16 },
344 [SCxTDR] = { 0x0c, 8 },
345 [SCxSR] = { 0x10, 16 },
346 [SCxRDR] = { 0x14, 8 },
347 [SCFCR] = { 0x18, 16 },
348 [SCFDR] = { 0x1c, 16 },
349 [SCSPTR] = { 0x20, 16 },
350 [SCLSR] = { 0x24, 16 },
351 [SCDL] = { 0x30, 16 },
352 [SCCKS] = { 0x34, 16 },
353 },
354 .fifosize = 16,
355 .overrun_reg = SCLSR,
356 .overrun_mask = SCLSR_ORER,
357 .sampling_rate_mask = SCI_SR(32),
358 .error_mask = SCIF_DEFAULT_ERROR_MASK,
359 .error_clear = SCIF_ERROR_CLEAR,
360 },
361
362 /*
363 * Common HSCIF definitions.
364 */
365 [SCIx_HSCIF_REGTYPE] = {
366 .regs = {
367 [SCSMR] = { 0x00, 16 },
368 [SCBRR] = { 0x04, 8 },
369 [SCSCR] = { 0x08, 16 },
370 [SCxTDR] = { 0x0c, 8 },
371 [SCxSR] = { 0x10, 16 },
372 [SCxRDR] = { 0x14, 8 },
373 [SCFCR] = { 0x18, 16 },
374 [SCFDR] = { 0x1c, 16 },
375 [SCSPTR] = { 0x20, 16 },
376 [SCLSR] = { 0x24, 16 },
377 [HSSRR] = { 0x40, 16 },
378 [SCDL] = { 0x30, 16 },
379 [SCCKS] = { 0x34, 16 },
380 [HSRTRGR] = { 0x54, 16 },
381 [HSTTRGR] = { 0x58, 16 },
382 },
383 .fifosize = 128,
384 .overrun_reg = SCLSR,
385 .overrun_mask = SCLSR_ORER,
386 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
387 .error_mask = SCIF_DEFAULT_ERROR_MASK,
388 .error_clear = SCIF_ERROR_CLEAR,
389 },
390
391 /*
392 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
393 * register.
394 */
395 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
396 .regs = {
397 [SCSMR] = { 0x00, 16 },
398 [SCBRR] = { 0x04, 8 },
399 [SCSCR] = { 0x08, 16 },
400 [SCxTDR] = { 0x0c, 8 },
401 [SCxSR] = { 0x10, 16 },
402 [SCxRDR] = { 0x14, 8 },
403 [SCFCR] = { 0x18, 16 },
404 [SCFDR] = { 0x1c, 16 },
405 [SCLSR] = { 0x24, 16 },
406 },
407 .fifosize = 16,
408 .overrun_reg = SCLSR,
409 .overrun_mask = SCLSR_ORER,
410 .sampling_rate_mask = SCI_SR(32),
411 .error_mask = SCIF_DEFAULT_ERROR_MASK,
412 .error_clear = SCIF_ERROR_CLEAR,
413 },
414
415 /*
416 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
417 * count registers.
418 */
419 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
420 .regs = {
421 [SCSMR] = { 0x00, 16 },
422 [SCBRR] = { 0x04, 8 },
423 [SCSCR] = { 0x08, 16 },
424 [SCxTDR] = { 0x0c, 8 },
425 [SCxSR] = { 0x10, 16 },
426 [SCxRDR] = { 0x14, 8 },
427 [SCFCR] = { 0x18, 16 },
428 [SCFDR] = { 0x1c, 16 },
429 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
430 [SCRFDR] = { 0x20, 16 },
431 [SCSPTR] = { 0x24, 16 },
432 [SCLSR] = { 0x28, 16 },
433 },
434 .fifosize = 16,
435 .overrun_reg = SCLSR,
436 .overrun_mask = SCLSR_ORER,
437 .sampling_rate_mask = SCI_SR(32),
438 .error_mask = SCIF_DEFAULT_ERROR_MASK,
439 .error_clear = SCIF_ERROR_CLEAR,
440 },
441
442 /*
443 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
444 * registers.
445 */
446 [SCIx_SH7705_SCIF_REGTYPE] = {
447 .regs = {
448 [SCSMR] = { 0x00, 16 },
449 [SCBRR] = { 0x04, 8 },
450 [SCSCR] = { 0x08, 16 },
451 [SCxTDR] = { 0x20, 8 },
452 [SCxSR] = { 0x14, 16 },
453 [SCxRDR] = { 0x24, 8 },
454 [SCFCR] = { 0x18, 16 },
455 [SCFDR] = { 0x1c, 16 },
456 },
457 .fifosize = 64,
458 .overrun_reg = SCxSR,
459 .overrun_mask = SCIFA_ORER,
460 .sampling_rate_mask = SCI_SR(16),
461 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
462 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
463 },
464};
465
466#define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
467
468/*
469 * The "offset" here is rather misleading, in that it refers to an enum
470 * value relative to the port mapping rather than the fixed offset
471 * itself, which needs to be manually retrieved from the platform's
472 * register map for the given port.
473 */
474static unsigned int sci_serial_in(struct uart_port *p, int offset)
475{
476 const struct plat_sci_reg *reg = sci_getreg(p, offset);
477
478 if (reg->size == 8)
479 return ioread8(p->membase + (reg->offset << p->regshift));
480 else if (reg->size == 16)
481 return ioread16(p->membase + (reg->offset << p->regshift));
482 else
483 WARN(1, "Invalid register access\n");
484
485 return 0;
486}
487
488static void sci_serial_out(struct uart_port *p, int offset, int value)
489{
490 const struct plat_sci_reg *reg = sci_getreg(p, offset);
491
492 if (reg->size == 8)
493 iowrite8(value, p->membase + (reg->offset << p->regshift));
494 else if (reg->size == 16)
495 iowrite16(value, p->membase + (reg->offset << p->regshift));
496 else
497 WARN(1, "Invalid register access\n");
498}
499
500static void sci_port_enable(struct sci_port *sci_port)
501{
502 unsigned int i;
503
504 if (!sci_port->port.dev)
505 return;
506
507 pm_runtime_get_sync(sci_port->port.dev);
508
509 for (i = 0; i < SCI_NUM_CLKS; i++) {
510 clk_prepare_enable(sci_port->clks[i]);
511 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
512 }
513 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
514}
515
516static void sci_port_disable(struct sci_port *sci_port)
517{
518 unsigned int i;
519
520 if (!sci_port->port.dev)
521 return;
522
523 for (i = SCI_NUM_CLKS; i-- > 0; )
524 clk_disable_unprepare(sci_port->clks[i]);
525
526 pm_runtime_put_sync(sci_port->port.dev);
527}
528
529static inline unsigned long port_rx_irq_mask(struct uart_port *port)
530{
531 /*
532 * Not all ports (such as SCIFA) will support REIE. Rather than
533 * special-casing the port type, we check the port initialization
534 * IRQ enable mask to see whether the IRQ is desired at all. If
535 * it's unset, it's logically inferred that there's no point in
536 * testing for it.
537 */
538 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
539}
540
541static void sci_start_tx(struct uart_port *port)
542{
543 struct sci_port *s = to_sci_port(port);
544 unsigned short ctrl;
545
546#ifdef CONFIG_SERIAL_SH_SCI_DMA
547 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
548 u16 new, scr = serial_port_in(port, SCSCR);
549 if (s->chan_tx)
550 new = scr | SCSCR_TDRQE;
551 else
552 new = scr & ~SCSCR_TDRQE;
553 if (new != scr)
554 serial_port_out(port, SCSCR, new);
555 }
556
557 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
558 dma_submit_error(s->cookie_tx)) {
559 s->cookie_tx = 0;
560 schedule_work(&s->work_tx);
561 }
562#endif
563
564 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
565 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
566 ctrl = serial_port_in(port, SCSCR);
567 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
568 }
569}
570
571static void sci_stop_tx(struct uart_port *port)
572{
573 unsigned short ctrl;
574
575 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
576 ctrl = serial_port_in(port, SCSCR);
577
578 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
579 ctrl &= ~SCSCR_TDRQE;
580
581 ctrl &= ~SCSCR_TIE;
582
583 serial_port_out(port, SCSCR, ctrl);
584}
585
586static void sci_start_rx(struct uart_port *port)
587{
588 unsigned short ctrl;
589
590 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
591
592 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
593 ctrl &= ~SCSCR_RDRQE;
594
595 serial_port_out(port, SCSCR, ctrl);
596}
597
598static void sci_stop_rx(struct uart_port *port)
599{
600 unsigned short ctrl;
601
602 ctrl = serial_port_in(port, SCSCR);
603
604 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
605 ctrl &= ~SCSCR_RDRQE;
606
607 ctrl &= ~port_rx_irq_mask(port);
608
609 serial_port_out(port, SCSCR, ctrl);
610}
611
612static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
613{
614 if (port->type == PORT_SCI) {
615 /* Just store the mask */
616 serial_port_out(port, SCxSR, mask);
617 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
618 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
619 /* Only clear the status bits we want to clear */
620 serial_port_out(port, SCxSR,
621 serial_port_in(port, SCxSR) & mask);
622 } else {
623 /* Store the mask, clear parity/framing errors */
624 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
625 }
626}
627
628#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
629 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
630
631#ifdef CONFIG_CONSOLE_POLL
632static int sci_poll_get_char(struct uart_port *port)
633{
634 unsigned short status;
635 int c;
636
637 do {
638 status = serial_port_in(port, SCxSR);
639 if (status & SCxSR_ERRORS(port)) {
640 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
641 continue;
642 }
643 break;
644 } while (1);
645
646 if (!(status & SCxSR_RDxF(port)))
647 return NO_POLL_CHAR;
648
649 c = serial_port_in(port, SCxRDR);
650
651 /* Dummy read */
652 serial_port_in(port, SCxSR);
653 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
654
655 return c;
656}
657#endif
658
659static void sci_poll_put_char(struct uart_port *port, unsigned char c)
660{
661 unsigned short status;
662
663 do {
664 status = serial_port_in(port, SCxSR);
665 } while (!(status & SCxSR_TDxE(port)));
666
667 serial_port_out(port, SCxTDR, c);
668 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
669}
670#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
671 CONFIG_SERIAL_SH_SCI_EARLYCON */
672
673static void sci_init_pins(struct uart_port *port, unsigned int cflag)
674{
675 struct sci_port *s = to_sci_port(port);
676
677 /*
678 * Use port-specific handler if provided.
679 */
680 if (s->cfg->ops && s->cfg->ops->init_pins) {
681 s->cfg->ops->init_pins(port, cflag);
682 return;
683 }
684
685 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
686 u16 data = serial_port_in(port, SCPDR);
687 u16 ctrl = serial_port_in(port, SCPCR);
688
689 /* Enable RXD and TXD pin functions */
690 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
691 if (to_sci_port(port)->has_rtscts) {
692 /* RTS# is output, active low, unless autorts */
693 if (!(port->mctrl & TIOCM_RTS)) {
694 ctrl |= SCPCR_RTSC;
695 data |= SCPDR_RTSD;
696 } else if (!s->autorts) {
697 ctrl |= SCPCR_RTSC;
698 data &= ~SCPDR_RTSD;
699 } else {
700 /* Enable RTS# pin function */
701 ctrl &= ~SCPCR_RTSC;
702 }
703 /* Enable CTS# pin function */
704 ctrl &= ~SCPCR_CTSC;
705 }
706 serial_port_out(port, SCPDR, data);
707 serial_port_out(port, SCPCR, ctrl);
708 } else if (sci_getreg(port, SCSPTR)->size) {
709 u16 status = serial_port_in(port, SCSPTR);
710
711 /* RTS# is always output; and active low, unless autorts */
712 status |= SCSPTR_RTSIO;
713 if (!(port->mctrl & TIOCM_RTS))
714 status |= SCSPTR_RTSDT;
715 else if (!s->autorts)
716 status &= ~SCSPTR_RTSDT;
717 /* CTS# and SCK are inputs */
718 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
719 serial_port_out(port, SCSPTR, status);
720 }
721}
722
723static int sci_txfill(struct uart_port *port)
724{
725 struct sci_port *s = to_sci_port(port);
726 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
727 const struct plat_sci_reg *reg;
728
729 reg = sci_getreg(port, SCTFDR);
730 if (reg->size)
731 return serial_port_in(port, SCTFDR) & fifo_mask;
732
733 reg = sci_getreg(port, SCFDR);
734 if (reg->size)
735 return serial_port_in(port, SCFDR) >> 8;
736
737 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
738}
739
740static int sci_txroom(struct uart_port *port)
741{
742 return port->fifosize - sci_txfill(port);
743}
744
745static int sci_rxfill(struct uart_port *port)
746{
747 struct sci_port *s = to_sci_port(port);
748 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
749 const struct plat_sci_reg *reg;
750
751 reg = sci_getreg(port, SCRFDR);
752 if (reg->size)
753 return serial_port_in(port, SCRFDR) & fifo_mask;
754
755 reg = sci_getreg(port, SCFDR);
756 if (reg->size)
757 return serial_port_in(port, SCFDR) & fifo_mask;
758
759 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
760}
761
762/* ********************************************************************** *
763 * the interrupt related routines *
764 * ********************************************************************** */
765
766static void sci_transmit_chars(struct uart_port *port)
767{
768 struct circ_buf *xmit = &port->state->xmit;
769 unsigned int stopped = uart_tx_stopped(port);
770 unsigned short status;
771 unsigned short ctrl;
772 int count;
773
774 status = serial_port_in(port, SCxSR);
775 if (!(status & SCxSR_TDxE(port))) {
776 ctrl = serial_port_in(port, SCSCR);
777 if (uart_circ_empty(xmit))
778 ctrl &= ~SCSCR_TIE;
779 else
780 ctrl |= SCSCR_TIE;
781 serial_port_out(port, SCSCR, ctrl);
782 return;
783 }
784
785 count = sci_txroom(port);
786
787 do {
788 unsigned char c;
789
790 if (port->x_char) {
791 c = port->x_char;
792 port->x_char = 0;
793 } else if (!uart_circ_empty(xmit) && !stopped) {
794 c = xmit->buf[xmit->tail];
795 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
796 } else {
797 break;
798 }
799
800 serial_port_out(port, SCxTDR, c);
801
802 port->icount.tx++;
803 } while (--count > 0);
804
805 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
806
807 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
808 uart_write_wakeup(port);
809 if (uart_circ_empty(xmit)) {
810 sci_stop_tx(port);
811 } else {
812 ctrl = serial_port_in(port, SCSCR);
813
814 if (port->type != PORT_SCI) {
815 serial_port_in(port, SCxSR); /* Dummy read */
816 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
817 }
818
819 ctrl |= SCSCR_TIE;
820 serial_port_out(port, SCSCR, ctrl);
821 }
822}
823
824/* On SH3, SCIF may read end-of-break as a space->mark char */
825#define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
826
827static void sci_receive_chars(struct uart_port *port)
828{
829 struct tty_port *tport = &port->state->port;
830 int i, count, copied = 0;
831 unsigned short status;
832 unsigned char flag;
833
834 status = serial_port_in(port, SCxSR);
835 if (!(status & SCxSR_RDxF(port)))
836 return;
837
838 while (1) {
839 /* Don't copy more bytes than there is room for in the buffer */
840 count = tty_buffer_request_room(tport, sci_rxfill(port));
841
842 /* If for any reason we can't copy more data, we're done! */
843 if (count == 0)
844 break;
845
846 if (port->type == PORT_SCI) {
847 char c = serial_port_in(port, SCxRDR);
848 if (uart_handle_sysrq_char(port, c))
849 count = 0;
850 else
851 tty_insert_flip_char(tport, c, TTY_NORMAL);
852 } else {
853 for (i = 0; i < count; i++) {
854 char c = serial_port_in(port, SCxRDR);
855
856 status = serial_port_in(port, SCxSR);
857 if (uart_handle_sysrq_char(port, c)) {
858 count--; i--;
859 continue;
860 }
861
862 /* Store data and status */
863 if (status & SCxSR_FER(port)) {
864 flag = TTY_FRAME;
865 port->icount.frame++;
866 dev_notice(port->dev, "frame error\n");
867 } else if (status & SCxSR_PER(port)) {
868 flag = TTY_PARITY;
869 port->icount.parity++;
870 dev_notice(port->dev, "parity error\n");
871 } else
872 flag = TTY_NORMAL;
873
874 tty_insert_flip_char(tport, c, flag);
875 }
876 }
877
878 serial_port_in(port, SCxSR); /* dummy read */
879 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
880
881 copied += count;
882 port->icount.rx += count;
883 }
884
885 if (copied) {
886 /* Tell the rest of the system the news. New characters! */
887 tty_flip_buffer_push(tport);
888 } else {
889 /* TTY buffers full; read from RX reg to prevent lockup */
890 serial_port_in(port, SCxRDR);
891 serial_port_in(port, SCxSR); /* dummy read */
892 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
893 }
894}
895
896static int sci_handle_errors(struct uart_port *port)
897{
898 int copied = 0;
899 unsigned short status = serial_port_in(port, SCxSR);
900 struct tty_port *tport = &port->state->port;
901 struct sci_port *s = to_sci_port(port);
902
903 /* Handle overruns */
904 if (status & s->params->overrun_mask) {
905 port->icount.overrun++;
906
907 /* overrun error */
908 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
909 copied++;
910
911 dev_notice(port->dev, "overrun error\n");
912 }
913
914 if (status & SCxSR_FER(port)) {
915 /* frame error */
916 port->icount.frame++;
917
918 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
919 copied++;
920
921 dev_notice(port->dev, "frame error\n");
922 }
923
924 if (status & SCxSR_PER(port)) {
925 /* parity error */
926 port->icount.parity++;
927
928 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
929 copied++;
930
931 dev_notice(port->dev, "parity error\n");
932 }
933
934 if (copied)
935 tty_flip_buffer_push(tport);
936
937 return copied;
938}
939
940static int sci_handle_fifo_overrun(struct uart_port *port)
941{
942 struct tty_port *tport = &port->state->port;
943 struct sci_port *s = to_sci_port(port);
944 const struct plat_sci_reg *reg;
945 int copied = 0;
946 u16 status;
947
948 reg = sci_getreg(port, s->params->overrun_reg);
949 if (!reg->size)
950 return 0;
951
952 status = serial_port_in(port, s->params->overrun_reg);
953 if (status & s->params->overrun_mask) {
954 status &= ~s->params->overrun_mask;
955 serial_port_out(port, s->params->overrun_reg, status);
956
957 port->icount.overrun++;
958
959 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
960 tty_flip_buffer_push(tport);
961
962 dev_dbg(port->dev, "overrun error\n");
963 copied++;
964 }
965
966 return copied;
967}
968
969static int sci_handle_breaks(struct uart_port *port)
970{
971 int copied = 0;
972 unsigned short status = serial_port_in(port, SCxSR);
973 struct tty_port *tport = &port->state->port;
974
975 if (uart_handle_break(port))
976 return 0;
977
978 if (status & SCxSR_BRK(port)) {
979 port->icount.brk++;
980
981 /* Notify of BREAK */
982 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
983 copied++;
984
985 dev_dbg(port->dev, "BREAK detected\n");
986 }
987
988 if (copied)
989 tty_flip_buffer_push(tport);
990
991 copied += sci_handle_fifo_overrun(port);
992
993 return copied;
994}
995
996static int scif_set_rtrg(struct uart_port *port, int rx_trig)
997{
998 unsigned int bits;
999
1000 if (rx_trig < 1)
1001 rx_trig = 1;
1002 if (rx_trig >= port->fifosize)
1003 rx_trig = port->fifosize;
1004
1005 /* HSCIF can be set to an arbitrary level. */
1006 if (sci_getreg(port, HSRTRGR)->size) {
1007 serial_port_out(port, HSRTRGR, rx_trig);
1008 return rx_trig;
1009 }
1010
1011 switch (port->type) {
1012 case PORT_SCIF:
1013 if (rx_trig < 4) {
1014 bits = 0;
1015 rx_trig = 1;
1016 } else if (rx_trig < 8) {
1017 bits = SCFCR_RTRG0;
1018 rx_trig = 4;
1019 } else if (rx_trig < 14) {
1020 bits = SCFCR_RTRG1;
1021 rx_trig = 8;
1022 } else {
1023 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1024 rx_trig = 14;
1025 }
1026 break;
1027 case PORT_SCIFA:
1028 case PORT_SCIFB:
1029 if (rx_trig < 16) {
1030 bits = 0;
1031 rx_trig = 1;
1032 } else if (rx_trig < 32) {
1033 bits = SCFCR_RTRG0;
1034 rx_trig = 16;
1035 } else if (rx_trig < 48) {
1036 bits = SCFCR_RTRG1;
1037 rx_trig = 32;
1038 } else {
1039 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1040 rx_trig = 48;
1041 }
1042 break;
1043 default:
1044 WARN(1, "unknown FIFO configuration");
1045 return 1;
1046 }
1047
1048 serial_port_out(port, SCFCR,
1049 (serial_port_in(port, SCFCR) &
1050 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1051
1052 return rx_trig;
1053}
1054
1055static int scif_rtrg_enabled(struct uart_port *port)
1056{
1057 if (sci_getreg(port, HSRTRGR)->size)
1058 return serial_port_in(port, HSRTRGR) != 0;
1059 else
1060 return (serial_port_in(port, SCFCR) &
1061 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1062}
1063
1064static void rx_fifo_timer_fn(struct timer_list *t)
1065{
1066 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
1067 struct uart_port *port = &s->port;
1068
1069 dev_dbg(port->dev, "Rx timed out\n");
1070 scif_set_rtrg(port, 1);
1071}
1072
1073static ssize_t rx_trigger_show(struct device *dev,
1074 struct device_attribute *attr,
1075 char *buf)
1076{
1077 struct uart_port *port = dev_get_drvdata(dev);
1078 struct sci_port *sci = to_sci_port(port);
1079
1080 return sprintf(buf, "%d\n", sci->rx_trigger);
1081}
1082
1083static ssize_t rx_trigger_store(struct device *dev,
1084 struct device_attribute *attr,
1085 const char *buf,
1086 size_t count)
1087{
1088 struct uart_port *port = dev_get_drvdata(dev);
1089 struct sci_port *sci = to_sci_port(port);
1090 int ret;
1091 long r;
1092
1093 ret = kstrtol(buf, 0, &r);
1094 if (ret)
1095 return ret;
1096
1097 sci->rx_trigger = scif_set_rtrg(port, r);
1098 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1099 scif_set_rtrg(port, 1);
1100
1101 return count;
1102}
1103
1104static DEVICE_ATTR(rx_fifo_trigger, 0644, rx_trigger_show, rx_trigger_store);
1105
1106static ssize_t rx_fifo_timeout_show(struct device *dev,
1107 struct device_attribute *attr,
1108 char *buf)
1109{
1110 struct uart_port *port = dev_get_drvdata(dev);
1111 struct sci_port *sci = to_sci_port(port);
1112 int v;
1113
1114 if (port->type == PORT_HSCIF)
1115 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1116 else
1117 v = sci->rx_fifo_timeout;
1118
1119 return sprintf(buf, "%d\n", v);
1120}
1121
1122static ssize_t rx_fifo_timeout_store(struct device *dev,
1123 struct device_attribute *attr,
1124 const char *buf,
1125 size_t count)
1126{
1127 struct uart_port *port = dev_get_drvdata(dev);
1128 struct sci_port *sci = to_sci_port(port);
1129 int ret;
1130 long r;
1131
1132 ret = kstrtol(buf, 0, &r);
1133 if (ret)
1134 return ret;
1135
1136 if (port->type == PORT_HSCIF) {
1137 if (r < 0 || r > 3)
1138 return -EINVAL;
1139 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1140 } else {
1141 sci->rx_fifo_timeout = r;
1142 scif_set_rtrg(port, 1);
1143 if (r > 0)
1144 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1145 }
1146
1147 return count;
1148}
1149
1150static DEVICE_ATTR_RW(rx_fifo_timeout);
1151
1152
1153#ifdef CONFIG_SERIAL_SH_SCI_DMA
1154static void sci_dma_tx_complete(void *arg)
1155{
1156 struct sci_port *s = arg;
1157 struct uart_port *port = &s->port;
1158 struct circ_buf *xmit = &port->state->xmit;
1159 unsigned long flags;
1160
1161 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1162
1163 spin_lock_irqsave(&port->lock, flags);
1164
1165 xmit->tail += s->tx_dma_len;
1166 xmit->tail &= UART_XMIT_SIZE - 1;
1167
1168 port->icount.tx += s->tx_dma_len;
1169
1170 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1171 uart_write_wakeup(port);
1172
1173 if (!uart_circ_empty(xmit)) {
1174 s->cookie_tx = 0;
1175 schedule_work(&s->work_tx);
1176 } else {
1177 s->cookie_tx = -EINVAL;
1178 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1179 u16 ctrl = serial_port_in(port, SCSCR);
1180 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1181 }
1182 }
1183
1184 spin_unlock_irqrestore(&port->lock, flags);
1185}
1186
1187/* Locking: called with port lock held */
1188static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1189{
1190 struct uart_port *port = &s->port;
1191 struct tty_port *tport = &port->state->port;
1192 int copied;
1193
1194 copied = tty_insert_flip_string(tport, buf, count);
1195 if (copied < count)
1196 port->icount.buf_overrun++;
1197
1198 port->icount.rx += copied;
1199
1200 return copied;
1201}
1202
1203static int sci_dma_rx_find_active(struct sci_port *s)
1204{
1205 unsigned int i;
1206
1207 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1208 if (s->active_rx == s->cookie_rx[i])
1209 return i;
1210
1211 return -1;
1212}
1213
1214static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1215{
1216 struct dma_chan *chan = s->chan_rx;
1217 struct uart_port *port = &s->port;
1218 unsigned long flags;
1219
1220 spin_lock_irqsave(&port->lock, flags);
1221 s->chan_rx = NULL;
1222 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1223 spin_unlock_irqrestore(&port->lock, flags);
1224 dmaengine_terminate_all(chan);
1225 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1226 sg_dma_address(&s->sg_rx[0]));
1227 dma_release_channel(chan);
1228 if (enable_pio) {
1229 spin_lock_irqsave(&port->lock, flags);
1230 sci_start_rx(port);
1231 spin_unlock_irqrestore(&port->lock, flags);
1232 }
1233}
1234
1235static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1236{
1237 long sec = usec / 1000000;
1238 long nsec = (usec % 1000000) * 1000;
1239 ktime_t t = ktime_set(sec, nsec);
1240
1241 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1242}
1243
1244static void sci_dma_rx_complete(void *arg)
1245{
1246 struct sci_port *s = arg;
1247 struct dma_chan *chan = s->chan_rx;
1248 struct uart_port *port = &s->port;
1249 struct dma_async_tx_descriptor *desc;
1250 unsigned long flags;
1251 int active, count = 0;
1252
1253 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1254 s->active_rx);
1255
1256 spin_lock_irqsave(&port->lock, flags);
1257
1258 active = sci_dma_rx_find_active(s);
1259 if (active >= 0)
1260 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1261
1262 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1263
1264 if (count)
1265 tty_flip_buffer_push(&port->state->port);
1266
1267 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1268 DMA_DEV_TO_MEM,
1269 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1270 if (!desc)
1271 goto fail;
1272
1273 desc->callback = sci_dma_rx_complete;
1274 desc->callback_param = s;
1275 s->cookie_rx[active] = dmaengine_submit(desc);
1276 if (dma_submit_error(s->cookie_rx[active]))
1277 goto fail;
1278
1279 s->active_rx = s->cookie_rx[!active];
1280
1281 dma_async_issue_pending(chan);
1282
1283 spin_unlock_irqrestore(&port->lock, flags);
1284 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1285 __func__, s->cookie_rx[active], active, s->active_rx);
1286 return;
1287
1288fail:
1289 spin_unlock_irqrestore(&port->lock, flags);
1290 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1291 sci_rx_dma_release(s, true);
1292}
1293
1294static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1295{
1296 struct dma_chan *chan = s->chan_tx;
1297 struct uart_port *port = &s->port;
1298 unsigned long flags;
1299
1300 spin_lock_irqsave(&port->lock, flags);
1301 s->chan_tx = NULL;
1302 s->cookie_tx = -EINVAL;
1303 spin_unlock_irqrestore(&port->lock, flags);
1304 dmaengine_terminate_all(chan);
1305 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1306 DMA_TO_DEVICE);
1307 dma_release_channel(chan);
1308 if (enable_pio) {
1309 spin_lock_irqsave(&port->lock, flags);
1310 sci_start_tx(port);
1311 spin_unlock_irqrestore(&port->lock, flags);
1312 }
1313}
1314
1315static void sci_submit_rx(struct sci_port *s)
1316{
1317 struct dma_chan *chan = s->chan_rx;
1318 int i;
1319
1320 for (i = 0; i < 2; i++) {
1321 struct scatterlist *sg = &s->sg_rx[i];
1322 struct dma_async_tx_descriptor *desc;
1323
1324 desc = dmaengine_prep_slave_sg(chan,
1325 sg, 1, DMA_DEV_TO_MEM,
1326 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1327 if (!desc)
1328 goto fail;
1329
1330 desc->callback = sci_dma_rx_complete;
1331 desc->callback_param = s;
1332 s->cookie_rx[i] = dmaengine_submit(desc);
1333 if (dma_submit_error(s->cookie_rx[i]))
1334 goto fail;
1335
1336 }
1337
1338 s->active_rx = s->cookie_rx[0];
1339
1340 dma_async_issue_pending(chan);
1341 return;
1342
1343fail:
1344 if (i)
1345 dmaengine_terminate_all(chan);
1346 for (i = 0; i < 2; i++)
1347 s->cookie_rx[i] = -EINVAL;
1348 s->active_rx = -EINVAL;
1349 sci_rx_dma_release(s, true);
1350}
1351
1352static void work_fn_tx(struct work_struct *work)
1353{
1354 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1355 struct dma_async_tx_descriptor *desc;
1356 struct dma_chan *chan = s->chan_tx;
1357 struct uart_port *port = &s->port;
1358 struct circ_buf *xmit = &port->state->xmit;
1359 dma_addr_t buf;
1360
1361 /*
1362 * DMA is idle now.
1363 * Port xmit buffer is already mapped, and it is one page... Just adjust
1364 * offsets and lengths. Since it is a circular buffer, we have to
1365 * transmit till the end, and then the rest. Take the port lock to get a
1366 * consistent xmit buffer state.
1367 */
1368 spin_lock_irq(&port->lock);
1369 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1370 s->tx_dma_len = min_t(unsigned int,
1371 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1372 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1373 spin_unlock_irq(&port->lock);
1374
1375 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1376 DMA_MEM_TO_DEV,
1377 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1378 if (!desc) {
1379 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1380 /* switch to PIO */
1381 sci_tx_dma_release(s, true);
1382 return;
1383 }
1384
1385 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1386 DMA_TO_DEVICE);
1387
1388 spin_lock_irq(&port->lock);
1389 desc->callback = sci_dma_tx_complete;
1390 desc->callback_param = s;
1391 spin_unlock_irq(&port->lock);
1392 s->cookie_tx = dmaengine_submit(desc);
1393 if (dma_submit_error(s->cookie_tx)) {
1394 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1395 /* switch to PIO */
1396 sci_tx_dma_release(s, true);
1397 return;
1398 }
1399
1400 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1401 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1402
1403 dma_async_issue_pending(chan);
1404}
1405
1406static enum hrtimer_restart rx_timer_fn(struct hrtimer *t)
1407{
1408 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1409 struct dma_chan *chan = s->chan_rx;
1410 struct uart_port *port = &s->port;
1411 struct dma_tx_state state;
1412 enum dma_status status;
1413 unsigned long flags;
1414 unsigned int read;
1415 int active, count;
1416 u16 scr;
1417
1418 dev_dbg(port->dev, "DMA Rx timed out\n");
1419
1420 spin_lock_irqsave(&port->lock, flags);
1421
1422 active = sci_dma_rx_find_active(s);
1423 if (active < 0) {
1424 spin_unlock_irqrestore(&port->lock, flags);
1425 return HRTIMER_NORESTART;
1426 }
1427
1428 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1429 if (status == DMA_COMPLETE) {
1430 spin_unlock_irqrestore(&port->lock, flags);
1431 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1432 s->active_rx, active);
1433
1434 /* Let packet complete handler take care of the packet */
1435 return HRTIMER_NORESTART;
1436 }
1437
1438 dmaengine_pause(chan);
1439
1440 /*
1441 * sometimes DMA transfer doesn't stop even if it is stopped and
1442 * data keeps on coming until transaction is complete so check
1443 * for DMA_COMPLETE again
1444 * Let packet complete handler take care of the packet
1445 */
1446 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1447 if (status == DMA_COMPLETE) {
1448 spin_unlock_irqrestore(&port->lock, flags);
1449 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1450 return HRTIMER_NORESTART;
1451 }
1452
1453 /* Handle incomplete DMA receive */
1454 dmaengine_terminate_all(s->chan_rx);
1455 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1456
1457 if (read) {
1458 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1459 if (count)
1460 tty_flip_buffer_push(&port->state->port);
1461 }
1462
1463 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1464 sci_submit_rx(s);
1465
1466 /* Direct new serial port interrupts back to CPU */
1467 scr = serial_port_in(port, SCSCR);
1468 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1469 scr &= ~SCSCR_RDRQE;
1470 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1471 }
1472 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1473
1474 spin_unlock_irqrestore(&port->lock, flags);
1475
1476 return HRTIMER_NORESTART;
1477}
1478
1479static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1480 enum dma_transfer_direction dir)
1481{
1482 struct dma_chan *chan;
1483 struct dma_slave_config cfg;
1484 int ret;
1485
1486 chan = dma_request_slave_channel(port->dev,
1487 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1488 if (!chan) {
1489 dev_warn(port->dev, "dma_request_slave_channel failed\n");
1490 return NULL;
1491 }
1492
1493 memset(&cfg, 0, sizeof(cfg));
1494 cfg.direction = dir;
1495 if (dir == DMA_MEM_TO_DEV) {
1496 cfg.dst_addr = port->mapbase +
1497 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1498 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1499 } else {
1500 cfg.src_addr = port->mapbase +
1501 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1502 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1503 }
1504
1505 ret = dmaengine_slave_config(chan, &cfg);
1506 if (ret) {
1507 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1508 dma_release_channel(chan);
1509 return NULL;
1510 }
1511
1512 return chan;
1513}
1514
1515static void sci_request_dma(struct uart_port *port)
1516{
1517 struct sci_port *s = to_sci_port(port);
1518 struct dma_chan *chan;
1519
1520 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1521
1522 if (!port->dev->of_node)
1523 return;
1524
1525 s->cookie_tx = -EINVAL;
1526
1527 /*
1528 * Don't request a dma channel if no channel was specified
1529 * in the device tree.
1530 */
1531 if (!of_find_property(port->dev->of_node, "dmas", NULL))
1532 return;
1533
1534 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1535 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1536 if (chan) {
1537 s->chan_tx = chan;
1538 /* UART circular tx buffer is an aligned page. */
1539 s->tx_dma_addr = dma_map_single(chan->device->dev,
1540 port->state->xmit.buf,
1541 UART_XMIT_SIZE,
1542 DMA_TO_DEVICE);
1543 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1544 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1545 dma_release_channel(chan);
1546 s->chan_tx = NULL;
1547 } else {
1548 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1549 __func__, UART_XMIT_SIZE,
1550 port->state->xmit.buf, &s->tx_dma_addr);
1551 }
1552
1553 INIT_WORK(&s->work_tx, work_fn_tx);
1554 }
1555
1556 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1557 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1558 if (chan) {
1559 unsigned int i;
1560 dma_addr_t dma;
1561 void *buf;
1562
1563 s->chan_rx = chan;
1564
1565 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1566 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1567 &dma, GFP_KERNEL);
1568 if (!buf) {
1569 dev_warn(port->dev,
1570 "Failed to allocate Rx dma buffer, using PIO\n");
1571 dma_release_channel(chan);
1572 s->chan_rx = NULL;
1573 return;
1574 }
1575
1576 for (i = 0; i < 2; i++) {
1577 struct scatterlist *sg = &s->sg_rx[i];
1578
1579 sg_init_table(sg, 1);
1580 s->rx_buf[i] = buf;
1581 sg_dma_address(sg) = dma;
1582 sg_dma_len(sg) = s->buf_len_rx;
1583
1584 buf += s->buf_len_rx;
1585 dma += s->buf_len_rx;
1586 }
1587
1588 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1589 s->rx_timer.function = rx_timer_fn;
1590
1591 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1592 sci_submit_rx(s);
1593 }
1594}
1595
1596static void sci_free_dma(struct uart_port *port)
1597{
1598 struct sci_port *s = to_sci_port(port);
1599
1600 if (s->chan_tx)
1601 sci_tx_dma_release(s, false);
1602 if (s->chan_rx)
1603 sci_rx_dma_release(s, false);
1604}
1605
1606static void sci_flush_buffer(struct uart_port *port)
1607{
1608 /*
1609 * In uart_flush_buffer(), the xmit circular buffer has just been
1610 * cleared, so we have to reset tx_dma_len accordingly.
1611 */
1612 to_sci_port(port)->tx_dma_len = 0;
1613}
1614#else /* !CONFIG_SERIAL_SH_SCI_DMA */
1615static inline void sci_request_dma(struct uart_port *port)
1616{
1617}
1618
1619static inline void sci_free_dma(struct uart_port *port)
1620{
1621}
1622
1623#define sci_flush_buffer NULL
1624#endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1625
1626static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1627{
1628 struct uart_port *port = ptr;
1629 struct sci_port *s = to_sci_port(port);
1630
1631#ifdef CONFIG_SERIAL_SH_SCI_DMA
1632 if (s->chan_rx) {
1633 u16 scr = serial_port_in(port, SCSCR);
1634 u16 ssr = serial_port_in(port, SCxSR);
1635
1636 /* Disable future Rx interrupts */
1637 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1638 disable_irq_nosync(irq);
1639 scr |= SCSCR_RDRQE;
1640 } else {
1641 scr &= ~SCSCR_RIE;
1642 sci_submit_rx(s);
1643 }
1644 serial_port_out(port, SCSCR, scr);
1645 /* Clear current interrupt */
1646 serial_port_out(port, SCxSR,
1647 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1648 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1649 jiffies, s->rx_timeout);
1650 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1651
1652 return IRQ_HANDLED;
1653 }
1654#endif
1655
1656 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1657 if (!scif_rtrg_enabled(port))
1658 scif_set_rtrg(port, s->rx_trigger);
1659
1660 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1661 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1662 }
1663
1664 /* I think sci_receive_chars has to be called irrespective
1665 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1666 * to be disabled?
1667 */
1668 sci_receive_chars(ptr);
1669
1670 return IRQ_HANDLED;
1671}
1672
1673static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1674{
1675 struct uart_port *port = ptr;
1676 unsigned long flags;
1677
1678 spin_lock_irqsave(&port->lock, flags);
1679 sci_transmit_chars(port);
1680 spin_unlock_irqrestore(&port->lock, flags);
1681
1682 return IRQ_HANDLED;
1683}
1684
1685static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1686{
1687 struct uart_port *port = ptr;
1688 struct sci_port *s = to_sci_port(port);
1689
1690 /* Handle errors */
1691 if (port->type == PORT_SCI) {
1692 if (sci_handle_errors(port)) {
1693 /* discard character in rx buffer */
1694 serial_port_in(port, SCxSR);
1695 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1696 }
1697 } else {
1698 sci_handle_fifo_overrun(port);
1699 if (!s->chan_rx)
1700 sci_receive_chars(ptr);
1701 }
1702
1703 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1704
1705 /* Kick the transmission */
1706 if (!s->chan_tx)
1707 sci_tx_interrupt(irq, ptr);
1708
1709 return IRQ_HANDLED;
1710}
1711
1712static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1713{
1714 struct uart_port *port = ptr;
1715
1716 /* Handle BREAKs */
1717 sci_handle_breaks(port);
1718 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1719
1720 return IRQ_HANDLED;
1721}
1722
1723static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1724{
1725 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1726 struct uart_port *port = ptr;
1727 struct sci_port *s = to_sci_port(port);
1728 irqreturn_t ret = IRQ_NONE;
1729
1730 ssr_status = serial_port_in(port, SCxSR);
1731 scr_status = serial_port_in(port, SCSCR);
1732 if (s->params->overrun_reg == SCxSR)
1733 orer_status = ssr_status;
1734 else if (sci_getreg(port, s->params->overrun_reg)->size)
1735 orer_status = serial_port_in(port, s->params->overrun_reg);
1736
1737 err_enabled = scr_status & port_rx_irq_mask(port);
1738
1739 /* Tx Interrupt */
1740 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1741 !s->chan_tx)
1742 ret = sci_tx_interrupt(irq, ptr);
1743
1744 /*
1745 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1746 * DR flags
1747 */
1748 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1749 (scr_status & SCSCR_RIE))
1750 ret = sci_rx_interrupt(irq, ptr);
1751
1752 /* Error Interrupt */
1753 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1754 ret = sci_er_interrupt(irq, ptr);
1755
1756 /* Break Interrupt */
1757 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1758 ret = sci_br_interrupt(irq, ptr);
1759
1760 /* Overrun Interrupt */
1761 if (orer_status & s->params->overrun_mask) {
1762 sci_handle_fifo_overrun(port);
1763 ret = IRQ_HANDLED;
1764 }
1765
1766 return ret;
1767}
1768
1769static const struct sci_irq_desc {
1770 const char *desc;
1771 irq_handler_t handler;
1772} sci_irq_desc[] = {
1773 /*
1774 * Split out handlers, the default case.
1775 */
1776 [SCIx_ERI_IRQ] = {
1777 .desc = "rx err",
1778 .handler = sci_er_interrupt,
1779 },
1780
1781 [SCIx_RXI_IRQ] = {
1782 .desc = "rx full",
1783 .handler = sci_rx_interrupt,
1784 },
1785
1786 [SCIx_TXI_IRQ] = {
1787 .desc = "tx empty",
1788 .handler = sci_tx_interrupt,
1789 },
1790
1791 [SCIx_BRI_IRQ] = {
1792 .desc = "break",
1793 .handler = sci_br_interrupt,
1794 },
1795
1796 /*
1797 * Special muxed handler.
1798 */
1799 [SCIx_MUX_IRQ] = {
1800 .desc = "mux",
1801 .handler = sci_mpxed_interrupt,
1802 },
1803};
1804
1805static int sci_request_irq(struct sci_port *port)
1806{
1807 struct uart_port *up = &port->port;
1808 int i, j, ret = 0;
1809
1810 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1811 const struct sci_irq_desc *desc;
1812 int irq;
1813
1814 if (SCIx_IRQ_IS_MUXED(port)) {
1815 i = SCIx_MUX_IRQ;
1816 irq = up->irq;
1817 } else {
1818 irq = port->irqs[i];
1819
1820 /*
1821 * Certain port types won't support all of the
1822 * available interrupt sources.
1823 */
1824 if (unlikely(irq < 0))
1825 continue;
1826 }
1827
1828 desc = sci_irq_desc + i;
1829 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1830 dev_name(up->dev), desc->desc);
1831 if (!port->irqstr[j]) {
1832 ret = -ENOMEM;
1833 goto out_nomem;
1834 }
1835
1836 ret = request_irq(irq, desc->handler, up->irqflags,
1837 port->irqstr[j], port);
1838 if (unlikely(ret)) {
1839 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1840 goto out_noirq;
1841 }
1842 }
1843
1844 return 0;
1845
1846out_noirq:
1847 while (--i >= 0)
1848 free_irq(port->irqs[i], port);
1849
1850out_nomem:
1851 while (--j >= 0)
1852 kfree(port->irqstr[j]);
1853
1854 return ret;
1855}
1856
1857static void sci_free_irq(struct sci_port *port)
1858{
1859 int i;
1860
1861 /*
1862 * Intentionally in reverse order so we iterate over the muxed
1863 * IRQ first.
1864 */
1865 for (i = 0; i < SCIx_NR_IRQS; i++) {
1866 int irq = port->irqs[i];
1867
1868 /*
1869 * Certain port types won't support all of the available
1870 * interrupt sources.
1871 */
1872 if (unlikely(irq < 0))
1873 continue;
1874
1875 free_irq(port->irqs[i], port);
1876 kfree(port->irqstr[i]);
1877
1878 if (SCIx_IRQ_IS_MUXED(port)) {
1879 /* If there's only one IRQ, we're done. */
1880 return;
1881 }
1882 }
1883}
1884
1885static unsigned int sci_tx_empty(struct uart_port *port)
1886{
1887 unsigned short status = serial_port_in(port, SCxSR);
1888 unsigned short in_tx_fifo = sci_txfill(port);
1889
1890 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1891}
1892
1893static void sci_set_rts(struct uart_port *port, bool state)
1894{
1895 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1896 u16 data = serial_port_in(port, SCPDR);
1897
1898 /* Active low */
1899 if (state)
1900 data &= ~SCPDR_RTSD;
1901 else
1902 data |= SCPDR_RTSD;
1903 serial_port_out(port, SCPDR, data);
1904
1905 /* RTS# is output */
1906 serial_port_out(port, SCPCR,
1907 serial_port_in(port, SCPCR) | SCPCR_RTSC);
1908 } else if (sci_getreg(port, SCSPTR)->size) {
1909 u16 ctrl = serial_port_in(port, SCSPTR);
1910
1911 /* Active low */
1912 if (state)
1913 ctrl &= ~SCSPTR_RTSDT;
1914 else
1915 ctrl |= SCSPTR_RTSDT;
1916 serial_port_out(port, SCSPTR, ctrl);
1917 }
1918}
1919
1920static bool sci_get_cts(struct uart_port *port)
1921{
1922 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1923 /* Active low */
1924 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
1925 } else if (sci_getreg(port, SCSPTR)->size) {
1926 /* Active low */
1927 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
1928 }
1929
1930 return true;
1931}
1932
1933/*
1934 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1935 * CTS/RTS is supported in hardware by at least one port and controlled
1936 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1937 * handled via the ->init_pins() op, which is a bit of a one-way street,
1938 * lacking any ability to defer pin control -- this will later be
1939 * converted over to the GPIO framework).
1940 *
1941 * Other modes (such as loopback) are supported generically on certain
1942 * port types, but not others. For these it's sufficient to test for the
1943 * existence of the support register and simply ignore the port type.
1944 */
1945static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1946{
1947 struct sci_port *s = to_sci_port(port);
1948
1949 if (mctrl & TIOCM_LOOP) {
1950 const struct plat_sci_reg *reg;
1951
1952 /*
1953 * Standard loopback mode for SCFCR ports.
1954 */
1955 reg = sci_getreg(port, SCFCR);
1956 if (reg->size)
1957 serial_port_out(port, SCFCR,
1958 serial_port_in(port, SCFCR) |
1959 SCFCR_LOOP);
1960 }
1961
1962 mctrl_gpio_set(s->gpios, mctrl);
1963
1964 if (!s->has_rtscts)
1965 return;
1966
1967 if (!(mctrl & TIOCM_RTS)) {
1968 /* Disable Auto RTS */
1969 serial_port_out(port, SCFCR,
1970 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
1971
1972 /* Clear RTS */
1973 sci_set_rts(port, 0);
1974 } else if (s->autorts) {
1975 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1976 /* Enable RTS# pin function */
1977 serial_port_out(port, SCPCR,
1978 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
1979 }
1980
1981 /* Enable Auto RTS */
1982 serial_port_out(port, SCFCR,
1983 serial_port_in(port, SCFCR) | SCFCR_MCE);
1984 } else {
1985 /* Set RTS */
1986 sci_set_rts(port, 1);
1987 }
1988}
1989
1990static unsigned int sci_get_mctrl(struct uart_port *port)
1991{
1992 struct sci_port *s = to_sci_port(port);
1993 struct mctrl_gpios *gpios = s->gpios;
1994 unsigned int mctrl = 0;
1995
1996 mctrl_gpio_get(gpios, &mctrl);
1997
1998 /*
1999 * CTS/RTS is handled in hardware when supported, while nothing
2000 * else is wired up.
2001 */
2002 if (s->autorts) {
2003 if (sci_get_cts(port))
2004 mctrl |= TIOCM_CTS;
2005 } else if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS))) {
2006 mctrl |= TIOCM_CTS;
2007 }
2008 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR)))
2009 mctrl |= TIOCM_DSR;
2010 if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD)))
2011 mctrl |= TIOCM_CAR;
2012
2013 return mctrl;
2014}
2015
2016static void sci_enable_ms(struct uart_port *port)
2017{
2018 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2019}
2020
2021static void sci_break_ctl(struct uart_port *port, int break_state)
2022{
2023 unsigned short scscr, scsptr;
2024 unsigned long flags;
2025
2026 /* check wheter the port has SCSPTR */
2027 if (!sci_getreg(port, SCSPTR)->size) {
2028 /*
2029 * Not supported by hardware. Most parts couple break and rx
2030 * interrupts together, with break detection always enabled.
2031 */
2032 return;
2033 }
2034
2035 spin_lock_irqsave(&port->lock, flags);
2036 scsptr = serial_port_in(port, SCSPTR);
2037 scscr = serial_port_in(port, SCSCR);
2038
2039 if (break_state == -1) {
2040 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2041 scscr &= ~SCSCR_TE;
2042 } else {
2043 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2044 scscr |= SCSCR_TE;
2045 }
2046
2047 serial_port_out(port, SCSPTR, scsptr);
2048 serial_port_out(port, SCSCR, scscr);
2049 spin_unlock_irqrestore(&port->lock, flags);
2050}
2051
2052static int sci_startup(struct uart_port *port)
2053{
2054 struct sci_port *s = to_sci_port(port);
2055 int ret;
2056
2057 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2058
2059 sci_request_dma(port);
2060
2061 ret = sci_request_irq(s);
2062 if (unlikely(ret < 0)) {
2063 sci_free_dma(port);
2064 return ret;
2065 }
2066
2067 return 0;
2068}
2069
2070static void sci_shutdown(struct uart_port *port)
2071{
2072 struct sci_port *s = to_sci_port(port);
2073 unsigned long flags;
2074 u16 scr;
2075
2076 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2077
2078 s->autorts = false;
2079 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2080
2081 spin_lock_irqsave(&port->lock, flags);
2082 sci_stop_rx(port);
2083 sci_stop_tx(port);
2084 /*
2085 * Stop RX and TX, disable related interrupts, keep clock source
2086 * and HSCIF TOT bits
2087 */
2088 scr = serial_port_in(port, SCSCR);
2089 serial_port_out(port, SCSCR, scr &
2090 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2091 spin_unlock_irqrestore(&port->lock, flags);
2092
2093#ifdef CONFIG_SERIAL_SH_SCI_DMA
2094 if (s->chan_rx) {
2095 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2096 port->line);
2097 hrtimer_cancel(&s->rx_timer);
2098 }
2099#endif
2100
2101 sci_free_irq(s);
2102 sci_free_dma(port);
2103}
2104
2105static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2106 unsigned int *srr)
2107{
2108 unsigned long freq = s->clk_rates[SCI_SCK];
2109 int err, min_err = INT_MAX;
2110 unsigned int sr;
2111
2112 if (s->port.type != PORT_HSCIF)
2113 freq *= 2;
2114
2115 for_each_sr(sr, s) {
2116 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2117 if (abs(err) >= abs(min_err))
2118 continue;
2119
2120 min_err = err;
2121 *srr = sr - 1;
2122
2123 if (!err)
2124 break;
2125 }
2126
2127 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2128 *srr + 1);
2129 return min_err;
2130}
2131
2132static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2133 unsigned long freq, unsigned int *dlr,
2134 unsigned int *srr)
2135{
2136 int err, min_err = INT_MAX;
2137 unsigned int sr, dl;
2138
2139 if (s->port.type != PORT_HSCIF)
2140 freq *= 2;
2141
2142 for_each_sr(sr, s) {
2143 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2144 dl = clamp(dl, 1U, 65535U);
2145
2146 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2147 if (abs(err) >= abs(min_err))
2148 continue;
2149
2150 min_err = err;
2151 *dlr = dl;
2152 *srr = sr - 1;
2153
2154 if (!err)
2155 break;
2156 }
2157
2158 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2159 min_err, *dlr, *srr + 1);
2160 return min_err;
2161}
2162
2163/* calculate sample rate, BRR, and clock select */
2164static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2165 unsigned int *brr, unsigned int *srr,
2166 unsigned int *cks)
2167{
2168 unsigned long freq = s->clk_rates[SCI_FCK];
2169 unsigned int sr, br, prediv, scrate, c;
2170 int err, min_err = INT_MAX;
2171
2172 if (s->port.type != PORT_HSCIF)
2173 freq *= 2;
2174
2175 /*
2176 * Find the combination of sample rate and clock select with the
2177 * smallest deviation from the desired baud rate.
2178 * Prefer high sample rates to maximise the receive margin.
2179 *
2180 * M: Receive margin (%)
2181 * N: Ratio of bit rate to clock (N = sampling rate)
2182 * D: Clock duty (D = 0 to 1.0)
2183 * L: Frame length (L = 9 to 12)
2184 * F: Absolute value of clock frequency deviation
2185 *
2186 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2187 * (|D - 0.5| / N * (1 + F))|
2188 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2189 */
2190 for_each_sr(sr, s) {
2191 for (c = 0; c <= 3; c++) {
2192 /* integerized formulas from HSCIF documentation */
2193 prediv = sr * (1 << (2 * c + 1));
2194
2195 /*
2196 * We need to calculate:
2197 *
2198 * br = freq / (prediv * bps) clamped to [1..256]
2199 * err = freq / (br * prediv) - bps
2200 *
2201 * Watch out for overflow when calculating the desired
2202 * sampling clock rate!
2203 */
2204 if (bps > UINT_MAX / prediv)
2205 break;
2206
2207 scrate = prediv * bps;
2208 br = DIV_ROUND_CLOSEST(freq, scrate);
2209 br = clamp(br, 1U, 256U);
2210
2211 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2212 if (abs(err) >= abs(min_err))
2213 continue;
2214
2215 min_err = err;
2216 *brr = br - 1;
2217 *srr = sr - 1;
2218 *cks = c;
2219
2220 if (!err)
2221 goto found;
2222 }
2223 }
2224
2225found:
2226 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2227 min_err, *brr, *srr + 1, *cks);
2228 return min_err;
2229}
2230
2231static void sci_reset(struct uart_port *port)
2232{
2233 const struct plat_sci_reg *reg;
2234 unsigned int status;
2235 struct sci_port *s = to_sci_port(port);
2236
2237 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2238
2239 reg = sci_getreg(port, SCFCR);
2240 if (reg->size)
2241 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2242
2243 sci_clear_SCxSR(port,
2244 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2245 SCxSR_BREAK_CLEAR(port));
2246 if (sci_getreg(port, SCLSR)->size) {
2247 status = serial_port_in(port, SCLSR);
2248 status &= ~(SCLSR_TO | SCLSR_ORER);
2249 serial_port_out(port, SCLSR, status);
2250 }
2251
2252 if (s->rx_trigger > 1) {
2253 if (s->rx_fifo_timeout) {
2254 scif_set_rtrg(port, 1);
2255 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2256 } else {
2257 if (port->type == PORT_SCIFA ||
2258 port->type == PORT_SCIFB)
2259 scif_set_rtrg(port, 1);
2260 else
2261 scif_set_rtrg(port, s->rx_trigger);
2262 }
2263 }
2264}
2265
2266static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2267 struct ktermios *old)
2268{
2269 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2270 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2271 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2272 struct sci_port *s = to_sci_port(port);
2273 const struct plat_sci_reg *reg;
2274 int min_err = INT_MAX, err;
2275 unsigned long max_freq = 0;
2276 int best_clk = -1;
2277 unsigned long flags;
2278
2279 if ((termios->c_cflag & CSIZE) == CS7)
2280 smr_val |= SCSMR_CHR;
2281 if (termios->c_cflag & PARENB)
2282 smr_val |= SCSMR_PE;
2283 if (termios->c_cflag & PARODD)
2284 smr_val |= SCSMR_PE | SCSMR_ODD;
2285 if (termios->c_cflag & CSTOPB)
2286 smr_val |= SCSMR_STOP;
2287
2288 /*
2289 * earlyprintk comes here early on with port->uartclk set to zero.
2290 * the clock framework is not up and running at this point so here
2291 * we assume that 115200 is the maximum baud rate. please note that
2292 * the baud rate is not programmed during earlyprintk - it is assumed
2293 * that the previous boot loader has enabled required clocks and
2294 * setup the baud rate generator hardware for us already.
2295 */
2296 if (!port->uartclk) {
2297 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2298 goto done;
2299 }
2300
2301 for (i = 0; i < SCI_NUM_CLKS; i++)
2302 max_freq = max(max_freq, s->clk_rates[i]);
2303
2304 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2305 if (!baud)
2306 goto done;
2307
2308 /*
2309 * There can be multiple sources for the sampling clock. Find the one
2310 * that gives us the smallest deviation from the desired baud rate.
2311 */
2312
2313 /* Optional Undivided External Clock */
2314 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2315 port->type != PORT_SCIFB) {
2316 err = sci_sck_calc(s, baud, &srr1);
2317 if (abs(err) < abs(min_err)) {
2318 best_clk = SCI_SCK;
2319 scr_val = SCSCR_CKE1;
2320 sccks = SCCKS_CKS;
2321 min_err = err;
2322 srr = srr1;
2323 if (!err)
2324 goto done;
2325 }
2326 }
2327
2328 /* Optional BRG Frequency Divided External Clock */
2329 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2330 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2331 &srr1);
2332 if (abs(err) < abs(min_err)) {
2333 best_clk = SCI_SCIF_CLK;
2334 scr_val = SCSCR_CKE1;
2335 sccks = 0;
2336 min_err = err;
2337 dl = dl1;
2338 srr = srr1;
2339 if (!err)
2340 goto done;
2341 }
2342 }
2343
2344 /* Optional BRG Frequency Divided Internal Clock */
2345 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2346 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2347 &srr1);
2348 if (abs(err) < abs(min_err)) {
2349 best_clk = SCI_BRG_INT;
2350 scr_val = SCSCR_CKE1;
2351 sccks = SCCKS_XIN;
2352 min_err = err;
2353 dl = dl1;
2354 srr = srr1;
2355 if (!min_err)
2356 goto done;
2357 }
2358 }
2359
2360 /* Divided Functional Clock using standard Bit Rate Register */
2361 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2362 if (abs(err) < abs(min_err)) {
2363 best_clk = SCI_FCK;
2364 scr_val = 0;
2365 min_err = err;
2366 brr = brr1;
2367 srr = srr1;
2368 cks = cks1;
2369 }
2370
2371done:
2372 if (best_clk >= 0)
2373 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2374 s->clks[best_clk], baud, min_err);
2375
2376 sci_port_enable(s);
2377
2378 /*
2379 * Program the optional External Baud Rate Generator (BRG) first.
2380 * It controls the mux to select (H)SCK or frequency divided clock.
2381 */
2382 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2383 serial_port_out(port, SCDL, dl);
2384 serial_port_out(port, SCCKS, sccks);
2385 }
2386
2387 spin_lock_irqsave(&port->lock, flags);
2388
2389 sci_reset(port);
2390
2391 uart_update_timeout(port, termios->c_cflag, baud);
2392
2393 if (best_clk >= 0) {
2394 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2395 switch (srr + 1) {
2396 case 5: smr_val |= SCSMR_SRC_5; break;
2397 case 7: smr_val |= SCSMR_SRC_7; break;
2398 case 11: smr_val |= SCSMR_SRC_11; break;
2399 case 13: smr_val |= SCSMR_SRC_13; break;
2400 case 16: smr_val |= SCSMR_SRC_16; break;
2401 case 17: smr_val |= SCSMR_SRC_17; break;
2402 case 19: smr_val |= SCSMR_SRC_19; break;
2403 case 27: smr_val |= SCSMR_SRC_27; break;
2404 }
2405 smr_val |= cks;
2406 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2407 serial_port_out(port, SCSMR, smr_val);
2408 serial_port_out(port, SCBRR, brr);
2409 if (sci_getreg(port, HSSRR)->size)
2410 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
2411
2412 /* Wait one bit interval */
2413 udelay((1000000 + (baud - 1)) / baud);
2414 } else {
2415 /* Don't touch the bit rate configuration */
2416 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2417 smr_val |= serial_port_in(port, SCSMR) &
2418 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2419 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2420 serial_port_out(port, SCSMR, smr_val);
2421 }
2422
2423 sci_init_pins(port, termios->c_cflag);
2424
2425 port->status &= ~UPSTAT_AUTOCTS;
2426 s->autorts = false;
2427 reg = sci_getreg(port, SCFCR);
2428 if (reg->size) {
2429 unsigned short ctrl = serial_port_in(port, SCFCR);
2430
2431 if ((port->flags & UPF_HARD_FLOW) &&
2432 (termios->c_cflag & CRTSCTS)) {
2433 /* There is no CTS interrupt to restart the hardware */
2434 port->status |= UPSTAT_AUTOCTS;
2435 /* MCE is enabled when RTS is raised */
2436 s->autorts = true;
2437 }
2438
2439 /*
2440 * As we've done a sci_reset() above, ensure we don't
2441 * interfere with the FIFOs while toggling MCE. As the
2442 * reset values could still be set, simply mask them out.
2443 */
2444 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2445
2446 serial_port_out(port, SCFCR, ctrl);
2447 }
2448 if (port->flags & UPF_HARD_FLOW) {
2449 /* Refresh (Auto) RTS */
2450 sci_set_mctrl(port, port->mctrl);
2451 }
2452
2453 scr_val |= SCSCR_RE | SCSCR_TE |
2454 (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2455 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2456 if ((srr + 1 == 5) &&
2457 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2458 /*
2459 * In asynchronous mode, when the sampling rate is 1/5, first
2460 * received data may become invalid on some SCIFA and SCIFB.
2461 * To avoid this problem wait more than 1 serial data time (1
2462 * bit time x serial data number) after setting SCSCR.RE = 1.
2463 */
2464 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2465 }
2466
2467 /*
2468 * Calculate delay for 2 DMA buffers (4 FIFO).
2469 * See serial_core.c::uart_update_timeout().
2470 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2471 * function calculates 1 jiffie for the data plus 5 jiffies for the
2472 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2473 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2474 * value obtained by this formula is too small. Therefore, if the value
2475 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2476 */
2477 /* byte size and parity */
2478 switch (termios->c_cflag & CSIZE) {
2479 case CS5:
2480 bits = 7;
2481 break;
2482 case CS6:
2483 bits = 8;
2484 break;
2485 case CS7:
2486 bits = 9;
2487 break;
2488 default:
2489 bits = 10;
2490 break;
2491 }
2492
2493 if (termios->c_cflag & CSTOPB)
2494 bits++;
2495 if (termios->c_cflag & PARENB)
2496 bits++;
2497
2498 s->rx_frame = (10000 * bits) / (baud / 100);
2499#ifdef CONFIG_SERIAL_SH_SCI_DMA
2500 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2501 if (s->rx_timeout < 20)
2502 s->rx_timeout = 20;
2503#endif
2504
2505 if ((termios->c_cflag & CREAD) != 0)
2506 sci_start_rx(port);
2507
2508 spin_unlock_irqrestore(&port->lock, flags);
2509
2510 sci_port_disable(s);
2511
2512 if (UART_ENABLE_MS(port, termios->c_cflag))
2513 sci_enable_ms(port);
2514}
2515
2516static void sci_pm(struct uart_port *port, unsigned int state,
2517 unsigned int oldstate)
2518{
2519 struct sci_port *sci_port = to_sci_port(port);
2520
2521 switch (state) {
2522 case UART_PM_STATE_OFF:
2523 sci_port_disable(sci_port);
2524 break;
2525 default:
2526 sci_port_enable(sci_port);
2527 break;
2528 }
2529}
2530
2531static const char *sci_type(struct uart_port *port)
2532{
2533 switch (port->type) {
2534 case PORT_IRDA:
2535 return "irda";
2536 case PORT_SCI:
2537 return "sci";
2538 case PORT_SCIF:
2539 return "scif";
2540 case PORT_SCIFA:
2541 return "scifa";
2542 case PORT_SCIFB:
2543 return "scifb";
2544 case PORT_HSCIF:
2545 return "hscif";
2546 }
2547
2548 return NULL;
2549}
2550
2551static int sci_remap_port(struct uart_port *port)
2552{
2553 struct sci_port *sport = to_sci_port(port);
2554
2555 /*
2556 * Nothing to do if there's already an established membase.
2557 */
2558 if (port->membase)
2559 return 0;
2560
2561 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2562 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2563 if (unlikely(!port->membase)) {
2564 dev_err(port->dev, "can't remap port#%d\n", port->line);
2565 return -ENXIO;
2566 }
2567 } else {
2568 /*
2569 * For the simple (and majority of) cases where we don't
2570 * need to do any remapping, just cast the cookie
2571 * directly.
2572 */
2573 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2574 }
2575
2576 return 0;
2577}
2578
2579static void sci_release_port(struct uart_port *port)
2580{
2581 struct sci_port *sport = to_sci_port(port);
2582
2583 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2584 iounmap(port->membase);
2585 port->membase = NULL;
2586 }
2587
2588 release_mem_region(port->mapbase, sport->reg_size);
2589}
2590
2591static int sci_request_port(struct uart_port *port)
2592{
2593 struct resource *res;
2594 struct sci_port *sport = to_sci_port(port);
2595 int ret;
2596
2597 res = request_mem_region(port->mapbase, sport->reg_size,
2598 dev_name(port->dev));
2599 if (unlikely(res == NULL)) {
2600 dev_err(port->dev, "request_mem_region failed.");
2601 return -EBUSY;
2602 }
2603
2604 ret = sci_remap_port(port);
2605 if (unlikely(ret != 0)) {
2606 release_resource(res);
2607 return ret;
2608 }
2609
2610 return 0;
2611}
2612
2613static void sci_config_port(struct uart_port *port, int flags)
2614{
2615 if (flags & UART_CONFIG_TYPE) {
2616 struct sci_port *sport = to_sci_port(port);
2617
2618 port->type = sport->cfg->type;
2619 sci_request_port(port);
2620 }
2621}
2622
2623static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2624{
2625 if (ser->baud_base < 2400)
2626 /* No paper tape reader for Mitch.. */
2627 return -EINVAL;
2628
2629 return 0;
2630}
2631
2632static const struct uart_ops sci_uart_ops = {
2633 .tx_empty = sci_tx_empty,
2634 .set_mctrl = sci_set_mctrl,
2635 .get_mctrl = sci_get_mctrl,
2636 .start_tx = sci_start_tx,
2637 .stop_tx = sci_stop_tx,
2638 .stop_rx = sci_stop_rx,
2639 .enable_ms = sci_enable_ms,
2640 .break_ctl = sci_break_ctl,
2641 .startup = sci_startup,
2642 .shutdown = sci_shutdown,
2643 .flush_buffer = sci_flush_buffer,
2644 .set_termios = sci_set_termios,
2645 .pm = sci_pm,
2646 .type = sci_type,
2647 .release_port = sci_release_port,
2648 .request_port = sci_request_port,
2649 .config_port = sci_config_port,
2650 .verify_port = sci_verify_port,
2651#ifdef CONFIG_CONSOLE_POLL
2652 .poll_get_char = sci_poll_get_char,
2653 .poll_put_char = sci_poll_put_char,
2654#endif
2655};
2656
2657static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2658{
2659 const char *clk_names[] = {
2660 [SCI_FCK] = "fck",
2661 [SCI_SCK] = "sck",
2662 [SCI_BRG_INT] = "brg_int",
2663 [SCI_SCIF_CLK] = "scif_clk",
2664 };
2665 struct clk *clk;
2666 unsigned int i;
2667
2668 if (sci_port->cfg->type == PORT_HSCIF)
2669 clk_names[SCI_SCK] = "hsck";
2670
2671 for (i = 0; i < SCI_NUM_CLKS; i++) {
2672 clk = devm_clk_get(dev, clk_names[i]);
2673 if (PTR_ERR(clk) == -EPROBE_DEFER)
2674 return -EPROBE_DEFER;
2675
2676 if (IS_ERR(clk) && i == SCI_FCK) {
2677 /*
2678 * "fck" used to be called "sci_ick", and we need to
2679 * maintain DT backward compatibility.
2680 */
2681 clk = devm_clk_get(dev, "sci_ick");
2682 if (PTR_ERR(clk) == -EPROBE_DEFER)
2683 return -EPROBE_DEFER;
2684
2685 if (!IS_ERR(clk))
2686 goto found;
2687
2688 /*
2689 * Not all SH platforms declare a clock lookup entry
2690 * for SCI devices, in which case we need to get the
2691 * global "peripheral_clk" clock.
2692 */
2693 clk = devm_clk_get(dev, "peripheral_clk");
2694 if (!IS_ERR(clk))
2695 goto found;
2696
2697 dev_err(dev, "failed to get %s (%ld)\n", clk_names[i],
2698 PTR_ERR(clk));
2699 return PTR_ERR(clk);
2700 }
2701
2702found:
2703 if (IS_ERR(clk))
2704 dev_dbg(dev, "failed to get %s (%ld)\n", clk_names[i],
2705 PTR_ERR(clk));
2706 else
2707 dev_dbg(dev, "clk %s is %pC rate %pCr\n", clk_names[i],
2708 clk, clk);
2709 sci_port->clks[i] = IS_ERR(clk) ? NULL : clk;
2710 }
2711 return 0;
2712}
2713
2714static const struct sci_port_params *
2715sci_probe_regmap(const struct plat_sci_port *cfg)
2716{
2717 unsigned int regtype;
2718
2719 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2720 return &sci_port_params[cfg->regtype];
2721
2722 switch (cfg->type) {
2723 case PORT_SCI:
2724 regtype = SCIx_SCI_REGTYPE;
2725 break;
2726 case PORT_IRDA:
2727 regtype = SCIx_IRDA_REGTYPE;
2728 break;
2729 case PORT_SCIFA:
2730 regtype = SCIx_SCIFA_REGTYPE;
2731 break;
2732 case PORT_SCIFB:
2733 regtype = SCIx_SCIFB_REGTYPE;
2734 break;
2735 case PORT_SCIF:
2736 /*
2737 * The SH-4 is a bit of a misnomer here, although that's
2738 * where this particular port layout originated. This
2739 * configuration (or some slight variation thereof)
2740 * remains the dominant model for all SCIFs.
2741 */
2742 regtype = SCIx_SH4_SCIF_REGTYPE;
2743 break;
2744 case PORT_HSCIF:
2745 regtype = SCIx_HSCIF_REGTYPE;
2746 break;
2747 default:
2748 pr_err("Can't probe register map for given port\n");
2749 return NULL;
2750 }
2751
2752 return &sci_port_params[regtype];
2753}
2754
2755static int sci_init_single(struct platform_device *dev,
2756 struct sci_port *sci_port, unsigned int index,
2757 const struct plat_sci_port *p, bool early)
2758{
2759 struct uart_port *port = &sci_port->port;
2760 const struct resource *res;
2761 unsigned int i;
2762 int ret;
2763
2764 sci_port->cfg = p;
2765
2766 port->ops = &sci_uart_ops;
2767 port->iotype = UPIO_MEM;
2768 port->line = index;
2769
2770 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2771 if (res == NULL)
2772 return -ENOMEM;
2773
2774 port->mapbase = res->start;
2775 sci_port->reg_size = resource_size(res);
2776
2777 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2778 sci_port->irqs[i] = platform_get_irq(dev, i);
2779
2780 /* The SCI generates several interrupts. They can be muxed together or
2781 * connected to different interrupt lines. In the muxed case only one
2782 * interrupt resource is specified. In the non-muxed case three or four
2783 * interrupt resources are specified, as the BRI interrupt is optional.
2784 */
2785 if (sci_port->irqs[0] < 0)
2786 return -ENXIO;
2787
2788 if (sci_port->irqs[1] < 0) {
2789 sci_port->irqs[1] = sci_port->irqs[0];
2790 sci_port->irqs[2] = sci_port->irqs[0];
2791 sci_port->irqs[3] = sci_port->irqs[0];
2792 }
2793
2794 sci_port->params = sci_probe_regmap(p);
2795 if (unlikely(sci_port->params == NULL))
2796 return -EINVAL;
2797
2798 switch (p->type) {
2799 case PORT_SCIFB:
2800 sci_port->rx_trigger = 48;
2801 break;
2802 case PORT_HSCIF:
2803 sci_port->rx_trigger = 64;
2804 break;
2805 case PORT_SCIFA:
2806 sci_port->rx_trigger = 32;
2807 break;
2808 case PORT_SCIF:
2809 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
2810 /* RX triggering not implemented for this IP */
2811 sci_port->rx_trigger = 1;
2812 else
2813 sci_port->rx_trigger = 8;
2814 break;
2815 default:
2816 sci_port->rx_trigger = 1;
2817 break;
2818 }
2819
2820 sci_port->rx_fifo_timeout = 0;
2821 sci_port->hscif_tot = 0;
2822
2823 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2824 * match the SoC datasheet, this should be investigated. Let platform
2825 * data override the sampling rate for now.
2826 */
2827 sci_port->sampling_rate_mask = p->sampling_rate
2828 ? SCI_SR(p->sampling_rate)
2829 : sci_port->params->sampling_rate_mask;
2830
2831 if (!early) {
2832 ret = sci_init_clocks(sci_port, &dev->dev);
2833 if (ret < 0)
2834 return ret;
2835
2836 port->dev = &dev->dev;
2837
2838 pm_runtime_enable(&dev->dev);
2839 }
2840
2841 port->type = p->type;
2842 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
2843 port->fifosize = sci_port->params->fifosize;
2844
2845 if (port->type == PORT_SCI) {
2846 if (sci_port->reg_size >= 0x20)
2847 port->regshift = 2;
2848 else
2849 port->regshift = 1;
2850 }
2851
2852 /*
2853 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2854 * for the multi-IRQ ports, which is where we are primarily
2855 * concerned with the shutdown path synchronization.
2856 *
2857 * For the muxed case there's nothing more to do.
2858 */
2859 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2860 port->irqflags = 0;
2861
2862 port->serial_in = sci_serial_in;
2863 port->serial_out = sci_serial_out;
2864
2865 return 0;
2866}
2867
2868static void sci_cleanup_single(struct sci_port *port)
2869{
2870 pm_runtime_disable(port->port.dev);
2871}
2872
2873#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
2874 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
2875static void serial_console_putchar(struct uart_port *port, int ch)
2876{
2877 sci_poll_put_char(port, ch);
2878}
2879
2880/*
2881 * Print a string to the serial port trying not to disturb
2882 * any possible real use of the port...
2883 */
2884static void serial_console_write(struct console *co, const char *s,
2885 unsigned count)
2886{
2887 struct sci_port *sci_port = &sci_ports[co->index];
2888 struct uart_port *port = &sci_port->port;
2889 unsigned short bits, ctrl, ctrl_temp;
2890 unsigned long flags;
2891 int locked = 1;
2892
2893 local_irq_save(flags);
2894#if defined(SUPPORT_SYSRQ)
2895 if (port->sysrq)
2896 locked = 0;
2897 else
2898#endif
2899 if (oops_in_progress)
2900 locked = spin_trylock(&port->lock);
2901 else
2902 spin_lock(&port->lock);
2903
2904 /* first save SCSCR then disable interrupts, keep clock source */
2905 ctrl = serial_port_in(port, SCSCR);
2906 ctrl_temp = SCSCR_RE | SCSCR_TE |
2907 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
2908 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
2909 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
2910
2911 uart_console_write(port, s, count, serial_console_putchar);
2912
2913 /* wait until fifo is empty and last bit has been transmitted */
2914 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2915 while ((serial_port_in(port, SCxSR) & bits) != bits)
2916 cpu_relax();
2917
2918 /* restore the SCSCR */
2919 serial_port_out(port, SCSCR, ctrl);
2920
2921 if (locked)
2922 spin_unlock(&port->lock);
2923 local_irq_restore(flags);
2924}
2925
2926static int serial_console_setup(struct console *co, char *options)
2927{
2928 struct sci_port *sci_port;
2929 struct uart_port *port;
2930 int baud = 115200;
2931 int bits = 8;
2932 int parity = 'n';
2933 int flow = 'n';
2934 int ret;
2935
2936 /*
2937 * Refuse to handle any bogus ports.
2938 */
2939 if (co->index < 0 || co->index >= SCI_NPORTS)
2940 return -ENODEV;
2941
2942 sci_port = &sci_ports[co->index];
2943 port = &sci_port->port;
2944
2945 /*
2946 * Refuse to handle uninitialized ports.
2947 */
2948 if (!port->ops)
2949 return -ENODEV;
2950
2951 ret = sci_remap_port(port);
2952 if (unlikely(ret != 0))
2953 return ret;
2954
2955 if (options)
2956 uart_parse_options(options, &baud, &parity, &bits, &flow);
2957
2958 return uart_set_options(port, co, baud, parity, bits, flow);
2959}
2960
2961static struct console serial_console = {
2962 .name = "ttySC",
2963 .device = uart_console_device,
2964 .write = serial_console_write,
2965 .setup = serial_console_setup,
2966 .flags = CON_PRINTBUFFER,
2967 .index = -1,
2968 .data = &sci_uart_driver,
2969};
2970
2971static struct console early_serial_console = {
2972 .name = "early_ttySC",
2973 .write = serial_console_write,
2974 .flags = CON_PRINTBUFFER,
2975 .index = -1,
2976};
2977
2978static char early_serial_buf[32];
2979
2980static int sci_probe_earlyprintk(struct platform_device *pdev)
2981{
2982 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2983
2984 if (early_serial_console.data)
2985 return -EEXIST;
2986
2987 early_serial_console.index = pdev->id;
2988
2989 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2990
2991 serial_console_setup(&early_serial_console, early_serial_buf);
2992
2993 if (!strstr(early_serial_buf, "keep"))
2994 early_serial_console.flags |= CON_BOOT;
2995
2996 register_console(&early_serial_console);
2997 return 0;
2998}
2999
3000#define SCI_CONSOLE (&serial_console)
3001
3002#else
3003static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3004{
3005 return -EINVAL;
3006}
3007
3008#define SCI_CONSOLE NULL
3009
3010#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3011
3012static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3013
3014static DEFINE_MUTEX(sci_uart_registration_lock);
3015static struct uart_driver sci_uart_driver = {
3016 .owner = THIS_MODULE,
3017 .driver_name = "sci",
3018 .dev_name = "ttySC",
3019 .major = SCI_MAJOR,
3020 .minor = SCI_MINOR_START,
3021 .nr = SCI_NPORTS,
3022 .cons = SCI_CONSOLE,
3023};
3024
3025static int sci_remove(struct platform_device *dev)
3026{
3027 struct sci_port *port = platform_get_drvdata(dev);
3028
3029 uart_remove_one_port(&sci_uart_driver, &port->port);
3030
3031 sci_cleanup_single(port);
3032
3033 if (port->port.fifosize > 1) {
3034 sysfs_remove_file(&dev->dev.kobj,
3035 &dev_attr_rx_fifo_trigger.attr);
3036 }
3037 if (port->port.type == PORT_SCIFA || port->port.type == PORT_SCIFB ||
3038 port->port.type == PORT_HSCIF) {
3039 sysfs_remove_file(&dev->dev.kobj,
3040 &dev_attr_rx_fifo_timeout.attr);
3041 }
3042
3043 return 0;
3044}
3045
3046
3047#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3048#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3049#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
3050
3051static const struct of_device_id of_sci_match[] = {
3052 /* SoC-specific types */
3053 {
3054 .compatible = "renesas,scif-r7s72100",
3055 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3056 },
3057 /* Family-specific types */
3058 {
3059 .compatible = "renesas,rcar-gen1-scif",
3060 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3061 }, {
3062 .compatible = "renesas,rcar-gen2-scif",
3063 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3064 }, {
3065 .compatible = "renesas,rcar-gen3-scif",
3066 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3067 },
3068 /* Generic types */
3069 {
3070 .compatible = "renesas,scif",
3071 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3072 }, {
3073 .compatible = "renesas,scifa",
3074 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3075 }, {
3076 .compatible = "renesas,scifb",
3077 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3078 }, {
3079 .compatible = "renesas,hscif",
3080 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3081 }, {
3082 .compatible = "renesas,sci",
3083 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3084 }, {
3085 /* Terminator */
3086 },
3087};
3088MODULE_DEVICE_TABLE(of, of_sci_match);
3089
3090static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3091 unsigned int *dev_id)
3092{
3093 struct device_node *np = pdev->dev.of_node;
3094 struct plat_sci_port *p;
3095 struct sci_port *sp;
3096 const void *data;
3097 int id;
3098
3099 if (!IS_ENABLED(CONFIG_OF) || !np)
3100 return NULL;
3101
3102 data = of_device_get_match_data(&pdev->dev);
3103
3104 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3105 if (!p)
3106 return NULL;
3107
3108 /* Get the line number from the aliases node. */
3109 id = of_alias_get_id(np, "serial");
3110 if (id < 0) {
3111 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3112 return NULL;
3113 }
3114 if (id >= ARRAY_SIZE(sci_ports)) {
3115 dev_err(&pdev->dev, "serial%d out of range\n", id);
3116 return NULL;
3117 }
3118
3119 sp = &sci_ports[id];
3120 *dev_id = id;
3121
3122 p->type = SCI_OF_TYPE(data);
3123 p->regtype = SCI_OF_REGTYPE(data);
3124
3125 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3126
3127 return p;
3128}
3129
3130static int sci_probe_single(struct platform_device *dev,
3131 unsigned int index,
3132 struct plat_sci_port *p,
3133 struct sci_port *sciport)
3134{
3135 int ret;
3136
3137 /* Sanity check */
3138 if (unlikely(index >= SCI_NPORTS)) {
3139 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3140 index+1, SCI_NPORTS);
3141 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3142 return -EINVAL;
3143 }
3144
3145 mutex_lock(&sci_uart_registration_lock);
3146 if (!sci_uart_driver.state) {
3147 ret = uart_register_driver(&sci_uart_driver);
3148 if (ret) {
3149 mutex_unlock(&sci_uart_registration_lock);
3150 return ret;
3151 }
3152 }
3153 mutex_unlock(&sci_uart_registration_lock);
3154
3155 ret = sci_init_single(dev, sciport, index, p, false);
3156 if (ret)
3157 return ret;
3158
3159 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3160 if (IS_ERR(sciport->gpios) && PTR_ERR(sciport->gpios) != -ENOSYS)
3161 return PTR_ERR(sciport->gpios);
3162
3163 if (sciport->has_rtscts) {
3164 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3165 UART_GPIO_CTS)) ||
3166 !IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(sciport->gpios,
3167 UART_GPIO_RTS))) {
3168 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3169 return -EINVAL;
3170 }
3171 sciport->port.flags |= UPF_HARD_FLOW;
3172 }
3173
3174 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
3175 if (ret) {
3176 sci_cleanup_single(sciport);
3177 return ret;
3178 }
3179
3180 return 0;
3181}
3182
3183static int sci_probe(struct platform_device *dev)
3184{
3185 struct plat_sci_port *p;
3186 struct sci_port *sp;
3187 unsigned int dev_id;
3188 int ret;
3189
3190 /*
3191 * If we've come here via earlyprintk initialization, head off to
3192 * the special early probe. We don't have sufficient device state
3193 * to make it beyond this yet.
3194 */
3195 if (is_early_platform_device(dev))
3196 return sci_probe_earlyprintk(dev);
3197
3198 if (dev->dev.of_node) {
3199 p = sci_parse_dt(dev, &dev_id);
3200 if (p == NULL)
3201 return -EINVAL;
3202 } else {
3203 p = dev->dev.platform_data;
3204 if (p == NULL) {
3205 dev_err(&dev->dev, "no platform data supplied\n");
3206 return -EINVAL;
3207 }
3208
3209 dev_id = dev->id;
3210 }
3211
3212 sp = &sci_ports[dev_id];
3213 platform_set_drvdata(dev, sp);
3214
3215 ret = sci_probe_single(dev, dev_id, p, sp);
3216 if (ret)
3217 return ret;
3218
3219 if (sp->port.fifosize > 1) {
3220 ret = sysfs_create_file(&dev->dev.kobj,
3221 &dev_attr_rx_fifo_trigger.attr);
3222 if (ret)
3223 return ret;
3224 }
3225 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3226 sp->port.type == PORT_HSCIF) {
3227 ret = sysfs_create_file(&dev->dev.kobj,
3228 &dev_attr_rx_fifo_timeout.attr);
3229 if (ret) {
3230 if (sp->port.fifosize > 1) {
3231 sysfs_remove_file(&dev->dev.kobj,
3232 &dev_attr_rx_fifo_trigger.attr);
3233 }
3234 return ret;
3235 }
3236 }
3237
3238#ifdef CONFIG_SH_STANDARD_BIOS
3239 sh_bios_gdb_detach();
3240#endif
3241
3242 return 0;
3243}
3244
3245static __maybe_unused int sci_suspend(struct device *dev)
3246{
3247 struct sci_port *sport = dev_get_drvdata(dev);
3248
3249 if (sport)
3250 uart_suspend_port(&sci_uart_driver, &sport->port);
3251
3252 return 0;
3253}
3254
3255static __maybe_unused int sci_resume(struct device *dev)
3256{
3257 struct sci_port *sport = dev_get_drvdata(dev);
3258
3259 if (sport)
3260 uart_resume_port(&sci_uart_driver, &sport->port);
3261
3262 return 0;
3263}
3264
3265static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3266
3267static struct platform_driver sci_driver = {
3268 .probe = sci_probe,
3269 .remove = sci_remove,
3270 .driver = {
3271 .name = "sh-sci",
3272 .pm = &sci_dev_pm_ops,
3273 .of_match_table = of_match_ptr(of_sci_match),
3274 },
3275};
3276
3277static int __init sci_init(void)
3278{
3279 pr_info("%s\n", banner);
3280
3281 return platform_driver_register(&sci_driver);
3282}
3283
3284static void __exit sci_exit(void)
3285{
3286 platform_driver_unregister(&sci_driver);
3287
3288 if (sci_uart_driver.state)
3289 uart_unregister_driver(&sci_uart_driver);
3290}
3291
3292#ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
3293early_platform_init_buffer("earlyprintk", &sci_driver,
3294 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3295#endif
3296#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3297static struct plat_sci_port port_cfg __initdata;
3298
3299static int __init early_console_setup(struct earlycon_device *device,
3300 int type)
3301{
3302 if (!device->port.membase)
3303 return -ENODEV;
3304
3305 device->port.serial_in = sci_serial_in;
3306 device->port.serial_out = sci_serial_out;
3307 device->port.type = type;
3308 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3309 port_cfg.type = type;
3310 sci_ports[0].cfg = &port_cfg;
3311 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3312 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3313 sci_serial_out(&sci_ports[0].port, SCSCR,
3314 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3315
3316 device->con->write = serial_console_write;
3317 return 0;
3318}
3319static int __init sci_early_console_setup(struct earlycon_device *device,
3320 const char *opt)
3321{
3322 return early_console_setup(device, PORT_SCI);
3323}
3324static int __init scif_early_console_setup(struct earlycon_device *device,
3325 const char *opt)
3326{
3327 return early_console_setup(device, PORT_SCIF);
3328}
3329static int __init scifa_early_console_setup(struct earlycon_device *device,
3330 const char *opt)
3331{
3332 return early_console_setup(device, PORT_SCIFA);
3333}
3334static int __init scifb_early_console_setup(struct earlycon_device *device,
3335 const char *opt)
3336{
3337 return early_console_setup(device, PORT_SCIFB);
3338}
3339static int __init hscif_early_console_setup(struct earlycon_device *device,
3340 const char *opt)
3341{
3342 return early_console_setup(device, PORT_HSCIF);
3343}
3344
3345OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3346OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3347OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3348OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3349OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3350#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3351
3352module_init(sci_init);
3353module_exit(sci_exit);
3354
3355MODULE_LICENSE("GPL");
3356MODULE_ALIAS("platform:sh-sci");
3357MODULE_AUTHOR("Paul Mundt");
3358MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 *
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 */
18#undef DEBUG
19
20#include <linux/clk.h>
21#include <linux/console.h>
22#include <linux/ctype.h>
23#include <linux/cpufreq.h>
24#include <linux/delay.h>
25#include <linux/dmaengine.h>
26#include <linux/dma-mapping.h>
27#include <linux/err.h>
28#include <linux/errno.h>
29#include <linux/init.h>
30#include <linux/interrupt.h>
31#include <linux/ioport.h>
32#include <linux/ktime.h>
33#include <linux/major.h>
34#include <linux/minmax.h>
35#include <linux/module.h>
36#include <linux/mm.h>
37#include <linux/of.h>
38#include <linux/platform_device.h>
39#include <linux/pm_runtime.h>
40#include <linux/reset.h>
41#include <linux/scatterlist.h>
42#include <linux/serial.h>
43#include <linux/serial_sci.h>
44#include <linux/sh_dma.h>
45#include <linux/slab.h>
46#include <linux/string.h>
47#include <linux/sysrq.h>
48#include <linux/timer.h>
49#include <linux/tty.h>
50#include <linux/tty_flip.h>
51
52#ifdef CONFIG_SUPERH
53#include <asm/sh_bios.h>
54#include <asm/platform_early.h>
55#endif
56
57#include "serial_mctrl_gpio.h"
58#include "sh-sci.h"
59
60/* Offsets into the sci_port->irqs array */
61enum {
62 SCIx_ERI_IRQ,
63 SCIx_RXI_IRQ,
64 SCIx_TXI_IRQ,
65 SCIx_BRI_IRQ,
66 SCIx_DRI_IRQ,
67 SCIx_TEI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71};
72
73#define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
79enum SCI_CLKS {
80 SCI_FCK, /* Functional Clock */
81 SCI_SCK, /* Optional External Clock */
82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
84 SCI_NUM_CLKS
85};
86
87/* Bit x set means sampling rate x + 1 is supported */
88#define SCI_SR(x) BIT((x) - 1)
89#define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
90
91#define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
92 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
93 SCI_SR(19) | SCI_SR(27)
94
95#define min_sr(_port) ffs((_port)->sampling_rate_mask)
96#define max_sr(_port) fls((_port)->sampling_rate_mask)
97
98/* Iterate over all supported sampling rates, from high to low */
99#define for_each_sr(_sr, _port) \
100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
101 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
102
103struct plat_sci_reg {
104 u8 offset, size;
105};
106
107struct sci_port_params {
108 const struct plat_sci_reg regs[SCIx_NR_REGS];
109 unsigned int fifosize;
110 unsigned int overrun_reg;
111 unsigned int overrun_mask;
112 unsigned int sampling_rate_mask;
113 unsigned int error_mask;
114 unsigned int error_clear;
115};
116
117struct sci_port {
118 struct uart_port port;
119
120 /* Platform configuration */
121 const struct sci_port_params *params;
122 const struct plat_sci_port *cfg;
123 unsigned int sampling_rate_mask;
124 resource_size_t reg_size;
125 struct mctrl_gpios *gpios;
126
127 /* Clocks */
128 struct clk *clks[SCI_NUM_CLKS];
129 unsigned long clk_rates[SCI_NUM_CLKS];
130
131 int irqs[SCIx_NR_IRQS];
132 char *irqstr[SCIx_NR_IRQS];
133
134 struct dma_chan *chan_tx;
135 struct dma_chan *chan_rx;
136
137#ifdef CONFIG_SERIAL_SH_SCI_DMA
138 struct dma_chan *chan_tx_saved;
139 struct dma_chan *chan_rx_saved;
140 dma_cookie_t cookie_tx;
141 dma_cookie_t cookie_rx[2];
142 dma_cookie_t active_rx;
143 dma_addr_t tx_dma_addr;
144 unsigned int tx_dma_len;
145 struct scatterlist sg_rx[2];
146 void *rx_buf[2];
147 size_t buf_len_rx;
148 struct work_struct work_tx;
149 struct hrtimer rx_timer;
150 unsigned int rx_timeout; /* microseconds */
151#endif
152 unsigned int rx_frame;
153 int rx_trigger;
154 struct timer_list rx_fifo_timer;
155 int rx_fifo_timeout;
156 u16 hscif_tot;
157
158 bool has_rtscts;
159 bool autorts;
160 bool tx_occurred;
161};
162
163#define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
164
165static struct sci_port sci_ports[SCI_NPORTS];
166static unsigned long sci_ports_in_use;
167static struct uart_driver sci_uart_driver;
168static bool sci_uart_earlycon;
169static bool sci_uart_earlycon_dev_probing;
170
171static inline struct sci_port *
172to_sci_port(struct uart_port *uart)
173{
174 return container_of(uart, struct sci_port, port);
175}
176
177static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
178 /*
179 * Common SCI definitions, dependent on the port's regshift
180 * value.
181 */
182 [SCIx_SCI_REGTYPE] = {
183 .regs = {
184 [SCSMR] = { 0x00, 8 },
185 [SCBRR] = { 0x01, 8 },
186 [SCSCR] = { 0x02, 8 },
187 [SCxTDR] = { 0x03, 8 },
188 [SCxSR] = { 0x04, 8 },
189 [SCxRDR] = { 0x05, 8 },
190 },
191 .fifosize = 1,
192 .overrun_reg = SCxSR,
193 .overrun_mask = SCI_ORER,
194 .sampling_rate_mask = SCI_SR(32),
195 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
196 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
197 },
198
199 /*
200 * Common definitions for legacy IrDA ports.
201 */
202 [SCIx_IRDA_REGTYPE] = {
203 .regs = {
204 [SCSMR] = { 0x00, 8 },
205 [SCBRR] = { 0x02, 8 },
206 [SCSCR] = { 0x04, 8 },
207 [SCxTDR] = { 0x06, 8 },
208 [SCxSR] = { 0x08, 16 },
209 [SCxRDR] = { 0x0a, 8 },
210 [SCFCR] = { 0x0c, 8 },
211 [SCFDR] = { 0x0e, 16 },
212 },
213 .fifosize = 1,
214 .overrun_reg = SCxSR,
215 .overrun_mask = SCI_ORER,
216 .sampling_rate_mask = SCI_SR(32),
217 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
218 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
219 },
220
221 /*
222 * Common SCIFA definitions.
223 */
224 [SCIx_SCIFA_REGTYPE] = {
225 .regs = {
226 [SCSMR] = { 0x00, 16 },
227 [SCBRR] = { 0x04, 8 },
228 [SCSCR] = { 0x08, 16 },
229 [SCxTDR] = { 0x20, 8 },
230 [SCxSR] = { 0x14, 16 },
231 [SCxRDR] = { 0x24, 8 },
232 [SCFCR] = { 0x18, 16 },
233 [SCFDR] = { 0x1c, 16 },
234 [SCPCR] = { 0x30, 16 },
235 [SCPDR] = { 0x34, 16 },
236 },
237 .fifosize = 64,
238 .overrun_reg = SCxSR,
239 .overrun_mask = SCIFA_ORER,
240 .sampling_rate_mask = SCI_SR_SCIFAB,
241 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
242 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
243 },
244
245 /*
246 * Common SCIFB definitions.
247 */
248 [SCIx_SCIFB_REGTYPE] = {
249 .regs = {
250 [SCSMR] = { 0x00, 16 },
251 [SCBRR] = { 0x04, 8 },
252 [SCSCR] = { 0x08, 16 },
253 [SCxTDR] = { 0x40, 8 },
254 [SCxSR] = { 0x14, 16 },
255 [SCxRDR] = { 0x60, 8 },
256 [SCFCR] = { 0x18, 16 },
257 [SCTFDR] = { 0x38, 16 },
258 [SCRFDR] = { 0x3c, 16 },
259 [SCPCR] = { 0x30, 16 },
260 [SCPDR] = { 0x34, 16 },
261 },
262 .fifosize = 256,
263 .overrun_reg = SCxSR,
264 .overrun_mask = SCIFA_ORER,
265 .sampling_rate_mask = SCI_SR_SCIFAB,
266 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
267 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
268 },
269
270 /*
271 * Common SH-2(A) SCIF definitions for ports with FIFO data
272 * count registers.
273 */
274 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
275 .regs = {
276 [SCSMR] = { 0x00, 16 },
277 [SCBRR] = { 0x04, 8 },
278 [SCSCR] = { 0x08, 16 },
279 [SCxTDR] = { 0x0c, 8 },
280 [SCxSR] = { 0x10, 16 },
281 [SCxRDR] = { 0x14, 8 },
282 [SCFCR] = { 0x18, 16 },
283 [SCFDR] = { 0x1c, 16 },
284 [SCSPTR] = { 0x20, 16 },
285 [SCLSR] = { 0x24, 16 },
286 },
287 .fifosize = 16,
288 .overrun_reg = SCLSR,
289 .overrun_mask = SCLSR_ORER,
290 .sampling_rate_mask = SCI_SR(32),
291 .error_mask = SCIF_DEFAULT_ERROR_MASK,
292 .error_clear = SCIF_ERROR_CLEAR,
293 },
294
295 /*
296 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T.
297 * It looks like a normal SCIF with FIFO data, but with a
298 * compressed address space. Also, the break out of interrupts
299 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
300 */
301 [SCIx_RZ_SCIFA_REGTYPE] = {
302 .regs = {
303 [SCSMR] = { 0x00, 16 },
304 [SCBRR] = { 0x02, 8 },
305 [SCSCR] = { 0x04, 16 },
306 [SCxTDR] = { 0x06, 8 },
307 [SCxSR] = { 0x08, 16 },
308 [SCxRDR] = { 0x0A, 8 },
309 [SCFCR] = { 0x0C, 16 },
310 [SCFDR] = { 0x0E, 16 },
311 [SCSPTR] = { 0x10, 16 },
312 [SCLSR] = { 0x12, 16 },
313 [SEMR] = { 0x14, 8 },
314 },
315 .fifosize = 16,
316 .overrun_reg = SCLSR,
317 .overrun_mask = SCLSR_ORER,
318 .sampling_rate_mask = SCI_SR(32),
319 .error_mask = SCIF_DEFAULT_ERROR_MASK,
320 .error_clear = SCIF_ERROR_CLEAR,
321 },
322
323 /*
324 * The "SCIF" that is in RZ/V2H(P) SoC is similar to one found on RZ/G2L SoC
325 * with below differences,
326 * - Break out of interrupts are different: ERI, BRI, RXI, TXI, TEI, DRI,
327 * TEI-DRI, RXI-EDGE and TXI-EDGE.
328 * - SCSMR register does not have CM bit (BIT(7)) ie it does not support synchronous mode.
329 * - SCFCR register does not have SCFCR_MCE bit.
330 * - SCSPTR register has only bits SCSPTR_SPB2DT and SCSPTR_SPB2IO.
331 */
332 [SCIx_RZV2H_SCIF_REGTYPE] = {
333 .regs = {
334 [SCSMR] = { 0x00, 16 },
335 [SCBRR] = { 0x02, 8 },
336 [SCSCR] = { 0x04, 16 },
337 [SCxTDR] = { 0x06, 8 },
338 [SCxSR] = { 0x08, 16 },
339 [SCxRDR] = { 0x0a, 8 },
340 [SCFCR] = { 0x0c, 16 },
341 [SCFDR] = { 0x0e, 16 },
342 [SCSPTR] = { 0x10, 16 },
343 [SCLSR] = { 0x12, 16 },
344 [SEMR] = { 0x14, 8 },
345 },
346 .fifosize = 16,
347 .overrun_reg = SCLSR,
348 .overrun_mask = SCLSR_ORER,
349 .sampling_rate_mask = SCI_SR(32),
350 .error_mask = SCIF_DEFAULT_ERROR_MASK,
351 .error_clear = SCIF_ERROR_CLEAR,
352 },
353
354 /*
355 * Common SH-3 SCIF definitions.
356 */
357 [SCIx_SH3_SCIF_REGTYPE] = {
358 .regs = {
359 [SCSMR] = { 0x00, 8 },
360 [SCBRR] = { 0x02, 8 },
361 [SCSCR] = { 0x04, 8 },
362 [SCxTDR] = { 0x06, 8 },
363 [SCxSR] = { 0x08, 16 },
364 [SCxRDR] = { 0x0a, 8 },
365 [SCFCR] = { 0x0c, 8 },
366 [SCFDR] = { 0x0e, 16 },
367 },
368 .fifosize = 16,
369 .overrun_reg = SCLSR,
370 .overrun_mask = SCLSR_ORER,
371 .sampling_rate_mask = SCI_SR(32),
372 .error_mask = SCIF_DEFAULT_ERROR_MASK,
373 .error_clear = SCIF_ERROR_CLEAR,
374 },
375
376 /*
377 * Common SH-4(A) SCIF(B) definitions.
378 */
379 [SCIx_SH4_SCIF_REGTYPE] = {
380 .regs = {
381 [SCSMR] = { 0x00, 16 },
382 [SCBRR] = { 0x04, 8 },
383 [SCSCR] = { 0x08, 16 },
384 [SCxTDR] = { 0x0c, 8 },
385 [SCxSR] = { 0x10, 16 },
386 [SCxRDR] = { 0x14, 8 },
387 [SCFCR] = { 0x18, 16 },
388 [SCFDR] = { 0x1c, 16 },
389 [SCSPTR] = { 0x20, 16 },
390 [SCLSR] = { 0x24, 16 },
391 },
392 .fifosize = 16,
393 .overrun_reg = SCLSR,
394 .overrun_mask = SCLSR_ORER,
395 .sampling_rate_mask = SCI_SR(32),
396 .error_mask = SCIF_DEFAULT_ERROR_MASK,
397 .error_clear = SCIF_ERROR_CLEAR,
398 },
399
400 /*
401 * Common SCIF definitions for ports with a Baud Rate Generator for
402 * External Clock (BRG).
403 */
404 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
405 .regs = {
406 [SCSMR] = { 0x00, 16 },
407 [SCBRR] = { 0x04, 8 },
408 [SCSCR] = { 0x08, 16 },
409 [SCxTDR] = { 0x0c, 8 },
410 [SCxSR] = { 0x10, 16 },
411 [SCxRDR] = { 0x14, 8 },
412 [SCFCR] = { 0x18, 16 },
413 [SCFDR] = { 0x1c, 16 },
414 [SCSPTR] = { 0x20, 16 },
415 [SCLSR] = { 0x24, 16 },
416 [SCDL] = { 0x30, 16 },
417 [SCCKS] = { 0x34, 16 },
418 },
419 .fifosize = 16,
420 .overrun_reg = SCLSR,
421 .overrun_mask = SCLSR_ORER,
422 .sampling_rate_mask = SCI_SR(32),
423 .error_mask = SCIF_DEFAULT_ERROR_MASK,
424 .error_clear = SCIF_ERROR_CLEAR,
425 },
426
427 /*
428 * Common HSCIF definitions.
429 */
430 [SCIx_HSCIF_REGTYPE] = {
431 .regs = {
432 [SCSMR] = { 0x00, 16 },
433 [SCBRR] = { 0x04, 8 },
434 [SCSCR] = { 0x08, 16 },
435 [SCxTDR] = { 0x0c, 8 },
436 [SCxSR] = { 0x10, 16 },
437 [SCxRDR] = { 0x14, 8 },
438 [SCFCR] = { 0x18, 16 },
439 [SCFDR] = { 0x1c, 16 },
440 [SCSPTR] = { 0x20, 16 },
441 [SCLSR] = { 0x24, 16 },
442 [HSSRR] = { 0x40, 16 },
443 [SCDL] = { 0x30, 16 },
444 [SCCKS] = { 0x34, 16 },
445 [HSRTRGR] = { 0x54, 16 },
446 [HSTTRGR] = { 0x58, 16 },
447 },
448 .fifosize = 128,
449 .overrun_reg = SCLSR,
450 .overrun_mask = SCLSR_ORER,
451 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
452 .error_mask = SCIF_DEFAULT_ERROR_MASK,
453 .error_clear = SCIF_ERROR_CLEAR,
454 },
455
456 /*
457 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
458 * register.
459 */
460 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
461 .regs = {
462 [SCSMR] = { 0x00, 16 },
463 [SCBRR] = { 0x04, 8 },
464 [SCSCR] = { 0x08, 16 },
465 [SCxTDR] = { 0x0c, 8 },
466 [SCxSR] = { 0x10, 16 },
467 [SCxRDR] = { 0x14, 8 },
468 [SCFCR] = { 0x18, 16 },
469 [SCFDR] = { 0x1c, 16 },
470 [SCLSR] = { 0x24, 16 },
471 },
472 .fifosize = 16,
473 .overrun_reg = SCLSR,
474 .overrun_mask = SCLSR_ORER,
475 .sampling_rate_mask = SCI_SR(32),
476 .error_mask = SCIF_DEFAULT_ERROR_MASK,
477 .error_clear = SCIF_ERROR_CLEAR,
478 },
479
480 /*
481 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
482 * count registers.
483 */
484 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
485 .regs = {
486 [SCSMR] = { 0x00, 16 },
487 [SCBRR] = { 0x04, 8 },
488 [SCSCR] = { 0x08, 16 },
489 [SCxTDR] = { 0x0c, 8 },
490 [SCxSR] = { 0x10, 16 },
491 [SCxRDR] = { 0x14, 8 },
492 [SCFCR] = { 0x18, 16 },
493 [SCFDR] = { 0x1c, 16 },
494 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
495 [SCRFDR] = { 0x20, 16 },
496 [SCSPTR] = { 0x24, 16 },
497 [SCLSR] = { 0x28, 16 },
498 },
499 .fifosize = 16,
500 .overrun_reg = SCLSR,
501 .overrun_mask = SCLSR_ORER,
502 .sampling_rate_mask = SCI_SR(32),
503 .error_mask = SCIF_DEFAULT_ERROR_MASK,
504 .error_clear = SCIF_ERROR_CLEAR,
505 },
506
507 /*
508 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
509 * registers.
510 */
511 [SCIx_SH7705_SCIF_REGTYPE] = {
512 .regs = {
513 [SCSMR] = { 0x00, 16 },
514 [SCBRR] = { 0x04, 8 },
515 [SCSCR] = { 0x08, 16 },
516 [SCxTDR] = { 0x20, 8 },
517 [SCxSR] = { 0x14, 16 },
518 [SCxRDR] = { 0x24, 8 },
519 [SCFCR] = { 0x18, 16 },
520 [SCFDR] = { 0x1c, 16 },
521 },
522 .fifosize = 64,
523 .overrun_reg = SCxSR,
524 .overrun_mask = SCIFA_ORER,
525 .sampling_rate_mask = SCI_SR(16),
526 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
527 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
528 },
529};
530
531#define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
532
533/*
534 * The "offset" here is rather misleading, in that it refers to an enum
535 * value relative to the port mapping rather than the fixed offset
536 * itself, which needs to be manually retrieved from the platform's
537 * register map for the given port.
538 */
539static unsigned int sci_serial_in(struct uart_port *p, int offset)
540{
541 const struct plat_sci_reg *reg = sci_getreg(p, offset);
542
543 if (reg->size == 8)
544 return ioread8(p->membase + (reg->offset << p->regshift));
545 else if (reg->size == 16)
546 return ioread16(p->membase + (reg->offset << p->regshift));
547 else
548 WARN(1, "Invalid register access\n");
549
550 return 0;
551}
552
553static void sci_serial_out(struct uart_port *p, int offset, int value)
554{
555 const struct plat_sci_reg *reg = sci_getreg(p, offset);
556
557 if (reg->size == 8)
558 iowrite8(value, p->membase + (reg->offset << p->regshift));
559 else if (reg->size == 16)
560 iowrite16(value, p->membase + (reg->offset << p->regshift));
561 else
562 WARN(1, "Invalid register access\n");
563}
564
565static void sci_port_enable(struct sci_port *sci_port)
566{
567 unsigned int i;
568
569 if (!sci_port->port.dev)
570 return;
571
572 pm_runtime_get_sync(sci_port->port.dev);
573
574 for (i = 0; i < SCI_NUM_CLKS; i++) {
575 clk_prepare_enable(sci_port->clks[i]);
576 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
577 }
578 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
579}
580
581static void sci_port_disable(struct sci_port *sci_port)
582{
583 unsigned int i;
584
585 if (!sci_port->port.dev)
586 return;
587
588 for (i = SCI_NUM_CLKS; i-- > 0; )
589 clk_disable_unprepare(sci_port->clks[i]);
590
591 pm_runtime_put_sync(sci_port->port.dev);
592}
593
594static inline unsigned long port_rx_irq_mask(struct uart_port *port)
595{
596 /*
597 * Not all ports (such as SCIFA) will support REIE. Rather than
598 * special-casing the port type, we check the port initialization
599 * IRQ enable mask to see whether the IRQ is desired at all. If
600 * it's unset, it's logically inferred that there's no point in
601 * testing for it.
602 */
603 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
604}
605
606static void sci_start_tx(struct uart_port *port)
607{
608 struct sci_port *s = to_sci_port(port);
609 unsigned short ctrl;
610
611#ifdef CONFIG_SERIAL_SH_SCI_DMA
612 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
613 u16 new, scr = sci_serial_in(port, SCSCR);
614 if (s->chan_tx)
615 new = scr | SCSCR_TDRQE;
616 else
617 new = scr & ~SCSCR_TDRQE;
618 if (new != scr)
619 sci_serial_out(port, SCSCR, new);
620 }
621
622 if (s->chan_tx && !kfifo_is_empty(&port->state->port.xmit_fifo) &&
623 dma_submit_error(s->cookie_tx)) {
624 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
625 /* Switch irq from SCIF to DMA */
626 disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]);
627
628 s->cookie_tx = 0;
629 schedule_work(&s->work_tx);
630 }
631#endif
632
633 if (!s->chan_tx || s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE ||
634 port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
635 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
636 ctrl = sci_serial_in(port, SCSCR);
637
638 /*
639 * For SCI, TE (transmit enable) must be set after setting TIE
640 * (transmit interrupt enable) or in the same instruction to start
641 * the transmit process.
642 */
643 if (port->type == PORT_SCI)
644 ctrl |= SCSCR_TE;
645
646 sci_serial_out(port, SCSCR, ctrl | SCSCR_TIE);
647 }
648}
649
650static void sci_stop_tx(struct uart_port *port)
651{
652 unsigned short ctrl;
653
654 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
655 ctrl = sci_serial_in(port, SCSCR);
656
657 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
658 ctrl &= ~SCSCR_TDRQE;
659
660 ctrl &= ~SCSCR_TIE;
661
662 sci_serial_out(port, SCSCR, ctrl);
663
664#ifdef CONFIG_SERIAL_SH_SCI_DMA
665 if (to_sci_port(port)->chan_tx &&
666 !dma_submit_error(to_sci_port(port)->cookie_tx)) {
667 dmaengine_terminate_async(to_sci_port(port)->chan_tx);
668 to_sci_port(port)->cookie_tx = -EINVAL;
669 }
670#endif
671}
672
673static void sci_start_rx(struct uart_port *port)
674{
675 unsigned short ctrl;
676
677 ctrl = sci_serial_in(port, SCSCR) | port_rx_irq_mask(port);
678
679 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
680 ctrl &= ~SCSCR_RDRQE;
681
682 sci_serial_out(port, SCSCR, ctrl);
683}
684
685static void sci_stop_rx(struct uart_port *port)
686{
687 unsigned short ctrl;
688
689 ctrl = sci_serial_in(port, SCSCR);
690
691 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
692 ctrl &= ~SCSCR_RDRQE;
693
694 ctrl &= ~port_rx_irq_mask(port);
695
696 sci_serial_out(port, SCSCR, ctrl);
697}
698
699static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
700{
701 if (port->type == PORT_SCI) {
702 /* Just store the mask */
703 sci_serial_out(port, SCxSR, mask);
704 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
705 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
706 /* Only clear the status bits we want to clear */
707 sci_serial_out(port, SCxSR, sci_serial_in(port, SCxSR) & mask);
708 } else {
709 /* Store the mask, clear parity/framing errors */
710 sci_serial_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
711 }
712}
713
714#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
715 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
716
717#ifdef CONFIG_CONSOLE_POLL
718static int sci_poll_get_char(struct uart_port *port)
719{
720 unsigned short status;
721 int c;
722
723 do {
724 status = sci_serial_in(port, SCxSR);
725 if (status & SCxSR_ERRORS(port)) {
726 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
727 continue;
728 }
729 break;
730 } while (1);
731
732 if (!(status & SCxSR_RDxF(port)))
733 return NO_POLL_CHAR;
734
735 c = sci_serial_in(port, SCxRDR);
736
737 /* Dummy read */
738 sci_serial_in(port, SCxSR);
739 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
740
741 return c;
742}
743#endif
744
745static void sci_poll_put_char(struct uart_port *port, unsigned char c)
746{
747 unsigned short status;
748
749 do {
750 status = sci_serial_in(port, SCxSR);
751 } while (!(status & SCxSR_TDxE(port)));
752
753 sci_serial_out(port, SCxTDR, c);
754 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
755}
756#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
757 CONFIG_SERIAL_SH_SCI_EARLYCON */
758
759static void sci_init_pins(struct uart_port *port, unsigned int cflag)
760{
761 struct sci_port *s = to_sci_port(port);
762
763 /*
764 * Use port-specific handler if provided.
765 */
766 if (s->cfg->ops && s->cfg->ops->init_pins) {
767 s->cfg->ops->init_pins(port, cflag);
768 return;
769 }
770
771 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
772 u16 data = sci_serial_in(port, SCPDR);
773 u16 ctrl = sci_serial_in(port, SCPCR);
774
775 /* Enable RXD and TXD pin functions */
776 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
777 if (to_sci_port(port)->has_rtscts) {
778 /* RTS# is output, active low, unless autorts */
779 if (!(port->mctrl & TIOCM_RTS)) {
780 ctrl |= SCPCR_RTSC;
781 data |= SCPDR_RTSD;
782 } else if (!s->autorts) {
783 ctrl |= SCPCR_RTSC;
784 data &= ~SCPDR_RTSD;
785 } else {
786 /* Enable RTS# pin function */
787 ctrl &= ~SCPCR_RTSC;
788 }
789 /* Enable CTS# pin function */
790 ctrl &= ~SCPCR_CTSC;
791 }
792 sci_serial_out(port, SCPDR, data);
793 sci_serial_out(port, SCPCR, ctrl);
794 } else if (sci_getreg(port, SCSPTR)->size && s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE) {
795 u16 status = sci_serial_in(port, SCSPTR);
796
797 /* RTS# is always output; and active low, unless autorts */
798 status |= SCSPTR_RTSIO;
799 if (!(port->mctrl & TIOCM_RTS))
800 status |= SCSPTR_RTSDT;
801 else if (!s->autorts)
802 status &= ~SCSPTR_RTSDT;
803 /* CTS# and SCK are inputs */
804 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
805 sci_serial_out(port, SCSPTR, status);
806 }
807}
808
809static int sci_txfill(struct uart_port *port)
810{
811 struct sci_port *s = to_sci_port(port);
812 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
813 const struct plat_sci_reg *reg;
814
815 reg = sci_getreg(port, SCTFDR);
816 if (reg->size)
817 return sci_serial_in(port, SCTFDR) & fifo_mask;
818
819 reg = sci_getreg(port, SCFDR);
820 if (reg->size)
821 return sci_serial_in(port, SCFDR) >> 8;
822
823 return !(sci_serial_in(port, SCxSR) & SCI_TDRE);
824}
825
826static int sci_txroom(struct uart_port *port)
827{
828 return port->fifosize - sci_txfill(port);
829}
830
831static int sci_rxfill(struct uart_port *port)
832{
833 struct sci_port *s = to_sci_port(port);
834 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
835 const struct plat_sci_reg *reg;
836
837 reg = sci_getreg(port, SCRFDR);
838 if (reg->size)
839 return sci_serial_in(port, SCRFDR) & fifo_mask;
840
841 reg = sci_getreg(port, SCFDR);
842 if (reg->size)
843 return sci_serial_in(port, SCFDR) & fifo_mask;
844
845 return (sci_serial_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
846}
847
848/* ********************************************************************** *
849 * the interrupt related routines *
850 * ********************************************************************** */
851
852static void sci_transmit_chars(struct uart_port *port)
853{
854 struct tty_port *tport = &port->state->port;
855 unsigned int stopped = uart_tx_stopped(port);
856 struct sci_port *s = to_sci_port(port);
857 unsigned short status;
858 unsigned short ctrl;
859 int count;
860
861 status = sci_serial_in(port, SCxSR);
862 if (!(status & SCxSR_TDxE(port))) {
863 ctrl = sci_serial_in(port, SCSCR);
864 if (kfifo_is_empty(&tport->xmit_fifo))
865 ctrl &= ~SCSCR_TIE;
866 else
867 ctrl |= SCSCR_TIE;
868 sci_serial_out(port, SCSCR, ctrl);
869 return;
870 }
871
872 count = sci_txroom(port);
873
874 do {
875 unsigned char c;
876
877 if (port->x_char) {
878 c = port->x_char;
879 port->x_char = 0;
880 } else if (stopped || !kfifo_get(&tport->xmit_fifo, &c)) {
881 if (port->type == PORT_SCI &&
882 kfifo_is_empty(&tport->xmit_fifo)) {
883 ctrl = sci_serial_in(port, SCSCR);
884 ctrl &= ~SCSCR_TE;
885 sci_serial_out(port, SCSCR, ctrl);
886 return;
887 }
888 break;
889 }
890
891 sci_serial_out(port, SCxTDR, c);
892 s->tx_occurred = true;
893
894 port->icount.tx++;
895 } while (--count > 0);
896
897 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
898
899 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
900 uart_write_wakeup(port);
901 if (kfifo_is_empty(&tport->xmit_fifo)) {
902 if (port->type == PORT_SCI) {
903 ctrl = sci_serial_in(port, SCSCR);
904 ctrl &= ~SCSCR_TIE;
905 ctrl |= SCSCR_TEIE;
906 sci_serial_out(port, SCSCR, ctrl);
907 }
908
909 sci_stop_tx(port);
910 }
911}
912
913static void sci_receive_chars(struct uart_port *port)
914{
915 struct tty_port *tport = &port->state->port;
916 int i, count, copied = 0;
917 unsigned short status;
918 unsigned char flag;
919
920 status = sci_serial_in(port, SCxSR);
921 if (!(status & SCxSR_RDxF(port)))
922 return;
923
924 while (1) {
925 /* Don't copy more bytes than there is room for in the buffer */
926 count = tty_buffer_request_room(tport, sci_rxfill(port));
927
928 /* If for any reason we can't copy more data, we're done! */
929 if (count == 0)
930 break;
931
932 if (port->type == PORT_SCI) {
933 char c = sci_serial_in(port, SCxRDR);
934 if (uart_handle_sysrq_char(port, c))
935 count = 0;
936 else
937 tty_insert_flip_char(tport, c, TTY_NORMAL);
938 } else {
939 for (i = 0; i < count; i++) {
940 char c;
941
942 if (port->type == PORT_SCIF ||
943 port->type == PORT_HSCIF) {
944 status = sci_serial_in(port, SCxSR);
945 c = sci_serial_in(port, SCxRDR);
946 } else {
947 c = sci_serial_in(port, SCxRDR);
948 status = sci_serial_in(port, SCxSR);
949 }
950 if (uart_handle_sysrq_char(port, c)) {
951 count--; i--;
952 continue;
953 }
954
955 /* Store data and status */
956 if (status & SCxSR_FER(port)) {
957 flag = TTY_FRAME;
958 port->icount.frame++;
959 } else if (status & SCxSR_PER(port)) {
960 flag = TTY_PARITY;
961 port->icount.parity++;
962 } else
963 flag = TTY_NORMAL;
964
965 tty_insert_flip_char(tport, c, flag);
966 }
967 }
968
969 sci_serial_in(port, SCxSR); /* dummy read */
970 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
971
972 copied += count;
973 port->icount.rx += count;
974 }
975
976 if (copied) {
977 /* Tell the rest of the system the news. New characters! */
978 tty_flip_buffer_push(tport);
979 } else {
980 /* TTY buffers full; read from RX reg to prevent lockup */
981 sci_serial_in(port, SCxRDR);
982 sci_serial_in(port, SCxSR); /* dummy read */
983 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
984 }
985}
986
987static int sci_handle_errors(struct uart_port *port)
988{
989 int copied = 0;
990 unsigned short status = sci_serial_in(port, SCxSR);
991 struct tty_port *tport = &port->state->port;
992 struct sci_port *s = to_sci_port(port);
993
994 /* Handle overruns */
995 if (status & s->params->overrun_mask) {
996 port->icount.overrun++;
997
998 /* overrun error */
999 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
1000 copied++;
1001 }
1002
1003 if (status & SCxSR_FER(port)) {
1004 /* frame error */
1005 port->icount.frame++;
1006
1007 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
1008 copied++;
1009 }
1010
1011 if (status & SCxSR_PER(port)) {
1012 /* parity error */
1013 port->icount.parity++;
1014
1015 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
1016 copied++;
1017 }
1018
1019 if (copied)
1020 tty_flip_buffer_push(tport);
1021
1022 return copied;
1023}
1024
1025static int sci_handle_fifo_overrun(struct uart_port *port)
1026{
1027 struct tty_port *tport = &port->state->port;
1028 struct sci_port *s = to_sci_port(port);
1029 const struct plat_sci_reg *reg;
1030 int copied = 0;
1031 u16 status;
1032
1033 reg = sci_getreg(port, s->params->overrun_reg);
1034 if (!reg->size)
1035 return 0;
1036
1037 status = sci_serial_in(port, s->params->overrun_reg);
1038 if (status & s->params->overrun_mask) {
1039 status &= ~s->params->overrun_mask;
1040 sci_serial_out(port, s->params->overrun_reg, status);
1041
1042 port->icount.overrun++;
1043
1044 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1045 tty_flip_buffer_push(tport);
1046 copied++;
1047 }
1048
1049 return copied;
1050}
1051
1052static int sci_handle_breaks(struct uart_port *port)
1053{
1054 int copied = 0;
1055 unsigned short status = sci_serial_in(port, SCxSR);
1056 struct tty_port *tport = &port->state->port;
1057
1058 if (uart_handle_break(port))
1059 return 0;
1060
1061 if (status & SCxSR_BRK(port)) {
1062 port->icount.brk++;
1063
1064 /* Notify of BREAK */
1065 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1066 copied++;
1067 }
1068
1069 if (copied)
1070 tty_flip_buffer_push(tport);
1071
1072 copied += sci_handle_fifo_overrun(port);
1073
1074 return copied;
1075}
1076
1077static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1078{
1079 unsigned int bits;
1080
1081 if (rx_trig >= port->fifosize)
1082 rx_trig = port->fifosize - 1;
1083 if (rx_trig < 1)
1084 rx_trig = 1;
1085
1086 /* HSCIF can be set to an arbitrary level. */
1087 if (sci_getreg(port, HSRTRGR)->size) {
1088 sci_serial_out(port, HSRTRGR, rx_trig);
1089 return rx_trig;
1090 }
1091
1092 switch (port->type) {
1093 case PORT_SCIF:
1094 if (rx_trig < 4) {
1095 bits = 0;
1096 rx_trig = 1;
1097 } else if (rx_trig < 8) {
1098 bits = SCFCR_RTRG0;
1099 rx_trig = 4;
1100 } else if (rx_trig < 14) {
1101 bits = SCFCR_RTRG1;
1102 rx_trig = 8;
1103 } else {
1104 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1105 rx_trig = 14;
1106 }
1107 break;
1108 case PORT_SCIFA:
1109 case PORT_SCIFB:
1110 if (rx_trig < 16) {
1111 bits = 0;
1112 rx_trig = 1;
1113 } else if (rx_trig < 32) {
1114 bits = SCFCR_RTRG0;
1115 rx_trig = 16;
1116 } else if (rx_trig < 48) {
1117 bits = SCFCR_RTRG1;
1118 rx_trig = 32;
1119 } else {
1120 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1121 rx_trig = 48;
1122 }
1123 break;
1124 default:
1125 WARN(1, "unknown FIFO configuration");
1126 return 1;
1127 }
1128
1129 sci_serial_out(port, SCFCR,
1130 (sci_serial_in(port, SCFCR) &
1131 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1132
1133 return rx_trig;
1134}
1135
1136static int scif_rtrg_enabled(struct uart_port *port)
1137{
1138 if (sci_getreg(port, HSRTRGR)->size)
1139 return sci_serial_in(port, HSRTRGR) != 0;
1140 else
1141 return (sci_serial_in(port, SCFCR) &
1142 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1143}
1144
1145static void rx_fifo_timer_fn(struct timer_list *t)
1146{
1147 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
1148 struct uart_port *port = &s->port;
1149
1150 dev_dbg(port->dev, "Rx timed out\n");
1151 scif_set_rtrg(port, 1);
1152}
1153
1154static ssize_t rx_fifo_trigger_show(struct device *dev,
1155 struct device_attribute *attr, char *buf)
1156{
1157 struct uart_port *port = dev_get_drvdata(dev);
1158 struct sci_port *sci = to_sci_port(port);
1159
1160 return sprintf(buf, "%d\n", sci->rx_trigger);
1161}
1162
1163static ssize_t rx_fifo_trigger_store(struct device *dev,
1164 struct device_attribute *attr,
1165 const char *buf, size_t count)
1166{
1167 struct uart_port *port = dev_get_drvdata(dev);
1168 struct sci_port *sci = to_sci_port(port);
1169 int ret;
1170 long r;
1171
1172 ret = kstrtol(buf, 0, &r);
1173 if (ret)
1174 return ret;
1175
1176 sci->rx_trigger = scif_set_rtrg(port, r);
1177 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1178 scif_set_rtrg(port, 1);
1179
1180 return count;
1181}
1182
1183static DEVICE_ATTR_RW(rx_fifo_trigger);
1184
1185static ssize_t rx_fifo_timeout_show(struct device *dev,
1186 struct device_attribute *attr,
1187 char *buf)
1188{
1189 struct uart_port *port = dev_get_drvdata(dev);
1190 struct sci_port *sci = to_sci_port(port);
1191 int v;
1192
1193 if (port->type == PORT_HSCIF)
1194 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1195 else
1196 v = sci->rx_fifo_timeout;
1197
1198 return sprintf(buf, "%d\n", v);
1199}
1200
1201static ssize_t rx_fifo_timeout_store(struct device *dev,
1202 struct device_attribute *attr,
1203 const char *buf,
1204 size_t count)
1205{
1206 struct uart_port *port = dev_get_drvdata(dev);
1207 struct sci_port *sci = to_sci_port(port);
1208 int ret;
1209 long r;
1210
1211 ret = kstrtol(buf, 0, &r);
1212 if (ret)
1213 return ret;
1214
1215 if (port->type == PORT_HSCIF) {
1216 if (r < 0 || r > 3)
1217 return -EINVAL;
1218 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1219 } else {
1220 sci->rx_fifo_timeout = r;
1221 scif_set_rtrg(port, 1);
1222 if (r > 0)
1223 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1224 }
1225
1226 return count;
1227}
1228
1229static DEVICE_ATTR_RW(rx_fifo_timeout);
1230
1231
1232#ifdef CONFIG_SERIAL_SH_SCI_DMA
1233static void sci_dma_tx_complete(void *arg)
1234{
1235 struct sci_port *s = arg;
1236 struct uart_port *port = &s->port;
1237 struct tty_port *tport = &port->state->port;
1238 unsigned long flags;
1239
1240 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1241
1242 uart_port_lock_irqsave(port, &flags);
1243
1244 uart_xmit_advance(port, s->tx_dma_len);
1245
1246 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
1247 uart_write_wakeup(port);
1248
1249 s->tx_occurred = true;
1250
1251 if (!kfifo_is_empty(&tport->xmit_fifo)) {
1252 s->cookie_tx = 0;
1253 schedule_work(&s->work_tx);
1254 } else {
1255 s->cookie_tx = -EINVAL;
1256 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1257 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1258 u16 ctrl = sci_serial_in(port, SCSCR);
1259 sci_serial_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1260 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1261 /* Switch irq from DMA to SCIF */
1262 dmaengine_pause(s->chan_tx_saved);
1263 enable_irq(s->irqs[SCIx_TXI_IRQ]);
1264 }
1265 }
1266 }
1267
1268 uart_port_unlock_irqrestore(port, flags);
1269}
1270
1271/* Locking: called with port lock held */
1272static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1273{
1274 struct uart_port *port = &s->port;
1275 struct tty_port *tport = &port->state->port;
1276 int copied;
1277
1278 copied = tty_insert_flip_string(tport, buf, count);
1279 if (copied < count)
1280 port->icount.buf_overrun++;
1281
1282 port->icount.rx += copied;
1283
1284 return copied;
1285}
1286
1287static int sci_dma_rx_find_active(struct sci_port *s)
1288{
1289 unsigned int i;
1290
1291 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1292 if (s->active_rx == s->cookie_rx[i])
1293 return i;
1294
1295 return -1;
1296}
1297
1298/* Must only be called with uart_port_lock taken */
1299static void sci_dma_rx_chan_invalidate(struct sci_port *s)
1300{
1301 unsigned int i;
1302
1303 s->chan_rx = NULL;
1304 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1305 s->cookie_rx[i] = -EINVAL;
1306 s->active_rx = 0;
1307}
1308
1309static void sci_dma_rx_release(struct sci_port *s)
1310{
1311 struct dma_chan *chan = s->chan_rx_saved;
1312 struct uart_port *port = &s->port;
1313 unsigned long flags;
1314
1315 uart_port_lock_irqsave(port, &flags);
1316 s->chan_rx_saved = NULL;
1317 sci_dma_rx_chan_invalidate(s);
1318 uart_port_unlock_irqrestore(port, flags);
1319
1320 dmaengine_terminate_sync(chan);
1321 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1322 sg_dma_address(&s->sg_rx[0]));
1323 dma_release_channel(chan);
1324}
1325
1326static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1327{
1328 long sec = usec / 1000000;
1329 long nsec = (usec % 1000000) * 1000;
1330 ktime_t t = ktime_set(sec, nsec);
1331
1332 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1333}
1334
1335static void sci_dma_rx_reenable_irq(struct sci_port *s)
1336{
1337 struct uart_port *port = &s->port;
1338 u16 scr;
1339
1340 /* Direct new serial port interrupts back to CPU */
1341 scr = sci_serial_in(port, SCSCR);
1342 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1343 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1344 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1345 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1346 scif_set_rtrg(port, s->rx_trigger);
1347 else
1348 scr &= ~SCSCR_RDRQE;
1349 }
1350 sci_serial_out(port, SCSCR, scr | SCSCR_RIE);
1351}
1352
1353static void sci_dma_rx_complete(void *arg)
1354{
1355 struct sci_port *s = arg;
1356 struct dma_chan *chan = s->chan_rx;
1357 struct uart_port *port = &s->port;
1358 struct dma_async_tx_descriptor *desc;
1359 unsigned long flags;
1360 int active, count = 0;
1361
1362 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1363 s->active_rx);
1364
1365 hrtimer_cancel(&s->rx_timer);
1366
1367 uart_port_lock_irqsave(port, &flags);
1368
1369 active = sci_dma_rx_find_active(s);
1370 if (active >= 0)
1371 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1372
1373 if (count)
1374 tty_flip_buffer_push(&port->state->port);
1375
1376 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1377 DMA_DEV_TO_MEM,
1378 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1379 if (!desc)
1380 goto fail;
1381
1382 desc->callback = sci_dma_rx_complete;
1383 desc->callback_param = s;
1384 s->cookie_rx[active] = dmaengine_submit(desc);
1385 if (dma_submit_error(s->cookie_rx[active]))
1386 goto fail;
1387
1388 s->active_rx = s->cookie_rx[!active];
1389
1390 dma_async_issue_pending(chan);
1391
1392 uart_port_unlock_irqrestore(port, flags);
1393 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1394 __func__, s->cookie_rx[active], active, s->active_rx);
1395
1396 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1397
1398 return;
1399
1400fail:
1401 /* Switch to PIO */
1402 dmaengine_terminate_async(chan);
1403 sci_dma_rx_chan_invalidate(s);
1404 sci_dma_rx_reenable_irq(s);
1405 uart_port_unlock_irqrestore(port, flags);
1406 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1407}
1408
1409static void sci_dma_tx_release(struct sci_port *s)
1410{
1411 struct dma_chan *chan = s->chan_tx_saved;
1412
1413 cancel_work_sync(&s->work_tx);
1414 s->chan_tx_saved = s->chan_tx = NULL;
1415 s->cookie_tx = -EINVAL;
1416 dmaengine_terminate_sync(chan);
1417 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1418 DMA_TO_DEVICE);
1419 dma_release_channel(chan);
1420}
1421
1422static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
1423{
1424 struct dma_chan *chan = s->chan_rx;
1425 struct uart_port *port = &s->port;
1426 unsigned long flags;
1427 int i;
1428
1429 for (i = 0; i < 2; i++) {
1430 struct scatterlist *sg = &s->sg_rx[i];
1431 struct dma_async_tx_descriptor *desc;
1432
1433 desc = dmaengine_prep_slave_sg(chan,
1434 sg, 1, DMA_DEV_TO_MEM,
1435 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1436 if (!desc)
1437 goto fail;
1438
1439 desc->callback = sci_dma_rx_complete;
1440 desc->callback_param = s;
1441 s->cookie_rx[i] = dmaengine_submit(desc);
1442 if (dma_submit_error(s->cookie_rx[i]))
1443 goto fail;
1444
1445 }
1446
1447 s->active_rx = s->cookie_rx[0];
1448
1449 dma_async_issue_pending(chan);
1450 return 0;
1451
1452fail:
1453 /* Switch to PIO */
1454 if (!port_lock_held)
1455 uart_port_lock_irqsave(port, &flags);
1456 if (i)
1457 dmaengine_terminate_async(chan);
1458 sci_dma_rx_chan_invalidate(s);
1459 sci_start_rx(port);
1460 if (!port_lock_held)
1461 uart_port_unlock_irqrestore(port, flags);
1462 return -EAGAIN;
1463}
1464
1465static void sci_dma_tx_work_fn(struct work_struct *work)
1466{
1467 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1468 struct dma_async_tx_descriptor *desc;
1469 struct dma_chan *chan = s->chan_tx;
1470 struct uart_port *port = &s->port;
1471 struct tty_port *tport = &port->state->port;
1472 unsigned long flags;
1473 unsigned int tail;
1474 dma_addr_t buf;
1475
1476 /*
1477 * DMA is idle now.
1478 * Port xmit buffer is already mapped, and it is one page... Just adjust
1479 * offsets and lengths. Since it is a circular buffer, we have to
1480 * transmit till the end, and then the rest. Take the port lock to get a
1481 * consistent xmit buffer state.
1482 */
1483 uart_port_lock_irq(port);
1484 s->tx_dma_len = kfifo_out_linear(&tport->xmit_fifo, &tail,
1485 UART_XMIT_SIZE);
1486 buf = s->tx_dma_addr + tail;
1487 if (!s->tx_dma_len) {
1488 /* Transmit buffer has been flushed */
1489 uart_port_unlock_irq(port);
1490 return;
1491 }
1492
1493 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1494 DMA_MEM_TO_DEV,
1495 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1496 if (!desc) {
1497 uart_port_unlock_irq(port);
1498 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1499 goto switch_to_pio;
1500 }
1501
1502 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1503 DMA_TO_DEVICE);
1504
1505 desc->callback = sci_dma_tx_complete;
1506 desc->callback_param = s;
1507 s->cookie_tx = dmaengine_submit(desc);
1508 if (dma_submit_error(s->cookie_tx)) {
1509 uart_port_unlock_irq(port);
1510 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1511 goto switch_to_pio;
1512 }
1513
1514 uart_port_unlock_irq(port);
1515 dev_dbg(port->dev, "%s: %p: %u, cookie %d\n",
1516 __func__, tport->xmit_buf, tail, s->cookie_tx);
1517
1518 dma_async_issue_pending(chan);
1519 return;
1520
1521switch_to_pio:
1522 uart_port_lock_irqsave(port, &flags);
1523 s->chan_tx = NULL;
1524 sci_start_tx(port);
1525 uart_port_unlock_irqrestore(port, flags);
1526 return;
1527}
1528
1529static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
1530{
1531 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1532 struct dma_chan *chan = s->chan_rx;
1533 struct uart_port *port = &s->port;
1534 struct dma_tx_state state;
1535 enum dma_status status;
1536 unsigned long flags;
1537 unsigned int read;
1538 int active, count;
1539
1540 dev_dbg(port->dev, "DMA Rx timed out\n");
1541
1542 uart_port_lock_irqsave(port, &flags);
1543
1544 active = sci_dma_rx_find_active(s);
1545 if (active < 0) {
1546 uart_port_unlock_irqrestore(port, flags);
1547 return HRTIMER_NORESTART;
1548 }
1549
1550 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1551 if (status == DMA_COMPLETE) {
1552 uart_port_unlock_irqrestore(port, flags);
1553 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1554 s->active_rx, active);
1555
1556 /* Let packet complete handler take care of the packet */
1557 return HRTIMER_NORESTART;
1558 }
1559
1560 dmaengine_pause(chan);
1561
1562 /*
1563 * sometimes DMA transfer doesn't stop even if it is stopped and
1564 * data keeps on coming until transaction is complete so check
1565 * for DMA_COMPLETE again
1566 * Let packet complete handler take care of the packet
1567 */
1568 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1569 if (status == DMA_COMPLETE) {
1570 uart_port_unlock_irqrestore(port, flags);
1571 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1572 return HRTIMER_NORESTART;
1573 }
1574
1575 /* Handle incomplete DMA receive */
1576 dmaengine_terminate_async(s->chan_rx);
1577 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1578
1579 if (read) {
1580 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1581 if (count)
1582 tty_flip_buffer_push(&port->state->port);
1583 }
1584
1585 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1586 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1587 sci_dma_rx_submit(s, true);
1588
1589 sci_dma_rx_reenable_irq(s);
1590
1591 uart_port_unlock_irqrestore(port, flags);
1592
1593 return HRTIMER_NORESTART;
1594}
1595
1596static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1597 enum dma_transfer_direction dir)
1598{
1599 struct dma_chan *chan;
1600 struct dma_slave_config cfg;
1601 int ret;
1602
1603 chan = dma_request_chan(port->dev, dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1604 if (IS_ERR(chan)) {
1605 dev_dbg(port->dev, "dma_request_chan failed\n");
1606 return NULL;
1607 }
1608
1609 memset(&cfg, 0, sizeof(cfg));
1610 cfg.direction = dir;
1611 cfg.dst_addr = port->mapbase +
1612 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1613 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1614 cfg.src_addr = port->mapbase +
1615 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1616 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1617
1618 ret = dmaengine_slave_config(chan, &cfg);
1619 if (ret) {
1620 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1621 dma_release_channel(chan);
1622 return NULL;
1623 }
1624
1625 return chan;
1626}
1627
1628static void sci_request_dma(struct uart_port *port)
1629{
1630 struct sci_port *s = to_sci_port(port);
1631 struct tty_port *tport = &port->state->port;
1632 struct dma_chan *chan;
1633
1634 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1635
1636 /*
1637 * DMA on console may interfere with Kernel log messages which use
1638 * plain putchar(). So, simply don't use it with a console.
1639 */
1640 if (uart_console(port))
1641 return;
1642
1643 if (!port->dev->of_node)
1644 return;
1645
1646 s->cookie_tx = -EINVAL;
1647
1648 /*
1649 * Don't request a dma channel if no channel was specified
1650 * in the device tree.
1651 */
1652 if (!of_property_present(port->dev->of_node, "dmas"))
1653 return;
1654
1655 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1656 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1657 if (chan) {
1658 /* UART circular tx buffer is an aligned page. */
1659 s->tx_dma_addr = dma_map_single(chan->device->dev,
1660 tport->xmit_buf,
1661 UART_XMIT_SIZE,
1662 DMA_TO_DEVICE);
1663 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1664 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1665 dma_release_channel(chan);
1666 } else {
1667 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1668 __func__, UART_XMIT_SIZE,
1669 tport->xmit_buf, &s->tx_dma_addr);
1670
1671 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
1672 s->chan_tx_saved = s->chan_tx = chan;
1673 }
1674 }
1675
1676 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1677 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1678 if (chan) {
1679 unsigned int i;
1680 dma_addr_t dma;
1681 void *buf;
1682
1683 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1684 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1685 &dma, GFP_KERNEL);
1686 if (!buf) {
1687 dev_warn(port->dev,
1688 "Failed to allocate Rx dma buffer, using PIO\n");
1689 dma_release_channel(chan);
1690 return;
1691 }
1692
1693 for (i = 0; i < 2; i++) {
1694 struct scatterlist *sg = &s->sg_rx[i];
1695
1696 sg_init_table(sg, 1);
1697 s->rx_buf[i] = buf;
1698 sg_dma_address(sg) = dma;
1699 sg_dma_len(sg) = s->buf_len_rx;
1700
1701 buf += s->buf_len_rx;
1702 dma += s->buf_len_rx;
1703 }
1704
1705 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1706 s->rx_timer.function = sci_dma_rx_timer_fn;
1707
1708 s->chan_rx_saved = s->chan_rx = chan;
1709
1710 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1711 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1712 sci_dma_rx_submit(s, false);
1713 }
1714}
1715
1716static void sci_free_dma(struct uart_port *port)
1717{
1718 struct sci_port *s = to_sci_port(port);
1719
1720 if (s->chan_tx_saved)
1721 sci_dma_tx_release(s);
1722 if (s->chan_rx_saved)
1723 sci_dma_rx_release(s);
1724}
1725
1726static void sci_flush_buffer(struct uart_port *port)
1727{
1728 struct sci_port *s = to_sci_port(port);
1729
1730 /*
1731 * In uart_flush_buffer(), the xmit circular buffer has just been
1732 * cleared, so we have to reset tx_dma_len accordingly, and stop any
1733 * pending transfers
1734 */
1735 s->tx_dma_len = 0;
1736 if (s->chan_tx) {
1737 dmaengine_terminate_async(s->chan_tx);
1738 s->cookie_tx = -EINVAL;
1739 }
1740}
1741
1742static void sci_dma_check_tx_occurred(struct sci_port *s)
1743{
1744 struct dma_tx_state state;
1745 enum dma_status status;
1746
1747 if (!s->chan_tx)
1748 return;
1749
1750 status = dmaengine_tx_status(s->chan_tx, s->cookie_tx, &state);
1751 if (status == DMA_COMPLETE || status == DMA_IN_PROGRESS)
1752 s->tx_occurred = true;
1753}
1754#else /* !CONFIG_SERIAL_SH_SCI_DMA */
1755static inline void sci_request_dma(struct uart_port *port)
1756{
1757}
1758
1759static inline void sci_free_dma(struct uart_port *port)
1760{
1761}
1762
1763static void sci_dma_check_tx_occurred(struct sci_port *s)
1764{
1765}
1766
1767#define sci_flush_buffer NULL
1768#endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1769
1770static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1771{
1772 struct uart_port *port = ptr;
1773 struct sci_port *s = to_sci_port(port);
1774
1775#ifdef CONFIG_SERIAL_SH_SCI_DMA
1776 if (s->chan_rx) {
1777 u16 scr = sci_serial_in(port, SCSCR);
1778 u16 ssr = sci_serial_in(port, SCxSR);
1779
1780 /* Disable future Rx interrupts */
1781 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1782 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1783 disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]);
1784 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1785 scif_set_rtrg(port, 1);
1786 scr |= SCSCR_RIE;
1787 } else {
1788 scr |= SCSCR_RDRQE;
1789 }
1790 } else {
1791 if (sci_dma_rx_submit(s, false) < 0)
1792 goto handle_pio;
1793
1794 scr &= ~SCSCR_RIE;
1795 }
1796 sci_serial_out(port, SCSCR, scr);
1797 /* Clear current interrupt */
1798 sci_serial_out(port, SCxSR,
1799 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1800 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1801 jiffies, s->rx_timeout);
1802 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1803
1804 return IRQ_HANDLED;
1805 }
1806
1807handle_pio:
1808#endif
1809
1810 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1811 if (!scif_rtrg_enabled(port))
1812 scif_set_rtrg(port, s->rx_trigger);
1813
1814 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1815 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1816 }
1817
1818 /* I think sci_receive_chars has to be called irrespective
1819 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1820 * to be disabled?
1821 */
1822 sci_receive_chars(port);
1823
1824 return IRQ_HANDLED;
1825}
1826
1827static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1828{
1829 struct uart_port *port = ptr;
1830 unsigned long flags;
1831
1832 uart_port_lock_irqsave(port, &flags);
1833 sci_transmit_chars(port);
1834 uart_port_unlock_irqrestore(port, flags);
1835
1836 return IRQ_HANDLED;
1837}
1838
1839static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr)
1840{
1841 struct uart_port *port = ptr;
1842 unsigned long flags;
1843 unsigned short ctrl;
1844
1845 if (port->type != PORT_SCI)
1846 return sci_tx_interrupt(irq, ptr);
1847
1848 uart_port_lock_irqsave(port, &flags);
1849 ctrl = sci_serial_in(port, SCSCR);
1850 ctrl &= ~(SCSCR_TE | SCSCR_TEIE);
1851 sci_serial_out(port, SCSCR, ctrl);
1852 uart_port_unlock_irqrestore(port, flags);
1853
1854 return IRQ_HANDLED;
1855}
1856
1857static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1858{
1859 struct uart_port *port = ptr;
1860
1861 /* Handle BREAKs */
1862 sci_handle_breaks(port);
1863
1864 /* drop invalid character received before break was detected */
1865 sci_serial_in(port, SCxRDR);
1866
1867 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1868
1869 return IRQ_HANDLED;
1870}
1871
1872static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1873{
1874 struct uart_port *port = ptr;
1875 struct sci_port *s = to_sci_port(port);
1876
1877 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
1878 /* Break and Error interrupts are muxed */
1879 unsigned short ssr_status = sci_serial_in(port, SCxSR);
1880
1881 /* Break Interrupt */
1882 if (ssr_status & SCxSR_BRK(port))
1883 sci_br_interrupt(irq, ptr);
1884
1885 /* Break only? */
1886 if (!(ssr_status & SCxSR_ERRORS(port)))
1887 return IRQ_HANDLED;
1888 }
1889
1890 /* Handle errors */
1891 if (port->type == PORT_SCI) {
1892 if (sci_handle_errors(port)) {
1893 /* discard character in rx buffer */
1894 sci_serial_in(port, SCxSR);
1895 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1896 }
1897 } else {
1898 sci_handle_fifo_overrun(port);
1899 if (!s->chan_rx)
1900 sci_receive_chars(port);
1901 }
1902
1903 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1904
1905 /* Kick the transmission */
1906 if (!s->chan_tx)
1907 sci_tx_interrupt(irq, ptr);
1908
1909 return IRQ_HANDLED;
1910}
1911
1912static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1913{
1914 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1915 struct uart_port *port = ptr;
1916 struct sci_port *s = to_sci_port(port);
1917 irqreturn_t ret = IRQ_NONE;
1918
1919 ssr_status = sci_serial_in(port, SCxSR);
1920 scr_status = sci_serial_in(port, SCSCR);
1921 if (s->params->overrun_reg == SCxSR)
1922 orer_status = ssr_status;
1923 else if (sci_getreg(port, s->params->overrun_reg)->size)
1924 orer_status = sci_serial_in(port, s->params->overrun_reg);
1925
1926 err_enabled = scr_status & port_rx_irq_mask(port);
1927
1928 /* Tx Interrupt */
1929 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1930 !s->chan_tx)
1931 ret = sci_tx_interrupt(irq, ptr);
1932
1933 /*
1934 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1935 * DR flags
1936 */
1937 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1938 (scr_status & SCSCR_RIE))
1939 ret = sci_rx_interrupt(irq, ptr);
1940
1941 /* Error Interrupt */
1942 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1943 ret = sci_er_interrupt(irq, ptr);
1944
1945 /* Break Interrupt */
1946 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] &&
1947 (ssr_status & SCxSR_BRK(port)) && err_enabled)
1948 ret = sci_br_interrupt(irq, ptr);
1949
1950 /* Overrun Interrupt */
1951 if (orer_status & s->params->overrun_mask) {
1952 sci_handle_fifo_overrun(port);
1953 ret = IRQ_HANDLED;
1954 }
1955
1956 return ret;
1957}
1958
1959static const struct sci_irq_desc {
1960 const char *desc;
1961 irq_handler_t handler;
1962} sci_irq_desc[] = {
1963 /*
1964 * Split out handlers, the default case.
1965 */
1966 [SCIx_ERI_IRQ] = {
1967 .desc = "rx err",
1968 .handler = sci_er_interrupt,
1969 },
1970
1971 [SCIx_RXI_IRQ] = {
1972 .desc = "rx full",
1973 .handler = sci_rx_interrupt,
1974 },
1975
1976 [SCIx_TXI_IRQ] = {
1977 .desc = "tx empty",
1978 .handler = sci_tx_interrupt,
1979 },
1980
1981 [SCIx_BRI_IRQ] = {
1982 .desc = "break",
1983 .handler = sci_br_interrupt,
1984 },
1985
1986 [SCIx_DRI_IRQ] = {
1987 .desc = "rx ready",
1988 .handler = sci_rx_interrupt,
1989 },
1990
1991 [SCIx_TEI_IRQ] = {
1992 .desc = "tx end",
1993 .handler = sci_tx_end_interrupt,
1994 },
1995
1996 /*
1997 * Special muxed handler.
1998 */
1999 [SCIx_MUX_IRQ] = {
2000 .desc = "mux",
2001 .handler = sci_mpxed_interrupt,
2002 },
2003};
2004
2005static int sci_request_irq(struct sci_port *port)
2006{
2007 struct uart_port *up = &port->port;
2008 int i, j, w, ret = 0;
2009
2010 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
2011 const struct sci_irq_desc *desc;
2012 int irq;
2013
2014 /* Check if already registered (muxed) */
2015 for (w = 0; w < i; w++)
2016 if (port->irqs[w] == port->irqs[i])
2017 w = i + 1;
2018 if (w > i)
2019 continue;
2020
2021 if (SCIx_IRQ_IS_MUXED(port)) {
2022 i = SCIx_MUX_IRQ;
2023 irq = up->irq;
2024 } else {
2025 irq = port->irqs[i];
2026
2027 /*
2028 * Certain port types won't support all of the
2029 * available interrupt sources.
2030 */
2031 if (unlikely(irq < 0))
2032 continue;
2033 }
2034
2035 desc = sci_irq_desc + i;
2036 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
2037 dev_name(up->dev), desc->desc);
2038 if (!port->irqstr[j]) {
2039 ret = -ENOMEM;
2040 goto out_nomem;
2041 }
2042
2043 ret = request_irq(irq, desc->handler, up->irqflags,
2044 port->irqstr[j], port);
2045 if (unlikely(ret)) {
2046 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
2047 goto out_noirq;
2048 }
2049 }
2050
2051 return 0;
2052
2053out_noirq:
2054 while (--i >= 0)
2055 free_irq(port->irqs[i], port);
2056
2057out_nomem:
2058 while (--j >= 0)
2059 kfree(port->irqstr[j]);
2060
2061 return ret;
2062}
2063
2064static void sci_free_irq(struct sci_port *port)
2065{
2066 int i, j;
2067
2068 /*
2069 * Intentionally in reverse order so we iterate over the muxed
2070 * IRQ first.
2071 */
2072 for (i = 0; i < SCIx_NR_IRQS; i++) {
2073 int irq = port->irqs[i];
2074
2075 /*
2076 * Certain port types won't support all of the available
2077 * interrupt sources.
2078 */
2079 if (unlikely(irq < 0))
2080 continue;
2081
2082 /* Check if already freed (irq was muxed) */
2083 for (j = 0; j < i; j++)
2084 if (port->irqs[j] == irq)
2085 j = i + 1;
2086 if (j > i)
2087 continue;
2088
2089 free_irq(port->irqs[i], port);
2090 kfree(port->irqstr[i]);
2091
2092 if (SCIx_IRQ_IS_MUXED(port)) {
2093 /* If there's only one IRQ, we're done. */
2094 return;
2095 }
2096 }
2097}
2098
2099static unsigned int sci_tx_empty(struct uart_port *port)
2100{
2101 unsigned short status = sci_serial_in(port, SCxSR);
2102 unsigned short in_tx_fifo = sci_txfill(port);
2103 struct sci_port *s = to_sci_port(port);
2104
2105 sci_dma_check_tx_occurred(s);
2106
2107 if (!s->tx_occurred)
2108 return TIOCSER_TEMT;
2109
2110 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
2111}
2112
2113static void sci_set_rts(struct uart_port *port, bool state)
2114{
2115 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2116 u16 data = sci_serial_in(port, SCPDR);
2117
2118 /* Active low */
2119 if (state)
2120 data &= ~SCPDR_RTSD;
2121 else
2122 data |= SCPDR_RTSD;
2123 sci_serial_out(port, SCPDR, data);
2124
2125 /* RTS# is output */
2126 sci_serial_out(port, SCPCR,
2127 sci_serial_in(port, SCPCR) | SCPCR_RTSC);
2128 } else if (sci_getreg(port, SCSPTR)->size) {
2129 u16 ctrl = sci_serial_in(port, SCSPTR);
2130
2131 /* Active low */
2132 if (state)
2133 ctrl &= ~SCSPTR_RTSDT;
2134 else
2135 ctrl |= SCSPTR_RTSDT;
2136 sci_serial_out(port, SCSPTR, ctrl);
2137 }
2138}
2139
2140static bool sci_get_cts(struct uart_port *port)
2141{
2142 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2143 /* Active low */
2144 return !(sci_serial_in(port, SCPDR) & SCPDR_CTSD);
2145 } else if (sci_getreg(port, SCSPTR)->size) {
2146 /* Active low */
2147 return !(sci_serial_in(port, SCSPTR) & SCSPTR_CTSDT);
2148 }
2149
2150 return true;
2151}
2152
2153/*
2154 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
2155 * CTS/RTS is supported in hardware by at least one port and controlled
2156 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
2157 * handled via the ->init_pins() op, which is a bit of a one-way street,
2158 * lacking any ability to defer pin control -- this will later be
2159 * converted over to the GPIO framework).
2160 *
2161 * Other modes (such as loopback) are supported generically on certain
2162 * port types, but not others. For these it's sufficient to test for the
2163 * existence of the support register and simply ignore the port type.
2164 */
2165static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2166{
2167 struct sci_port *s = to_sci_port(port);
2168
2169 if (mctrl & TIOCM_LOOP) {
2170 const struct plat_sci_reg *reg;
2171
2172 /*
2173 * Standard loopback mode for SCFCR ports.
2174 */
2175 reg = sci_getreg(port, SCFCR);
2176 if (reg->size)
2177 sci_serial_out(port, SCFCR,
2178 sci_serial_in(port, SCFCR) | SCFCR_LOOP);
2179 }
2180
2181 mctrl_gpio_set(s->gpios, mctrl);
2182
2183 if (!s->has_rtscts)
2184 return;
2185
2186 if (!(mctrl & TIOCM_RTS)) {
2187 /* Disable Auto RTS */
2188 if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE)
2189 sci_serial_out(port, SCFCR,
2190 sci_serial_in(port, SCFCR) & ~SCFCR_MCE);
2191
2192 /* Clear RTS */
2193 sci_set_rts(port, 0);
2194 } else if (s->autorts) {
2195 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2196 /* Enable RTS# pin function */
2197 sci_serial_out(port, SCPCR,
2198 sci_serial_in(port, SCPCR) & ~SCPCR_RTSC);
2199 }
2200
2201 /* Enable Auto RTS */
2202 if (s->cfg->regtype != SCIx_RZV2H_SCIF_REGTYPE)
2203 sci_serial_out(port, SCFCR,
2204 sci_serial_in(port, SCFCR) | SCFCR_MCE);
2205 } else {
2206 /* Set RTS */
2207 sci_set_rts(port, 1);
2208 }
2209}
2210
2211static unsigned int sci_get_mctrl(struct uart_port *port)
2212{
2213 struct sci_port *s = to_sci_port(port);
2214 struct mctrl_gpios *gpios = s->gpios;
2215 unsigned int mctrl = 0;
2216
2217 mctrl_gpio_get(gpios, &mctrl);
2218
2219 /*
2220 * CTS/RTS is handled in hardware when supported, while nothing
2221 * else is wired up.
2222 */
2223 if (s->autorts) {
2224 if (sci_get_cts(port))
2225 mctrl |= TIOCM_CTS;
2226 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) {
2227 mctrl |= TIOCM_CTS;
2228 }
2229 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
2230 mctrl |= TIOCM_DSR;
2231 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
2232 mctrl |= TIOCM_CAR;
2233
2234 return mctrl;
2235}
2236
2237static void sci_enable_ms(struct uart_port *port)
2238{
2239 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2240}
2241
2242static void sci_break_ctl(struct uart_port *port, int break_state)
2243{
2244 unsigned short scscr, scsptr;
2245 unsigned long flags;
2246
2247 /* check whether the port has SCSPTR */
2248 if (!sci_getreg(port, SCSPTR)->size) {
2249 /*
2250 * Not supported by hardware. Most parts couple break and rx
2251 * interrupts together, with break detection always enabled.
2252 */
2253 return;
2254 }
2255
2256 uart_port_lock_irqsave(port, &flags);
2257 scsptr = sci_serial_in(port, SCSPTR);
2258 scscr = sci_serial_in(port, SCSCR);
2259
2260 if (break_state == -1) {
2261 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2262 scscr &= ~SCSCR_TE;
2263 } else {
2264 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2265 scscr |= SCSCR_TE;
2266 }
2267
2268 sci_serial_out(port, SCSPTR, scsptr);
2269 sci_serial_out(port, SCSCR, scscr);
2270 uart_port_unlock_irqrestore(port, flags);
2271}
2272
2273static int sci_startup(struct uart_port *port)
2274{
2275 struct sci_port *s = to_sci_port(port);
2276 int ret;
2277
2278 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2279
2280 s->tx_occurred = false;
2281 sci_request_dma(port);
2282
2283 ret = sci_request_irq(s);
2284 if (unlikely(ret < 0)) {
2285 sci_free_dma(port);
2286 return ret;
2287 }
2288
2289 return 0;
2290}
2291
2292static void sci_shutdown(struct uart_port *port)
2293{
2294 struct sci_port *s = to_sci_port(port);
2295 unsigned long flags;
2296 u16 scr;
2297
2298 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2299
2300 s->autorts = false;
2301 mctrl_gpio_disable_ms(to_sci_port(port)->gpios);
2302
2303 uart_port_lock_irqsave(port, &flags);
2304 sci_stop_rx(port);
2305 sci_stop_tx(port);
2306 /*
2307 * Stop RX and TX, disable related interrupts, keep clock source
2308 * and HSCIF TOT bits
2309 */
2310 scr = sci_serial_in(port, SCSCR);
2311 sci_serial_out(port, SCSCR,
2312 scr & (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2313 uart_port_unlock_irqrestore(port, flags);
2314
2315#ifdef CONFIG_SERIAL_SH_SCI_DMA
2316 if (s->chan_rx_saved) {
2317 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2318 port->line);
2319 hrtimer_cancel(&s->rx_timer);
2320 }
2321#endif
2322
2323 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2324 del_timer_sync(&s->rx_fifo_timer);
2325 sci_free_irq(s);
2326 sci_free_dma(port);
2327}
2328
2329static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2330 unsigned int *srr)
2331{
2332 unsigned long freq = s->clk_rates[SCI_SCK];
2333 int err, min_err = INT_MAX;
2334 unsigned int sr;
2335
2336 if (s->port.type != PORT_HSCIF)
2337 freq *= 2;
2338
2339 for_each_sr(sr, s) {
2340 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2341 if (abs(err) >= abs(min_err))
2342 continue;
2343
2344 min_err = err;
2345 *srr = sr - 1;
2346
2347 if (!err)
2348 break;
2349 }
2350
2351 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2352 *srr + 1);
2353 return min_err;
2354}
2355
2356static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2357 unsigned long freq, unsigned int *dlr,
2358 unsigned int *srr)
2359{
2360 int err, min_err = INT_MAX;
2361 unsigned int sr, dl;
2362
2363 if (s->port.type != PORT_HSCIF)
2364 freq *= 2;
2365
2366 for_each_sr(sr, s) {
2367 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2368 dl = clamp(dl, 1U, 65535U);
2369
2370 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2371 if (abs(err) >= abs(min_err))
2372 continue;
2373
2374 min_err = err;
2375 *dlr = dl;
2376 *srr = sr - 1;
2377
2378 if (!err)
2379 break;
2380 }
2381
2382 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2383 min_err, *dlr, *srr + 1);
2384 return min_err;
2385}
2386
2387/* calculate sample rate, BRR, and clock select */
2388static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2389 unsigned int *brr, unsigned int *srr,
2390 unsigned int *cks)
2391{
2392 unsigned long freq = s->clk_rates[SCI_FCK];
2393 unsigned int sr, br, prediv, scrate, c;
2394 int err, min_err = INT_MAX;
2395
2396 if (s->port.type != PORT_HSCIF)
2397 freq *= 2;
2398
2399 /*
2400 * Find the combination of sample rate and clock select with the
2401 * smallest deviation from the desired baud rate.
2402 * Prefer high sample rates to maximise the receive margin.
2403 *
2404 * M: Receive margin (%)
2405 * N: Ratio of bit rate to clock (N = sampling rate)
2406 * D: Clock duty (D = 0 to 1.0)
2407 * L: Frame length (L = 9 to 12)
2408 * F: Absolute value of clock frequency deviation
2409 *
2410 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2411 * (|D - 0.5| / N * (1 + F))|
2412 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2413 */
2414 for_each_sr(sr, s) {
2415 for (c = 0; c <= 3; c++) {
2416 /* integerized formulas from HSCIF documentation */
2417 prediv = sr << (2 * c + 1);
2418
2419 /*
2420 * We need to calculate:
2421 *
2422 * br = freq / (prediv * bps) clamped to [1..256]
2423 * err = freq / (br * prediv) - bps
2424 *
2425 * Watch out for overflow when calculating the desired
2426 * sampling clock rate!
2427 */
2428 if (bps > UINT_MAX / prediv)
2429 break;
2430
2431 scrate = prediv * bps;
2432 br = DIV_ROUND_CLOSEST(freq, scrate);
2433 br = clamp(br, 1U, 256U);
2434
2435 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2436 if (abs(err) >= abs(min_err))
2437 continue;
2438
2439 min_err = err;
2440 *brr = br - 1;
2441 *srr = sr - 1;
2442 *cks = c;
2443
2444 if (!err)
2445 goto found;
2446 }
2447 }
2448
2449found:
2450 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2451 min_err, *brr, *srr + 1, *cks);
2452 return min_err;
2453}
2454
2455static void sci_reset(struct uart_port *port)
2456{
2457 const struct plat_sci_reg *reg;
2458 unsigned int status;
2459 struct sci_port *s = to_sci_port(port);
2460
2461 sci_serial_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2462
2463 reg = sci_getreg(port, SCFCR);
2464 if (reg->size)
2465 sci_serial_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2466
2467 sci_clear_SCxSR(port,
2468 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2469 SCxSR_BREAK_CLEAR(port));
2470 if (sci_getreg(port, SCLSR)->size) {
2471 status = sci_serial_in(port, SCLSR);
2472 status &= ~(SCLSR_TO | SCLSR_ORER);
2473 sci_serial_out(port, SCLSR, status);
2474 }
2475
2476 if (s->rx_trigger > 1) {
2477 if (s->rx_fifo_timeout) {
2478 scif_set_rtrg(port, 1);
2479 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2480 } else {
2481 if (port->type == PORT_SCIFA ||
2482 port->type == PORT_SCIFB)
2483 scif_set_rtrg(port, 1);
2484 else
2485 scif_set_rtrg(port, s->rx_trigger);
2486 }
2487 }
2488}
2489
2490static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2491 const struct ktermios *old)
2492{
2493 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2494 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2495 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2496 struct sci_port *s = to_sci_port(port);
2497 const struct plat_sci_reg *reg;
2498 int min_err = INT_MAX, err;
2499 unsigned long max_freq = 0;
2500 int best_clk = -1;
2501 unsigned long flags;
2502
2503 if ((termios->c_cflag & CSIZE) == CS7) {
2504 smr_val |= SCSMR_CHR;
2505 } else {
2506 termios->c_cflag &= ~CSIZE;
2507 termios->c_cflag |= CS8;
2508 }
2509 if (termios->c_cflag & PARENB)
2510 smr_val |= SCSMR_PE;
2511 if (termios->c_cflag & PARODD)
2512 smr_val |= SCSMR_PE | SCSMR_ODD;
2513 if (termios->c_cflag & CSTOPB)
2514 smr_val |= SCSMR_STOP;
2515
2516 /*
2517 * earlyprintk comes here early on with port->uartclk set to zero.
2518 * the clock framework is not up and running at this point so here
2519 * we assume that 115200 is the maximum baud rate. please note that
2520 * the baud rate is not programmed during earlyprintk - it is assumed
2521 * that the previous boot loader has enabled required clocks and
2522 * setup the baud rate generator hardware for us already.
2523 */
2524 if (!port->uartclk) {
2525 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2526 goto done;
2527 }
2528
2529 for (i = 0; i < SCI_NUM_CLKS; i++)
2530 max_freq = max(max_freq, s->clk_rates[i]);
2531
2532 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2533 if (!baud)
2534 goto done;
2535
2536 /*
2537 * There can be multiple sources for the sampling clock. Find the one
2538 * that gives us the smallest deviation from the desired baud rate.
2539 */
2540
2541 /* Optional Undivided External Clock */
2542 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2543 port->type != PORT_SCIFB) {
2544 err = sci_sck_calc(s, baud, &srr1);
2545 if (abs(err) < abs(min_err)) {
2546 best_clk = SCI_SCK;
2547 scr_val = SCSCR_CKE1;
2548 sccks = SCCKS_CKS;
2549 min_err = err;
2550 srr = srr1;
2551 if (!err)
2552 goto done;
2553 }
2554 }
2555
2556 /* Optional BRG Frequency Divided External Clock */
2557 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2558 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2559 &srr1);
2560 if (abs(err) < abs(min_err)) {
2561 best_clk = SCI_SCIF_CLK;
2562 scr_val = SCSCR_CKE1;
2563 sccks = 0;
2564 min_err = err;
2565 dl = dl1;
2566 srr = srr1;
2567 if (!err)
2568 goto done;
2569 }
2570 }
2571
2572 /* Optional BRG Frequency Divided Internal Clock */
2573 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2574 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2575 &srr1);
2576 if (abs(err) < abs(min_err)) {
2577 best_clk = SCI_BRG_INT;
2578 scr_val = SCSCR_CKE1;
2579 sccks = SCCKS_XIN;
2580 min_err = err;
2581 dl = dl1;
2582 srr = srr1;
2583 if (!min_err)
2584 goto done;
2585 }
2586 }
2587
2588 /* Divided Functional Clock using standard Bit Rate Register */
2589 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2590 if (abs(err) < abs(min_err)) {
2591 best_clk = SCI_FCK;
2592 scr_val = 0;
2593 min_err = err;
2594 brr = brr1;
2595 srr = srr1;
2596 cks = cks1;
2597 }
2598
2599done:
2600 if (best_clk >= 0)
2601 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2602 s->clks[best_clk], baud, min_err);
2603
2604 sci_port_enable(s);
2605
2606 /*
2607 * Program the optional External Baud Rate Generator (BRG) first.
2608 * It controls the mux to select (H)SCK or frequency divided clock.
2609 */
2610 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2611 sci_serial_out(port, SCDL, dl);
2612 sci_serial_out(port, SCCKS, sccks);
2613 }
2614
2615 uart_port_lock_irqsave(port, &flags);
2616
2617 sci_reset(port);
2618
2619 uart_update_timeout(port, termios->c_cflag, baud);
2620
2621 /* byte size and parity */
2622 bits = tty_get_frame_size(termios->c_cflag);
2623
2624 if (sci_getreg(port, SEMR)->size)
2625 sci_serial_out(port, SEMR, 0);
2626
2627 if (best_clk >= 0) {
2628 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2629 switch (srr + 1) {
2630 case 5: smr_val |= SCSMR_SRC_5; break;
2631 case 7: smr_val |= SCSMR_SRC_7; break;
2632 case 11: smr_val |= SCSMR_SRC_11; break;
2633 case 13: smr_val |= SCSMR_SRC_13; break;
2634 case 16: smr_val |= SCSMR_SRC_16; break;
2635 case 17: smr_val |= SCSMR_SRC_17; break;
2636 case 19: smr_val |= SCSMR_SRC_19; break;
2637 case 27: smr_val |= SCSMR_SRC_27; break;
2638 }
2639 smr_val |= cks;
2640 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2641 sci_serial_out(port, SCSMR, smr_val);
2642 sci_serial_out(port, SCBRR, brr);
2643 if (sci_getreg(port, HSSRR)->size) {
2644 unsigned int hssrr = srr | HSCIF_SRE;
2645 /* Calculate deviation from intended rate at the
2646 * center of the last stop bit in sampling clocks.
2647 */
2648 int last_stop = bits * 2 - 1;
2649 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
2650 (int)(srr + 1),
2651 2 * (int)baud);
2652
2653 if (abs(deviation) >= 2) {
2654 /* At least two sampling clocks off at the
2655 * last stop bit; we can increase the error
2656 * margin by shifting the sampling point.
2657 */
2658 int shift = clamp(deviation / 2, -8, 7);
2659
2660 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2661 HSCIF_SRHP_MASK;
2662 hssrr |= HSCIF_SRDE;
2663 }
2664 sci_serial_out(port, HSSRR, hssrr);
2665 }
2666
2667 /* Wait one bit interval */
2668 udelay((1000000 + (baud - 1)) / baud);
2669 } else {
2670 /* Don't touch the bit rate configuration */
2671 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2672 smr_val |= sci_serial_in(port, SCSMR) &
2673 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2674 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2675 sci_serial_out(port, SCSMR, smr_val);
2676 }
2677
2678 sci_init_pins(port, termios->c_cflag);
2679
2680 port->status &= ~UPSTAT_AUTOCTS;
2681 s->autorts = false;
2682 reg = sci_getreg(port, SCFCR);
2683 if (reg->size) {
2684 unsigned short ctrl = sci_serial_in(port, SCFCR);
2685
2686 if ((port->flags & UPF_HARD_FLOW) &&
2687 (termios->c_cflag & CRTSCTS)) {
2688 /* There is no CTS interrupt to restart the hardware */
2689 port->status |= UPSTAT_AUTOCTS;
2690 /* MCE is enabled when RTS is raised */
2691 s->autorts = true;
2692 }
2693
2694 /*
2695 * As we've done a sci_reset() above, ensure we don't
2696 * interfere with the FIFOs while toggling MCE. As the
2697 * reset values could still be set, simply mask them out.
2698 */
2699 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2700
2701 sci_serial_out(port, SCFCR, ctrl);
2702 }
2703 if (port->flags & UPF_HARD_FLOW) {
2704 /* Refresh (Auto) RTS */
2705 sci_set_mctrl(port, port->mctrl);
2706 }
2707
2708 /*
2709 * For SCI, TE (transmit enable) must be set after setting TIE
2710 * (transmit interrupt enable) or in the same instruction to
2711 * start the transmitting process. So skip setting TE here for SCI.
2712 */
2713 if (port->type != PORT_SCI)
2714 scr_val |= SCSCR_TE;
2715 scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2716 sci_serial_out(port, SCSCR, scr_val | s->hscif_tot);
2717 if ((srr + 1 == 5) &&
2718 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2719 /*
2720 * In asynchronous mode, when the sampling rate is 1/5, first
2721 * received data may become invalid on some SCIFA and SCIFB.
2722 * To avoid this problem wait more than 1 serial data time (1
2723 * bit time x serial data number) after setting SCSCR.RE = 1.
2724 */
2725 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2726 }
2727
2728 /* Calculate delay for 2 DMA buffers (4 FIFO). */
2729 s->rx_frame = (10000 * bits) / (baud / 100);
2730#ifdef CONFIG_SERIAL_SH_SCI_DMA
2731 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2732#endif
2733
2734 if ((termios->c_cflag & CREAD) != 0)
2735 sci_start_rx(port);
2736
2737 uart_port_unlock_irqrestore(port, flags);
2738
2739 sci_port_disable(s);
2740
2741 if (UART_ENABLE_MS(port, termios->c_cflag))
2742 sci_enable_ms(port);
2743}
2744
2745static void sci_pm(struct uart_port *port, unsigned int state,
2746 unsigned int oldstate)
2747{
2748 struct sci_port *sci_port = to_sci_port(port);
2749
2750 switch (state) {
2751 case UART_PM_STATE_OFF:
2752 sci_port_disable(sci_port);
2753 break;
2754 default:
2755 sci_port_enable(sci_port);
2756 break;
2757 }
2758}
2759
2760static const char *sci_type(struct uart_port *port)
2761{
2762 switch (port->type) {
2763 case PORT_IRDA:
2764 return "irda";
2765 case PORT_SCI:
2766 return "sci";
2767 case PORT_SCIF:
2768 return "scif";
2769 case PORT_SCIFA:
2770 return "scifa";
2771 case PORT_SCIFB:
2772 return "scifb";
2773 case PORT_HSCIF:
2774 return "hscif";
2775 }
2776
2777 return NULL;
2778}
2779
2780static int sci_remap_port(struct uart_port *port)
2781{
2782 struct sci_port *sport = to_sci_port(port);
2783
2784 /*
2785 * Nothing to do if there's already an established membase.
2786 */
2787 if (port->membase)
2788 return 0;
2789
2790 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2791 port->membase = ioremap(port->mapbase, sport->reg_size);
2792 if (unlikely(!port->membase)) {
2793 dev_err(port->dev, "can't remap port#%d\n", port->line);
2794 return -ENXIO;
2795 }
2796 } else {
2797 /*
2798 * For the simple (and majority of) cases where we don't
2799 * need to do any remapping, just cast the cookie
2800 * directly.
2801 */
2802 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2803 }
2804
2805 return 0;
2806}
2807
2808static void sci_release_port(struct uart_port *port)
2809{
2810 struct sci_port *sport = to_sci_port(port);
2811
2812 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2813 iounmap(port->membase);
2814 port->membase = NULL;
2815 }
2816
2817 release_mem_region(port->mapbase, sport->reg_size);
2818}
2819
2820static int sci_request_port(struct uart_port *port)
2821{
2822 struct resource *res;
2823 struct sci_port *sport = to_sci_port(port);
2824 int ret;
2825
2826 res = request_mem_region(port->mapbase, sport->reg_size,
2827 dev_name(port->dev));
2828 if (unlikely(res == NULL)) {
2829 dev_err(port->dev, "request_mem_region failed.");
2830 return -EBUSY;
2831 }
2832
2833 ret = sci_remap_port(port);
2834 if (unlikely(ret != 0)) {
2835 release_resource(res);
2836 return ret;
2837 }
2838
2839 return 0;
2840}
2841
2842static void sci_config_port(struct uart_port *port, int flags)
2843{
2844 if (flags & UART_CONFIG_TYPE) {
2845 struct sci_port *sport = to_sci_port(port);
2846
2847 port->type = sport->cfg->type;
2848 sci_request_port(port);
2849 }
2850}
2851
2852static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2853{
2854 if (ser->baud_base < 2400)
2855 /* No paper tape reader for Mitch.. */
2856 return -EINVAL;
2857
2858 return 0;
2859}
2860
2861static const struct uart_ops sci_uart_ops = {
2862 .tx_empty = sci_tx_empty,
2863 .set_mctrl = sci_set_mctrl,
2864 .get_mctrl = sci_get_mctrl,
2865 .start_tx = sci_start_tx,
2866 .stop_tx = sci_stop_tx,
2867 .stop_rx = sci_stop_rx,
2868 .enable_ms = sci_enable_ms,
2869 .break_ctl = sci_break_ctl,
2870 .startup = sci_startup,
2871 .shutdown = sci_shutdown,
2872 .flush_buffer = sci_flush_buffer,
2873 .set_termios = sci_set_termios,
2874 .pm = sci_pm,
2875 .type = sci_type,
2876 .release_port = sci_release_port,
2877 .request_port = sci_request_port,
2878 .config_port = sci_config_port,
2879 .verify_port = sci_verify_port,
2880#ifdef CONFIG_CONSOLE_POLL
2881 .poll_get_char = sci_poll_get_char,
2882 .poll_put_char = sci_poll_put_char,
2883#endif
2884};
2885
2886static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2887{
2888 const char *clk_names[] = {
2889 [SCI_FCK] = "fck",
2890 [SCI_SCK] = "sck",
2891 [SCI_BRG_INT] = "brg_int",
2892 [SCI_SCIF_CLK] = "scif_clk",
2893 };
2894 struct clk *clk;
2895 unsigned int i;
2896
2897 if (sci_port->cfg->type == PORT_HSCIF)
2898 clk_names[SCI_SCK] = "hsck";
2899
2900 for (i = 0; i < SCI_NUM_CLKS; i++) {
2901 clk = devm_clk_get_optional(dev, clk_names[i]);
2902 if (IS_ERR(clk))
2903 return PTR_ERR(clk);
2904
2905 if (!clk && i == SCI_FCK) {
2906 /*
2907 * Not all SH platforms declare a clock lookup entry
2908 * for SCI devices, in which case we need to get the
2909 * global "peripheral_clk" clock.
2910 */
2911 clk = devm_clk_get(dev, "peripheral_clk");
2912 if (IS_ERR(clk))
2913 return dev_err_probe(dev, PTR_ERR(clk),
2914 "failed to get %s\n",
2915 clk_names[i]);
2916 }
2917
2918 if (!clk)
2919 dev_dbg(dev, "failed to get %s\n", clk_names[i]);
2920 else
2921 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2922 clk, clk_get_rate(clk));
2923 sci_port->clks[i] = clk;
2924 }
2925 return 0;
2926}
2927
2928static const struct sci_port_params *
2929sci_probe_regmap(const struct plat_sci_port *cfg)
2930{
2931 unsigned int regtype;
2932
2933 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2934 return &sci_port_params[cfg->regtype];
2935
2936 switch (cfg->type) {
2937 case PORT_SCI:
2938 regtype = SCIx_SCI_REGTYPE;
2939 break;
2940 case PORT_IRDA:
2941 regtype = SCIx_IRDA_REGTYPE;
2942 break;
2943 case PORT_SCIFA:
2944 regtype = SCIx_SCIFA_REGTYPE;
2945 break;
2946 case PORT_SCIFB:
2947 regtype = SCIx_SCIFB_REGTYPE;
2948 break;
2949 case PORT_SCIF:
2950 /*
2951 * The SH-4 is a bit of a misnomer here, although that's
2952 * where this particular port layout originated. This
2953 * configuration (or some slight variation thereof)
2954 * remains the dominant model for all SCIFs.
2955 */
2956 regtype = SCIx_SH4_SCIF_REGTYPE;
2957 break;
2958 case PORT_HSCIF:
2959 regtype = SCIx_HSCIF_REGTYPE;
2960 break;
2961 default:
2962 pr_err("Can't probe register map for given port\n");
2963 return NULL;
2964 }
2965
2966 return &sci_port_params[regtype];
2967}
2968
2969static int sci_init_single(struct platform_device *dev,
2970 struct sci_port *sci_port, unsigned int index,
2971 const struct plat_sci_port *p, bool early)
2972{
2973 struct uart_port *port = &sci_port->port;
2974 const struct resource *res;
2975 unsigned int i;
2976 int ret;
2977
2978 sci_port->cfg = p;
2979
2980 port->ops = &sci_uart_ops;
2981 port->iotype = UPIO_MEM;
2982 port->line = index;
2983 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
2984
2985 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2986 if (res == NULL)
2987 return -ENOMEM;
2988
2989 port->mapbase = res->start;
2990 sci_port->reg_size = resource_size(res);
2991
2992 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) {
2993 if (i)
2994 sci_port->irqs[i] = platform_get_irq_optional(dev, i);
2995 else
2996 sci_port->irqs[i] = platform_get_irq(dev, i);
2997 }
2998
2999 /*
3000 * The fourth interrupt on SCI port is transmit end interrupt, so
3001 * shuffle the interrupts.
3002 */
3003 if (p->type == PORT_SCI)
3004 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]);
3005
3006 /* The SCI generates several interrupts. They can be muxed together or
3007 * connected to different interrupt lines. In the muxed case only one
3008 * interrupt resource is specified as there is only one interrupt ID.
3009 * In the non-muxed case, up to 6 interrupt signals might be generated
3010 * from the SCI, however those signals might have their own individual
3011 * interrupt ID numbers, or muxed together with another interrupt.
3012 */
3013 if (sci_port->irqs[0] < 0)
3014 return -ENXIO;
3015
3016 if (sci_port->irqs[1] < 0)
3017 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
3018 sci_port->irqs[i] = sci_port->irqs[0];
3019
3020 sci_port->params = sci_probe_regmap(p);
3021 if (unlikely(sci_port->params == NULL))
3022 return -EINVAL;
3023
3024 switch (p->type) {
3025 case PORT_SCIFB:
3026 sci_port->rx_trigger = 48;
3027 break;
3028 case PORT_HSCIF:
3029 sci_port->rx_trigger = 64;
3030 break;
3031 case PORT_SCIFA:
3032 sci_port->rx_trigger = 32;
3033 break;
3034 case PORT_SCIF:
3035 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
3036 /* RX triggering not implemented for this IP */
3037 sci_port->rx_trigger = 1;
3038 else
3039 sci_port->rx_trigger = 8;
3040 break;
3041 default:
3042 sci_port->rx_trigger = 1;
3043 break;
3044 }
3045
3046 sci_port->rx_fifo_timeout = 0;
3047 sci_port->hscif_tot = 0;
3048
3049 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
3050 * match the SoC datasheet, this should be investigated. Let platform
3051 * data override the sampling rate for now.
3052 */
3053 sci_port->sampling_rate_mask = p->sampling_rate
3054 ? SCI_SR(p->sampling_rate)
3055 : sci_port->params->sampling_rate_mask;
3056
3057 if (!early) {
3058 ret = sci_init_clocks(sci_port, &dev->dev);
3059 if (ret < 0)
3060 return ret;
3061 }
3062
3063 port->type = p->type;
3064 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
3065 port->fifosize = sci_port->params->fifosize;
3066
3067 if (port->type == PORT_SCI && !dev->dev.of_node) {
3068 if (sci_port->reg_size >= 0x20)
3069 port->regshift = 2;
3070 else
3071 port->regshift = 1;
3072 }
3073
3074 /*
3075 * The UART port needs an IRQ value, so we peg this to the RX IRQ
3076 * for the multi-IRQ ports, which is where we are primarily
3077 * concerned with the shutdown path synchronization.
3078 *
3079 * For the muxed case there's nothing more to do.
3080 */
3081 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
3082 port->irqflags = 0;
3083
3084 return 0;
3085}
3086
3087#if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
3088 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
3089static void serial_console_putchar(struct uart_port *port, unsigned char ch)
3090{
3091 sci_poll_put_char(port, ch);
3092}
3093
3094/*
3095 * Print a string to the serial port trying not to disturb
3096 * any possible real use of the port...
3097 */
3098static void serial_console_write(struct console *co, const char *s,
3099 unsigned count)
3100{
3101 struct sci_port *sci_port = &sci_ports[co->index];
3102 struct uart_port *port = &sci_port->port;
3103 unsigned short bits, ctrl, ctrl_temp;
3104 unsigned long flags;
3105 int locked = 1;
3106
3107 if (port->sysrq)
3108 locked = 0;
3109 else if (oops_in_progress)
3110 locked = uart_port_trylock_irqsave(port, &flags);
3111 else
3112 uart_port_lock_irqsave(port, &flags);
3113
3114 /* first save SCSCR then disable interrupts, keep clock source */
3115 ctrl = sci_serial_in(port, SCSCR);
3116 ctrl_temp = SCSCR_RE | SCSCR_TE |
3117 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
3118 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
3119 sci_serial_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
3120
3121 uart_console_write(port, s, count, serial_console_putchar);
3122
3123 /* wait until fifo is empty and last bit has been transmitted */
3124 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
3125 while ((sci_serial_in(port, SCxSR) & bits) != bits)
3126 cpu_relax();
3127
3128 /* restore the SCSCR */
3129 sci_serial_out(port, SCSCR, ctrl);
3130
3131 if (locked)
3132 uart_port_unlock_irqrestore(port, flags);
3133}
3134
3135static int serial_console_setup(struct console *co, char *options)
3136{
3137 struct sci_port *sci_port;
3138 struct uart_port *port;
3139 int baud = 115200;
3140 int bits = 8;
3141 int parity = 'n';
3142 int flow = 'n';
3143 int ret;
3144
3145 /*
3146 * Refuse to handle any bogus ports.
3147 */
3148 if (co->index < 0 || co->index >= SCI_NPORTS)
3149 return -ENODEV;
3150
3151 sci_port = &sci_ports[co->index];
3152 port = &sci_port->port;
3153
3154 /*
3155 * Refuse to handle uninitialized ports.
3156 */
3157 if (!port->ops)
3158 return -ENODEV;
3159
3160 ret = sci_remap_port(port);
3161 if (unlikely(ret != 0))
3162 return ret;
3163
3164 if (options)
3165 uart_parse_options(options, &baud, &parity, &bits, &flow);
3166
3167 return uart_set_options(port, co, baud, parity, bits, flow);
3168}
3169
3170static struct console serial_console = {
3171 .name = "ttySC",
3172 .device = uart_console_device,
3173 .write = serial_console_write,
3174 .setup = serial_console_setup,
3175 .flags = CON_PRINTBUFFER,
3176 .index = -1,
3177 .data = &sci_uart_driver,
3178};
3179
3180#ifdef CONFIG_SUPERH
3181static char early_serial_buf[32];
3182
3183static int early_serial_console_setup(struct console *co, char *options)
3184{
3185 /*
3186 * This early console is always registered using the earlyprintk=
3187 * parameter, which does not call add_preferred_console(). Thus
3188 * @options is always NULL and the options for this early console
3189 * are passed using a custom buffer.
3190 */
3191 WARN_ON(options);
3192
3193 return serial_console_setup(co, early_serial_buf);
3194}
3195
3196static struct console early_serial_console = {
3197 .name = "early_ttySC",
3198 .write = serial_console_write,
3199 .setup = early_serial_console_setup,
3200 .flags = CON_PRINTBUFFER,
3201 .index = -1,
3202};
3203
3204static int sci_probe_earlyprintk(struct platform_device *pdev)
3205{
3206 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3207
3208 if (early_serial_console.data)
3209 return -EEXIST;
3210
3211 early_serial_console.index = pdev->id;
3212
3213 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
3214
3215 if (!strstr(early_serial_buf, "keep"))
3216 early_serial_console.flags |= CON_BOOT;
3217
3218 register_console(&early_serial_console);
3219 return 0;
3220}
3221#endif
3222
3223#define SCI_CONSOLE (&serial_console)
3224
3225#else
3226static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3227{
3228 return -EINVAL;
3229}
3230
3231#define SCI_CONSOLE NULL
3232
3233#endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3234
3235static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3236
3237static DEFINE_MUTEX(sci_uart_registration_lock);
3238static struct uart_driver sci_uart_driver = {
3239 .owner = THIS_MODULE,
3240 .driver_name = "sci",
3241 .dev_name = "ttySC",
3242 .major = SCI_MAJOR,
3243 .minor = SCI_MINOR_START,
3244 .nr = SCI_NPORTS,
3245 .cons = SCI_CONSOLE,
3246};
3247
3248static void sci_remove(struct platform_device *dev)
3249{
3250 struct sci_port *port = platform_get_drvdata(dev);
3251 unsigned int type = port->port.type; /* uart_remove_... clears it */
3252
3253 sci_ports_in_use &= ~BIT(port->port.line);
3254 uart_remove_one_port(&sci_uart_driver, &port->port);
3255
3256 if (port->port.fifosize > 1)
3257 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3258 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF)
3259 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3260}
3261
3262
3263#define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3264#define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3265#define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
3266
3267static const struct of_device_id of_sci_match[] __maybe_unused = {
3268 /* SoC-specific types */
3269 {
3270 .compatible = "renesas,scif-r7s72100",
3271 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3272 },
3273 {
3274 .compatible = "renesas,scif-r7s9210",
3275 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3276 },
3277 {
3278 .compatible = "renesas,scif-r9a07g044",
3279 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3280 },
3281 {
3282 .compatible = "renesas,scif-r9a09g057",
3283 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZV2H_SCIF_REGTYPE),
3284 },
3285 /* Family-specific types */
3286 {
3287 .compatible = "renesas,rcar-gen1-scif",
3288 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3289 }, {
3290 .compatible = "renesas,rcar-gen2-scif",
3291 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3292 }, {
3293 .compatible = "renesas,rcar-gen3-scif",
3294 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3295 }, {
3296 .compatible = "renesas,rcar-gen4-scif",
3297 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3298 },
3299 /* Generic types */
3300 {
3301 .compatible = "renesas,scif",
3302 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3303 }, {
3304 .compatible = "renesas,scifa",
3305 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3306 }, {
3307 .compatible = "renesas,scifb",
3308 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3309 }, {
3310 .compatible = "renesas,hscif",
3311 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3312 }, {
3313 .compatible = "renesas,sci",
3314 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3315 }, {
3316 /* Terminator */
3317 },
3318};
3319MODULE_DEVICE_TABLE(of, of_sci_match);
3320
3321static void sci_reset_control_assert(void *data)
3322{
3323 reset_control_assert(data);
3324}
3325
3326static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3327 unsigned int *dev_id)
3328{
3329 struct device_node *np = pdev->dev.of_node;
3330 struct reset_control *rstc;
3331 struct plat_sci_port *p;
3332 struct sci_port *sp;
3333 const void *data;
3334 int id, ret;
3335
3336 if (!IS_ENABLED(CONFIG_OF) || !np)
3337 return ERR_PTR(-EINVAL);
3338
3339 data = of_device_get_match_data(&pdev->dev);
3340
3341 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
3342 if (IS_ERR(rstc))
3343 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc),
3344 "failed to get reset ctrl\n"));
3345
3346 ret = reset_control_deassert(rstc);
3347 if (ret) {
3348 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret);
3349 return ERR_PTR(ret);
3350 }
3351
3352 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc);
3353 if (ret) {
3354 dev_err(&pdev->dev, "failed to register assert devm action, %d\n",
3355 ret);
3356 return ERR_PTR(ret);
3357 }
3358
3359 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3360 if (!p)
3361 return ERR_PTR(-ENOMEM);
3362
3363 /* Get the line number from the aliases node. */
3364 id = of_alias_get_id(np, "serial");
3365 if (id < 0 && ~sci_ports_in_use)
3366 id = ffz(sci_ports_in_use);
3367 if (id < 0) {
3368 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3369 return ERR_PTR(-EINVAL);
3370 }
3371 if (id >= ARRAY_SIZE(sci_ports)) {
3372 dev_err(&pdev->dev, "serial%d out of range\n", id);
3373 return ERR_PTR(-EINVAL);
3374 }
3375
3376 sp = &sci_ports[id];
3377 *dev_id = id;
3378
3379 p->type = SCI_OF_TYPE(data);
3380 p->regtype = SCI_OF_REGTYPE(data);
3381
3382 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3383
3384 return p;
3385}
3386
3387static int sci_probe_single(struct platform_device *dev,
3388 unsigned int index,
3389 struct plat_sci_port *p,
3390 struct sci_port *sciport,
3391 struct resource *sci_res)
3392{
3393 int ret;
3394
3395 /* Sanity check */
3396 if (unlikely(index >= SCI_NPORTS)) {
3397 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3398 index+1, SCI_NPORTS);
3399 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3400 return -EINVAL;
3401 }
3402 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3403 if (sci_ports_in_use & BIT(index))
3404 return -EBUSY;
3405
3406 mutex_lock(&sci_uart_registration_lock);
3407 if (!sci_uart_driver.state) {
3408 ret = uart_register_driver(&sci_uart_driver);
3409 if (ret) {
3410 mutex_unlock(&sci_uart_registration_lock);
3411 return ret;
3412 }
3413 }
3414 mutex_unlock(&sci_uart_registration_lock);
3415
3416 ret = sci_init_single(dev, sciport, index, p, false);
3417 if (ret)
3418 return ret;
3419
3420 sciport->port.dev = &dev->dev;
3421 ret = devm_pm_runtime_enable(&dev->dev);
3422 if (ret)
3423 return ret;
3424
3425 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3426 if (IS_ERR(sciport->gpios))
3427 return PTR_ERR(sciport->gpios);
3428
3429 if (sciport->has_rtscts) {
3430 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) ||
3431 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) {
3432 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3433 return -EINVAL;
3434 }
3435 sciport->port.flags |= UPF_HARD_FLOW;
3436 }
3437
3438 if (sci_uart_earlycon && sci_ports[0].port.mapbase == sci_res->start) {
3439 /*
3440 * In case:
3441 * - this is the earlycon port (mapped on index 0 in sci_ports[]) and
3442 * - it now maps to an alias other than zero and
3443 * - the earlycon is still alive (e.g., "earlycon keep_bootcon" is
3444 * available in bootargs)
3445 *
3446 * we need to avoid disabling clocks and PM domains through the runtime
3447 * PM APIs called in __device_attach(). For this, increment the runtime
3448 * PM reference counter (the clocks and PM domains were already enabled
3449 * by the bootloader). Otherwise the earlycon may access the HW when it
3450 * has no clocks enabled leading to failures (infinite loop in
3451 * sci_poll_put_char()).
3452 */
3453 pm_runtime_get_noresume(&dev->dev);
3454
3455 /*
3456 * Skip cleanup the sci_port[0] in early_console_exit(), this
3457 * port is the same as the earlycon one.
3458 */
3459 sci_uart_earlycon_dev_probing = true;
3460 }
3461
3462 return uart_add_one_port(&sci_uart_driver, &sciport->port);
3463}
3464
3465static int sci_probe(struct platform_device *dev)
3466{
3467 struct plat_sci_port *p;
3468 struct resource *res;
3469 struct sci_port *sp;
3470 unsigned int dev_id;
3471 int ret;
3472
3473 /*
3474 * If we've come here via earlyprintk initialization, head off to
3475 * the special early probe. We don't have sufficient device state
3476 * to make it beyond this yet.
3477 */
3478#ifdef CONFIG_SUPERH
3479 if (is_sh_early_platform_device(dev))
3480 return sci_probe_earlyprintk(dev);
3481#endif
3482
3483 if (dev->dev.of_node) {
3484 p = sci_parse_dt(dev, &dev_id);
3485 if (IS_ERR(p))
3486 return PTR_ERR(p);
3487 } else {
3488 p = dev->dev.platform_data;
3489 if (p == NULL) {
3490 dev_err(&dev->dev, "no platform data supplied\n");
3491 return -EINVAL;
3492 }
3493
3494 dev_id = dev->id;
3495 }
3496
3497 sp = &sci_ports[dev_id];
3498
3499 /*
3500 * In case:
3501 * - the probed port alias is zero (as the one used by earlycon), and
3502 * - the earlycon is still active (e.g., "earlycon keep_bootcon" in
3503 * bootargs)
3504 *
3505 * defer the probe of this serial. This is a debug scenario and the user
3506 * must be aware of it.
3507 *
3508 * Except when the probed port is the same as the earlycon port.
3509 */
3510
3511 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
3512 if (!res)
3513 return -ENODEV;
3514
3515 if (sci_uart_earlycon && sp == &sci_ports[0] && sp->port.mapbase != res->start)
3516 return dev_err_probe(&dev->dev, -EBUSY, "sci_port[0] is used by earlycon!\n");
3517
3518 platform_set_drvdata(dev, sp);
3519
3520 ret = sci_probe_single(dev, dev_id, p, sp, res);
3521 if (ret)
3522 return ret;
3523
3524 if (sp->port.fifosize > 1) {
3525 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3526 if (ret)
3527 return ret;
3528 }
3529 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3530 sp->port.type == PORT_HSCIF) {
3531 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3532 if (ret) {
3533 if (sp->port.fifosize > 1) {
3534 device_remove_file(&dev->dev,
3535 &dev_attr_rx_fifo_trigger);
3536 }
3537 return ret;
3538 }
3539 }
3540
3541#ifdef CONFIG_SH_STANDARD_BIOS
3542 sh_bios_gdb_detach();
3543#endif
3544
3545 sci_ports_in_use |= BIT(dev_id);
3546 return 0;
3547}
3548
3549static __maybe_unused int sci_suspend(struct device *dev)
3550{
3551 struct sci_port *sport = dev_get_drvdata(dev);
3552
3553 if (sport)
3554 uart_suspend_port(&sci_uart_driver, &sport->port);
3555
3556 return 0;
3557}
3558
3559static __maybe_unused int sci_resume(struct device *dev)
3560{
3561 struct sci_port *sport = dev_get_drvdata(dev);
3562
3563 if (sport)
3564 uart_resume_port(&sci_uart_driver, &sport->port);
3565
3566 return 0;
3567}
3568
3569static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3570
3571static struct platform_driver sci_driver = {
3572 .probe = sci_probe,
3573 .remove = sci_remove,
3574 .driver = {
3575 .name = "sh-sci",
3576 .pm = &sci_dev_pm_ops,
3577 .of_match_table = of_match_ptr(of_sci_match),
3578 },
3579};
3580
3581static int __init sci_init(void)
3582{
3583 pr_info("%s\n", banner);
3584
3585 return platform_driver_register(&sci_driver);
3586}
3587
3588static void __exit sci_exit(void)
3589{
3590 platform_driver_unregister(&sci_driver);
3591
3592 if (sci_uart_driver.state)
3593 uart_unregister_driver(&sci_uart_driver);
3594}
3595
3596#if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
3597sh_early_platform_init_buffer("earlyprintk", &sci_driver,
3598 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3599#endif
3600#ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3601static struct plat_sci_port port_cfg;
3602
3603static int early_console_exit(struct console *co)
3604{
3605 struct sci_port *sci_port = &sci_ports[0];
3606
3607 /*
3608 * Clean the slot used by earlycon. A new SCI device might
3609 * map to this slot.
3610 */
3611 if (!sci_uart_earlycon_dev_probing) {
3612 memset(sci_port, 0, sizeof(*sci_port));
3613 sci_uart_earlycon = false;
3614 }
3615
3616 return 0;
3617}
3618
3619static int __init early_console_setup(struct earlycon_device *device,
3620 int type)
3621{
3622 if (!device->port.membase)
3623 return -ENODEV;
3624
3625 device->port.type = type;
3626 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3627 port_cfg.type = type;
3628 sci_ports[0].cfg = &port_cfg;
3629 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3630 sci_uart_earlycon = true;
3631 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3632 sci_serial_out(&sci_ports[0].port, SCSCR,
3633 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3634
3635 device->con->write = serial_console_write;
3636 device->con->exit = early_console_exit;
3637
3638 return 0;
3639}
3640static int __init sci_early_console_setup(struct earlycon_device *device,
3641 const char *opt)
3642{
3643 return early_console_setup(device, PORT_SCI);
3644}
3645static int __init scif_early_console_setup(struct earlycon_device *device,
3646 const char *opt)
3647{
3648 return early_console_setup(device, PORT_SCIF);
3649}
3650static int __init rzscifa_early_console_setup(struct earlycon_device *device,
3651 const char *opt)
3652{
3653 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
3654 return early_console_setup(device, PORT_SCIF);
3655}
3656
3657static int __init rzv2hscif_early_console_setup(struct earlycon_device *device,
3658 const char *opt)
3659{
3660 port_cfg.regtype = SCIx_RZV2H_SCIF_REGTYPE;
3661 return early_console_setup(device, PORT_SCIF);
3662}
3663
3664static int __init scifa_early_console_setup(struct earlycon_device *device,
3665 const char *opt)
3666{
3667 return early_console_setup(device, PORT_SCIFA);
3668}
3669static int __init scifb_early_console_setup(struct earlycon_device *device,
3670 const char *opt)
3671{
3672 return early_console_setup(device, PORT_SCIFB);
3673}
3674static int __init hscif_early_console_setup(struct earlycon_device *device,
3675 const char *opt)
3676{
3677 return early_console_setup(device, PORT_HSCIF);
3678}
3679
3680OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3681OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3682OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3683OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
3684OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a09g057", rzv2hscif_early_console_setup);
3685OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3686OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3687OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3688#endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3689
3690module_init(sci_init);
3691module_exit(sci_exit);
3692
3693MODULE_LICENSE("GPL");
3694MODULE_ALIAS("platform:sh-sci");
3695MODULE_AUTHOR("Paul Mundt");
3696MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");