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1/* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
2/*
3 Copyright (c) 2001, 2002 by D-Link Corporation
4 Written by Edward Peng.<edward_peng@dlink.com.tw>
5 Created 03-May-2001, base on Linux' sundance.c.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
11*/
12
13#define DRV_NAME "DL2000/TC902x-based linux driver"
14#define DRV_VERSION "v1.19"
15#define DRV_RELDATE "2007/08/12"
16#include "dl2k.h"
17#include <linux/dma-mapping.h>
18
19#define dw32(reg, val) iowrite32(val, ioaddr + (reg))
20#define dw16(reg, val) iowrite16(val, ioaddr + (reg))
21#define dw8(reg, val) iowrite8(val, ioaddr + (reg))
22#define dr32(reg) ioread32(ioaddr + (reg))
23#define dr16(reg) ioread16(ioaddr + (reg))
24#define dr8(reg) ioread8(ioaddr + (reg))
25
26static char version[] =
27 KERN_INFO DRV_NAME " " DRV_VERSION " " DRV_RELDATE "\n";
28#define MAX_UNITS 8
29static int mtu[MAX_UNITS];
30static int vlan[MAX_UNITS];
31static int jumbo[MAX_UNITS];
32static char *media[MAX_UNITS];
33static int tx_flow=-1;
34static int rx_flow=-1;
35static int copy_thresh;
36static int rx_coalesce=10; /* Rx frame count each interrupt */
37static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
38static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
39
40
41MODULE_AUTHOR ("Edward Peng");
42MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
43MODULE_LICENSE("GPL");
44module_param_array(mtu, int, NULL, 0);
45module_param_array(media, charp, NULL, 0);
46module_param_array(vlan, int, NULL, 0);
47module_param_array(jumbo, int, NULL, 0);
48module_param(tx_flow, int, 0);
49module_param(rx_flow, int, 0);
50module_param(copy_thresh, int, 0);
51module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
52module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */
53module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
54
55
56/* Enable the default interrupts */
57#define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
58 UpdateStats | LinkEvent)
59
60static void dl2k_enable_int(struct netdev_private *np)
61{
62 void __iomem *ioaddr = np->ioaddr;
63
64 dw16(IntEnable, DEFAULT_INTR);
65}
66
67static const int max_intrloop = 50;
68static const int multicast_filter_limit = 0x40;
69
70static int rio_open (struct net_device *dev);
71static void rio_timer (struct timer_list *t);
72static void rio_tx_timeout (struct net_device *dev);
73static netdev_tx_t start_xmit (struct sk_buff *skb, struct net_device *dev);
74static irqreturn_t rio_interrupt (int irq, void *dev_instance);
75static void rio_free_tx (struct net_device *dev, int irq);
76static void tx_error (struct net_device *dev, int tx_status);
77static int receive_packet (struct net_device *dev);
78static void rio_error (struct net_device *dev, int int_status);
79static void set_multicast (struct net_device *dev);
80static struct net_device_stats *get_stats (struct net_device *dev);
81static int clear_stats (struct net_device *dev);
82static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
83static int rio_close (struct net_device *dev);
84static int find_miiphy (struct net_device *dev);
85static int parse_eeprom (struct net_device *dev);
86static int read_eeprom (struct netdev_private *, int eep_addr);
87static int mii_wait_link (struct net_device *dev, int wait);
88static int mii_set_media (struct net_device *dev);
89static int mii_get_media (struct net_device *dev);
90static int mii_set_media_pcs (struct net_device *dev);
91static int mii_get_media_pcs (struct net_device *dev);
92static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
93static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
94 u16 data);
95
96static const struct ethtool_ops ethtool_ops;
97
98static const struct net_device_ops netdev_ops = {
99 .ndo_open = rio_open,
100 .ndo_start_xmit = start_xmit,
101 .ndo_stop = rio_close,
102 .ndo_get_stats = get_stats,
103 .ndo_validate_addr = eth_validate_addr,
104 .ndo_set_mac_address = eth_mac_addr,
105 .ndo_set_rx_mode = set_multicast,
106 .ndo_do_ioctl = rio_ioctl,
107 .ndo_tx_timeout = rio_tx_timeout,
108};
109
110static int
111rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
112{
113 struct net_device *dev;
114 struct netdev_private *np;
115 static int card_idx;
116 int chip_idx = ent->driver_data;
117 int err, irq;
118 void __iomem *ioaddr;
119 static int version_printed;
120 void *ring_space;
121 dma_addr_t ring_dma;
122
123 if (!version_printed++)
124 printk ("%s", version);
125
126 err = pci_enable_device (pdev);
127 if (err)
128 return err;
129
130 irq = pdev->irq;
131 err = pci_request_regions (pdev, "dl2k");
132 if (err)
133 goto err_out_disable;
134
135 pci_set_master (pdev);
136
137 err = -ENOMEM;
138
139 dev = alloc_etherdev (sizeof (*np));
140 if (!dev)
141 goto err_out_res;
142 SET_NETDEV_DEV(dev, &pdev->dev);
143
144 np = netdev_priv(dev);
145
146 /* IO registers range. */
147 ioaddr = pci_iomap(pdev, 0, 0);
148 if (!ioaddr)
149 goto err_out_dev;
150 np->eeprom_addr = ioaddr;
151
152#ifdef MEM_MAPPING
153 /* MM registers range. */
154 ioaddr = pci_iomap(pdev, 1, 0);
155 if (!ioaddr)
156 goto err_out_iounmap;
157#endif
158 np->ioaddr = ioaddr;
159 np->chip_id = chip_idx;
160 np->pdev = pdev;
161 spin_lock_init (&np->tx_lock);
162 spin_lock_init (&np->rx_lock);
163
164 /* Parse manual configuration */
165 np->an_enable = 1;
166 np->tx_coalesce = 1;
167 if (card_idx < MAX_UNITS) {
168 if (media[card_idx] != NULL) {
169 np->an_enable = 0;
170 if (strcmp (media[card_idx], "auto") == 0 ||
171 strcmp (media[card_idx], "autosense") == 0 ||
172 strcmp (media[card_idx], "0") == 0 ) {
173 np->an_enable = 2;
174 } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
175 strcmp (media[card_idx], "4") == 0) {
176 np->speed = 100;
177 np->full_duplex = 1;
178 } else if (strcmp (media[card_idx], "100mbps_hd") == 0 ||
179 strcmp (media[card_idx], "3") == 0) {
180 np->speed = 100;
181 np->full_duplex = 0;
182 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
183 strcmp (media[card_idx], "2") == 0) {
184 np->speed = 10;
185 np->full_duplex = 1;
186 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
187 strcmp (media[card_idx], "1") == 0) {
188 np->speed = 10;
189 np->full_duplex = 0;
190 } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
191 strcmp (media[card_idx], "6") == 0) {
192 np->speed=1000;
193 np->full_duplex=1;
194 } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
195 strcmp (media[card_idx], "5") == 0) {
196 np->speed = 1000;
197 np->full_duplex = 0;
198 } else {
199 np->an_enable = 1;
200 }
201 }
202 if (jumbo[card_idx] != 0) {
203 np->jumbo = 1;
204 dev->mtu = MAX_JUMBO;
205 } else {
206 np->jumbo = 0;
207 if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
208 dev->mtu = mtu[card_idx];
209 }
210 np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
211 vlan[card_idx] : 0;
212 if (rx_coalesce > 0 && rx_timeout > 0) {
213 np->rx_coalesce = rx_coalesce;
214 np->rx_timeout = rx_timeout;
215 np->coalesce = 1;
216 }
217 np->tx_flow = (tx_flow == 0) ? 0 : 1;
218 np->rx_flow = (rx_flow == 0) ? 0 : 1;
219
220 if (tx_coalesce < 1)
221 tx_coalesce = 1;
222 else if (tx_coalesce > TX_RING_SIZE-1)
223 tx_coalesce = TX_RING_SIZE - 1;
224 }
225 dev->netdev_ops = &netdev_ops;
226 dev->watchdog_timeo = TX_TIMEOUT;
227 dev->ethtool_ops = ðtool_ops;
228#if 0
229 dev->features = NETIF_F_IP_CSUM;
230#endif
231 /* MTU range: 68 - 1536 or 8000 */
232 dev->min_mtu = ETH_MIN_MTU;
233 dev->max_mtu = np->jumbo ? MAX_JUMBO : PACKET_SIZE;
234
235 pci_set_drvdata (pdev, dev);
236
237 ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma);
238 if (!ring_space)
239 goto err_out_iounmap;
240 np->tx_ring = ring_space;
241 np->tx_ring_dma = ring_dma;
242
243 ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma);
244 if (!ring_space)
245 goto err_out_unmap_tx;
246 np->rx_ring = ring_space;
247 np->rx_ring_dma = ring_dma;
248
249 /* Parse eeprom data */
250 parse_eeprom (dev);
251
252 /* Find PHY address */
253 err = find_miiphy (dev);
254 if (err)
255 goto err_out_unmap_rx;
256
257 /* Fiber device? */
258 np->phy_media = (dr16(ASICCtrl) & PhyMedia) ? 1 : 0;
259 np->link_status = 0;
260 /* Set media and reset PHY */
261 if (np->phy_media) {
262 /* default Auto-Negotiation for fiber deivices */
263 if (np->an_enable == 2) {
264 np->an_enable = 1;
265 }
266 } else {
267 /* Auto-Negotiation is mandatory for 1000BASE-T,
268 IEEE 802.3ab Annex 28D page 14 */
269 if (np->speed == 1000)
270 np->an_enable = 1;
271 }
272
273 err = register_netdev (dev);
274 if (err)
275 goto err_out_unmap_rx;
276
277 card_idx++;
278
279 printk (KERN_INFO "%s: %s, %pM, IRQ %d\n",
280 dev->name, np->name, dev->dev_addr, irq);
281 if (tx_coalesce > 1)
282 printk(KERN_INFO "tx_coalesce:\t%d packets\n",
283 tx_coalesce);
284 if (np->coalesce)
285 printk(KERN_INFO
286 "rx_coalesce:\t%d packets\n"
287 "rx_timeout: \t%d ns\n",
288 np->rx_coalesce, np->rx_timeout*640);
289 if (np->vlan)
290 printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
291 return 0;
292
293err_out_unmap_rx:
294 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
295err_out_unmap_tx:
296 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
297err_out_iounmap:
298#ifdef MEM_MAPPING
299 pci_iounmap(pdev, np->ioaddr);
300#endif
301 pci_iounmap(pdev, np->eeprom_addr);
302err_out_dev:
303 free_netdev (dev);
304err_out_res:
305 pci_release_regions (pdev);
306err_out_disable:
307 pci_disable_device (pdev);
308 return err;
309}
310
311static int
312find_miiphy (struct net_device *dev)
313{
314 struct netdev_private *np = netdev_priv(dev);
315 int i, phy_found = 0;
316
317 np->phy_addr = 1;
318
319 for (i = 31; i >= 0; i--) {
320 int mii_status = mii_read (dev, i, 1);
321 if (mii_status != 0xffff && mii_status != 0x0000) {
322 np->phy_addr = i;
323 phy_found++;
324 }
325 }
326 if (!phy_found) {
327 printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
328 return -ENODEV;
329 }
330 return 0;
331}
332
333static int
334parse_eeprom (struct net_device *dev)
335{
336 struct netdev_private *np = netdev_priv(dev);
337 void __iomem *ioaddr = np->ioaddr;
338 int i, j;
339 u8 sromdata[256];
340 u8 *psib;
341 u32 crc;
342 PSROM_t psrom = (PSROM_t) sromdata;
343
344 int cid, next;
345
346 for (i = 0; i < 128; i++)
347 ((__le16 *) sromdata)[i] = cpu_to_le16(read_eeprom(np, i));
348
349 if (np->pdev->vendor == PCI_VENDOR_ID_DLINK) { /* D-Link Only */
350 /* Check CRC */
351 crc = ~ether_crc_le (256 - 4, sromdata);
352 if (psrom->crc != cpu_to_le32(crc)) {
353 printk (KERN_ERR "%s: EEPROM data CRC error.\n",
354 dev->name);
355 return -1;
356 }
357 }
358
359 /* Set MAC address */
360 for (i = 0; i < 6; i++)
361 dev->dev_addr[i] = psrom->mac_addr[i];
362
363 if (np->chip_id == CHIP_IP1000A) {
364 np->led_mode = psrom->led_mode;
365 return 0;
366 }
367
368 if (np->pdev->vendor != PCI_VENDOR_ID_DLINK) {
369 return 0;
370 }
371
372 /* Parse Software Information Block */
373 i = 0x30;
374 psib = (u8 *) sromdata;
375 do {
376 cid = psib[i++];
377 next = psib[i++];
378 if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
379 printk (KERN_ERR "Cell data error\n");
380 return -1;
381 }
382 switch (cid) {
383 case 0: /* Format version */
384 break;
385 case 1: /* End of cell */
386 return 0;
387 case 2: /* Duplex Polarity */
388 np->duplex_polarity = psib[i];
389 dw8(PhyCtrl, dr8(PhyCtrl) | psib[i]);
390 break;
391 case 3: /* Wake Polarity */
392 np->wake_polarity = psib[i];
393 break;
394 case 9: /* Adapter description */
395 j = (next - i > 255) ? 255 : next - i;
396 memcpy (np->name, &(psib[i]), j);
397 break;
398 case 4:
399 case 5:
400 case 6:
401 case 7:
402 case 8: /* Reversed */
403 break;
404 default: /* Unknown cell */
405 return -1;
406 }
407 i = next;
408 } while (1);
409
410 return 0;
411}
412
413static void rio_set_led_mode(struct net_device *dev)
414{
415 struct netdev_private *np = netdev_priv(dev);
416 void __iomem *ioaddr = np->ioaddr;
417 u32 mode;
418
419 if (np->chip_id != CHIP_IP1000A)
420 return;
421
422 mode = dr32(ASICCtrl);
423 mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED);
424
425 if (np->led_mode & 0x01)
426 mode |= IPG_AC_LED_MODE;
427 if (np->led_mode & 0x02)
428 mode |= IPG_AC_LED_MODE_BIT_1;
429 if (np->led_mode & 0x08)
430 mode |= IPG_AC_LED_SPEED;
431
432 dw32(ASICCtrl, mode);
433}
434
435static inline dma_addr_t desc_to_dma(struct netdev_desc *desc)
436{
437 return le64_to_cpu(desc->fraginfo) & DMA_BIT_MASK(48);
438}
439
440static void free_list(struct net_device *dev)
441{
442 struct netdev_private *np = netdev_priv(dev);
443 struct sk_buff *skb;
444 int i;
445
446 /* Free all the skbuffs in the queue. */
447 for (i = 0; i < RX_RING_SIZE; i++) {
448 skb = np->rx_skbuff[i];
449 if (skb) {
450 pci_unmap_single(np->pdev, desc_to_dma(&np->rx_ring[i]),
451 skb->len, PCI_DMA_FROMDEVICE);
452 dev_kfree_skb(skb);
453 np->rx_skbuff[i] = NULL;
454 }
455 np->rx_ring[i].status = 0;
456 np->rx_ring[i].fraginfo = 0;
457 }
458 for (i = 0; i < TX_RING_SIZE; i++) {
459 skb = np->tx_skbuff[i];
460 if (skb) {
461 pci_unmap_single(np->pdev, desc_to_dma(&np->tx_ring[i]),
462 skb->len, PCI_DMA_TODEVICE);
463 dev_kfree_skb(skb);
464 np->tx_skbuff[i] = NULL;
465 }
466 }
467}
468
469static void rio_reset_ring(struct netdev_private *np)
470{
471 int i;
472
473 np->cur_rx = 0;
474 np->cur_tx = 0;
475 np->old_rx = 0;
476 np->old_tx = 0;
477
478 for (i = 0; i < TX_RING_SIZE; i++)
479 np->tx_ring[i].status = cpu_to_le64(TFDDone);
480
481 for (i = 0; i < RX_RING_SIZE; i++)
482 np->rx_ring[i].status = 0;
483}
484
485 /* allocate and initialize Tx and Rx descriptors */
486static int alloc_list(struct net_device *dev)
487{
488 struct netdev_private *np = netdev_priv(dev);
489 int i;
490
491 rio_reset_ring(np);
492 np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
493
494 /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
495 for (i = 0; i < TX_RING_SIZE; i++) {
496 np->tx_skbuff[i] = NULL;
497 np->tx_ring[i].next_desc = cpu_to_le64(np->tx_ring_dma +
498 ((i + 1) % TX_RING_SIZE) *
499 sizeof(struct netdev_desc));
500 }
501
502 /* Initialize Rx descriptors & allocate buffers */
503 for (i = 0; i < RX_RING_SIZE; i++) {
504 /* Allocated fixed size of skbuff */
505 struct sk_buff *skb;
506
507 skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
508 np->rx_skbuff[i] = skb;
509 if (!skb) {
510 free_list(dev);
511 return -ENOMEM;
512 }
513
514 np->rx_ring[i].next_desc = cpu_to_le64(np->rx_ring_dma +
515 ((i + 1) % RX_RING_SIZE) *
516 sizeof(struct netdev_desc));
517 /* Rubicon now supports 40 bits of addressing space. */
518 np->rx_ring[i].fraginfo =
519 cpu_to_le64(pci_map_single(
520 np->pdev, skb->data, np->rx_buf_sz,
521 PCI_DMA_FROMDEVICE));
522 np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48);
523 }
524
525 return 0;
526}
527
528static void rio_hw_init(struct net_device *dev)
529{
530 struct netdev_private *np = netdev_priv(dev);
531 void __iomem *ioaddr = np->ioaddr;
532 int i;
533 u16 macctrl;
534
535 /* Reset all logic functions */
536 dw16(ASICCtrl + 2,
537 GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset);
538 mdelay(10);
539
540 rio_set_led_mode(dev);
541
542 /* DebugCtrl bit 4, 5, 9 must set */
543 dw32(DebugCtrl, dr32(DebugCtrl) | 0x0230);
544
545 if (np->chip_id == CHIP_IP1000A &&
546 (np->pdev->revision == 0x40 || np->pdev->revision == 0x41)) {
547 /* PHY magic taken from ipg driver, undocumented registers */
548 mii_write(dev, np->phy_addr, 31, 0x0001);
549 mii_write(dev, np->phy_addr, 27, 0x01e0);
550 mii_write(dev, np->phy_addr, 31, 0x0002);
551 mii_write(dev, np->phy_addr, 27, 0xeb8e);
552 mii_write(dev, np->phy_addr, 31, 0x0000);
553 mii_write(dev, np->phy_addr, 30, 0x005e);
554 /* advertise 1000BASE-T half & full duplex, prefer MASTER */
555 mii_write(dev, np->phy_addr, MII_CTRL1000, 0x0700);
556 }
557
558 if (np->phy_media)
559 mii_set_media_pcs(dev);
560 else
561 mii_set_media(dev);
562
563 /* Jumbo frame */
564 if (np->jumbo != 0)
565 dw16(MaxFrameSize, MAX_JUMBO+14);
566
567 /* Set RFDListPtr */
568 dw32(RFDListPtr0, np->rx_ring_dma);
569 dw32(RFDListPtr1, 0);
570
571 /* Set station address */
572 /* 16 or 32-bit access is required by TC9020 datasheet but 8-bit works
573 * too. However, it doesn't work on IP1000A so we use 16-bit access.
574 */
575 for (i = 0; i < 3; i++)
576 dw16(StationAddr0 + 2 * i,
577 cpu_to_le16(((u16 *)dev->dev_addr)[i]));
578
579 set_multicast (dev);
580 if (np->coalesce) {
581 dw32(RxDMAIntCtrl, np->rx_coalesce | np->rx_timeout << 16);
582 }
583 /* Set RIO to poll every N*320nsec. */
584 dw8(RxDMAPollPeriod, 0x20);
585 dw8(TxDMAPollPeriod, 0xff);
586 dw8(RxDMABurstThresh, 0x30);
587 dw8(RxDMAUrgentThresh, 0x30);
588 dw32(RmonStatMask, 0x0007ffff);
589 /* clear statistics */
590 clear_stats (dev);
591
592 /* VLAN supported */
593 if (np->vlan) {
594 /* priority field in RxDMAIntCtrl */
595 dw32(RxDMAIntCtrl, dr32(RxDMAIntCtrl) | 0x7 << 10);
596 /* VLANId */
597 dw16(VLANId, np->vlan);
598 /* Length/Type should be 0x8100 */
599 dw32(VLANTag, 0x8100 << 16 | np->vlan);
600 /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
601 VLAN information tagged by TFC' VID, CFI fields. */
602 dw32(MACCtrl, dr32(MACCtrl) | AutoVLANuntagging);
603 }
604
605 /* Start Tx/Rx */
606 dw32(MACCtrl, dr32(MACCtrl) | StatsEnable | RxEnable | TxEnable);
607
608 macctrl = 0;
609 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
610 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
611 macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
612 macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
613 dw16(MACCtrl, macctrl);
614}
615
616static void rio_hw_stop(struct net_device *dev)
617{
618 struct netdev_private *np = netdev_priv(dev);
619 void __iomem *ioaddr = np->ioaddr;
620
621 /* Disable interrupts */
622 dw16(IntEnable, 0);
623
624 /* Stop Tx and Rx logics */
625 dw32(MACCtrl, TxDisable | RxDisable | StatsDisable);
626}
627
628static int rio_open(struct net_device *dev)
629{
630 struct netdev_private *np = netdev_priv(dev);
631 const int irq = np->pdev->irq;
632 int i;
633
634 i = alloc_list(dev);
635 if (i)
636 return i;
637
638 rio_hw_init(dev);
639
640 i = request_irq(irq, rio_interrupt, IRQF_SHARED, dev->name, dev);
641 if (i) {
642 rio_hw_stop(dev);
643 free_list(dev);
644 return i;
645 }
646
647 timer_setup(&np->timer, rio_timer, 0);
648 np->timer.expires = jiffies + 1 * HZ;
649 add_timer(&np->timer);
650
651 netif_start_queue (dev);
652
653 dl2k_enable_int(np);
654 return 0;
655}
656
657static void
658rio_timer (struct timer_list *t)
659{
660 struct netdev_private *np = from_timer(np, t, timer);
661 struct net_device *dev = pci_get_drvdata(np->pdev);
662 unsigned int entry;
663 int next_tick = 1*HZ;
664 unsigned long flags;
665
666 spin_lock_irqsave(&np->rx_lock, flags);
667 /* Recover rx ring exhausted error */
668 if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
669 printk(KERN_INFO "Try to recover rx ring exhausted...\n");
670 /* Re-allocate skbuffs to fill the descriptor ring */
671 for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
672 struct sk_buff *skb;
673 entry = np->old_rx % RX_RING_SIZE;
674 /* Dropped packets don't need to re-allocate */
675 if (np->rx_skbuff[entry] == NULL) {
676 skb = netdev_alloc_skb_ip_align(dev,
677 np->rx_buf_sz);
678 if (skb == NULL) {
679 np->rx_ring[entry].fraginfo = 0;
680 printk (KERN_INFO
681 "%s: Still unable to re-allocate Rx skbuff.#%d\n",
682 dev->name, entry);
683 break;
684 }
685 np->rx_skbuff[entry] = skb;
686 np->rx_ring[entry].fraginfo =
687 cpu_to_le64 (pci_map_single
688 (np->pdev, skb->data, np->rx_buf_sz,
689 PCI_DMA_FROMDEVICE));
690 }
691 np->rx_ring[entry].fraginfo |=
692 cpu_to_le64((u64)np->rx_buf_sz << 48);
693 np->rx_ring[entry].status = 0;
694 } /* end for */
695 } /* end if */
696 spin_unlock_irqrestore (&np->rx_lock, flags);
697 np->timer.expires = jiffies + next_tick;
698 add_timer(&np->timer);
699}
700
701static void
702rio_tx_timeout (struct net_device *dev)
703{
704 struct netdev_private *np = netdev_priv(dev);
705 void __iomem *ioaddr = np->ioaddr;
706
707 printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
708 dev->name, dr32(TxStatus));
709 rio_free_tx(dev, 0);
710 dev->if_port = 0;
711 netif_trans_update(dev); /* prevent tx timeout */
712}
713
714static netdev_tx_t
715start_xmit (struct sk_buff *skb, struct net_device *dev)
716{
717 struct netdev_private *np = netdev_priv(dev);
718 void __iomem *ioaddr = np->ioaddr;
719 struct netdev_desc *txdesc;
720 unsigned entry;
721 u64 tfc_vlan_tag = 0;
722
723 if (np->link_status == 0) { /* Link Down */
724 dev_kfree_skb(skb);
725 return NETDEV_TX_OK;
726 }
727 entry = np->cur_tx % TX_RING_SIZE;
728 np->tx_skbuff[entry] = skb;
729 txdesc = &np->tx_ring[entry];
730
731#if 0
732 if (skb->ip_summed == CHECKSUM_PARTIAL) {
733 txdesc->status |=
734 cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
735 IPChecksumEnable);
736 }
737#endif
738 if (np->vlan) {
739 tfc_vlan_tag = VLANTagInsert |
740 ((u64)np->vlan << 32) |
741 ((u64)skb->priority << 45);
742 }
743 txdesc->fraginfo = cpu_to_le64 (pci_map_single (np->pdev, skb->data,
744 skb->len,
745 PCI_DMA_TODEVICE));
746 txdesc->fraginfo |= cpu_to_le64((u64)skb->len << 48);
747
748 /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
749 * Work around: Always use 1 descriptor in 10Mbps mode */
750 if (entry % np->tx_coalesce == 0 || np->speed == 10)
751 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
752 WordAlignDisable |
753 TxDMAIndicate |
754 (1 << FragCountShift));
755 else
756 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
757 WordAlignDisable |
758 (1 << FragCountShift));
759
760 /* TxDMAPollNow */
761 dw32(DMACtrl, dr32(DMACtrl) | 0x00001000);
762 /* Schedule ISR */
763 dw32(CountDown, 10000);
764 np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
765 if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
766 < TX_QUEUE_LEN - 1 && np->speed != 10) {
767 /* do nothing */
768 } else if (!netif_queue_stopped(dev)) {
769 netif_stop_queue (dev);
770 }
771
772 /* The first TFDListPtr */
773 if (!dr32(TFDListPtr0)) {
774 dw32(TFDListPtr0, np->tx_ring_dma +
775 entry * sizeof (struct netdev_desc));
776 dw32(TFDListPtr1, 0);
777 }
778
779 return NETDEV_TX_OK;
780}
781
782static irqreturn_t
783rio_interrupt (int irq, void *dev_instance)
784{
785 struct net_device *dev = dev_instance;
786 struct netdev_private *np = netdev_priv(dev);
787 void __iomem *ioaddr = np->ioaddr;
788 unsigned int_status;
789 int cnt = max_intrloop;
790 int handled = 0;
791
792 while (1) {
793 int_status = dr16(IntStatus);
794 dw16(IntStatus, int_status);
795 int_status &= DEFAULT_INTR;
796 if (int_status == 0 || --cnt < 0)
797 break;
798 handled = 1;
799 /* Processing received packets */
800 if (int_status & RxDMAComplete)
801 receive_packet (dev);
802 /* TxDMAComplete interrupt */
803 if ((int_status & (TxDMAComplete|IntRequested))) {
804 int tx_status;
805 tx_status = dr32(TxStatus);
806 if (tx_status & 0x01)
807 tx_error (dev, tx_status);
808 /* Free used tx skbuffs */
809 rio_free_tx (dev, 1);
810 }
811
812 /* Handle uncommon events */
813 if (int_status &
814 (HostError | LinkEvent | UpdateStats))
815 rio_error (dev, int_status);
816 }
817 if (np->cur_tx != np->old_tx)
818 dw32(CountDown, 100);
819 return IRQ_RETVAL(handled);
820}
821
822static void
823rio_free_tx (struct net_device *dev, int irq)
824{
825 struct netdev_private *np = netdev_priv(dev);
826 int entry = np->old_tx % TX_RING_SIZE;
827 int tx_use = 0;
828 unsigned long flag = 0;
829
830 if (irq)
831 spin_lock(&np->tx_lock);
832 else
833 spin_lock_irqsave(&np->tx_lock, flag);
834
835 /* Free used tx skbuffs */
836 while (entry != np->cur_tx) {
837 struct sk_buff *skb;
838
839 if (!(np->tx_ring[entry].status & cpu_to_le64(TFDDone)))
840 break;
841 skb = np->tx_skbuff[entry];
842 pci_unmap_single (np->pdev,
843 desc_to_dma(&np->tx_ring[entry]),
844 skb->len, PCI_DMA_TODEVICE);
845 if (irq)
846 dev_kfree_skb_irq (skb);
847 else
848 dev_kfree_skb (skb);
849
850 np->tx_skbuff[entry] = NULL;
851 entry = (entry + 1) % TX_RING_SIZE;
852 tx_use++;
853 }
854 if (irq)
855 spin_unlock(&np->tx_lock);
856 else
857 spin_unlock_irqrestore(&np->tx_lock, flag);
858 np->old_tx = entry;
859
860 /* If the ring is no longer full, clear tx_full and
861 call netif_wake_queue() */
862
863 if (netif_queue_stopped(dev) &&
864 ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
865 < TX_QUEUE_LEN - 1 || np->speed == 10)) {
866 netif_wake_queue (dev);
867 }
868}
869
870static void
871tx_error (struct net_device *dev, int tx_status)
872{
873 struct netdev_private *np = netdev_priv(dev);
874 void __iomem *ioaddr = np->ioaddr;
875 int frame_id;
876 int i;
877
878 frame_id = (tx_status & 0xffff0000);
879 printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
880 dev->name, tx_status, frame_id);
881 dev->stats.tx_errors++;
882 /* Ttransmit Underrun */
883 if (tx_status & 0x10) {
884 dev->stats.tx_fifo_errors++;
885 dw16(TxStartThresh, dr16(TxStartThresh) + 0x10);
886 /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
887 dw16(ASICCtrl + 2,
888 TxReset | DMAReset | FIFOReset | NetworkReset);
889 /* Wait for ResetBusy bit clear */
890 for (i = 50; i > 0; i--) {
891 if (!(dr16(ASICCtrl + 2) & ResetBusy))
892 break;
893 mdelay (1);
894 }
895 rio_set_led_mode(dev);
896 rio_free_tx (dev, 1);
897 /* Reset TFDListPtr */
898 dw32(TFDListPtr0, np->tx_ring_dma +
899 np->old_tx * sizeof (struct netdev_desc));
900 dw32(TFDListPtr1, 0);
901
902 /* Let TxStartThresh stay default value */
903 }
904 /* Late Collision */
905 if (tx_status & 0x04) {
906 dev->stats.tx_fifo_errors++;
907 /* TxReset and clear FIFO */
908 dw16(ASICCtrl + 2, TxReset | FIFOReset);
909 /* Wait reset done */
910 for (i = 50; i > 0; i--) {
911 if (!(dr16(ASICCtrl + 2) & ResetBusy))
912 break;
913 mdelay (1);
914 }
915 rio_set_led_mode(dev);
916 /* Let TxStartThresh stay default value */
917 }
918 /* Maximum Collisions */
919 if (tx_status & 0x08)
920 dev->stats.collisions++;
921 /* Restart the Tx */
922 dw32(MACCtrl, dr16(MACCtrl) | TxEnable);
923}
924
925static int
926receive_packet (struct net_device *dev)
927{
928 struct netdev_private *np = netdev_priv(dev);
929 int entry = np->cur_rx % RX_RING_SIZE;
930 int cnt = 30;
931
932 /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
933 while (1) {
934 struct netdev_desc *desc = &np->rx_ring[entry];
935 int pkt_len;
936 u64 frame_status;
937
938 if (!(desc->status & cpu_to_le64(RFDDone)) ||
939 !(desc->status & cpu_to_le64(FrameStart)) ||
940 !(desc->status & cpu_to_le64(FrameEnd)))
941 break;
942
943 /* Chip omits the CRC. */
944 frame_status = le64_to_cpu(desc->status);
945 pkt_len = frame_status & 0xffff;
946 if (--cnt < 0)
947 break;
948 /* Update rx error statistics, drop packet. */
949 if (frame_status & RFS_Errors) {
950 dev->stats.rx_errors++;
951 if (frame_status & (RxRuntFrame | RxLengthError))
952 dev->stats.rx_length_errors++;
953 if (frame_status & RxFCSError)
954 dev->stats.rx_crc_errors++;
955 if (frame_status & RxAlignmentError && np->speed != 1000)
956 dev->stats.rx_frame_errors++;
957 if (frame_status & RxFIFOOverrun)
958 dev->stats.rx_fifo_errors++;
959 } else {
960 struct sk_buff *skb;
961
962 /* Small skbuffs for short packets */
963 if (pkt_len > copy_thresh) {
964 pci_unmap_single (np->pdev,
965 desc_to_dma(desc),
966 np->rx_buf_sz,
967 PCI_DMA_FROMDEVICE);
968 skb_put (skb = np->rx_skbuff[entry], pkt_len);
969 np->rx_skbuff[entry] = NULL;
970 } else if ((skb = netdev_alloc_skb_ip_align(dev, pkt_len))) {
971 pci_dma_sync_single_for_cpu(np->pdev,
972 desc_to_dma(desc),
973 np->rx_buf_sz,
974 PCI_DMA_FROMDEVICE);
975 skb_copy_to_linear_data (skb,
976 np->rx_skbuff[entry]->data,
977 pkt_len);
978 skb_put (skb, pkt_len);
979 pci_dma_sync_single_for_device(np->pdev,
980 desc_to_dma(desc),
981 np->rx_buf_sz,
982 PCI_DMA_FROMDEVICE);
983 }
984 skb->protocol = eth_type_trans (skb, dev);
985#if 0
986 /* Checksum done by hw, but csum value unavailable. */
987 if (np->pdev->pci_rev_id >= 0x0c &&
988 !(frame_status & (TCPError | UDPError | IPError))) {
989 skb->ip_summed = CHECKSUM_UNNECESSARY;
990 }
991#endif
992 netif_rx (skb);
993 }
994 entry = (entry + 1) % RX_RING_SIZE;
995 }
996 spin_lock(&np->rx_lock);
997 np->cur_rx = entry;
998 /* Re-allocate skbuffs to fill the descriptor ring */
999 entry = np->old_rx;
1000 while (entry != np->cur_rx) {
1001 struct sk_buff *skb;
1002 /* Dropped packets don't need to re-allocate */
1003 if (np->rx_skbuff[entry] == NULL) {
1004 skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
1005 if (skb == NULL) {
1006 np->rx_ring[entry].fraginfo = 0;
1007 printk (KERN_INFO
1008 "%s: receive_packet: "
1009 "Unable to re-allocate Rx skbuff.#%d\n",
1010 dev->name, entry);
1011 break;
1012 }
1013 np->rx_skbuff[entry] = skb;
1014 np->rx_ring[entry].fraginfo =
1015 cpu_to_le64 (pci_map_single
1016 (np->pdev, skb->data, np->rx_buf_sz,
1017 PCI_DMA_FROMDEVICE));
1018 }
1019 np->rx_ring[entry].fraginfo |=
1020 cpu_to_le64((u64)np->rx_buf_sz << 48);
1021 np->rx_ring[entry].status = 0;
1022 entry = (entry + 1) % RX_RING_SIZE;
1023 }
1024 np->old_rx = entry;
1025 spin_unlock(&np->rx_lock);
1026 return 0;
1027}
1028
1029static void
1030rio_error (struct net_device *dev, int int_status)
1031{
1032 struct netdev_private *np = netdev_priv(dev);
1033 void __iomem *ioaddr = np->ioaddr;
1034 u16 macctrl;
1035
1036 /* Link change event */
1037 if (int_status & LinkEvent) {
1038 if (mii_wait_link (dev, 10) == 0) {
1039 printk (KERN_INFO "%s: Link up\n", dev->name);
1040 if (np->phy_media)
1041 mii_get_media_pcs (dev);
1042 else
1043 mii_get_media (dev);
1044 if (np->speed == 1000)
1045 np->tx_coalesce = tx_coalesce;
1046 else
1047 np->tx_coalesce = 1;
1048 macctrl = 0;
1049 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
1050 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
1051 macctrl |= (np->tx_flow) ?
1052 TxFlowControlEnable : 0;
1053 macctrl |= (np->rx_flow) ?
1054 RxFlowControlEnable : 0;
1055 dw16(MACCtrl, macctrl);
1056 np->link_status = 1;
1057 netif_carrier_on(dev);
1058 } else {
1059 printk (KERN_INFO "%s: Link off\n", dev->name);
1060 np->link_status = 0;
1061 netif_carrier_off(dev);
1062 }
1063 }
1064
1065 /* UpdateStats statistics registers */
1066 if (int_status & UpdateStats) {
1067 get_stats (dev);
1068 }
1069
1070 /* PCI Error, a catastronphic error related to the bus interface
1071 occurs, set GlobalReset and HostReset to reset. */
1072 if (int_status & HostError) {
1073 printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
1074 dev->name, int_status);
1075 dw16(ASICCtrl + 2, GlobalReset | HostReset);
1076 mdelay (500);
1077 rio_set_led_mode(dev);
1078 }
1079}
1080
1081static struct net_device_stats *
1082get_stats (struct net_device *dev)
1083{
1084 struct netdev_private *np = netdev_priv(dev);
1085 void __iomem *ioaddr = np->ioaddr;
1086#ifdef MEM_MAPPING
1087 int i;
1088#endif
1089 unsigned int stat_reg;
1090
1091 /* All statistics registers need to be acknowledged,
1092 else statistic overflow could cause problems */
1093
1094 dev->stats.rx_packets += dr32(FramesRcvOk);
1095 dev->stats.tx_packets += dr32(FramesXmtOk);
1096 dev->stats.rx_bytes += dr32(OctetRcvOk);
1097 dev->stats.tx_bytes += dr32(OctetXmtOk);
1098
1099 dev->stats.multicast = dr32(McstFramesRcvdOk);
1100 dev->stats.collisions += dr32(SingleColFrames)
1101 + dr32(MultiColFrames);
1102
1103 /* detailed tx errors */
1104 stat_reg = dr16(FramesAbortXSColls);
1105 dev->stats.tx_aborted_errors += stat_reg;
1106 dev->stats.tx_errors += stat_reg;
1107
1108 stat_reg = dr16(CarrierSenseErrors);
1109 dev->stats.tx_carrier_errors += stat_reg;
1110 dev->stats.tx_errors += stat_reg;
1111
1112 /* Clear all other statistic register. */
1113 dr32(McstOctetXmtOk);
1114 dr16(BcstFramesXmtdOk);
1115 dr32(McstFramesXmtdOk);
1116 dr16(BcstFramesRcvdOk);
1117 dr16(MacControlFramesRcvd);
1118 dr16(FrameTooLongErrors);
1119 dr16(InRangeLengthErrors);
1120 dr16(FramesCheckSeqErrors);
1121 dr16(FramesLostRxErrors);
1122 dr32(McstOctetXmtOk);
1123 dr32(BcstOctetXmtOk);
1124 dr32(McstFramesXmtdOk);
1125 dr32(FramesWDeferredXmt);
1126 dr32(LateCollisions);
1127 dr16(BcstFramesXmtdOk);
1128 dr16(MacControlFramesXmtd);
1129 dr16(FramesWEXDeferal);
1130
1131#ifdef MEM_MAPPING
1132 for (i = 0x100; i <= 0x150; i += 4)
1133 dr32(i);
1134#endif
1135 dr16(TxJumboFrames);
1136 dr16(RxJumboFrames);
1137 dr16(TCPCheckSumErrors);
1138 dr16(UDPCheckSumErrors);
1139 dr16(IPCheckSumErrors);
1140 return &dev->stats;
1141}
1142
1143static int
1144clear_stats (struct net_device *dev)
1145{
1146 struct netdev_private *np = netdev_priv(dev);
1147 void __iomem *ioaddr = np->ioaddr;
1148#ifdef MEM_MAPPING
1149 int i;
1150#endif
1151
1152 /* All statistics registers need to be acknowledged,
1153 else statistic overflow could cause problems */
1154 dr32(FramesRcvOk);
1155 dr32(FramesXmtOk);
1156 dr32(OctetRcvOk);
1157 dr32(OctetXmtOk);
1158
1159 dr32(McstFramesRcvdOk);
1160 dr32(SingleColFrames);
1161 dr32(MultiColFrames);
1162 dr32(LateCollisions);
1163 /* detailed rx errors */
1164 dr16(FrameTooLongErrors);
1165 dr16(InRangeLengthErrors);
1166 dr16(FramesCheckSeqErrors);
1167 dr16(FramesLostRxErrors);
1168
1169 /* detailed tx errors */
1170 dr16(FramesAbortXSColls);
1171 dr16(CarrierSenseErrors);
1172
1173 /* Clear all other statistic register. */
1174 dr32(McstOctetXmtOk);
1175 dr16(BcstFramesXmtdOk);
1176 dr32(McstFramesXmtdOk);
1177 dr16(BcstFramesRcvdOk);
1178 dr16(MacControlFramesRcvd);
1179 dr32(McstOctetXmtOk);
1180 dr32(BcstOctetXmtOk);
1181 dr32(McstFramesXmtdOk);
1182 dr32(FramesWDeferredXmt);
1183 dr16(BcstFramesXmtdOk);
1184 dr16(MacControlFramesXmtd);
1185 dr16(FramesWEXDeferal);
1186#ifdef MEM_MAPPING
1187 for (i = 0x100; i <= 0x150; i += 4)
1188 dr32(i);
1189#endif
1190 dr16(TxJumboFrames);
1191 dr16(RxJumboFrames);
1192 dr16(TCPCheckSumErrors);
1193 dr16(UDPCheckSumErrors);
1194 dr16(IPCheckSumErrors);
1195 return 0;
1196}
1197
1198static void
1199set_multicast (struct net_device *dev)
1200{
1201 struct netdev_private *np = netdev_priv(dev);
1202 void __iomem *ioaddr = np->ioaddr;
1203 u32 hash_table[2];
1204 u16 rx_mode = 0;
1205
1206 hash_table[0] = hash_table[1] = 0;
1207 /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
1208 hash_table[1] |= 0x02000000;
1209 if (dev->flags & IFF_PROMISC) {
1210 /* Receive all frames promiscuously. */
1211 rx_mode = ReceiveAllFrames;
1212 } else if ((dev->flags & IFF_ALLMULTI) ||
1213 (netdev_mc_count(dev) > multicast_filter_limit)) {
1214 /* Receive broadcast and multicast frames */
1215 rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
1216 } else if (!netdev_mc_empty(dev)) {
1217 struct netdev_hw_addr *ha;
1218 /* Receive broadcast frames and multicast frames filtering
1219 by Hashtable */
1220 rx_mode =
1221 ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
1222 netdev_for_each_mc_addr(ha, dev) {
1223 int bit, index = 0;
1224 int crc = ether_crc_le(ETH_ALEN, ha->addr);
1225 /* The inverted high significant 6 bits of CRC are
1226 used as an index to hashtable */
1227 for (bit = 0; bit < 6; bit++)
1228 if (crc & (1 << (31 - bit)))
1229 index |= (1 << bit);
1230 hash_table[index / 32] |= (1 << (index % 32));
1231 }
1232 } else {
1233 rx_mode = ReceiveBroadcast | ReceiveUnicast;
1234 }
1235 if (np->vlan) {
1236 /* ReceiveVLANMatch field in ReceiveMode */
1237 rx_mode |= ReceiveVLANMatch;
1238 }
1239
1240 dw32(HashTable0, hash_table[0]);
1241 dw32(HashTable1, hash_table[1]);
1242 dw16(ReceiveMode, rx_mode);
1243}
1244
1245static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1246{
1247 struct netdev_private *np = netdev_priv(dev);
1248
1249 strlcpy(info->driver, "dl2k", sizeof(info->driver));
1250 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1251 strlcpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
1252}
1253
1254static int rio_get_link_ksettings(struct net_device *dev,
1255 struct ethtool_link_ksettings *cmd)
1256{
1257 struct netdev_private *np = netdev_priv(dev);
1258 u32 supported, advertising;
1259
1260 if (np->phy_media) {
1261 /* fiber device */
1262 supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1263 advertising = ADVERTISED_Autoneg | ADVERTISED_FIBRE;
1264 cmd->base.port = PORT_FIBRE;
1265 } else {
1266 /* copper device */
1267 supported = SUPPORTED_10baseT_Half |
1268 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
1269 | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
1270 SUPPORTED_Autoneg | SUPPORTED_MII;
1271 advertising = ADVERTISED_10baseT_Half |
1272 ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
1273 ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full |
1274 ADVERTISED_Autoneg | ADVERTISED_MII;
1275 cmd->base.port = PORT_MII;
1276 }
1277 if (np->link_status) {
1278 cmd->base.speed = np->speed;
1279 cmd->base.duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1280 } else {
1281 cmd->base.speed = SPEED_UNKNOWN;
1282 cmd->base.duplex = DUPLEX_UNKNOWN;
1283 }
1284 if (np->an_enable)
1285 cmd->base.autoneg = AUTONEG_ENABLE;
1286 else
1287 cmd->base.autoneg = AUTONEG_DISABLE;
1288
1289 cmd->base.phy_address = np->phy_addr;
1290
1291 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1292 supported);
1293 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1294 advertising);
1295
1296 return 0;
1297}
1298
1299static int rio_set_link_ksettings(struct net_device *dev,
1300 const struct ethtool_link_ksettings *cmd)
1301{
1302 struct netdev_private *np = netdev_priv(dev);
1303 u32 speed = cmd->base.speed;
1304 u8 duplex = cmd->base.duplex;
1305
1306 netif_carrier_off(dev);
1307 if (cmd->base.autoneg == AUTONEG_ENABLE) {
1308 if (np->an_enable) {
1309 return 0;
1310 } else {
1311 np->an_enable = 1;
1312 mii_set_media(dev);
1313 return 0;
1314 }
1315 } else {
1316 np->an_enable = 0;
1317 if (np->speed == 1000) {
1318 speed = SPEED_100;
1319 duplex = DUPLEX_FULL;
1320 printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n");
1321 }
1322 switch (speed) {
1323 case SPEED_10:
1324 np->speed = 10;
1325 np->full_duplex = (duplex == DUPLEX_FULL);
1326 break;
1327 case SPEED_100:
1328 np->speed = 100;
1329 np->full_duplex = (duplex == DUPLEX_FULL);
1330 break;
1331 case SPEED_1000: /* not supported */
1332 default:
1333 return -EINVAL;
1334 }
1335 mii_set_media(dev);
1336 }
1337 return 0;
1338}
1339
1340static u32 rio_get_link(struct net_device *dev)
1341{
1342 struct netdev_private *np = netdev_priv(dev);
1343 return np->link_status;
1344}
1345
1346static const struct ethtool_ops ethtool_ops = {
1347 .get_drvinfo = rio_get_drvinfo,
1348 .get_link = rio_get_link,
1349 .get_link_ksettings = rio_get_link_ksettings,
1350 .set_link_ksettings = rio_set_link_ksettings,
1351};
1352
1353static int
1354rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1355{
1356 int phy_addr;
1357 struct netdev_private *np = netdev_priv(dev);
1358 struct mii_ioctl_data *miidata = if_mii(rq);
1359
1360 phy_addr = np->phy_addr;
1361 switch (cmd) {
1362 case SIOCGMIIPHY:
1363 miidata->phy_id = phy_addr;
1364 break;
1365 case SIOCGMIIREG:
1366 miidata->val_out = mii_read (dev, phy_addr, miidata->reg_num);
1367 break;
1368 case SIOCSMIIREG:
1369 if (!capable(CAP_NET_ADMIN))
1370 return -EPERM;
1371 mii_write (dev, phy_addr, miidata->reg_num, miidata->val_in);
1372 break;
1373 default:
1374 return -EOPNOTSUPP;
1375 }
1376 return 0;
1377}
1378
1379#define EEP_READ 0x0200
1380#define EEP_BUSY 0x8000
1381/* Read the EEPROM word */
1382/* We use I/O instruction to read/write eeprom to avoid fail on some machines */
1383static int read_eeprom(struct netdev_private *np, int eep_addr)
1384{
1385 void __iomem *ioaddr = np->eeprom_addr;
1386 int i = 1000;
1387
1388 dw16(EepromCtrl, EEP_READ | (eep_addr & 0xff));
1389 while (i-- > 0) {
1390 if (!(dr16(EepromCtrl) & EEP_BUSY))
1391 return dr16(EepromData);
1392 }
1393 return 0;
1394}
1395
1396enum phy_ctrl_bits {
1397 MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
1398 MII_DUPLEX = 0x08,
1399};
1400
1401#define mii_delay() dr8(PhyCtrl)
1402static void
1403mii_sendbit (struct net_device *dev, u32 data)
1404{
1405 struct netdev_private *np = netdev_priv(dev);
1406 void __iomem *ioaddr = np->ioaddr;
1407
1408 data = ((data) ? MII_DATA1 : 0) | (dr8(PhyCtrl) & 0xf8) | MII_WRITE;
1409 dw8(PhyCtrl, data);
1410 mii_delay ();
1411 dw8(PhyCtrl, data | MII_CLK);
1412 mii_delay ();
1413}
1414
1415static int
1416mii_getbit (struct net_device *dev)
1417{
1418 struct netdev_private *np = netdev_priv(dev);
1419 void __iomem *ioaddr = np->ioaddr;
1420 u8 data;
1421
1422 data = (dr8(PhyCtrl) & 0xf8) | MII_READ;
1423 dw8(PhyCtrl, data);
1424 mii_delay ();
1425 dw8(PhyCtrl, data | MII_CLK);
1426 mii_delay ();
1427 return (dr8(PhyCtrl) >> 1) & 1;
1428}
1429
1430static void
1431mii_send_bits (struct net_device *dev, u32 data, int len)
1432{
1433 int i;
1434
1435 for (i = len - 1; i >= 0; i--) {
1436 mii_sendbit (dev, data & (1 << i));
1437 }
1438}
1439
1440static int
1441mii_read (struct net_device *dev, int phy_addr, int reg_num)
1442{
1443 u32 cmd;
1444 int i;
1445 u32 retval = 0;
1446
1447 /* Preamble */
1448 mii_send_bits (dev, 0xffffffff, 32);
1449 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1450 /* ST,OP = 0110'b for read operation */
1451 cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
1452 mii_send_bits (dev, cmd, 14);
1453 /* Turnaround */
1454 if (mii_getbit (dev))
1455 goto err_out;
1456 /* Read data */
1457 for (i = 0; i < 16; i++) {
1458 retval |= mii_getbit (dev);
1459 retval <<= 1;
1460 }
1461 /* End cycle */
1462 mii_getbit (dev);
1463 return (retval >> 1) & 0xffff;
1464
1465 err_out:
1466 return 0;
1467}
1468static int
1469mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
1470{
1471 u32 cmd;
1472
1473 /* Preamble */
1474 mii_send_bits (dev, 0xffffffff, 32);
1475 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1476 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1477 cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
1478 mii_send_bits (dev, cmd, 32);
1479 /* End cycle */
1480 mii_getbit (dev);
1481 return 0;
1482}
1483static int
1484mii_wait_link (struct net_device *dev, int wait)
1485{
1486 __u16 bmsr;
1487 int phy_addr;
1488 struct netdev_private *np;
1489
1490 np = netdev_priv(dev);
1491 phy_addr = np->phy_addr;
1492
1493 do {
1494 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1495 if (bmsr & BMSR_LSTATUS)
1496 return 0;
1497 mdelay (1);
1498 } while (--wait > 0);
1499 return -1;
1500}
1501static int
1502mii_get_media (struct net_device *dev)
1503{
1504 __u16 negotiate;
1505 __u16 bmsr;
1506 __u16 mscr;
1507 __u16 mssr;
1508 int phy_addr;
1509 struct netdev_private *np;
1510
1511 np = netdev_priv(dev);
1512 phy_addr = np->phy_addr;
1513
1514 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1515 if (np->an_enable) {
1516 if (!(bmsr & BMSR_ANEGCOMPLETE)) {
1517 /* Auto-Negotiation not completed */
1518 return -1;
1519 }
1520 negotiate = mii_read (dev, phy_addr, MII_ADVERTISE) &
1521 mii_read (dev, phy_addr, MII_LPA);
1522 mscr = mii_read (dev, phy_addr, MII_CTRL1000);
1523 mssr = mii_read (dev, phy_addr, MII_STAT1000);
1524 if (mscr & ADVERTISE_1000FULL && mssr & LPA_1000FULL) {
1525 np->speed = 1000;
1526 np->full_duplex = 1;
1527 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1528 } else if (mscr & ADVERTISE_1000HALF && mssr & LPA_1000HALF) {
1529 np->speed = 1000;
1530 np->full_duplex = 0;
1531 printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
1532 } else if (negotiate & ADVERTISE_100FULL) {
1533 np->speed = 100;
1534 np->full_duplex = 1;
1535 printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
1536 } else if (negotiate & ADVERTISE_100HALF) {
1537 np->speed = 100;
1538 np->full_duplex = 0;
1539 printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
1540 } else if (negotiate & ADVERTISE_10FULL) {
1541 np->speed = 10;
1542 np->full_duplex = 1;
1543 printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
1544 } else if (negotiate & ADVERTISE_10HALF) {
1545 np->speed = 10;
1546 np->full_duplex = 0;
1547 printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
1548 }
1549 if (negotiate & ADVERTISE_PAUSE_CAP) {
1550 np->tx_flow &= 1;
1551 np->rx_flow &= 1;
1552 } else if (negotiate & ADVERTISE_PAUSE_ASYM) {
1553 np->tx_flow = 0;
1554 np->rx_flow &= 1;
1555 }
1556 /* else tx_flow, rx_flow = user select */
1557 } else {
1558 __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR);
1559 switch (bmcr & (BMCR_SPEED100 | BMCR_SPEED1000)) {
1560 case BMCR_SPEED1000:
1561 printk (KERN_INFO "Operating at 1000 Mbps, ");
1562 break;
1563 case BMCR_SPEED100:
1564 printk (KERN_INFO "Operating at 100 Mbps, ");
1565 break;
1566 case 0:
1567 printk (KERN_INFO "Operating at 10 Mbps, ");
1568 }
1569 if (bmcr & BMCR_FULLDPLX) {
1570 printk (KERN_CONT "Full duplex\n");
1571 } else {
1572 printk (KERN_CONT "Half duplex\n");
1573 }
1574 }
1575 if (np->tx_flow)
1576 printk(KERN_INFO "Enable Tx Flow Control\n");
1577 else
1578 printk(KERN_INFO "Disable Tx Flow Control\n");
1579 if (np->rx_flow)
1580 printk(KERN_INFO "Enable Rx Flow Control\n");
1581 else
1582 printk(KERN_INFO "Disable Rx Flow Control\n");
1583
1584 return 0;
1585}
1586
1587static int
1588mii_set_media (struct net_device *dev)
1589{
1590 __u16 pscr;
1591 __u16 bmcr;
1592 __u16 bmsr;
1593 __u16 anar;
1594 int phy_addr;
1595 struct netdev_private *np;
1596 np = netdev_priv(dev);
1597 phy_addr = np->phy_addr;
1598
1599 /* Does user set speed? */
1600 if (np->an_enable) {
1601 /* Advertise capabilities */
1602 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1603 anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
1604 ~(ADVERTISE_100FULL | ADVERTISE_10FULL |
1605 ADVERTISE_100HALF | ADVERTISE_10HALF |
1606 ADVERTISE_100BASE4);
1607 if (bmsr & BMSR_100FULL)
1608 anar |= ADVERTISE_100FULL;
1609 if (bmsr & BMSR_100HALF)
1610 anar |= ADVERTISE_100HALF;
1611 if (bmsr & BMSR_100BASE4)
1612 anar |= ADVERTISE_100BASE4;
1613 if (bmsr & BMSR_10FULL)
1614 anar |= ADVERTISE_10FULL;
1615 if (bmsr & BMSR_10HALF)
1616 anar |= ADVERTISE_10HALF;
1617 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1618 mii_write (dev, phy_addr, MII_ADVERTISE, anar);
1619
1620 /* Enable Auto crossover */
1621 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1622 pscr |= 3 << 5; /* 11'b */
1623 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
1624
1625 /* Soft reset PHY */
1626 mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
1627 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
1628 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1629 mdelay(1);
1630 } else {
1631 /* Force speed setting */
1632 /* 1) Disable Auto crossover */
1633 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1634 pscr &= ~(3 << 5);
1635 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
1636
1637 /* 2) PHY Reset */
1638 bmcr = mii_read (dev, phy_addr, MII_BMCR);
1639 bmcr |= BMCR_RESET;
1640 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1641
1642 /* 3) Power Down */
1643 bmcr = 0x1940; /* must be 0x1940 */
1644 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1645 mdelay (100); /* wait a certain time */
1646
1647 /* 4) Advertise nothing */
1648 mii_write (dev, phy_addr, MII_ADVERTISE, 0);
1649
1650 /* 5) Set media and Power Up */
1651 bmcr = BMCR_PDOWN;
1652 if (np->speed == 100) {
1653 bmcr |= BMCR_SPEED100;
1654 printk (KERN_INFO "Manual 100 Mbps, ");
1655 } else if (np->speed == 10) {
1656 printk (KERN_INFO "Manual 10 Mbps, ");
1657 }
1658 if (np->full_duplex) {
1659 bmcr |= BMCR_FULLDPLX;
1660 printk (KERN_CONT "Full duplex\n");
1661 } else {
1662 printk (KERN_CONT "Half duplex\n");
1663 }
1664#if 0
1665 /* Set 1000BaseT Master/Slave setting */
1666 mscr = mii_read (dev, phy_addr, MII_CTRL1000);
1667 mscr |= MII_MSCR_CFG_ENABLE;
1668 mscr &= ~MII_MSCR_CFG_VALUE = 0;
1669#endif
1670 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1671 mdelay(10);
1672 }
1673 return 0;
1674}
1675
1676static int
1677mii_get_media_pcs (struct net_device *dev)
1678{
1679 __u16 negotiate;
1680 __u16 bmsr;
1681 int phy_addr;
1682 struct netdev_private *np;
1683
1684 np = netdev_priv(dev);
1685 phy_addr = np->phy_addr;
1686
1687 bmsr = mii_read (dev, phy_addr, PCS_BMSR);
1688 if (np->an_enable) {
1689 if (!(bmsr & BMSR_ANEGCOMPLETE)) {
1690 /* Auto-Negotiation not completed */
1691 return -1;
1692 }
1693 negotiate = mii_read (dev, phy_addr, PCS_ANAR) &
1694 mii_read (dev, phy_addr, PCS_ANLPAR);
1695 np->speed = 1000;
1696 if (negotiate & PCS_ANAR_FULL_DUPLEX) {
1697 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1698 np->full_duplex = 1;
1699 } else {
1700 printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
1701 np->full_duplex = 0;
1702 }
1703 if (negotiate & PCS_ANAR_PAUSE) {
1704 np->tx_flow &= 1;
1705 np->rx_flow &= 1;
1706 } else if (negotiate & PCS_ANAR_ASYMMETRIC) {
1707 np->tx_flow = 0;
1708 np->rx_flow &= 1;
1709 }
1710 /* else tx_flow, rx_flow = user select */
1711 } else {
1712 __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR);
1713 printk (KERN_INFO "Operating at 1000 Mbps, ");
1714 if (bmcr & BMCR_FULLDPLX) {
1715 printk (KERN_CONT "Full duplex\n");
1716 } else {
1717 printk (KERN_CONT "Half duplex\n");
1718 }
1719 }
1720 if (np->tx_flow)
1721 printk(KERN_INFO "Enable Tx Flow Control\n");
1722 else
1723 printk(KERN_INFO "Disable Tx Flow Control\n");
1724 if (np->rx_flow)
1725 printk(KERN_INFO "Enable Rx Flow Control\n");
1726 else
1727 printk(KERN_INFO "Disable Rx Flow Control\n");
1728
1729 return 0;
1730}
1731
1732static int
1733mii_set_media_pcs (struct net_device *dev)
1734{
1735 __u16 bmcr;
1736 __u16 esr;
1737 __u16 anar;
1738 int phy_addr;
1739 struct netdev_private *np;
1740 np = netdev_priv(dev);
1741 phy_addr = np->phy_addr;
1742
1743 /* Auto-Negotiation? */
1744 if (np->an_enable) {
1745 /* Advertise capabilities */
1746 esr = mii_read (dev, phy_addr, PCS_ESR);
1747 anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
1748 ~PCS_ANAR_HALF_DUPLEX &
1749 ~PCS_ANAR_FULL_DUPLEX;
1750 if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD))
1751 anar |= PCS_ANAR_HALF_DUPLEX;
1752 if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD))
1753 anar |= PCS_ANAR_FULL_DUPLEX;
1754 anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC;
1755 mii_write (dev, phy_addr, MII_ADVERTISE, anar);
1756
1757 /* Soft reset PHY */
1758 mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
1759 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
1760 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1761 mdelay(1);
1762 } else {
1763 /* Force speed setting */
1764 /* PHY Reset */
1765 bmcr = BMCR_RESET;
1766 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1767 mdelay(10);
1768 if (np->full_duplex) {
1769 bmcr = BMCR_FULLDPLX;
1770 printk (KERN_INFO "Manual full duplex\n");
1771 } else {
1772 bmcr = 0;
1773 printk (KERN_INFO "Manual half duplex\n");
1774 }
1775 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1776 mdelay(10);
1777
1778 /* Advertise nothing */
1779 mii_write (dev, phy_addr, MII_ADVERTISE, 0);
1780 }
1781 return 0;
1782}
1783
1784
1785static int
1786rio_close (struct net_device *dev)
1787{
1788 struct netdev_private *np = netdev_priv(dev);
1789 struct pci_dev *pdev = np->pdev;
1790
1791 netif_stop_queue (dev);
1792
1793 rio_hw_stop(dev);
1794
1795 free_irq(pdev->irq, dev);
1796 del_timer_sync (&np->timer);
1797
1798 free_list(dev);
1799
1800 return 0;
1801}
1802
1803static void
1804rio_remove1 (struct pci_dev *pdev)
1805{
1806 struct net_device *dev = pci_get_drvdata (pdev);
1807
1808 if (dev) {
1809 struct netdev_private *np = netdev_priv(dev);
1810
1811 unregister_netdev (dev);
1812 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring,
1813 np->rx_ring_dma);
1814 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring,
1815 np->tx_ring_dma);
1816#ifdef MEM_MAPPING
1817 pci_iounmap(pdev, np->ioaddr);
1818#endif
1819 pci_iounmap(pdev, np->eeprom_addr);
1820 free_netdev (dev);
1821 pci_release_regions (pdev);
1822 pci_disable_device (pdev);
1823 }
1824}
1825
1826#ifdef CONFIG_PM_SLEEP
1827static int rio_suspend(struct device *device)
1828{
1829 struct net_device *dev = dev_get_drvdata(device);
1830 struct netdev_private *np = netdev_priv(dev);
1831
1832 if (!netif_running(dev))
1833 return 0;
1834
1835 netif_device_detach(dev);
1836 del_timer_sync(&np->timer);
1837 rio_hw_stop(dev);
1838
1839 return 0;
1840}
1841
1842static int rio_resume(struct device *device)
1843{
1844 struct net_device *dev = dev_get_drvdata(device);
1845 struct netdev_private *np = netdev_priv(dev);
1846
1847 if (!netif_running(dev))
1848 return 0;
1849
1850 rio_reset_ring(np);
1851 rio_hw_init(dev);
1852 np->timer.expires = jiffies + 1 * HZ;
1853 add_timer(&np->timer);
1854 netif_device_attach(dev);
1855 dl2k_enable_int(np);
1856
1857 return 0;
1858}
1859
1860static SIMPLE_DEV_PM_OPS(rio_pm_ops, rio_suspend, rio_resume);
1861#define RIO_PM_OPS (&rio_pm_ops)
1862
1863#else
1864
1865#define RIO_PM_OPS NULL
1866
1867#endif /* CONFIG_PM_SLEEP */
1868
1869static struct pci_driver rio_driver = {
1870 .name = "dl2k",
1871 .id_table = rio_pci_tbl,
1872 .probe = rio_probe1,
1873 .remove = rio_remove1,
1874 .driver.pm = RIO_PM_OPS,
1875};
1876
1877module_pci_driver(rio_driver);
1878/*
1879
1880Compile command:
1881
1882gcc -D__KERNEL__ -DMODULE -I/usr/src/linux/include -Wall -Wstrict-prototypes -O2 -c dl2k.c
1883
1884Read Documentation/networking/dl2k.txt for details.
1885
1886*/
1887
1// SPDX-License-Identifier: GPL-2.0-or-later
2/* D-Link DL2000-based Gigabit Ethernet Adapter Linux driver */
3/*
4 Copyright (c) 2001, 2002 by D-Link Corporation
5 Written by Edward Peng.<edward_peng@dlink.com.tw>
6 Created 03-May-2001, base on Linux' sundance.c.
7
8*/
9
10#define DRV_NAME "DL2000/TC902x-based linux driver"
11#include "dl2k.h"
12#include <linux/dma-mapping.h>
13
14#define dw32(reg, val) iowrite32(val, ioaddr + (reg))
15#define dw16(reg, val) iowrite16(val, ioaddr + (reg))
16#define dw8(reg, val) iowrite8(val, ioaddr + (reg))
17#define dr32(reg) ioread32(ioaddr + (reg))
18#define dr16(reg) ioread16(ioaddr + (reg))
19#define dr8(reg) ioread8(ioaddr + (reg))
20
21#define MAX_UNITS 8
22static int mtu[MAX_UNITS];
23static int vlan[MAX_UNITS];
24static int jumbo[MAX_UNITS];
25static char *media[MAX_UNITS];
26static int tx_flow=-1;
27static int rx_flow=-1;
28static int copy_thresh;
29static int rx_coalesce=10; /* Rx frame count each interrupt */
30static int rx_timeout=200; /* Rx DMA wait time in 640ns increments */
31static int tx_coalesce=16; /* HW xmit count each TxDMAComplete */
32
33
34MODULE_AUTHOR ("Edward Peng");
35MODULE_DESCRIPTION ("D-Link DL2000-based Gigabit Ethernet Adapter");
36MODULE_LICENSE("GPL");
37module_param_array(mtu, int, NULL, 0);
38module_param_array(media, charp, NULL, 0);
39module_param_array(vlan, int, NULL, 0);
40module_param_array(jumbo, int, NULL, 0);
41module_param(tx_flow, int, 0);
42module_param(rx_flow, int, 0);
43module_param(copy_thresh, int, 0);
44module_param(rx_coalesce, int, 0); /* Rx frame count each interrupt */
45module_param(rx_timeout, int, 0); /* Rx DMA wait time in 64ns increments */
46module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
47
48
49/* Enable the default interrupts */
50#define DEFAULT_INTR (RxDMAComplete | HostError | IntRequested | TxDMAComplete| \
51 UpdateStats | LinkEvent)
52
53static void dl2k_enable_int(struct netdev_private *np)
54{
55 void __iomem *ioaddr = np->ioaddr;
56
57 dw16(IntEnable, DEFAULT_INTR);
58}
59
60static const int max_intrloop = 50;
61static const int multicast_filter_limit = 0x40;
62
63static int rio_open (struct net_device *dev);
64static void rio_timer (struct timer_list *t);
65static void rio_tx_timeout (struct net_device *dev, unsigned int txqueue);
66static netdev_tx_t start_xmit (struct sk_buff *skb, struct net_device *dev);
67static irqreturn_t rio_interrupt (int irq, void *dev_instance);
68static void rio_free_tx (struct net_device *dev, int irq);
69static void tx_error (struct net_device *dev, int tx_status);
70static int receive_packet (struct net_device *dev);
71static void rio_error (struct net_device *dev, int int_status);
72static void set_multicast (struct net_device *dev);
73static struct net_device_stats *get_stats (struct net_device *dev);
74static int clear_stats (struct net_device *dev);
75static int rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
76static int rio_close (struct net_device *dev);
77static int find_miiphy (struct net_device *dev);
78static int parse_eeprom (struct net_device *dev);
79static int read_eeprom (struct netdev_private *, int eep_addr);
80static int mii_wait_link (struct net_device *dev, int wait);
81static int mii_set_media (struct net_device *dev);
82static int mii_get_media (struct net_device *dev);
83static int mii_set_media_pcs (struct net_device *dev);
84static int mii_get_media_pcs (struct net_device *dev);
85static int mii_read (struct net_device *dev, int phy_addr, int reg_num);
86static int mii_write (struct net_device *dev, int phy_addr, int reg_num,
87 u16 data);
88
89static const struct ethtool_ops ethtool_ops;
90
91static const struct net_device_ops netdev_ops = {
92 .ndo_open = rio_open,
93 .ndo_start_xmit = start_xmit,
94 .ndo_stop = rio_close,
95 .ndo_get_stats = get_stats,
96 .ndo_validate_addr = eth_validate_addr,
97 .ndo_set_mac_address = eth_mac_addr,
98 .ndo_set_rx_mode = set_multicast,
99 .ndo_do_ioctl = rio_ioctl,
100 .ndo_tx_timeout = rio_tx_timeout,
101};
102
103static int
104rio_probe1 (struct pci_dev *pdev, const struct pci_device_id *ent)
105{
106 struct net_device *dev;
107 struct netdev_private *np;
108 static int card_idx;
109 int chip_idx = ent->driver_data;
110 int err, irq;
111 void __iomem *ioaddr;
112 void *ring_space;
113 dma_addr_t ring_dma;
114
115 err = pci_enable_device (pdev);
116 if (err)
117 return err;
118
119 irq = pdev->irq;
120 err = pci_request_regions (pdev, "dl2k");
121 if (err)
122 goto err_out_disable;
123
124 pci_set_master (pdev);
125
126 err = -ENOMEM;
127
128 dev = alloc_etherdev (sizeof (*np));
129 if (!dev)
130 goto err_out_res;
131 SET_NETDEV_DEV(dev, &pdev->dev);
132
133 np = netdev_priv(dev);
134
135 /* IO registers range. */
136 ioaddr = pci_iomap(pdev, 0, 0);
137 if (!ioaddr)
138 goto err_out_dev;
139 np->eeprom_addr = ioaddr;
140
141#ifdef MEM_MAPPING
142 /* MM registers range. */
143 ioaddr = pci_iomap(pdev, 1, 0);
144 if (!ioaddr)
145 goto err_out_iounmap;
146#endif
147 np->ioaddr = ioaddr;
148 np->chip_id = chip_idx;
149 np->pdev = pdev;
150 spin_lock_init (&np->tx_lock);
151 spin_lock_init (&np->rx_lock);
152
153 /* Parse manual configuration */
154 np->an_enable = 1;
155 np->tx_coalesce = 1;
156 if (card_idx < MAX_UNITS) {
157 if (media[card_idx] != NULL) {
158 np->an_enable = 0;
159 if (strcmp (media[card_idx], "auto") == 0 ||
160 strcmp (media[card_idx], "autosense") == 0 ||
161 strcmp (media[card_idx], "0") == 0 ) {
162 np->an_enable = 2;
163 } else if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
164 strcmp (media[card_idx], "4") == 0) {
165 np->speed = 100;
166 np->full_duplex = 1;
167 } else if (strcmp (media[card_idx], "100mbps_hd") == 0 ||
168 strcmp (media[card_idx], "3") == 0) {
169 np->speed = 100;
170 np->full_duplex = 0;
171 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
172 strcmp (media[card_idx], "2") == 0) {
173 np->speed = 10;
174 np->full_duplex = 1;
175 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
176 strcmp (media[card_idx], "1") == 0) {
177 np->speed = 10;
178 np->full_duplex = 0;
179 } else if (strcmp (media[card_idx], "1000mbps_fd") == 0 ||
180 strcmp (media[card_idx], "6") == 0) {
181 np->speed=1000;
182 np->full_duplex=1;
183 } else if (strcmp (media[card_idx], "1000mbps_hd") == 0 ||
184 strcmp (media[card_idx], "5") == 0) {
185 np->speed = 1000;
186 np->full_duplex = 0;
187 } else {
188 np->an_enable = 1;
189 }
190 }
191 if (jumbo[card_idx] != 0) {
192 np->jumbo = 1;
193 dev->mtu = MAX_JUMBO;
194 } else {
195 np->jumbo = 0;
196 if (mtu[card_idx] > 0 && mtu[card_idx] < PACKET_SIZE)
197 dev->mtu = mtu[card_idx];
198 }
199 np->vlan = (vlan[card_idx] > 0 && vlan[card_idx] < 4096) ?
200 vlan[card_idx] : 0;
201 if (rx_coalesce > 0 && rx_timeout > 0) {
202 np->rx_coalesce = rx_coalesce;
203 np->rx_timeout = rx_timeout;
204 np->coalesce = 1;
205 }
206 np->tx_flow = (tx_flow == 0) ? 0 : 1;
207 np->rx_flow = (rx_flow == 0) ? 0 : 1;
208
209 if (tx_coalesce < 1)
210 tx_coalesce = 1;
211 else if (tx_coalesce > TX_RING_SIZE-1)
212 tx_coalesce = TX_RING_SIZE - 1;
213 }
214 dev->netdev_ops = &netdev_ops;
215 dev->watchdog_timeo = TX_TIMEOUT;
216 dev->ethtool_ops = ðtool_ops;
217#if 0
218 dev->features = NETIF_F_IP_CSUM;
219#endif
220 /* MTU range: 68 - 1536 or 8000 */
221 dev->min_mtu = ETH_MIN_MTU;
222 dev->max_mtu = np->jumbo ? MAX_JUMBO : PACKET_SIZE;
223
224 pci_set_drvdata (pdev, dev);
225
226 ring_space = pci_alloc_consistent (pdev, TX_TOTAL_SIZE, &ring_dma);
227 if (!ring_space)
228 goto err_out_iounmap;
229 np->tx_ring = ring_space;
230 np->tx_ring_dma = ring_dma;
231
232 ring_space = pci_alloc_consistent (pdev, RX_TOTAL_SIZE, &ring_dma);
233 if (!ring_space)
234 goto err_out_unmap_tx;
235 np->rx_ring = ring_space;
236 np->rx_ring_dma = ring_dma;
237
238 /* Parse eeprom data */
239 parse_eeprom (dev);
240
241 /* Find PHY address */
242 err = find_miiphy (dev);
243 if (err)
244 goto err_out_unmap_rx;
245
246 /* Fiber device? */
247 np->phy_media = (dr16(ASICCtrl) & PhyMedia) ? 1 : 0;
248 np->link_status = 0;
249 /* Set media and reset PHY */
250 if (np->phy_media) {
251 /* default Auto-Negotiation for fiber deivices */
252 if (np->an_enable == 2) {
253 np->an_enable = 1;
254 }
255 } else {
256 /* Auto-Negotiation is mandatory for 1000BASE-T,
257 IEEE 802.3ab Annex 28D page 14 */
258 if (np->speed == 1000)
259 np->an_enable = 1;
260 }
261
262 err = register_netdev (dev);
263 if (err)
264 goto err_out_unmap_rx;
265
266 card_idx++;
267
268 printk (KERN_INFO "%s: %s, %pM, IRQ %d\n",
269 dev->name, np->name, dev->dev_addr, irq);
270 if (tx_coalesce > 1)
271 printk(KERN_INFO "tx_coalesce:\t%d packets\n",
272 tx_coalesce);
273 if (np->coalesce)
274 printk(KERN_INFO
275 "rx_coalesce:\t%d packets\n"
276 "rx_timeout: \t%d ns\n",
277 np->rx_coalesce, np->rx_timeout*640);
278 if (np->vlan)
279 printk(KERN_INFO "vlan(id):\t%d\n", np->vlan);
280 return 0;
281
282err_out_unmap_rx:
283 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
284err_out_unmap_tx:
285 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
286err_out_iounmap:
287#ifdef MEM_MAPPING
288 pci_iounmap(pdev, np->ioaddr);
289#endif
290 pci_iounmap(pdev, np->eeprom_addr);
291err_out_dev:
292 free_netdev (dev);
293err_out_res:
294 pci_release_regions (pdev);
295err_out_disable:
296 pci_disable_device (pdev);
297 return err;
298}
299
300static int
301find_miiphy (struct net_device *dev)
302{
303 struct netdev_private *np = netdev_priv(dev);
304 int i, phy_found = 0;
305
306 np->phy_addr = 1;
307
308 for (i = 31; i >= 0; i--) {
309 int mii_status = mii_read (dev, i, 1);
310 if (mii_status != 0xffff && mii_status != 0x0000) {
311 np->phy_addr = i;
312 phy_found++;
313 }
314 }
315 if (!phy_found) {
316 printk (KERN_ERR "%s: No MII PHY found!\n", dev->name);
317 return -ENODEV;
318 }
319 return 0;
320}
321
322static int
323parse_eeprom (struct net_device *dev)
324{
325 struct netdev_private *np = netdev_priv(dev);
326 void __iomem *ioaddr = np->ioaddr;
327 int i, j;
328 u8 sromdata[256];
329 u8 *psib;
330 u32 crc;
331 PSROM_t psrom = (PSROM_t) sromdata;
332
333 int cid, next;
334
335 for (i = 0; i < 128; i++)
336 ((__le16 *) sromdata)[i] = cpu_to_le16(read_eeprom(np, i));
337
338 if (np->pdev->vendor == PCI_VENDOR_ID_DLINK) { /* D-Link Only */
339 /* Check CRC */
340 crc = ~ether_crc_le (256 - 4, sromdata);
341 if (psrom->crc != cpu_to_le32(crc)) {
342 printk (KERN_ERR "%s: EEPROM data CRC error.\n",
343 dev->name);
344 return -1;
345 }
346 }
347
348 /* Set MAC address */
349 for (i = 0; i < 6; i++)
350 dev->dev_addr[i] = psrom->mac_addr[i];
351
352 if (np->chip_id == CHIP_IP1000A) {
353 np->led_mode = psrom->led_mode;
354 return 0;
355 }
356
357 if (np->pdev->vendor != PCI_VENDOR_ID_DLINK) {
358 return 0;
359 }
360
361 /* Parse Software Information Block */
362 i = 0x30;
363 psib = (u8 *) sromdata;
364 do {
365 cid = psib[i++];
366 next = psib[i++];
367 if ((cid == 0 && next == 0) || (cid == 0xff && next == 0xff)) {
368 printk (KERN_ERR "Cell data error\n");
369 return -1;
370 }
371 switch (cid) {
372 case 0: /* Format version */
373 break;
374 case 1: /* End of cell */
375 return 0;
376 case 2: /* Duplex Polarity */
377 np->duplex_polarity = psib[i];
378 dw8(PhyCtrl, dr8(PhyCtrl) | psib[i]);
379 break;
380 case 3: /* Wake Polarity */
381 np->wake_polarity = psib[i];
382 break;
383 case 9: /* Adapter description */
384 j = (next - i > 255) ? 255 : next - i;
385 memcpy (np->name, &(psib[i]), j);
386 break;
387 case 4:
388 case 5:
389 case 6:
390 case 7:
391 case 8: /* Reversed */
392 break;
393 default: /* Unknown cell */
394 return -1;
395 }
396 i = next;
397 } while (1);
398
399 return 0;
400}
401
402static void rio_set_led_mode(struct net_device *dev)
403{
404 struct netdev_private *np = netdev_priv(dev);
405 void __iomem *ioaddr = np->ioaddr;
406 u32 mode;
407
408 if (np->chip_id != CHIP_IP1000A)
409 return;
410
411 mode = dr32(ASICCtrl);
412 mode &= ~(IPG_AC_LED_MODE_BIT_1 | IPG_AC_LED_MODE | IPG_AC_LED_SPEED);
413
414 if (np->led_mode & 0x01)
415 mode |= IPG_AC_LED_MODE;
416 if (np->led_mode & 0x02)
417 mode |= IPG_AC_LED_MODE_BIT_1;
418 if (np->led_mode & 0x08)
419 mode |= IPG_AC_LED_SPEED;
420
421 dw32(ASICCtrl, mode);
422}
423
424static inline dma_addr_t desc_to_dma(struct netdev_desc *desc)
425{
426 return le64_to_cpu(desc->fraginfo) & DMA_BIT_MASK(48);
427}
428
429static void free_list(struct net_device *dev)
430{
431 struct netdev_private *np = netdev_priv(dev);
432 struct sk_buff *skb;
433 int i;
434
435 /* Free all the skbuffs in the queue. */
436 for (i = 0; i < RX_RING_SIZE; i++) {
437 skb = np->rx_skbuff[i];
438 if (skb) {
439 pci_unmap_single(np->pdev, desc_to_dma(&np->rx_ring[i]),
440 skb->len, PCI_DMA_FROMDEVICE);
441 dev_kfree_skb(skb);
442 np->rx_skbuff[i] = NULL;
443 }
444 np->rx_ring[i].status = 0;
445 np->rx_ring[i].fraginfo = 0;
446 }
447 for (i = 0; i < TX_RING_SIZE; i++) {
448 skb = np->tx_skbuff[i];
449 if (skb) {
450 pci_unmap_single(np->pdev, desc_to_dma(&np->tx_ring[i]),
451 skb->len, PCI_DMA_TODEVICE);
452 dev_kfree_skb(skb);
453 np->tx_skbuff[i] = NULL;
454 }
455 }
456}
457
458static void rio_reset_ring(struct netdev_private *np)
459{
460 int i;
461
462 np->cur_rx = 0;
463 np->cur_tx = 0;
464 np->old_rx = 0;
465 np->old_tx = 0;
466
467 for (i = 0; i < TX_RING_SIZE; i++)
468 np->tx_ring[i].status = cpu_to_le64(TFDDone);
469
470 for (i = 0; i < RX_RING_SIZE; i++)
471 np->rx_ring[i].status = 0;
472}
473
474 /* allocate and initialize Tx and Rx descriptors */
475static int alloc_list(struct net_device *dev)
476{
477 struct netdev_private *np = netdev_priv(dev);
478 int i;
479
480 rio_reset_ring(np);
481 np->rx_buf_sz = (dev->mtu <= 1500 ? PACKET_SIZE : dev->mtu + 32);
482
483 /* Initialize Tx descriptors, TFDListPtr leaves in start_xmit(). */
484 for (i = 0; i < TX_RING_SIZE; i++) {
485 np->tx_skbuff[i] = NULL;
486 np->tx_ring[i].next_desc = cpu_to_le64(np->tx_ring_dma +
487 ((i + 1) % TX_RING_SIZE) *
488 sizeof(struct netdev_desc));
489 }
490
491 /* Initialize Rx descriptors & allocate buffers */
492 for (i = 0; i < RX_RING_SIZE; i++) {
493 /* Allocated fixed size of skbuff */
494 struct sk_buff *skb;
495
496 skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
497 np->rx_skbuff[i] = skb;
498 if (!skb) {
499 free_list(dev);
500 return -ENOMEM;
501 }
502
503 np->rx_ring[i].next_desc = cpu_to_le64(np->rx_ring_dma +
504 ((i + 1) % RX_RING_SIZE) *
505 sizeof(struct netdev_desc));
506 /* Rubicon now supports 40 bits of addressing space. */
507 np->rx_ring[i].fraginfo =
508 cpu_to_le64(pci_map_single(
509 np->pdev, skb->data, np->rx_buf_sz,
510 PCI_DMA_FROMDEVICE));
511 np->rx_ring[i].fraginfo |= cpu_to_le64((u64)np->rx_buf_sz << 48);
512 }
513
514 return 0;
515}
516
517static void rio_hw_init(struct net_device *dev)
518{
519 struct netdev_private *np = netdev_priv(dev);
520 void __iomem *ioaddr = np->ioaddr;
521 int i;
522 u16 macctrl;
523
524 /* Reset all logic functions */
525 dw16(ASICCtrl + 2,
526 GlobalReset | DMAReset | FIFOReset | NetworkReset | HostReset);
527 mdelay(10);
528
529 rio_set_led_mode(dev);
530
531 /* DebugCtrl bit 4, 5, 9 must set */
532 dw32(DebugCtrl, dr32(DebugCtrl) | 0x0230);
533
534 if (np->chip_id == CHIP_IP1000A &&
535 (np->pdev->revision == 0x40 || np->pdev->revision == 0x41)) {
536 /* PHY magic taken from ipg driver, undocumented registers */
537 mii_write(dev, np->phy_addr, 31, 0x0001);
538 mii_write(dev, np->phy_addr, 27, 0x01e0);
539 mii_write(dev, np->phy_addr, 31, 0x0002);
540 mii_write(dev, np->phy_addr, 27, 0xeb8e);
541 mii_write(dev, np->phy_addr, 31, 0x0000);
542 mii_write(dev, np->phy_addr, 30, 0x005e);
543 /* advertise 1000BASE-T half & full duplex, prefer MASTER */
544 mii_write(dev, np->phy_addr, MII_CTRL1000, 0x0700);
545 }
546
547 if (np->phy_media)
548 mii_set_media_pcs(dev);
549 else
550 mii_set_media(dev);
551
552 /* Jumbo frame */
553 if (np->jumbo != 0)
554 dw16(MaxFrameSize, MAX_JUMBO+14);
555
556 /* Set RFDListPtr */
557 dw32(RFDListPtr0, np->rx_ring_dma);
558 dw32(RFDListPtr1, 0);
559
560 /* Set station address */
561 /* 16 or 32-bit access is required by TC9020 datasheet but 8-bit works
562 * too. However, it doesn't work on IP1000A so we use 16-bit access.
563 */
564 for (i = 0; i < 3; i++)
565 dw16(StationAddr0 + 2 * i,
566 cpu_to_le16(((u16 *)dev->dev_addr)[i]));
567
568 set_multicast (dev);
569 if (np->coalesce) {
570 dw32(RxDMAIntCtrl, np->rx_coalesce | np->rx_timeout << 16);
571 }
572 /* Set RIO to poll every N*320nsec. */
573 dw8(RxDMAPollPeriod, 0x20);
574 dw8(TxDMAPollPeriod, 0xff);
575 dw8(RxDMABurstThresh, 0x30);
576 dw8(RxDMAUrgentThresh, 0x30);
577 dw32(RmonStatMask, 0x0007ffff);
578 /* clear statistics */
579 clear_stats (dev);
580
581 /* VLAN supported */
582 if (np->vlan) {
583 /* priority field in RxDMAIntCtrl */
584 dw32(RxDMAIntCtrl, dr32(RxDMAIntCtrl) | 0x7 << 10);
585 /* VLANId */
586 dw16(VLANId, np->vlan);
587 /* Length/Type should be 0x8100 */
588 dw32(VLANTag, 0x8100 << 16 | np->vlan);
589 /* Enable AutoVLANuntagging, but disable AutoVLANtagging.
590 VLAN information tagged by TFC' VID, CFI fields. */
591 dw32(MACCtrl, dr32(MACCtrl) | AutoVLANuntagging);
592 }
593
594 /* Start Tx/Rx */
595 dw32(MACCtrl, dr32(MACCtrl) | StatsEnable | RxEnable | TxEnable);
596
597 macctrl = 0;
598 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
599 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
600 macctrl |= (np->tx_flow) ? TxFlowControlEnable : 0;
601 macctrl |= (np->rx_flow) ? RxFlowControlEnable : 0;
602 dw16(MACCtrl, macctrl);
603}
604
605static void rio_hw_stop(struct net_device *dev)
606{
607 struct netdev_private *np = netdev_priv(dev);
608 void __iomem *ioaddr = np->ioaddr;
609
610 /* Disable interrupts */
611 dw16(IntEnable, 0);
612
613 /* Stop Tx and Rx logics */
614 dw32(MACCtrl, TxDisable | RxDisable | StatsDisable);
615}
616
617static int rio_open(struct net_device *dev)
618{
619 struct netdev_private *np = netdev_priv(dev);
620 const int irq = np->pdev->irq;
621 int i;
622
623 i = alloc_list(dev);
624 if (i)
625 return i;
626
627 rio_hw_init(dev);
628
629 i = request_irq(irq, rio_interrupt, IRQF_SHARED, dev->name, dev);
630 if (i) {
631 rio_hw_stop(dev);
632 free_list(dev);
633 return i;
634 }
635
636 timer_setup(&np->timer, rio_timer, 0);
637 np->timer.expires = jiffies + 1 * HZ;
638 add_timer(&np->timer);
639
640 netif_start_queue (dev);
641
642 dl2k_enable_int(np);
643 return 0;
644}
645
646static void
647rio_timer (struct timer_list *t)
648{
649 struct netdev_private *np = from_timer(np, t, timer);
650 struct net_device *dev = pci_get_drvdata(np->pdev);
651 unsigned int entry;
652 int next_tick = 1*HZ;
653 unsigned long flags;
654
655 spin_lock_irqsave(&np->rx_lock, flags);
656 /* Recover rx ring exhausted error */
657 if (np->cur_rx - np->old_rx >= RX_RING_SIZE) {
658 printk(KERN_INFO "Try to recover rx ring exhausted...\n");
659 /* Re-allocate skbuffs to fill the descriptor ring */
660 for (; np->cur_rx - np->old_rx > 0; np->old_rx++) {
661 struct sk_buff *skb;
662 entry = np->old_rx % RX_RING_SIZE;
663 /* Dropped packets don't need to re-allocate */
664 if (np->rx_skbuff[entry] == NULL) {
665 skb = netdev_alloc_skb_ip_align(dev,
666 np->rx_buf_sz);
667 if (skb == NULL) {
668 np->rx_ring[entry].fraginfo = 0;
669 printk (KERN_INFO
670 "%s: Still unable to re-allocate Rx skbuff.#%d\n",
671 dev->name, entry);
672 break;
673 }
674 np->rx_skbuff[entry] = skb;
675 np->rx_ring[entry].fraginfo =
676 cpu_to_le64 (pci_map_single
677 (np->pdev, skb->data, np->rx_buf_sz,
678 PCI_DMA_FROMDEVICE));
679 }
680 np->rx_ring[entry].fraginfo |=
681 cpu_to_le64((u64)np->rx_buf_sz << 48);
682 np->rx_ring[entry].status = 0;
683 } /* end for */
684 } /* end if */
685 spin_unlock_irqrestore (&np->rx_lock, flags);
686 np->timer.expires = jiffies + next_tick;
687 add_timer(&np->timer);
688}
689
690static void
691rio_tx_timeout (struct net_device *dev, unsigned int txqueue)
692{
693 struct netdev_private *np = netdev_priv(dev);
694 void __iomem *ioaddr = np->ioaddr;
695
696 printk (KERN_INFO "%s: Tx timed out (%4.4x), is buffer full?\n",
697 dev->name, dr32(TxStatus));
698 rio_free_tx(dev, 0);
699 dev->if_port = 0;
700 netif_trans_update(dev); /* prevent tx timeout */
701}
702
703static netdev_tx_t
704start_xmit (struct sk_buff *skb, struct net_device *dev)
705{
706 struct netdev_private *np = netdev_priv(dev);
707 void __iomem *ioaddr = np->ioaddr;
708 struct netdev_desc *txdesc;
709 unsigned entry;
710 u64 tfc_vlan_tag = 0;
711
712 if (np->link_status == 0) { /* Link Down */
713 dev_kfree_skb(skb);
714 return NETDEV_TX_OK;
715 }
716 entry = np->cur_tx % TX_RING_SIZE;
717 np->tx_skbuff[entry] = skb;
718 txdesc = &np->tx_ring[entry];
719
720#if 0
721 if (skb->ip_summed == CHECKSUM_PARTIAL) {
722 txdesc->status |=
723 cpu_to_le64 (TCPChecksumEnable | UDPChecksumEnable |
724 IPChecksumEnable);
725 }
726#endif
727 if (np->vlan) {
728 tfc_vlan_tag = VLANTagInsert |
729 ((u64)np->vlan << 32) |
730 ((u64)skb->priority << 45);
731 }
732 txdesc->fraginfo = cpu_to_le64 (pci_map_single (np->pdev, skb->data,
733 skb->len,
734 PCI_DMA_TODEVICE));
735 txdesc->fraginfo |= cpu_to_le64((u64)skb->len << 48);
736
737 /* DL2K bug: DMA fails to get next descriptor ptr in 10Mbps mode
738 * Work around: Always use 1 descriptor in 10Mbps mode */
739 if (entry % np->tx_coalesce == 0 || np->speed == 10)
740 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
741 WordAlignDisable |
742 TxDMAIndicate |
743 (1 << FragCountShift));
744 else
745 txdesc->status = cpu_to_le64 (entry | tfc_vlan_tag |
746 WordAlignDisable |
747 (1 << FragCountShift));
748
749 /* TxDMAPollNow */
750 dw32(DMACtrl, dr32(DMACtrl) | 0x00001000);
751 /* Schedule ISR */
752 dw32(CountDown, 10000);
753 np->cur_tx = (np->cur_tx + 1) % TX_RING_SIZE;
754 if ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
755 < TX_QUEUE_LEN - 1 && np->speed != 10) {
756 /* do nothing */
757 } else if (!netif_queue_stopped(dev)) {
758 netif_stop_queue (dev);
759 }
760
761 /* The first TFDListPtr */
762 if (!dr32(TFDListPtr0)) {
763 dw32(TFDListPtr0, np->tx_ring_dma +
764 entry * sizeof (struct netdev_desc));
765 dw32(TFDListPtr1, 0);
766 }
767
768 return NETDEV_TX_OK;
769}
770
771static irqreturn_t
772rio_interrupt (int irq, void *dev_instance)
773{
774 struct net_device *dev = dev_instance;
775 struct netdev_private *np = netdev_priv(dev);
776 void __iomem *ioaddr = np->ioaddr;
777 unsigned int_status;
778 int cnt = max_intrloop;
779 int handled = 0;
780
781 while (1) {
782 int_status = dr16(IntStatus);
783 dw16(IntStatus, int_status);
784 int_status &= DEFAULT_INTR;
785 if (int_status == 0 || --cnt < 0)
786 break;
787 handled = 1;
788 /* Processing received packets */
789 if (int_status & RxDMAComplete)
790 receive_packet (dev);
791 /* TxDMAComplete interrupt */
792 if ((int_status & (TxDMAComplete|IntRequested))) {
793 int tx_status;
794 tx_status = dr32(TxStatus);
795 if (tx_status & 0x01)
796 tx_error (dev, tx_status);
797 /* Free used tx skbuffs */
798 rio_free_tx (dev, 1);
799 }
800
801 /* Handle uncommon events */
802 if (int_status &
803 (HostError | LinkEvent | UpdateStats))
804 rio_error (dev, int_status);
805 }
806 if (np->cur_tx != np->old_tx)
807 dw32(CountDown, 100);
808 return IRQ_RETVAL(handled);
809}
810
811static void
812rio_free_tx (struct net_device *dev, int irq)
813{
814 struct netdev_private *np = netdev_priv(dev);
815 int entry = np->old_tx % TX_RING_SIZE;
816 int tx_use = 0;
817 unsigned long flag = 0;
818
819 if (irq)
820 spin_lock(&np->tx_lock);
821 else
822 spin_lock_irqsave(&np->tx_lock, flag);
823
824 /* Free used tx skbuffs */
825 while (entry != np->cur_tx) {
826 struct sk_buff *skb;
827
828 if (!(np->tx_ring[entry].status & cpu_to_le64(TFDDone)))
829 break;
830 skb = np->tx_skbuff[entry];
831 pci_unmap_single (np->pdev,
832 desc_to_dma(&np->tx_ring[entry]),
833 skb->len, PCI_DMA_TODEVICE);
834 if (irq)
835 dev_consume_skb_irq(skb);
836 else
837 dev_kfree_skb(skb);
838
839 np->tx_skbuff[entry] = NULL;
840 entry = (entry + 1) % TX_RING_SIZE;
841 tx_use++;
842 }
843 if (irq)
844 spin_unlock(&np->tx_lock);
845 else
846 spin_unlock_irqrestore(&np->tx_lock, flag);
847 np->old_tx = entry;
848
849 /* If the ring is no longer full, clear tx_full and
850 call netif_wake_queue() */
851
852 if (netif_queue_stopped(dev) &&
853 ((np->cur_tx - np->old_tx + TX_RING_SIZE) % TX_RING_SIZE
854 < TX_QUEUE_LEN - 1 || np->speed == 10)) {
855 netif_wake_queue (dev);
856 }
857}
858
859static void
860tx_error (struct net_device *dev, int tx_status)
861{
862 struct netdev_private *np = netdev_priv(dev);
863 void __iomem *ioaddr = np->ioaddr;
864 int frame_id;
865 int i;
866
867 frame_id = (tx_status & 0xffff0000);
868 printk (KERN_ERR "%s: Transmit error, TxStatus %4.4x, FrameId %d.\n",
869 dev->name, tx_status, frame_id);
870 dev->stats.tx_errors++;
871 /* Ttransmit Underrun */
872 if (tx_status & 0x10) {
873 dev->stats.tx_fifo_errors++;
874 dw16(TxStartThresh, dr16(TxStartThresh) + 0x10);
875 /* Transmit Underrun need to set TxReset, DMARest, FIFOReset */
876 dw16(ASICCtrl + 2,
877 TxReset | DMAReset | FIFOReset | NetworkReset);
878 /* Wait for ResetBusy bit clear */
879 for (i = 50; i > 0; i--) {
880 if (!(dr16(ASICCtrl + 2) & ResetBusy))
881 break;
882 mdelay (1);
883 }
884 rio_set_led_mode(dev);
885 rio_free_tx (dev, 1);
886 /* Reset TFDListPtr */
887 dw32(TFDListPtr0, np->tx_ring_dma +
888 np->old_tx * sizeof (struct netdev_desc));
889 dw32(TFDListPtr1, 0);
890
891 /* Let TxStartThresh stay default value */
892 }
893 /* Late Collision */
894 if (tx_status & 0x04) {
895 dev->stats.tx_fifo_errors++;
896 /* TxReset and clear FIFO */
897 dw16(ASICCtrl + 2, TxReset | FIFOReset);
898 /* Wait reset done */
899 for (i = 50; i > 0; i--) {
900 if (!(dr16(ASICCtrl + 2) & ResetBusy))
901 break;
902 mdelay (1);
903 }
904 rio_set_led_mode(dev);
905 /* Let TxStartThresh stay default value */
906 }
907 /* Maximum Collisions */
908 if (tx_status & 0x08)
909 dev->stats.collisions++;
910 /* Restart the Tx */
911 dw32(MACCtrl, dr16(MACCtrl) | TxEnable);
912}
913
914static int
915receive_packet (struct net_device *dev)
916{
917 struct netdev_private *np = netdev_priv(dev);
918 int entry = np->cur_rx % RX_RING_SIZE;
919 int cnt = 30;
920
921 /* If RFDDone, FrameStart and FrameEnd set, there is a new packet in. */
922 while (1) {
923 struct netdev_desc *desc = &np->rx_ring[entry];
924 int pkt_len;
925 u64 frame_status;
926
927 if (!(desc->status & cpu_to_le64(RFDDone)) ||
928 !(desc->status & cpu_to_le64(FrameStart)) ||
929 !(desc->status & cpu_to_le64(FrameEnd)))
930 break;
931
932 /* Chip omits the CRC. */
933 frame_status = le64_to_cpu(desc->status);
934 pkt_len = frame_status & 0xffff;
935 if (--cnt < 0)
936 break;
937 /* Update rx error statistics, drop packet. */
938 if (frame_status & RFS_Errors) {
939 dev->stats.rx_errors++;
940 if (frame_status & (RxRuntFrame | RxLengthError))
941 dev->stats.rx_length_errors++;
942 if (frame_status & RxFCSError)
943 dev->stats.rx_crc_errors++;
944 if (frame_status & RxAlignmentError && np->speed != 1000)
945 dev->stats.rx_frame_errors++;
946 if (frame_status & RxFIFOOverrun)
947 dev->stats.rx_fifo_errors++;
948 } else {
949 struct sk_buff *skb;
950
951 /* Small skbuffs for short packets */
952 if (pkt_len > copy_thresh) {
953 pci_unmap_single (np->pdev,
954 desc_to_dma(desc),
955 np->rx_buf_sz,
956 PCI_DMA_FROMDEVICE);
957 skb_put (skb = np->rx_skbuff[entry], pkt_len);
958 np->rx_skbuff[entry] = NULL;
959 } else if ((skb = netdev_alloc_skb_ip_align(dev, pkt_len))) {
960 pci_dma_sync_single_for_cpu(np->pdev,
961 desc_to_dma(desc),
962 np->rx_buf_sz,
963 PCI_DMA_FROMDEVICE);
964 skb_copy_to_linear_data (skb,
965 np->rx_skbuff[entry]->data,
966 pkt_len);
967 skb_put (skb, pkt_len);
968 pci_dma_sync_single_for_device(np->pdev,
969 desc_to_dma(desc),
970 np->rx_buf_sz,
971 PCI_DMA_FROMDEVICE);
972 }
973 skb->protocol = eth_type_trans (skb, dev);
974#if 0
975 /* Checksum done by hw, but csum value unavailable. */
976 if (np->pdev->pci_rev_id >= 0x0c &&
977 !(frame_status & (TCPError | UDPError | IPError))) {
978 skb->ip_summed = CHECKSUM_UNNECESSARY;
979 }
980#endif
981 netif_rx (skb);
982 }
983 entry = (entry + 1) % RX_RING_SIZE;
984 }
985 spin_lock(&np->rx_lock);
986 np->cur_rx = entry;
987 /* Re-allocate skbuffs to fill the descriptor ring */
988 entry = np->old_rx;
989 while (entry != np->cur_rx) {
990 struct sk_buff *skb;
991 /* Dropped packets don't need to re-allocate */
992 if (np->rx_skbuff[entry] == NULL) {
993 skb = netdev_alloc_skb_ip_align(dev, np->rx_buf_sz);
994 if (skb == NULL) {
995 np->rx_ring[entry].fraginfo = 0;
996 printk (KERN_INFO
997 "%s: receive_packet: "
998 "Unable to re-allocate Rx skbuff.#%d\n",
999 dev->name, entry);
1000 break;
1001 }
1002 np->rx_skbuff[entry] = skb;
1003 np->rx_ring[entry].fraginfo =
1004 cpu_to_le64 (pci_map_single
1005 (np->pdev, skb->data, np->rx_buf_sz,
1006 PCI_DMA_FROMDEVICE));
1007 }
1008 np->rx_ring[entry].fraginfo |=
1009 cpu_to_le64((u64)np->rx_buf_sz << 48);
1010 np->rx_ring[entry].status = 0;
1011 entry = (entry + 1) % RX_RING_SIZE;
1012 }
1013 np->old_rx = entry;
1014 spin_unlock(&np->rx_lock);
1015 return 0;
1016}
1017
1018static void
1019rio_error (struct net_device *dev, int int_status)
1020{
1021 struct netdev_private *np = netdev_priv(dev);
1022 void __iomem *ioaddr = np->ioaddr;
1023 u16 macctrl;
1024
1025 /* Link change event */
1026 if (int_status & LinkEvent) {
1027 if (mii_wait_link (dev, 10) == 0) {
1028 printk (KERN_INFO "%s: Link up\n", dev->name);
1029 if (np->phy_media)
1030 mii_get_media_pcs (dev);
1031 else
1032 mii_get_media (dev);
1033 if (np->speed == 1000)
1034 np->tx_coalesce = tx_coalesce;
1035 else
1036 np->tx_coalesce = 1;
1037 macctrl = 0;
1038 macctrl |= (np->vlan) ? AutoVLANuntagging : 0;
1039 macctrl |= (np->full_duplex) ? DuplexSelect : 0;
1040 macctrl |= (np->tx_flow) ?
1041 TxFlowControlEnable : 0;
1042 macctrl |= (np->rx_flow) ?
1043 RxFlowControlEnable : 0;
1044 dw16(MACCtrl, macctrl);
1045 np->link_status = 1;
1046 netif_carrier_on(dev);
1047 } else {
1048 printk (KERN_INFO "%s: Link off\n", dev->name);
1049 np->link_status = 0;
1050 netif_carrier_off(dev);
1051 }
1052 }
1053
1054 /* UpdateStats statistics registers */
1055 if (int_status & UpdateStats) {
1056 get_stats (dev);
1057 }
1058
1059 /* PCI Error, a catastronphic error related to the bus interface
1060 occurs, set GlobalReset and HostReset to reset. */
1061 if (int_status & HostError) {
1062 printk (KERN_ERR "%s: HostError! IntStatus %4.4x.\n",
1063 dev->name, int_status);
1064 dw16(ASICCtrl + 2, GlobalReset | HostReset);
1065 mdelay (500);
1066 rio_set_led_mode(dev);
1067 }
1068}
1069
1070static struct net_device_stats *
1071get_stats (struct net_device *dev)
1072{
1073 struct netdev_private *np = netdev_priv(dev);
1074 void __iomem *ioaddr = np->ioaddr;
1075#ifdef MEM_MAPPING
1076 int i;
1077#endif
1078 unsigned int stat_reg;
1079
1080 /* All statistics registers need to be acknowledged,
1081 else statistic overflow could cause problems */
1082
1083 dev->stats.rx_packets += dr32(FramesRcvOk);
1084 dev->stats.tx_packets += dr32(FramesXmtOk);
1085 dev->stats.rx_bytes += dr32(OctetRcvOk);
1086 dev->stats.tx_bytes += dr32(OctetXmtOk);
1087
1088 dev->stats.multicast = dr32(McstFramesRcvdOk);
1089 dev->stats.collisions += dr32(SingleColFrames)
1090 + dr32(MultiColFrames);
1091
1092 /* detailed tx errors */
1093 stat_reg = dr16(FramesAbortXSColls);
1094 dev->stats.tx_aborted_errors += stat_reg;
1095 dev->stats.tx_errors += stat_reg;
1096
1097 stat_reg = dr16(CarrierSenseErrors);
1098 dev->stats.tx_carrier_errors += stat_reg;
1099 dev->stats.tx_errors += stat_reg;
1100
1101 /* Clear all other statistic register. */
1102 dr32(McstOctetXmtOk);
1103 dr16(BcstFramesXmtdOk);
1104 dr32(McstFramesXmtdOk);
1105 dr16(BcstFramesRcvdOk);
1106 dr16(MacControlFramesRcvd);
1107 dr16(FrameTooLongErrors);
1108 dr16(InRangeLengthErrors);
1109 dr16(FramesCheckSeqErrors);
1110 dr16(FramesLostRxErrors);
1111 dr32(McstOctetXmtOk);
1112 dr32(BcstOctetXmtOk);
1113 dr32(McstFramesXmtdOk);
1114 dr32(FramesWDeferredXmt);
1115 dr32(LateCollisions);
1116 dr16(BcstFramesXmtdOk);
1117 dr16(MacControlFramesXmtd);
1118 dr16(FramesWEXDeferal);
1119
1120#ifdef MEM_MAPPING
1121 for (i = 0x100; i <= 0x150; i += 4)
1122 dr32(i);
1123#endif
1124 dr16(TxJumboFrames);
1125 dr16(RxJumboFrames);
1126 dr16(TCPCheckSumErrors);
1127 dr16(UDPCheckSumErrors);
1128 dr16(IPCheckSumErrors);
1129 return &dev->stats;
1130}
1131
1132static int
1133clear_stats (struct net_device *dev)
1134{
1135 struct netdev_private *np = netdev_priv(dev);
1136 void __iomem *ioaddr = np->ioaddr;
1137#ifdef MEM_MAPPING
1138 int i;
1139#endif
1140
1141 /* All statistics registers need to be acknowledged,
1142 else statistic overflow could cause problems */
1143 dr32(FramesRcvOk);
1144 dr32(FramesXmtOk);
1145 dr32(OctetRcvOk);
1146 dr32(OctetXmtOk);
1147
1148 dr32(McstFramesRcvdOk);
1149 dr32(SingleColFrames);
1150 dr32(MultiColFrames);
1151 dr32(LateCollisions);
1152 /* detailed rx errors */
1153 dr16(FrameTooLongErrors);
1154 dr16(InRangeLengthErrors);
1155 dr16(FramesCheckSeqErrors);
1156 dr16(FramesLostRxErrors);
1157
1158 /* detailed tx errors */
1159 dr16(FramesAbortXSColls);
1160 dr16(CarrierSenseErrors);
1161
1162 /* Clear all other statistic register. */
1163 dr32(McstOctetXmtOk);
1164 dr16(BcstFramesXmtdOk);
1165 dr32(McstFramesXmtdOk);
1166 dr16(BcstFramesRcvdOk);
1167 dr16(MacControlFramesRcvd);
1168 dr32(McstOctetXmtOk);
1169 dr32(BcstOctetXmtOk);
1170 dr32(McstFramesXmtdOk);
1171 dr32(FramesWDeferredXmt);
1172 dr16(BcstFramesXmtdOk);
1173 dr16(MacControlFramesXmtd);
1174 dr16(FramesWEXDeferal);
1175#ifdef MEM_MAPPING
1176 for (i = 0x100; i <= 0x150; i += 4)
1177 dr32(i);
1178#endif
1179 dr16(TxJumboFrames);
1180 dr16(RxJumboFrames);
1181 dr16(TCPCheckSumErrors);
1182 dr16(UDPCheckSumErrors);
1183 dr16(IPCheckSumErrors);
1184 return 0;
1185}
1186
1187static void
1188set_multicast (struct net_device *dev)
1189{
1190 struct netdev_private *np = netdev_priv(dev);
1191 void __iomem *ioaddr = np->ioaddr;
1192 u32 hash_table[2];
1193 u16 rx_mode = 0;
1194
1195 hash_table[0] = hash_table[1] = 0;
1196 /* RxFlowcontrol DA: 01-80-C2-00-00-01. Hash index=0x39 */
1197 hash_table[1] |= 0x02000000;
1198 if (dev->flags & IFF_PROMISC) {
1199 /* Receive all frames promiscuously. */
1200 rx_mode = ReceiveAllFrames;
1201 } else if ((dev->flags & IFF_ALLMULTI) ||
1202 (netdev_mc_count(dev) > multicast_filter_limit)) {
1203 /* Receive broadcast and multicast frames */
1204 rx_mode = ReceiveBroadcast | ReceiveMulticast | ReceiveUnicast;
1205 } else if (!netdev_mc_empty(dev)) {
1206 struct netdev_hw_addr *ha;
1207 /* Receive broadcast frames and multicast frames filtering
1208 by Hashtable */
1209 rx_mode =
1210 ReceiveBroadcast | ReceiveMulticastHash | ReceiveUnicast;
1211 netdev_for_each_mc_addr(ha, dev) {
1212 int bit, index = 0;
1213 int crc = ether_crc_le(ETH_ALEN, ha->addr);
1214 /* The inverted high significant 6 bits of CRC are
1215 used as an index to hashtable */
1216 for (bit = 0; bit < 6; bit++)
1217 if (crc & (1 << (31 - bit)))
1218 index |= (1 << bit);
1219 hash_table[index / 32] |= (1 << (index % 32));
1220 }
1221 } else {
1222 rx_mode = ReceiveBroadcast | ReceiveUnicast;
1223 }
1224 if (np->vlan) {
1225 /* ReceiveVLANMatch field in ReceiveMode */
1226 rx_mode |= ReceiveVLANMatch;
1227 }
1228
1229 dw32(HashTable0, hash_table[0]);
1230 dw32(HashTable1, hash_table[1]);
1231 dw16(ReceiveMode, rx_mode);
1232}
1233
1234static void rio_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1235{
1236 struct netdev_private *np = netdev_priv(dev);
1237
1238 strlcpy(info->driver, "dl2k", sizeof(info->driver));
1239 strlcpy(info->bus_info, pci_name(np->pdev), sizeof(info->bus_info));
1240}
1241
1242static int rio_get_link_ksettings(struct net_device *dev,
1243 struct ethtool_link_ksettings *cmd)
1244{
1245 struct netdev_private *np = netdev_priv(dev);
1246 u32 supported, advertising;
1247
1248 if (np->phy_media) {
1249 /* fiber device */
1250 supported = SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1251 advertising = ADVERTISED_Autoneg | ADVERTISED_FIBRE;
1252 cmd->base.port = PORT_FIBRE;
1253 } else {
1254 /* copper device */
1255 supported = SUPPORTED_10baseT_Half |
1256 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half
1257 | SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full |
1258 SUPPORTED_Autoneg | SUPPORTED_MII;
1259 advertising = ADVERTISED_10baseT_Half |
1260 ADVERTISED_10baseT_Full | ADVERTISED_100baseT_Half |
1261 ADVERTISED_100baseT_Full | ADVERTISED_1000baseT_Full |
1262 ADVERTISED_Autoneg | ADVERTISED_MII;
1263 cmd->base.port = PORT_MII;
1264 }
1265 if (np->link_status) {
1266 cmd->base.speed = np->speed;
1267 cmd->base.duplex = np->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1268 } else {
1269 cmd->base.speed = SPEED_UNKNOWN;
1270 cmd->base.duplex = DUPLEX_UNKNOWN;
1271 }
1272 if (np->an_enable)
1273 cmd->base.autoneg = AUTONEG_ENABLE;
1274 else
1275 cmd->base.autoneg = AUTONEG_DISABLE;
1276
1277 cmd->base.phy_address = np->phy_addr;
1278
1279 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
1280 supported);
1281 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
1282 advertising);
1283
1284 return 0;
1285}
1286
1287static int rio_set_link_ksettings(struct net_device *dev,
1288 const struct ethtool_link_ksettings *cmd)
1289{
1290 struct netdev_private *np = netdev_priv(dev);
1291 u32 speed = cmd->base.speed;
1292 u8 duplex = cmd->base.duplex;
1293
1294 netif_carrier_off(dev);
1295 if (cmd->base.autoneg == AUTONEG_ENABLE) {
1296 if (np->an_enable) {
1297 return 0;
1298 } else {
1299 np->an_enable = 1;
1300 mii_set_media(dev);
1301 return 0;
1302 }
1303 } else {
1304 np->an_enable = 0;
1305 if (np->speed == 1000) {
1306 speed = SPEED_100;
1307 duplex = DUPLEX_FULL;
1308 printk("Warning!! Can't disable Auto negotiation in 1000Mbps, change to Manual 100Mbps, Full duplex.\n");
1309 }
1310 switch (speed) {
1311 case SPEED_10:
1312 np->speed = 10;
1313 np->full_duplex = (duplex == DUPLEX_FULL);
1314 break;
1315 case SPEED_100:
1316 np->speed = 100;
1317 np->full_duplex = (duplex == DUPLEX_FULL);
1318 break;
1319 case SPEED_1000: /* not supported */
1320 default:
1321 return -EINVAL;
1322 }
1323 mii_set_media(dev);
1324 }
1325 return 0;
1326}
1327
1328static u32 rio_get_link(struct net_device *dev)
1329{
1330 struct netdev_private *np = netdev_priv(dev);
1331 return np->link_status;
1332}
1333
1334static const struct ethtool_ops ethtool_ops = {
1335 .get_drvinfo = rio_get_drvinfo,
1336 .get_link = rio_get_link,
1337 .get_link_ksettings = rio_get_link_ksettings,
1338 .set_link_ksettings = rio_set_link_ksettings,
1339};
1340
1341static int
1342rio_ioctl (struct net_device *dev, struct ifreq *rq, int cmd)
1343{
1344 int phy_addr;
1345 struct netdev_private *np = netdev_priv(dev);
1346 struct mii_ioctl_data *miidata = if_mii(rq);
1347
1348 phy_addr = np->phy_addr;
1349 switch (cmd) {
1350 case SIOCGMIIPHY:
1351 miidata->phy_id = phy_addr;
1352 break;
1353 case SIOCGMIIREG:
1354 miidata->val_out = mii_read (dev, phy_addr, miidata->reg_num);
1355 break;
1356 case SIOCSMIIREG:
1357 if (!capable(CAP_NET_ADMIN))
1358 return -EPERM;
1359 mii_write (dev, phy_addr, miidata->reg_num, miidata->val_in);
1360 break;
1361 default:
1362 return -EOPNOTSUPP;
1363 }
1364 return 0;
1365}
1366
1367#define EEP_READ 0x0200
1368#define EEP_BUSY 0x8000
1369/* Read the EEPROM word */
1370/* We use I/O instruction to read/write eeprom to avoid fail on some machines */
1371static int read_eeprom(struct netdev_private *np, int eep_addr)
1372{
1373 void __iomem *ioaddr = np->eeprom_addr;
1374 int i = 1000;
1375
1376 dw16(EepromCtrl, EEP_READ | (eep_addr & 0xff));
1377 while (i-- > 0) {
1378 if (!(dr16(EepromCtrl) & EEP_BUSY))
1379 return dr16(EepromData);
1380 }
1381 return 0;
1382}
1383
1384enum phy_ctrl_bits {
1385 MII_READ = 0x00, MII_CLK = 0x01, MII_DATA1 = 0x02, MII_WRITE = 0x04,
1386 MII_DUPLEX = 0x08,
1387};
1388
1389#define mii_delay() dr8(PhyCtrl)
1390static void
1391mii_sendbit (struct net_device *dev, u32 data)
1392{
1393 struct netdev_private *np = netdev_priv(dev);
1394 void __iomem *ioaddr = np->ioaddr;
1395
1396 data = ((data) ? MII_DATA1 : 0) | (dr8(PhyCtrl) & 0xf8) | MII_WRITE;
1397 dw8(PhyCtrl, data);
1398 mii_delay ();
1399 dw8(PhyCtrl, data | MII_CLK);
1400 mii_delay ();
1401}
1402
1403static int
1404mii_getbit (struct net_device *dev)
1405{
1406 struct netdev_private *np = netdev_priv(dev);
1407 void __iomem *ioaddr = np->ioaddr;
1408 u8 data;
1409
1410 data = (dr8(PhyCtrl) & 0xf8) | MII_READ;
1411 dw8(PhyCtrl, data);
1412 mii_delay ();
1413 dw8(PhyCtrl, data | MII_CLK);
1414 mii_delay ();
1415 return (dr8(PhyCtrl) >> 1) & 1;
1416}
1417
1418static void
1419mii_send_bits (struct net_device *dev, u32 data, int len)
1420{
1421 int i;
1422
1423 for (i = len - 1; i >= 0; i--) {
1424 mii_sendbit (dev, data & (1 << i));
1425 }
1426}
1427
1428static int
1429mii_read (struct net_device *dev, int phy_addr, int reg_num)
1430{
1431 u32 cmd;
1432 int i;
1433 u32 retval = 0;
1434
1435 /* Preamble */
1436 mii_send_bits (dev, 0xffffffff, 32);
1437 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1438 /* ST,OP = 0110'b for read operation */
1439 cmd = (0x06 << 10 | phy_addr << 5 | reg_num);
1440 mii_send_bits (dev, cmd, 14);
1441 /* Turnaround */
1442 if (mii_getbit (dev))
1443 goto err_out;
1444 /* Read data */
1445 for (i = 0; i < 16; i++) {
1446 retval |= mii_getbit (dev);
1447 retval <<= 1;
1448 }
1449 /* End cycle */
1450 mii_getbit (dev);
1451 return (retval >> 1) & 0xffff;
1452
1453 err_out:
1454 return 0;
1455}
1456static int
1457mii_write (struct net_device *dev, int phy_addr, int reg_num, u16 data)
1458{
1459 u32 cmd;
1460
1461 /* Preamble */
1462 mii_send_bits (dev, 0xffffffff, 32);
1463 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */
1464 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */
1465 cmd = (0x5002 << 16) | (phy_addr << 23) | (reg_num << 18) | data;
1466 mii_send_bits (dev, cmd, 32);
1467 /* End cycle */
1468 mii_getbit (dev);
1469 return 0;
1470}
1471static int
1472mii_wait_link (struct net_device *dev, int wait)
1473{
1474 __u16 bmsr;
1475 int phy_addr;
1476 struct netdev_private *np;
1477
1478 np = netdev_priv(dev);
1479 phy_addr = np->phy_addr;
1480
1481 do {
1482 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1483 if (bmsr & BMSR_LSTATUS)
1484 return 0;
1485 mdelay (1);
1486 } while (--wait > 0);
1487 return -1;
1488}
1489static int
1490mii_get_media (struct net_device *dev)
1491{
1492 __u16 negotiate;
1493 __u16 bmsr;
1494 __u16 mscr;
1495 __u16 mssr;
1496 int phy_addr;
1497 struct netdev_private *np;
1498
1499 np = netdev_priv(dev);
1500 phy_addr = np->phy_addr;
1501
1502 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1503 if (np->an_enable) {
1504 if (!(bmsr & BMSR_ANEGCOMPLETE)) {
1505 /* Auto-Negotiation not completed */
1506 return -1;
1507 }
1508 negotiate = mii_read (dev, phy_addr, MII_ADVERTISE) &
1509 mii_read (dev, phy_addr, MII_LPA);
1510 mscr = mii_read (dev, phy_addr, MII_CTRL1000);
1511 mssr = mii_read (dev, phy_addr, MII_STAT1000);
1512 if (mscr & ADVERTISE_1000FULL && mssr & LPA_1000FULL) {
1513 np->speed = 1000;
1514 np->full_duplex = 1;
1515 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1516 } else if (mscr & ADVERTISE_1000HALF && mssr & LPA_1000HALF) {
1517 np->speed = 1000;
1518 np->full_duplex = 0;
1519 printk (KERN_INFO "Auto 1000 Mbps, Half duplex\n");
1520 } else if (negotiate & ADVERTISE_100FULL) {
1521 np->speed = 100;
1522 np->full_duplex = 1;
1523 printk (KERN_INFO "Auto 100 Mbps, Full duplex\n");
1524 } else if (negotiate & ADVERTISE_100HALF) {
1525 np->speed = 100;
1526 np->full_duplex = 0;
1527 printk (KERN_INFO "Auto 100 Mbps, Half duplex\n");
1528 } else if (negotiate & ADVERTISE_10FULL) {
1529 np->speed = 10;
1530 np->full_duplex = 1;
1531 printk (KERN_INFO "Auto 10 Mbps, Full duplex\n");
1532 } else if (negotiate & ADVERTISE_10HALF) {
1533 np->speed = 10;
1534 np->full_duplex = 0;
1535 printk (KERN_INFO "Auto 10 Mbps, Half duplex\n");
1536 }
1537 if (negotiate & ADVERTISE_PAUSE_CAP) {
1538 np->tx_flow &= 1;
1539 np->rx_flow &= 1;
1540 } else if (negotiate & ADVERTISE_PAUSE_ASYM) {
1541 np->tx_flow = 0;
1542 np->rx_flow &= 1;
1543 }
1544 /* else tx_flow, rx_flow = user select */
1545 } else {
1546 __u16 bmcr = mii_read (dev, phy_addr, MII_BMCR);
1547 switch (bmcr & (BMCR_SPEED100 | BMCR_SPEED1000)) {
1548 case BMCR_SPEED1000:
1549 printk (KERN_INFO "Operating at 1000 Mbps, ");
1550 break;
1551 case BMCR_SPEED100:
1552 printk (KERN_INFO "Operating at 100 Mbps, ");
1553 break;
1554 case 0:
1555 printk (KERN_INFO "Operating at 10 Mbps, ");
1556 }
1557 if (bmcr & BMCR_FULLDPLX) {
1558 printk (KERN_CONT "Full duplex\n");
1559 } else {
1560 printk (KERN_CONT "Half duplex\n");
1561 }
1562 }
1563 if (np->tx_flow)
1564 printk(KERN_INFO "Enable Tx Flow Control\n");
1565 else
1566 printk(KERN_INFO "Disable Tx Flow Control\n");
1567 if (np->rx_flow)
1568 printk(KERN_INFO "Enable Rx Flow Control\n");
1569 else
1570 printk(KERN_INFO "Disable Rx Flow Control\n");
1571
1572 return 0;
1573}
1574
1575static int
1576mii_set_media (struct net_device *dev)
1577{
1578 __u16 pscr;
1579 __u16 bmcr;
1580 __u16 bmsr;
1581 __u16 anar;
1582 int phy_addr;
1583 struct netdev_private *np;
1584 np = netdev_priv(dev);
1585 phy_addr = np->phy_addr;
1586
1587 /* Does user set speed? */
1588 if (np->an_enable) {
1589 /* Advertise capabilities */
1590 bmsr = mii_read (dev, phy_addr, MII_BMSR);
1591 anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
1592 ~(ADVERTISE_100FULL | ADVERTISE_10FULL |
1593 ADVERTISE_100HALF | ADVERTISE_10HALF |
1594 ADVERTISE_100BASE4);
1595 if (bmsr & BMSR_100FULL)
1596 anar |= ADVERTISE_100FULL;
1597 if (bmsr & BMSR_100HALF)
1598 anar |= ADVERTISE_100HALF;
1599 if (bmsr & BMSR_100BASE4)
1600 anar |= ADVERTISE_100BASE4;
1601 if (bmsr & BMSR_10FULL)
1602 anar |= ADVERTISE_10FULL;
1603 if (bmsr & BMSR_10HALF)
1604 anar |= ADVERTISE_10HALF;
1605 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1606 mii_write (dev, phy_addr, MII_ADVERTISE, anar);
1607
1608 /* Enable Auto crossover */
1609 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1610 pscr |= 3 << 5; /* 11'b */
1611 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
1612
1613 /* Soft reset PHY */
1614 mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
1615 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
1616 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1617 mdelay(1);
1618 } else {
1619 /* Force speed setting */
1620 /* 1) Disable Auto crossover */
1621 pscr = mii_read (dev, phy_addr, MII_PHY_SCR);
1622 pscr &= ~(3 << 5);
1623 mii_write (dev, phy_addr, MII_PHY_SCR, pscr);
1624
1625 /* 2) PHY Reset */
1626 bmcr = mii_read (dev, phy_addr, MII_BMCR);
1627 bmcr |= BMCR_RESET;
1628 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1629
1630 /* 3) Power Down */
1631 bmcr = 0x1940; /* must be 0x1940 */
1632 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1633 mdelay (100); /* wait a certain time */
1634
1635 /* 4) Advertise nothing */
1636 mii_write (dev, phy_addr, MII_ADVERTISE, 0);
1637
1638 /* 5) Set media and Power Up */
1639 bmcr = BMCR_PDOWN;
1640 if (np->speed == 100) {
1641 bmcr |= BMCR_SPEED100;
1642 printk (KERN_INFO "Manual 100 Mbps, ");
1643 } else if (np->speed == 10) {
1644 printk (KERN_INFO "Manual 10 Mbps, ");
1645 }
1646 if (np->full_duplex) {
1647 bmcr |= BMCR_FULLDPLX;
1648 printk (KERN_CONT "Full duplex\n");
1649 } else {
1650 printk (KERN_CONT "Half duplex\n");
1651 }
1652#if 0
1653 /* Set 1000BaseT Master/Slave setting */
1654 mscr = mii_read (dev, phy_addr, MII_CTRL1000);
1655 mscr |= MII_MSCR_CFG_ENABLE;
1656 mscr &= ~MII_MSCR_CFG_VALUE = 0;
1657#endif
1658 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1659 mdelay(10);
1660 }
1661 return 0;
1662}
1663
1664static int
1665mii_get_media_pcs (struct net_device *dev)
1666{
1667 __u16 negotiate;
1668 __u16 bmsr;
1669 int phy_addr;
1670 struct netdev_private *np;
1671
1672 np = netdev_priv(dev);
1673 phy_addr = np->phy_addr;
1674
1675 bmsr = mii_read (dev, phy_addr, PCS_BMSR);
1676 if (np->an_enable) {
1677 if (!(bmsr & BMSR_ANEGCOMPLETE)) {
1678 /* Auto-Negotiation not completed */
1679 return -1;
1680 }
1681 negotiate = mii_read (dev, phy_addr, PCS_ANAR) &
1682 mii_read (dev, phy_addr, PCS_ANLPAR);
1683 np->speed = 1000;
1684 if (negotiate & PCS_ANAR_FULL_DUPLEX) {
1685 printk (KERN_INFO "Auto 1000 Mbps, Full duplex\n");
1686 np->full_duplex = 1;
1687 } else {
1688 printk (KERN_INFO "Auto 1000 Mbps, half duplex\n");
1689 np->full_duplex = 0;
1690 }
1691 if (negotiate & PCS_ANAR_PAUSE) {
1692 np->tx_flow &= 1;
1693 np->rx_flow &= 1;
1694 } else if (negotiate & PCS_ANAR_ASYMMETRIC) {
1695 np->tx_flow = 0;
1696 np->rx_flow &= 1;
1697 }
1698 /* else tx_flow, rx_flow = user select */
1699 } else {
1700 __u16 bmcr = mii_read (dev, phy_addr, PCS_BMCR);
1701 printk (KERN_INFO "Operating at 1000 Mbps, ");
1702 if (bmcr & BMCR_FULLDPLX) {
1703 printk (KERN_CONT "Full duplex\n");
1704 } else {
1705 printk (KERN_CONT "Half duplex\n");
1706 }
1707 }
1708 if (np->tx_flow)
1709 printk(KERN_INFO "Enable Tx Flow Control\n");
1710 else
1711 printk(KERN_INFO "Disable Tx Flow Control\n");
1712 if (np->rx_flow)
1713 printk(KERN_INFO "Enable Rx Flow Control\n");
1714 else
1715 printk(KERN_INFO "Disable Rx Flow Control\n");
1716
1717 return 0;
1718}
1719
1720static int
1721mii_set_media_pcs (struct net_device *dev)
1722{
1723 __u16 bmcr;
1724 __u16 esr;
1725 __u16 anar;
1726 int phy_addr;
1727 struct netdev_private *np;
1728 np = netdev_priv(dev);
1729 phy_addr = np->phy_addr;
1730
1731 /* Auto-Negotiation? */
1732 if (np->an_enable) {
1733 /* Advertise capabilities */
1734 esr = mii_read (dev, phy_addr, PCS_ESR);
1735 anar = mii_read (dev, phy_addr, MII_ADVERTISE) &
1736 ~PCS_ANAR_HALF_DUPLEX &
1737 ~PCS_ANAR_FULL_DUPLEX;
1738 if (esr & (MII_ESR_1000BT_HD | MII_ESR_1000BX_HD))
1739 anar |= PCS_ANAR_HALF_DUPLEX;
1740 if (esr & (MII_ESR_1000BT_FD | MII_ESR_1000BX_FD))
1741 anar |= PCS_ANAR_FULL_DUPLEX;
1742 anar |= PCS_ANAR_PAUSE | PCS_ANAR_ASYMMETRIC;
1743 mii_write (dev, phy_addr, MII_ADVERTISE, anar);
1744
1745 /* Soft reset PHY */
1746 mii_write (dev, phy_addr, MII_BMCR, BMCR_RESET);
1747 bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET;
1748 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1749 mdelay(1);
1750 } else {
1751 /* Force speed setting */
1752 /* PHY Reset */
1753 bmcr = BMCR_RESET;
1754 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1755 mdelay(10);
1756 if (np->full_duplex) {
1757 bmcr = BMCR_FULLDPLX;
1758 printk (KERN_INFO "Manual full duplex\n");
1759 } else {
1760 bmcr = 0;
1761 printk (KERN_INFO "Manual half duplex\n");
1762 }
1763 mii_write (dev, phy_addr, MII_BMCR, bmcr);
1764 mdelay(10);
1765
1766 /* Advertise nothing */
1767 mii_write (dev, phy_addr, MII_ADVERTISE, 0);
1768 }
1769 return 0;
1770}
1771
1772
1773static int
1774rio_close (struct net_device *dev)
1775{
1776 struct netdev_private *np = netdev_priv(dev);
1777 struct pci_dev *pdev = np->pdev;
1778
1779 netif_stop_queue (dev);
1780
1781 rio_hw_stop(dev);
1782
1783 free_irq(pdev->irq, dev);
1784 del_timer_sync (&np->timer);
1785
1786 free_list(dev);
1787
1788 return 0;
1789}
1790
1791static void
1792rio_remove1 (struct pci_dev *pdev)
1793{
1794 struct net_device *dev = pci_get_drvdata (pdev);
1795
1796 if (dev) {
1797 struct netdev_private *np = netdev_priv(dev);
1798
1799 unregister_netdev (dev);
1800 pci_free_consistent (pdev, RX_TOTAL_SIZE, np->rx_ring,
1801 np->rx_ring_dma);
1802 pci_free_consistent (pdev, TX_TOTAL_SIZE, np->tx_ring,
1803 np->tx_ring_dma);
1804#ifdef MEM_MAPPING
1805 pci_iounmap(pdev, np->ioaddr);
1806#endif
1807 pci_iounmap(pdev, np->eeprom_addr);
1808 free_netdev (dev);
1809 pci_release_regions (pdev);
1810 pci_disable_device (pdev);
1811 }
1812}
1813
1814#ifdef CONFIG_PM_SLEEP
1815static int rio_suspend(struct device *device)
1816{
1817 struct net_device *dev = dev_get_drvdata(device);
1818 struct netdev_private *np = netdev_priv(dev);
1819
1820 if (!netif_running(dev))
1821 return 0;
1822
1823 netif_device_detach(dev);
1824 del_timer_sync(&np->timer);
1825 rio_hw_stop(dev);
1826
1827 return 0;
1828}
1829
1830static int rio_resume(struct device *device)
1831{
1832 struct net_device *dev = dev_get_drvdata(device);
1833 struct netdev_private *np = netdev_priv(dev);
1834
1835 if (!netif_running(dev))
1836 return 0;
1837
1838 rio_reset_ring(np);
1839 rio_hw_init(dev);
1840 np->timer.expires = jiffies + 1 * HZ;
1841 add_timer(&np->timer);
1842 netif_device_attach(dev);
1843 dl2k_enable_int(np);
1844
1845 return 0;
1846}
1847
1848static SIMPLE_DEV_PM_OPS(rio_pm_ops, rio_suspend, rio_resume);
1849#define RIO_PM_OPS (&rio_pm_ops)
1850
1851#else
1852
1853#define RIO_PM_OPS NULL
1854
1855#endif /* CONFIG_PM_SLEEP */
1856
1857static struct pci_driver rio_driver = {
1858 .name = "dl2k",
1859 .id_table = rio_pci_tbl,
1860 .probe = rio_probe1,
1861 .remove = rio_remove1,
1862 .driver.pm = RIO_PM_OPS,
1863};
1864
1865module_pci_driver(rio_driver);
1866
1867/* Read Documentation/networking/device_drivers/ethernet/dlink/dl2k.rst. */