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1perf-list(1)
2============
3
4NAME
5----
6perf-list - List all symbolic event types
7
8SYNOPSIS
9--------
10[verse]
11'perf list' [--no-desc] [--long-desc]
12 [hw|sw|cache|tracepoint|pmu|sdt|metric|metricgroup|event_glob]
13
14DESCRIPTION
15-----------
16This command displays the symbolic event types which can be selected in the
17various perf commands with the -e option.
18
19OPTIONS
20-------
21--no-desc::
22Don't print descriptions.
23
24-v::
25--long-desc::
26Print longer event descriptions.
27
28--details::
29Print how named events are resolved internally into perf events, and also
30any extra expressions computed by perf stat.
31
32
33[[EVENT_MODIFIERS]]
34EVENT MODIFIERS
35---------------
36
37Events can optionally have a modifier by appending a colon and one or
38more modifiers. Modifiers allow the user to restrict the events to be
39counted. The following modifiers exist:
40
41 u - user-space counting
42 k - kernel counting
43 h - hypervisor counting
44 I - non idle counting
45 G - guest counting (in KVM guests)
46 H - host counting (not in KVM guests)
47 p - precise level
48 P - use maximum detected precise level
49 S - read sample value (PERF_SAMPLE_READ)
50 D - pin the event to the PMU
51 W - group is weak and will fallback to non-group if not schedulable,
52 only supported in 'perf stat' for now.
53
54The 'p' modifier can be used for specifying how precise the instruction
55address should be. The 'p' modifier can be specified multiple times:
56
57 0 - SAMPLE_IP can have arbitrary skid
58 1 - SAMPLE_IP must have constant skid
59 2 - SAMPLE_IP requested to have 0 skid
60 3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid
61 sample shadowing effects.
62
63For Intel systems precise event sampling is implemented with PEBS
64which supports up to precise-level 2, and precise level 3 for
65some special cases
66
67On AMD systems it is implemented using IBS (up to precise-level 2).
68The precise modifier works with event types 0x76 (cpu-cycles, CPU
69clocks not halted) and 0xC1 (micro-ops retired). Both events map to
70IBS execution sampling (IBS op) with the IBS Op Counter Control bit
71(IbsOpCntCtl) set respectively (see AMD64 Architecture Programmer’s
72Manual Volume 2: System Programming, 13.3 Instruction-Based
73Sampling). Examples to use IBS:
74
75 perf record -a -e cpu-cycles:p ... # use ibs op counting cycles
76 perf record -a -e r076:p ... # same as -e cpu-cycles:p
77 perf record -a -e r0C1:p ... # use ibs op counting micro-ops
78
79RAW HARDWARE EVENT DESCRIPTOR
80-----------------------------
81Even when an event is not available in a symbolic form within perf right now,
82it can be encoded in a per processor specific way.
83
84For instance For x86 CPUs NNN represents the raw register encoding with the
85layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout
86of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344,
87Figure 13-7 Performance Event-Select Register (PerfEvtSeln)).
88
89Note: Only the following bit fields can be set in x86 counter
90registers: event, umask, edge, inv, cmask. Esp. guest/host only and
91OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT
92MODIFIERS>>.
93
94Example:
95
96If the Intel docs for a QM720 Core i7 describe an event as:
97
98 Event Umask Event Mask
99 Num. Value Mnemonic Description Comment
100
101 A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and
102 delivered by loop stream detector invert to count
103 cycles
104
105raw encoding of 0x1A8 can be used:
106
107 perf stat -e r1a8 -a sleep 1
108 perf record -e r1a8 ...
109
110You should refer to the processor specific documentation for getting these
111details. Some of them are referenced in the SEE ALSO section below.
112
113ARBITRARY PMUS
114--------------
115
116perf also supports an extended syntax for specifying raw parameters
117to PMUs. Using this typically requires looking up the specific event
118in the CPU vendor specific documentation.
119
120The available PMUs and their raw parameters can be listed with
121
122 ls /sys/devices/*/format
123
124For example the raw event "LSD.UOPS" core pmu event above could
125be specified as
126
127 perf stat -e cpu/event=0xa8,umask=0x1,name=LSD.UOPS_CYCLES,cmask=1/ ...
128
129PER SOCKET PMUS
130---------------
131
132Some PMUs are not associated with a core, but with a whole CPU socket.
133Events on these PMUs generally cannot be sampled, but only counted globally
134with perf stat -a. They can be bound to one logical CPU, but will measure
135all the CPUs in the same socket.
136
137This example measures memory bandwidth every second
138on the first memory controller on socket 0 of a Intel Xeon system
139
140 perf stat -C 0 -a uncore_imc_0/cas_count_read/,uncore_imc_0/cas_count_write/ -I 1000 ...
141
142Each memory controller has its own PMU. Measuring the complete system
143bandwidth would require specifying all imc PMUs (see perf list output),
144and adding the values together. To simplify creation of multiple events,
145prefix and glob matching is supported in the PMU name, and the prefix
146'uncore_' is also ignored when performing the match. So the command above
147can be expanded to all memory controllers by using the syntaxes:
148
149 perf stat -C 0 -a imc/cas_count_read/,imc/cas_count_write/ -I 1000 ...
150 perf stat -C 0 -a *imc*/cas_count_read/,*imc*/cas_count_write/ -I 1000 ...
151
152This example measures the combined core power every second
153
154 perf stat -I 1000 -e power/energy-cores/ -a
155
156ACCESS RESTRICTIONS
157-------------------
158
159For non root users generally only context switched PMU events are available.
160This is normally only the events in the cpu PMU, the predefined events
161like cycles and instructions and some software events.
162
163Other PMUs and global measurements are normally root only.
164Some event qualifiers, such as "any", are also root only.
165
166This can be overriden by setting the kernel.perf_event_paranoid
167sysctl to -1, which allows non root to use these events.
168
169For accessing trace point events perf needs to have read access to
170/sys/kernel/debug/tracing, even when perf_event_paranoid is in a relaxed
171setting.
172
173TRACING
174-------
175
176Some PMUs control advanced hardware tracing capabilities, such as Intel PT,
177that allows low overhead execution tracing. These are described in a separate
178intel-pt.txt document.
179
180PARAMETERIZED EVENTS
181--------------------
182
183Some pmu events listed by 'perf-list' will be displayed with '?' in them. For
184example:
185
186 hv_gpci/dtbp_ptitc,phys_processor_idx=?/
187
188This means that when provided as an event, a value for '?' must
189also be supplied. For example:
190
191 perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ...
192
193EVENT GROUPS
194------------
195
196Perf supports time based multiplexing of events, when the number of events
197active exceeds the number of hardware performance counters. Multiplexing
198can cause measurement errors when the workload changes its execution
199profile.
200
201When metrics are computed using formulas from event counts, it is useful to
202ensure some events are always measured together as a group to minimize multiplexing
203errors. Event groups can be specified using { }.
204
205 perf stat -e '{instructions,cycles}' ...
206
207The number of available performance counters depend on the CPU. A group
208cannot contain more events than available counters.
209For example Intel Core CPUs typically have four generic performance counters
210for the core, plus three fixed counters for instructions, cycles and
211ref-cycles. Some special events have restrictions on which counter they
212can schedule, and may not support multiple instances in a single group.
213When too many events are specified in the group some of them will not
214be measured.
215
216Globally pinned events can limit the number of counters available for
217other groups. On x86 systems, the NMI watchdog pins a counter by default.
218The nmi watchdog can be disabled as root with
219
220 echo 0 > /proc/sys/kernel/nmi_watchdog
221
222Events from multiple different PMUs cannot be mixed in a group, with
223some exceptions for software events.
224
225LEADER SAMPLING
226---------------
227
228perf also supports group leader sampling using the :S specifier.
229
230 perf record -e '{cycles,instructions}:S' ...
231 perf report --group
232
233Normally all events in a event group sample, but with :S only
234the first event (the leader) samples, and it only reads the values of the
235other events in the group.
236
237OPTIONS
238-------
239
240Without options all known events will be listed.
241
242To limit the list use:
243
244. 'hw' or 'hardware' to list hardware events such as cache-misses, etc.
245
246. 'sw' or 'software' to list software events such as context switches, etc.
247
248. 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc.
249
250. 'tracepoint' to list all tracepoint events, alternatively use
251 'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched,
252 block, etc.
253
254. 'pmu' to print the kernel supplied PMU events.
255
256. 'sdt' to list all Statically Defined Tracepoint events.
257
258. 'metric' to list metrics
259
260. 'metricgroup' to list metricgroups with metrics.
261
262. If none of the above is matched, it will apply the supplied glob to all
263 events, printing the ones that match.
264
265. As a last resort, it will do a substring search in all event names.
266
267One or more types can be used at the same time, listing the events for the
268types specified.
269
270Support raw format:
271
272. '--raw-dump', shows the raw-dump of all the events.
273. '--raw-dump [hw|sw|cache|tracepoint|pmu|event_glob]', shows the raw-dump of
274 a certain kind of events.
275
276SEE ALSO
277--------
278linkperf:perf-stat[1], linkperf:perf-top[1],
279linkperf:perf-record[1],
280http://www.intel.com/sdm/[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide],
281http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming]
1perf-list(1)
2============
3
4NAME
5----
6perf-list - List all symbolic event types
7
8SYNOPSIS
9--------
10[verse]
11'perf list' [--no-desc] [--long-desc]
12 [hw|sw|cache|tracepoint|pmu|sdt|metric|metricgroup|event_glob]
13
14DESCRIPTION
15-----------
16This command displays the symbolic event types which can be selected in the
17various perf commands with the -e option.
18
19OPTIONS
20-------
21-d::
22--desc::
23Print extra event descriptions. (default)
24
25--no-desc::
26Don't print descriptions.
27
28-v::
29--long-desc::
30Print longer event descriptions.
31
32--debug::
33Enable debugging output.
34
35--details::
36Print how named events are resolved internally into perf events, and also
37any extra expressions computed by perf stat.
38
39--deprecated::
40Print deprecated events. By default the deprecated events are hidden.
41
42[[EVENT_MODIFIERS]]
43EVENT MODIFIERS
44---------------
45
46Events can optionally have a modifier by appending a colon and one or
47more modifiers. Modifiers allow the user to restrict the events to be
48counted. The following modifiers exist:
49
50 u - user-space counting
51 k - kernel counting
52 h - hypervisor counting
53 I - non idle counting
54 G - guest counting (in KVM guests)
55 H - host counting (not in KVM guests)
56 p - precise level
57 P - use maximum detected precise level
58 S - read sample value (PERF_SAMPLE_READ)
59 D - pin the event to the PMU
60 W - group is weak and will fallback to non-group if not schedulable,
61
62The 'p' modifier can be used for specifying how precise the instruction
63address should be. The 'p' modifier can be specified multiple times:
64
65 0 - SAMPLE_IP can have arbitrary skid
66 1 - SAMPLE_IP must have constant skid
67 2 - SAMPLE_IP requested to have 0 skid
68 3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid
69 sample shadowing effects.
70
71For Intel systems precise event sampling is implemented with PEBS
72which supports up to precise-level 2, and precise level 3 for
73some special cases
74
75On AMD systems it is implemented using IBS (up to precise-level 2).
76The precise modifier works with event types 0x76 (cpu-cycles, CPU
77clocks not halted) and 0xC1 (micro-ops retired). Both events map to
78IBS execution sampling (IBS op) with the IBS Op Counter Control bit
79(IbsOpCntCtl) set respectively (see AMD64 Architecture Programmer’s
80Manual Volume 2: System Programming, 13.3 Instruction-Based
81Sampling). Examples to use IBS:
82
83 perf record -a -e cpu-cycles:p ... # use ibs op counting cycles
84 perf record -a -e r076:p ... # same as -e cpu-cycles:p
85 perf record -a -e r0C1:p ... # use ibs op counting micro-ops
86
87RAW HARDWARE EVENT DESCRIPTOR
88-----------------------------
89Even when an event is not available in a symbolic form within perf right now,
90it can be encoded in a per processor specific way.
91
92For instance For x86 CPUs NNN represents the raw register encoding with the
93layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout
94of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344,
95Figure 13-7 Performance Event-Select Register (PerfEvtSeln)).
96
97Note: Only the following bit fields can be set in x86 counter
98registers: event, umask, edge, inv, cmask. Esp. guest/host only and
99OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT
100MODIFIERS>>.
101
102Example:
103
104If the Intel docs for a QM720 Core i7 describe an event as:
105
106 Event Umask Event Mask
107 Num. Value Mnemonic Description Comment
108
109 A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and
110 delivered by loop stream detector invert to count
111 cycles
112
113raw encoding of 0x1A8 can be used:
114
115 perf stat -e r1a8 -a sleep 1
116 perf record -e r1a8 ...
117
118It's also possible to use pmu syntax:
119
120 perf record -e r1a8 -a sleep 1
121 perf record -e cpu/r1a8/ ...
122 perf record -e cpu/r0x1a8/ ...
123
124You should refer to the processor specific documentation for getting these
125details. Some of them are referenced in the SEE ALSO section below.
126
127ARBITRARY PMUS
128--------------
129
130perf also supports an extended syntax for specifying raw parameters
131to PMUs. Using this typically requires looking up the specific event
132in the CPU vendor specific documentation.
133
134The available PMUs and their raw parameters can be listed with
135
136 ls /sys/devices/*/format
137
138For example the raw event "LSD.UOPS" core pmu event above could
139be specified as
140
141 perf stat -e cpu/event=0xa8,umask=0x1,name=LSD.UOPS_CYCLES,cmask=0x1/ ...
142
143 or using extended name syntax
144
145 perf stat -e cpu/event=0xa8,umask=0x1,cmask=0x1,name=\'LSD.UOPS_CYCLES:cmask=0x1\'/ ...
146
147PER SOCKET PMUS
148---------------
149
150Some PMUs are not associated with a core, but with a whole CPU socket.
151Events on these PMUs generally cannot be sampled, but only counted globally
152with perf stat -a. They can be bound to one logical CPU, but will measure
153all the CPUs in the same socket.
154
155This example measures memory bandwidth every second
156on the first memory controller on socket 0 of a Intel Xeon system
157
158 perf stat -C 0 -a uncore_imc_0/cas_count_read/,uncore_imc_0/cas_count_write/ -I 1000 ...
159
160Each memory controller has its own PMU. Measuring the complete system
161bandwidth would require specifying all imc PMUs (see perf list output),
162and adding the values together. To simplify creation of multiple events,
163prefix and glob matching is supported in the PMU name, and the prefix
164'uncore_' is also ignored when performing the match. So the command above
165can be expanded to all memory controllers by using the syntaxes:
166
167 perf stat -C 0 -a imc/cas_count_read/,imc/cas_count_write/ -I 1000 ...
168 perf stat -C 0 -a *imc*/cas_count_read/,*imc*/cas_count_write/ -I 1000 ...
169
170This example measures the combined core power every second
171
172 perf stat -I 1000 -e power/energy-cores/ -a
173
174ACCESS RESTRICTIONS
175-------------------
176
177For non root users generally only context switched PMU events are available.
178This is normally only the events in the cpu PMU, the predefined events
179like cycles and instructions and some software events.
180
181Other PMUs and global measurements are normally root only.
182Some event qualifiers, such as "any", are also root only.
183
184This can be overridden by setting the kernel.perf_event_paranoid
185sysctl to -1, which allows non root to use these events.
186
187For accessing trace point events perf needs to have read access to
188/sys/kernel/debug/tracing, even when perf_event_paranoid is in a relaxed
189setting.
190
191TRACING
192-------
193
194Some PMUs control advanced hardware tracing capabilities, such as Intel PT,
195that allows low overhead execution tracing. These are described in a separate
196intel-pt.txt document.
197
198PARAMETERIZED EVENTS
199--------------------
200
201Some pmu events listed by 'perf-list' will be displayed with '?' in them. For
202example:
203
204 hv_gpci/dtbp_ptitc,phys_processor_idx=?/
205
206This means that when provided as an event, a value for '?' must
207also be supplied. For example:
208
209 perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ...
210
211EVENT QUALIFIERS:
212
213It is also possible to add extra qualifiers to an event:
214
215percore:
216
217Sums up the event counts for all hardware threads in a core, e.g.:
218
219
220 perf stat -e cpu/event=0,umask=0x3,percore=1/
221
222
223EVENT GROUPS
224------------
225
226Perf supports time based multiplexing of events, when the number of events
227active exceeds the number of hardware performance counters. Multiplexing
228can cause measurement errors when the workload changes its execution
229profile.
230
231When metrics are computed using formulas from event counts, it is useful to
232ensure some events are always measured together as a group to minimize multiplexing
233errors. Event groups can be specified using { }.
234
235 perf stat -e '{instructions,cycles}' ...
236
237The number of available performance counters depend on the CPU. A group
238cannot contain more events than available counters.
239For example Intel Core CPUs typically have four generic performance counters
240for the core, plus three fixed counters for instructions, cycles and
241ref-cycles. Some special events have restrictions on which counter they
242can schedule, and may not support multiple instances in a single group.
243When too many events are specified in the group some of them will not
244be measured.
245
246Globally pinned events can limit the number of counters available for
247other groups. On x86 systems, the NMI watchdog pins a counter by default.
248The nmi watchdog can be disabled as root with
249
250 echo 0 > /proc/sys/kernel/nmi_watchdog
251
252Events from multiple different PMUs cannot be mixed in a group, with
253some exceptions for software events.
254
255LEADER SAMPLING
256---------------
257
258perf also supports group leader sampling using the :S specifier.
259
260 perf record -e '{cycles,instructions}:S' ...
261 perf report --group
262
263Normally all events in an event group sample, but with :S only
264the first event (the leader) samples, and it only reads the values of the
265other events in the group.
266
267However, in the case AUX area events (e.g. Intel PT or CoreSight), the AUX
268area event must be the leader, so then the second event samples, not the first.
269
270OPTIONS
271-------
272
273Without options all known events will be listed.
274
275To limit the list use:
276
277. 'hw' or 'hardware' to list hardware events such as cache-misses, etc.
278
279. 'sw' or 'software' to list software events such as context switches, etc.
280
281. 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc.
282
283. 'tracepoint' to list all tracepoint events, alternatively use
284 'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched,
285 block, etc.
286
287. 'pmu' to print the kernel supplied PMU events.
288
289. 'sdt' to list all Statically Defined Tracepoint events.
290
291. 'metric' to list metrics
292
293. 'metricgroup' to list metricgroups with metrics.
294
295. If none of the above is matched, it will apply the supplied glob to all
296 events, printing the ones that match.
297
298. As a last resort, it will do a substring search in all event names.
299
300One or more types can be used at the same time, listing the events for the
301types specified.
302
303Support raw format:
304
305. '--raw-dump', shows the raw-dump of all the events.
306. '--raw-dump [hw|sw|cache|tracepoint|pmu|event_glob]', shows the raw-dump of
307 a certain kind of events.
308
309SEE ALSO
310--------
311linkperf:perf-stat[1], linkperf:perf-top[1],
312linkperf:perf-record[1],
313http://www.intel.com/sdm/[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide],
314http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming]