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1perf-list(1)
2============
3
4NAME
5----
6perf-list - List all symbolic event types
7
8SYNOPSIS
9--------
10[verse]
11'perf list' [--no-desc] [--long-desc]
12 [hw|sw|cache|tracepoint|pmu|sdt|metric|metricgroup|event_glob]
13
14DESCRIPTION
15-----------
16This command displays the symbolic event types which can be selected in the
17various perf commands with the -e option.
18
19OPTIONS
20-------
21--no-desc::
22Don't print descriptions.
23
24-v::
25--long-desc::
26Print longer event descriptions.
27
28--details::
29Print how named events are resolved internally into perf events, and also
30any extra expressions computed by perf stat.
31
32
33[[EVENT_MODIFIERS]]
34EVENT MODIFIERS
35---------------
36
37Events can optionally have a modifier by appending a colon and one or
38more modifiers. Modifiers allow the user to restrict the events to be
39counted. The following modifiers exist:
40
41 u - user-space counting
42 k - kernel counting
43 h - hypervisor counting
44 I - non idle counting
45 G - guest counting (in KVM guests)
46 H - host counting (not in KVM guests)
47 p - precise level
48 P - use maximum detected precise level
49 S - read sample value (PERF_SAMPLE_READ)
50 D - pin the event to the PMU
51 W - group is weak and will fallback to non-group if not schedulable,
52 only supported in 'perf stat' for now.
53
54The 'p' modifier can be used for specifying how precise the instruction
55address should be. The 'p' modifier can be specified multiple times:
56
57 0 - SAMPLE_IP can have arbitrary skid
58 1 - SAMPLE_IP must have constant skid
59 2 - SAMPLE_IP requested to have 0 skid
60 3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid
61 sample shadowing effects.
62
63For Intel systems precise event sampling is implemented with PEBS
64which supports up to precise-level 2, and precise level 3 for
65some special cases
66
67On AMD systems it is implemented using IBS (up to precise-level 2).
68The precise modifier works with event types 0x76 (cpu-cycles, CPU
69clocks not halted) and 0xC1 (micro-ops retired). Both events map to
70IBS execution sampling (IBS op) with the IBS Op Counter Control bit
71(IbsOpCntCtl) set respectively (see AMD64 Architecture Programmer’s
72Manual Volume 2: System Programming, 13.3 Instruction-Based
73Sampling). Examples to use IBS:
74
75 perf record -a -e cpu-cycles:p ... # use ibs op counting cycles
76 perf record -a -e r076:p ... # same as -e cpu-cycles:p
77 perf record -a -e r0C1:p ... # use ibs op counting micro-ops
78
79RAW HARDWARE EVENT DESCRIPTOR
80-----------------------------
81Even when an event is not available in a symbolic form within perf right now,
82it can be encoded in a per processor specific way.
83
84For instance For x86 CPUs NNN represents the raw register encoding with the
85layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout
86of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344,
87Figure 13-7 Performance Event-Select Register (PerfEvtSeln)).
88
89Note: Only the following bit fields can be set in x86 counter
90registers: event, umask, edge, inv, cmask. Esp. guest/host only and
91OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT
92MODIFIERS>>.
93
94Example:
95
96If the Intel docs for a QM720 Core i7 describe an event as:
97
98 Event Umask Event Mask
99 Num. Value Mnemonic Description Comment
100
101 A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and
102 delivered by loop stream detector invert to count
103 cycles
104
105raw encoding of 0x1A8 can be used:
106
107 perf stat -e r1a8 -a sleep 1
108 perf record -e r1a8 ...
109
110You should refer to the processor specific documentation for getting these
111details. Some of them are referenced in the SEE ALSO section below.
112
113ARBITRARY PMUS
114--------------
115
116perf also supports an extended syntax for specifying raw parameters
117to PMUs. Using this typically requires looking up the specific event
118in the CPU vendor specific documentation.
119
120The available PMUs and their raw parameters can be listed with
121
122 ls /sys/devices/*/format
123
124For example the raw event "LSD.UOPS" core pmu event above could
125be specified as
126
127 perf stat -e cpu/event=0xa8,umask=0x1,name=LSD.UOPS_CYCLES,cmask=1/ ...
128
129PER SOCKET PMUS
130---------------
131
132Some PMUs are not associated with a core, but with a whole CPU socket.
133Events on these PMUs generally cannot be sampled, but only counted globally
134with perf stat -a. They can be bound to one logical CPU, but will measure
135all the CPUs in the same socket.
136
137This example measures memory bandwidth every second
138on the first memory controller on socket 0 of a Intel Xeon system
139
140 perf stat -C 0 -a uncore_imc_0/cas_count_read/,uncore_imc_0/cas_count_write/ -I 1000 ...
141
142Each memory controller has its own PMU. Measuring the complete system
143bandwidth would require specifying all imc PMUs (see perf list output),
144and adding the values together. To simplify creation of multiple events,
145prefix and glob matching is supported in the PMU name, and the prefix
146'uncore_' is also ignored when performing the match. So the command above
147can be expanded to all memory controllers by using the syntaxes:
148
149 perf stat -C 0 -a imc/cas_count_read/,imc/cas_count_write/ -I 1000 ...
150 perf stat -C 0 -a *imc*/cas_count_read/,*imc*/cas_count_write/ -I 1000 ...
151
152This example measures the combined core power every second
153
154 perf stat -I 1000 -e power/energy-cores/ -a
155
156ACCESS RESTRICTIONS
157-------------------
158
159For non root users generally only context switched PMU events are available.
160This is normally only the events in the cpu PMU, the predefined events
161like cycles and instructions and some software events.
162
163Other PMUs and global measurements are normally root only.
164Some event qualifiers, such as "any", are also root only.
165
166This can be overriden by setting the kernel.perf_event_paranoid
167sysctl to -1, which allows non root to use these events.
168
169For accessing trace point events perf needs to have read access to
170/sys/kernel/debug/tracing, even when perf_event_paranoid is in a relaxed
171setting.
172
173TRACING
174-------
175
176Some PMUs control advanced hardware tracing capabilities, such as Intel PT,
177that allows low overhead execution tracing. These are described in a separate
178intel-pt.txt document.
179
180PARAMETERIZED EVENTS
181--------------------
182
183Some pmu events listed by 'perf-list' will be displayed with '?' in them. For
184example:
185
186 hv_gpci/dtbp_ptitc,phys_processor_idx=?/
187
188This means that when provided as an event, a value for '?' must
189also be supplied. For example:
190
191 perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ...
192
193EVENT GROUPS
194------------
195
196Perf supports time based multiplexing of events, when the number of events
197active exceeds the number of hardware performance counters. Multiplexing
198can cause measurement errors when the workload changes its execution
199profile.
200
201When metrics are computed using formulas from event counts, it is useful to
202ensure some events are always measured together as a group to minimize multiplexing
203errors. Event groups can be specified using { }.
204
205 perf stat -e '{instructions,cycles}' ...
206
207The number of available performance counters depend on the CPU. A group
208cannot contain more events than available counters.
209For example Intel Core CPUs typically have four generic performance counters
210for the core, plus three fixed counters for instructions, cycles and
211ref-cycles. Some special events have restrictions on which counter they
212can schedule, and may not support multiple instances in a single group.
213When too many events are specified in the group some of them will not
214be measured.
215
216Globally pinned events can limit the number of counters available for
217other groups. On x86 systems, the NMI watchdog pins a counter by default.
218The nmi watchdog can be disabled as root with
219
220 echo 0 > /proc/sys/kernel/nmi_watchdog
221
222Events from multiple different PMUs cannot be mixed in a group, with
223some exceptions for software events.
224
225LEADER SAMPLING
226---------------
227
228perf also supports group leader sampling using the :S specifier.
229
230 perf record -e '{cycles,instructions}:S' ...
231 perf report --group
232
233Normally all events in a event group sample, but with :S only
234the first event (the leader) samples, and it only reads the values of the
235other events in the group.
236
237OPTIONS
238-------
239
240Without options all known events will be listed.
241
242To limit the list use:
243
244. 'hw' or 'hardware' to list hardware events such as cache-misses, etc.
245
246. 'sw' or 'software' to list software events such as context switches, etc.
247
248. 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc.
249
250. 'tracepoint' to list all tracepoint events, alternatively use
251 'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched,
252 block, etc.
253
254. 'pmu' to print the kernel supplied PMU events.
255
256. 'sdt' to list all Statically Defined Tracepoint events.
257
258. 'metric' to list metrics
259
260. 'metricgroup' to list metricgroups with metrics.
261
262. If none of the above is matched, it will apply the supplied glob to all
263 events, printing the ones that match.
264
265. As a last resort, it will do a substring search in all event names.
266
267One or more types can be used at the same time, listing the events for the
268types specified.
269
270Support raw format:
271
272. '--raw-dump', shows the raw-dump of all the events.
273. '--raw-dump [hw|sw|cache|tracepoint|pmu|event_glob]', shows the raw-dump of
274 a certain kind of events.
275
276SEE ALSO
277--------
278linkperf:perf-stat[1], linkperf:perf-top[1],
279linkperf:perf-record[1],
280http://www.intel.com/sdm/[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide],
281http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming]
1perf-list(1)
2============
3
4NAME
5----
6perf-list - List all symbolic event types
7
8SYNOPSIS
9--------
10[verse]
11'perf list' [--no-desc] [--long-desc] [hw|sw|cache|tracepoint|pmu|event_glob]
12
13DESCRIPTION
14-----------
15This command displays the symbolic event types which can be selected in the
16various perf commands with the -e option.
17
18OPTIONS
19-------
20--no-desc::
21Don't print descriptions.
22
23-v::
24--long-desc::
25Print longer event descriptions.
26
27
28[[EVENT_MODIFIERS]]
29EVENT MODIFIERS
30---------------
31
32Events can optionally have a modifier by appending a colon and one or
33more modifiers. Modifiers allow the user to restrict the events to be
34counted. The following modifiers exist:
35
36 u - user-space counting
37 k - kernel counting
38 h - hypervisor counting
39 I - non idle counting
40 G - guest counting (in KVM guests)
41 H - host counting (not in KVM guests)
42 p - precise level
43 P - use maximum detected precise level
44 S - read sample value (PERF_SAMPLE_READ)
45 D - pin the event to the PMU
46
47The 'p' modifier can be used for specifying how precise the instruction
48address should be. The 'p' modifier can be specified multiple times:
49
50 0 - SAMPLE_IP can have arbitrary skid
51 1 - SAMPLE_IP must have constant skid
52 2 - SAMPLE_IP requested to have 0 skid
53 3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid
54 sample shadowing effects.
55
56For Intel systems precise event sampling is implemented with PEBS
57which supports up to precise-level 2, and precise level 3 for
58some special cases
59
60On AMD systems it is implemented using IBS (up to precise-level 2).
61The precise modifier works with event types 0x76 (cpu-cycles, CPU
62clocks not halted) and 0xC1 (micro-ops retired). Both events map to
63IBS execution sampling (IBS op) with the IBS Op Counter Control bit
64(IbsOpCntCtl) set respectively (see AMD64 Architecture Programmer’s
65Manual Volume 2: System Programming, 13.3 Instruction-Based
66Sampling). Examples to use IBS:
67
68 perf record -a -e cpu-cycles:p ... # use ibs op counting cycles
69 perf record -a -e r076:p ... # same as -e cpu-cycles:p
70 perf record -a -e r0C1:p ... # use ibs op counting micro-ops
71
72RAW HARDWARE EVENT DESCRIPTOR
73-----------------------------
74Even when an event is not available in a symbolic form within perf right now,
75it can be encoded in a per processor specific way.
76
77For instance For x86 CPUs NNN represents the raw register encoding with the
78layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout
79of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344,
80Figure 13-7 Performance Event-Select Register (PerfEvtSeln)).
81
82Note: Only the following bit fields can be set in x86 counter
83registers: event, umask, edge, inv, cmask. Esp. guest/host only and
84OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT
85MODIFIERS>>.
86
87Example:
88
89If the Intel docs for a QM720 Core i7 describe an event as:
90
91 Event Umask Event Mask
92 Num. Value Mnemonic Description Comment
93
94 A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and
95 delivered by loop stream detector invert to count
96 cycles
97
98raw encoding of 0x1A8 can be used:
99
100 perf stat -e r1a8 -a sleep 1
101 perf record -e r1a8 ...
102
103You should refer to the processor specific documentation for getting these
104details. Some of them are referenced in the SEE ALSO section below.
105
106ARBITRARY PMUS
107--------------
108
109perf also supports an extended syntax for specifying raw parameters
110to PMUs. Using this typically requires looking up the specific event
111in the CPU vendor specific documentation.
112
113The available PMUs and their raw parameters can be listed with
114
115 ls /sys/devices/*/format
116
117For example the raw event "LSD.UOPS" core pmu event above could
118be specified as
119
120 perf stat -e cpu/event=0xa8,umask=0x1,name=LSD.UOPS_CYCLES,cmask=1/ ...
121
122PER SOCKET PMUS
123---------------
124
125Some PMUs are not associated with a core, but with a whole CPU socket.
126Events on these PMUs generally cannot be sampled, but only counted globally
127with perf stat -a. They can be bound to one logical CPU, but will measure
128all the CPUs in the same socket.
129
130This example measures memory bandwidth every second
131on the first memory controller on socket 0 of a Intel Xeon system
132
133 perf stat -C 0 -a uncore_imc_0/cas_count_read/,uncore_imc_0/cas_count_write/ -I 1000 ...
134
135Each memory controller has its own PMU. Measuring the complete system
136bandwidth would require specifying all imc PMUs (see perf list output),
137and adding the values together.
138
139This example measures the combined core power every second
140
141 perf stat -I 1000 -e power/energy-cores/ -a
142
143ACCESS RESTRICTIONS
144-------------------
145
146For non root users generally only context switched PMU events are available.
147This is normally only the events in the cpu PMU, the predefined events
148like cycles and instructions and some software events.
149
150Other PMUs and global measurements are normally root only.
151Some event qualifiers, such as "any", are also root only.
152
153This can be overriden by setting the kernel.perf_event_paranoid
154sysctl to -1, which allows non root to use these events.
155
156For accessing trace point events perf needs to have read access to
157/sys/kernel/debug/tracing, even when perf_event_paranoid is in a relaxed
158setting.
159
160TRACING
161-------
162
163Some PMUs control advanced hardware tracing capabilities, such as Intel PT,
164that allows low overhead execution tracing. These are described in a separate
165intel-pt.txt document.
166
167PARAMETERIZED EVENTS
168--------------------
169
170Some pmu events listed by 'perf-list' will be displayed with '?' in them. For
171example:
172
173 hv_gpci/dtbp_ptitc,phys_processor_idx=?/
174
175This means that when provided as an event, a value for '?' must
176also be supplied. For example:
177
178 perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ...
179
180EVENT GROUPS
181------------
182
183Perf supports time based multiplexing of events, when the number of events
184active exceeds the number of hardware performance counters. Multiplexing
185can cause measurement errors when the workload changes its execution
186profile.
187
188When metrics are computed using formulas from event counts, it is useful to
189ensure some events are always measured together as a group to minimize multiplexing
190errors. Event groups can be specified using { }.
191
192 perf stat -e '{instructions,cycles}' ...
193
194The number of available performance counters depend on the CPU. A group
195cannot contain more events than available counters.
196For example Intel Core CPUs typically have four generic performance counters
197for the core, plus three fixed counters for instructions, cycles and
198ref-cycles. Some special events have restrictions on which counter they
199can schedule, and may not support multiple instances in a single group.
200When too many events are specified in the group none of them will not
201be measured.
202
203Globally pinned events can limit the number of counters available for
204other groups. On x86 systems, the NMI watchdog pins a counter by default.
205The nmi watchdog can be disabled as root with
206
207 echo 0 > /proc/sys/kernel/nmi_watchdog
208
209Events from multiple different PMUs cannot be mixed in a group, with
210some exceptions for software events.
211
212LEADER SAMPLING
213---------------
214
215perf also supports group leader sampling using the :S specifier.
216
217 perf record -e '{cycles,instructions}:S' ...
218 perf report --group
219
220Normally all events in a event group sample, but with :S only
221the first event (the leader) samples, and it only reads the values of the
222other events in the group.
223
224OPTIONS
225-------
226
227Without options all known events will be listed.
228
229To limit the list use:
230
231. 'hw' or 'hardware' to list hardware events such as cache-misses, etc.
232
233. 'sw' or 'software' to list software events such as context switches, etc.
234
235. 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc.
236
237. 'tracepoint' to list all tracepoint events, alternatively use
238 'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched,
239 block, etc.
240
241. 'pmu' to print the kernel supplied PMU events.
242
243. If none of the above is matched, it will apply the supplied glob to all
244 events, printing the ones that match.
245
246. As a last resort, it will do a substring search in all event names.
247
248One or more types can be used at the same time, listing the events for the
249types specified.
250
251Support raw format:
252
253. '--raw-dump', shows the raw-dump of all the events.
254. '--raw-dump [hw|sw|cache|tracepoint|pmu|event_glob]', shows the raw-dump of
255 a certain kind of events.
256
257SEE ALSO
258--------
259linkperf:perf-stat[1], linkperf:perf-top[1],
260linkperf:perf-record[1],
261http://www.intel.com/sdm/[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide],
262http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming]