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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * KVM/MIPS: MIPS specific KVM APIs
7 *
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
10 */
11
12#include <linux/bitops.h>
13#include <linux/errno.h>
14#include <linux/err.h>
15#include <linux/kdebug.h>
16#include <linux/module.h>
17#include <linux/uaccess.h>
18#include <linux/vmalloc.h>
19#include <linux/sched/signal.h>
20#include <linux/fs.h>
21#include <linux/bootmem.h>
22
23#include <asm/fpu.h>
24#include <asm/page.h>
25#include <asm/cacheflush.h>
26#include <asm/mmu_context.h>
27#include <asm/pgalloc.h>
28#include <asm/pgtable.h>
29
30#include <linux/kvm_host.h>
31
32#include "interrupt.h"
33#include "commpage.h"
34
35#define CREATE_TRACE_POINTS
36#include "trace.h"
37
38#ifndef VECTORSPACING
39#define VECTORSPACING 0x100 /* for EI/VI mode */
40#endif
41
42#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x)
43struct kvm_stats_debugfs_item debugfs_entries[] = {
44 { "wait", VCPU_STAT(wait_exits), KVM_STAT_VCPU },
45 { "cache", VCPU_STAT(cache_exits), KVM_STAT_VCPU },
46 { "signal", VCPU_STAT(signal_exits), KVM_STAT_VCPU },
47 { "interrupt", VCPU_STAT(int_exits), KVM_STAT_VCPU },
48 { "cop_unusable", VCPU_STAT(cop_unusable_exits), KVM_STAT_VCPU },
49 { "tlbmod", VCPU_STAT(tlbmod_exits), KVM_STAT_VCPU },
50 { "tlbmiss_ld", VCPU_STAT(tlbmiss_ld_exits), KVM_STAT_VCPU },
51 { "tlbmiss_st", VCPU_STAT(tlbmiss_st_exits), KVM_STAT_VCPU },
52 { "addrerr_st", VCPU_STAT(addrerr_st_exits), KVM_STAT_VCPU },
53 { "addrerr_ld", VCPU_STAT(addrerr_ld_exits), KVM_STAT_VCPU },
54 { "syscall", VCPU_STAT(syscall_exits), KVM_STAT_VCPU },
55 { "resvd_inst", VCPU_STAT(resvd_inst_exits), KVM_STAT_VCPU },
56 { "break_inst", VCPU_STAT(break_inst_exits), KVM_STAT_VCPU },
57 { "trap_inst", VCPU_STAT(trap_inst_exits), KVM_STAT_VCPU },
58 { "msa_fpe", VCPU_STAT(msa_fpe_exits), KVM_STAT_VCPU },
59 { "fpe", VCPU_STAT(fpe_exits), KVM_STAT_VCPU },
60 { "msa_disabled", VCPU_STAT(msa_disabled_exits), KVM_STAT_VCPU },
61 { "flush_dcache", VCPU_STAT(flush_dcache_exits), KVM_STAT_VCPU },
62#ifdef CONFIG_KVM_MIPS_VZ
63 { "vz_gpsi", VCPU_STAT(vz_gpsi_exits), KVM_STAT_VCPU },
64 { "vz_gsfc", VCPU_STAT(vz_gsfc_exits), KVM_STAT_VCPU },
65 { "vz_hc", VCPU_STAT(vz_hc_exits), KVM_STAT_VCPU },
66 { "vz_grr", VCPU_STAT(vz_grr_exits), KVM_STAT_VCPU },
67 { "vz_gva", VCPU_STAT(vz_gva_exits), KVM_STAT_VCPU },
68 { "vz_ghfc", VCPU_STAT(vz_ghfc_exits), KVM_STAT_VCPU },
69 { "vz_gpa", VCPU_STAT(vz_gpa_exits), KVM_STAT_VCPU },
70 { "vz_resvd", VCPU_STAT(vz_resvd_exits), KVM_STAT_VCPU },
71#endif
72 { "halt_successful_poll", VCPU_STAT(halt_successful_poll), KVM_STAT_VCPU },
73 { "halt_attempted_poll", VCPU_STAT(halt_attempted_poll), KVM_STAT_VCPU },
74 { "halt_poll_invalid", VCPU_STAT(halt_poll_invalid), KVM_STAT_VCPU },
75 { "halt_wakeup", VCPU_STAT(halt_wakeup), KVM_STAT_VCPU },
76 {NULL}
77};
78
79bool kvm_trace_guest_mode_change;
80
81int kvm_guest_mode_change_trace_reg(void)
82{
83 kvm_trace_guest_mode_change = 1;
84 return 0;
85}
86
87void kvm_guest_mode_change_trace_unreg(void)
88{
89 kvm_trace_guest_mode_change = 0;
90}
91
92/*
93 * XXXKYMA: We are simulatoring a processor that has the WII bit set in
94 * Config7, so we are "runnable" if interrupts are pending
95 */
96int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
97{
98 return !!(vcpu->arch.pending_exceptions);
99}
100
101bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
102{
103 return false;
104}
105
106int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
107{
108 return 1;
109}
110
111int kvm_arch_hardware_enable(void)
112{
113 return kvm_mips_callbacks->hardware_enable();
114}
115
116void kvm_arch_hardware_disable(void)
117{
118 kvm_mips_callbacks->hardware_disable();
119}
120
121int kvm_arch_hardware_setup(void)
122{
123 return 0;
124}
125
126void kvm_arch_check_processor_compat(void *rtn)
127{
128 *(int *)rtn = 0;
129}
130
131int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
132{
133 switch (type) {
134#ifdef CONFIG_KVM_MIPS_VZ
135 case KVM_VM_MIPS_VZ:
136#else
137 case KVM_VM_MIPS_TE:
138#endif
139 break;
140 default:
141 /* Unsupported KVM type */
142 return -EINVAL;
143 };
144
145 /* Allocate page table to map GPA -> RPA */
146 kvm->arch.gpa_mm.pgd = kvm_pgd_alloc();
147 if (!kvm->arch.gpa_mm.pgd)
148 return -ENOMEM;
149
150 return 0;
151}
152
153bool kvm_arch_has_vcpu_debugfs(void)
154{
155 return false;
156}
157
158int kvm_arch_create_vcpu_debugfs(struct kvm_vcpu *vcpu)
159{
160 return 0;
161}
162
163void kvm_mips_free_vcpus(struct kvm *kvm)
164{
165 unsigned int i;
166 struct kvm_vcpu *vcpu;
167
168 kvm_for_each_vcpu(i, vcpu, kvm) {
169 kvm_arch_vcpu_free(vcpu);
170 }
171
172 mutex_lock(&kvm->lock);
173
174 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
175 kvm->vcpus[i] = NULL;
176
177 atomic_set(&kvm->online_vcpus, 0);
178
179 mutex_unlock(&kvm->lock);
180}
181
182static void kvm_mips_free_gpa_pt(struct kvm *kvm)
183{
184 /* It should always be safe to remove after flushing the whole range */
185 WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0));
186 pgd_free(NULL, kvm->arch.gpa_mm.pgd);
187}
188
189void kvm_arch_destroy_vm(struct kvm *kvm)
190{
191 kvm_mips_free_vcpus(kvm);
192 kvm_mips_free_gpa_pt(kvm);
193}
194
195long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
196 unsigned long arg)
197{
198 return -ENOIOCTLCMD;
199}
200
201int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
202 unsigned long npages)
203{
204 return 0;
205}
206
207void kvm_arch_flush_shadow_all(struct kvm *kvm)
208{
209 /* Flush whole GPA */
210 kvm_mips_flush_gpa_pt(kvm, 0, ~0);
211
212 /* Let implementation do the rest */
213 kvm_mips_callbacks->flush_shadow_all(kvm);
214}
215
216void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
217 struct kvm_memory_slot *slot)
218{
219 /*
220 * The slot has been made invalid (ready for moving or deletion), so we
221 * need to ensure that it can no longer be accessed by any guest VCPUs.
222 */
223
224 spin_lock(&kvm->mmu_lock);
225 /* Flush slot from GPA */
226 kvm_mips_flush_gpa_pt(kvm, slot->base_gfn,
227 slot->base_gfn + slot->npages - 1);
228 /* Let implementation do the rest */
229 kvm_mips_callbacks->flush_shadow_memslot(kvm, slot);
230 spin_unlock(&kvm->mmu_lock);
231}
232
233int kvm_arch_prepare_memory_region(struct kvm *kvm,
234 struct kvm_memory_slot *memslot,
235 const struct kvm_userspace_memory_region *mem,
236 enum kvm_mr_change change)
237{
238 return 0;
239}
240
241void kvm_arch_commit_memory_region(struct kvm *kvm,
242 const struct kvm_userspace_memory_region *mem,
243 const struct kvm_memory_slot *old,
244 const struct kvm_memory_slot *new,
245 enum kvm_mr_change change)
246{
247 int needs_flush;
248
249 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
250 __func__, kvm, mem->slot, mem->guest_phys_addr,
251 mem->memory_size, mem->userspace_addr);
252
253 /*
254 * If dirty page logging is enabled, write protect all pages in the slot
255 * ready for dirty logging.
256 *
257 * There is no need to do this in any of the following cases:
258 * CREATE: No dirty mappings will already exist.
259 * MOVE/DELETE: The old mappings will already have been cleaned up by
260 * kvm_arch_flush_shadow_memslot()
261 */
262 if (change == KVM_MR_FLAGS_ONLY &&
263 (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
264 new->flags & KVM_MEM_LOG_DIRTY_PAGES)) {
265 spin_lock(&kvm->mmu_lock);
266 /* Write protect GPA page table entries */
267 needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn,
268 new->base_gfn + new->npages - 1);
269 /* Let implementation do the rest */
270 if (needs_flush)
271 kvm_mips_callbacks->flush_shadow_memslot(kvm, new);
272 spin_unlock(&kvm->mmu_lock);
273 }
274}
275
276static inline void dump_handler(const char *symbol, void *start, void *end)
277{
278 u32 *p;
279
280 pr_debug("LEAF(%s)\n", symbol);
281
282 pr_debug("\t.set push\n");
283 pr_debug("\t.set noreorder\n");
284
285 for (p = start; p < (u32 *)end; ++p)
286 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p);
287
288 pr_debug("\t.set\tpop\n");
289
290 pr_debug("\tEND(%s)\n", symbol);
291}
292
293struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm, unsigned int id)
294{
295 int err, size;
296 void *gebase, *p, *handler, *refill_start, *refill_end;
297 int i;
298
299 struct kvm_vcpu *vcpu = kzalloc(sizeof(struct kvm_vcpu), GFP_KERNEL);
300
301 if (!vcpu) {
302 err = -ENOMEM;
303 goto out;
304 }
305
306 err = kvm_vcpu_init(vcpu, kvm, id);
307
308 if (err)
309 goto out_free_cpu;
310
311 kvm_debug("kvm @ %p: create cpu %d at %p\n", kvm, id, vcpu);
312
313 /*
314 * Allocate space for host mode exception handlers that handle
315 * guest mode exits
316 */
317 if (cpu_has_veic || cpu_has_vint)
318 size = 0x200 + VECTORSPACING * 64;
319 else
320 size = 0x4000;
321
322 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
323
324 if (!gebase) {
325 err = -ENOMEM;
326 goto out_uninit_cpu;
327 }
328 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
329 ALIGN(size, PAGE_SIZE), gebase);
330
331 /*
332 * Check new ebase actually fits in CP0_EBase. The lack of a write gate
333 * limits us to the low 512MB of physical address space. If the memory
334 * we allocate is out of range, just give up now.
335 */
336 if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) {
337 kvm_err("CP0_EBase.WG required for guest exception base %pK\n",
338 gebase);
339 err = -ENOMEM;
340 goto out_free_gebase;
341 }
342
343 /* Save new ebase */
344 vcpu->arch.guest_ebase = gebase;
345
346 /* Build guest exception vectors dynamically in unmapped memory */
347 handler = gebase + 0x2000;
348
349 /* TLB refill (or XTLB refill on 64-bit VZ where KX=1) */
350 refill_start = gebase;
351 if (IS_ENABLED(CONFIG_KVM_MIPS_VZ) && IS_ENABLED(CONFIG_64BIT))
352 refill_start += 0x080;
353 refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler);
354
355 /* General Exception Entry point */
356 kvm_mips_build_exception(gebase + 0x180, handler);
357
358 /* For vectored interrupts poke the exception code @ all offsets 0-7 */
359 for (i = 0; i < 8; i++) {
360 kvm_debug("L1 Vectored handler @ %p\n",
361 gebase + 0x200 + (i * VECTORSPACING));
362 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING,
363 handler);
364 }
365
366 /* General exit handler */
367 p = handler;
368 p = kvm_mips_build_exit(p);
369
370 /* Guest entry routine */
371 vcpu->arch.vcpu_run = p;
372 p = kvm_mips_build_vcpu_run(p);
373
374 /* Dump the generated code */
375 pr_debug("#include <asm/asm.h>\n");
376 pr_debug("#include <asm/regdef.h>\n");
377 pr_debug("\n");
378 dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p);
379 dump_handler("kvm_tlb_refill", refill_start, refill_end);
380 dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200);
381 dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run);
382
383 /* Invalidate the icache for these ranges */
384 flush_icache_range((unsigned long)gebase,
385 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
386
387 /*
388 * Allocate comm page for guest kernel, a TLB will be reserved for
389 * mapping GVA @ 0xFFFF8000 to this page
390 */
391 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
392
393 if (!vcpu->arch.kseg0_commpage) {
394 err = -ENOMEM;
395 goto out_free_gebase;
396 }
397
398 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
399 kvm_mips_commpage_init(vcpu);
400
401 /* Init */
402 vcpu->arch.last_sched_cpu = -1;
403 vcpu->arch.last_exec_cpu = -1;
404
405 return vcpu;
406
407out_free_gebase:
408 kfree(gebase);
409
410out_uninit_cpu:
411 kvm_vcpu_uninit(vcpu);
412
413out_free_cpu:
414 kfree(vcpu);
415
416out:
417 return ERR_PTR(err);
418}
419
420void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
421{
422 hrtimer_cancel(&vcpu->arch.comparecount_timer);
423
424 kvm_vcpu_uninit(vcpu);
425
426 kvm_mips_dump_stats(vcpu);
427
428 kvm_mmu_free_memory_caches(vcpu);
429 kfree(vcpu->arch.guest_ebase);
430 kfree(vcpu->arch.kseg0_commpage);
431 kfree(vcpu);
432}
433
434void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
435{
436 kvm_arch_vcpu_free(vcpu);
437}
438
439int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
440 struct kvm_guest_debug *dbg)
441{
442 return -ENOIOCTLCMD;
443}
444
445int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
446{
447 int r = -EINTR;
448
449 vcpu_load(vcpu);
450
451 kvm_sigset_activate(vcpu);
452
453 if (vcpu->mmio_needed) {
454 if (!vcpu->mmio_is_write)
455 kvm_mips_complete_mmio_load(vcpu, run);
456 vcpu->mmio_needed = 0;
457 }
458
459 if (run->immediate_exit)
460 goto out;
461
462 lose_fpu(1);
463
464 local_irq_disable();
465 guest_enter_irqoff();
466 trace_kvm_enter(vcpu);
467
468 /*
469 * Make sure the read of VCPU requests in vcpu_run() callback is not
470 * reordered ahead of the write to vcpu->mode, or we could miss a TLB
471 * flush request while the requester sees the VCPU as outside of guest
472 * mode and not needing an IPI.
473 */
474 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
475
476 r = kvm_mips_callbacks->vcpu_run(run, vcpu);
477
478 trace_kvm_out(vcpu);
479 guest_exit_irqoff();
480 local_irq_enable();
481
482out:
483 kvm_sigset_deactivate(vcpu);
484
485 vcpu_put(vcpu);
486 return r;
487}
488
489int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
490 struct kvm_mips_interrupt *irq)
491{
492 int intr = (int)irq->irq;
493 struct kvm_vcpu *dvcpu = NULL;
494
495 if (intr == 3 || intr == -3 || intr == 4 || intr == -4)
496 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
497 (int)intr);
498
499 if (irq->cpu == -1)
500 dvcpu = vcpu;
501 else
502 dvcpu = vcpu->kvm->vcpus[irq->cpu];
503
504 if (intr == 2 || intr == 3 || intr == 4) {
505 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
506
507 } else if (intr == -2 || intr == -3 || intr == -4) {
508 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
509 } else {
510 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
511 irq->cpu, irq->irq);
512 return -EINVAL;
513 }
514
515 dvcpu->arch.wait = 0;
516
517 if (swq_has_sleeper(&dvcpu->wq))
518 swake_up(&dvcpu->wq);
519
520 return 0;
521}
522
523int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
524 struct kvm_mp_state *mp_state)
525{
526 return -ENOIOCTLCMD;
527}
528
529int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
530 struct kvm_mp_state *mp_state)
531{
532 return -ENOIOCTLCMD;
533}
534
535static u64 kvm_mips_get_one_regs[] = {
536 KVM_REG_MIPS_R0,
537 KVM_REG_MIPS_R1,
538 KVM_REG_MIPS_R2,
539 KVM_REG_MIPS_R3,
540 KVM_REG_MIPS_R4,
541 KVM_REG_MIPS_R5,
542 KVM_REG_MIPS_R6,
543 KVM_REG_MIPS_R7,
544 KVM_REG_MIPS_R8,
545 KVM_REG_MIPS_R9,
546 KVM_REG_MIPS_R10,
547 KVM_REG_MIPS_R11,
548 KVM_REG_MIPS_R12,
549 KVM_REG_MIPS_R13,
550 KVM_REG_MIPS_R14,
551 KVM_REG_MIPS_R15,
552 KVM_REG_MIPS_R16,
553 KVM_REG_MIPS_R17,
554 KVM_REG_MIPS_R18,
555 KVM_REG_MIPS_R19,
556 KVM_REG_MIPS_R20,
557 KVM_REG_MIPS_R21,
558 KVM_REG_MIPS_R22,
559 KVM_REG_MIPS_R23,
560 KVM_REG_MIPS_R24,
561 KVM_REG_MIPS_R25,
562 KVM_REG_MIPS_R26,
563 KVM_REG_MIPS_R27,
564 KVM_REG_MIPS_R28,
565 KVM_REG_MIPS_R29,
566 KVM_REG_MIPS_R30,
567 KVM_REG_MIPS_R31,
568
569#ifndef CONFIG_CPU_MIPSR6
570 KVM_REG_MIPS_HI,
571 KVM_REG_MIPS_LO,
572#endif
573 KVM_REG_MIPS_PC,
574};
575
576static u64 kvm_mips_get_one_regs_fpu[] = {
577 KVM_REG_MIPS_FCR_IR,
578 KVM_REG_MIPS_FCR_CSR,
579};
580
581static u64 kvm_mips_get_one_regs_msa[] = {
582 KVM_REG_MIPS_MSA_IR,
583 KVM_REG_MIPS_MSA_CSR,
584};
585
586static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
587{
588 unsigned long ret;
589
590 ret = ARRAY_SIZE(kvm_mips_get_one_regs);
591 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
592 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48;
593 /* odd doubles */
594 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64)
595 ret += 16;
596 }
597 if (kvm_mips_guest_can_have_msa(&vcpu->arch))
598 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32;
599 ret += kvm_mips_callbacks->num_regs(vcpu);
600
601 return ret;
602}
603
604static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
605{
606 u64 index;
607 unsigned int i;
608
609 if (copy_to_user(indices, kvm_mips_get_one_regs,
610 sizeof(kvm_mips_get_one_regs)))
611 return -EFAULT;
612 indices += ARRAY_SIZE(kvm_mips_get_one_regs);
613
614 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
615 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu,
616 sizeof(kvm_mips_get_one_regs_fpu)))
617 return -EFAULT;
618 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu);
619
620 for (i = 0; i < 32; ++i) {
621 index = KVM_REG_MIPS_FPR_32(i);
622 if (copy_to_user(indices, &index, sizeof(index)))
623 return -EFAULT;
624 ++indices;
625
626 /* skip odd doubles if no F64 */
627 if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
628 continue;
629
630 index = KVM_REG_MIPS_FPR_64(i);
631 if (copy_to_user(indices, &index, sizeof(index)))
632 return -EFAULT;
633 ++indices;
634 }
635 }
636
637 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) {
638 if (copy_to_user(indices, kvm_mips_get_one_regs_msa,
639 sizeof(kvm_mips_get_one_regs_msa)))
640 return -EFAULT;
641 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa);
642
643 for (i = 0; i < 32; ++i) {
644 index = KVM_REG_MIPS_VEC_128(i);
645 if (copy_to_user(indices, &index, sizeof(index)))
646 return -EFAULT;
647 ++indices;
648 }
649 }
650
651 return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
652}
653
654static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
655 const struct kvm_one_reg *reg)
656{
657 struct mips_coproc *cop0 = vcpu->arch.cop0;
658 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
659 int ret;
660 s64 v;
661 s64 vs[2];
662 unsigned int idx;
663
664 switch (reg->id) {
665 /* General purpose registers */
666 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
667 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
668 break;
669#ifndef CONFIG_CPU_MIPSR6
670 case KVM_REG_MIPS_HI:
671 v = (long)vcpu->arch.hi;
672 break;
673 case KVM_REG_MIPS_LO:
674 v = (long)vcpu->arch.lo;
675 break;
676#endif
677 case KVM_REG_MIPS_PC:
678 v = (long)vcpu->arch.pc;
679 break;
680
681 /* Floating point registers */
682 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
683 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
684 return -EINVAL;
685 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
686 /* Odd singles in top of even double when FR=0 */
687 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
688 v = get_fpr32(&fpu->fpr[idx], 0);
689 else
690 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
691 break;
692 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
693 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
694 return -EINVAL;
695 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
696 /* Can't access odd doubles in FR=0 mode */
697 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
698 return -EINVAL;
699 v = get_fpr64(&fpu->fpr[idx], 0);
700 break;
701 case KVM_REG_MIPS_FCR_IR:
702 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
703 return -EINVAL;
704 v = boot_cpu_data.fpu_id;
705 break;
706 case KVM_REG_MIPS_FCR_CSR:
707 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
708 return -EINVAL;
709 v = fpu->fcr31;
710 break;
711
712 /* MIPS SIMD Architecture (MSA) registers */
713 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
714 if (!kvm_mips_guest_has_msa(&vcpu->arch))
715 return -EINVAL;
716 /* Can't access MSA registers in FR=0 mode */
717 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
718 return -EINVAL;
719 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
720#ifdef CONFIG_CPU_LITTLE_ENDIAN
721 /* least significant byte first */
722 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
723 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
724#else
725 /* most significant byte first */
726 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
727 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
728#endif
729 break;
730 case KVM_REG_MIPS_MSA_IR:
731 if (!kvm_mips_guest_has_msa(&vcpu->arch))
732 return -EINVAL;
733 v = boot_cpu_data.msa_id;
734 break;
735 case KVM_REG_MIPS_MSA_CSR:
736 if (!kvm_mips_guest_has_msa(&vcpu->arch))
737 return -EINVAL;
738 v = fpu->msacsr;
739 break;
740
741 /* registers to be handled specially */
742 default:
743 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
744 if (ret)
745 return ret;
746 break;
747 }
748 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
749 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
750
751 return put_user(v, uaddr64);
752 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
753 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
754 u32 v32 = (u32)v;
755
756 return put_user(v32, uaddr32);
757 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
758 void __user *uaddr = (void __user *)(long)reg->addr;
759
760 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
761 } else {
762 return -EINVAL;
763 }
764}
765
766static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
767 const struct kvm_one_reg *reg)
768{
769 struct mips_coproc *cop0 = vcpu->arch.cop0;
770 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
771 s64 v;
772 s64 vs[2];
773 unsigned int idx;
774
775 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
776 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
777
778 if (get_user(v, uaddr64) != 0)
779 return -EFAULT;
780 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
781 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
782 s32 v32;
783
784 if (get_user(v32, uaddr32) != 0)
785 return -EFAULT;
786 v = (s64)v32;
787 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
788 void __user *uaddr = (void __user *)(long)reg->addr;
789
790 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
791 } else {
792 return -EINVAL;
793 }
794
795 switch (reg->id) {
796 /* General purpose registers */
797 case KVM_REG_MIPS_R0:
798 /* Silently ignore requests to set $0 */
799 break;
800 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
801 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
802 break;
803#ifndef CONFIG_CPU_MIPSR6
804 case KVM_REG_MIPS_HI:
805 vcpu->arch.hi = v;
806 break;
807 case KVM_REG_MIPS_LO:
808 vcpu->arch.lo = v;
809 break;
810#endif
811 case KVM_REG_MIPS_PC:
812 vcpu->arch.pc = v;
813 break;
814
815 /* Floating point registers */
816 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
817 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
818 return -EINVAL;
819 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
820 /* Odd singles in top of even double when FR=0 */
821 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
822 set_fpr32(&fpu->fpr[idx], 0, v);
823 else
824 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
825 break;
826 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
827 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
828 return -EINVAL;
829 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
830 /* Can't access odd doubles in FR=0 mode */
831 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
832 return -EINVAL;
833 set_fpr64(&fpu->fpr[idx], 0, v);
834 break;
835 case KVM_REG_MIPS_FCR_IR:
836 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
837 return -EINVAL;
838 /* Read-only */
839 break;
840 case KVM_REG_MIPS_FCR_CSR:
841 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
842 return -EINVAL;
843 fpu->fcr31 = v;
844 break;
845
846 /* MIPS SIMD Architecture (MSA) registers */
847 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
848 if (!kvm_mips_guest_has_msa(&vcpu->arch))
849 return -EINVAL;
850 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
851#ifdef CONFIG_CPU_LITTLE_ENDIAN
852 /* least significant byte first */
853 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
854 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
855#else
856 /* most significant byte first */
857 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
858 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
859#endif
860 break;
861 case KVM_REG_MIPS_MSA_IR:
862 if (!kvm_mips_guest_has_msa(&vcpu->arch))
863 return -EINVAL;
864 /* Read-only */
865 break;
866 case KVM_REG_MIPS_MSA_CSR:
867 if (!kvm_mips_guest_has_msa(&vcpu->arch))
868 return -EINVAL;
869 fpu->msacsr = v;
870 break;
871
872 /* registers to be handled specially */
873 default:
874 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
875 }
876 return 0;
877}
878
879static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
880 struct kvm_enable_cap *cap)
881{
882 int r = 0;
883
884 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
885 return -EINVAL;
886 if (cap->flags)
887 return -EINVAL;
888 if (cap->args[0])
889 return -EINVAL;
890
891 switch (cap->cap) {
892 case KVM_CAP_MIPS_FPU:
893 vcpu->arch.fpu_enabled = true;
894 break;
895 case KVM_CAP_MIPS_MSA:
896 vcpu->arch.msa_enabled = true;
897 break;
898 default:
899 r = -EINVAL;
900 break;
901 }
902
903 return r;
904}
905
906long kvm_arch_vcpu_async_ioctl(struct file *filp, unsigned int ioctl,
907 unsigned long arg)
908{
909 struct kvm_vcpu *vcpu = filp->private_data;
910 void __user *argp = (void __user *)arg;
911
912 if (ioctl == KVM_INTERRUPT) {
913 struct kvm_mips_interrupt irq;
914
915 if (copy_from_user(&irq, argp, sizeof(irq)))
916 return -EFAULT;
917 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
918 irq.irq);
919
920 return kvm_vcpu_ioctl_interrupt(vcpu, &irq);
921 }
922
923 return -ENOIOCTLCMD;
924}
925
926long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
927 unsigned long arg)
928{
929 struct kvm_vcpu *vcpu = filp->private_data;
930 void __user *argp = (void __user *)arg;
931 long r;
932
933 vcpu_load(vcpu);
934
935 switch (ioctl) {
936 case KVM_SET_ONE_REG:
937 case KVM_GET_ONE_REG: {
938 struct kvm_one_reg reg;
939
940 r = -EFAULT;
941 if (copy_from_user(®, argp, sizeof(reg)))
942 break;
943 if (ioctl == KVM_SET_ONE_REG)
944 r = kvm_mips_set_reg(vcpu, ®);
945 else
946 r = kvm_mips_get_reg(vcpu, ®);
947 break;
948 }
949 case KVM_GET_REG_LIST: {
950 struct kvm_reg_list __user *user_list = argp;
951 struct kvm_reg_list reg_list;
952 unsigned n;
953
954 r = -EFAULT;
955 if (copy_from_user(®_list, user_list, sizeof(reg_list)))
956 break;
957 n = reg_list.n;
958 reg_list.n = kvm_mips_num_regs(vcpu);
959 if (copy_to_user(user_list, ®_list, sizeof(reg_list)))
960 break;
961 r = -E2BIG;
962 if (n < reg_list.n)
963 break;
964 r = kvm_mips_copy_reg_indices(vcpu, user_list->reg);
965 break;
966 }
967 case KVM_ENABLE_CAP: {
968 struct kvm_enable_cap cap;
969
970 r = -EFAULT;
971 if (copy_from_user(&cap, argp, sizeof(cap)))
972 break;
973 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
974 break;
975 }
976 default:
977 r = -ENOIOCTLCMD;
978 }
979
980 vcpu_put(vcpu);
981 return r;
982}
983
984/**
985 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
986 * @kvm: kvm instance
987 * @log: slot id and address to which we copy the log
988 *
989 * Steps 1-4 below provide general overview of dirty page logging. See
990 * kvm_get_dirty_log_protect() function description for additional details.
991 *
992 * We call kvm_get_dirty_log_protect() to handle steps 1-3, upon return we
993 * always flush the TLB (step 4) even if previous step failed and the dirty
994 * bitmap may be corrupt. Regardless of previous outcome the KVM logging API
995 * does not preclude user space subsequent dirty log read. Flushing TLB ensures
996 * writes will be marked dirty for next log read.
997 *
998 * 1. Take a snapshot of the bit and clear it if needed.
999 * 2. Write protect the corresponding page.
1000 * 3. Copy the snapshot to the userspace.
1001 * 4. Flush TLB's if needed.
1002 */
1003int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
1004{
1005 struct kvm_memslots *slots;
1006 struct kvm_memory_slot *memslot;
1007 bool is_dirty = false;
1008 int r;
1009
1010 mutex_lock(&kvm->slots_lock);
1011
1012 r = kvm_get_dirty_log_protect(kvm, log, &is_dirty);
1013
1014 if (is_dirty) {
1015 slots = kvm_memslots(kvm);
1016 memslot = id_to_memslot(slots, log->slot);
1017
1018 /* Let implementation handle TLB/GVA invalidation */
1019 kvm_mips_callbacks->flush_shadow_memslot(kvm, memslot);
1020 }
1021
1022 mutex_unlock(&kvm->slots_lock);
1023 return r;
1024}
1025
1026long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1027{
1028 long r;
1029
1030 switch (ioctl) {
1031 default:
1032 r = -ENOIOCTLCMD;
1033 }
1034
1035 return r;
1036}
1037
1038int kvm_arch_init(void *opaque)
1039{
1040 if (kvm_mips_callbacks) {
1041 kvm_err("kvm: module already exists\n");
1042 return -EEXIST;
1043 }
1044
1045 return kvm_mips_emulation_init(&kvm_mips_callbacks);
1046}
1047
1048void kvm_arch_exit(void)
1049{
1050 kvm_mips_callbacks = NULL;
1051}
1052
1053int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1054 struct kvm_sregs *sregs)
1055{
1056 return -ENOIOCTLCMD;
1057}
1058
1059int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1060 struct kvm_sregs *sregs)
1061{
1062 return -ENOIOCTLCMD;
1063}
1064
1065void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1066{
1067}
1068
1069int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1070{
1071 return -ENOIOCTLCMD;
1072}
1073
1074int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1075{
1076 return -ENOIOCTLCMD;
1077}
1078
1079int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1080{
1081 return VM_FAULT_SIGBUS;
1082}
1083
1084int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1085{
1086 int r;
1087
1088 switch (ext) {
1089 case KVM_CAP_ONE_REG:
1090 case KVM_CAP_ENABLE_CAP:
1091 case KVM_CAP_READONLY_MEM:
1092 case KVM_CAP_SYNC_MMU:
1093 case KVM_CAP_IMMEDIATE_EXIT:
1094 r = 1;
1095 break;
1096 case KVM_CAP_NR_VCPUS:
1097 r = num_online_cpus();
1098 break;
1099 case KVM_CAP_MAX_VCPUS:
1100 r = KVM_MAX_VCPUS;
1101 break;
1102 case KVM_CAP_MIPS_FPU:
1103 /* We don't handle systems with inconsistent cpu_has_fpu */
1104 r = !!raw_cpu_has_fpu;
1105 break;
1106 case KVM_CAP_MIPS_MSA:
1107 /*
1108 * We don't support MSA vector partitioning yet:
1109 * 1) It would require explicit support which can't be tested
1110 * yet due to lack of support in current hardware.
1111 * 2) It extends the state that would need to be saved/restored
1112 * by e.g. QEMU for migration.
1113 *
1114 * When vector partitioning hardware becomes available, support
1115 * could be added by requiring a flag when enabling
1116 * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1117 * to save/restore the appropriate extra state.
1118 */
1119 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1120 break;
1121 default:
1122 r = kvm_mips_callbacks->check_extension(kvm, ext);
1123 break;
1124 }
1125 return r;
1126}
1127
1128int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1129{
1130 return kvm_mips_pending_timer(vcpu) ||
1131 kvm_read_c0_guest_cause(vcpu->arch.cop0) & C_TI;
1132}
1133
1134int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1135{
1136 int i;
1137 struct mips_coproc *cop0;
1138
1139 if (!vcpu)
1140 return -1;
1141
1142 kvm_debug("VCPU Register Dump:\n");
1143 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1144 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1145
1146 for (i = 0; i < 32; i += 4) {
1147 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1148 vcpu->arch.gprs[i],
1149 vcpu->arch.gprs[i + 1],
1150 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1151 }
1152 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1153 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1154
1155 cop0 = vcpu->arch.cop0;
1156 kvm_debug("\tStatus: 0x%08x, Cause: 0x%08x\n",
1157 kvm_read_c0_guest_status(cop0),
1158 kvm_read_c0_guest_cause(cop0));
1159
1160 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1161
1162 return 0;
1163}
1164
1165int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1166{
1167 int i;
1168
1169 vcpu_load(vcpu);
1170
1171 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1172 vcpu->arch.gprs[i] = regs->gpr[i];
1173 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1174 vcpu->arch.hi = regs->hi;
1175 vcpu->arch.lo = regs->lo;
1176 vcpu->arch.pc = regs->pc;
1177
1178 vcpu_put(vcpu);
1179 return 0;
1180}
1181
1182int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1183{
1184 int i;
1185
1186 vcpu_load(vcpu);
1187
1188 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1189 regs->gpr[i] = vcpu->arch.gprs[i];
1190
1191 regs->hi = vcpu->arch.hi;
1192 regs->lo = vcpu->arch.lo;
1193 regs->pc = vcpu->arch.pc;
1194
1195 vcpu_put(vcpu);
1196 return 0;
1197}
1198
1199static void kvm_mips_comparecount_func(unsigned long data)
1200{
1201 struct kvm_vcpu *vcpu = (struct kvm_vcpu *)data;
1202
1203 kvm_mips_callbacks->queue_timer_int(vcpu);
1204
1205 vcpu->arch.wait = 0;
1206 if (swq_has_sleeper(&vcpu->wq))
1207 swake_up(&vcpu->wq);
1208}
1209
1210/* low level hrtimer wake routine */
1211static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
1212{
1213 struct kvm_vcpu *vcpu;
1214
1215 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
1216 kvm_mips_comparecount_func((unsigned long) vcpu);
1217 return kvm_mips_count_timeout(vcpu);
1218}
1219
1220int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
1221{
1222 int err;
1223
1224 err = kvm_mips_callbacks->vcpu_init(vcpu);
1225 if (err)
1226 return err;
1227
1228 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
1229 HRTIMER_MODE_REL);
1230 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
1231 return 0;
1232}
1233
1234void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
1235{
1236 kvm_mips_callbacks->vcpu_uninit(vcpu);
1237}
1238
1239int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1240 struct kvm_translation *tr)
1241{
1242 return 0;
1243}
1244
1245/* Initial guest state */
1246int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
1247{
1248 return kvm_mips_callbacks->vcpu_setup(vcpu);
1249}
1250
1251static void kvm_mips_set_c0_status(void)
1252{
1253 u32 status = read_c0_status();
1254
1255 if (cpu_has_dsp)
1256 status |= (ST0_MX);
1257
1258 write_c0_status(status);
1259 ehb();
1260}
1261
1262/*
1263 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1264 */
1265int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1266{
1267 u32 cause = vcpu->arch.host_cp0_cause;
1268 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1269 u32 __user *opc = (u32 __user *) vcpu->arch.pc;
1270 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1271 enum emulation_result er = EMULATE_DONE;
1272 u32 inst;
1273 int ret = RESUME_GUEST;
1274
1275 vcpu->mode = OUTSIDE_GUEST_MODE;
1276
1277 /* re-enable HTW before enabling interrupts */
1278 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
1279 htw_start();
1280
1281 /* Set a default exit reason */
1282 run->exit_reason = KVM_EXIT_UNKNOWN;
1283 run->ready_for_interrupt_injection = 1;
1284
1285 /*
1286 * Set the appropriate status bits based on host CPU features,
1287 * before we hit the scheduler
1288 */
1289 kvm_mips_set_c0_status();
1290
1291 local_irq_enable();
1292
1293 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1294 cause, opc, run, vcpu);
1295 trace_kvm_exit(vcpu, exccode);
1296
1297 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1298 /*
1299 * Do a privilege check, if in UM most of these exit conditions
1300 * end up causing an exception to be delivered to the Guest
1301 * Kernel
1302 */
1303 er = kvm_mips_check_privilege(cause, opc, run, vcpu);
1304 if (er == EMULATE_PRIV_FAIL) {
1305 goto skip_emul;
1306 } else if (er == EMULATE_FAIL) {
1307 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1308 ret = RESUME_HOST;
1309 goto skip_emul;
1310 }
1311 }
1312
1313 switch (exccode) {
1314 case EXCCODE_INT:
1315 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1316
1317 ++vcpu->stat.int_exits;
1318
1319 if (need_resched())
1320 cond_resched();
1321
1322 ret = RESUME_GUEST;
1323 break;
1324
1325 case EXCCODE_CPU:
1326 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1327
1328 ++vcpu->stat.cop_unusable_exits;
1329 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1330 /* XXXKYMA: Might need to return to user space */
1331 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1332 ret = RESUME_HOST;
1333 break;
1334
1335 case EXCCODE_MOD:
1336 ++vcpu->stat.tlbmod_exits;
1337 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1338 break;
1339
1340 case EXCCODE_TLBS:
1341 kvm_debug("TLB ST fault: cause %#x, status %#x, PC: %p, BadVaddr: %#lx\n",
1342 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1343 badvaddr);
1344
1345 ++vcpu->stat.tlbmiss_st_exits;
1346 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1347 break;
1348
1349 case EXCCODE_TLBL:
1350 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1351 cause, opc, badvaddr);
1352
1353 ++vcpu->stat.tlbmiss_ld_exits;
1354 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1355 break;
1356
1357 case EXCCODE_ADES:
1358 ++vcpu->stat.addrerr_st_exits;
1359 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1360 break;
1361
1362 case EXCCODE_ADEL:
1363 ++vcpu->stat.addrerr_ld_exits;
1364 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1365 break;
1366
1367 case EXCCODE_SYS:
1368 ++vcpu->stat.syscall_exits;
1369 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1370 break;
1371
1372 case EXCCODE_RI:
1373 ++vcpu->stat.resvd_inst_exits;
1374 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1375 break;
1376
1377 case EXCCODE_BP:
1378 ++vcpu->stat.break_inst_exits;
1379 ret = kvm_mips_callbacks->handle_break(vcpu);
1380 break;
1381
1382 case EXCCODE_TR:
1383 ++vcpu->stat.trap_inst_exits;
1384 ret = kvm_mips_callbacks->handle_trap(vcpu);
1385 break;
1386
1387 case EXCCODE_MSAFPE:
1388 ++vcpu->stat.msa_fpe_exits;
1389 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1390 break;
1391
1392 case EXCCODE_FPE:
1393 ++vcpu->stat.fpe_exits;
1394 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1395 break;
1396
1397 case EXCCODE_MSADIS:
1398 ++vcpu->stat.msa_disabled_exits;
1399 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1400 break;
1401
1402 case EXCCODE_GE:
1403 /* defer exit accounting to handler */
1404 ret = kvm_mips_callbacks->handle_guest_exit(vcpu);
1405 break;
1406
1407 default:
1408 if (cause & CAUSEF_BD)
1409 opc += 1;
1410 inst = 0;
1411 kvm_get_badinstr(opc, vcpu, &inst);
1412 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#x\n",
1413 exccode, opc, inst, badvaddr,
1414 kvm_read_c0_guest_status(vcpu->arch.cop0));
1415 kvm_arch_vcpu_dump_regs(vcpu);
1416 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1417 ret = RESUME_HOST;
1418 break;
1419
1420 }
1421
1422skip_emul:
1423 local_irq_disable();
1424
1425 if (ret == RESUME_GUEST)
1426 kvm_vz_acquire_htimer(vcpu);
1427
1428 if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1429 kvm_mips_deliver_interrupts(vcpu, cause);
1430
1431 if (!(ret & RESUME_HOST)) {
1432 /* Only check for signals if not already exiting to userspace */
1433 if (signal_pending(current)) {
1434 run->exit_reason = KVM_EXIT_INTR;
1435 ret = (-EINTR << 2) | RESUME_HOST;
1436 ++vcpu->stat.signal_exits;
1437 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
1438 }
1439 }
1440
1441 if (ret == RESUME_GUEST) {
1442 trace_kvm_reenter(vcpu);
1443
1444 /*
1445 * Make sure the read of VCPU requests in vcpu_reenter()
1446 * callback is not reordered ahead of the write to vcpu->mode,
1447 * or we could miss a TLB flush request while the requester sees
1448 * the VCPU as outside of guest mode and not needing an IPI.
1449 */
1450 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
1451
1452 kvm_mips_callbacks->vcpu_reenter(run, vcpu);
1453
1454 /*
1455 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1456 * is live), restore FCR31 / MSACSR.
1457 *
1458 * This should be before returning to the guest exception
1459 * vector, as it may well cause an [MSA] FP exception if there
1460 * are pending exception bits unmasked. (see
1461 * kvm_mips_csr_die_notifier() for how that is handled).
1462 */
1463 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1464 read_c0_status() & ST0_CU1)
1465 __kvm_restore_fcsr(&vcpu->arch);
1466
1467 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1468 read_c0_config5() & MIPS_CONF5_MSAEN)
1469 __kvm_restore_msacsr(&vcpu->arch);
1470 }
1471
1472 /* Disable HTW before returning to guest or host */
1473 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
1474 htw_stop();
1475
1476 return ret;
1477}
1478
1479/* Enable FPU for guest and restore context */
1480void kvm_own_fpu(struct kvm_vcpu *vcpu)
1481{
1482 struct mips_coproc *cop0 = vcpu->arch.cop0;
1483 unsigned int sr, cfg5;
1484
1485 preempt_disable();
1486
1487 sr = kvm_read_c0_guest_status(cop0);
1488
1489 /*
1490 * If MSA state is already live, it is undefined how it interacts with
1491 * FR=0 FPU state, and we don't want to hit reserved instruction
1492 * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1493 * play it safe and save it first.
1494 *
1495 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1496 * get called when guest CU1 is set, however we can't trust the guest
1497 * not to clobber the status register directly via the commpage.
1498 */
1499 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1500 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1501 kvm_lose_fpu(vcpu);
1502
1503 /*
1504 * Enable FPU for guest
1505 * We set FR and FRE according to guest context
1506 */
1507 change_c0_status(ST0_CU1 | ST0_FR, sr);
1508 if (cpu_has_fre) {
1509 cfg5 = kvm_read_c0_guest_config5(cop0);
1510 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1511 }
1512 enable_fpu_hazard();
1513
1514 /* If guest FPU state not active, restore it now */
1515 if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1516 __kvm_restore_fpu(&vcpu->arch);
1517 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1518 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1519 } else {
1520 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
1521 }
1522
1523 preempt_enable();
1524}
1525
1526#ifdef CONFIG_CPU_HAS_MSA
1527/* Enable MSA for guest and restore context */
1528void kvm_own_msa(struct kvm_vcpu *vcpu)
1529{
1530 struct mips_coproc *cop0 = vcpu->arch.cop0;
1531 unsigned int sr, cfg5;
1532
1533 preempt_disable();
1534
1535 /*
1536 * Enable FPU if enabled in guest, since we're restoring FPU context
1537 * anyway. We set FR and FRE according to guest context.
1538 */
1539 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1540 sr = kvm_read_c0_guest_status(cop0);
1541
1542 /*
1543 * If FR=0 FPU state is already live, it is undefined how it
1544 * interacts with MSA state, so play it safe and save it first.
1545 */
1546 if (!(sr & ST0_FR) &&
1547 (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1548 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
1549 kvm_lose_fpu(vcpu);
1550
1551 change_c0_status(ST0_CU1 | ST0_FR, sr);
1552 if (sr & ST0_CU1 && cpu_has_fre) {
1553 cfg5 = kvm_read_c0_guest_config5(cop0);
1554 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1555 }
1556 }
1557
1558 /* Enable MSA for guest */
1559 set_c0_config5(MIPS_CONF5_MSAEN);
1560 enable_fpu_hazard();
1561
1562 switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1563 case KVM_MIPS_AUX_FPU:
1564 /*
1565 * Guest FPU state already loaded, only restore upper MSA state
1566 */
1567 __kvm_restore_msa_upper(&vcpu->arch);
1568 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1569 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
1570 break;
1571 case 0:
1572 /* Neither FPU or MSA already active, restore full MSA state */
1573 __kvm_restore_msa(&vcpu->arch);
1574 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1575 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1576 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1577 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1578 KVM_TRACE_AUX_FPU_MSA);
1579 break;
1580 default:
1581 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
1582 break;
1583 }
1584
1585 preempt_enable();
1586}
1587#endif
1588
1589/* Drop FPU & MSA without saving it */
1590void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1591{
1592 preempt_disable();
1593 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1594 disable_msa();
1595 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
1596 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
1597 }
1598 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1599 clear_c0_status(ST0_CU1 | ST0_FR);
1600 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
1601 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1602 }
1603 preempt_enable();
1604}
1605
1606/* Save and disable FPU & MSA */
1607void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1608{
1609 /*
1610 * With T&E, FPU & MSA get disabled in root context (hardware) when it
1611 * is disabled in guest context (software), but the register state in
1612 * the hardware may still be in use.
1613 * This is why we explicitly re-enable the hardware before saving.
1614 */
1615
1616 preempt_disable();
1617 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1618 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1619 set_c0_config5(MIPS_CONF5_MSAEN);
1620 enable_fpu_hazard();
1621 }
1622
1623 __kvm_save_msa(&vcpu->arch);
1624 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
1625
1626 /* Disable MSA & FPU */
1627 disable_msa();
1628 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1629 clear_c0_status(ST0_CU1 | ST0_FR);
1630 disable_fpu_hazard();
1631 }
1632 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1633 } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1634 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1635 set_c0_status(ST0_CU1);
1636 enable_fpu_hazard();
1637 }
1638
1639 __kvm_save_fpu(&vcpu->arch);
1640 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1641 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
1642
1643 /* Disable FPU */
1644 clear_c0_status(ST0_CU1 | ST0_FR);
1645 disable_fpu_hazard();
1646 }
1647 preempt_enable();
1648}
1649
1650/*
1651 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1652 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1653 * exception if cause bits are set in the value being written.
1654 */
1655static int kvm_mips_csr_die_notify(struct notifier_block *self,
1656 unsigned long cmd, void *ptr)
1657{
1658 struct die_args *args = (struct die_args *)ptr;
1659 struct pt_regs *regs = args->regs;
1660 unsigned long pc;
1661
1662 /* Only interested in FPE and MSAFPE */
1663 if (cmd != DIE_FP && cmd != DIE_MSAFP)
1664 return NOTIFY_DONE;
1665
1666 /* Return immediately if guest context isn't active */
1667 if (!(current->flags & PF_VCPU))
1668 return NOTIFY_DONE;
1669
1670 /* Should never get here from user mode */
1671 BUG_ON(user_mode(regs));
1672
1673 pc = instruction_pointer(regs);
1674 switch (cmd) {
1675 case DIE_FP:
1676 /* match 2nd instruction in __kvm_restore_fcsr */
1677 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1678 return NOTIFY_DONE;
1679 break;
1680 case DIE_MSAFP:
1681 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1682 if (!cpu_has_msa ||
1683 pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1684 pc > (unsigned long)&__kvm_restore_msacsr + 8)
1685 return NOTIFY_DONE;
1686 break;
1687 }
1688
1689 /* Move PC forward a little and continue executing */
1690 instruction_pointer(regs) += 4;
1691
1692 return NOTIFY_STOP;
1693}
1694
1695static struct notifier_block kvm_mips_csr_die_notifier = {
1696 .notifier_call = kvm_mips_csr_die_notify,
1697};
1698
1699static int __init kvm_mips_init(void)
1700{
1701 int ret;
1702
1703 ret = kvm_mips_entry_setup();
1704 if (ret)
1705 return ret;
1706
1707 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1708
1709 if (ret)
1710 return ret;
1711
1712 register_die_notifier(&kvm_mips_csr_die_notifier);
1713
1714 return 0;
1715}
1716
1717static void __exit kvm_mips_exit(void)
1718{
1719 kvm_exit();
1720
1721 unregister_die_notifier(&kvm_mips_csr_die_notifier);
1722}
1723
1724module_init(kvm_mips_init);
1725module_exit(kvm_mips_exit);
1726
1727EXPORT_TRACEPOINT_SYMBOL(kvm_exit);
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * KVM/MIPS: MIPS specific KVM APIs
7 *
8 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
9 * Authors: Sanjay Lal <sanjayl@kymasys.com>
10 */
11
12#include <linux/bitops.h>
13#include <linux/errno.h>
14#include <linux/err.h>
15#include <linux/kdebug.h>
16#include <linux/module.h>
17#include <linux/uaccess.h>
18#include <linux/vmalloc.h>
19#include <linux/sched/signal.h>
20#include <linux/fs.h>
21#include <linux/memblock.h>
22#include <linux/pgtable.h>
23
24#include <asm/fpu.h>
25#include <asm/page.h>
26#include <asm/cacheflush.h>
27#include <asm/mmu_context.h>
28#include <asm/pgalloc.h>
29
30#include <linux/kvm_host.h>
31
32#include "interrupt.h"
33#include "commpage.h"
34
35#define CREATE_TRACE_POINTS
36#include "trace.h"
37
38#ifndef VECTORSPACING
39#define VECTORSPACING 0x100 /* for EI/VI mode */
40#endif
41
42struct kvm_stats_debugfs_item debugfs_entries[] = {
43 VCPU_STAT("wait", wait_exits),
44 VCPU_STAT("cache", cache_exits),
45 VCPU_STAT("signal", signal_exits),
46 VCPU_STAT("interrupt", int_exits),
47 VCPU_STAT("cop_unusable", cop_unusable_exits),
48 VCPU_STAT("tlbmod", tlbmod_exits),
49 VCPU_STAT("tlbmiss_ld", tlbmiss_ld_exits),
50 VCPU_STAT("tlbmiss_st", tlbmiss_st_exits),
51 VCPU_STAT("addrerr_st", addrerr_st_exits),
52 VCPU_STAT("addrerr_ld", addrerr_ld_exits),
53 VCPU_STAT("syscall", syscall_exits),
54 VCPU_STAT("resvd_inst", resvd_inst_exits),
55 VCPU_STAT("break_inst", break_inst_exits),
56 VCPU_STAT("trap_inst", trap_inst_exits),
57 VCPU_STAT("msa_fpe", msa_fpe_exits),
58 VCPU_STAT("fpe", fpe_exits),
59 VCPU_STAT("msa_disabled", msa_disabled_exits),
60 VCPU_STAT("flush_dcache", flush_dcache_exits),
61#ifdef CONFIG_KVM_MIPS_VZ
62 VCPU_STAT("vz_gpsi", vz_gpsi_exits),
63 VCPU_STAT("vz_gsfc", vz_gsfc_exits),
64 VCPU_STAT("vz_hc", vz_hc_exits),
65 VCPU_STAT("vz_grr", vz_grr_exits),
66 VCPU_STAT("vz_gva", vz_gva_exits),
67 VCPU_STAT("vz_ghfc", vz_ghfc_exits),
68 VCPU_STAT("vz_gpa", vz_gpa_exits),
69 VCPU_STAT("vz_resvd", vz_resvd_exits),
70#ifdef CONFIG_CPU_LOONGSON64
71 VCPU_STAT("vz_cpucfg", vz_cpucfg_exits),
72#endif
73#endif
74 VCPU_STAT("halt_successful_poll", halt_successful_poll),
75 VCPU_STAT("halt_attempted_poll", halt_attempted_poll),
76 VCPU_STAT("halt_poll_invalid", halt_poll_invalid),
77 VCPU_STAT("halt_wakeup", halt_wakeup),
78 VCPU_STAT("halt_poll_success_ns", halt_poll_success_ns),
79 VCPU_STAT("halt_poll_fail_ns", halt_poll_fail_ns),
80 {NULL}
81};
82
83bool kvm_trace_guest_mode_change;
84
85int kvm_guest_mode_change_trace_reg(void)
86{
87 kvm_trace_guest_mode_change = true;
88 return 0;
89}
90
91void kvm_guest_mode_change_trace_unreg(void)
92{
93 kvm_trace_guest_mode_change = false;
94}
95
96/*
97 * XXXKYMA: We are simulatoring a processor that has the WII bit set in
98 * Config7, so we are "runnable" if interrupts are pending
99 */
100int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
101{
102 return !!(vcpu->arch.pending_exceptions);
103}
104
105bool kvm_arch_vcpu_in_kernel(struct kvm_vcpu *vcpu)
106{
107 return false;
108}
109
110int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
111{
112 return 1;
113}
114
115int kvm_arch_hardware_enable(void)
116{
117 return kvm_mips_callbacks->hardware_enable();
118}
119
120void kvm_arch_hardware_disable(void)
121{
122 kvm_mips_callbacks->hardware_disable();
123}
124
125int kvm_arch_hardware_setup(void *opaque)
126{
127 return 0;
128}
129
130int kvm_arch_check_processor_compat(void *opaque)
131{
132 return 0;
133}
134
135extern void kvm_init_loongson_ipi(struct kvm *kvm);
136
137int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
138{
139 switch (type) {
140 case KVM_VM_MIPS_AUTO:
141 break;
142#ifdef CONFIG_KVM_MIPS_VZ
143 case KVM_VM_MIPS_VZ:
144#else
145 case KVM_VM_MIPS_TE:
146#endif
147 break;
148 default:
149 /* Unsupported KVM type */
150 return -EINVAL;
151 };
152
153 /* Allocate page table to map GPA -> RPA */
154 kvm->arch.gpa_mm.pgd = kvm_pgd_alloc();
155 if (!kvm->arch.gpa_mm.pgd)
156 return -ENOMEM;
157
158#ifdef CONFIG_CPU_LOONGSON64
159 kvm_init_loongson_ipi(kvm);
160#endif
161
162 return 0;
163}
164
165void kvm_mips_free_vcpus(struct kvm *kvm)
166{
167 unsigned int i;
168 struct kvm_vcpu *vcpu;
169
170 kvm_for_each_vcpu(i, vcpu, kvm) {
171 kvm_vcpu_destroy(vcpu);
172 }
173
174 mutex_lock(&kvm->lock);
175
176 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
177 kvm->vcpus[i] = NULL;
178
179 atomic_set(&kvm->online_vcpus, 0);
180
181 mutex_unlock(&kvm->lock);
182}
183
184static void kvm_mips_free_gpa_pt(struct kvm *kvm)
185{
186 /* It should always be safe to remove after flushing the whole range */
187 WARN_ON(!kvm_mips_flush_gpa_pt(kvm, 0, ~0));
188 pgd_free(NULL, kvm->arch.gpa_mm.pgd);
189}
190
191void kvm_arch_destroy_vm(struct kvm *kvm)
192{
193 kvm_mips_free_vcpus(kvm);
194 kvm_mips_free_gpa_pt(kvm);
195}
196
197long kvm_arch_dev_ioctl(struct file *filp, unsigned int ioctl,
198 unsigned long arg)
199{
200 return -ENOIOCTLCMD;
201}
202
203void kvm_arch_flush_shadow_all(struct kvm *kvm)
204{
205 /* Flush whole GPA */
206 kvm_mips_flush_gpa_pt(kvm, 0, ~0);
207
208 /* Let implementation do the rest */
209 kvm_mips_callbacks->flush_shadow_all(kvm);
210}
211
212void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
213 struct kvm_memory_slot *slot)
214{
215 /*
216 * The slot has been made invalid (ready for moving or deletion), so we
217 * need to ensure that it can no longer be accessed by any guest VCPUs.
218 */
219
220 spin_lock(&kvm->mmu_lock);
221 /* Flush slot from GPA */
222 kvm_mips_flush_gpa_pt(kvm, slot->base_gfn,
223 slot->base_gfn + slot->npages - 1);
224 /* Let implementation do the rest */
225 kvm_mips_callbacks->flush_shadow_memslot(kvm, slot);
226 spin_unlock(&kvm->mmu_lock);
227}
228
229int kvm_arch_prepare_memory_region(struct kvm *kvm,
230 struct kvm_memory_slot *memslot,
231 const struct kvm_userspace_memory_region *mem,
232 enum kvm_mr_change change)
233{
234 return 0;
235}
236
237void kvm_arch_commit_memory_region(struct kvm *kvm,
238 const struct kvm_userspace_memory_region *mem,
239 struct kvm_memory_slot *old,
240 const struct kvm_memory_slot *new,
241 enum kvm_mr_change change)
242{
243 int needs_flush;
244
245 kvm_debug("%s: kvm: %p slot: %d, GPA: %llx, size: %llx, QVA: %llx\n",
246 __func__, kvm, mem->slot, mem->guest_phys_addr,
247 mem->memory_size, mem->userspace_addr);
248
249 /*
250 * If dirty page logging is enabled, write protect all pages in the slot
251 * ready for dirty logging.
252 *
253 * There is no need to do this in any of the following cases:
254 * CREATE: No dirty mappings will already exist.
255 * MOVE/DELETE: The old mappings will already have been cleaned up by
256 * kvm_arch_flush_shadow_memslot()
257 */
258 if (change == KVM_MR_FLAGS_ONLY &&
259 (!(old->flags & KVM_MEM_LOG_DIRTY_PAGES) &&
260 new->flags & KVM_MEM_LOG_DIRTY_PAGES)) {
261 spin_lock(&kvm->mmu_lock);
262 /* Write protect GPA page table entries */
263 needs_flush = kvm_mips_mkclean_gpa_pt(kvm, new->base_gfn,
264 new->base_gfn + new->npages - 1);
265 /* Let implementation do the rest */
266 if (needs_flush)
267 kvm_mips_callbacks->flush_shadow_memslot(kvm, new);
268 spin_unlock(&kvm->mmu_lock);
269 }
270}
271
272static inline void dump_handler(const char *symbol, void *start, void *end)
273{
274 u32 *p;
275
276 pr_debug("LEAF(%s)\n", symbol);
277
278 pr_debug("\t.set push\n");
279 pr_debug("\t.set noreorder\n");
280
281 for (p = start; p < (u32 *)end; ++p)
282 pr_debug("\t.word\t0x%08x\t\t# %p\n", *p, p);
283
284 pr_debug("\t.set\tpop\n");
285
286 pr_debug("\tEND(%s)\n", symbol);
287}
288
289/* low level hrtimer wake routine */
290static enum hrtimer_restart kvm_mips_comparecount_wakeup(struct hrtimer *timer)
291{
292 struct kvm_vcpu *vcpu;
293
294 vcpu = container_of(timer, struct kvm_vcpu, arch.comparecount_timer);
295
296 kvm_mips_callbacks->queue_timer_int(vcpu);
297
298 vcpu->arch.wait = 0;
299 rcuwait_wake_up(&vcpu->wait);
300
301 return kvm_mips_count_timeout(vcpu);
302}
303
304int kvm_arch_vcpu_precreate(struct kvm *kvm, unsigned int id)
305{
306 return 0;
307}
308
309int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu)
310{
311 int err, size;
312 void *gebase, *p, *handler, *refill_start, *refill_end;
313 int i;
314
315 kvm_debug("kvm @ %p: create cpu %d at %p\n",
316 vcpu->kvm, vcpu->vcpu_id, vcpu);
317
318 err = kvm_mips_callbacks->vcpu_init(vcpu);
319 if (err)
320 return err;
321
322 hrtimer_init(&vcpu->arch.comparecount_timer, CLOCK_MONOTONIC,
323 HRTIMER_MODE_REL);
324 vcpu->arch.comparecount_timer.function = kvm_mips_comparecount_wakeup;
325
326 /*
327 * Allocate space for host mode exception handlers that handle
328 * guest mode exits
329 */
330 if (cpu_has_veic || cpu_has_vint)
331 size = 0x200 + VECTORSPACING * 64;
332 else
333 size = 0x4000;
334
335 gebase = kzalloc(ALIGN(size, PAGE_SIZE), GFP_KERNEL);
336
337 if (!gebase) {
338 err = -ENOMEM;
339 goto out_uninit_vcpu;
340 }
341 kvm_debug("Allocated %d bytes for KVM Exception Handlers @ %p\n",
342 ALIGN(size, PAGE_SIZE), gebase);
343
344 /*
345 * Check new ebase actually fits in CP0_EBase. The lack of a write gate
346 * limits us to the low 512MB of physical address space. If the memory
347 * we allocate is out of range, just give up now.
348 */
349 if (!cpu_has_ebase_wg && virt_to_phys(gebase) >= 0x20000000) {
350 kvm_err("CP0_EBase.WG required for guest exception base %pK\n",
351 gebase);
352 err = -ENOMEM;
353 goto out_free_gebase;
354 }
355
356 /* Save new ebase */
357 vcpu->arch.guest_ebase = gebase;
358
359 /* Build guest exception vectors dynamically in unmapped memory */
360 handler = gebase + 0x2000;
361
362 /* TLB refill (or XTLB refill on 64-bit VZ where KX=1) */
363 refill_start = gebase;
364 if (IS_ENABLED(CONFIG_KVM_MIPS_VZ) && IS_ENABLED(CONFIG_64BIT))
365 refill_start += 0x080;
366 refill_end = kvm_mips_build_tlb_refill_exception(refill_start, handler);
367
368 /* General Exception Entry point */
369 kvm_mips_build_exception(gebase + 0x180, handler);
370
371 /* For vectored interrupts poke the exception code @ all offsets 0-7 */
372 for (i = 0; i < 8; i++) {
373 kvm_debug("L1 Vectored handler @ %p\n",
374 gebase + 0x200 + (i * VECTORSPACING));
375 kvm_mips_build_exception(gebase + 0x200 + i * VECTORSPACING,
376 handler);
377 }
378
379 /* General exit handler */
380 p = handler;
381 p = kvm_mips_build_exit(p);
382
383 /* Guest entry routine */
384 vcpu->arch.vcpu_run = p;
385 p = kvm_mips_build_vcpu_run(p);
386
387 /* Dump the generated code */
388 pr_debug("#include <asm/asm.h>\n");
389 pr_debug("#include <asm/regdef.h>\n");
390 pr_debug("\n");
391 dump_handler("kvm_vcpu_run", vcpu->arch.vcpu_run, p);
392 dump_handler("kvm_tlb_refill", refill_start, refill_end);
393 dump_handler("kvm_gen_exc", gebase + 0x180, gebase + 0x200);
394 dump_handler("kvm_exit", gebase + 0x2000, vcpu->arch.vcpu_run);
395
396 /* Invalidate the icache for these ranges */
397 flush_icache_range((unsigned long)gebase,
398 (unsigned long)gebase + ALIGN(size, PAGE_SIZE));
399
400 /*
401 * Allocate comm page for guest kernel, a TLB will be reserved for
402 * mapping GVA @ 0xFFFF8000 to this page
403 */
404 vcpu->arch.kseg0_commpage = kzalloc(PAGE_SIZE << 1, GFP_KERNEL);
405
406 if (!vcpu->arch.kseg0_commpage) {
407 err = -ENOMEM;
408 goto out_free_gebase;
409 }
410
411 kvm_debug("Allocated COMM page @ %p\n", vcpu->arch.kseg0_commpage);
412 kvm_mips_commpage_init(vcpu);
413
414 /* Init */
415 vcpu->arch.last_sched_cpu = -1;
416 vcpu->arch.last_exec_cpu = -1;
417
418 /* Initial guest state */
419 err = kvm_mips_callbacks->vcpu_setup(vcpu);
420 if (err)
421 goto out_free_commpage;
422
423 return 0;
424
425out_free_commpage:
426 kfree(vcpu->arch.kseg0_commpage);
427out_free_gebase:
428 kfree(gebase);
429out_uninit_vcpu:
430 kvm_mips_callbacks->vcpu_uninit(vcpu);
431 return err;
432}
433
434void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
435{
436 hrtimer_cancel(&vcpu->arch.comparecount_timer);
437
438 kvm_mips_dump_stats(vcpu);
439
440 kvm_mmu_free_memory_caches(vcpu);
441 kfree(vcpu->arch.guest_ebase);
442 kfree(vcpu->arch.kseg0_commpage);
443
444 kvm_mips_callbacks->vcpu_uninit(vcpu);
445}
446
447int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
448 struct kvm_guest_debug *dbg)
449{
450 return -ENOIOCTLCMD;
451}
452
453int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu)
454{
455 int r = -EINTR;
456
457 vcpu_load(vcpu);
458
459 kvm_sigset_activate(vcpu);
460
461 if (vcpu->mmio_needed) {
462 if (!vcpu->mmio_is_write)
463 kvm_mips_complete_mmio_load(vcpu);
464 vcpu->mmio_needed = 0;
465 }
466
467 if (vcpu->run->immediate_exit)
468 goto out;
469
470 lose_fpu(1);
471
472 local_irq_disable();
473 guest_enter_irqoff();
474 trace_kvm_enter(vcpu);
475
476 /*
477 * Make sure the read of VCPU requests in vcpu_run() callback is not
478 * reordered ahead of the write to vcpu->mode, or we could miss a TLB
479 * flush request while the requester sees the VCPU as outside of guest
480 * mode and not needing an IPI.
481 */
482 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
483
484 r = kvm_mips_callbacks->vcpu_run(vcpu);
485
486 trace_kvm_out(vcpu);
487 guest_exit_irqoff();
488 local_irq_enable();
489
490out:
491 kvm_sigset_deactivate(vcpu);
492
493 vcpu_put(vcpu);
494 return r;
495}
496
497int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
498 struct kvm_mips_interrupt *irq)
499{
500 int intr = (int)irq->irq;
501 struct kvm_vcpu *dvcpu = NULL;
502
503 if (intr == kvm_priority_to_irq[MIPS_EXC_INT_IPI_1] ||
504 intr == kvm_priority_to_irq[MIPS_EXC_INT_IPI_2] ||
505 intr == (-kvm_priority_to_irq[MIPS_EXC_INT_IPI_1]) ||
506 intr == (-kvm_priority_to_irq[MIPS_EXC_INT_IPI_2]))
507 kvm_debug("%s: CPU: %d, INTR: %d\n", __func__, irq->cpu,
508 (int)intr);
509
510 if (irq->cpu == -1)
511 dvcpu = vcpu;
512 else
513 dvcpu = vcpu->kvm->vcpus[irq->cpu];
514
515 if (intr == 2 || intr == 3 || intr == 4 || intr == 6) {
516 kvm_mips_callbacks->queue_io_int(dvcpu, irq);
517
518 } else if (intr == -2 || intr == -3 || intr == -4 || intr == -6) {
519 kvm_mips_callbacks->dequeue_io_int(dvcpu, irq);
520 } else {
521 kvm_err("%s: invalid interrupt ioctl (%d:%d)\n", __func__,
522 irq->cpu, irq->irq);
523 return -EINVAL;
524 }
525
526 dvcpu->arch.wait = 0;
527
528 rcuwait_wake_up(&dvcpu->wait);
529
530 return 0;
531}
532
533int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
534 struct kvm_mp_state *mp_state)
535{
536 return -ENOIOCTLCMD;
537}
538
539int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
540 struct kvm_mp_state *mp_state)
541{
542 return -ENOIOCTLCMD;
543}
544
545static u64 kvm_mips_get_one_regs[] = {
546 KVM_REG_MIPS_R0,
547 KVM_REG_MIPS_R1,
548 KVM_REG_MIPS_R2,
549 KVM_REG_MIPS_R3,
550 KVM_REG_MIPS_R4,
551 KVM_REG_MIPS_R5,
552 KVM_REG_MIPS_R6,
553 KVM_REG_MIPS_R7,
554 KVM_REG_MIPS_R8,
555 KVM_REG_MIPS_R9,
556 KVM_REG_MIPS_R10,
557 KVM_REG_MIPS_R11,
558 KVM_REG_MIPS_R12,
559 KVM_REG_MIPS_R13,
560 KVM_REG_MIPS_R14,
561 KVM_REG_MIPS_R15,
562 KVM_REG_MIPS_R16,
563 KVM_REG_MIPS_R17,
564 KVM_REG_MIPS_R18,
565 KVM_REG_MIPS_R19,
566 KVM_REG_MIPS_R20,
567 KVM_REG_MIPS_R21,
568 KVM_REG_MIPS_R22,
569 KVM_REG_MIPS_R23,
570 KVM_REG_MIPS_R24,
571 KVM_REG_MIPS_R25,
572 KVM_REG_MIPS_R26,
573 KVM_REG_MIPS_R27,
574 KVM_REG_MIPS_R28,
575 KVM_REG_MIPS_R29,
576 KVM_REG_MIPS_R30,
577 KVM_REG_MIPS_R31,
578
579#ifndef CONFIG_CPU_MIPSR6
580 KVM_REG_MIPS_HI,
581 KVM_REG_MIPS_LO,
582#endif
583 KVM_REG_MIPS_PC,
584};
585
586static u64 kvm_mips_get_one_regs_fpu[] = {
587 KVM_REG_MIPS_FCR_IR,
588 KVM_REG_MIPS_FCR_CSR,
589};
590
591static u64 kvm_mips_get_one_regs_msa[] = {
592 KVM_REG_MIPS_MSA_IR,
593 KVM_REG_MIPS_MSA_CSR,
594};
595
596static unsigned long kvm_mips_num_regs(struct kvm_vcpu *vcpu)
597{
598 unsigned long ret;
599
600 ret = ARRAY_SIZE(kvm_mips_get_one_regs);
601 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
602 ret += ARRAY_SIZE(kvm_mips_get_one_regs_fpu) + 48;
603 /* odd doubles */
604 if (boot_cpu_data.fpu_id & MIPS_FPIR_F64)
605 ret += 16;
606 }
607 if (kvm_mips_guest_can_have_msa(&vcpu->arch))
608 ret += ARRAY_SIZE(kvm_mips_get_one_regs_msa) + 32;
609 ret += kvm_mips_callbacks->num_regs(vcpu);
610
611 return ret;
612}
613
614static int kvm_mips_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices)
615{
616 u64 index;
617 unsigned int i;
618
619 if (copy_to_user(indices, kvm_mips_get_one_regs,
620 sizeof(kvm_mips_get_one_regs)))
621 return -EFAULT;
622 indices += ARRAY_SIZE(kvm_mips_get_one_regs);
623
624 if (kvm_mips_guest_can_have_fpu(&vcpu->arch)) {
625 if (copy_to_user(indices, kvm_mips_get_one_regs_fpu,
626 sizeof(kvm_mips_get_one_regs_fpu)))
627 return -EFAULT;
628 indices += ARRAY_SIZE(kvm_mips_get_one_regs_fpu);
629
630 for (i = 0; i < 32; ++i) {
631 index = KVM_REG_MIPS_FPR_32(i);
632 if (copy_to_user(indices, &index, sizeof(index)))
633 return -EFAULT;
634 ++indices;
635
636 /* skip odd doubles if no F64 */
637 if (i & 1 && !(boot_cpu_data.fpu_id & MIPS_FPIR_F64))
638 continue;
639
640 index = KVM_REG_MIPS_FPR_64(i);
641 if (copy_to_user(indices, &index, sizeof(index)))
642 return -EFAULT;
643 ++indices;
644 }
645 }
646
647 if (kvm_mips_guest_can_have_msa(&vcpu->arch)) {
648 if (copy_to_user(indices, kvm_mips_get_one_regs_msa,
649 sizeof(kvm_mips_get_one_regs_msa)))
650 return -EFAULT;
651 indices += ARRAY_SIZE(kvm_mips_get_one_regs_msa);
652
653 for (i = 0; i < 32; ++i) {
654 index = KVM_REG_MIPS_VEC_128(i);
655 if (copy_to_user(indices, &index, sizeof(index)))
656 return -EFAULT;
657 ++indices;
658 }
659 }
660
661 return kvm_mips_callbacks->copy_reg_indices(vcpu, indices);
662}
663
664static int kvm_mips_get_reg(struct kvm_vcpu *vcpu,
665 const struct kvm_one_reg *reg)
666{
667 struct mips_coproc *cop0 = vcpu->arch.cop0;
668 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
669 int ret;
670 s64 v;
671 s64 vs[2];
672 unsigned int idx;
673
674 switch (reg->id) {
675 /* General purpose registers */
676 case KVM_REG_MIPS_R0 ... KVM_REG_MIPS_R31:
677 v = (long)vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0];
678 break;
679#ifndef CONFIG_CPU_MIPSR6
680 case KVM_REG_MIPS_HI:
681 v = (long)vcpu->arch.hi;
682 break;
683 case KVM_REG_MIPS_LO:
684 v = (long)vcpu->arch.lo;
685 break;
686#endif
687 case KVM_REG_MIPS_PC:
688 v = (long)vcpu->arch.pc;
689 break;
690
691 /* Floating point registers */
692 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
693 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
694 return -EINVAL;
695 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
696 /* Odd singles in top of even double when FR=0 */
697 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
698 v = get_fpr32(&fpu->fpr[idx], 0);
699 else
700 v = get_fpr32(&fpu->fpr[idx & ~1], idx & 1);
701 break;
702 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
703 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
704 return -EINVAL;
705 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
706 /* Can't access odd doubles in FR=0 mode */
707 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
708 return -EINVAL;
709 v = get_fpr64(&fpu->fpr[idx], 0);
710 break;
711 case KVM_REG_MIPS_FCR_IR:
712 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
713 return -EINVAL;
714 v = boot_cpu_data.fpu_id;
715 break;
716 case KVM_REG_MIPS_FCR_CSR:
717 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
718 return -EINVAL;
719 v = fpu->fcr31;
720 break;
721
722 /* MIPS SIMD Architecture (MSA) registers */
723 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
724 if (!kvm_mips_guest_has_msa(&vcpu->arch))
725 return -EINVAL;
726 /* Can't access MSA registers in FR=0 mode */
727 if (!(kvm_read_c0_guest_status(cop0) & ST0_FR))
728 return -EINVAL;
729 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
730#ifdef CONFIG_CPU_LITTLE_ENDIAN
731 /* least significant byte first */
732 vs[0] = get_fpr64(&fpu->fpr[idx], 0);
733 vs[1] = get_fpr64(&fpu->fpr[idx], 1);
734#else
735 /* most significant byte first */
736 vs[0] = get_fpr64(&fpu->fpr[idx], 1);
737 vs[1] = get_fpr64(&fpu->fpr[idx], 0);
738#endif
739 break;
740 case KVM_REG_MIPS_MSA_IR:
741 if (!kvm_mips_guest_has_msa(&vcpu->arch))
742 return -EINVAL;
743 v = boot_cpu_data.msa_id;
744 break;
745 case KVM_REG_MIPS_MSA_CSR:
746 if (!kvm_mips_guest_has_msa(&vcpu->arch))
747 return -EINVAL;
748 v = fpu->msacsr;
749 break;
750
751 /* registers to be handled specially */
752 default:
753 ret = kvm_mips_callbacks->get_one_reg(vcpu, reg, &v);
754 if (ret)
755 return ret;
756 break;
757 }
758 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
759 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
760
761 return put_user(v, uaddr64);
762 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
763 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
764 u32 v32 = (u32)v;
765
766 return put_user(v32, uaddr32);
767 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
768 void __user *uaddr = (void __user *)(long)reg->addr;
769
770 return copy_to_user(uaddr, vs, 16) ? -EFAULT : 0;
771 } else {
772 return -EINVAL;
773 }
774}
775
776static int kvm_mips_set_reg(struct kvm_vcpu *vcpu,
777 const struct kvm_one_reg *reg)
778{
779 struct mips_coproc *cop0 = vcpu->arch.cop0;
780 struct mips_fpu_struct *fpu = &vcpu->arch.fpu;
781 s64 v;
782 s64 vs[2];
783 unsigned int idx;
784
785 if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U64) {
786 u64 __user *uaddr64 = (u64 __user *)(long)reg->addr;
787
788 if (get_user(v, uaddr64) != 0)
789 return -EFAULT;
790 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U32) {
791 u32 __user *uaddr32 = (u32 __user *)(long)reg->addr;
792 s32 v32;
793
794 if (get_user(v32, uaddr32) != 0)
795 return -EFAULT;
796 v = (s64)v32;
797 } else if ((reg->id & KVM_REG_SIZE_MASK) == KVM_REG_SIZE_U128) {
798 void __user *uaddr = (void __user *)(long)reg->addr;
799
800 return copy_from_user(vs, uaddr, 16) ? -EFAULT : 0;
801 } else {
802 return -EINVAL;
803 }
804
805 switch (reg->id) {
806 /* General purpose registers */
807 case KVM_REG_MIPS_R0:
808 /* Silently ignore requests to set $0 */
809 break;
810 case KVM_REG_MIPS_R1 ... KVM_REG_MIPS_R31:
811 vcpu->arch.gprs[reg->id - KVM_REG_MIPS_R0] = v;
812 break;
813#ifndef CONFIG_CPU_MIPSR6
814 case KVM_REG_MIPS_HI:
815 vcpu->arch.hi = v;
816 break;
817 case KVM_REG_MIPS_LO:
818 vcpu->arch.lo = v;
819 break;
820#endif
821 case KVM_REG_MIPS_PC:
822 vcpu->arch.pc = v;
823 break;
824
825 /* Floating point registers */
826 case KVM_REG_MIPS_FPR_32(0) ... KVM_REG_MIPS_FPR_32(31):
827 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
828 return -EINVAL;
829 idx = reg->id - KVM_REG_MIPS_FPR_32(0);
830 /* Odd singles in top of even double when FR=0 */
831 if (kvm_read_c0_guest_status(cop0) & ST0_FR)
832 set_fpr32(&fpu->fpr[idx], 0, v);
833 else
834 set_fpr32(&fpu->fpr[idx & ~1], idx & 1, v);
835 break;
836 case KVM_REG_MIPS_FPR_64(0) ... KVM_REG_MIPS_FPR_64(31):
837 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
838 return -EINVAL;
839 idx = reg->id - KVM_REG_MIPS_FPR_64(0);
840 /* Can't access odd doubles in FR=0 mode */
841 if (idx & 1 && !(kvm_read_c0_guest_status(cop0) & ST0_FR))
842 return -EINVAL;
843 set_fpr64(&fpu->fpr[idx], 0, v);
844 break;
845 case KVM_REG_MIPS_FCR_IR:
846 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
847 return -EINVAL;
848 /* Read-only */
849 break;
850 case KVM_REG_MIPS_FCR_CSR:
851 if (!kvm_mips_guest_has_fpu(&vcpu->arch))
852 return -EINVAL;
853 fpu->fcr31 = v;
854 break;
855
856 /* MIPS SIMD Architecture (MSA) registers */
857 case KVM_REG_MIPS_VEC_128(0) ... KVM_REG_MIPS_VEC_128(31):
858 if (!kvm_mips_guest_has_msa(&vcpu->arch))
859 return -EINVAL;
860 idx = reg->id - KVM_REG_MIPS_VEC_128(0);
861#ifdef CONFIG_CPU_LITTLE_ENDIAN
862 /* least significant byte first */
863 set_fpr64(&fpu->fpr[idx], 0, vs[0]);
864 set_fpr64(&fpu->fpr[idx], 1, vs[1]);
865#else
866 /* most significant byte first */
867 set_fpr64(&fpu->fpr[idx], 1, vs[0]);
868 set_fpr64(&fpu->fpr[idx], 0, vs[1]);
869#endif
870 break;
871 case KVM_REG_MIPS_MSA_IR:
872 if (!kvm_mips_guest_has_msa(&vcpu->arch))
873 return -EINVAL;
874 /* Read-only */
875 break;
876 case KVM_REG_MIPS_MSA_CSR:
877 if (!kvm_mips_guest_has_msa(&vcpu->arch))
878 return -EINVAL;
879 fpu->msacsr = v;
880 break;
881
882 /* registers to be handled specially */
883 default:
884 return kvm_mips_callbacks->set_one_reg(vcpu, reg, v);
885 }
886 return 0;
887}
888
889static int kvm_vcpu_ioctl_enable_cap(struct kvm_vcpu *vcpu,
890 struct kvm_enable_cap *cap)
891{
892 int r = 0;
893
894 if (!kvm_vm_ioctl_check_extension(vcpu->kvm, cap->cap))
895 return -EINVAL;
896 if (cap->flags)
897 return -EINVAL;
898 if (cap->args[0])
899 return -EINVAL;
900
901 switch (cap->cap) {
902 case KVM_CAP_MIPS_FPU:
903 vcpu->arch.fpu_enabled = true;
904 break;
905 case KVM_CAP_MIPS_MSA:
906 vcpu->arch.msa_enabled = true;
907 break;
908 default:
909 r = -EINVAL;
910 break;
911 }
912
913 return r;
914}
915
916long kvm_arch_vcpu_async_ioctl(struct file *filp, unsigned int ioctl,
917 unsigned long arg)
918{
919 struct kvm_vcpu *vcpu = filp->private_data;
920 void __user *argp = (void __user *)arg;
921
922 if (ioctl == KVM_INTERRUPT) {
923 struct kvm_mips_interrupt irq;
924
925 if (copy_from_user(&irq, argp, sizeof(irq)))
926 return -EFAULT;
927 kvm_debug("[%d] %s: irq: %d\n", vcpu->vcpu_id, __func__,
928 irq.irq);
929
930 return kvm_vcpu_ioctl_interrupt(vcpu, &irq);
931 }
932
933 return -ENOIOCTLCMD;
934}
935
936long kvm_arch_vcpu_ioctl(struct file *filp, unsigned int ioctl,
937 unsigned long arg)
938{
939 struct kvm_vcpu *vcpu = filp->private_data;
940 void __user *argp = (void __user *)arg;
941 long r;
942
943 vcpu_load(vcpu);
944
945 switch (ioctl) {
946 case KVM_SET_ONE_REG:
947 case KVM_GET_ONE_REG: {
948 struct kvm_one_reg reg;
949
950 r = -EFAULT;
951 if (copy_from_user(®, argp, sizeof(reg)))
952 break;
953 if (ioctl == KVM_SET_ONE_REG)
954 r = kvm_mips_set_reg(vcpu, ®);
955 else
956 r = kvm_mips_get_reg(vcpu, ®);
957 break;
958 }
959 case KVM_GET_REG_LIST: {
960 struct kvm_reg_list __user *user_list = argp;
961 struct kvm_reg_list reg_list;
962 unsigned n;
963
964 r = -EFAULT;
965 if (copy_from_user(®_list, user_list, sizeof(reg_list)))
966 break;
967 n = reg_list.n;
968 reg_list.n = kvm_mips_num_regs(vcpu);
969 if (copy_to_user(user_list, ®_list, sizeof(reg_list)))
970 break;
971 r = -E2BIG;
972 if (n < reg_list.n)
973 break;
974 r = kvm_mips_copy_reg_indices(vcpu, user_list->reg);
975 break;
976 }
977 case KVM_ENABLE_CAP: {
978 struct kvm_enable_cap cap;
979
980 r = -EFAULT;
981 if (copy_from_user(&cap, argp, sizeof(cap)))
982 break;
983 r = kvm_vcpu_ioctl_enable_cap(vcpu, &cap);
984 break;
985 }
986 default:
987 r = -ENOIOCTLCMD;
988 }
989
990 vcpu_put(vcpu);
991 return r;
992}
993
994void kvm_arch_sync_dirty_log(struct kvm *kvm, struct kvm_memory_slot *memslot)
995{
996
997}
998
999void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
1000 struct kvm_memory_slot *memslot)
1001{
1002 /* Let implementation handle TLB/GVA invalidation */
1003 kvm_mips_callbacks->flush_shadow_memslot(kvm, memslot);
1004}
1005
1006long kvm_arch_vm_ioctl(struct file *filp, unsigned int ioctl, unsigned long arg)
1007{
1008 long r;
1009
1010 switch (ioctl) {
1011 default:
1012 r = -ENOIOCTLCMD;
1013 }
1014
1015 return r;
1016}
1017
1018int kvm_arch_init(void *opaque)
1019{
1020 if (kvm_mips_callbacks) {
1021 kvm_err("kvm: module already exists\n");
1022 return -EEXIST;
1023 }
1024
1025 return kvm_mips_emulation_init(&kvm_mips_callbacks);
1026}
1027
1028void kvm_arch_exit(void)
1029{
1030 kvm_mips_callbacks = NULL;
1031}
1032
1033int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
1034 struct kvm_sregs *sregs)
1035{
1036 return -ENOIOCTLCMD;
1037}
1038
1039int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
1040 struct kvm_sregs *sregs)
1041{
1042 return -ENOIOCTLCMD;
1043}
1044
1045void kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
1046{
1047}
1048
1049int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1050{
1051 return -ENOIOCTLCMD;
1052}
1053
1054int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
1055{
1056 return -ENOIOCTLCMD;
1057}
1058
1059vm_fault_t kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
1060{
1061 return VM_FAULT_SIGBUS;
1062}
1063
1064int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
1065{
1066 int r;
1067
1068 switch (ext) {
1069 case KVM_CAP_ONE_REG:
1070 case KVM_CAP_ENABLE_CAP:
1071 case KVM_CAP_READONLY_MEM:
1072 case KVM_CAP_SYNC_MMU:
1073 case KVM_CAP_IMMEDIATE_EXIT:
1074 r = 1;
1075 break;
1076 case KVM_CAP_NR_VCPUS:
1077 r = num_online_cpus();
1078 break;
1079 case KVM_CAP_MAX_VCPUS:
1080 r = KVM_MAX_VCPUS;
1081 break;
1082 case KVM_CAP_MAX_VCPU_ID:
1083 r = KVM_MAX_VCPU_ID;
1084 break;
1085 case KVM_CAP_MIPS_FPU:
1086 /* We don't handle systems with inconsistent cpu_has_fpu */
1087 r = !!raw_cpu_has_fpu;
1088 break;
1089 case KVM_CAP_MIPS_MSA:
1090 /*
1091 * We don't support MSA vector partitioning yet:
1092 * 1) It would require explicit support which can't be tested
1093 * yet due to lack of support in current hardware.
1094 * 2) It extends the state that would need to be saved/restored
1095 * by e.g. QEMU for migration.
1096 *
1097 * When vector partitioning hardware becomes available, support
1098 * could be added by requiring a flag when enabling
1099 * KVM_CAP_MIPS_MSA capability to indicate that userland knows
1100 * to save/restore the appropriate extra state.
1101 */
1102 r = cpu_has_msa && !(boot_cpu_data.msa_id & MSA_IR_WRPF);
1103 break;
1104 default:
1105 r = kvm_mips_callbacks->check_extension(kvm, ext);
1106 break;
1107 }
1108 return r;
1109}
1110
1111int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
1112{
1113 return kvm_mips_pending_timer(vcpu) ||
1114 kvm_read_c0_guest_cause(vcpu->arch.cop0) & C_TI;
1115}
1116
1117int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu)
1118{
1119 int i;
1120 struct mips_coproc *cop0;
1121
1122 if (!vcpu)
1123 return -1;
1124
1125 kvm_debug("VCPU Register Dump:\n");
1126 kvm_debug("\tpc = 0x%08lx\n", vcpu->arch.pc);
1127 kvm_debug("\texceptions: %08lx\n", vcpu->arch.pending_exceptions);
1128
1129 for (i = 0; i < 32; i += 4) {
1130 kvm_debug("\tgpr%02d: %08lx %08lx %08lx %08lx\n", i,
1131 vcpu->arch.gprs[i],
1132 vcpu->arch.gprs[i + 1],
1133 vcpu->arch.gprs[i + 2], vcpu->arch.gprs[i + 3]);
1134 }
1135 kvm_debug("\thi: 0x%08lx\n", vcpu->arch.hi);
1136 kvm_debug("\tlo: 0x%08lx\n", vcpu->arch.lo);
1137
1138 cop0 = vcpu->arch.cop0;
1139 kvm_debug("\tStatus: 0x%08x, Cause: 0x%08x\n",
1140 kvm_read_c0_guest_status(cop0),
1141 kvm_read_c0_guest_cause(cop0));
1142
1143 kvm_debug("\tEPC: 0x%08lx\n", kvm_read_c0_guest_epc(cop0));
1144
1145 return 0;
1146}
1147
1148int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1149{
1150 int i;
1151
1152 vcpu_load(vcpu);
1153
1154 for (i = 1; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1155 vcpu->arch.gprs[i] = regs->gpr[i];
1156 vcpu->arch.gprs[0] = 0; /* zero is special, and cannot be set. */
1157 vcpu->arch.hi = regs->hi;
1158 vcpu->arch.lo = regs->lo;
1159 vcpu->arch.pc = regs->pc;
1160
1161 vcpu_put(vcpu);
1162 return 0;
1163}
1164
1165int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
1166{
1167 int i;
1168
1169 vcpu_load(vcpu);
1170
1171 for (i = 0; i < ARRAY_SIZE(vcpu->arch.gprs); i++)
1172 regs->gpr[i] = vcpu->arch.gprs[i];
1173
1174 regs->hi = vcpu->arch.hi;
1175 regs->lo = vcpu->arch.lo;
1176 regs->pc = vcpu->arch.pc;
1177
1178 vcpu_put(vcpu);
1179 return 0;
1180}
1181
1182int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
1183 struct kvm_translation *tr)
1184{
1185 return 0;
1186}
1187
1188static void kvm_mips_set_c0_status(void)
1189{
1190 u32 status = read_c0_status();
1191
1192 if (cpu_has_dsp)
1193 status |= (ST0_MX);
1194
1195 write_c0_status(status);
1196 ehb();
1197}
1198
1199/*
1200 * Return value is in the form (errcode<<2 | RESUME_FLAG_HOST | RESUME_FLAG_NV)
1201 */
1202int kvm_mips_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu)
1203{
1204 u32 cause = vcpu->arch.host_cp0_cause;
1205 u32 exccode = (cause >> CAUSEB_EXCCODE) & 0x1f;
1206 u32 __user *opc = (u32 __user *) vcpu->arch.pc;
1207 unsigned long badvaddr = vcpu->arch.host_cp0_badvaddr;
1208 enum emulation_result er = EMULATE_DONE;
1209 u32 inst;
1210 int ret = RESUME_GUEST;
1211
1212 vcpu->mode = OUTSIDE_GUEST_MODE;
1213
1214 /* re-enable HTW before enabling interrupts */
1215 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
1216 htw_start();
1217
1218 /* Set a default exit reason */
1219 run->exit_reason = KVM_EXIT_UNKNOWN;
1220 run->ready_for_interrupt_injection = 1;
1221
1222 /*
1223 * Set the appropriate status bits based on host CPU features,
1224 * before we hit the scheduler
1225 */
1226 kvm_mips_set_c0_status();
1227
1228 local_irq_enable();
1229
1230 kvm_debug("kvm_mips_handle_exit: cause: %#x, PC: %p, kvm_run: %p, kvm_vcpu: %p\n",
1231 cause, opc, run, vcpu);
1232 trace_kvm_exit(vcpu, exccode);
1233
1234 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1235 /*
1236 * Do a privilege check, if in UM most of these exit conditions
1237 * end up causing an exception to be delivered to the Guest
1238 * Kernel
1239 */
1240 er = kvm_mips_check_privilege(cause, opc, vcpu);
1241 if (er == EMULATE_PRIV_FAIL) {
1242 goto skip_emul;
1243 } else if (er == EMULATE_FAIL) {
1244 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1245 ret = RESUME_HOST;
1246 goto skip_emul;
1247 }
1248 }
1249
1250 switch (exccode) {
1251 case EXCCODE_INT:
1252 kvm_debug("[%d]EXCCODE_INT @ %p\n", vcpu->vcpu_id, opc);
1253
1254 ++vcpu->stat.int_exits;
1255
1256 if (need_resched())
1257 cond_resched();
1258
1259 ret = RESUME_GUEST;
1260 break;
1261
1262 case EXCCODE_CPU:
1263 kvm_debug("EXCCODE_CPU: @ PC: %p\n", opc);
1264
1265 ++vcpu->stat.cop_unusable_exits;
1266 ret = kvm_mips_callbacks->handle_cop_unusable(vcpu);
1267 /* XXXKYMA: Might need to return to user space */
1268 if (run->exit_reason == KVM_EXIT_IRQ_WINDOW_OPEN)
1269 ret = RESUME_HOST;
1270 break;
1271
1272 case EXCCODE_MOD:
1273 ++vcpu->stat.tlbmod_exits;
1274 ret = kvm_mips_callbacks->handle_tlb_mod(vcpu);
1275 break;
1276
1277 case EXCCODE_TLBS:
1278 kvm_debug("TLB ST fault: cause %#x, status %#x, PC: %p, BadVaddr: %#lx\n",
1279 cause, kvm_read_c0_guest_status(vcpu->arch.cop0), opc,
1280 badvaddr);
1281
1282 ++vcpu->stat.tlbmiss_st_exits;
1283 ret = kvm_mips_callbacks->handle_tlb_st_miss(vcpu);
1284 break;
1285
1286 case EXCCODE_TLBL:
1287 kvm_debug("TLB LD fault: cause %#x, PC: %p, BadVaddr: %#lx\n",
1288 cause, opc, badvaddr);
1289
1290 ++vcpu->stat.tlbmiss_ld_exits;
1291 ret = kvm_mips_callbacks->handle_tlb_ld_miss(vcpu);
1292 break;
1293
1294 case EXCCODE_ADES:
1295 ++vcpu->stat.addrerr_st_exits;
1296 ret = kvm_mips_callbacks->handle_addr_err_st(vcpu);
1297 break;
1298
1299 case EXCCODE_ADEL:
1300 ++vcpu->stat.addrerr_ld_exits;
1301 ret = kvm_mips_callbacks->handle_addr_err_ld(vcpu);
1302 break;
1303
1304 case EXCCODE_SYS:
1305 ++vcpu->stat.syscall_exits;
1306 ret = kvm_mips_callbacks->handle_syscall(vcpu);
1307 break;
1308
1309 case EXCCODE_RI:
1310 ++vcpu->stat.resvd_inst_exits;
1311 ret = kvm_mips_callbacks->handle_res_inst(vcpu);
1312 break;
1313
1314 case EXCCODE_BP:
1315 ++vcpu->stat.break_inst_exits;
1316 ret = kvm_mips_callbacks->handle_break(vcpu);
1317 break;
1318
1319 case EXCCODE_TR:
1320 ++vcpu->stat.trap_inst_exits;
1321 ret = kvm_mips_callbacks->handle_trap(vcpu);
1322 break;
1323
1324 case EXCCODE_MSAFPE:
1325 ++vcpu->stat.msa_fpe_exits;
1326 ret = kvm_mips_callbacks->handle_msa_fpe(vcpu);
1327 break;
1328
1329 case EXCCODE_FPE:
1330 ++vcpu->stat.fpe_exits;
1331 ret = kvm_mips_callbacks->handle_fpe(vcpu);
1332 break;
1333
1334 case EXCCODE_MSADIS:
1335 ++vcpu->stat.msa_disabled_exits;
1336 ret = kvm_mips_callbacks->handle_msa_disabled(vcpu);
1337 break;
1338
1339 case EXCCODE_GE:
1340 /* defer exit accounting to handler */
1341 ret = kvm_mips_callbacks->handle_guest_exit(vcpu);
1342 break;
1343
1344 default:
1345 if (cause & CAUSEF_BD)
1346 opc += 1;
1347 inst = 0;
1348 kvm_get_badinstr(opc, vcpu, &inst);
1349 kvm_err("Exception Code: %d, not yet handled, @ PC: %p, inst: 0x%08x BadVaddr: %#lx Status: %#x\n",
1350 exccode, opc, inst, badvaddr,
1351 kvm_read_c0_guest_status(vcpu->arch.cop0));
1352 kvm_arch_vcpu_dump_regs(vcpu);
1353 run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
1354 ret = RESUME_HOST;
1355 break;
1356
1357 }
1358
1359skip_emul:
1360 local_irq_disable();
1361
1362 if (ret == RESUME_GUEST)
1363 kvm_vz_acquire_htimer(vcpu);
1364
1365 if (er == EMULATE_DONE && !(ret & RESUME_HOST))
1366 kvm_mips_deliver_interrupts(vcpu, cause);
1367
1368 if (!(ret & RESUME_HOST)) {
1369 /* Only check for signals if not already exiting to userspace */
1370 if (signal_pending(current)) {
1371 run->exit_reason = KVM_EXIT_INTR;
1372 ret = (-EINTR << 2) | RESUME_HOST;
1373 ++vcpu->stat.signal_exits;
1374 trace_kvm_exit(vcpu, KVM_TRACE_EXIT_SIGNAL);
1375 }
1376 }
1377
1378 if (ret == RESUME_GUEST) {
1379 trace_kvm_reenter(vcpu);
1380
1381 /*
1382 * Make sure the read of VCPU requests in vcpu_reenter()
1383 * callback is not reordered ahead of the write to vcpu->mode,
1384 * or we could miss a TLB flush request while the requester sees
1385 * the VCPU as outside of guest mode and not needing an IPI.
1386 */
1387 smp_store_mb(vcpu->mode, IN_GUEST_MODE);
1388
1389 kvm_mips_callbacks->vcpu_reenter(vcpu);
1390
1391 /*
1392 * If FPU / MSA are enabled (i.e. the guest's FPU / MSA context
1393 * is live), restore FCR31 / MSACSR.
1394 *
1395 * This should be before returning to the guest exception
1396 * vector, as it may well cause an [MSA] FP exception if there
1397 * are pending exception bits unmasked. (see
1398 * kvm_mips_csr_die_notifier() for how that is handled).
1399 */
1400 if (kvm_mips_guest_has_fpu(&vcpu->arch) &&
1401 read_c0_status() & ST0_CU1)
1402 __kvm_restore_fcsr(&vcpu->arch);
1403
1404 if (kvm_mips_guest_has_msa(&vcpu->arch) &&
1405 read_c0_config5() & MIPS_CONF5_MSAEN)
1406 __kvm_restore_msacsr(&vcpu->arch);
1407 }
1408
1409 /* Disable HTW before returning to guest or host */
1410 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ))
1411 htw_stop();
1412
1413 return ret;
1414}
1415
1416/* Enable FPU for guest and restore context */
1417void kvm_own_fpu(struct kvm_vcpu *vcpu)
1418{
1419 struct mips_coproc *cop0 = vcpu->arch.cop0;
1420 unsigned int sr, cfg5;
1421
1422 preempt_disable();
1423
1424 sr = kvm_read_c0_guest_status(cop0);
1425
1426 /*
1427 * If MSA state is already live, it is undefined how it interacts with
1428 * FR=0 FPU state, and we don't want to hit reserved instruction
1429 * exceptions trying to save the MSA state later when CU=1 && FR=1, so
1430 * play it safe and save it first.
1431 *
1432 * In theory we shouldn't ever hit this case since kvm_lose_fpu() should
1433 * get called when guest CU1 is set, however we can't trust the guest
1434 * not to clobber the status register directly via the commpage.
1435 */
1436 if (cpu_has_msa && sr & ST0_CU1 && !(sr & ST0_FR) &&
1437 vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA)
1438 kvm_lose_fpu(vcpu);
1439
1440 /*
1441 * Enable FPU for guest
1442 * We set FR and FRE according to guest context
1443 */
1444 change_c0_status(ST0_CU1 | ST0_FR, sr);
1445 if (cpu_has_fre) {
1446 cfg5 = kvm_read_c0_guest_config5(cop0);
1447 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1448 }
1449 enable_fpu_hazard();
1450
1451 /* If guest FPU state not active, restore it now */
1452 if (!(vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU)) {
1453 __kvm_restore_fpu(&vcpu->arch);
1454 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1455 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_FPU);
1456 } else {
1457 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_FPU);
1458 }
1459
1460 preempt_enable();
1461}
1462
1463#ifdef CONFIG_CPU_HAS_MSA
1464/* Enable MSA for guest and restore context */
1465void kvm_own_msa(struct kvm_vcpu *vcpu)
1466{
1467 struct mips_coproc *cop0 = vcpu->arch.cop0;
1468 unsigned int sr, cfg5;
1469
1470 preempt_disable();
1471
1472 /*
1473 * Enable FPU if enabled in guest, since we're restoring FPU context
1474 * anyway. We set FR and FRE according to guest context.
1475 */
1476 if (kvm_mips_guest_has_fpu(&vcpu->arch)) {
1477 sr = kvm_read_c0_guest_status(cop0);
1478
1479 /*
1480 * If FR=0 FPU state is already live, it is undefined how it
1481 * interacts with MSA state, so play it safe and save it first.
1482 */
1483 if (!(sr & ST0_FR) &&
1484 (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU |
1485 KVM_MIPS_AUX_MSA)) == KVM_MIPS_AUX_FPU)
1486 kvm_lose_fpu(vcpu);
1487
1488 change_c0_status(ST0_CU1 | ST0_FR, sr);
1489 if (sr & ST0_CU1 && cpu_has_fre) {
1490 cfg5 = kvm_read_c0_guest_config5(cop0);
1491 change_c0_config5(MIPS_CONF5_FRE, cfg5);
1492 }
1493 }
1494
1495 /* Enable MSA for guest */
1496 set_c0_config5(MIPS_CONF5_MSAEN);
1497 enable_fpu_hazard();
1498
1499 switch (vcpu->arch.aux_inuse & (KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA)) {
1500 case KVM_MIPS_AUX_FPU:
1501 /*
1502 * Guest FPU state already loaded, only restore upper MSA state
1503 */
1504 __kvm_restore_msa_upper(&vcpu->arch);
1505 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1506 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE, KVM_TRACE_AUX_MSA);
1507 break;
1508 case 0:
1509 /* Neither FPU or MSA already active, restore full MSA state */
1510 __kvm_restore_msa(&vcpu->arch);
1511 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_MSA;
1512 if (kvm_mips_guest_has_fpu(&vcpu->arch))
1513 vcpu->arch.aux_inuse |= KVM_MIPS_AUX_FPU;
1514 trace_kvm_aux(vcpu, KVM_TRACE_AUX_RESTORE,
1515 KVM_TRACE_AUX_FPU_MSA);
1516 break;
1517 default:
1518 trace_kvm_aux(vcpu, KVM_TRACE_AUX_ENABLE, KVM_TRACE_AUX_MSA);
1519 break;
1520 }
1521
1522 preempt_enable();
1523}
1524#endif
1525
1526/* Drop FPU & MSA without saving it */
1527void kvm_drop_fpu(struct kvm_vcpu *vcpu)
1528{
1529 preempt_disable();
1530 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1531 disable_msa();
1532 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_MSA);
1533 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_MSA;
1534 }
1535 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1536 clear_c0_status(ST0_CU1 | ST0_FR);
1537 trace_kvm_aux(vcpu, KVM_TRACE_AUX_DISCARD, KVM_TRACE_AUX_FPU);
1538 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1539 }
1540 preempt_enable();
1541}
1542
1543/* Save and disable FPU & MSA */
1544void kvm_lose_fpu(struct kvm_vcpu *vcpu)
1545{
1546 /*
1547 * With T&E, FPU & MSA get disabled in root context (hardware) when it
1548 * is disabled in guest context (software), but the register state in
1549 * the hardware may still be in use.
1550 * This is why we explicitly re-enable the hardware before saving.
1551 */
1552
1553 preempt_disable();
1554 if (cpu_has_msa && vcpu->arch.aux_inuse & KVM_MIPS_AUX_MSA) {
1555 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1556 set_c0_config5(MIPS_CONF5_MSAEN);
1557 enable_fpu_hazard();
1558 }
1559
1560 __kvm_save_msa(&vcpu->arch);
1561 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU_MSA);
1562
1563 /* Disable MSA & FPU */
1564 disable_msa();
1565 if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1566 clear_c0_status(ST0_CU1 | ST0_FR);
1567 disable_fpu_hazard();
1568 }
1569 vcpu->arch.aux_inuse &= ~(KVM_MIPS_AUX_FPU | KVM_MIPS_AUX_MSA);
1570 } else if (vcpu->arch.aux_inuse & KVM_MIPS_AUX_FPU) {
1571 if (!IS_ENABLED(CONFIG_KVM_MIPS_VZ)) {
1572 set_c0_status(ST0_CU1);
1573 enable_fpu_hazard();
1574 }
1575
1576 __kvm_save_fpu(&vcpu->arch);
1577 vcpu->arch.aux_inuse &= ~KVM_MIPS_AUX_FPU;
1578 trace_kvm_aux(vcpu, KVM_TRACE_AUX_SAVE, KVM_TRACE_AUX_FPU);
1579
1580 /* Disable FPU */
1581 clear_c0_status(ST0_CU1 | ST0_FR);
1582 disable_fpu_hazard();
1583 }
1584 preempt_enable();
1585}
1586
1587/*
1588 * Step over a specific ctc1 to FCSR and a specific ctcmsa to MSACSR which are
1589 * used to restore guest FCSR/MSACSR state and may trigger a "harmless" FP/MSAFP
1590 * exception if cause bits are set in the value being written.
1591 */
1592static int kvm_mips_csr_die_notify(struct notifier_block *self,
1593 unsigned long cmd, void *ptr)
1594{
1595 struct die_args *args = (struct die_args *)ptr;
1596 struct pt_regs *regs = args->regs;
1597 unsigned long pc;
1598
1599 /* Only interested in FPE and MSAFPE */
1600 if (cmd != DIE_FP && cmd != DIE_MSAFP)
1601 return NOTIFY_DONE;
1602
1603 /* Return immediately if guest context isn't active */
1604 if (!(current->flags & PF_VCPU))
1605 return NOTIFY_DONE;
1606
1607 /* Should never get here from user mode */
1608 BUG_ON(user_mode(regs));
1609
1610 pc = instruction_pointer(regs);
1611 switch (cmd) {
1612 case DIE_FP:
1613 /* match 2nd instruction in __kvm_restore_fcsr */
1614 if (pc != (unsigned long)&__kvm_restore_fcsr + 4)
1615 return NOTIFY_DONE;
1616 break;
1617 case DIE_MSAFP:
1618 /* match 2nd/3rd instruction in __kvm_restore_msacsr */
1619 if (!cpu_has_msa ||
1620 pc < (unsigned long)&__kvm_restore_msacsr + 4 ||
1621 pc > (unsigned long)&__kvm_restore_msacsr + 8)
1622 return NOTIFY_DONE;
1623 break;
1624 }
1625
1626 /* Move PC forward a little and continue executing */
1627 instruction_pointer(regs) += 4;
1628
1629 return NOTIFY_STOP;
1630}
1631
1632static struct notifier_block kvm_mips_csr_die_notifier = {
1633 .notifier_call = kvm_mips_csr_die_notify,
1634};
1635
1636static u32 kvm_default_priority_to_irq[MIPS_EXC_MAX] = {
1637 [MIPS_EXC_INT_TIMER] = C_IRQ5,
1638 [MIPS_EXC_INT_IO_1] = C_IRQ0,
1639 [MIPS_EXC_INT_IPI_1] = C_IRQ1,
1640 [MIPS_EXC_INT_IPI_2] = C_IRQ2,
1641};
1642
1643static u32 kvm_loongson3_priority_to_irq[MIPS_EXC_MAX] = {
1644 [MIPS_EXC_INT_TIMER] = C_IRQ5,
1645 [MIPS_EXC_INT_IO_1] = C_IRQ0,
1646 [MIPS_EXC_INT_IO_2] = C_IRQ1,
1647 [MIPS_EXC_INT_IPI_1] = C_IRQ4,
1648};
1649
1650u32 *kvm_priority_to_irq = kvm_default_priority_to_irq;
1651
1652u32 kvm_irq_to_priority(u32 irq)
1653{
1654 int i;
1655
1656 for (i = MIPS_EXC_INT_TIMER; i < MIPS_EXC_MAX; i++) {
1657 if (kvm_priority_to_irq[i] == (1 << (irq + 8)))
1658 return i;
1659 }
1660
1661 return MIPS_EXC_MAX;
1662}
1663
1664static int __init kvm_mips_init(void)
1665{
1666 int ret;
1667
1668 if (cpu_has_mmid) {
1669 pr_warn("KVM does not yet support MMIDs. KVM Disabled\n");
1670 return -EOPNOTSUPP;
1671 }
1672
1673 ret = kvm_mips_entry_setup();
1674 if (ret)
1675 return ret;
1676
1677 ret = kvm_init(NULL, sizeof(struct kvm_vcpu), 0, THIS_MODULE);
1678
1679 if (ret)
1680 return ret;
1681
1682 if (boot_cpu_type() == CPU_LOONGSON64)
1683 kvm_priority_to_irq = kvm_loongson3_priority_to_irq;
1684
1685 register_die_notifier(&kvm_mips_csr_die_notifier);
1686
1687 return 0;
1688}
1689
1690static void __exit kvm_mips_exit(void)
1691{
1692 kvm_exit();
1693
1694 unregister_die_notifier(&kvm_mips_csr_die_notifier);
1695}
1696
1697module_init(kvm_mips_init);
1698module_exit(kvm_mips_exit);
1699
1700EXPORT_TRACEPOINT_SYMBOL(kvm_exit);