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1/*
2 * arch/arm/mach-at91/pm.c
3 * AT91 Power Management
4 *
5 * Copyright (C) 2005 David Brownell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/genalloc.h>
14#include <linux/io.h>
15#include <linux/of_address.h>
16#include <linux/of.h>
17#include <linux/of_platform.h>
18#include <linux/parser.h>
19#include <linux/suspend.h>
20
21#include <linux/clk/at91_pmc.h>
22
23#include <asm/cacheflush.h>
24#include <asm/fncpy.h>
25#include <asm/system_misc.h>
26#include <asm/suspend.h>
27
28#include "generic.h"
29#include "pm.h"
30
31/*
32 * FIXME: this is needed to communicate between the pinctrl driver and
33 * the PM implementation in the machine. Possibly part of the PM
34 * implementation should be moved down into the pinctrl driver and get
35 * called as part of the generic suspend/resume path.
36 */
37#ifdef CONFIG_PINCTRL_AT91
38extern void at91_pinctrl_gpio_suspend(void);
39extern void at91_pinctrl_gpio_resume(void);
40#endif
41
42static const match_table_t pm_modes __initconst = {
43 { 0, "standby" },
44 { AT91_PM_SLOW_CLOCK, "ulp0" },
45 { AT91_PM_BACKUP, "backup" },
46 { -1, NULL },
47};
48
49static struct at91_pm_data pm_data = {
50 .standby_mode = 0,
51 .suspend_mode = AT91_PM_SLOW_CLOCK,
52};
53
54#define at91_ramc_read(id, field) \
55 __raw_readl(pm_data.ramc[id] + field)
56
57#define at91_ramc_write(id, field, value) \
58 __raw_writel(value, pm_data.ramc[id] + field)
59
60static int at91_pm_valid_state(suspend_state_t state)
61{
62 switch (state) {
63 case PM_SUSPEND_ON:
64 case PM_SUSPEND_STANDBY:
65 case PM_SUSPEND_MEM:
66 return 1;
67
68 default:
69 return 0;
70 }
71}
72
73static int canary = 0xA5A5A5A5;
74
75static struct at91_pm_bu {
76 int suspended;
77 unsigned long reserved;
78 phys_addr_t canary;
79 phys_addr_t resume;
80} *pm_bu;
81
82/*
83 * Called after processes are frozen, but before we shutdown devices.
84 */
85static int at91_pm_begin(suspend_state_t state)
86{
87 switch (state) {
88 case PM_SUSPEND_MEM:
89 pm_data.mode = pm_data.suspend_mode;
90 break;
91
92 case PM_SUSPEND_STANDBY:
93 pm_data.mode = pm_data.standby_mode;
94 break;
95
96 default:
97 pm_data.mode = -1;
98 }
99
100 return 0;
101}
102
103/*
104 * Verify that all the clocks are correct before entering
105 * slow-clock mode.
106 */
107static int at91_pm_verify_clocks(void)
108{
109 unsigned long scsr;
110 int i;
111
112 scsr = readl(pm_data.pmc + AT91_PMC_SCSR);
113
114 /* USB must not be using PLLB */
115 if ((scsr & pm_data.uhp_udp_mask) != 0) {
116 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
117 return 0;
118 }
119
120 /* PCK0..PCK3 must be disabled, or configured to use clk32k */
121 for (i = 0; i < 4; i++) {
122 u32 css;
123
124 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
125 continue;
126 css = readl(pm_data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
127 if (css != AT91_PMC_CSS_SLOW) {
128 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
129 return 0;
130 }
131 }
132
133 return 1;
134}
135
136/*
137 * Call this from platform driver suspend() to see how deeply to suspend.
138 * For example, some controllers (like OHCI) need one of the PLL clocks
139 * in order to act as a wakeup source, and those are not available when
140 * going into slow clock mode.
141 *
142 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
143 * the very same problem (but not using at91 main_clk), and it'd be better
144 * to add one generic API rather than lots of platform-specific ones.
145 */
146int at91_suspend_entering_slow_clock(void)
147{
148 return (pm_data.mode >= AT91_PM_SLOW_CLOCK);
149}
150EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
151
152static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
153extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
154extern u32 at91_pm_suspend_in_sram_sz;
155
156static int at91_suspend_finish(unsigned long val)
157{
158 flush_cache_all();
159 outer_disable();
160
161 at91_suspend_sram_fn(&pm_data);
162
163 return 0;
164}
165
166static void at91_pm_suspend(suspend_state_t state)
167{
168 if (pm_data.mode == AT91_PM_BACKUP) {
169 pm_bu->suspended = 1;
170
171 cpu_suspend(0, at91_suspend_finish);
172
173 /* The SRAM is lost between suspend cycles */
174 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
175 &at91_pm_suspend_in_sram,
176 at91_pm_suspend_in_sram_sz);
177 } else {
178 at91_suspend_finish(0);
179 }
180
181 outer_resume();
182}
183
184/*
185 * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup'
186 * event sources; and reduces DRAM power. But otherwise it's identical to
187 * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks.
188 *
189 * AT91_PM_SLOW_CLOCK is like STANDBY plus slow clock mode, so drivers must
190 * suspend more deeply, the master clock switches to the clk32k and turns off
191 * the main oscillator
192 *
193 * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh
194 */
195static int at91_pm_enter(suspend_state_t state)
196{
197#ifdef CONFIG_PINCTRL_AT91
198 at91_pinctrl_gpio_suspend();
199#endif
200
201 switch (state) {
202 case PM_SUSPEND_MEM:
203 case PM_SUSPEND_STANDBY:
204 /*
205 * Ensure that clocks are in a valid state.
206 */
207 if ((pm_data.mode >= AT91_PM_SLOW_CLOCK) &&
208 !at91_pm_verify_clocks())
209 goto error;
210
211 at91_pm_suspend(state);
212
213 break;
214
215 case PM_SUSPEND_ON:
216 cpu_do_idle();
217 break;
218
219 default:
220 pr_debug("AT91: PM - bogus suspend state %d\n", state);
221 goto error;
222 }
223
224error:
225#ifdef CONFIG_PINCTRL_AT91
226 at91_pinctrl_gpio_resume();
227#endif
228 return 0;
229}
230
231/*
232 * Called right prior to thawing processes.
233 */
234static void at91_pm_end(void)
235{
236}
237
238
239static const struct platform_suspend_ops at91_pm_ops = {
240 .valid = at91_pm_valid_state,
241 .begin = at91_pm_begin,
242 .enter = at91_pm_enter,
243 .end = at91_pm_end,
244};
245
246static struct platform_device at91_cpuidle_device = {
247 .name = "cpuidle-at91",
248};
249
250/*
251 * The AT91RM9200 goes into self-refresh mode with this command, and will
252 * terminate self-refresh automatically on the next SDRAM access.
253 *
254 * Self-refresh mode is exited as soon as a memory access is made, but we don't
255 * know for sure when that happens. However, we need to restore the low-power
256 * mode if it was enabled before going idle. Restoring low-power mode while
257 * still in self-refresh is "not recommended", but seems to work.
258 */
259static void at91rm9200_standby(void)
260{
261 asm volatile(
262 "b 1f\n\t"
263 ".align 5\n\t"
264 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
265 " str %2, [%1, %3]\n\t"
266 " mcr p15, 0, %0, c7, c0, 4\n\t"
267 :
268 : "r" (0), "r" (pm_data.ramc[0]),
269 "r" (1), "r" (AT91_MC_SDRAMC_SRR));
270}
271
272/* We manage both DDRAM/SDRAM controllers, we need more than one value to
273 * remember.
274 */
275static void at91_ddr_standby(void)
276{
277 /* Those two values allow us to delay self-refresh activation
278 * to the maximum. */
279 u32 lpr0, lpr1 = 0;
280 u32 mdr, saved_mdr0, saved_mdr1 = 0;
281 u32 saved_lpr0, saved_lpr1 = 0;
282
283 /* LPDDR1 --> force DDR2 mode during self-refresh */
284 saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR);
285 if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
286 mdr = saved_mdr0 & ~AT91_DDRSDRC_MD;
287 mdr |= AT91_DDRSDRC_MD_DDR2;
288 at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
289 }
290
291 if (pm_data.ramc[1]) {
292 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
293 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
294 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
295 saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR);
296 if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
297 mdr = saved_mdr1 & ~AT91_DDRSDRC_MD;
298 mdr |= AT91_DDRSDRC_MD_DDR2;
299 at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr);
300 }
301 }
302
303 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
304 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
305 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
306
307 /* self-refresh mode now */
308 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
309 if (pm_data.ramc[1])
310 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
311
312 cpu_do_idle();
313
314 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0);
315 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
316 if (pm_data.ramc[1]) {
317 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1);
318 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
319 }
320}
321
322static void sama5d3_ddr_standby(void)
323{
324 u32 lpr0;
325 u32 saved_lpr0;
326
327 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
328 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
329 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
330
331 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
332
333 cpu_do_idle();
334
335 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
336}
337
338/* We manage both DDRAM/SDRAM controllers, we need more than one value to
339 * remember.
340 */
341static void at91sam9_sdram_standby(void)
342{
343 u32 lpr0, lpr1 = 0;
344 u32 saved_lpr0, saved_lpr1 = 0;
345
346 if (pm_data.ramc[1]) {
347 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
348 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
349 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
350 }
351
352 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
353 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
354 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
355
356 /* self-refresh mode now */
357 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
358 if (pm_data.ramc[1])
359 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
360
361 cpu_do_idle();
362
363 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
364 if (pm_data.ramc[1])
365 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
366}
367
368struct ramc_info {
369 void (*idle)(void);
370 unsigned int memctrl;
371};
372
373static const struct ramc_info ramc_infos[] __initconst = {
374 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC},
375 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
376 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
377 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
378};
379
380static const struct of_device_id ramc_ids[] __initconst = {
381 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
382 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
383 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
384 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
385 { /*sentinel*/ }
386};
387
388static __init void at91_dt_ramc(void)
389{
390 struct device_node *np;
391 const struct of_device_id *of_id;
392 int idx = 0;
393 void *standby = NULL;
394 const struct ramc_info *ramc;
395
396 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
397 pm_data.ramc[idx] = of_iomap(np, 0);
398 if (!pm_data.ramc[idx])
399 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
400
401 ramc = of_id->data;
402 if (!standby)
403 standby = ramc->idle;
404 pm_data.memctrl = ramc->memctrl;
405
406 idx++;
407 }
408
409 if (!idx)
410 panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
411
412 if (!standby) {
413 pr_warn("ramc no standby function available\n");
414 return;
415 }
416
417 at91_cpuidle_device.dev.platform_data = standby;
418}
419
420static void at91rm9200_idle(void)
421{
422 /*
423 * Disable the processor clock. The processor will be automatically
424 * re-enabled by an interrupt or by a reset.
425 */
426 writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR);
427}
428
429static void at91sam9_idle(void)
430{
431 writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR);
432 cpu_do_idle();
433}
434
435static void __init at91_pm_sram_init(void)
436{
437 struct gen_pool *sram_pool;
438 phys_addr_t sram_pbase;
439 unsigned long sram_base;
440 struct device_node *node;
441 struct platform_device *pdev = NULL;
442
443 for_each_compatible_node(node, NULL, "mmio-sram") {
444 pdev = of_find_device_by_node(node);
445 if (pdev) {
446 of_node_put(node);
447 break;
448 }
449 }
450
451 if (!pdev) {
452 pr_warn("%s: failed to find sram device!\n", __func__);
453 return;
454 }
455
456 sram_pool = gen_pool_get(&pdev->dev, NULL);
457 if (!sram_pool) {
458 pr_warn("%s: sram pool unavailable!\n", __func__);
459 return;
460 }
461
462 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
463 if (!sram_base) {
464 pr_warn("%s: unable to alloc sram!\n", __func__);
465 return;
466 }
467
468 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
469 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
470 at91_pm_suspend_in_sram_sz, false);
471 if (!at91_suspend_sram_fn) {
472 pr_warn("SRAM: Could not map\n");
473 return;
474 }
475
476 /* Copy the pm suspend handler to SRAM */
477 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
478 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
479}
480
481static void __init at91_pm_backup_init(void)
482{
483 struct gen_pool *sram_pool;
484 struct device_node *np;
485 struct platform_device *pdev = NULL;
486
487 if ((pm_data.standby_mode != AT91_PM_BACKUP) &&
488 (pm_data.suspend_mode != AT91_PM_BACKUP))
489 return;
490
491 pm_bu = NULL;
492
493 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-shdwc");
494 if (!np) {
495 pr_warn("%s: failed to find shdwc!\n", __func__);
496 return;
497 }
498
499 pm_data.shdwc = of_iomap(np, 0);
500 of_node_put(np);
501
502 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
503 if (!np) {
504 pr_warn("%s: failed to find sfrbu!\n", __func__);
505 goto sfrbu_fail;
506 }
507
508 pm_data.sfrbu = of_iomap(np, 0);
509 of_node_put(np);
510 pm_bu = NULL;
511
512 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
513 if (!np)
514 goto securam_fail;
515
516 pdev = of_find_device_by_node(np);
517 of_node_put(np);
518 if (!pdev) {
519 pr_warn("%s: failed to find securam device!\n", __func__);
520 goto securam_fail;
521 }
522
523 sram_pool = gen_pool_get(&pdev->dev, NULL);
524 if (!sram_pool) {
525 pr_warn("%s: securam pool unavailable!\n", __func__);
526 goto securam_fail;
527 }
528
529 pm_bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
530 if (!pm_bu) {
531 pr_warn("%s: unable to alloc securam!\n", __func__);
532 goto securam_fail;
533 }
534
535 pm_bu->suspended = 0;
536 pm_bu->canary = __pa_symbol(&canary);
537 pm_bu->resume = __pa_symbol(cpu_resume);
538
539 return;
540
541sfrbu_fail:
542 iounmap(pm_data.shdwc);
543 pm_data.shdwc = NULL;
544securam_fail:
545 iounmap(pm_data.sfrbu);
546 pm_data.sfrbu = NULL;
547
548 if (pm_data.standby_mode == AT91_PM_BACKUP)
549 pm_data.standby_mode = AT91_PM_SLOW_CLOCK;
550 if (pm_data.suspend_mode == AT91_PM_BACKUP)
551 pm_data.suspend_mode = AT91_PM_SLOW_CLOCK;
552}
553
554struct pmc_info {
555 unsigned long uhp_udp_mask;
556};
557
558static const struct pmc_info pmc_infos[] __initconst = {
559 { .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP },
560 { .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP },
561 { .uhp_udp_mask = AT91SAM926x_PMC_UHP },
562};
563
564static const struct of_device_id atmel_pmc_ids[] __initconst = {
565 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] },
566 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] },
567 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] },
568 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] },
569 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] },
570 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
571 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
572 { /* sentinel */ },
573};
574
575static void __init at91_pm_init(void (*pm_idle)(void))
576{
577 struct device_node *pmc_np;
578 const struct of_device_id *of_id;
579 const struct pmc_info *pmc;
580
581 if (at91_cpuidle_device.dev.platform_data)
582 platform_device_register(&at91_cpuidle_device);
583
584 pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id);
585 pm_data.pmc = of_iomap(pmc_np, 0);
586 if (!pm_data.pmc) {
587 pr_err("AT91: PM not supported, PMC not found\n");
588 return;
589 }
590
591 pmc = of_id->data;
592 pm_data.uhp_udp_mask = pmc->uhp_udp_mask;
593
594 if (pm_idle)
595 arm_pm_idle = pm_idle;
596
597 at91_pm_sram_init();
598
599 if (at91_suspend_sram_fn) {
600 suspend_set_ops(&at91_pm_ops);
601 pr_info("AT91: PM: standby: %s, suspend: %s\n",
602 pm_modes[pm_data.standby_mode].pattern,
603 pm_modes[pm_data.suspend_mode].pattern);
604 } else {
605 pr_info("AT91: PM not supported, due to no SRAM allocated\n");
606 }
607}
608
609void __init at91rm9200_pm_init(void)
610{
611 if (!IS_ENABLED(CONFIG_SOC_AT91RM9200))
612 return;
613
614 at91_dt_ramc();
615
616 /*
617 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
618 */
619 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
620
621 at91_pm_init(at91rm9200_idle);
622}
623
624void __init at91sam9_pm_init(void)
625{
626 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
627 return;
628
629 at91_dt_ramc();
630 at91_pm_init(at91sam9_idle);
631}
632
633void __init sama5_pm_init(void)
634{
635 if (!IS_ENABLED(CONFIG_SOC_SAMA5))
636 return;
637
638 at91_dt_ramc();
639 at91_pm_init(NULL);
640}
641
642void __init sama5d2_pm_init(void)
643{
644 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
645 return;
646
647 at91_pm_backup_init();
648 sama5_pm_init();
649}
650
651static int __init at91_pm_modes_select(char *str)
652{
653 char *s;
654 substring_t args[MAX_OPT_ARGS];
655 int standby, suspend;
656
657 if (!str)
658 return 0;
659
660 s = strsep(&str, ",");
661 standby = match_token(s, pm_modes, args);
662 if (standby < 0)
663 return 0;
664
665 suspend = match_token(str, pm_modes, args);
666 if (suspend < 0)
667 return 0;
668
669 pm_data.standby_mode = standby;
670 pm_data.suspend_mode = suspend;
671
672 return 0;
673}
674early_param("atmel.pm_modes", at91_pm_modes_select);
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * arch/arm/mach-at91/pm.c
4 * AT91 Power Management
5 *
6 * Copyright (C) 2005 David Brownell
7 */
8
9#include <linux/genalloc.h>
10#include <linux/io.h>
11#include <linux/of_address.h>
12#include <linux/of.h>
13#include <linux/of_platform.h>
14#include <linux/parser.h>
15#include <linux/suspend.h>
16
17#include <linux/clk/at91_pmc.h>
18#include <linux/platform_data/atmel.h>
19
20#include <asm/cacheflush.h>
21#include <asm/fncpy.h>
22#include <asm/system_misc.h>
23#include <asm/suspend.h>
24
25#include "generic.h"
26#include "pm.h"
27
28/*
29 * FIXME: this is needed to communicate between the pinctrl driver and
30 * the PM implementation in the machine. Possibly part of the PM
31 * implementation should be moved down into the pinctrl driver and get
32 * called as part of the generic suspend/resume path.
33 */
34#ifdef CONFIG_PINCTRL_AT91
35extern void at91_pinctrl_gpio_suspend(void);
36extern void at91_pinctrl_gpio_resume(void);
37#endif
38
39struct at91_soc_pm {
40 int (*config_shdwc_ws)(void __iomem *shdwc, u32 *mode, u32 *polarity);
41 int (*config_pmc_ws)(void __iomem *pmc, u32 mode, u32 polarity);
42 const struct of_device_id *ws_ids;
43 struct at91_pm_data data;
44};
45
46static struct at91_soc_pm soc_pm = {
47 .data = {
48 .standby_mode = AT91_PM_STANDBY,
49 .suspend_mode = AT91_PM_ULP0,
50 },
51};
52
53static const match_table_t pm_modes __initconst = {
54 { AT91_PM_STANDBY, "standby" },
55 { AT91_PM_ULP0, "ulp0" },
56 { AT91_PM_ULP1, "ulp1" },
57 { AT91_PM_BACKUP, "backup" },
58 { -1, NULL },
59};
60
61#define at91_ramc_read(id, field) \
62 __raw_readl(soc_pm.data.ramc[id] + field)
63
64#define at91_ramc_write(id, field, value) \
65 __raw_writel(value, soc_pm.data.ramc[id] + field)
66
67static int at91_pm_valid_state(suspend_state_t state)
68{
69 switch (state) {
70 case PM_SUSPEND_ON:
71 case PM_SUSPEND_STANDBY:
72 case PM_SUSPEND_MEM:
73 return 1;
74
75 default:
76 return 0;
77 }
78}
79
80static int canary = 0xA5A5A5A5;
81
82static struct at91_pm_bu {
83 int suspended;
84 unsigned long reserved;
85 phys_addr_t canary;
86 phys_addr_t resume;
87} *pm_bu;
88
89struct wakeup_source_info {
90 unsigned int pmc_fsmr_bit;
91 unsigned int shdwc_mr_bit;
92 bool set_polarity;
93};
94
95static const struct wakeup_source_info ws_info[] = {
96 { .pmc_fsmr_bit = AT91_PMC_FSTT(10), .set_polarity = true },
97 { .pmc_fsmr_bit = AT91_PMC_RTCAL, .shdwc_mr_bit = BIT(17) },
98 { .pmc_fsmr_bit = AT91_PMC_USBAL },
99 { .pmc_fsmr_bit = AT91_PMC_SDMMC_CD },
100 { .pmc_fsmr_bit = AT91_PMC_RTTAL },
101 { .pmc_fsmr_bit = AT91_PMC_RXLP_MCE },
102};
103
104static const struct of_device_id sama5d2_ws_ids[] = {
105 { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] },
106 { .compatible = "atmel,at91rm9200-rtc", .data = &ws_info[1] },
107 { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] },
108 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
109 { .compatible = "usb-ohci", .data = &ws_info[2] },
110 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
111 { .compatible = "usb-ehci", .data = &ws_info[2] },
112 { .compatible = "atmel,sama5d2-sdhci", .data = &ws_info[3] },
113 { /* sentinel */ }
114};
115
116static const struct of_device_id sam9x60_ws_ids[] = {
117 { .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] },
118 { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
119 { .compatible = "usb-ohci", .data = &ws_info[2] },
120 { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
121 { .compatible = "usb-ehci", .data = &ws_info[2] },
122 { .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] },
123 { .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] },
124 { /* sentinel */ }
125};
126
127static int at91_pm_config_ws(unsigned int pm_mode, bool set)
128{
129 const struct wakeup_source_info *wsi;
130 const struct of_device_id *match;
131 struct platform_device *pdev;
132 struct device_node *np;
133 unsigned int mode = 0, polarity = 0, val = 0;
134
135 if (pm_mode != AT91_PM_ULP1)
136 return 0;
137
138 if (!soc_pm.data.pmc || !soc_pm.data.shdwc || !soc_pm.ws_ids)
139 return -EPERM;
140
141 if (!set) {
142 writel(mode, soc_pm.data.pmc + AT91_PMC_FSMR);
143 return 0;
144 }
145
146 if (soc_pm.config_shdwc_ws)
147 soc_pm.config_shdwc_ws(soc_pm.data.shdwc, &mode, &polarity);
148
149 /* SHDWC.MR */
150 val = readl(soc_pm.data.shdwc + 0x04);
151
152 /* Loop through defined wakeup sources. */
153 for_each_matching_node_and_match(np, soc_pm.ws_ids, &match) {
154 pdev = of_find_device_by_node(np);
155 if (!pdev)
156 continue;
157
158 if (device_may_wakeup(&pdev->dev)) {
159 wsi = match->data;
160
161 /* Check if enabled on SHDWC. */
162 if (wsi->shdwc_mr_bit && !(val & wsi->shdwc_mr_bit))
163 goto put_device;
164
165 mode |= wsi->pmc_fsmr_bit;
166 if (wsi->set_polarity)
167 polarity |= wsi->pmc_fsmr_bit;
168 }
169
170put_device:
171 put_device(&pdev->dev);
172 }
173
174 if (mode) {
175 if (soc_pm.config_pmc_ws)
176 soc_pm.config_pmc_ws(soc_pm.data.pmc, mode, polarity);
177 } else {
178 pr_err("AT91: PM: no ULP1 wakeup sources found!");
179 }
180
181 return mode ? 0 : -EPERM;
182}
183
184static int at91_sama5d2_config_shdwc_ws(void __iomem *shdwc, u32 *mode,
185 u32 *polarity)
186{
187 u32 val;
188
189 /* SHDWC.WUIR */
190 val = readl(shdwc + 0x0c);
191 *mode |= (val & 0x3ff);
192 *polarity |= ((val >> 16) & 0x3ff);
193
194 return 0;
195}
196
197static int at91_sama5d2_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
198{
199 writel(mode, pmc + AT91_PMC_FSMR);
200 writel(polarity, pmc + AT91_PMC_FSPR);
201
202 return 0;
203}
204
205static int at91_sam9x60_config_pmc_ws(void __iomem *pmc, u32 mode, u32 polarity)
206{
207 writel(mode, pmc + AT91_PMC_FSMR);
208
209 return 0;
210}
211
212/*
213 * Called after processes are frozen, but before we shutdown devices.
214 */
215static int at91_pm_begin(suspend_state_t state)
216{
217 switch (state) {
218 case PM_SUSPEND_MEM:
219 soc_pm.data.mode = soc_pm.data.suspend_mode;
220 break;
221
222 case PM_SUSPEND_STANDBY:
223 soc_pm.data.mode = soc_pm.data.standby_mode;
224 break;
225
226 default:
227 soc_pm.data.mode = -1;
228 }
229
230 return at91_pm_config_ws(soc_pm.data.mode, true);
231}
232
233/*
234 * Verify that all the clocks are correct before entering
235 * slow-clock mode.
236 */
237static int at91_pm_verify_clocks(void)
238{
239 unsigned long scsr;
240 int i;
241
242 scsr = readl(soc_pm.data.pmc + AT91_PMC_SCSR);
243
244 /* USB must not be using PLLB */
245 if ((scsr & soc_pm.data.uhp_udp_mask) != 0) {
246 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
247 return 0;
248 }
249
250 /* PCK0..PCK3 must be disabled, or configured to use clk32k */
251 for (i = 0; i < 4; i++) {
252 u32 css;
253
254 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
255 continue;
256 css = readl(soc_pm.data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
257 if (css != AT91_PMC_CSS_SLOW) {
258 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
259 return 0;
260 }
261 }
262
263 return 1;
264}
265
266/*
267 * Call this from platform driver suspend() to see how deeply to suspend.
268 * For example, some controllers (like OHCI) need one of the PLL clocks
269 * in order to act as a wakeup source, and those are not available when
270 * going into slow clock mode.
271 *
272 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
273 * the very same problem (but not using at91 main_clk), and it'd be better
274 * to add one generic API rather than lots of platform-specific ones.
275 */
276int at91_suspend_entering_slow_clock(void)
277{
278 return (soc_pm.data.mode >= AT91_PM_ULP0);
279}
280EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
281
282static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
283extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
284extern u32 at91_pm_suspend_in_sram_sz;
285
286static int at91_suspend_finish(unsigned long val)
287{
288 flush_cache_all();
289 outer_disable();
290
291 at91_suspend_sram_fn(&soc_pm.data);
292
293 return 0;
294}
295
296static void at91_pm_suspend(suspend_state_t state)
297{
298 if (soc_pm.data.mode == AT91_PM_BACKUP) {
299 pm_bu->suspended = 1;
300
301 cpu_suspend(0, at91_suspend_finish);
302
303 /* The SRAM is lost between suspend cycles */
304 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
305 &at91_pm_suspend_in_sram,
306 at91_pm_suspend_in_sram_sz);
307 } else {
308 at91_suspend_finish(0);
309 }
310
311 outer_resume();
312}
313
314/*
315 * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup'
316 * event sources; and reduces DRAM power. But otherwise it's identical to
317 * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks.
318 *
319 * AT91_PM_ULP0 is like STANDBY plus slow clock mode, so drivers must
320 * suspend more deeply, the master clock switches to the clk32k and turns off
321 * the main oscillator
322 *
323 * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh
324 */
325static int at91_pm_enter(suspend_state_t state)
326{
327#ifdef CONFIG_PINCTRL_AT91
328 at91_pinctrl_gpio_suspend();
329#endif
330
331 switch (state) {
332 case PM_SUSPEND_MEM:
333 case PM_SUSPEND_STANDBY:
334 /*
335 * Ensure that clocks are in a valid state.
336 */
337 if (soc_pm.data.mode >= AT91_PM_ULP0 &&
338 !at91_pm_verify_clocks())
339 goto error;
340
341 at91_pm_suspend(state);
342
343 break;
344
345 case PM_SUSPEND_ON:
346 cpu_do_idle();
347 break;
348
349 default:
350 pr_debug("AT91: PM - bogus suspend state %d\n", state);
351 goto error;
352 }
353
354error:
355#ifdef CONFIG_PINCTRL_AT91
356 at91_pinctrl_gpio_resume();
357#endif
358 return 0;
359}
360
361/*
362 * Called right prior to thawing processes.
363 */
364static void at91_pm_end(void)
365{
366 at91_pm_config_ws(soc_pm.data.mode, false);
367}
368
369
370static const struct platform_suspend_ops at91_pm_ops = {
371 .valid = at91_pm_valid_state,
372 .begin = at91_pm_begin,
373 .enter = at91_pm_enter,
374 .end = at91_pm_end,
375};
376
377static struct platform_device at91_cpuidle_device = {
378 .name = "cpuidle-at91",
379};
380
381/*
382 * The AT91RM9200 goes into self-refresh mode with this command, and will
383 * terminate self-refresh automatically on the next SDRAM access.
384 *
385 * Self-refresh mode is exited as soon as a memory access is made, but we don't
386 * know for sure when that happens. However, we need to restore the low-power
387 * mode if it was enabled before going idle. Restoring low-power mode while
388 * still in self-refresh is "not recommended", but seems to work.
389 */
390static void at91rm9200_standby(void)
391{
392 asm volatile(
393 "b 1f\n\t"
394 ".align 5\n\t"
395 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
396 " str %2, [%1, %3]\n\t"
397 " mcr p15, 0, %0, c7, c0, 4\n\t"
398 :
399 : "r" (0), "r" (soc_pm.data.ramc[0]),
400 "r" (1), "r" (AT91_MC_SDRAMC_SRR));
401}
402
403/* We manage both DDRAM/SDRAM controllers, we need more than one value to
404 * remember.
405 */
406static void at91_ddr_standby(void)
407{
408 /* Those two values allow us to delay self-refresh activation
409 * to the maximum. */
410 u32 lpr0, lpr1 = 0;
411 u32 mdr, saved_mdr0, saved_mdr1 = 0;
412 u32 saved_lpr0, saved_lpr1 = 0;
413
414 /* LPDDR1 --> force DDR2 mode during self-refresh */
415 saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR);
416 if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
417 mdr = saved_mdr0 & ~AT91_DDRSDRC_MD;
418 mdr |= AT91_DDRSDRC_MD_DDR2;
419 at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
420 }
421
422 if (soc_pm.data.ramc[1]) {
423 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
424 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
425 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
426 saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR);
427 if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
428 mdr = saved_mdr1 & ~AT91_DDRSDRC_MD;
429 mdr |= AT91_DDRSDRC_MD_DDR2;
430 at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr);
431 }
432 }
433
434 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
435 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
436 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
437
438 /* self-refresh mode now */
439 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
440 if (soc_pm.data.ramc[1])
441 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
442
443 cpu_do_idle();
444
445 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0);
446 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
447 if (soc_pm.data.ramc[1]) {
448 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1);
449 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
450 }
451}
452
453static void sama5d3_ddr_standby(void)
454{
455 u32 lpr0;
456 u32 saved_lpr0;
457
458 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
459 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
460 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
461
462 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
463
464 cpu_do_idle();
465
466 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
467}
468
469/* We manage both DDRAM/SDRAM controllers, we need more than one value to
470 * remember.
471 */
472static void at91sam9_sdram_standby(void)
473{
474 u32 lpr0, lpr1 = 0;
475 u32 saved_lpr0, saved_lpr1 = 0;
476
477 if (soc_pm.data.ramc[1]) {
478 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
479 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
480 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
481 }
482
483 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
484 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
485 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
486
487 /* self-refresh mode now */
488 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
489 if (soc_pm.data.ramc[1])
490 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
491
492 cpu_do_idle();
493
494 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
495 if (soc_pm.data.ramc[1])
496 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
497}
498
499struct ramc_info {
500 void (*idle)(void);
501 unsigned int memctrl;
502};
503
504static const struct ramc_info ramc_infos[] __initconst = {
505 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC},
506 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
507 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
508 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
509};
510
511static const struct of_device_id ramc_ids[] __initconst = {
512 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
513 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
514 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
515 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
516 { /*sentinel*/ }
517};
518
519static __init void at91_dt_ramc(void)
520{
521 struct device_node *np;
522 const struct of_device_id *of_id;
523 int idx = 0;
524 void *standby = NULL;
525 const struct ramc_info *ramc;
526
527 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
528 soc_pm.data.ramc[idx] = of_iomap(np, 0);
529 if (!soc_pm.data.ramc[idx])
530 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
531
532 ramc = of_id->data;
533 if (!standby)
534 standby = ramc->idle;
535 soc_pm.data.memctrl = ramc->memctrl;
536
537 idx++;
538 }
539
540 if (!idx)
541 panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
542
543 if (!standby) {
544 pr_warn("ramc no standby function available\n");
545 return;
546 }
547
548 at91_cpuidle_device.dev.platform_data = standby;
549}
550
551static void at91rm9200_idle(void)
552{
553 /*
554 * Disable the processor clock. The processor will be automatically
555 * re-enabled by an interrupt or by a reset.
556 */
557 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
558}
559
560static void at91sam9x60_idle(void)
561{
562 cpu_do_idle();
563}
564
565static void at91sam9_idle(void)
566{
567 writel(AT91_PMC_PCK, soc_pm.data.pmc + AT91_PMC_SCDR);
568 cpu_do_idle();
569}
570
571static void __init at91_pm_sram_init(void)
572{
573 struct gen_pool *sram_pool;
574 phys_addr_t sram_pbase;
575 unsigned long sram_base;
576 struct device_node *node;
577 struct platform_device *pdev = NULL;
578
579 for_each_compatible_node(node, NULL, "mmio-sram") {
580 pdev = of_find_device_by_node(node);
581 if (pdev) {
582 of_node_put(node);
583 break;
584 }
585 }
586
587 if (!pdev) {
588 pr_warn("%s: failed to find sram device!\n", __func__);
589 return;
590 }
591
592 sram_pool = gen_pool_get(&pdev->dev, NULL);
593 if (!sram_pool) {
594 pr_warn("%s: sram pool unavailable!\n", __func__);
595 goto out_put_device;
596 }
597
598 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
599 if (!sram_base) {
600 pr_warn("%s: unable to alloc sram!\n", __func__);
601 goto out_put_device;
602 }
603
604 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
605 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
606 at91_pm_suspend_in_sram_sz, false);
607 if (!at91_suspend_sram_fn) {
608 pr_warn("SRAM: Could not map\n");
609 goto out_put_device;
610 }
611
612 /* Copy the pm suspend handler to SRAM */
613 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
614 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
615 return;
616
617out_put_device:
618 put_device(&pdev->dev);
619 return;
620}
621
622static bool __init at91_is_pm_mode_active(int pm_mode)
623{
624 return (soc_pm.data.standby_mode == pm_mode ||
625 soc_pm.data.suspend_mode == pm_mode);
626}
627
628static int __init at91_pm_backup_init(void)
629{
630 struct gen_pool *sram_pool;
631 struct device_node *np;
632 struct platform_device *pdev = NULL;
633 int ret = -ENODEV;
634
635 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
636 return -EPERM;
637
638 if (!at91_is_pm_mode_active(AT91_PM_BACKUP))
639 return 0;
640
641 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
642 if (!np) {
643 pr_warn("%s: failed to find sfrbu!\n", __func__);
644 return ret;
645 }
646
647 soc_pm.data.sfrbu = of_iomap(np, 0);
648 of_node_put(np);
649
650 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
651 if (!np)
652 goto securam_fail_no_ref_dev;
653
654 pdev = of_find_device_by_node(np);
655 of_node_put(np);
656 if (!pdev) {
657 pr_warn("%s: failed to find securam device!\n", __func__);
658 goto securam_fail_no_ref_dev;
659 }
660
661 sram_pool = gen_pool_get(&pdev->dev, NULL);
662 if (!sram_pool) {
663 pr_warn("%s: securam pool unavailable!\n", __func__);
664 goto securam_fail;
665 }
666
667 pm_bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
668 if (!pm_bu) {
669 pr_warn("%s: unable to alloc securam!\n", __func__);
670 ret = -ENOMEM;
671 goto securam_fail;
672 }
673
674 pm_bu->suspended = 0;
675 pm_bu->canary = __pa_symbol(&canary);
676 pm_bu->resume = __pa_symbol(cpu_resume);
677
678 return 0;
679
680securam_fail:
681 put_device(&pdev->dev);
682securam_fail_no_ref_dev:
683 iounmap(soc_pm.data.sfrbu);
684 soc_pm.data.sfrbu = NULL;
685 return ret;
686}
687
688static void __init at91_pm_use_default_mode(int pm_mode)
689{
690 if (pm_mode != AT91_PM_ULP1 && pm_mode != AT91_PM_BACKUP)
691 return;
692
693 if (soc_pm.data.standby_mode == pm_mode)
694 soc_pm.data.standby_mode = AT91_PM_ULP0;
695 if (soc_pm.data.suspend_mode == pm_mode)
696 soc_pm.data.suspend_mode = AT91_PM_ULP0;
697}
698
699static const struct of_device_id atmel_shdwc_ids[] = {
700 { .compatible = "atmel,sama5d2-shdwc" },
701 { .compatible = "microchip,sam9x60-shdwc" },
702 { /* sentinel. */ }
703};
704
705static void __init at91_pm_modes_init(void)
706{
707 struct device_node *np;
708 int ret;
709
710 if (!at91_is_pm_mode_active(AT91_PM_BACKUP) &&
711 !at91_is_pm_mode_active(AT91_PM_ULP1))
712 return;
713
714 np = of_find_matching_node(NULL, atmel_shdwc_ids);
715 if (!np) {
716 pr_warn("%s: failed to find shdwc!\n", __func__);
717 goto ulp1_default;
718 }
719
720 soc_pm.data.shdwc = of_iomap(np, 0);
721 of_node_put(np);
722
723 ret = at91_pm_backup_init();
724 if (ret) {
725 if (!at91_is_pm_mode_active(AT91_PM_ULP1))
726 goto unmap;
727 else
728 goto backup_default;
729 }
730
731 return;
732
733unmap:
734 iounmap(soc_pm.data.shdwc);
735 soc_pm.data.shdwc = NULL;
736ulp1_default:
737 at91_pm_use_default_mode(AT91_PM_ULP1);
738backup_default:
739 at91_pm_use_default_mode(AT91_PM_BACKUP);
740}
741
742struct pmc_info {
743 unsigned long uhp_udp_mask;
744 unsigned long mckr;
745 unsigned long version;
746};
747
748static const struct pmc_info pmc_infos[] __initconst = {
749 {
750 .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP,
751 .mckr = 0x30,
752 .version = AT91_PMC_V1,
753 },
754
755 {
756 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
757 .mckr = 0x30,
758 .version = AT91_PMC_V1,
759 },
760 {
761 .uhp_udp_mask = AT91SAM926x_PMC_UHP,
762 .mckr = 0x30,
763 .version = AT91_PMC_V1,
764 },
765 { .uhp_udp_mask = 0,
766 .mckr = 0x30,
767 .version = AT91_PMC_V1,
768 },
769 {
770 .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP,
771 .mckr = 0x28,
772 .version = AT91_PMC_V2,
773 },
774};
775
776static const struct of_device_id atmel_pmc_ids[] __initconst = {
777 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] },
778 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] },
779 { .compatible = "atmel,at91sam9261-pmc", .data = &pmc_infos[1] },
780 { .compatible = "atmel,at91sam9263-pmc", .data = &pmc_infos[1] },
781 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] },
782 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] },
783 { .compatible = "atmel,at91sam9rl-pmc", .data = &pmc_infos[3] },
784 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] },
785 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
786 { .compatible = "atmel,sama5d4-pmc", .data = &pmc_infos[1] },
787 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
788 { .compatible = "microchip,sam9x60-pmc", .data = &pmc_infos[4] },
789 { /* sentinel */ },
790};
791
792static void __init at91_pm_init(void (*pm_idle)(void))
793{
794 struct device_node *pmc_np;
795 const struct of_device_id *of_id;
796 const struct pmc_info *pmc;
797
798 if (at91_cpuidle_device.dev.platform_data)
799 platform_device_register(&at91_cpuidle_device);
800
801 pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id);
802 soc_pm.data.pmc = of_iomap(pmc_np, 0);
803 if (!soc_pm.data.pmc) {
804 pr_err("AT91: PM not supported, PMC not found\n");
805 return;
806 }
807
808 pmc = of_id->data;
809 soc_pm.data.uhp_udp_mask = pmc->uhp_udp_mask;
810 soc_pm.data.pmc_mckr_offset = pmc->mckr;
811 soc_pm.data.pmc_version = pmc->version;
812
813 if (pm_idle)
814 arm_pm_idle = pm_idle;
815
816 at91_pm_sram_init();
817
818 if (at91_suspend_sram_fn) {
819 suspend_set_ops(&at91_pm_ops);
820 pr_info("AT91: PM: standby: %s, suspend: %s\n",
821 pm_modes[soc_pm.data.standby_mode].pattern,
822 pm_modes[soc_pm.data.suspend_mode].pattern);
823 } else {
824 pr_info("AT91: PM not supported, due to no SRAM allocated\n");
825 }
826}
827
828void __init at91rm9200_pm_init(void)
829{
830 if (!IS_ENABLED(CONFIG_SOC_AT91RM9200))
831 return;
832
833 at91_dt_ramc();
834
835 /*
836 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
837 */
838 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
839
840 at91_pm_init(at91rm9200_idle);
841}
842
843void __init sam9x60_pm_init(void)
844{
845 if (!IS_ENABLED(CONFIG_SOC_SAM9X60))
846 return;
847
848 at91_pm_modes_init();
849 at91_dt_ramc();
850 at91_pm_init(at91sam9x60_idle);
851
852 soc_pm.ws_ids = sam9x60_ws_ids;
853 soc_pm.config_pmc_ws = at91_sam9x60_config_pmc_ws;
854}
855
856void __init at91sam9_pm_init(void)
857{
858 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
859 return;
860
861 at91_dt_ramc();
862 at91_pm_init(at91sam9_idle);
863}
864
865void __init sama5_pm_init(void)
866{
867 if (!IS_ENABLED(CONFIG_SOC_SAMA5))
868 return;
869
870 at91_dt_ramc();
871 at91_pm_init(NULL);
872}
873
874void __init sama5d2_pm_init(void)
875{
876 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
877 return;
878
879 at91_pm_modes_init();
880 sama5_pm_init();
881
882 soc_pm.ws_ids = sama5d2_ws_ids;
883 soc_pm.config_shdwc_ws = at91_sama5d2_config_shdwc_ws;
884 soc_pm.config_pmc_ws = at91_sama5d2_config_pmc_ws;
885}
886
887static int __init at91_pm_modes_select(char *str)
888{
889 char *s;
890 substring_t args[MAX_OPT_ARGS];
891 int standby, suspend;
892
893 if (!str)
894 return 0;
895
896 s = strsep(&str, ",");
897 standby = match_token(s, pm_modes, args);
898 if (standby < 0)
899 return 0;
900
901 suspend = match_token(str, pm_modes, args);
902 if (suspend < 0)
903 return 0;
904
905 soc_pm.data.standby_mode = standby;
906 soc_pm.data.suspend_mode = suspend;
907
908 return 0;
909}
910early_param("atmel.pm_modes", at91_pm_modes_select);