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1/*
2 * arch/arm/mach-at91/pm.c
3 * AT91 Power Management
4 *
5 * Copyright (C) 2005 David Brownell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/genalloc.h>
14#include <linux/io.h>
15#include <linux/of_address.h>
16#include <linux/of.h>
17#include <linux/of_platform.h>
18#include <linux/parser.h>
19#include <linux/suspend.h>
20
21#include <linux/clk/at91_pmc.h>
22
23#include <asm/cacheflush.h>
24#include <asm/fncpy.h>
25#include <asm/system_misc.h>
26#include <asm/suspend.h>
27
28#include "generic.h"
29#include "pm.h"
30
31/*
32 * FIXME: this is needed to communicate between the pinctrl driver and
33 * the PM implementation in the machine. Possibly part of the PM
34 * implementation should be moved down into the pinctrl driver and get
35 * called as part of the generic suspend/resume path.
36 */
37#ifdef CONFIG_PINCTRL_AT91
38extern void at91_pinctrl_gpio_suspend(void);
39extern void at91_pinctrl_gpio_resume(void);
40#endif
41
42static const match_table_t pm_modes __initconst = {
43 { 0, "standby" },
44 { AT91_PM_SLOW_CLOCK, "ulp0" },
45 { AT91_PM_BACKUP, "backup" },
46 { -1, NULL },
47};
48
49static struct at91_pm_data pm_data = {
50 .standby_mode = 0,
51 .suspend_mode = AT91_PM_SLOW_CLOCK,
52};
53
54#define at91_ramc_read(id, field) \
55 __raw_readl(pm_data.ramc[id] + field)
56
57#define at91_ramc_write(id, field, value) \
58 __raw_writel(value, pm_data.ramc[id] + field)
59
60static int at91_pm_valid_state(suspend_state_t state)
61{
62 switch (state) {
63 case PM_SUSPEND_ON:
64 case PM_SUSPEND_STANDBY:
65 case PM_SUSPEND_MEM:
66 return 1;
67
68 default:
69 return 0;
70 }
71}
72
73static int canary = 0xA5A5A5A5;
74
75static struct at91_pm_bu {
76 int suspended;
77 unsigned long reserved;
78 phys_addr_t canary;
79 phys_addr_t resume;
80} *pm_bu;
81
82/*
83 * Called after processes are frozen, but before we shutdown devices.
84 */
85static int at91_pm_begin(suspend_state_t state)
86{
87 switch (state) {
88 case PM_SUSPEND_MEM:
89 pm_data.mode = pm_data.suspend_mode;
90 break;
91
92 case PM_SUSPEND_STANDBY:
93 pm_data.mode = pm_data.standby_mode;
94 break;
95
96 default:
97 pm_data.mode = -1;
98 }
99
100 return 0;
101}
102
103/*
104 * Verify that all the clocks are correct before entering
105 * slow-clock mode.
106 */
107static int at91_pm_verify_clocks(void)
108{
109 unsigned long scsr;
110 int i;
111
112 scsr = readl(pm_data.pmc + AT91_PMC_SCSR);
113
114 /* USB must not be using PLLB */
115 if ((scsr & pm_data.uhp_udp_mask) != 0) {
116 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
117 return 0;
118 }
119
120 /* PCK0..PCK3 must be disabled, or configured to use clk32k */
121 for (i = 0; i < 4; i++) {
122 u32 css;
123
124 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
125 continue;
126 css = readl(pm_data.pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
127 if (css != AT91_PMC_CSS_SLOW) {
128 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
129 return 0;
130 }
131 }
132
133 return 1;
134}
135
136/*
137 * Call this from platform driver suspend() to see how deeply to suspend.
138 * For example, some controllers (like OHCI) need one of the PLL clocks
139 * in order to act as a wakeup source, and those are not available when
140 * going into slow clock mode.
141 *
142 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
143 * the very same problem (but not using at91 main_clk), and it'd be better
144 * to add one generic API rather than lots of platform-specific ones.
145 */
146int at91_suspend_entering_slow_clock(void)
147{
148 return (pm_data.mode >= AT91_PM_SLOW_CLOCK);
149}
150EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
151
152static void (*at91_suspend_sram_fn)(struct at91_pm_data *);
153extern void at91_pm_suspend_in_sram(struct at91_pm_data *pm_data);
154extern u32 at91_pm_suspend_in_sram_sz;
155
156static int at91_suspend_finish(unsigned long val)
157{
158 flush_cache_all();
159 outer_disable();
160
161 at91_suspend_sram_fn(&pm_data);
162
163 return 0;
164}
165
166static void at91_pm_suspend(suspend_state_t state)
167{
168 if (pm_data.mode == AT91_PM_BACKUP) {
169 pm_bu->suspended = 1;
170
171 cpu_suspend(0, at91_suspend_finish);
172
173 /* The SRAM is lost between suspend cycles */
174 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
175 &at91_pm_suspend_in_sram,
176 at91_pm_suspend_in_sram_sz);
177 } else {
178 at91_suspend_finish(0);
179 }
180
181 outer_resume();
182}
183
184/*
185 * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup'
186 * event sources; and reduces DRAM power. But otherwise it's identical to
187 * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks.
188 *
189 * AT91_PM_SLOW_CLOCK is like STANDBY plus slow clock mode, so drivers must
190 * suspend more deeply, the master clock switches to the clk32k and turns off
191 * the main oscillator
192 *
193 * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh
194 */
195static int at91_pm_enter(suspend_state_t state)
196{
197#ifdef CONFIG_PINCTRL_AT91
198 at91_pinctrl_gpio_suspend();
199#endif
200
201 switch (state) {
202 case PM_SUSPEND_MEM:
203 case PM_SUSPEND_STANDBY:
204 /*
205 * Ensure that clocks are in a valid state.
206 */
207 if ((pm_data.mode >= AT91_PM_SLOW_CLOCK) &&
208 !at91_pm_verify_clocks())
209 goto error;
210
211 at91_pm_suspend(state);
212
213 break;
214
215 case PM_SUSPEND_ON:
216 cpu_do_idle();
217 break;
218
219 default:
220 pr_debug("AT91: PM - bogus suspend state %d\n", state);
221 goto error;
222 }
223
224error:
225#ifdef CONFIG_PINCTRL_AT91
226 at91_pinctrl_gpio_resume();
227#endif
228 return 0;
229}
230
231/*
232 * Called right prior to thawing processes.
233 */
234static void at91_pm_end(void)
235{
236}
237
238
239static const struct platform_suspend_ops at91_pm_ops = {
240 .valid = at91_pm_valid_state,
241 .begin = at91_pm_begin,
242 .enter = at91_pm_enter,
243 .end = at91_pm_end,
244};
245
246static struct platform_device at91_cpuidle_device = {
247 .name = "cpuidle-at91",
248};
249
250/*
251 * The AT91RM9200 goes into self-refresh mode with this command, and will
252 * terminate self-refresh automatically on the next SDRAM access.
253 *
254 * Self-refresh mode is exited as soon as a memory access is made, but we don't
255 * know for sure when that happens. However, we need to restore the low-power
256 * mode if it was enabled before going idle. Restoring low-power mode while
257 * still in self-refresh is "not recommended", but seems to work.
258 */
259static void at91rm9200_standby(void)
260{
261 asm volatile(
262 "b 1f\n\t"
263 ".align 5\n\t"
264 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
265 " str %2, [%1, %3]\n\t"
266 " mcr p15, 0, %0, c7, c0, 4\n\t"
267 :
268 : "r" (0), "r" (pm_data.ramc[0]),
269 "r" (1), "r" (AT91_MC_SDRAMC_SRR));
270}
271
272/* We manage both DDRAM/SDRAM controllers, we need more than one value to
273 * remember.
274 */
275static void at91_ddr_standby(void)
276{
277 /* Those two values allow us to delay self-refresh activation
278 * to the maximum. */
279 u32 lpr0, lpr1 = 0;
280 u32 mdr, saved_mdr0, saved_mdr1 = 0;
281 u32 saved_lpr0, saved_lpr1 = 0;
282
283 /* LPDDR1 --> force DDR2 mode during self-refresh */
284 saved_mdr0 = at91_ramc_read(0, AT91_DDRSDRC_MDR);
285 if ((saved_mdr0 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
286 mdr = saved_mdr0 & ~AT91_DDRSDRC_MD;
287 mdr |= AT91_DDRSDRC_MD_DDR2;
288 at91_ramc_write(0, AT91_DDRSDRC_MDR, mdr);
289 }
290
291 if (pm_data.ramc[1]) {
292 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
293 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
294 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
295 saved_mdr1 = at91_ramc_read(1, AT91_DDRSDRC_MDR);
296 if ((saved_mdr1 & AT91_DDRSDRC_MD) == AT91_DDRSDRC_MD_LOW_POWER_DDR) {
297 mdr = saved_mdr1 & ~AT91_DDRSDRC_MD;
298 mdr |= AT91_DDRSDRC_MD_DDR2;
299 at91_ramc_write(1, AT91_DDRSDRC_MDR, mdr);
300 }
301 }
302
303 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
304 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
305 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
306
307 /* self-refresh mode now */
308 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
309 if (pm_data.ramc[1])
310 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
311
312 cpu_do_idle();
313
314 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr0);
315 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
316 if (pm_data.ramc[1]) {
317 at91_ramc_write(0, AT91_DDRSDRC_MDR, saved_mdr1);
318 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
319 }
320}
321
322static void sama5d3_ddr_standby(void)
323{
324 u32 lpr0;
325 u32 saved_lpr0;
326
327 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
328 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
329 lpr0 |= AT91_DDRSDRC_LPCB_POWER_DOWN;
330
331 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
332
333 cpu_do_idle();
334
335 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
336}
337
338/* We manage both DDRAM/SDRAM controllers, we need more than one value to
339 * remember.
340 */
341static void at91sam9_sdram_standby(void)
342{
343 u32 lpr0, lpr1 = 0;
344 u32 saved_lpr0, saved_lpr1 = 0;
345
346 if (pm_data.ramc[1]) {
347 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
348 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
349 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
350 }
351
352 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
353 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
354 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
355
356 /* self-refresh mode now */
357 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
358 if (pm_data.ramc[1])
359 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
360
361 cpu_do_idle();
362
363 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
364 if (pm_data.ramc[1])
365 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
366}
367
368struct ramc_info {
369 void (*idle)(void);
370 unsigned int memctrl;
371};
372
373static const struct ramc_info ramc_infos[] __initconst = {
374 { .idle = at91rm9200_standby, .memctrl = AT91_MEMCTRL_MC},
375 { .idle = at91sam9_sdram_standby, .memctrl = AT91_MEMCTRL_SDRAMC},
376 { .idle = at91_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
377 { .idle = sama5d3_ddr_standby, .memctrl = AT91_MEMCTRL_DDRSDR},
378};
379
380static const struct of_device_id ramc_ids[] __initconst = {
381 { .compatible = "atmel,at91rm9200-sdramc", .data = &ramc_infos[0] },
382 { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
383 { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
384 { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
385 { /*sentinel*/ }
386};
387
388static __init void at91_dt_ramc(void)
389{
390 struct device_node *np;
391 const struct of_device_id *of_id;
392 int idx = 0;
393 void *standby = NULL;
394 const struct ramc_info *ramc;
395
396 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
397 pm_data.ramc[idx] = of_iomap(np, 0);
398 if (!pm_data.ramc[idx])
399 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
400
401 ramc = of_id->data;
402 if (!standby)
403 standby = ramc->idle;
404 pm_data.memctrl = ramc->memctrl;
405
406 idx++;
407 }
408
409 if (!idx)
410 panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
411
412 if (!standby) {
413 pr_warn("ramc no standby function available\n");
414 return;
415 }
416
417 at91_cpuidle_device.dev.platform_data = standby;
418}
419
420static void at91rm9200_idle(void)
421{
422 /*
423 * Disable the processor clock. The processor will be automatically
424 * re-enabled by an interrupt or by a reset.
425 */
426 writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR);
427}
428
429static void at91sam9_idle(void)
430{
431 writel(AT91_PMC_PCK, pm_data.pmc + AT91_PMC_SCDR);
432 cpu_do_idle();
433}
434
435static void __init at91_pm_sram_init(void)
436{
437 struct gen_pool *sram_pool;
438 phys_addr_t sram_pbase;
439 unsigned long sram_base;
440 struct device_node *node;
441 struct platform_device *pdev = NULL;
442
443 for_each_compatible_node(node, NULL, "mmio-sram") {
444 pdev = of_find_device_by_node(node);
445 if (pdev) {
446 of_node_put(node);
447 break;
448 }
449 }
450
451 if (!pdev) {
452 pr_warn("%s: failed to find sram device!\n", __func__);
453 return;
454 }
455
456 sram_pool = gen_pool_get(&pdev->dev, NULL);
457 if (!sram_pool) {
458 pr_warn("%s: sram pool unavailable!\n", __func__);
459 return;
460 }
461
462 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
463 if (!sram_base) {
464 pr_warn("%s: unable to alloc sram!\n", __func__);
465 return;
466 }
467
468 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
469 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
470 at91_pm_suspend_in_sram_sz, false);
471 if (!at91_suspend_sram_fn) {
472 pr_warn("SRAM: Could not map\n");
473 return;
474 }
475
476 /* Copy the pm suspend handler to SRAM */
477 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
478 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
479}
480
481static void __init at91_pm_backup_init(void)
482{
483 struct gen_pool *sram_pool;
484 struct device_node *np;
485 struct platform_device *pdev = NULL;
486
487 if ((pm_data.standby_mode != AT91_PM_BACKUP) &&
488 (pm_data.suspend_mode != AT91_PM_BACKUP))
489 return;
490
491 pm_bu = NULL;
492
493 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-shdwc");
494 if (!np) {
495 pr_warn("%s: failed to find shdwc!\n", __func__);
496 return;
497 }
498
499 pm_data.shdwc = of_iomap(np, 0);
500 of_node_put(np);
501
502 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-sfrbu");
503 if (!np) {
504 pr_warn("%s: failed to find sfrbu!\n", __func__);
505 goto sfrbu_fail;
506 }
507
508 pm_data.sfrbu = of_iomap(np, 0);
509 of_node_put(np);
510 pm_bu = NULL;
511
512 np = of_find_compatible_node(NULL, NULL, "atmel,sama5d2-securam");
513 if (!np)
514 goto securam_fail;
515
516 pdev = of_find_device_by_node(np);
517 of_node_put(np);
518 if (!pdev) {
519 pr_warn("%s: failed to find securam device!\n", __func__);
520 goto securam_fail;
521 }
522
523 sram_pool = gen_pool_get(&pdev->dev, NULL);
524 if (!sram_pool) {
525 pr_warn("%s: securam pool unavailable!\n", __func__);
526 goto securam_fail;
527 }
528
529 pm_bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
530 if (!pm_bu) {
531 pr_warn("%s: unable to alloc securam!\n", __func__);
532 goto securam_fail;
533 }
534
535 pm_bu->suspended = 0;
536 pm_bu->canary = __pa_symbol(&canary);
537 pm_bu->resume = __pa_symbol(cpu_resume);
538
539 return;
540
541sfrbu_fail:
542 iounmap(pm_data.shdwc);
543 pm_data.shdwc = NULL;
544securam_fail:
545 iounmap(pm_data.sfrbu);
546 pm_data.sfrbu = NULL;
547
548 if (pm_data.standby_mode == AT91_PM_BACKUP)
549 pm_data.standby_mode = AT91_PM_SLOW_CLOCK;
550 if (pm_data.suspend_mode == AT91_PM_BACKUP)
551 pm_data.suspend_mode = AT91_PM_SLOW_CLOCK;
552}
553
554struct pmc_info {
555 unsigned long uhp_udp_mask;
556};
557
558static const struct pmc_info pmc_infos[] __initconst = {
559 { .uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP },
560 { .uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP },
561 { .uhp_udp_mask = AT91SAM926x_PMC_UHP },
562};
563
564static const struct of_device_id atmel_pmc_ids[] __initconst = {
565 { .compatible = "atmel,at91rm9200-pmc", .data = &pmc_infos[0] },
566 { .compatible = "atmel,at91sam9260-pmc", .data = &pmc_infos[1] },
567 { .compatible = "atmel,at91sam9g45-pmc", .data = &pmc_infos[2] },
568 { .compatible = "atmel,at91sam9n12-pmc", .data = &pmc_infos[1] },
569 { .compatible = "atmel,at91sam9x5-pmc", .data = &pmc_infos[1] },
570 { .compatible = "atmel,sama5d3-pmc", .data = &pmc_infos[1] },
571 { .compatible = "atmel,sama5d2-pmc", .data = &pmc_infos[1] },
572 { /* sentinel */ },
573};
574
575static void __init at91_pm_init(void (*pm_idle)(void))
576{
577 struct device_node *pmc_np;
578 const struct of_device_id *of_id;
579 const struct pmc_info *pmc;
580
581 if (at91_cpuidle_device.dev.platform_data)
582 platform_device_register(&at91_cpuidle_device);
583
584 pmc_np = of_find_matching_node_and_match(NULL, atmel_pmc_ids, &of_id);
585 pm_data.pmc = of_iomap(pmc_np, 0);
586 if (!pm_data.pmc) {
587 pr_err("AT91: PM not supported, PMC not found\n");
588 return;
589 }
590
591 pmc = of_id->data;
592 pm_data.uhp_udp_mask = pmc->uhp_udp_mask;
593
594 if (pm_idle)
595 arm_pm_idle = pm_idle;
596
597 at91_pm_sram_init();
598
599 if (at91_suspend_sram_fn) {
600 suspend_set_ops(&at91_pm_ops);
601 pr_info("AT91: PM: standby: %s, suspend: %s\n",
602 pm_modes[pm_data.standby_mode].pattern,
603 pm_modes[pm_data.suspend_mode].pattern);
604 } else {
605 pr_info("AT91: PM not supported, due to no SRAM allocated\n");
606 }
607}
608
609void __init at91rm9200_pm_init(void)
610{
611 if (!IS_ENABLED(CONFIG_SOC_AT91RM9200))
612 return;
613
614 at91_dt_ramc();
615
616 /*
617 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
618 */
619 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
620
621 at91_pm_init(at91rm9200_idle);
622}
623
624void __init at91sam9_pm_init(void)
625{
626 if (!IS_ENABLED(CONFIG_SOC_AT91SAM9))
627 return;
628
629 at91_dt_ramc();
630 at91_pm_init(at91sam9_idle);
631}
632
633void __init sama5_pm_init(void)
634{
635 if (!IS_ENABLED(CONFIG_SOC_SAMA5))
636 return;
637
638 at91_dt_ramc();
639 at91_pm_init(NULL);
640}
641
642void __init sama5d2_pm_init(void)
643{
644 if (!IS_ENABLED(CONFIG_SOC_SAMA5D2))
645 return;
646
647 at91_pm_backup_init();
648 sama5_pm_init();
649}
650
651static int __init at91_pm_modes_select(char *str)
652{
653 char *s;
654 substring_t args[MAX_OPT_ARGS];
655 int standby, suspend;
656
657 if (!str)
658 return 0;
659
660 s = strsep(&str, ",");
661 standby = match_token(s, pm_modes, args);
662 if (standby < 0)
663 return 0;
664
665 suspend = match_token(str, pm_modes, args);
666 if (suspend < 0)
667 return 0;
668
669 pm_data.standby_mode = standby;
670 pm_data.suspend_mode = suspend;
671
672 return 0;
673}
674early_param("atmel.pm_modes", at91_pm_modes_select);
1/*
2 * arch/arm/mach-at91/pm.c
3 * AT91 Power Management
4 *
5 * Copyright (C) 2005 David Brownell
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#include <linux/gpio.h>
14#include <linux/suspend.h>
15#include <linux/sched.h>
16#include <linux/proc_fs.h>
17#include <linux/genalloc.h>
18#include <linux/interrupt.h>
19#include <linux/sysfs.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_platform.h>
23#include <linux/of_address.h>
24#include <linux/platform_device.h>
25#include <linux/io.h>
26#include <linux/clk/at91_pmc.h>
27
28#include <asm/irq.h>
29#include <linux/atomic.h>
30#include <asm/mach/time.h>
31#include <asm/mach/irq.h>
32#include <asm/fncpy.h>
33#include <asm/cacheflush.h>
34#include <asm/system_misc.h>
35
36#include "generic.h"
37#include "pm.h"
38
39static void __iomem *pmc;
40
41/*
42 * FIXME: this is needed to communicate between the pinctrl driver and
43 * the PM implementation in the machine. Possibly part of the PM
44 * implementation should be moved down into the pinctrl driver and get
45 * called as part of the generic suspend/resume path.
46 */
47#ifdef CONFIG_PINCTRL_AT91
48extern void at91_pinctrl_gpio_suspend(void);
49extern void at91_pinctrl_gpio_resume(void);
50#endif
51
52static struct {
53 unsigned long uhp_udp_mask;
54 int memctrl;
55} at91_pm_data;
56
57void __iomem *at91_ramc_base[2];
58
59static int at91_pm_valid_state(suspend_state_t state)
60{
61 switch (state) {
62 case PM_SUSPEND_ON:
63 case PM_SUSPEND_STANDBY:
64 case PM_SUSPEND_MEM:
65 return 1;
66
67 default:
68 return 0;
69 }
70}
71
72
73static suspend_state_t target_state;
74
75/*
76 * Called after processes are frozen, but before we shutdown devices.
77 */
78static int at91_pm_begin(suspend_state_t state)
79{
80 target_state = state;
81 return 0;
82}
83
84/*
85 * Verify that all the clocks are correct before entering
86 * slow-clock mode.
87 */
88static int at91_pm_verify_clocks(void)
89{
90 unsigned long scsr;
91 int i;
92
93 scsr = readl(pmc + AT91_PMC_SCSR);
94
95 /* USB must not be using PLLB */
96 if ((scsr & at91_pm_data.uhp_udp_mask) != 0) {
97 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
98 return 0;
99 }
100
101 /* PCK0..PCK3 must be disabled, or configured to use clk32k */
102 for (i = 0; i < 4; i++) {
103 u32 css;
104
105 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
106 continue;
107 css = readl(pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
108 if (css != AT91_PMC_CSS_SLOW) {
109 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
110 return 0;
111 }
112 }
113
114 return 1;
115}
116
117/*
118 * Call this from platform driver suspend() to see how deeply to suspend.
119 * For example, some controllers (like OHCI) need one of the PLL clocks
120 * in order to act as a wakeup source, and those are not available when
121 * going into slow clock mode.
122 *
123 * REVISIT: generalize as clk_will_be_available(clk)? Other platforms have
124 * the very same problem (but not using at91 main_clk), and it'd be better
125 * to add one generic API rather than lots of platform-specific ones.
126 */
127int at91_suspend_entering_slow_clock(void)
128{
129 return (target_state == PM_SUSPEND_MEM);
130}
131EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
132
133static void (*at91_suspend_sram_fn)(void __iomem *pmc, void __iomem *ramc0,
134 void __iomem *ramc1, int memctrl);
135
136extern void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *ramc0,
137 void __iomem *ramc1, int memctrl);
138extern u32 at91_pm_suspend_in_sram_sz;
139
140static void at91_pm_suspend(suspend_state_t state)
141{
142 unsigned int pm_data = at91_pm_data.memctrl;
143
144 pm_data |= (state == PM_SUSPEND_MEM) ?
145 AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;
146
147 flush_cache_all();
148 outer_disable();
149
150 at91_suspend_sram_fn(pmc, at91_ramc_base[0],
151 at91_ramc_base[1], pm_data);
152
153 outer_resume();
154}
155
156static int at91_pm_enter(suspend_state_t state)
157{
158#ifdef CONFIG_PINCTRL_AT91
159 at91_pinctrl_gpio_suspend();
160#endif
161 switch (state) {
162 /*
163 * Suspend-to-RAM is like STANDBY plus slow clock mode, so
164 * drivers must suspend more deeply, the master clock switches
165 * to the clk32k and turns off the main oscillator
166 */
167 case PM_SUSPEND_MEM:
168 /*
169 * Ensure that clocks are in a valid state.
170 */
171 if (!at91_pm_verify_clocks())
172 goto error;
173
174 at91_pm_suspend(state);
175
176 break;
177
178 /*
179 * STANDBY mode has *all* drivers suspended; ignores irqs not
180 * marked as 'wakeup' event sources; and reduces DRAM power.
181 * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and
182 * nothing fancy done with main or cpu clocks.
183 */
184 case PM_SUSPEND_STANDBY:
185 at91_pm_suspend(state);
186 break;
187
188 case PM_SUSPEND_ON:
189 cpu_do_idle();
190 break;
191
192 default:
193 pr_debug("AT91: PM - bogus suspend state %d\n", state);
194 goto error;
195 }
196
197error:
198 target_state = PM_SUSPEND_ON;
199
200#ifdef CONFIG_PINCTRL_AT91
201 at91_pinctrl_gpio_resume();
202#endif
203 return 0;
204}
205
206/*
207 * Called right prior to thawing processes.
208 */
209static void at91_pm_end(void)
210{
211 target_state = PM_SUSPEND_ON;
212}
213
214
215static const struct platform_suspend_ops at91_pm_ops = {
216 .valid = at91_pm_valid_state,
217 .begin = at91_pm_begin,
218 .enter = at91_pm_enter,
219 .end = at91_pm_end,
220};
221
222static struct platform_device at91_cpuidle_device = {
223 .name = "cpuidle-at91",
224};
225
226static void at91_pm_set_standby(void (*at91_standby)(void))
227{
228 if (at91_standby)
229 at91_cpuidle_device.dev.platform_data = at91_standby;
230}
231
232/*
233 * The AT91RM9200 goes into self-refresh mode with this command, and will
234 * terminate self-refresh automatically on the next SDRAM access.
235 *
236 * Self-refresh mode is exited as soon as a memory access is made, but we don't
237 * know for sure when that happens. However, we need to restore the low-power
238 * mode if it was enabled before going idle. Restoring low-power mode while
239 * still in self-refresh is "not recommended", but seems to work.
240 */
241static void at91rm9200_standby(void)
242{
243 u32 lpr = at91_ramc_read(0, AT91_MC_SDRAMC_LPR);
244
245 asm volatile(
246 "b 1f\n\t"
247 ".align 5\n\t"
248 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
249 " str %0, [%1, %2]\n\t"
250 " str %3, [%1, %4]\n\t"
251 " mcr p15, 0, %0, c7, c0, 4\n\t"
252 " str %5, [%1, %2]"
253 :
254 : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91_MC_SDRAMC_LPR),
255 "r" (1), "r" (AT91_MC_SDRAMC_SRR),
256 "r" (lpr));
257}
258
259/* We manage both DDRAM/SDRAM controllers, we need more than one value to
260 * remember.
261 */
262static void at91_ddr_standby(void)
263{
264 /* Those two values allow us to delay self-refresh activation
265 * to the maximum. */
266 u32 lpr0, lpr1 = 0;
267 u32 saved_lpr0, saved_lpr1 = 0;
268
269 if (at91_ramc_base[1]) {
270 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
271 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
272 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
273 }
274
275 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
276 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
277 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
278
279 /* self-refresh mode now */
280 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
281 if (at91_ramc_base[1])
282 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
283
284 cpu_do_idle();
285
286 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
287 if (at91_ramc_base[1])
288 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
289}
290
291/* We manage both DDRAM/SDRAM controllers, we need more than one value to
292 * remember.
293 */
294static void at91sam9_sdram_standby(void)
295{
296 u32 lpr0, lpr1 = 0;
297 u32 saved_lpr0, saved_lpr1 = 0;
298
299 if (at91_ramc_base[1]) {
300 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
301 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
302 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
303 }
304
305 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
306 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
307 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
308
309 /* self-refresh mode now */
310 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
311 if (at91_ramc_base[1])
312 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
313
314 cpu_do_idle();
315
316 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
317 if (at91_ramc_base[1])
318 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
319}
320
321static const struct of_device_id const ramc_ids[] __initconst = {
322 { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
323 { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
324 { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
325 { .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
326 { /*sentinel*/ }
327};
328
329static __init void at91_dt_ramc(void)
330{
331 struct device_node *np;
332 const struct of_device_id *of_id;
333 int idx = 0;
334 const void *standby = NULL;
335
336 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
337 at91_ramc_base[idx] = of_iomap(np, 0);
338 if (!at91_ramc_base[idx])
339 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
340
341 if (!standby)
342 standby = of_id->data;
343
344 idx++;
345 }
346
347 if (!idx)
348 panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
349
350 if (!standby) {
351 pr_warn("ramc no standby function available\n");
352 return;
353 }
354
355 at91_pm_set_standby(standby);
356}
357
358void at91rm9200_idle(void)
359{
360 /*
361 * Disable the processor clock. The processor will be automatically
362 * re-enabled by an interrupt or by a reset.
363 */
364 writel(AT91_PMC_PCK, pmc + AT91_PMC_SCDR);
365}
366
367void at91sam9_idle(void)
368{
369 writel(AT91_PMC_PCK, pmc + AT91_PMC_SCDR);
370 cpu_do_idle();
371}
372
373static void __init at91_pm_sram_init(void)
374{
375 struct gen_pool *sram_pool;
376 phys_addr_t sram_pbase;
377 unsigned long sram_base;
378 struct device_node *node;
379 struct platform_device *pdev = NULL;
380
381 for_each_compatible_node(node, NULL, "mmio-sram") {
382 pdev = of_find_device_by_node(node);
383 if (pdev) {
384 of_node_put(node);
385 break;
386 }
387 }
388
389 if (!pdev) {
390 pr_warn("%s: failed to find sram device!\n", __func__);
391 return;
392 }
393
394 sram_pool = gen_pool_get(&pdev->dev, NULL);
395 if (!sram_pool) {
396 pr_warn("%s: sram pool unavailable!\n", __func__);
397 return;
398 }
399
400 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
401 if (!sram_base) {
402 pr_warn("%s: unable to alloc sram!\n", __func__);
403 return;
404 }
405
406 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
407 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
408 at91_pm_suspend_in_sram_sz, false);
409 if (!at91_suspend_sram_fn) {
410 pr_warn("SRAM: Could not map\n");
411 return;
412 }
413
414 /* Copy the pm suspend handler to SRAM */
415 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
416 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
417}
418
419static const struct of_device_id atmel_pmc_ids[] __initconst = {
420 { .compatible = "atmel,at91rm9200-pmc" },
421 { .compatible = "atmel,at91sam9260-pmc" },
422 { .compatible = "atmel,at91sam9g45-pmc" },
423 { .compatible = "atmel,at91sam9n12-pmc" },
424 { .compatible = "atmel,at91sam9x5-pmc" },
425 { .compatible = "atmel,sama5d3-pmc" },
426 { .compatible = "atmel,sama5d2-pmc" },
427 { /* sentinel */ },
428};
429
430static void __init at91_pm_init(void (*pm_idle)(void))
431{
432 struct device_node *pmc_np;
433
434 if (at91_cpuidle_device.dev.platform_data)
435 platform_device_register(&at91_cpuidle_device);
436
437 pmc_np = of_find_matching_node(NULL, atmel_pmc_ids);
438 pmc = of_iomap(pmc_np, 0);
439 if (!pmc) {
440 pr_err("AT91: PM not supported, PMC not found\n");
441 return;
442 }
443
444 if (pm_idle)
445 arm_pm_idle = pm_idle;
446
447 at91_pm_sram_init();
448
449 if (at91_suspend_sram_fn)
450 suspend_set_ops(&at91_pm_ops);
451 else
452 pr_info("AT91: PM not supported, due to no SRAM allocated\n");
453}
454
455void __init at91rm9200_pm_init(void)
456{
457 at91_dt_ramc();
458
459 /*
460 * AT91RM9200 SDRAM low-power mode cannot be used with self-refresh.
461 */
462 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
463
464 at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP;
465 at91_pm_data.memctrl = AT91_MEMCTRL_MC;
466
467 at91_pm_init(at91rm9200_idle);
468}
469
470void __init at91sam9260_pm_init(void)
471{
472 at91_dt_ramc();
473 at91_pm_data.memctrl = AT91_MEMCTRL_SDRAMC;
474 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
475 at91_pm_init(at91sam9_idle);
476}
477
478void __init at91sam9g45_pm_init(void)
479{
480 at91_dt_ramc();
481 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP;
482 at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
483 at91_pm_init(at91sam9_idle);
484}
485
486void __init at91sam9x5_pm_init(void)
487{
488 at91_dt_ramc();
489 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
490 at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
491 at91_pm_init(at91sam9_idle);
492}
493
494void __init sama5_pm_init(void)
495{
496 at91_dt_ramc();
497 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
498 at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
499 at91_pm_init(NULL);
500}