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1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: John Crispin <john@phrozen.org>
4 * Sean Wang <sean.wang@mediatek.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <dt-bindings/interrupt-controller/irq.h>
17#include <dt-bindings/interrupt-controller/arm-gic.h>
18#include <dt-bindings/clock/mt2701-clk.h>
19#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
20#include <dt-bindings/power/mt2701-power.h>
21#include <dt-bindings/gpio/gpio.h>
22#include <dt-bindings/phy/phy.h>
23#include <dt-bindings/reset/mt2701-resets.h>
24#include <dt-bindings/thermal/thermal.h>
25#include "skeleton64.dtsi"
26
27/ {
28 compatible = "mediatek,mt7623";
29 interrupt-parent = <&sysirq>;
30
31 cpu_opp_table: opp-table {
32 compatible = "operating-points-v2";
33 opp-shared;
34
35 opp-98000000 {
36 opp-hz = /bits/ 64 <98000000>;
37 opp-microvolt = <1050000>;
38 };
39
40 opp-198000000 {
41 opp-hz = /bits/ 64 <198000000>;
42 opp-microvolt = <1050000>;
43 };
44
45 opp-398000000 {
46 opp-hz = /bits/ 64 <398000000>;
47 opp-microvolt = <1050000>;
48 };
49
50 opp-598000000 {
51 opp-hz = /bits/ 64 <598000000>;
52 opp-microvolt = <1050000>;
53 };
54
55 opp-747500000 {
56 opp-hz = /bits/ 64 <747500000>;
57 opp-microvolt = <1050000>;
58 };
59
60 opp-1040000000 {
61 opp-hz = /bits/ 64 <1040000000>;
62 opp-microvolt = <1150000>;
63 };
64
65 opp-1196000000 {
66 opp-hz = /bits/ 64 <1196000000>;
67 opp-microvolt = <1200000>;
68 };
69
70 opp-1300000000 {
71 opp-hz = /bits/ 64 <1300000000>;
72 opp-microvolt = <1300000>;
73 };
74 };
75
76 cpus {
77 #address-cells = <1>;
78 #size-cells = <0>;
79 enable-method = "mediatek,mt6589-smp";
80
81 cpu0: cpu@0 {
82 device_type = "cpu";
83 compatible = "arm,cortex-a7";
84 reg = <0x0>;
85 clocks = <&infracfg CLK_INFRA_CPUSEL>,
86 <&apmixedsys CLK_APMIXED_MAINPLL>;
87 clock-names = "cpu", "intermediate";
88 operating-points-v2 = <&cpu_opp_table>;
89 #cooling-cells = <2>;
90 clock-frequency = <1300000000>;
91 };
92
93 cpu1: cpu@1 {
94 device_type = "cpu";
95 compatible = "arm,cortex-a7";
96 reg = <0x1>;
97 clocks = <&infracfg CLK_INFRA_CPUSEL>,
98 <&apmixedsys CLK_APMIXED_MAINPLL>;
99 clock-names = "cpu", "intermediate";
100 operating-points-v2 = <&cpu_opp_table>;
101 clock-frequency = <1300000000>;
102 };
103
104 cpu2: cpu@2 {
105 device_type = "cpu";
106 compatible = "arm,cortex-a7";
107 reg = <0x2>;
108 clocks = <&infracfg CLK_INFRA_CPUSEL>,
109 <&apmixedsys CLK_APMIXED_MAINPLL>;
110 clock-names = "cpu", "intermediate";
111 operating-points-v2 = <&cpu_opp_table>;
112 clock-frequency = <1300000000>;
113 };
114
115 cpu3: cpu@3 {
116 device_type = "cpu";
117 compatible = "arm,cortex-a7";
118 reg = <0x3>;
119 clocks = <&infracfg CLK_INFRA_CPUSEL>,
120 <&apmixedsys CLK_APMIXED_MAINPLL>;
121 clock-names = "cpu", "intermediate";
122 operating-points-v2 = <&cpu_opp_table>;
123 clock-frequency = <1300000000>;
124 };
125 };
126
127 system_clk: dummy13m {
128 compatible = "fixed-clock";
129 clock-frequency = <13000000>;
130 #clock-cells = <0>;
131 };
132
133 rtc32k: oscillator@1 {
134 compatible = "fixed-clock";
135 #clock-cells = <0>;
136 clock-frequency = <32000>;
137 clock-output-names = "rtc32k";
138 };
139
140 clk26m: oscillator@0 {
141 compatible = "fixed-clock";
142 #clock-cells = <0>;
143 clock-frequency = <26000000>;
144 clock-output-names = "clk26m";
145 };
146
147 thermal-zones {
148 cpu_thermal: cpu-thermal {
149 polling-delay-passive = <1000>;
150 polling-delay = <1000>;
151
152 thermal-sensors = <&thermal 0>;
153
154 trips {
155 cpu_passive: cpu-passive {
156 temperature = <47000>;
157 hysteresis = <2000>;
158 type = "passive";
159 };
160
161 cpu_active: cpu-active {
162 temperature = <67000>;
163 hysteresis = <2000>;
164 type = "active";
165 };
166
167 cpu_hot: cpu-hot {
168 temperature = <87000>;
169 hysteresis = <2000>;
170 type = "hot";
171 };
172
173 cpu-crit {
174 temperature = <107000>;
175 hysteresis = <2000>;
176 type = "critical";
177 };
178 };
179
180 cooling-maps {
181 map0 {
182 trip = <&cpu_passive>;
183 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
184 };
185
186 map1 {
187 trip = <&cpu_active>;
188 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
189 };
190
191 map2 {
192 trip = <&cpu_hot>;
193 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
194 };
195 };
196 };
197 };
198
199 timer {
200 compatible = "arm,armv7-timer";
201 interrupt-parent = <&gic>;
202 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
203 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
204 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
205 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
206 clock-frequency = <13000000>;
207 arm,cpu-registers-not-fw-configured;
208 };
209
210 topckgen: syscon@10000000 {
211 compatible = "mediatek,mt7623-topckgen",
212 "mediatek,mt2701-topckgen",
213 "syscon";
214 reg = <0 0x10000000 0 0x1000>;
215 #clock-cells = <1>;
216 };
217
218 infracfg: syscon@10001000 {
219 compatible = "mediatek,mt7623-infracfg",
220 "mediatek,mt2701-infracfg",
221 "syscon";
222 reg = <0 0x10001000 0 0x1000>;
223 #clock-cells = <1>;
224 #reset-cells = <1>;
225 };
226
227 pericfg: syscon@10003000 {
228 compatible = "mediatek,mt7623-pericfg",
229 "mediatek,mt2701-pericfg",
230 "syscon";
231 reg = <0 0x10003000 0 0x1000>;
232 #clock-cells = <1>;
233 #reset-cells = <1>;
234 };
235
236 pio: pinctrl@10005000 {
237 compatible = "mediatek,mt7623-pinctrl";
238 reg = <0 0x1000b000 0 0x1000>;
239 mediatek,pctl-regmap = <&syscfg_pctl_a>;
240 pins-are-numbered;
241 gpio-controller;
242 #gpio-cells = <2>;
243 interrupt-controller;
244 interrupt-parent = <&gic>;
245 #interrupt-cells = <2>;
246 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
247 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
248 };
249
250 syscfg_pctl_a: syscfg@10005000 {
251 compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
252 reg = <0 0x10005000 0 0x1000>;
253 };
254
255 scpsys: scpsys@10006000 {
256 compatible = "mediatek,mt7623-scpsys",
257 "mediatek,mt2701-scpsys",
258 "syscon";
259 #power-domain-cells = <1>;
260 reg = <0 0x10006000 0 0x1000>;
261 infracfg = <&infracfg>;
262 clocks = <&topckgen CLK_TOP_MM_SEL>,
263 <&topckgen CLK_TOP_MFG_SEL>,
264 <&topckgen CLK_TOP_ETHIF_SEL>;
265 clock-names = "mm", "mfg", "ethif";
266 };
267
268 watchdog: watchdog@10007000 {
269 compatible = "mediatek,mt7623-wdt",
270 "mediatek,mt6589-wdt";
271 reg = <0 0x10007000 0 0x100>;
272 };
273
274 timer: timer@10008000 {
275 compatible = "mediatek,mt7623-timer",
276 "mediatek,mt6577-timer";
277 reg = <0 0x10008000 0 0x80>;
278 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
279 clocks = <&system_clk>, <&rtc32k>;
280 clock-names = "system-clk", "rtc-clk";
281 };
282
283 pwrap: pwrap@1000d000 {
284 compatible = "mediatek,mt7623-pwrap",
285 "mediatek,mt2701-pwrap";
286 reg = <0 0x1000d000 0 0x1000>;
287 reg-names = "pwrap";
288 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
289 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
290 reset-names = "pwrap";
291 clocks = <&infracfg CLK_INFRA_PMICSPI>,
292 <&infracfg CLK_INFRA_PMICWRAP>;
293 clock-names = "spi", "wrap";
294 };
295
296 cir: cir@10013000 {
297 compatible = "mediatek,mt7623-cir";
298 reg = <0 0x10013000 0 0x1000>;
299 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
300 clocks = <&infracfg CLK_INFRA_IRRX>;
301 clock-names = "clk";
302 status = "disabled";
303 };
304
305 sysirq: interrupt-controller@10200100 {
306 compatible = "mediatek,mt7623-sysirq",
307 "mediatek,mt6577-sysirq";
308 interrupt-controller;
309 #interrupt-cells = <3>;
310 interrupt-parent = <&gic>;
311 reg = <0 0x10200100 0 0x1c>;
312 };
313
314 efuse: efuse@10206000 {
315 compatible = "mediatek,mt7623-efuse",
316 "mediatek,mt8173-efuse";
317 reg = <0 0x10206000 0 0x1000>;
318 #address-cells = <1>;
319 #size-cells = <1>;
320 thermal_calibration_data: calib@424 {
321 reg = <0x424 0xc>;
322 };
323 };
324
325 apmixedsys: syscon@10209000 {
326 compatible = "mediatek,mt7623-apmixedsys",
327 "mediatek,mt2701-apmixedsys",
328 "syscon";
329 reg = <0 0x10209000 0 0x1000>;
330 #clock-cells = <1>;
331 };
332
333 rng: rng@1020f000 {
334 compatible = "mediatek,mt7623-rng";
335 reg = <0 0x1020f000 0 0x1000>;
336 clocks = <&infracfg CLK_INFRA_TRNG>;
337 clock-names = "rng";
338 };
339
340 gic: interrupt-controller@10211000 {
341 compatible = "arm,cortex-a7-gic";
342 interrupt-controller;
343 #interrupt-cells = <3>;
344 interrupt-parent = <&gic>;
345 reg = <0 0x10211000 0 0x1000>,
346 <0 0x10212000 0 0x2000>,
347 <0 0x10214000 0 0x2000>,
348 <0 0x10216000 0 0x2000>;
349 };
350
351 auxadc: adc@11001000 {
352 compatible = "mediatek,mt7623-auxadc",
353 "mediatek,mt2701-auxadc";
354 reg = <0 0x11001000 0 0x1000>;
355 clocks = <&pericfg CLK_PERI_AUXADC>;
356 clock-names = "main";
357 #io-channel-cells = <1>;
358 };
359
360 uart0: serial@11002000 {
361 compatible = "mediatek,mt7623-uart",
362 "mediatek,mt6577-uart";
363 reg = <0 0x11002000 0 0x400>;
364 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
365 clocks = <&pericfg CLK_PERI_UART0_SEL>,
366 <&pericfg CLK_PERI_UART0>;
367 clock-names = "baud", "bus";
368 status = "disabled";
369 };
370
371 uart1: serial@11003000 {
372 compatible = "mediatek,mt7623-uart",
373 "mediatek,mt6577-uart";
374 reg = <0 0x11003000 0 0x400>;
375 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
376 clocks = <&pericfg CLK_PERI_UART1_SEL>,
377 <&pericfg CLK_PERI_UART1>;
378 clock-names = "baud", "bus";
379 status = "disabled";
380 };
381
382 uart2: serial@11004000 {
383 compatible = "mediatek,mt7623-uart",
384 "mediatek,mt6577-uart";
385 reg = <0 0x11004000 0 0x400>;
386 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
387 clocks = <&pericfg CLK_PERI_UART2_SEL>,
388 <&pericfg CLK_PERI_UART2>;
389 clock-names = "baud", "bus";
390 status = "disabled";
391 };
392
393 uart3: serial@11005000 {
394 compatible = "mediatek,mt7623-uart",
395 "mediatek,mt6577-uart";
396 reg = <0 0x11005000 0 0x400>;
397 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
398 clocks = <&pericfg CLK_PERI_UART3_SEL>,
399 <&pericfg CLK_PERI_UART3>;
400 clock-names = "baud", "bus";
401 status = "disabled";
402 };
403
404 pwm: pwm@11006000 {
405 compatible = "mediatek,mt7623-pwm";
406 reg = <0 0x11006000 0 0x1000>;
407 #pwm-cells = <2>;
408 clocks = <&topckgen CLK_TOP_PWM_SEL>,
409 <&pericfg CLK_PERI_PWM>,
410 <&pericfg CLK_PERI_PWM1>,
411 <&pericfg CLK_PERI_PWM2>,
412 <&pericfg CLK_PERI_PWM3>,
413 <&pericfg CLK_PERI_PWM4>,
414 <&pericfg CLK_PERI_PWM5>;
415 clock-names = "top", "main", "pwm1", "pwm2",
416 "pwm3", "pwm4", "pwm5";
417 status = "disabled";
418 };
419
420 i2c0: i2c@11007000 {
421 compatible = "mediatek,mt7623-i2c",
422 "mediatek,mt6577-i2c";
423 reg = <0 0x11007000 0 0x70>,
424 <0 0x11000200 0 0x80>;
425 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
426 clock-div = <16>;
427 clocks = <&pericfg CLK_PERI_I2C0>,
428 <&pericfg CLK_PERI_AP_DMA>;
429 clock-names = "main", "dma";
430 #address-cells = <1>;
431 #size-cells = <0>;
432 status = "disabled";
433 };
434
435 i2c1: i2c@11008000 {
436 compatible = "mediatek,mt7623-i2c",
437 "mediatek,mt6577-i2c";
438 reg = <0 0x11008000 0 0x70>,
439 <0 0x11000280 0 0x80>;
440 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
441 clock-div = <16>;
442 clocks = <&pericfg CLK_PERI_I2C1>,
443 <&pericfg CLK_PERI_AP_DMA>;
444 clock-names = "main", "dma";
445 #address-cells = <1>;
446 #size-cells = <0>;
447 status = "disabled";
448 };
449
450 i2c2: i2c@11009000 {
451 compatible = "mediatek,mt7623-i2c",
452 "mediatek,mt6577-i2c";
453 reg = <0 0x11009000 0 0x70>,
454 <0 0x11000300 0 0x80>;
455 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
456 clock-div = <16>;
457 clocks = <&pericfg CLK_PERI_I2C2>,
458 <&pericfg CLK_PERI_AP_DMA>;
459 clock-names = "main", "dma";
460 #address-cells = <1>;
461 #size-cells = <0>;
462 status = "disabled";
463 };
464
465 spi0: spi@1100a000 {
466 compatible = "mediatek,mt7623-spi",
467 "mediatek,mt2701-spi";
468 #address-cells = <1>;
469 #size-cells = <0>;
470 reg = <0 0x1100a000 0 0x100>;
471 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
472 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
473 <&topckgen CLK_TOP_SPI0_SEL>,
474 <&pericfg CLK_PERI_SPI0>;
475 clock-names = "parent-clk", "sel-clk", "spi-clk";
476 status = "disabled";
477 };
478
479 thermal: thermal@1100b000 {
480 #thermal-sensor-cells = <1>;
481 compatible = "mediatek,mt7623-thermal",
482 "mediatek,mt2701-thermal";
483 reg = <0 0x1100b000 0 0x1000>;
484 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
485 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
486 clock-names = "therm", "auxadc";
487 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
488 reset-names = "therm";
489 mediatek,auxadc = <&auxadc>;
490 mediatek,apmixedsys = <&apmixedsys>;
491 nvmem-cells = <&thermal_calibration_data>;
492 nvmem-cell-names = "calibration-data";
493 };
494
495 nandc: nfi@1100d000 {
496 compatible = "mediatek,mt7623-nfc",
497 "mediatek,mt2701-nfc";
498 reg = <0 0x1100d000 0 0x1000>;
499 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
500 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
501 clocks = <&pericfg CLK_PERI_NFI>,
502 <&pericfg CLK_PERI_NFI_PAD>;
503 clock-names = "nfi_clk", "pad_clk";
504 status = "disabled";
505 ecc-engine = <&bch>;
506 #address-cells = <1>;
507 #size-cells = <0>;
508 };
509
510 bch: ecc@1100e000 {
511 compatible = "mediatek,mt7623-ecc",
512 "mediatek,mt2701-ecc";
513 reg = <0 0x1100e000 0 0x1000>;
514 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
515 clocks = <&pericfg CLK_PERI_NFI_ECC>;
516 clock-names = "nfiecc_clk";
517 status = "disabled";
518 };
519
520 spi1: spi@11016000 {
521 compatible = "mediatek,mt7623-spi",
522 "mediatek,mt2701-spi";
523 #address-cells = <1>;
524 #size-cells = <0>;
525 reg = <0 0x11016000 0 0x100>;
526 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
527 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
528 <&topckgen CLK_TOP_SPI1_SEL>,
529 <&pericfg CLK_PERI_SPI1>;
530 clock-names = "parent-clk", "sel-clk", "spi-clk";
531 status = "disabled";
532 };
533
534 spi2: spi@11017000 {
535 compatible = "mediatek,mt7623-spi",
536 "mediatek,mt2701-spi";
537 #address-cells = <1>;
538 #size-cells = <0>;
539 reg = <0 0x11017000 0 0x1000>;
540 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
541 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
542 <&topckgen CLK_TOP_SPI2_SEL>,
543 <&pericfg CLK_PERI_SPI2>;
544 clock-names = "parent-clk", "sel-clk", "spi-clk";
545 status = "disabled";
546 };
547
548 afe: audio-controller@11220000 {
549 compatible = "mediatek,mt7623-audio",
550 "mediatek,mt2701-audio";
551 reg = <0 0x11220000 0 0x2000>,
552 <0 0x112a0000 0 0x20000>;
553 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
554 <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
555 interrupt-names = "afe", "asys";
556 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
557
558 clocks = <&infracfg CLK_INFRA_AUDIO>,
559 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
560 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
561 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
562 <&topckgen CLK_TOP_AUD_MUX2_DIV>,
563 <&topckgen CLK_TOP_AUD_48K_TIMING>,
564 <&topckgen CLK_TOP_AUD_44K_TIMING>,
565 <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
566 <&topckgen CLK_TOP_APLL_SEL>,
567 <&topckgen CLK_TOP_AUD1PLL_98M>,
568 <&topckgen CLK_TOP_AUD2PLL_90M>,
569 <&topckgen CLK_TOP_HADDS2PLL_98M>,
570 <&topckgen CLK_TOP_HADDS2PLL_294M>,
571 <&topckgen CLK_TOP_AUDPLL>,
572 <&topckgen CLK_TOP_AUDPLL_D4>,
573 <&topckgen CLK_TOP_AUDPLL_D8>,
574 <&topckgen CLK_TOP_AUDPLL_D16>,
575 <&topckgen CLK_TOP_AUDPLL_D24>,
576 <&topckgen CLK_TOP_AUDINTBUS_SEL>,
577 <&clk26m>,
578 <&topckgen CLK_TOP_SYSPLL1_D4>,
579 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
580 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
581 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
582 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
583 <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
584 <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
585 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
586 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
587 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
588 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
589 <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
590 <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
591 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
592 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
593 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
594 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
595 <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
596 <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
597 <&topckgen CLK_TOP_ASM_M_SEL>,
598 <&topckgen CLK_TOP_ASM_H_SEL>,
599 <&topckgen CLK_TOP_UNIVPLL2_D4>,
600 <&topckgen CLK_TOP_UNIVPLL2_D2>,
601 <&topckgen CLK_TOP_SYSPLL_D5>;
602
603 clock-names = "infra_sys_audio_clk",
604 "top_audio_mux1_sel",
605 "top_audio_mux2_sel",
606 "top_audio_mux1_div",
607 "top_audio_mux2_div",
608 "top_audio_48k_timing",
609 "top_audio_44k_timing",
610 "top_audpll_mux_sel",
611 "top_apll_sel",
612 "top_aud1_pll_98M",
613 "top_aud2_pll_90M",
614 "top_hadds2_pll_98M",
615 "top_hadds2_pll_294M",
616 "top_audpll",
617 "top_audpll_d4",
618 "top_audpll_d8",
619 "top_audpll_d16",
620 "top_audpll_d24",
621 "top_audintbus_sel",
622 "clk_26m",
623 "top_syspll1_d4",
624 "top_aud_k1_src_sel",
625 "top_aud_k2_src_sel",
626 "top_aud_k3_src_sel",
627 "top_aud_k4_src_sel",
628 "top_aud_k5_src_sel",
629 "top_aud_k6_src_sel",
630 "top_aud_k1_src_div",
631 "top_aud_k2_src_div",
632 "top_aud_k3_src_div",
633 "top_aud_k4_src_div",
634 "top_aud_k5_src_div",
635 "top_aud_k6_src_div",
636 "top_aud_i2s1_mclk",
637 "top_aud_i2s2_mclk",
638 "top_aud_i2s3_mclk",
639 "top_aud_i2s4_mclk",
640 "top_aud_i2s5_mclk",
641 "top_aud_i2s6_mclk",
642 "top_asm_m_sel",
643 "top_asm_h_sel",
644 "top_univpll2_d4",
645 "top_univpll2_d2",
646 "top_syspll_d5";
647 };
648
649 mmc0: mmc@11230000 {
650 compatible = "mediatek,mt7623-mmc",
651 "mediatek,mt2701-mmc";
652 reg = <0 0x11230000 0 0x1000>;
653 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
654 clocks = <&pericfg CLK_PERI_MSDC30_0>,
655 <&topckgen CLK_TOP_MSDC30_0_SEL>;
656 clock-names = "source", "hclk";
657 status = "disabled";
658 };
659
660 mmc1: mmc@11240000 {
661 compatible = "mediatek,mt7623-mmc",
662 "mediatek,mt2701-mmc";
663 reg = <0 0x11240000 0 0x1000>;
664 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
665 clocks = <&pericfg CLK_PERI_MSDC30_1>,
666 <&topckgen CLK_TOP_MSDC30_1_SEL>;
667 clock-names = "source", "hclk";
668 status = "disabled";
669 };
670
671 hifsys: syscon@1a000000 {
672 compatible = "mediatek,mt7623-hifsys",
673 "mediatek,mt2701-hifsys",
674 "syscon";
675 reg = <0 0x1a000000 0 0x1000>;
676 #clock-cells = <1>;
677 #reset-cells = <1>;
678 };
679
680 pcie: pcie@1a140000 {
681 compatible = "mediatek,mt7623-pcie";
682 device_type = "pci";
683 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
684 <0 0x1a142000 0 0x1000>, /* Port0 registers */
685 <0 0x1a143000 0 0x1000>, /* Port1 registers */
686 <0 0x1a144000 0 0x1000>; /* Port2 registers */
687 reg-names = "subsys", "port0", "port1", "port2";
688 #address-cells = <3>;
689 #size-cells = <2>;
690 #interrupt-cells = <1>;
691 interrupt-map-mask = <0xf800 0 0 0>;
692 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
693 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
694 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
695 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
696 <&hifsys CLK_HIFSYS_PCIE0>,
697 <&hifsys CLK_HIFSYS_PCIE1>,
698 <&hifsys CLK_HIFSYS_PCIE2>;
699 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
700 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
701 <&hifsys MT2701_HIFSYS_PCIE1_RST>,
702 <&hifsys MT2701_HIFSYS_PCIE2_RST>;
703 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
704 phys = <&pcie0_port PHY_TYPE_PCIE>,
705 <&pcie1_port PHY_TYPE_PCIE>,
706 <&u3port1 PHY_TYPE_PCIE>;
707 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
708 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
709 bus-range = <0x00 0xff>;
710 status = "disabled";
711 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
712 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;
713
714 pcie@0,0 {
715 reg = <0x0000 0 0 0 0>;
716 #address-cells = <3>;
717 #size-cells = <2>;
718 #interrupt-cells = <1>;
719 interrupt-map-mask = <0 0 0 0>;
720 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
721 ranges;
722 num-lanes = <1>;
723 status = "disabled";
724 };
725
726 pcie@1,0 {
727 reg = <0x0800 0 0 0 0>;
728 #address-cells = <3>;
729 #size-cells = <2>;
730 #interrupt-cells = <1>;
731 interrupt-map-mask = <0 0 0 0>;
732 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
733 ranges;
734 num-lanes = <1>;
735 status = "disabled";
736 };
737
738 pcie@2,0 {
739 reg = <0x1000 0 0 0 0>;
740 #address-cells = <3>;
741 #size-cells = <2>;
742 #interrupt-cells = <1>;
743 interrupt-map-mask = <0 0 0 0>;
744 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
745 ranges;
746 num-lanes = <1>;
747 status = "disabled";
748 };
749 };
750
751 pcie0_phy: pcie-phy@1a149000 {
752 compatible = "mediatek,generic-tphy-v1";
753 reg = <0 0x1a149000 0 0x0700>;
754 #address-cells = <2>;
755 #size-cells = <2>;
756 ranges;
757 status = "disabled";
758
759 pcie0_port: pcie-phy@1a149900 {
760 reg = <0 0x1a149900 0 0x0700>;
761 clocks = <&clk26m>;
762 clock-names = "ref";
763 #phy-cells = <1>;
764 status = "okay";
765 };
766 };
767
768 pcie1_phy: pcie-phy@1a14a000 {
769 compatible = "mediatek,generic-tphy-v1";
770 reg = <0 0x1a14a000 0 0x0700>;
771 #address-cells = <2>;
772 #size-cells = <2>;
773 ranges;
774 status = "disabled";
775
776 pcie1_port: pcie-phy@1a14a900 {
777 reg = <0 0x1a14a900 0 0x0700>;
778 clocks = <&clk26m>;
779 clock-names = "ref";
780 #phy-cells = <1>;
781 status = "okay";
782 };
783 };
784
785 usb1: usb@1a1c0000 {
786 compatible = "mediatek,mt7623-xhci",
787 "mediatek,mt8173-xhci";
788 reg = <0 0x1a1c0000 0 0x1000>,
789 <0 0x1a1c4700 0 0x0100>;
790 reg-names = "mac", "ippc";
791 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
792 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
793 <&topckgen CLK_TOP_ETHIF_SEL>;
794 clock-names = "sys_ck", "ref_ck";
795 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
796 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
797 status = "disabled";
798 };
799
800 u3phy1: usb-phy@1a1c4000 {
801 compatible = "mediatek,mt7623-u3phy",
802 "mediatek,mt2701-u3phy";
803 reg = <0 0x1a1c4000 0 0x0700>;
804 #address-cells = <2>;
805 #size-cells = <2>;
806 ranges;
807 status = "disabled";
808
809 u2port0: usb-phy@1a1c4800 {
810 reg = <0 0x1a1c4800 0 0x0100>;
811 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
812 clock-names = "ref";
813 #phy-cells = <1>;
814 status = "okay";
815 };
816
817 u3port0: usb-phy@1a1c4900 {
818 reg = <0 0x1a1c4900 0 0x0700>;
819 clocks = <&clk26m>;
820 clock-names = "ref";
821 #phy-cells = <1>;
822 status = "okay";
823 };
824 };
825
826 usb2: usb@1a240000 {
827 compatible = "mediatek,mt7623-xhci",
828 "mediatek,mt8173-xhci";
829 reg = <0 0x1a240000 0 0x1000>,
830 <0 0x1a244700 0 0x0100>;
831 reg-names = "mac", "ippc";
832 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
833 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
834 <&topckgen CLK_TOP_ETHIF_SEL>;
835 clock-names = "sys_ck", "ref_ck";
836 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
837 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
838 status = "disabled";
839 };
840
841 u3phy2: usb-phy@1a244000 {
842 compatible = "mediatek,mt7623-u3phy",
843 "mediatek,mt2701-u3phy";
844 reg = <0 0x1a244000 0 0x0700>;
845 #address-cells = <2>;
846 #size-cells = <2>;
847 ranges;
848 status = "disabled";
849
850 u2port1: usb-phy@1a244800 {
851 reg = <0 0x1a244800 0 0x0100>;
852 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
853 clock-names = "ref";
854 #phy-cells = <1>;
855 status = "okay";
856 };
857
858 u3port1: usb-phy@1a244900 {
859 reg = <0 0x1a244900 0 0x0700>;
860 clocks = <&clk26m>;
861 clock-names = "ref";
862 #phy-cells = <1>;
863 status = "okay";
864 };
865 };
866
867 ethsys: syscon@1b000000 {
868 compatible = "mediatek,mt7623-ethsys",
869 "mediatek,mt2701-ethsys",
870 "syscon";
871 reg = <0 0x1b000000 0 0x1000>;
872 #clock-cells = <1>;
873 #reset-cells = <1>;
874 };
875
876 eth: ethernet@1b100000 {
877 compatible = "mediatek,mt7623-eth",
878 "mediatek,mt2701-eth",
879 "syscon";
880 reg = <0 0x1b100000 0 0x20000>;
881 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
882 <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
883 <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
884 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
885 <ðsys CLK_ETHSYS_ESW>,
886 <ðsys CLK_ETHSYS_GP1>,
887 <ðsys CLK_ETHSYS_GP2>,
888 <&apmixedsys CLK_APMIXED_TRGPLL>;
889 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
890 resets = <ðsys MT2701_ETHSYS_FE_RST>,
891 <ðsys MT2701_ETHSYS_GMAC_RST>,
892 <ðsys MT2701_ETHSYS_PPE_RST>;
893 reset-names = "fe", "gmac", "ppe";
894 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
895 mediatek,ethsys = <ðsys>;
896 mediatek,pctl = <&syscfg_pctl_a>;
897 #address-cells = <1>;
898 #size-cells = <0>;
899 status = "disabled";
900 };
901
902 crypto: crypto@1b240000 {
903 compatible = "mediatek,eip97-crypto";
904 reg = <0 0x1b240000 0 0x20000>;
905 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
906 <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
907 <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
908 <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
909 <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
910 clocks = <ðsys CLK_ETHSYS_CRYPTO>;
911 clock-names = "cryp";
912 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
913 status = "disabled";
914 };
915};
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (c) 2017-2018 MediaTek Inc.
4 * Author: John Crispin <john@phrozen.org>
5 * Sean Wang <sean.wang@mediatek.com>
6 * Ryder Lee <ryder.lee@mediatek.com>
7 *
8 */
9
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12#include <dt-bindings/clock/mt2701-clk.h>
13#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
14#include <dt-bindings/power/mt2701-power.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/phy/phy.h>
17#include <dt-bindings/memory/mt2701-larb-port.h>
18#include <dt-bindings/reset/mt2701-resets.h>
19#include <dt-bindings/thermal/thermal.h>
20
21/ {
22 compatible = "mediatek,mt7623";
23 interrupt-parent = <&sysirq>;
24 #address-cells = <2>;
25 #size-cells = <2>;
26
27 cpu_opp_table: opp-table {
28 compatible = "operating-points-v2";
29 opp-shared;
30
31 opp-98000000 {
32 opp-hz = /bits/ 64 <98000000>;
33 opp-microvolt = <1050000>;
34 };
35
36 opp-198000000 {
37 opp-hz = /bits/ 64 <198000000>;
38 opp-microvolt = <1050000>;
39 };
40
41 opp-398000000 {
42 opp-hz = /bits/ 64 <398000000>;
43 opp-microvolt = <1050000>;
44 };
45
46 opp-598000000 {
47 opp-hz = /bits/ 64 <598000000>;
48 opp-microvolt = <1050000>;
49 };
50
51 opp-747500000 {
52 opp-hz = /bits/ 64 <747500000>;
53 opp-microvolt = <1050000>;
54 };
55
56 opp-1040000000 {
57 opp-hz = /bits/ 64 <1040000000>;
58 opp-microvolt = <1150000>;
59 };
60
61 opp-1196000000 {
62 opp-hz = /bits/ 64 <1196000000>;
63 opp-microvolt = <1200000>;
64 };
65
66 opp-1300000000 {
67 opp-hz = /bits/ 64 <1300000000>;
68 opp-microvolt = <1300000>;
69 };
70 };
71
72 cpus {
73 #address-cells = <1>;
74 #size-cells = <0>;
75 enable-method = "mediatek,mt6589-smp";
76
77 cpu0: cpu@0 {
78 device_type = "cpu";
79 compatible = "arm,cortex-a7";
80 reg = <0x0>;
81 clocks = <&infracfg CLK_INFRA_CPUSEL>,
82 <&apmixedsys CLK_APMIXED_MAINPLL>;
83 clock-names = "cpu", "intermediate";
84 operating-points-v2 = <&cpu_opp_table>;
85 #cooling-cells = <2>;
86 clock-frequency = <1300000000>;
87 };
88
89 cpu1: cpu@1 {
90 device_type = "cpu";
91 compatible = "arm,cortex-a7";
92 reg = <0x1>;
93 clocks = <&infracfg CLK_INFRA_CPUSEL>,
94 <&apmixedsys CLK_APMIXED_MAINPLL>;
95 clock-names = "cpu", "intermediate";
96 operating-points-v2 = <&cpu_opp_table>;
97 #cooling-cells = <2>;
98 clock-frequency = <1300000000>;
99 };
100
101 cpu2: cpu@2 {
102 device_type = "cpu";
103 compatible = "arm,cortex-a7";
104 reg = <0x2>;
105 clocks = <&infracfg CLK_INFRA_CPUSEL>,
106 <&apmixedsys CLK_APMIXED_MAINPLL>;
107 clock-names = "cpu", "intermediate";
108 operating-points-v2 = <&cpu_opp_table>;
109 #cooling-cells = <2>;
110 clock-frequency = <1300000000>;
111 };
112
113 cpu3: cpu@3 {
114 device_type = "cpu";
115 compatible = "arm,cortex-a7";
116 reg = <0x3>;
117 clocks = <&infracfg CLK_INFRA_CPUSEL>,
118 <&apmixedsys CLK_APMIXED_MAINPLL>;
119 clock-names = "cpu", "intermediate";
120 operating-points-v2 = <&cpu_opp_table>;
121 #cooling-cells = <2>;
122 clock-frequency = <1300000000>;
123 };
124 };
125
126 pmu {
127 compatible = "arm,cortex-a7-pmu";
128 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_LOW>,
129 <GIC_SPI 5 IRQ_TYPE_LEVEL_LOW>,
130 <GIC_SPI 6 IRQ_TYPE_LEVEL_LOW>,
131 <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
132 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
133 };
134
135 system_clk: dummy13m {
136 compatible = "fixed-clock";
137 clock-frequency = <13000000>;
138 #clock-cells = <0>;
139 };
140
141 rtc32k: oscillator-1 {
142 compatible = "fixed-clock";
143 #clock-cells = <0>;
144 clock-frequency = <32000>;
145 clock-output-names = "rtc32k";
146 };
147
148 clk26m: oscillator-0 {
149 compatible = "fixed-clock";
150 #clock-cells = <0>;
151 clock-frequency = <26000000>;
152 clock-output-names = "clk26m";
153 };
154
155 thermal-zones {
156 cpu_thermal: cpu-thermal {
157 polling-delay-passive = <1000>;
158 polling-delay = <1000>;
159
160 thermal-sensors = <&thermal 0>;
161
162 trips {
163 cpu_passive: cpu-passive {
164 temperature = <47000>;
165 hysteresis = <2000>;
166 type = "passive";
167 };
168
169 cpu_active: cpu-active {
170 temperature = <67000>;
171 hysteresis = <2000>;
172 type = "active";
173 };
174
175 cpu_hot: cpu-hot {
176 temperature = <87000>;
177 hysteresis = <2000>;
178 type = "hot";
179 };
180
181 cpu-crit {
182 temperature = <107000>;
183 hysteresis = <2000>;
184 type = "critical";
185 };
186 };
187
188 cooling-maps {
189 map0 {
190 trip = <&cpu_passive>;
191 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
192 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
193 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
194 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
195 };
196
197 map1 {
198 trip = <&cpu_active>;
199 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
200 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
201 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
202 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
203 };
204
205 map2 {
206 trip = <&cpu_hot>;
207 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
208 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
209 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
210 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
211 };
212 };
213 };
214 };
215
216 timer {
217 compatible = "arm,armv7-timer";
218 interrupt-parent = <&gic>;
219 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
220 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
221 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
222 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
223 clock-frequency = <13000000>;
224 arm,cpu-registers-not-fw-configured;
225 };
226
227 topckgen: syscon@10000000 {
228 compatible = "mediatek,mt7623-topckgen",
229 "mediatek,mt2701-topckgen",
230 "syscon";
231 reg = <0 0x10000000 0 0x1000>;
232 #clock-cells = <1>;
233 };
234
235 infracfg: syscon@10001000 {
236 compatible = "mediatek,mt7623-infracfg",
237 "mediatek,mt2701-infracfg",
238 "syscon";
239 reg = <0 0x10001000 0 0x1000>;
240 #clock-cells = <1>;
241 #reset-cells = <1>;
242 };
243
244 pericfg: syscon@10003000 {
245 compatible = "mediatek,mt7623-pericfg",
246 "mediatek,mt2701-pericfg",
247 "syscon";
248 reg = <0 0x10003000 0 0x1000>;
249 #clock-cells = <1>;
250 #reset-cells = <1>;
251 };
252
253 pio: pinctrl@10005000 {
254 compatible = "mediatek,mt7623-pinctrl";
255 reg = <0 0x1000b000 0 0x1000>;
256 mediatek,pctl-regmap = <&syscfg_pctl_a>;
257 pins-are-numbered;
258 gpio-controller;
259 #gpio-cells = <2>;
260 interrupt-controller;
261 interrupt-parent = <&gic>;
262 #interrupt-cells = <2>;
263 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
265 };
266
267 syscfg_pctl_a: syscfg@10005000 {
268 compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
269 reg = <0 0x10005000 0 0x1000>;
270 };
271
272 scpsys: power-controller@10006000 {
273 compatible = "mediatek,mt7623-scpsys",
274 "mediatek,mt2701-scpsys",
275 "syscon";
276 #power-domain-cells = <1>;
277 reg = <0 0x10006000 0 0x1000>;
278 infracfg = <&infracfg>;
279 clocks = <&topckgen CLK_TOP_MM_SEL>,
280 <&topckgen CLK_TOP_MFG_SEL>,
281 <&topckgen CLK_TOP_ETHIF_SEL>;
282 clock-names = "mm", "mfg", "ethif";
283 };
284
285 watchdog: watchdog@10007000 {
286 compatible = "mediatek,mt7623-wdt",
287 "mediatek,mt6589-wdt";
288 reg = <0 0x10007000 0 0x100>;
289 };
290
291 timer: timer@10008000 {
292 compatible = "mediatek,mt7623-timer",
293 "mediatek,mt6577-timer";
294 reg = <0 0x10008000 0 0x80>;
295 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
296 clocks = <&system_clk>, <&rtc32k>;
297 clock-names = "system-clk", "rtc-clk";
298 };
299
300 smi_common: smi@1000c000 {
301 compatible = "mediatek,mt7623-smi-common",
302 "mediatek,mt2701-smi-common";
303 reg = <0 0x1000c000 0 0x1000>;
304 clocks = <&infracfg CLK_INFRA_SMI>,
305 <&mmsys CLK_MM_SMI_COMMON>,
306 <&infracfg CLK_INFRA_SMI>;
307 clock-names = "apb", "smi", "async";
308 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
309 };
310
311 pwrap: pwrap@1000d000 {
312 compatible = "mediatek,mt7623-pwrap",
313 "mediatek,mt2701-pwrap";
314 reg = <0 0x1000d000 0 0x1000>;
315 reg-names = "pwrap";
316 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
317 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
318 reset-names = "pwrap";
319 clocks = <&infracfg CLK_INFRA_PMICSPI>,
320 <&infracfg CLK_INFRA_PMICWRAP>;
321 clock-names = "spi", "wrap";
322 };
323
324 cir: cir@10013000 {
325 compatible = "mediatek,mt7623-cir";
326 reg = <0 0x10013000 0 0x1000>;
327 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
328 clocks = <&infracfg CLK_INFRA_IRRX>;
329 clock-names = "clk";
330 status = "disabled";
331 };
332
333 sysirq: interrupt-controller@10200100 {
334 compatible = "mediatek,mt7623-sysirq",
335 "mediatek,mt6577-sysirq";
336 interrupt-controller;
337 #interrupt-cells = <3>;
338 interrupt-parent = <&gic>;
339 reg = <0 0x10200100 0 0x1c>;
340 };
341
342 iommu: mmsys_iommu@10205000 {
343 compatible = "mediatek,mt7623-m4u",
344 "mediatek,mt2701-m4u";
345 reg = <0 0x10205000 0 0x1000>;
346 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
347 clocks = <&infracfg CLK_INFRA_M4U>;
348 clock-names = "bclk";
349 mediatek,larbs = <&larb0 &larb1 &larb2>;
350 #iommu-cells = <1>;
351 };
352
353 efuse: efuse@10206000 {
354 compatible = "mediatek,mt7623-efuse",
355 "mediatek,mt8173-efuse";
356 reg = <0 0x10206000 0 0x1000>;
357 #address-cells = <1>;
358 #size-cells = <1>;
359 thermal_calibration_data: calib@424 {
360 reg = <0x424 0xc>;
361 };
362 };
363
364 apmixedsys: syscon@10209000 {
365 compatible = "mediatek,mt7623-apmixedsys",
366 "mediatek,mt2701-apmixedsys",
367 "syscon";
368 reg = <0 0x10209000 0 0x1000>;
369 #clock-cells = <1>;
370 };
371
372 rng: rng@1020f000 {
373 compatible = "mediatek,mt7623-rng";
374 reg = <0 0x1020f000 0 0x1000>;
375 clocks = <&infracfg CLK_INFRA_TRNG>;
376 clock-names = "rng";
377 };
378
379 gic: interrupt-controller@10211000 {
380 compatible = "arm,cortex-a7-gic";
381 interrupt-controller;
382 #interrupt-cells = <3>;
383 interrupt-parent = <&gic>;
384 reg = <0 0x10211000 0 0x1000>,
385 <0 0x10212000 0 0x2000>,
386 <0 0x10214000 0 0x2000>,
387 <0 0x10216000 0 0x2000>;
388 };
389
390 auxadc: adc@11001000 {
391 compatible = "mediatek,mt7623-auxadc",
392 "mediatek,mt2701-auxadc";
393 reg = <0 0x11001000 0 0x1000>;
394 clocks = <&pericfg CLK_PERI_AUXADC>;
395 clock-names = "main";
396 #io-channel-cells = <1>;
397 };
398
399 uart0: serial@11002000 {
400 compatible = "mediatek,mt7623-uart",
401 "mediatek,mt6577-uart";
402 reg = <0 0x11002000 0 0x400>;
403 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
404 clocks = <&pericfg CLK_PERI_UART0_SEL>,
405 <&pericfg CLK_PERI_UART0>;
406 clock-names = "baud", "bus";
407 status = "disabled";
408 };
409
410 uart1: serial@11003000 {
411 compatible = "mediatek,mt7623-uart",
412 "mediatek,mt6577-uart";
413 reg = <0 0x11003000 0 0x400>;
414 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
415 clocks = <&pericfg CLK_PERI_UART1_SEL>,
416 <&pericfg CLK_PERI_UART1>;
417 clock-names = "baud", "bus";
418 status = "disabled";
419 };
420
421 uart2: serial@11004000 {
422 compatible = "mediatek,mt7623-uart",
423 "mediatek,mt6577-uart";
424 reg = <0 0x11004000 0 0x400>;
425 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
426 clocks = <&pericfg CLK_PERI_UART2_SEL>,
427 <&pericfg CLK_PERI_UART2>;
428 clock-names = "baud", "bus";
429 status = "disabled";
430 };
431
432 uart3: serial@11005000 {
433 compatible = "mediatek,mt7623-uart",
434 "mediatek,mt6577-uart";
435 reg = <0 0x11005000 0 0x400>;
436 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
437 clocks = <&pericfg CLK_PERI_UART3_SEL>,
438 <&pericfg CLK_PERI_UART3>;
439 clock-names = "baud", "bus";
440 status = "disabled";
441 };
442
443 pwm: pwm@11006000 {
444 compatible = "mediatek,mt7623-pwm";
445 reg = <0 0x11006000 0 0x1000>;
446 #pwm-cells = <2>;
447 clocks = <&topckgen CLK_TOP_PWM_SEL>,
448 <&pericfg CLK_PERI_PWM>,
449 <&pericfg CLK_PERI_PWM1>,
450 <&pericfg CLK_PERI_PWM2>,
451 <&pericfg CLK_PERI_PWM3>,
452 <&pericfg CLK_PERI_PWM4>,
453 <&pericfg CLK_PERI_PWM5>;
454 clock-names = "top", "main", "pwm1", "pwm2",
455 "pwm3", "pwm4", "pwm5";
456 status = "disabled";
457 };
458
459 i2c0: i2c@11007000 {
460 compatible = "mediatek,mt7623-i2c",
461 "mediatek,mt6577-i2c";
462 reg = <0 0x11007000 0 0x70>,
463 <0 0x11000200 0 0x80>;
464 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
465 clock-div = <16>;
466 clocks = <&pericfg CLK_PERI_I2C0>,
467 <&pericfg CLK_PERI_AP_DMA>;
468 clock-names = "main", "dma";
469 #address-cells = <1>;
470 #size-cells = <0>;
471 status = "disabled";
472 };
473
474 i2c1: i2c@11008000 {
475 compatible = "mediatek,mt7623-i2c",
476 "mediatek,mt6577-i2c";
477 reg = <0 0x11008000 0 0x70>,
478 <0 0x11000280 0 0x80>;
479 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
480 clock-div = <16>;
481 clocks = <&pericfg CLK_PERI_I2C1>,
482 <&pericfg CLK_PERI_AP_DMA>;
483 clock-names = "main", "dma";
484 #address-cells = <1>;
485 #size-cells = <0>;
486 status = "disabled";
487 };
488
489 i2c2: i2c@11009000 {
490 compatible = "mediatek,mt7623-i2c",
491 "mediatek,mt6577-i2c";
492 reg = <0 0x11009000 0 0x70>,
493 <0 0x11000300 0 0x80>;
494 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
495 clock-div = <16>;
496 clocks = <&pericfg CLK_PERI_I2C2>,
497 <&pericfg CLK_PERI_AP_DMA>;
498 clock-names = "main", "dma";
499 #address-cells = <1>;
500 #size-cells = <0>;
501 status = "disabled";
502 };
503
504 spi0: spi@1100a000 {
505 compatible = "mediatek,mt7623-spi",
506 "mediatek,mt2701-spi";
507 #address-cells = <1>;
508 #size-cells = <0>;
509 reg = <0 0x1100a000 0 0x100>;
510 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
511 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
512 <&topckgen CLK_TOP_SPI0_SEL>,
513 <&pericfg CLK_PERI_SPI0>;
514 clock-names = "parent-clk", "sel-clk", "spi-clk";
515 status = "disabled";
516 };
517
518 thermal: thermal@1100b000 {
519 #thermal-sensor-cells = <1>;
520 compatible = "mediatek,mt7623-thermal",
521 "mediatek,mt2701-thermal";
522 reg = <0 0x1100b000 0 0x1000>;
523 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>;
524 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
525 clock-names = "therm", "auxadc";
526 resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
527 reset-names = "therm";
528 mediatek,auxadc = <&auxadc>;
529 mediatek,apmixedsys = <&apmixedsys>;
530 nvmem-cells = <&thermal_calibration_data>;
531 nvmem-cell-names = "calibration-data";
532 };
533
534 btif: serial@1100c000 {
535 compatible = "mediatek,mt7623-btif",
536 "mediatek,mtk-btif";
537 reg = <0 0x1100c000 0 0x1000>;
538 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_LOW>;
539 clocks = <&pericfg CLK_PERI_BTIF>;
540 clock-names = "main";
541 reg-shift = <2>;
542 reg-io-width = <4>;
543 status = "disabled";
544 };
545
546 nandc: nfi@1100d000 {
547 compatible = "mediatek,mt7623-nfc",
548 "mediatek,mt2701-nfc";
549 reg = <0 0x1100d000 0 0x1000>;
550 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
551 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
552 clocks = <&pericfg CLK_PERI_NFI>,
553 <&pericfg CLK_PERI_NFI_PAD>;
554 clock-names = "nfi_clk", "pad_clk";
555 status = "disabled";
556 ecc-engine = <&bch>;
557 #address-cells = <1>;
558 #size-cells = <0>;
559 };
560
561 bch: ecc@1100e000 {
562 compatible = "mediatek,mt7623-ecc",
563 "mediatek,mt2701-ecc";
564 reg = <0 0x1100e000 0 0x1000>;
565 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
566 clocks = <&pericfg CLK_PERI_NFI_ECC>;
567 clock-names = "nfiecc_clk";
568 status = "disabled";
569 };
570
571 nor_flash: spi@11014000 {
572 compatible = "mediatek,mt7623-nor",
573 "mediatek,mt8173-nor";
574 reg = <0 0x11014000 0 0x1000>;
575 clocks = <&pericfg CLK_PERI_FLASH>,
576 <&topckgen CLK_TOP_FLASH_SEL>;
577 clock-names = "spi", "sf";
578 #address-cells = <1>;
579 #size-cells = <0>;
580 status = "disabled";
581 };
582
583 spi1: spi@11016000 {
584 compatible = "mediatek,mt7623-spi",
585 "mediatek,mt2701-spi";
586 #address-cells = <1>;
587 #size-cells = <0>;
588 reg = <0 0x11016000 0 0x100>;
589 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
590 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
591 <&topckgen CLK_TOP_SPI1_SEL>,
592 <&pericfg CLK_PERI_SPI1>;
593 clock-names = "parent-clk", "sel-clk", "spi-clk";
594 status = "disabled";
595 };
596
597 spi2: spi@11017000 {
598 compatible = "mediatek,mt7623-spi",
599 "mediatek,mt2701-spi";
600 #address-cells = <1>;
601 #size-cells = <0>;
602 reg = <0 0x11017000 0 0x1000>;
603 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
604 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
605 <&topckgen CLK_TOP_SPI2_SEL>,
606 <&pericfg CLK_PERI_SPI2>;
607 clock-names = "parent-clk", "sel-clk", "spi-clk";
608 status = "disabled";
609 };
610
611 audsys: clock-controller@11220000 {
612 compatible = "mediatek,mt7623-audsys",
613 "mediatek,mt2701-audsys",
614 "syscon";
615 reg = <0 0x11220000 0 0x2000>;
616 #clock-cells = <1>;
617
618 afe: audio-controller {
619 compatible = "mediatek,mt7623-audio",
620 "mediatek,mt2701-audio";
621 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
622 <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
623 interrupt-names = "afe", "asys";
624 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
625
626 clocks = <&infracfg CLK_INFRA_AUDIO>,
627 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
628 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
629 <&topckgen CLK_TOP_AUD_48K_TIMING>,
630 <&topckgen CLK_TOP_AUD_44K_TIMING>,
631 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
632 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
633 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
634 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
635 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
636 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
637 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
638 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
639 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
640 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
641 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
642 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
643 <&audsys CLK_AUD_I2SO1>,
644 <&audsys CLK_AUD_I2SO2>,
645 <&audsys CLK_AUD_I2SO3>,
646 <&audsys CLK_AUD_I2SO4>,
647 <&audsys CLK_AUD_I2SIN1>,
648 <&audsys CLK_AUD_I2SIN2>,
649 <&audsys CLK_AUD_I2SIN3>,
650 <&audsys CLK_AUD_I2SIN4>,
651 <&audsys CLK_AUD_ASRCO1>,
652 <&audsys CLK_AUD_ASRCO2>,
653 <&audsys CLK_AUD_ASRCO3>,
654 <&audsys CLK_AUD_ASRCO4>,
655 <&audsys CLK_AUD_AFE>,
656 <&audsys CLK_AUD_AFE_CONN>,
657 <&audsys CLK_AUD_A1SYS>,
658 <&audsys CLK_AUD_A2SYS>,
659 <&audsys CLK_AUD_AFE_MRGIF>;
660
661 clock-names = "infra_sys_audio_clk",
662 "top_audio_mux1_sel",
663 "top_audio_mux2_sel",
664 "top_audio_a1sys_hp",
665 "top_audio_a2sys_hp",
666 "i2s0_src_sel",
667 "i2s1_src_sel",
668 "i2s2_src_sel",
669 "i2s3_src_sel",
670 "i2s0_src_div",
671 "i2s1_src_div",
672 "i2s2_src_div",
673 "i2s3_src_div",
674 "i2s0_mclk_en",
675 "i2s1_mclk_en",
676 "i2s2_mclk_en",
677 "i2s3_mclk_en",
678 "i2so0_hop_ck",
679 "i2so1_hop_ck",
680 "i2so2_hop_ck",
681 "i2so3_hop_ck",
682 "i2si0_hop_ck",
683 "i2si1_hop_ck",
684 "i2si2_hop_ck",
685 "i2si3_hop_ck",
686 "asrc0_out_ck",
687 "asrc1_out_ck",
688 "asrc2_out_ck",
689 "asrc3_out_ck",
690 "audio_afe_pd",
691 "audio_afe_conn_pd",
692 "audio_a1sys_pd",
693 "audio_a2sys_pd",
694 "audio_mrgif_pd";
695
696 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
697 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
698 <&topckgen CLK_TOP_AUD_MUX1_DIV>,
699 <&topckgen CLK_TOP_AUD_MUX2_DIV>;
700 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
701 <&topckgen CLK_TOP_AUD2PLL_90M>;
702 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
703 };
704 };
705
706 mmc0: mmc@11230000 {
707 compatible = "mediatek,mt7623-mmc",
708 "mediatek,mt2701-mmc";
709 reg = <0 0x11230000 0 0x1000>;
710 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
711 clocks = <&pericfg CLK_PERI_MSDC30_0>,
712 <&topckgen CLK_TOP_MSDC30_0_SEL>;
713 clock-names = "source", "hclk";
714 status = "disabled";
715 };
716
717 mmc1: mmc@11240000 {
718 compatible = "mediatek,mt7623-mmc",
719 "mediatek,mt2701-mmc";
720 reg = <0 0x11240000 0 0x1000>;
721 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_LOW>;
722 clocks = <&pericfg CLK_PERI_MSDC30_1>,
723 <&topckgen CLK_TOP_MSDC30_1_SEL>;
724 clock-names = "source", "hclk";
725 status = "disabled";
726 };
727
728 g3dsys: syscon@13000000 {
729 compatible = "mediatek,mt7623-g3dsys",
730 "mediatek,mt2701-g3dsys",
731 "syscon";
732 reg = <0 0x13000000 0 0x200>;
733 #clock-cells = <1>;
734 #reset-cells = <1>;
735 };
736
737 mali: gpu@13040000 {
738 compatible = "mediatek,mt7623-mali", "arm,mali-450";
739 reg = <0 0x13040000 0 0x30000>;
740 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>,
741 <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>,
742 <GIC_SPI 172 IRQ_TYPE_LEVEL_LOW>,
743 <GIC_SPI 173 IRQ_TYPE_LEVEL_LOW>,
744 <GIC_SPI 174 IRQ_TYPE_LEVEL_LOW>,
745 <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>,
746 <GIC_SPI 176 IRQ_TYPE_LEVEL_LOW>,
747 <GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>,
748 <GIC_SPI 178 IRQ_TYPE_LEVEL_LOW>,
749 <GIC_SPI 179 IRQ_TYPE_LEVEL_LOW>,
750 <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
751 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1",
752 "ppmmu1", "pp2", "ppmmu2", "pp3", "ppmmu3",
753 "pp";
754 clocks = <&topckgen CLK_TOP_MMPLL>,
755 <&g3dsys CLK_G3DSYS_CORE>;
756 clock-names = "bus", "core";
757 power-domains = <&scpsys MT2701_POWER_DOMAIN_MFG>;
758 resets = <&g3dsys MT2701_G3DSYS_CORE_RST>;
759 };
760
761 mmsys: syscon@14000000 {
762 compatible = "mediatek,mt7623-mmsys",
763 "mediatek,mt2701-mmsys",
764 "syscon";
765 reg = <0 0x14000000 0 0x1000>;
766 #clock-cells = <1>;
767 };
768
769 larb0: larb@14010000 {
770 compatible = "mediatek,mt7623-smi-larb",
771 "mediatek,mt2701-smi-larb";
772 reg = <0 0x14010000 0 0x1000>;
773 mediatek,smi = <&smi_common>;
774 mediatek,larb-id = <0>;
775 clocks = <&mmsys CLK_MM_SMI_LARB0>,
776 <&mmsys CLK_MM_SMI_LARB0>;
777 clock-names = "apb", "smi";
778 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
779 };
780
781 imgsys: syscon@15000000 {
782 compatible = "mediatek,mt7623-imgsys",
783 "mediatek,mt2701-imgsys",
784 "syscon";
785 reg = <0 0x15000000 0 0x1000>;
786 #clock-cells = <1>;
787 };
788
789 larb2: larb@15001000 {
790 compatible = "mediatek,mt7623-smi-larb",
791 "mediatek,mt2701-smi-larb";
792 reg = <0 0x15001000 0 0x1000>;
793 mediatek,smi = <&smi_common>;
794 mediatek,larb-id = <2>;
795 clocks = <&imgsys CLK_IMG_SMI_COMM>,
796 <&imgsys CLK_IMG_SMI_COMM>;
797 clock-names = "apb", "smi";
798 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
799 };
800
801 jpegdec: jpegdec@15004000 {
802 compatible = "mediatek,mt7623-jpgdec",
803 "mediatek,mt2701-jpgdec";
804 reg = <0 0x15004000 0 0x1000>;
805 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
806 clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
807 <&imgsys CLK_IMG_JPGDEC>;
808 clock-names = "jpgdec-smi",
809 "jpgdec";
810 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
811 mediatek,larb = <&larb2>;
812 iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
813 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
814 };
815
816 vdecsys: syscon@16000000 {
817 compatible = "mediatek,mt7623-vdecsys",
818 "mediatek,mt2701-vdecsys",
819 "syscon";
820 reg = <0 0x16000000 0 0x1000>;
821 #clock-cells = <1>;
822 };
823
824 larb1: larb@16010000 {
825 compatible = "mediatek,mt7623-smi-larb",
826 "mediatek,mt2701-smi-larb";
827 reg = <0 0x16010000 0 0x1000>;
828 mediatek,smi = <&smi_common>;
829 mediatek,larb-id = <1>;
830 clocks = <&vdecsys CLK_VDEC_CKGEN>,
831 <&vdecsys CLK_VDEC_LARB>;
832 clock-names = "apb", "smi";
833 power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
834 };
835
836 hifsys: syscon@1a000000 {
837 compatible = "mediatek,mt7623-hifsys",
838 "mediatek,mt2701-hifsys",
839 "syscon";
840 reg = <0 0x1a000000 0 0x1000>;
841 #clock-cells = <1>;
842 #reset-cells = <1>;
843 };
844
845 pcie: pcie@1a140000 {
846 compatible = "mediatek,mt7623-pcie";
847 device_type = "pci";
848 reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
849 <0 0x1a142000 0 0x1000>, /* Port0 registers */
850 <0 0x1a143000 0 0x1000>, /* Port1 registers */
851 <0 0x1a144000 0 0x1000>; /* Port2 registers */
852 reg-names = "subsys", "port0", "port1", "port2";
853 #address-cells = <3>;
854 #size-cells = <2>;
855 #interrupt-cells = <1>;
856 interrupt-map-mask = <0xf800 0 0 0>;
857 interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
858 <0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
859 <0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
860 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
861 <&hifsys CLK_HIFSYS_PCIE0>,
862 <&hifsys CLK_HIFSYS_PCIE1>,
863 <&hifsys CLK_HIFSYS_PCIE2>;
864 clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
865 resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
866 <&hifsys MT2701_HIFSYS_PCIE1_RST>,
867 <&hifsys MT2701_HIFSYS_PCIE2_RST>;
868 reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
869 phys = <&pcie0_port PHY_TYPE_PCIE>,
870 <&pcie1_port PHY_TYPE_PCIE>,
871 <&u3port1 PHY_TYPE_PCIE>;
872 phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
873 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
874 bus-range = <0x00 0xff>;
875 status = "disabled";
876 ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
877 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;
878
879 pcie@0,0 {
880 reg = <0x0000 0 0 0 0>;
881 #address-cells = <3>;
882 #size-cells = <2>;
883 #interrupt-cells = <1>;
884 interrupt-map-mask = <0 0 0 0>;
885 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
886 ranges;
887 status = "disabled";
888 };
889
890 pcie@1,0 {
891 reg = <0x0800 0 0 0 0>;
892 #address-cells = <3>;
893 #size-cells = <2>;
894 #interrupt-cells = <1>;
895 interrupt-map-mask = <0 0 0 0>;
896 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
897 ranges;
898 status = "disabled";
899 };
900
901 pcie@2,0 {
902 reg = <0x1000 0 0 0 0>;
903 #address-cells = <3>;
904 #size-cells = <2>;
905 #interrupt-cells = <1>;
906 interrupt-map-mask = <0 0 0 0>;
907 interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
908 ranges;
909 status = "disabled";
910 };
911 };
912
913 pcie0_phy: pcie-phy@1a149000 {
914 compatible = "mediatek,generic-tphy-v1";
915 reg = <0 0x1a149000 0 0x0700>;
916 #address-cells = <2>;
917 #size-cells = <2>;
918 ranges;
919 status = "disabled";
920
921 pcie0_port: pcie-phy@1a149900 {
922 reg = <0 0x1a149900 0 0x0700>;
923 clocks = <&clk26m>;
924 clock-names = "ref";
925 #phy-cells = <1>;
926 status = "okay";
927 };
928 };
929
930 pcie1_phy: pcie-phy@1a14a000 {
931 compatible = "mediatek,generic-tphy-v1";
932 reg = <0 0x1a14a000 0 0x0700>;
933 #address-cells = <2>;
934 #size-cells = <2>;
935 ranges;
936 status = "disabled";
937
938 pcie1_port: pcie-phy@1a14a900 {
939 reg = <0 0x1a14a900 0 0x0700>;
940 clocks = <&clk26m>;
941 clock-names = "ref";
942 #phy-cells = <1>;
943 status = "okay";
944 };
945 };
946
947 usb1: usb@1a1c0000 {
948 compatible = "mediatek,mt7623-xhci",
949 "mediatek,mt8173-xhci";
950 reg = <0 0x1a1c0000 0 0x1000>,
951 <0 0x1a1c4700 0 0x0100>;
952 reg-names = "mac", "ippc";
953 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
954 clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
955 <&topckgen CLK_TOP_ETHIF_SEL>;
956 clock-names = "sys_ck", "ref_ck";
957 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
958 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
959 status = "disabled";
960 };
961
962 u3phy1: usb-phy@1a1c4000 {
963 compatible = "mediatek,mt7623-u3phy",
964 "mediatek,mt2701-u3phy";
965 reg = <0 0x1a1c4000 0 0x0700>;
966 #address-cells = <2>;
967 #size-cells = <2>;
968 ranges;
969 status = "disabled";
970
971 u2port0: usb-phy@1a1c4800 {
972 reg = <0 0x1a1c4800 0 0x0100>;
973 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
974 clock-names = "ref";
975 #phy-cells = <1>;
976 status = "okay";
977 };
978
979 u3port0: usb-phy@1a1c4900 {
980 reg = <0 0x1a1c4900 0 0x0700>;
981 clocks = <&clk26m>;
982 clock-names = "ref";
983 #phy-cells = <1>;
984 status = "okay";
985 };
986 };
987
988 usb2: usb@1a240000 {
989 compatible = "mediatek,mt7623-xhci",
990 "mediatek,mt8173-xhci";
991 reg = <0 0x1a240000 0 0x1000>,
992 <0 0x1a244700 0 0x0100>;
993 reg-names = "mac", "ippc";
994 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
995 clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
996 <&topckgen CLK_TOP_ETHIF_SEL>;
997 clock-names = "sys_ck", "ref_ck";
998 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
999 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
1000 status = "disabled";
1001 };
1002
1003 u3phy2: usb-phy@1a244000 {
1004 compatible = "mediatek,mt7623-u3phy",
1005 "mediatek,mt2701-u3phy";
1006 reg = <0 0x1a244000 0 0x0700>;
1007 #address-cells = <2>;
1008 #size-cells = <2>;
1009 ranges;
1010 status = "disabled";
1011
1012 u2port1: usb-phy@1a244800 {
1013 reg = <0 0x1a244800 0 0x0100>;
1014 clocks = <&topckgen CLK_TOP_USB_PHY48M>;
1015 clock-names = "ref";
1016 #phy-cells = <1>;
1017 status = "okay";
1018 };
1019
1020 u3port1: usb-phy@1a244900 {
1021 reg = <0 0x1a244900 0 0x0700>;
1022 clocks = <&clk26m>;
1023 clock-names = "ref";
1024 #phy-cells = <1>;
1025 status = "okay";
1026 };
1027 };
1028
1029 ethsys: syscon@1b000000 {
1030 compatible = "mediatek,mt7623-ethsys",
1031 "mediatek,mt2701-ethsys",
1032 "syscon";
1033 reg = <0 0x1b000000 0 0x1000>;
1034 #clock-cells = <1>;
1035 #reset-cells = <1>;
1036 };
1037
1038 hsdma: dma-controller@1b007000 {
1039 compatible = "mediatek,mt7623-hsdma";
1040 reg = <0 0x1b007000 0 0x1000>;
1041 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>;
1042 clocks = <ðsys CLK_ETHSYS_HSDMA>;
1043 clock-names = "hsdma";
1044 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
1045 #dma-cells = <1>;
1046 };
1047
1048 eth: ethernet@1b100000 {
1049 compatible = "mediatek,mt7623-eth",
1050 "mediatek,mt2701-eth",
1051 "syscon";
1052 reg = <0 0x1b100000 0 0x20000>;
1053 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
1054 <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
1055 <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
1056 clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
1057 <ðsys CLK_ETHSYS_ESW>,
1058 <ðsys CLK_ETHSYS_GP1>,
1059 <ðsys CLK_ETHSYS_GP2>,
1060 <&apmixedsys CLK_APMIXED_TRGPLL>;
1061 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
1062 resets = <ðsys MT2701_ETHSYS_FE_RST>,
1063 <ðsys MT2701_ETHSYS_GMAC_RST>,
1064 <ðsys MT2701_ETHSYS_PPE_RST>;
1065 reset-names = "fe", "gmac", "ppe";
1066 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
1067 mediatek,ethsys = <ðsys>;
1068 mediatek,pctl = <&syscfg_pctl_a>;
1069 #address-cells = <1>;
1070 #size-cells = <0>;
1071 status = "disabled";
1072 };
1073
1074 crypto: crypto@1b240000 {
1075 compatible = "mediatek,eip97-crypto";
1076 reg = <0 0x1b240000 0 0x20000>;
1077 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>,
1078 <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>,
1079 <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>,
1080 <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>,
1081 <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
1082 clocks = <ðsys CLK_ETHSYS_CRYPTO>;
1083 clock-names = "cryp";
1084 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
1085 status = "disabled";
1086 };
1087
1088 bdpsys: syscon@1c000000 {
1089 compatible = "mediatek,mt7623-bdpsys",
1090 "mediatek,mt2701-bdpsys",
1091 "syscon";
1092 reg = <0 0x1c000000 0 0x1000>;
1093 #clock-cells = <1>;
1094 };
1095};
1096
1097&pio {
1098 cir_pins_a:cir-default {
1099 pins-cir {
1100 pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
1101 bias-disable;
1102 };
1103 };
1104
1105 i2c0_pins_a: i2c0-default {
1106 pins-i2c0 {
1107 pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
1108 <MT7623_PIN_76_SCL0_FUNC_SCL0>;
1109 bias-disable;
1110 };
1111 };
1112
1113 i2c1_pins_a: i2c1-default {
1114 pin-i2c1 {
1115 pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
1116 <MT7623_PIN_58_SCL1_FUNC_SCL1>;
1117 bias-disable;
1118 };
1119 };
1120
1121 i2c1_pins_b: i2c1-alt {
1122 pin-i2c1 {
1123 pinmux = <MT7623_PIN_242_URTS2_FUNC_SCL1>,
1124 <MT7623_PIN_243_UCTS2_FUNC_SDA1>;
1125 bias-disable;
1126 };
1127 };
1128
1129 i2c2_pins_a: i2c2-default {
1130 pin-i2c2 {
1131 pinmux = <MT7623_PIN_77_SDA2_FUNC_SDA2>,
1132 <MT7623_PIN_78_SCL2_FUNC_SCL2>;
1133 bias-disable;
1134 };
1135 };
1136
1137 i2c2_pins_b: i2c2-alt {
1138 pin-i2c2 {
1139 pinmux = <MT7623_PIN_122_GPIO122_FUNC_SDA2>,
1140 <MT7623_PIN_123_HTPLG_FUNC_SCL2>;
1141 bias-disable;
1142 };
1143 };
1144
1145 i2s0_pins_a: i2s0-default {
1146 pin-i2s0 {
1147 pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
1148 <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
1149 <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
1150 <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
1151 <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
1152 drive-strength = <MTK_DRIVE_12mA>;
1153 bias-pull-down;
1154 };
1155 };
1156
1157 i2s1_pins_a: i2s1-default {
1158 pin-i2s1 {
1159 pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
1160 <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
1161 <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
1162 <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
1163 <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
1164 drive-strength = <MTK_DRIVE_12mA>;
1165 bias-pull-down;
1166 };
1167 };
1168
1169 key_pins_a: keys-alt {
1170 pins-keys {
1171 pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
1172 <MT7623_PIN_257_GPIO257_FUNC_GPIO257> ;
1173 input-enable;
1174 };
1175 };
1176
1177 led_pins_a: leds-alt {
1178 pins-leds {
1179 pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>,
1180 <MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>,
1181 <MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>;
1182 };
1183 };
1184
1185 mmc0_pins_default: mmc0default {
1186 pins-cmd-dat {
1187 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
1188 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
1189 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
1190 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
1191 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
1192 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
1193 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
1194 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
1195 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
1196 input-enable;
1197 bias-pull-up;
1198 };
1199
1200 pins-clk {
1201 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
1202 bias-pull-down;
1203 };
1204
1205 pins-rst {
1206 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
1207 bias-pull-up;
1208 };
1209 };
1210
1211 mmc0_pins_uhs: mmc0 {
1212 pins-cmd-dat {
1213 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
1214 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
1215 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
1216 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
1217 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
1218 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
1219 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
1220 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
1221 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
1222 input-enable;
1223 drive-strength = <MTK_DRIVE_2mA>;
1224 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1225 };
1226
1227 pins-clk {
1228 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
1229 drive-strength = <MTK_DRIVE_2mA>;
1230 bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
1231 };
1232
1233 pins-rst {
1234 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
1235 bias-pull-up;
1236 };
1237 };
1238
1239 mmc1_pins_default: mmc1default {
1240 pins-cmd-dat {
1241 pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
1242 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
1243 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
1244 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
1245 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
1246 input-enable;
1247 drive-strength = <MTK_DRIVE_4mA>;
1248 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1249 };
1250
1251 pins-clk {
1252 pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
1253 bias-pull-down;
1254 drive-strength = <MTK_DRIVE_4mA>;
1255 };
1256
1257 pins-wp {
1258 pinmux = <MT7623_PIN_29_EINT7_FUNC_MSDC1_WP>;
1259 input-enable;
1260 bias-pull-up;
1261 };
1262
1263 pins-insert {
1264 pinmux = <MT7623_PIN_261_MSDC1_INS_FUNC_GPIO261>;
1265 bias-pull-up;
1266 };
1267 };
1268
1269 mmc1_pins_uhs: mmc1 {
1270 pins-cmd-dat {
1271 pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
1272 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
1273 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
1274 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
1275 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
1276 input-enable;
1277 drive-strength = <MTK_DRIVE_4mA>;
1278 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1279 };
1280
1281 pins-clk {
1282 pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
1283 drive-strength = <MTK_DRIVE_4mA>;
1284 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1285 };
1286 };
1287
1288 nand_pins_default: nanddefault {
1289 pins-ale {
1290 pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>;
1291 drive-strength = <MTK_DRIVE_8mA>;
1292 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1293 };
1294
1295 pins-dat {
1296 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_NLD7>,
1297 <MT7623_PIN_112_MSDC0_DAT6_FUNC_NLD6>,
1298 <MT7623_PIN_114_MSDC0_DAT4_FUNC_NLD4>,
1299 <MT7623_PIN_118_MSDC0_DAT3_FUNC_NLD3>,
1300 <MT7623_PIN_121_MSDC0_DAT0_FUNC_NLD0>,
1301 <MT7623_PIN_120_MSDC0_DAT1_FUNC_NLD1>,
1302 <MT7623_PIN_113_MSDC0_DAT5_FUNC_NLD5>,
1303 <MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>,
1304 <MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>;
1305 input-enable;
1306 drive-strength = <MTK_DRIVE_8mA>;
1307 bias-pull-up;
1308 };
1309
1310 pins-we {
1311 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>;
1312 drive-strength = <MTK_DRIVE_8mA>;
1313 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
1314 };
1315 };
1316
1317 pcie_default: pcie_pin_default {
1318 pins_cmd_dat {
1319 pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
1320 <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
1321 bias-disable;
1322 };
1323 };
1324
1325 pwm_pins_a: pwm-default {
1326 pins-pwm {
1327 pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
1328 <MT7623_PIN_204_PWM1_FUNC_PWM1>,
1329 <MT7623_PIN_205_PWM2_FUNC_PWM2>,
1330 <MT7623_PIN_206_PWM3_FUNC_PWM3>,
1331 <MT7623_PIN_207_PWM4_FUNC_PWM4>;
1332 };
1333 };
1334
1335 spi0_pins_a: spi0-default {
1336 pins-spi {
1337 pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
1338 <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
1339 <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
1340 <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
1341 bias-disable;
1342 };
1343 };
1344
1345 spi1_pins_a: spi1-default {
1346 pins-spi {
1347 pinmux = <MT7623_PIN_7_SPI1_CSN_FUNC_SPI1_CS>,
1348 <MT7623_PIN_199_SPI1_CK_FUNC_SPI1_CK>,
1349 <MT7623_PIN_8_SPI1_MI_FUNC_SPI1_MI>,
1350 <MT7623_PIN_9_SPI1_MO_FUNC_SPI1_MO>;
1351 };
1352 };
1353
1354 spi2_pins_a: spi2-default {
1355 pins-spi {
1356 pinmux = <MT7623_PIN_101_SPI2_CSN_FUNC_SPI2_CS>,
1357 <MT7623_PIN_104_SPI2_CK_FUNC_SPI2_CK>,
1358 <MT7623_PIN_102_SPI2_MI_FUNC_SPI2_MI>,
1359 <MT7623_PIN_103_SPI2_MO_FUNC_SPI2_MO>;
1360 };
1361 };
1362
1363 uart0_pins_a: uart0-default {
1364 pins-dat {
1365 pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
1366 <MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
1367 };
1368 };
1369
1370 uart1_pins_a: uart1-default {
1371 pins-dat {
1372 pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
1373 <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
1374 };
1375 };
1376
1377 uart2_pins_a: uart2-default {
1378 pins-dat {
1379 pinmux = <MT7623_PIN_14_GPIO14_FUNC_URXD2>,
1380 <MT7623_PIN_15_GPIO15_FUNC_UTXD2>;
1381 };
1382 };
1383
1384 uart2_pins_b: uart2-alt {
1385 pins-dat {
1386 pinmux = <MT7623_PIN_200_URXD2_FUNC_URXD2>,
1387 <MT7623_PIN_201_UTXD2_FUNC_UTXD2>;
1388 };
1389 };
1390};