1menu "IRQ chip support"
  2
  3config IRQCHIP
  4	def_bool y
  5	depends on OF_IRQ
  6
  7config ARM_GIC
  8	bool
  9	select IRQ_DOMAIN
 10	select IRQ_DOMAIN_HIERARCHY
 11	select MULTI_IRQ_HANDLER
 12	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
 13
 14config ARM_GIC_PM
 15	bool
 16	depends on PM
 17	select ARM_GIC
 18	select PM_CLK
 19
 20config ARM_GIC_MAX_NR
 21	int
 
 22	default 2 if ARCH_REALVIEW
 23	default 1
 24
 25config ARM_GIC_V2M
 26	bool
 27	depends on PCI
 28	select ARM_GIC
 29	select PCI_MSI
 30
 31config GIC_NON_BANKED
 32	bool
 33
 34config ARM_GIC_V3
 35	bool
 36	select IRQ_DOMAIN
 37	select MULTI_IRQ_HANDLER
 38	select IRQ_DOMAIN_HIERARCHY
 39	select PARTITION_PERCPU
 40	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
 41
 42config ARM_GIC_V3_ITS
 43	bool
 44	select GENERIC_MSI_IRQ_DOMAIN
 45	default ARM_GIC_V3
 46
 47config ARM_GIC_V3_ITS_PCI
 48	bool
 49	depends on ARM_GIC_V3_ITS
 50	depends on PCI
 51	depends on PCI_MSI
 52	default ARM_GIC_V3_ITS
 53
 54config ARM_GIC_V3_ITS_FSL_MC
 55	bool
 56	depends on ARM_GIC_V3_ITS
 57	depends on FSL_MC_BUS
 58	default ARM_GIC_V3_ITS
 59
 60config ARM_NVIC
 61	bool
 62	select IRQ_DOMAIN
 63	select IRQ_DOMAIN_HIERARCHY
 64	select GENERIC_IRQ_CHIP
 65
 66config ARM_VIC
 67	bool
 68	select IRQ_DOMAIN
 69	select MULTI_IRQ_HANDLER
 70
 71config ARM_VIC_NR
 72	int
 73	default 4 if ARCH_S5PV210
 74	default 2
 75	depends on ARM_VIC
 76	help
 77	  The maximum number of VICs available in the system, for
 78	  power management.
 79
 80config ARMADA_370_XP_IRQ
 81	bool
 82	select GENERIC_IRQ_CHIP
 83	select PCI_MSI if PCI
 84	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
 85
 86config ALPINE_MSI
 87	bool
 88	depends on PCI
 89	select PCI_MSI
 90	select GENERIC_IRQ_CHIP
 91
 
 
 
 
 
 
 
 
 92config ATMEL_AIC_IRQ
 93	bool
 94	select GENERIC_IRQ_CHIP
 95	select IRQ_DOMAIN
 96	select MULTI_IRQ_HANDLER
 97	select SPARSE_IRQ
 98
 99config ATMEL_AIC5_IRQ
100	bool
101	select GENERIC_IRQ_CHIP
102	select IRQ_DOMAIN
103	select MULTI_IRQ_HANDLER
104	select SPARSE_IRQ
105
106config I8259
107	bool
108	select IRQ_DOMAIN
109
110config BCM6345_L1_IRQ
111	bool
112	select GENERIC_IRQ_CHIP
113	select IRQ_DOMAIN
114	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
115
116config BCM7038_L1_IRQ
117	bool
118	select GENERIC_IRQ_CHIP
119	select IRQ_DOMAIN
120	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
121
122config BCM7120_L2_IRQ
123	bool
124	select GENERIC_IRQ_CHIP
125	select IRQ_DOMAIN
126
127config BRCMSTB_L2_IRQ
128	bool
129	select GENERIC_IRQ_CHIP
130	select IRQ_DOMAIN
131
 
 
 
 
 
 
 
 
 
 
132config DW_APB_ICTL
133	bool
134	select GENERIC_IRQ_CHIP
135	select IRQ_DOMAIN
136
137config FARADAY_FTINTC010
138	bool
139	select IRQ_DOMAIN
140	select MULTI_IRQ_HANDLER
141	select SPARSE_IRQ
142
143config HISILICON_IRQ_MBIGEN
144	bool
145	select ARM_GIC_V3
146	select ARM_GIC_V3_ITS
147
148config IMGPDC_IRQ
149	bool
150	select GENERIC_IRQ_CHIP
151	select IRQ_DOMAIN
152
 
 
 
 
 
 
 
 
 
153config IRQ_MIPS_CPU
154	bool
155	select GENERIC_IRQ_CHIP
156	select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
157	select IRQ_DOMAIN
158	select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
159	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
160
161config CLPS711X_IRQCHIP
162	bool
163	depends on ARCH_CLPS711X
164	select IRQ_DOMAIN
165	select MULTI_IRQ_HANDLER
166	select SPARSE_IRQ
167	default y
168
169config OMPIC
170	bool
171
172config OR1K_PIC
173	bool
174	select IRQ_DOMAIN
175
176config OMAP_IRQCHIP
177	bool
178	select GENERIC_IRQ_CHIP
179	select IRQ_DOMAIN
180
181config ORION_IRQCHIP
182	bool
183	select IRQ_DOMAIN
184	select MULTI_IRQ_HANDLER
185
186config PIC32_EVIC
187	bool
188	select GENERIC_IRQ_CHIP
189	select IRQ_DOMAIN
190
191config JCORE_AIC
192	bool "J-Core integrated AIC" if COMPILE_TEST
193	depends on OF
194	select IRQ_DOMAIN
195	help
196	  Support for the J-Core integrated AIC.
197
198config RENESAS_INTC_IRQPIN
199	bool
200	select IRQ_DOMAIN
201
 
 
 
 
 
 
 
202config RENESAS_IRQC
203	bool
204	select GENERIC_IRQ_CHIP
205	select IRQ_DOMAIN
 
 
 
 
 
 
 
 
 
 
206
207config ST_IRQCHIP
208	bool
209	select REGMAP
210	select MFD_SYSCON
211	help
212	  Enables SysCfg Controlled IRQs on STi based platforms.
213
214config TANGO_IRQ
215	bool
216	select IRQ_DOMAIN
217	select GENERIC_IRQ_CHIP
218
219config TB10X_IRQC
220	bool
221	select IRQ_DOMAIN
222	select GENERIC_IRQ_CHIP
223
224config TS4800_IRQ
225	tristate "TS-4800 IRQ controller"
226	select IRQ_DOMAIN
227	depends on HAS_IOMEM
228	depends on SOC_IMX51 || COMPILE_TEST
229	help
230	  Support for the TS-4800 FPGA IRQ controller
231
232config VERSATILE_FPGA_IRQ
233	bool
234	select IRQ_DOMAIN
235
236config VERSATILE_FPGA_IRQ_NR
237       int
238       default 4
239       depends on VERSATILE_FPGA_IRQ
240
241config XTENSA_MX
242	bool
243	select IRQ_DOMAIN
244	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
245
246config XILINX_INTC
247	bool
248	select IRQ_DOMAIN
249
250config IRQ_CROSSBAR
251	bool
252	help
253	  Support for a CROSSBAR ip that precedes the main interrupt controller.
254	  The primary irqchip invokes the crossbar's callback which inturn allocates
255	  a free irq and configures the IP. Thus the peripheral interrupts are
256	  routed to one of the free irqchip interrupt lines.
257
258config KEYSTONE_IRQ
259	tristate "Keystone 2 IRQ controller IP"
260	depends on ARCH_KEYSTONE
261	help
262		Support for Texas Instruments Keystone 2 IRQ controller IP which
263		is part of the Keystone 2 IPC mechanism
264
265config MIPS_GIC
266	bool
267	select GENERIC_IRQ_IPI
268	select IRQ_DOMAIN_HIERARCHY
269	select MIPS_CM
270
271config INGENIC_IRQ
272	bool
273	depends on MACH_INGENIC
274	default y
275
 
 
 
 
 
 
 
 
 
 
 
 
276config RENESAS_H8300H_INTC
277        bool
278	select IRQ_DOMAIN
279
280config RENESAS_H8S_INTC
281        bool
282	select IRQ_DOMAIN
 
 
 
283
284config IMX_GPCV2
285	bool
286	select IRQ_DOMAIN
287	help
288	  Enables the wakeup IRQs for IMX platforms with GPCv2 block
289
290config IRQ_MXS
291	def_bool y if MACH_ASM9260 || ARCH_MXS
292	select IRQ_DOMAIN
293	select STMP_DEVICE
294
295config MSCC_OCELOT_IRQ
296	bool
297	select IRQ_DOMAIN
298	select GENERIC_IRQ_CHIP
299
300config MVEBU_GICP
301	bool
302
303config MVEBU_ICU
304	bool
305
306config MVEBU_ODMI
307	bool
308	select GENERIC_MSI_IRQ_DOMAIN
309
310config MVEBU_PIC
311	bool
312
 
 
 
313config LS_SCFG_MSI
314	def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
315	depends on PCI && PCI_MSI
316
317config PARTITION_PERCPU
318	bool
319
320config EZNPS_GIC
321	bool "NPS400 Global Interrupt Manager (GIM)"
322	depends on ARC || (COMPILE_TEST && !64BIT)
323	select IRQ_DOMAIN
324	help
325	  Support the EZchip NPS400 global interrupt controller
326
327config STM32_EXTI
328	bool
329	select IRQ_DOMAIN
330	select GENERIC_IRQ_CHIP
331
332config QCOM_IRQ_COMBINER
333	bool "QCOM IRQ combiner support"
334	depends on ARCH_QCOM && ACPI
335	select IRQ_DOMAIN
336	select IRQ_DOMAIN_HIERARCHY
337	help
338	  Say yes here to add support for the IRQ combiner devices embedded
339	  in Qualcomm Technologies chips.
340
341config IRQ_UNIPHIER_AIDET
342	bool "UniPhier AIDET support" if COMPILE_TEST
343	depends on ARCH_UNIPHIER || COMPILE_TEST
344	default ARCH_UNIPHIER
345	select IRQ_DOMAIN_HIERARCHY
346	help
347	  Support for the UniPhier AIDET (ARM Interrupt Detector).
348
349config MESON_IRQ_GPIO
350       bool "Meson GPIO Interrupt Multiplexer"
351       depends on ARCH_MESON
352       select IRQ_DOMAIN
353       select IRQ_DOMAIN_HIERARCHY
354       help
355         Support Meson SoC Family GPIO Interrupt Multiplexer
356
357config GOLDFISH_PIC
358       bool "Goldfish programmable interrupt controller"
359       depends on MIPS && (GOLDFISH || COMPILE_TEST)
360       select IRQ_DOMAIN
361       help
362         Say yes here to enable Goldfish interrupt controller driver used
363         for Goldfish based virtual platforms.
364
365config QCOM_PDC
366	bool "QCOM PDC"
367	depends on ARCH_QCOM
368	select IRQ_DOMAIN
369	select IRQ_DOMAIN_HIERARCHY
370	help
371	  Power Domain Controller driver to manage and configure wakeup
372	  IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
373
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
374endmenu

  1# SPDX-License-Identifier: GPL-2.0-only
  2menu "IRQ chip support"
  3
  4config IRQCHIP
  5	def_bool y
  6	depends on OF_IRQ
  7
  8config ARM_GIC
  9	bool
 
 10	select IRQ_DOMAIN_HIERARCHY
 11	select GENERIC_IRQ_MULTI_HANDLER
 12	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
 13
 14config ARM_GIC_PM
 15	bool
 16	depends on PM
 17	select ARM_GIC
 
 18
 19config ARM_GIC_MAX_NR
 20	int
 21	depends on ARM_GIC
 22	default 2 if ARCH_REALVIEW
 23	default 1
 24
 25config ARM_GIC_V2M
 26	bool
 27	depends on PCI
 28	select ARM_GIC
 29	select PCI_MSI
 30
 31config GIC_NON_BANKED
 32	bool
 33
 34config ARM_GIC_V3
 35	bool
 36	select GENERIC_IRQ_MULTI_HANDLER
 
 37	select IRQ_DOMAIN_HIERARCHY
 38	select PARTITION_PERCPU
 39	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
 40
 41config ARM_GIC_V3_ITS
 42	bool
 43	select GENERIC_MSI_IRQ_DOMAIN
 44	default ARM_GIC_V3
 45
 46config ARM_GIC_V3_ITS_PCI
 47	bool
 48	depends on ARM_GIC_V3_ITS
 49	depends on PCI
 50	depends on PCI_MSI
 51	default ARM_GIC_V3_ITS
 52
 53config ARM_GIC_V3_ITS_FSL_MC
 54	bool
 55	depends on ARM_GIC_V3_ITS
 56	depends on FSL_MC_BUS
 57	default ARM_GIC_V3_ITS
 58
 59config ARM_NVIC
 60	bool
 
 61	select IRQ_DOMAIN_HIERARCHY
 62	select GENERIC_IRQ_CHIP
 63
 64config ARM_VIC
 65	bool
 66	select IRQ_DOMAIN
 67	select GENERIC_IRQ_MULTI_HANDLER
 68
 69config ARM_VIC_NR
 70	int
 71	default 4 if ARCH_S5PV210
 72	default 2
 73	depends on ARM_VIC
 74	help
 75	  The maximum number of VICs available in the system, for
 76	  power management.
 77
 78config ARMADA_370_XP_IRQ
 79	bool
 80	select GENERIC_IRQ_CHIP
 81	select PCI_MSI if PCI
 82	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
 83
 84config ALPINE_MSI
 85	bool
 86	depends on PCI
 87	select PCI_MSI
 88	select GENERIC_IRQ_CHIP
 89
 90config AL_FIC
 91	bool "Amazon's Annapurna Labs Fabric Interrupt Controller"
 92	depends on OF || COMPILE_TEST
 93	select GENERIC_IRQ_CHIP
 94	select IRQ_DOMAIN
 95	help
 96	  Support Amazon's Annapurna Labs Fabric Interrupt Controller.
 97
 98config ATMEL_AIC_IRQ
 99	bool
100	select GENERIC_IRQ_CHIP
101	select IRQ_DOMAIN
102	select GENERIC_IRQ_MULTI_HANDLER
103	select SPARSE_IRQ
104
105config ATMEL_AIC5_IRQ
106	bool
107	select GENERIC_IRQ_CHIP
108	select IRQ_DOMAIN
109	select GENERIC_IRQ_MULTI_HANDLER
110	select SPARSE_IRQ
111
112config I8259
113	bool
114	select IRQ_DOMAIN
115
116config BCM6345_L1_IRQ
117	bool
118	select GENERIC_IRQ_CHIP
119	select IRQ_DOMAIN
120	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
121
122config BCM7038_L1_IRQ
123	bool
124	select GENERIC_IRQ_CHIP
125	select IRQ_DOMAIN
126	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
127
128config BCM7120_L2_IRQ
129	bool
130	select GENERIC_IRQ_CHIP
131	select IRQ_DOMAIN
132
133config BRCMSTB_L2_IRQ
134	bool
135	select GENERIC_IRQ_CHIP
136	select IRQ_DOMAIN
137
138config DAVINCI_AINTC
139	bool
140	select GENERIC_IRQ_CHIP
141	select IRQ_DOMAIN
142
143config DAVINCI_CP_INTC
144	bool
145	select GENERIC_IRQ_CHIP
146	select IRQ_DOMAIN
147
148config DW_APB_ICTL
149	bool
150	select GENERIC_IRQ_CHIP
151	select IRQ_DOMAIN
152
153config FARADAY_FTINTC010
154	bool
155	select IRQ_DOMAIN
156	select GENERIC_IRQ_MULTI_HANDLER
157	select SPARSE_IRQ
158
159config HISILICON_IRQ_MBIGEN
160	bool
161	select ARM_GIC_V3
162	select ARM_GIC_V3_ITS
163
164config IMGPDC_IRQ
165	bool
166	select GENERIC_IRQ_CHIP
167	select IRQ_DOMAIN
168
169config IXP4XX_IRQ
170	bool
171	select IRQ_DOMAIN
172	select GENERIC_IRQ_MULTI_HANDLER
173	select SPARSE_IRQ
174
175config MADERA_IRQ
176	tristate
177
178config IRQ_MIPS_CPU
179	bool
180	select GENERIC_IRQ_CHIP
181	select GENERIC_IRQ_IPI if SYS_SUPPORTS_MULTITHREADING
182	select IRQ_DOMAIN
183	select IRQ_DOMAIN_HIERARCHY if GENERIC_IRQ_IPI
184	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
185
186config CLPS711X_IRQCHIP
187	bool
188	depends on ARCH_CLPS711X
189	select IRQ_DOMAIN
190	select GENERIC_IRQ_MULTI_HANDLER
191	select SPARSE_IRQ
192	default y
193
194config OMPIC
195	bool
196
197config OR1K_PIC
198	bool
199	select IRQ_DOMAIN
200
201config OMAP_IRQCHIP
202	bool
203	select GENERIC_IRQ_CHIP
204	select IRQ_DOMAIN
205
206config ORION_IRQCHIP
207	bool
208	select IRQ_DOMAIN
209	select GENERIC_IRQ_MULTI_HANDLER
210
211config PIC32_EVIC
212	bool
213	select GENERIC_IRQ_CHIP
214	select IRQ_DOMAIN
215
216config JCORE_AIC
217	bool "J-Core integrated AIC" if COMPILE_TEST
218	depends on OF
219	select IRQ_DOMAIN
220	help
221	  Support for the J-Core integrated AIC.
222
223config RDA_INTC
224	bool
225	select IRQ_DOMAIN
226
227config RENESAS_INTC_IRQPIN
228	bool "Renesas INTC External IRQ Pin Support" if COMPILE_TEST
229	select IRQ_DOMAIN
230	help
231	  Enable support for the Renesas Interrupt Controller for external
232	  interrupt pins, as found on SH/R-Mobile and R-Car Gen1 SoCs.
233
234config RENESAS_IRQC
235	bool "Renesas R-Mobile APE6 and R-Car IRQC support" if COMPILE_TEST
236	select GENERIC_IRQ_CHIP
237	select IRQ_DOMAIN
238	help
239	  Enable support for the Renesas Interrupt Controller for external
240	  devices, as found on R-Mobile APE6, R-Car Gen2, and R-Car Gen3 SoCs.
241
242config RENESAS_RZA1_IRQC
243	bool "Renesas RZ/A1 IRQC support" if COMPILE_TEST
244	select IRQ_DOMAIN_HIERARCHY
245	help
246	  Enable support for the Renesas RZ/A1 Interrupt Controller, to use up
247	  to 8 external interrupts with configurable sense select.
248
249config ST_IRQCHIP
250	bool
251	select REGMAP
252	select MFD_SYSCON
253	help
254	  Enables SysCfg Controlled IRQs on STi based platforms.
255
256config TANGO_IRQ
257	bool
258	select IRQ_DOMAIN
259	select GENERIC_IRQ_CHIP
260
261config TB10X_IRQC
262	bool
263	select IRQ_DOMAIN
264	select GENERIC_IRQ_CHIP
265
266config TS4800_IRQ
267	tristate "TS-4800 IRQ controller"
268	select IRQ_DOMAIN
269	depends on HAS_IOMEM
270	depends on SOC_IMX51 || COMPILE_TEST
271	help
272	  Support for the TS-4800 FPGA IRQ controller
273
274config VERSATILE_FPGA_IRQ
275	bool
276	select IRQ_DOMAIN
277
278config VERSATILE_FPGA_IRQ_NR
279       int
280       default 4
281       depends on VERSATILE_FPGA_IRQ
282
283config XTENSA_MX
284	bool
285	select IRQ_DOMAIN
286	select GENERIC_IRQ_EFFECTIVE_AFF_MASK
287
288config XILINX_INTC
289	bool
290	select IRQ_DOMAIN
291
292config IRQ_CROSSBAR
293	bool
294	help
295	  Support for a CROSSBAR ip that precedes the main interrupt controller.
296	  The primary irqchip invokes the crossbar's callback which inturn allocates
297	  a free irq and configures the IP. Thus the peripheral interrupts are
298	  routed to one of the free irqchip interrupt lines.
299
300config KEYSTONE_IRQ
301	tristate "Keystone 2 IRQ controller IP"
302	depends on ARCH_KEYSTONE
303	help
304		Support for Texas Instruments Keystone 2 IRQ controller IP which
305		is part of the Keystone 2 IPC mechanism
306
307config MIPS_GIC
308	bool
309	select GENERIC_IRQ_IPI
310	select IRQ_DOMAIN_HIERARCHY
311	select MIPS_CM
312
313config INGENIC_IRQ
314	bool
315	depends on MACH_INGENIC
316	default y
317
318config INGENIC_TCU_IRQ
319	bool "Ingenic JZ47xx TCU interrupt controller"
320	default MACH_INGENIC
321	depends on MIPS || COMPILE_TEST
322	select MFD_SYSCON
323	select GENERIC_IRQ_CHIP
324	help
325	  Support for interrupts in the Timer/Counter Unit (TCU) of the Ingenic
326	  JZ47xx SoCs.
327
328	  If unsure, say N.
329
330config RENESAS_H8300H_INTC
331        bool
332	select IRQ_DOMAIN
333
334config RENESAS_H8S_INTC
335	bool "Renesas H8S Interrupt Controller Support" if COMPILE_TEST
336	select IRQ_DOMAIN
337	help
338	  Enable support for the Renesas H8/300 Interrupt Controller, as found
339	  on Renesas H8S SoCs.
340
341config IMX_GPCV2
342	bool
343	select IRQ_DOMAIN
344	help
345	  Enables the wakeup IRQs for IMX platforms with GPCv2 block
346
347config IRQ_MXS
348	def_bool y if MACH_ASM9260 || ARCH_MXS
349	select IRQ_DOMAIN
350	select STMP_DEVICE
351
352config MSCC_OCELOT_IRQ
353	bool
354	select IRQ_DOMAIN
355	select GENERIC_IRQ_CHIP
356
357config MVEBU_GICP
358	bool
359
360config MVEBU_ICU
361	bool
362
363config MVEBU_ODMI
364	bool
365	select GENERIC_MSI_IRQ_DOMAIN
366
367config MVEBU_PIC
368	bool
369
370config MVEBU_SEI
371        bool
372
373config LS_SCFG_MSI
374	def_bool y if SOC_LS1021A || ARCH_LAYERSCAPE
375	depends on PCI && PCI_MSI
376
377config PARTITION_PERCPU
378	bool
379
380config EZNPS_GIC
381	bool "NPS400 Global Interrupt Manager (GIM)"
382	depends on ARC || (COMPILE_TEST && !64BIT)
383	select IRQ_DOMAIN
384	help
385	  Support the EZchip NPS400 global interrupt controller
386
387config STM32_EXTI
388	bool
389	select IRQ_DOMAIN
390	select GENERIC_IRQ_CHIP
391
392config QCOM_IRQ_COMBINER
393	bool "QCOM IRQ combiner support"
394	depends on ARCH_QCOM && ACPI
 
395	select IRQ_DOMAIN_HIERARCHY
396	help
397	  Say yes here to add support for the IRQ combiner devices embedded
398	  in Qualcomm Technologies chips.
399
400config IRQ_UNIPHIER_AIDET
401	bool "UniPhier AIDET support" if COMPILE_TEST
402	depends on ARCH_UNIPHIER || COMPILE_TEST
403	default ARCH_UNIPHIER
404	select IRQ_DOMAIN_HIERARCHY
405	help
406	  Support for the UniPhier AIDET (ARM Interrupt Detector).
407
408config MESON_IRQ_GPIO
409       bool "Meson GPIO Interrupt Multiplexer"
410       depends on ARCH_MESON
 
411       select IRQ_DOMAIN_HIERARCHY
412       help
413         Support Meson SoC Family GPIO Interrupt Multiplexer
414
415config GOLDFISH_PIC
416       bool "Goldfish programmable interrupt controller"
417       depends on MIPS && (GOLDFISH || COMPILE_TEST)
418       select IRQ_DOMAIN
419       help
420         Say yes here to enable Goldfish interrupt controller driver used
421         for Goldfish based virtual platforms.
422
423config QCOM_PDC
424	bool "QCOM PDC"
425	depends on ARCH_QCOM
 
426	select IRQ_DOMAIN_HIERARCHY
427	help
428	  Power Domain Controller driver to manage and configure wakeup
429	  IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
430
431config CSKY_MPINTC
432	bool "C-SKY Multi Processor Interrupt Controller"
433	depends on CSKY
434	help
435	  Say yes here to enable C-SKY SMP interrupt controller driver used
436	  for C-SKY SMP system.
437	  In fact it's not mmio map in hw and it use ld/st to visit the
438	  controller's register inside CPU.
439
440config CSKY_APB_INTC
441	bool "C-SKY APB Interrupt Controller"
442	depends on CSKY
443	help
444	  Say yes here to enable C-SKY APB interrupt controller driver used
445	  by C-SKY single core SOC system. It use mmio map apb-bus to visit
446	  the controller's register.
447
448config IMX_IRQSTEER
449	bool "i.MX IRQSTEER support"
450	depends on ARCH_MXC || COMPILE_TEST
451	default ARCH_MXC
452	select IRQ_DOMAIN
453	help
454	  Support for the i.MX IRQSTEER interrupt multiplexer/remapper.
455
456config LS1X_IRQ
457	bool "Loongson-1 Interrupt Controller"
458	depends on MACH_LOONGSON32
459	default y
460	select IRQ_DOMAIN
461	select GENERIC_IRQ_CHIP
462	help
463	  Support for the Loongson-1 platform Interrupt Controller.
464
465config TI_SCI_INTR_IRQCHIP
466	bool
467	depends on TI_SCI_PROTOCOL
468	select IRQ_DOMAIN_HIERARCHY
469	help
470	  This enables the irqchip driver support for K3 Interrupt router
471	  over TI System Control Interface available on some new TI's SoCs.
472	  If you wish to use interrupt router irq resources managed by the
473	  TI System Controller, say Y here. Otherwise, say N.
474
475config TI_SCI_INTA_IRQCHIP
476	bool
477	depends on TI_SCI_PROTOCOL
478	select IRQ_DOMAIN_HIERARCHY
479	select TI_SCI_INTA_MSI_DOMAIN
480	help
481	  This enables the irqchip driver support for K3 Interrupt aggregator
482	  over TI System Control Interface available on some new TI's SoCs.
483	  If you wish to use interrupt aggregator irq resources managed by the
484	  TI System Controller, say Y here. Otherwise, say N.
485
486endmenu
487
488config SIFIVE_PLIC
489	bool "SiFive Platform-Level Interrupt Controller"
490	depends on RISCV
491	help
492	   This enables support for the PLIC chip found in SiFive (and
493	   potentially other) RISC-V systems.  The PLIC controls devices
494	   interrupts and connects them to each core's local interrupt
495	   controller.  Aside from timer and software interrupts, all other
496	   interrupt sources are subordinate to the PLIC.
497
498	   If you don't know what to do here, say Y.