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v4.17
   1/*
   2 * Copyright 2008 Advanced Micro Devices, Inc.
   3 * Copyright 2008 Red Hat Inc.
   4 * Copyright 2009 Jerome Glisse.
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a
   7 * copy of this software and associated documentation files (the "Software"),
   8 * to deal in the Software without restriction, including without limitation
   9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10 * and/or sell copies of the Software, and to permit persons to whom the
  11 * Software is furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22 * OTHER DEALINGS IN THE SOFTWARE.
  23 *
  24 * Authors: Dave Airlie
  25 *          Alex Deucher
  26 *          Jerome Glisse
  27 */
  28#include <linux/dma-fence-array.h>
  29#include <linux/interval_tree_generic.h>
  30#include <linux/idr.h>
  31#include <drm/drmP.h>
  32#include <drm/amdgpu_drm.h>
  33#include "amdgpu.h"
  34#include "amdgpu_trace.h"
  35#include "amdgpu_amdkfd.h"
 
 
  36
  37/*
  38 * GPUVM
 
  39 * GPUVM is similar to the legacy gart on older asics, however
  40 * rather than there being a single global gart table
  41 * for the entire GPU, there are multiple VM page tables active
  42 * at any given time.  The VM page tables can contain a mix
  43 * vram pages and system memory pages and system memory pages
  44 * can be mapped as snooped (cached system pages) or unsnooped
  45 * (uncached system pages).
  46 * Each VM has an ID associated with it and there is a page table
  47 * associated with each VMID.  When execting a command buffer,
  48 * the kernel tells the the ring what VMID to use for that command
  49 * buffer.  VMIDs are allocated dynamically as commands are submitted.
  50 * The userspace drivers maintain their own address space and the kernel
  51 * sets up their pages tables accordingly when they submit their
  52 * command buffers and a VMID is assigned.
  53 * Cayman/Trinity support up to 8 active VMs at any given time;
  54 * SI supports 16.
  55 */
  56
  57#define START(node) ((node)->start)
  58#define LAST(node) ((node)->last)
  59
  60INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
  61		     START, LAST, static, amdgpu_vm_it)
  62
  63#undef START
  64#undef LAST
  65
  66/* Local structure. Encapsulate some VM table update parameters to reduce
  67 * the number of function parameters
  68 */
  69struct amdgpu_pte_update_params {
  70	/* amdgpu device we do this update for */
  71	struct amdgpu_device *adev;
  72	/* optional amdgpu_vm we do this update for */
  73	struct amdgpu_vm *vm;
  74	/* address where to copy page table entries from */
  75	uint64_t src;
  76	/* indirect buffer to fill with commands */
  77	struct amdgpu_ib *ib;
  78	/* Function which actually does the update */
  79	void (*func)(struct amdgpu_pte_update_params *params,
  80		     struct amdgpu_bo *bo, uint64_t pe,
  81		     uint64_t addr, unsigned count, uint32_t incr,
  82		     uint64_t flags);
  83	/* The next two are used during VM update by CPU
  84	 *  DMA addresses to use for mapping
  85	 *  Kernel pointer of PD/PT BO that needs to be updated
  86	 */
  87	dma_addr_t *pages_addr;
  88	void *kptr;
  89};
  90
  91/* Helper to disable partial resident texture feature from a fence callback */
  92struct amdgpu_prt_cb {
 
 
 
 
  93	struct amdgpu_device *adev;
 
 
 
 
  94	struct dma_fence_cb cb;
  95};
  96
  97/**
  98 * amdgpu_vm_level_shift - return the addr shift for each level
  99 *
 100 * @adev: amdgpu_device pointer
 
 101 *
 102 * Returns the number of bits the pfn needs to be right shifted for a level.
 
 103 */
 104static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
 105				      unsigned level)
 106{
 107	unsigned shift = 0xff;
 108
 109	switch (level) {
 110	case AMDGPU_VM_PDB2:
 111	case AMDGPU_VM_PDB1:
 112	case AMDGPU_VM_PDB0:
 113		shift = 9 * (AMDGPU_VM_PDB0 - level) +
 114			adev->vm_manager.block_size;
 115		break;
 116	case AMDGPU_VM_PTB:
 117		shift = 0;
 118		break;
 119	default:
 120		dev_err(adev->dev, "the level%d isn't supported.\n", level);
 121	}
 122
 123	return shift;
 124}
 125
 126/**
 127 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
 128 *
 129 * @adev: amdgpu_device pointer
 
 130 *
 131 * Calculate the number of entries in a page directory or page table.
 
 132 */
 133static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
 134				      unsigned level)
 135{
 136	unsigned shift = amdgpu_vm_level_shift(adev,
 137					       adev->vm_manager.root_level);
 138
 139	if (level == adev->vm_manager.root_level)
 140		/* For the root directory */
 141		return round_up(adev->vm_manager.max_pfn, 1 << shift) >> shift;
 142	else if (level != AMDGPU_VM_PTB)
 143		/* Everything in between */
 144		return 512;
 145	else
 146		/* For the page tables on the leaves */
 147		return AMDGPU_VM_PTE_COUNT(adev);
 148}
 149
 150/**
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 151 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
 152 *
 153 * @adev: amdgpu_device pointer
 
 154 *
 155 * Calculate the size of the BO for a page directory or page table in bytes.
 
 156 */
 157static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
 158{
 159	return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
 160}
 161
 162/**
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 163 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
 164 *
 165 * @vm: vm providing the BOs
 166 * @validated: head of validation list
 167 * @entry: entry to add
 168 *
 169 * Add the page directory to the list of BOs to
 170 * validate for command submission.
 171 */
 172void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
 173			 struct list_head *validated,
 174			 struct amdgpu_bo_list_entry *entry)
 175{
 176	entry->robj = vm->root.base.bo;
 177	entry->priority = 0;
 178	entry->tv.bo = &entry->robj->tbo;
 179	entry->tv.shared = true;
 
 180	entry->user_pages = NULL;
 181	list_add(&entry->tv.head, validated);
 182}
 183
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 184/**
 185 * amdgpu_vm_validate_pt_bos - validate the page table BOs
 186 *
 187 * @adev: amdgpu device pointer
 188 * @vm: vm providing the BOs
 189 * @validate: callback to do the validation
 190 * @param: parameter for the validation callback
 191 *
 192 * Validate the page table BOs on command submission if neccessary.
 
 
 
 193 */
 194int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 195			      int (*validate)(void *p, struct amdgpu_bo *bo),
 196			      void *param)
 197{
 198	struct ttm_bo_global *glob = adev->mman.bdev.glob;
 199	int r;
 200
 201	spin_lock(&vm->status_lock);
 202	while (!list_empty(&vm->evicted)) {
 203		struct amdgpu_vm_bo_base *bo_base;
 204		struct amdgpu_bo *bo;
 205
 206		bo_base = list_first_entry(&vm->evicted,
 207					   struct amdgpu_vm_bo_base,
 208					   vm_status);
 209		spin_unlock(&vm->status_lock);
 210
 211		bo = bo_base->bo;
 212		BUG_ON(!bo);
 213		if (bo->parent) {
 214			r = validate(param, bo);
 215			if (r)
 216				return r;
 217
 218			spin_lock(&glob->lru_lock);
 219			ttm_bo_move_to_lru_tail(&bo->tbo);
 220			if (bo->shadow)
 221				ttm_bo_move_to_lru_tail(&bo->shadow->tbo);
 222			spin_unlock(&glob->lru_lock);
 223		}
 224
 225		if (bo->tbo.type == ttm_bo_type_kernel &&
 226		    vm->use_cpu_for_update) {
 227			r = amdgpu_bo_kmap(bo, NULL);
 228			if (r)
 229				return r;
 230		}
 231
 232		spin_lock(&vm->status_lock);
 233		if (bo->tbo.type != ttm_bo_type_kernel)
 234			list_move(&bo_base->vm_status, &vm->moved);
 235		else
 236			list_move(&bo_base->vm_status, &vm->relocated);
 237	}
 238	spin_unlock(&vm->status_lock);
 239
 240	return 0;
 241}
 242
 243/**
 244 * amdgpu_vm_ready - check VM is ready for updates
 245 *
 246 * @vm: VM to check
 247 *
 248 * Check if all VM PDs/PTs are ready for updates
 
 
 
 249 */
 250bool amdgpu_vm_ready(struct amdgpu_vm *vm)
 251{
 252	bool ready;
 253
 254	spin_lock(&vm->status_lock);
 255	ready = list_empty(&vm->evicted);
 256	spin_unlock(&vm->status_lock);
 257
 258	return ready;
 259}
 260
 261/**
 262 * amdgpu_vm_clear_bo - initially clear the PDs/PTs
 263 *
 264 * @adev: amdgpu_device pointer
 
 265 * @bo: BO to clear
 266 * @level: level this BO is at
 267 *
 268 * Root PD needs to be reserved when calling this.
 
 
 
 269 */
 270static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
 271			      struct amdgpu_vm *vm, struct amdgpu_bo *bo,
 272			      unsigned level, bool pte_support_ats)
 273{
 274	struct ttm_operation_ctx ctx = { true, false };
 275	struct dma_fence *fence = NULL;
 
 
 276	unsigned entries, ats_entries;
 277	struct amdgpu_ring *ring;
 278	struct amdgpu_job *job;
 279	uint64_t addr;
 280	int r;
 281
 282	addr = amdgpu_bo_gpu_offset(bo);
 
 
 
 
 
 
 
 
 283	entries = amdgpu_bo_size(bo) / 8;
 
 
 
 
 
 
 
 284
 285	if (pte_support_ats) {
 286		if (level == adev->vm_manager.root_level) {
 287			ats_entries = amdgpu_vm_level_shift(adev, level);
 288			ats_entries += AMDGPU_GPU_PAGE_SHIFT;
 289			ats_entries = AMDGPU_VA_HOLE_START >> ats_entries;
 290			ats_entries = min(ats_entries, entries);
 291			entries -= ats_entries;
 292		} else {
 293			ats_entries = entries;
 294			entries = 0;
 295		}
 296	} else {
 297		ats_entries = 0;
 298	}
 299
 300	ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
 301
 302	r = reservation_object_reserve_shared(bo->tbo.resv);
 303	if (r)
 304		return r;
 305
 306	r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 
 
 
 
 
 
 
 307	if (r)
 308		goto error;
 
 
 
 
 309
 310	r = amdgpu_job_alloc_with_ib(adev, 64, &job);
 311	if (r)
 312		goto error;
 313
 
 314	if (ats_entries) {
 315		uint64_t ats_value;
 
 
 
 
 
 
 
 316
 317		ats_value = AMDGPU_PTE_DEFAULT_ATC;
 318		if (level != AMDGPU_VM_PTB)
 319			ats_value |= AMDGPU_PDE_PTE;
 
 320
 321		amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
 322				      ats_entries, 0, ats_value);
 323		addr += ats_entries * 8;
 324	}
 325
 326	if (entries)
 327		amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
 328				      entries, 0, 0);
 329
 330	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 331
 332	WARN_ON(job->ibs[0].length_dw > 64);
 333	r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv,
 334			     AMDGPU_FENCE_OWNER_UNDEFINED, false);
 335	if (r)
 336		goto error_free;
 337
 338	r = amdgpu_job_submit(job, ring, &vm->entity,
 339			      AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
 340	if (r)
 341		goto error_free;
 342
 343	amdgpu_bo_fence(bo, fence, true);
 344	dma_fence_put(fence);
 
 
 
 
 
 
 
 
 
 345
 346	if (bo->shadow)
 347		return amdgpu_vm_clear_bo(adev, vm, bo->shadow,
 348					  level, pte_support_ats);
 
 
 349
 350	return 0;
 
 351
 352error_free:
 353	amdgpu_job_free(job);
 
 
 
 
 
 
 
 
 
 354
 355error:
 356	return r;
 
 
 
 
 
 
 
 
 
 
 
 357}
 358
 359/**
 360 * amdgpu_vm_alloc_levels - allocate the PD/PT levels
 361 *
 362 * @adev: amdgpu_device pointer
 363 * @vm: requested vm
 364 * @saddr: start of the address range
 365 * @eaddr: end of the address range
 
 366 *
 367 * Make sure the page directories and page tables are allocated
 
 
 368 */
 369static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
 370				  struct amdgpu_vm *vm,
 371				  struct amdgpu_vm_pt *parent,
 372				  uint64_t saddr, uint64_t eaddr,
 373				  unsigned level, bool ats)
 374{
 375	unsigned shift = amdgpu_vm_level_shift(adev, level);
 376	unsigned pt_idx, from, to;
 377	u64 flags;
 378	int r;
 379
 380	if (!parent->entries) {
 381		unsigned num_entries = amdgpu_vm_num_entries(adev, level);
 382
 383		parent->entries = kvmalloc_array(num_entries,
 384						   sizeof(struct amdgpu_vm_pt),
 385						   GFP_KERNEL | __GFP_ZERO);
 386		if (!parent->entries)
 
 387			return -ENOMEM;
 388		memset(parent->entries, 0 , sizeof(struct amdgpu_vm_pt));
 389	}
 390
 391	from = saddr >> shift;
 392	to = eaddr >> shift;
 393	if (from >= amdgpu_vm_num_entries(adev, level) ||
 394	    to >= amdgpu_vm_num_entries(adev, level))
 395		return -EINVAL;
 396
 397	++level;
 398	saddr = saddr & ((1 << shift) - 1);
 399	eaddr = eaddr & ((1 << shift) - 1);
 400
 401	flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
 402	if (vm->use_cpu_for_update)
 403		flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 404	else
 405		flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
 406				AMDGPU_GEM_CREATE_SHADOW);
 407
 408	/* walk over the address space and allocate the page tables */
 409	for (pt_idx = from; pt_idx <= to; ++pt_idx) {
 410		struct reservation_object *resv = vm->root.base.bo->tbo.resv;
 411		struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
 412		struct amdgpu_bo *pt;
 413
 414		if (!entry->base.bo) {
 415			r = amdgpu_bo_create(adev,
 416					     amdgpu_vm_bo_size(adev, level),
 417					     AMDGPU_GPU_PAGE_SIZE,
 418					     AMDGPU_GEM_DOMAIN_VRAM, flags,
 419					     ttm_bo_type_kernel, resv, &pt);
 420			if (r)
 421				return r;
 422
 423			r = amdgpu_vm_clear_bo(adev, vm, pt, level, ats);
 424			if (r) {
 425				amdgpu_bo_unref(&pt->shadow);
 426				amdgpu_bo_unref(&pt);
 427				return r;
 428			}
 429
 430			if (vm->use_cpu_for_update) {
 431				r = amdgpu_bo_kmap(pt, NULL);
 432				if (r) {
 433					amdgpu_bo_unref(&pt->shadow);
 434					amdgpu_bo_unref(&pt);
 435					return r;
 436				}
 437			}
 438
 439			/* Keep a reference to the root directory to avoid
 440			* freeing them up in the wrong order.
 441			*/
 442			pt->parent = amdgpu_bo_ref(parent->base.bo);
 443
 444			entry->base.vm = vm;
 445			entry->base.bo = pt;
 446			list_add_tail(&entry->base.bo_list, &pt->va);
 447			spin_lock(&vm->status_lock);
 448			list_add(&entry->base.vm_status, &vm->relocated);
 449			spin_unlock(&vm->status_lock);
 450		}
 451
 452		if (level < AMDGPU_VM_PTB) {
 453			uint64_t sub_saddr = (pt_idx == from) ? saddr : 0;
 454			uint64_t sub_eaddr = (pt_idx == to) ? eaddr :
 455				((1 << shift) - 1);
 456			r = amdgpu_vm_alloc_levels(adev, vm, entry, sub_saddr,
 457						   sub_eaddr, level, ats);
 458			if (r)
 459				return r;
 460		}
 461	}
 462
 463	return 0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 464}
 465
 466/**
 467 * amdgpu_vm_alloc_pts - Allocate page tables.
 468 *
 469 * @adev: amdgpu_device pointer
 470 * @vm: VM to allocate page tables for
 471 * @saddr: Start address which needs to be allocated
 472 * @size: Size from start address we need.
 473 *
 474 * Make sure the page tables are allocated.
 475 */
 476int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
 477			struct amdgpu_vm *vm,
 478			uint64_t saddr, uint64_t size)
 479{
 480	uint64_t eaddr;
 481	bool ats = false;
 482
 483	/* validate the parameters */
 484	if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK)
 485		return -EINVAL;
 486
 487	eaddr = saddr + size - 1;
 488
 489	if (vm->pte_support_ats)
 490		ats = saddr < AMDGPU_VA_HOLE_START;
 491
 492	saddr /= AMDGPU_GPU_PAGE_SIZE;
 493	eaddr /= AMDGPU_GPU_PAGE_SIZE;
 494
 495	if (eaddr >= adev->vm_manager.max_pfn) {
 496		dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n",
 497			eaddr, adev->vm_manager.max_pfn);
 498		return -EINVAL;
 499	}
 500
 501	return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr,
 502				      adev->vm_manager.root_level, ats);
 503}
 504
 505/**
 506 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
 507 *
 508 * @adev: amdgpu_device pointer
 509 */
 510void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
 511{
 512	const struct amdgpu_ip_block *ip_block;
 513	bool has_compute_vm_bug;
 514	struct amdgpu_ring *ring;
 515	int i;
 516
 517	has_compute_vm_bug = false;
 518
 519	ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
 520	if (ip_block) {
 521		/* Compute has a VM bug for GFX version < 7.
 522		   Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
 523		if (ip_block->version->major <= 7)
 524			has_compute_vm_bug = true;
 525		else if (ip_block->version->major == 8)
 526			if (adev->gfx.mec_fw_version < 673)
 527				has_compute_vm_bug = true;
 528	}
 529
 530	for (i = 0; i < adev->num_rings; i++) {
 531		ring = adev->rings[i];
 532		if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
 533			/* only compute rings */
 534			ring->has_compute_vm_bug = has_compute_vm_bug;
 535		else
 536			ring->has_compute_vm_bug = false;
 537	}
 538}
 539
 
 
 
 
 
 
 
 
 
 540bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
 541				  struct amdgpu_job *job)
 542{
 543	struct amdgpu_device *adev = ring->adev;
 544	unsigned vmhub = ring->funcs->vmhub;
 545	struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
 546	struct amdgpu_vmid *id;
 547	bool gds_switch_needed;
 548	bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
 549
 550	if (job->vmid == 0)
 551		return false;
 552	id = &id_mgr->ids[job->vmid];
 553	gds_switch_needed = ring->funcs->emit_gds_switch && (
 554		id->gds_base != job->gds_base ||
 555		id->gds_size != job->gds_size ||
 556		id->gws_base != job->gws_base ||
 557		id->gws_size != job->gws_size ||
 558		id->oa_base != job->oa_base ||
 559		id->oa_size != job->oa_size);
 560
 561	if (amdgpu_vmid_had_gpu_reset(adev, id))
 562		return true;
 563
 564	return vm_flush_needed || gds_switch_needed;
 565}
 566
 567static bool amdgpu_vm_is_large_bar(struct amdgpu_device *adev)
 568{
 569	return (adev->gmc.real_vram_size == adev->gmc.visible_vram_size);
 570}
 571
 572/**
 573 * amdgpu_vm_flush - hardware flush the vm
 574 *
 575 * @ring: ring to use for flush
 576 * @vmid: vmid number to use
 577 * @pd_addr: address of the page directory
 578 *
 579 * Emit a VM flush when it is necessary.
 
 
 
 580 */
 581int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync)
 582{
 583	struct amdgpu_device *adev = ring->adev;
 584	unsigned vmhub = ring->funcs->vmhub;
 585	struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
 586	struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
 587	bool gds_switch_needed = ring->funcs->emit_gds_switch && (
 588		id->gds_base != job->gds_base ||
 589		id->gds_size != job->gds_size ||
 590		id->gws_base != job->gws_base ||
 591		id->gws_size != job->gws_size ||
 592		id->oa_base != job->oa_base ||
 593		id->oa_size != job->oa_size);
 594	bool vm_flush_needed = job->vm_needs_flush;
 595	bool pasid_mapping_needed = id->pasid != job->pasid ||
 596		!id->pasid_mapping ||
 597		!dma_fence_is_signaled(id->pasid_mapping);
 598	struct dma_fence *fence = NULL;
 599	unsigned patch_offset = 0;
 600	int r;
 601
 602	if (amdgpu_vmid_had_gpu_reset(adev, id)) {
 603		gds_switch_needed = true;
 604		vm_flush_needed = true;
 605		pasid_mapping_needed = true;
 606	}
 607
 608	gds_switch_needed &= !!ring->funcs->emit_gds_switch;
 609	vm_flush_needed &= !!ring->funcs->emit_vm_flush;
 
 610	pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
 611		ring->funcs->emit_wreg;
 612
 613	if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
 614		return 0;
 615
 616	if (ring->funcs->init_cond_exec)
 617		patch_offset = amdgpu_ring_init_cond_exec(ring);
 618
 619	if (need_pipe_sync)
 620		amdgpu_ring_emit_pipeline_sync(ring);
 621
 622	if (vm_flush_needed) {
 623		trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
 624		amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
 625	}
 626
 627	if (pasid_mapping_needed)
 628		amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
 629
 630	if (vm_flush_needed || pasid_mapping_needed) {
 631		r = amdgpu_fence_emit(ring, &fence);
 632		if (r)
 633			return r;
 634	}
 635
 636	if (vm_flush_needed) {
 637		mutex_lock(&id_mgr->lock);
 638		dma_fence_put(id->last_flush);
 639		id->last_flush = dma_fence_get(fence);
 640		id->current_gpu_reset_count =
 641			atomic_read(&adev->gpu_reset_counter);
 642		mutex_unlock(&id_mgr->lock);
 643	}
 644
 645	if (pasid_mapping_needed) {
 646		id->pasid = job->pasid;
 647		dma_fence_put(id->pasid_mapping);
 648		id->pasid_mapping = dma_fence_get(fence);
 649	}
 650	dma_fence_put(fence);
 651
 652	if (ring->funcs->emit_gds_switch && gds_switch_needed) {
 653		id->gds_base = job->gds_base;
 654		id->gds_size = job->gds_size;
 655		id->gws_base = job->gws_base;
 656		id->gws_size = job->gws_size;
 657		id->oa_base = job->oa_base;
 658		id->oa_size = job->oa_size;
 659		amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
 660					    job->gds_size, job->gws_base,
 661					    job->gws_size, job->oa_base,
 662					    job->oa_size);
 663	}
 664
 665	if (ring->funcs->patch_cond_exec)
 666		amdgpu_ring_patch_cond_exec(ring, patch_offset);
 667
 668	/* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
 669	if (ring->funcs->emit_switch_buffer) {
 670		amdgpu_ring_emit_switch_buffer(ring);
 671		amdgpu_ring_emit_switch_buffer(ring);
 672	}
 673	return 0;
 674}
 675
 676/**
 677 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
 678 *
 679 * @vm: requested vm
 680 * @bo: requested buffer object
 681 *
 682 * Find @bo inside the requested vm.
 683 * Search inside the @bos vm list for the requested vm
 684 * Returns the found bo_va or NULL if none is found
 685 *
 686 * Object has to be reserved!
 
 
 
 687 */
 688struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
 689				       struct amdgpu_bo *bo)
 690{
 691	struct amdgpu_bo_va *bo_va;
 692
 693	list_for_each_entry(bo_va, &bo->va, base.bo_list) {
 694		if (bo_va->base.vm == vm) {
 695			return bo_va;
 696		}
 697	}
 698	return NULL;
 699}
 700
 701/**
 702 * amdgpu_vm_do_set_ptes - helper to call the right asic function
 703 *
 704 * @params: see amdgpu_pte_update_params definition
 705 * @bo: PD/PT to update
 706 * @pe: addr of the page entry
 707 * @addr: dst addr to write into pe
 708 * @count: number of page entries to update
 709 * @incr: increase next addr by incr bytes
 710 * @flags: hw access flags
 711 *
 712 * Traces the parameters and calls the right asic functions
 713 * to setup the page table using the DMA.
 714 */
 715static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params,
 716				  struct amdgpu_bo *bo,
 717				  uint64_t pe, uint64_t addr,
 718				  unsigned count, uint32_t incr,
 719				  uint64_t flags)
 720{
 721	pe += amdgpu_bo_gpu_offset(bo);
 722	trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
 723
 724	if (count < 3) {
 725		amdgpu_vm_write_pte(params->adev, params->ib, pe,
 726				    addr | flags, count, incr);
 727
 728	} else {
 729		amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr,
 730				      count, incr, flags);
 731	}
 732}
 733
 734/**
 735 * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART
 736 *
 737 * @params: see amdgpu_pte_update_params definition
 738 * @bo: PD/PT to update
 739 * @pe: addr of the page entry
 740 * @addr: dst addr to write into pe
 741 * @count: number of page entries to update
 742 * @incr: increase next addr by incr bytes
 743 * @flags: hw access flags
 744 *
 745 * Traces the parameters and calls the DMA function to copy the PTEs.
 746 */
 747static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params,
 748				   struct amdgpu_bo *bo,
 749				   uint64_t pe, uint64_t addr,
 750				   unsigned count, uint32_t incr,
 751				   uint64_t flags)
 752{
 753	uint64_t src = (params->src + (addr >> 12) * 8);
 754
 755	pe += amdgpu_bo_gpu_offset(bo);
 756	trace_amdgpu_vm_copy_ptes(pe, src, count);
 757
 758	amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count);
 759}
 760
 761/**
 762 * amdgpu_vm_map_gart - Resolve gart mapping of addr
 763 *
 764 * @pages_addr: optional DMA address to use for lookup
 765 * @addr: the unmapped addr
 766 *
 767 * Look up the physical address of the page that the pte resolves
 768 * to and return the pointer for the page table entry.
 
 
 
 769 */
 770static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
 771{
 772	uint64_t result;
 773
 774	/* page table offset */
 775	result = pages_addr[addr >> PAGE_SHIFT];
 776
 777	/* in case cpu page size != gpu page size*/
 778	result |= addr & (~PAGE_MASK);
 779
 780	result &= 0xFFFFFFFFFFFFF000ULL;
 781
 782	return result;
 783}
 784
 785/**
 786 * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU
 787 *
 788 * @params: see amdgpu_pte_update_params definition
 789 * @bo: PD/PT to update
 790 * @pe: kmap addr of the page entry
 791 * @addr: dst addr to write into pe
 792 * @count: number of page entries to update
 793 * @incr: increase next addr by incr bytes
 794 * @flags: hw access flags
 795 *
 796 * Write count number of PT/PD entries directly.
 797 */
 798static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params,
 799				   struct amdgpu_bo *bo,
 800				   uint64_t pe, uint64_t addr,
 801				   unsigned count, uint32_t incr,
 802				   uint64_t flags)
 803{
 804	unsigned int i;
 805	uint64_t value;
 806
 807	pe += (unsigned long)amdgpu_bo_kptr(bo);
 808
 809	trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
 810
 811	for (i = 0; i < count; i++) {
 812		value = params->pages_addr ?
 813			amdgpu_vm_map_gart(params->pages_addr, addr) :
 814			addr;
 815		amdgpu_gmc_set_pte_pde(params->adev, (void *)(uintptr_t)pe,
 816				       i, value, flags);
 817		addr += incr;
 818	}
 819}
 820
 821static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 822			     void *owner)
 823{
 824	struct amdgpu_sync sync;
 825	int r;
 826
 827	amdgpu_sync_create(&sync);
 828	amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner, false);
 829	r = amdgpu_sync_wait(&sync, true);
 830	amdgpu_sync_free(&sync);
 831
 832	return r;
 833}
 834
 835/*
 836 * amdgpu_vm_update_pde - update a single level in the hierarchy
 837 *
 838 * @param: parameters for the update
 839 * @vm: requested vm
 840 * @parent: parent directory
 841 * @entry: entry to update
 842 *
 843 * Makes sure the requested entry in parent is up to date.
 844 */
 845static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params,
 846				 struct amdgpu_vm *vm,
 847				 struct amdgpu_vm_pt *parent,
 848				 struct amdgpu_vm_pt *entry)
 849{
 
 850	struct amdgpu_bo *bo = parent->base.bo, *pbo;
 851	uint64_t pde, pt, flags;
 852	unsigned level;
 853
 854	/* Don't update huge pages here */
 855	if (entry->huge)
 856		return;
 857
 858	for (level = 0, pbo = bo->parent; pbo; ++level)
 859		pbo = pbo->parent;
 860
 861	level += params->adev->vm_manager.root_level;
 862	pt = amdgpu_bo_gpu_offset(entry->base.bo);
 863	flags = AMDGPU_PTE_VALID;
 864	amdgpu_gmc_get_vm_pde(params->adev, level, &pt, &flags);
 865	pde = (entry - parent->entries) * 8;
 866	if (bo->shadow)
 867		params->func(params, bo->shadow, pde, pt, 1, 0, flags);
 868	params->func(params, bo, pde, pt, 1, 0, flags);
 869}
 870
 871/*
 872 * amdgpu_vm_invalidate_level - mark all PD levels as invalid
 873 *
 874 * @parent: parent PD
 
 875 *
 876 * Mark all PD level as invalid after an error.
 877 */
 878static void amdgpu_vm_invalidate_level(struct amdgpu_device *adev,
 879				       struct amdgpu_vm *vm,
 880				       struct amdgpu_vm_pt *parent,
 881				       unsigned level)
 882{
 883	unsigned pt_idx, num_entries;
 
 884
 885	/*
 886	 * Recurse into the subdirectories. This recursion is harmless because
 887	 * we only have a maximum of 5 layers.
 888	 */
 889	num_entries = amdgpu_vm_num_entries(adev, level);
 890	for (pt_idx = 0; pt_idx < num_entries; ++pt_idx) {
 891		struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
 892
 893		if (!entry->base.bo)
 894			continue;
 895
 896		spin_lock(&vm->status_lock);
 897		if (list_empty(&entry->base.vm_status))
 898			list_add(&entry->base.vm_status, &vm->relocated);
 899		spin_unlock(&vm->status_lock);
 900		amdgpu_vm_invalidate_level(adev, vm, entry, level + 1);
 901	}
 902}
 903
 904/*
 905 * amdgpu_vm_update_directories - make sure that all directories are valid
 906 *
 907 * @adev: amdgpu_device pointer
 908 * @vm: requested vm
 909 *
 910 * Makes sure all directories are up to date.
 911 * Returns 0 for success, error for failure.
 
 
 912 */
 913int amdgpu_vm_update_directories(struct amdgpu_device *adev,
 914				 struct amdgpu_vm *vm)
 915{
 916	struct amdgpu_pte_update_params params;
 917	struct amdgpu_job *job;
 918	unsigned ndw = 0;
 919	int r = 0;
 920
 921	if (list_empty(&vm->relocated))
 922		return 0;
 923
 924restart:
 925	memset(&params, 0, sizeof(params));
 926	params.adev = adev;
 
 927
 928	if (vm->use_cpu_for_update) {
 929		r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM);
 930		if (unlikely(r))
 931			return r;
 932
 933		params.func = amdgpu_vm_cpu_set_ptes;
 934	} else {
 935		ndw = 512 * 8;
 936		r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
 937		if (r)
 938			return r;
 939
 940		params.ib = &job->ibs[0];
 941		params.func = amdgpu_vm_do_set_ptes;
 942	}
 943
 944	spin_lock(&vm->status_lock);
 945	while (!list_empty(&vm->relocated)) {
 946		struct amdgpu_vm_bo_base *bo_base, *parent;
 947		struct amdgpu_vm_pt *pt, *entry;
 948		struct amdgpu_bo *bo;
 949
 950		bo_base = list_first_entry(&vm->relocated,
 951					   struct amdgpu_vm_bo_base,
 952					   vm_status);
 953		list_del_init(&bo_base->vm_status);
 954		spin_unlock(&vm->status_lock);
 955
 956		bo = bo_base->bo->parent;
 957		if (!bo) {
 958			spin_lock(&vm->status_lock);
 959			continue;
 960		}
 961
 962		parent = list_first_entry(&bo->va, struct amdgpu_vm_bo_base,
 963					  bo_list);
 964		pt = container_of(parent, struct amdgpu_vm_pt, base);
 965		entry = container_of(bo_base, struct amdgpu_vm_pt, base);
 966
 967		amdgpu_vm_update_pde(&params, vm, pt, entry);
 968
 969		spin_lock(&vm->status_lock);
 970		if (!vm->use_cpu_for_update &&
 971		    (ndw - params.ib->length_dw) < 32)
 972			break;
 973	}
 974	spin_unlock(&vm->status_lock);
 975
 976	if (vm->use_cpu_for_update) {
 977		/* Flush HDP */
 978		mb();
 979		amdgpu_asic_flush_hdp(adev, NULL);
 980	} else if (params.ib->length_dw == 0) {
 981		amdgpu_job_free(job);
 982	} else {
 983		struct amdgpu_bo *root = vm->root.base.bo;
 984		struct amdgpu_ring *ring;
 985		struct dma_fence *fence;
 986
 987		ring = container_of(vm->entity.sched, struct amdgpu_ring,
 988				    sched);
 989
 990		amdgpu_ring_pad_ib(ring, params.ib);
 991		amdgpu_sync_resv(adev, &job->sync, root->tbo.resv,
 992				 AMDGPU_FENCE_OWNER_VM, false);
 993		WARN_ON(params.ib->length_dw > ndw);
 994		r = amdgpu_job_submit(job, ring, &vm->entity,
 995				      AMDGPU_FENCE_OWNER_VM, &fence);
 996		if (r)
 997			goto error;
 998
 999		amdgpu_bo_fence(root, fence, true);
1000		dma_fence_put(vm->last_update);
1001		vm->last_update = fence;
1002	}
1003
1004	if (!list_empty(&vm->relocated))
1005		goto restart;
1006
1007	return 0;
1008
1009error:
1010	amdgpu_vm_invalidate_level(adev, vm, &vm->root,
1011				   adev->vm_manager.root_level);
1012	amdgpu_job_free(job);
1013	return r;
1014}
1015
1016/**
1017 * amdgpu_vm_find_entry - find the entry for an address
1018 *
1019 * @p: see amdgpu_pte_update_params definition
1020 * @addr: virtual address in question
1021 * @entry: resulting entry or NULL
1022 * @parent: parent entry
1023 *
1024 * Find the vm_pt entry and it's parent for the given address.
1025 */
1026void amdgpu_vm_get_entry(struct amdgpu_pte_update_params *p, uint64_t addr,
1027			 struct amdgpu_vm_pt **entry,
1028			 struct amdgpu_vm_pt **parent)
 
 
 
1029{
1030	unsigned level = p->adev->vm_manager.root_level;
 
 
1031
1032	*parent = NULL;
1033	*entry = &p->vm->root;
1034	while ((*entry)->entries) {
1035		unsigned shift = amdgpu_vm_level_shift(p->adev, level++);
1036
1037		*parent = *entry;
1038		*entry = &(*entry)->entries[addr >> shift];
1039		addr &= (1ULL << shift) - 1;
1040	}
1041
1042	if (level != AMDGPU_VM_PTB)
1043		*entry = NULL;
1044}
1045
1046/**
1047 * amdgpu_vm_handle_huge_pages - handle updating the PD with huge pages
1048 *
1049 * @p: see amdgpu_pte_update_params definition
1050 * @entry: vm_pt entry to check
1051 * @parent: parent entry
1052 * @nptes: number of PTEs updated with this operation
1053 * @dst: destination address where the PTEs should point to
1054 * @flags: access flags fro the PTEs
1055 *
1056 * Check if we can update the PD with a huge page.
1057 */
1058static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p,
1059					struct amdgpu_vm_pt *entry,
1060					struct amdgpu_vm_pt *parent,
1061					unsigned nptes, uint64_t dst,
1062					uint64_t flags)
1063{
1064	uint64_t pde;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1065
1066	/* In the case of a mixed PT the PDE must point to it*/
1067	if (p->adev->asic_type >= CHIP_VEGA10 && !p->src &&
1068	    nptes == AMDGPU_VM_PTE_COUNT(p->adev)) {
1069		/* Set the huge page flag to stop scanning at this PDE */
1070		flags |= AMDGPU_PDE_PTE;
1071	}
1072
1073	if (!(flags & AMDGPU_PDE_PTE)) {
1074		if (entry->huge) {
1075			/* Add the entry to the relocated list to update it. */
1076			entry->huge = false;
1077			spin_lock(&p->vm->status_lock);
1078			list_move(&entry->base.vm_status, &p->vm->relocated);
1079			spin_unlock(&p->vm->status_lock);
1080		}
1081		return;
1082	}
1083
1084	entry->huge = true;
1085	amdgpu_gmc_get_vm_pde(p->adev, AMDGPU_VM_PDB0, &dst, &flags);
1086
1087	pde = (entry - parent->entries) * 8;
1088	if (parent->base.bo->shadow)
1089		p->func(p, parent->base.bo->shadow, pde, dst, 1, 0, flags);
1090	p->func(p, parent->base.bo, pde, dst, 1, 0, flags);
 
1091}
1092
1093/**
1094 * amdgpu_vm_update_ptes - make sure that page tables are valid
1095 *
1096 * @params: see amdgpu_pte_update_params definition
1097 * @vm: requested vm
1098 * @start: start of GPU address range
1099 * @end: end of GPU address range
1100 * @dst: destination address to map to, the next dst inside the function
1101 * @flags: mapping flags
1102 *
1103 * Update the page tables in the range @start - @end.
1104 * Returns 0 for success, -EINVAL for failure.
 
 
1105 */
1106static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
1107				  uint64_t start, uint64_t end,
1108				  uint64_t dst, uint64_t flags)
1109{
1110	struct amdgpu_device *adev = params->adev;
1111	const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1;
 
 
 
1112
1113	uint64_t addr, pe_start;
1114	struct amdgpu_bo *pt;
1115	unsigned nptes;
1116
1117	/* walk over the address space and update the page tables */
1118	for (addr = start; addr < end; addr += nptes,
1119	     dst += nptes * AMDGPU_GPU_PAGE_SIZE) {
1120		struct amdgpu_vm_pt *entry, *parent;
 
 
1121
1122		amdgpu_vm_get_entry(params, addr, &entry, &parent);
1123		if (!entry)
1124			return -ENOENT;
1125
1126		if ((addr & ~mask) == (end & ~mask))
1127			nptes = end - addr;
1128		else
1129			nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask);
1130
1131		amdgpu_vm_handle_huge_pages(params, entry, parent,
1132					    nptes, dst, flags);
1133		/* We don't need to update PTEs for huge pages */
1134		if (entry->huge)
1135			continue;
 
1136
1137		pt = entry->base.bo;
1138		pe_start = (addr & mask) * 8;
1139		if (pt->shadow)
1140			params->func(params, pt->shadow, pe_start, dst, nptes,
1141				     AMDGPU_GPU_PAGE_SIZE, flags);
1142		params->func(params, pt, pe_start, dst, nptes,
1143			     AMDGPU_GPU_PAGE_SIZE, flags);
1144	}
1145
1146	return 0;
1147}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1148
1149/*
1150 * amdgpu_vm_frag_ptes - add fragment information to PTEs
1151 *
1152 * @params: see amdgpu_pte_update_params definition
1153 * @vm: requested vm
1154 * @start: first PTE to handle
1155 * @end: last PTE to handle
1156 * @dst: addr those PTEs should point to
1157 * @flags: hw mapping flags
1158 * Returns 0 for success, -EINVAL for failure.
1159 */
1160static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params	*params,
1161				uint64_t start, uint64_t end,
1162				uint64_t dst, uint64_t flags)
1163{
1164	/**
1165	 * The MC L1 TLB supports variable sized pages, based on a fragment
1166	 * field in the PTE. When this field is set to a non-zero value, page
1167	 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
1168	 * flags are considered valid for all PTEs within the fragment range
1169	 * and corresponding mappings are assumed to be physically contiguous.
1170	 *
1171	 * The L1 TLB can store a single PTE for the whole fragment,
1172	 * significantly increasing the space available for translation
1173	 * caching. This leads to large improvements in throughput when the
1174	 * TLB is under pressure.
1175	 *
1176	 * The L2 TLB distributes small and large fragments into two
1177	 * asymmetric partitions. The large fragment cache is significantly
1178	 * larger. Thus, we try to use large fragments wherever possible.
1179	 * Userspace can support this by aligning virtual base address and
1180	 * allocation size to the fragment size.
1181	 */
1182	unsigned max_frag = params->adev->vm_manager.fragment_size;
1183	int r;
1184
1185	/* system pages are non continuously */
1186	if (params->src || !(flags & AMDGPU_PTE_VALID))
1187		return amdgpu_vm_update_ptes(params, start, end, dst, flags);
 
 
 
1188
1189	while (start != end) {
1190		uint64_t frag_flags, frag_end;
1191		unsigned frag;
1192
1193		/* This intentionally wraps around if no bit is set */
1194		frag = min((unsigned)ffs(start) - 1,
1195			   (unsigned)fls64(end - start) - 1);
1196		if (frag >= max_frag) {
1197			frag_flags = AMDGPU_PTE_FRAG(max_frag);
1198			frag_end = end & ~((1ULL << max_frag) - 1);
1199		} else {
1200			frag_flags = AMDGPU_PTE_FRAG(frag);
1201			frag_end = start + (1 << frag);
1202		}
1203
1204		r = amdgpu_vm_update_ptes(params, start, frag_end, dst,
1205					  flags | frag_flags);
1206		if (r)
1207			return r;
1208
1209		dst += (frag_end - start) * AMDGPU_GPU_PAGE_SIZE;
1210		start = frag_end;
1211	}
1212
1213	return 0;
1214}
1215
1216/**
1217 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
1218 *
1219 * @adev: amdgpu_device pointer
1220 * @exclusive: fence we need to sync to
1221 * @pages_addr: DMA addresses to use for mapping
1222 * @vm: requested vm
1223 * @start: start of mapped range
1224 * @last: last mapped entry
1225 * @flags: flags for the entries
1226 * @addr: addr to set the area to
1227 * @fence: optional resulting fence
1228 *
1229 * Fill in the page table entries between @start and @last.
1230 * Returns 0 for success, -EINVAL for failure.
 
 
1231 */
1232static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1233				       struct dma_fence *exclusive,
1234				       dma_addr_t *pages_addr,
1235				       struct amdgpu_vm *vm,
1236				       uint64_t start, uint64_t last,
1237				       uint64_t flags, uint64_t addr,
1238				       struct dma_fence **fence)
1239{
1240	struct amdgpu_ring *ring;
1241	void *owner = AMDGPU_FENCE_OWNER_VM;
1242	unsigned nptes, ncmds, ndw;
1243	struct amdgpu_job *job;
1244	struct amdgpu_pte_update_params params;
1245	struct dma_fence *f = NULL;
1246	int r;
1247
1248	memset(&params, 0, sizeof(params));
1249	params.adev = adev;
1250	params.vm = vm;
 
1251
1252	/* sync to everything on unmapping */
1253	if (!(flags & AMDGPU_PTE_VALID))
1254		owner = AMDGPU_FENCE_OWNER_UNDEFINED;
1255
1256	if (vm->use_cpu_for_update) {
1257		/* params.src is used as flag to indicate system Memory */
1258		if (pages_addr)
1259			params.src = ~0;
1260
1261		/* Wait for PT BOs to be free. PTs share the same resv. object
1262		 * as the root PD BO
1263		 */
1264		r = amdgpu_vm_wait_pd(adev, vm, owner);
1265		if (unlikely(r))
1266			return r;
1267
1268		params.func = amdgpu_vm_cpu_set_ptes;
1269		params.pages_addr = pages_addr;
1270		return amdgpu_vm_frag_ptes(&params, start, last + 1,
1271					   addr, flags);
1272	}
1273
1274	ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
1275
1276	nptes = last - start + 1;
1277
1278	/*
1279	 * reserve space for two commands every (1 << BLOCK_SIZE)
1280	 *  entries or 2k dwords (whatever is smaller)
1281         *
1282         * The second command is for the shadow pagetables.
1283	 */
1284	if (vm->root.base.bo->shadow)
1285		ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1) * 2;
1286	else
1287		ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1);
1288
1289	/* padding, etc. */
1290	ndw = 64;
1291
1292	if (pages_addr) {
1293		/* copy commands needed */
1294		ndw += ncmds * adev->vm_manager.vm_pte_funcs->copy_pte_num_dw;
1295
1296		/* and also PTEs */
1297		ndw += nptes * 2;
1298
1299		params.func = amdgpu_vm_do_copy_ptes;
1300
1301	} else {
1302		/* set page commands needed */
1303		ndw += ncmds * 10;
1304
1305		/* extra commands for begin/end fragments */
1306		ndw += 2 * 10 * adev->vm_manager.fragment_size;
1307
1308		params.func = amdgpu_vm_do_set_ptes;
1309	}
1310
1311	r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
1312	if (r)
1313		return r;
1314
1315	params.ib = &job->ibs[0];
1316
1317	if (pages_addr) {
1318		uint64_t *pte;
1319		unsigned i;
1320
1321		/* Put the PTEs at the end of the IB. */
1322		i = ndw - nptes * 2;
1323		pte= (uint64_t *)&(job->ibs->ptr[i]);
1324		params.src = job->ibs->gpu_addr + i * 4;
1325
1326		for (i = 0; i < nptes; ++i) {
1327			pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i *
1328						    AMDGPU_GPU_PAGE_SIZE);
1329			pte[i] |= flags;
1330		}
1331		addr = 0;
1332	}
1333
1334	r = amdgpu_sync_fence(adev, &job->sync, exclusive, false);
1335	if (r)
1336		goto error_free;
1337
1338	r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv,
1339			     owner, false);
1340	if (r)
1341		goto error_free;
1342
1343	r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv);
1344	if (r)
1345		goto error_free;
1346
1347	r = amdgpu_vm_frag_ptes(&params, start, last + 1, addr, flags);
1348	if (r)
1349		goto error_free;
1350
1351	amdgpu_ring_pad_ib(ring, params.ib);
1352	WARN_ON(params.ib->length_dw > ndw);
1353	r = amdgpu_job_submit(job, ring, &vm->entity,
1354			      AMDGPU_FENCE_OWNER_VM, &f);
1355	if (r)
1356		goto error_free;
1357
1358	amdgpu_bo_fence(vm->root.base.bo, f, true);
1359	dma_fence_put(*fence);
1360	*fence = f;
1361	return 0;
1362
1363error_free:
1364	amdgpu_job_free(job);
1365	return r;
1366}
1367
1368/**
1369 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
1370 *
1371 * @adev: amdgpu_device pointer
1372 * @exclusive: fence we need to sync to
1373 * @pages_addr: DMA addresses to use for mapping
1374 * @vm: requested vm
1375 * @mapping: mapped range and flags to use for the update
1376 * @flags: HW flags for the mapping
 
1377 * @nodes: array of drm_mm_nodes with the MC addresses
1378 * @fence: optional resulting fence
1379 *
1380 * Split the mapping into smaller chunks so that each update fits
1381 * into a SDMA IB.
1382 * Returns 0 for success, -EINVAL for failure.
 
 
1383 */
1384static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
1385				      struct dma_fence *exclusive,
1386				      dma_addr_t *pages_addr,
1387				      struct amdgpu_vm *vm,
1388				      struct amdgpu_bo_va_mapping *mapping,
1389				      uint64_t flags,
 
1390				      struct drm_mm_node *nodes,
1391				      struct dma_fence **fence)
1392{
1393	unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size;
1394	uint64_t pfn, start = mapping->start;
1395	int r;
1396
1397	/* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1398	 * but in case of something, we filter the flags in first place
1399	 */
1400	if (!(mapping->flags & AMDGPU_PTE_READABLE))
1401		flags &= ~AMDGPU_PTE_READABLE;
1402	if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1403		flags &= ~AMDGPU_PTE_WRITEABLE;
1404
1405	flags &= ~AMDGPU_PTE_EXECUTABLE;
1406	flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
1407
1408	flags &= ~AMDGPU_PTE_MTYPE_MASK;
1409	flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK);
 
 
 
 
 
1410
1411	if ((mapping->flags & AMDGPU_PTE_PRT) &&
1412	    (adev->asic_type >= CHIP_VEGA10)) {
1413		flags |= AMDGPU_PTE_PRT;
 
 
 
 
 
1414		flags &= ~AMDGPU_PTE_VALID;
1415	}
1416
1417	trace_amdgpu_vm_bo_update(mapping);
1418
1419	pfn = mapping->offset >> PAGE_SHIFT;
1420	if (nodes) {
1421		while (pfn >= nodes->size) {
1422			pfn -= nodes->size;
1423			++nodes;
1424		}
1425	}
1426
1427	do {
1428		dma_addr_t *dma_addr = NULL;
1429		uint64_t max_entries;
1430		uint64_t addr, last;
1431
1432		if (nodes) {
1433			addr = nodes->start << PAGE_SHIFT;
1434			max_entries = (nodes->size - pfn) *
1435				(PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
1436		} else {
1437			addr = 0;
1438			max_entries = S64_MAX;
1439		}
1440
1441		if (pages_addr) {
1442			uint64_t count;
1443
1444			max_entries = min(max_entries, 16ull * 1024ull);
1445			for (count = 1; count < max_entries; ++count) {
 
1446				uint64_t idx = pfn + count;
1447
1448				if (pages_addr[idx] !=
1449				    (pages_addr[idx - 1] + PAGE_SIZE))
1450					break;
1451			}
1452
1453			if (count < min_linear_pages) {
1454				addr = pfn << PAGE_SHIFT;
1455				dma_addr = pages_addr;
1456			} else {
1457				addr = pages_addr[pfn];
1458				max_entries = count;
1459			}
1460
1461		} else if (flags & AMDGPU_PTE_VALID) {
1462			addr += adev->vm_manager.vram_base_offset;
1463			addr += pfn << PAGE_SHIFT;
1464		}
1465
1466		last = min((uint64_t)mapping->last, start + max_entries - 1);
1467		r = amdgpu_vm_bo_update_mapping(adev, exclusive, dma_addr, vm,
1468						start, last, flags, addr,
1469						fence);
1470		if (r)
1471			return r;
1472
1473		pfn += last - start + 1;
1474		if (nodes && nodes->size == pfn) {
1475			pfn = 0;
1476			++nodes;
1477		}
1478		start = last + 1;
1479
1480	} while (unlikely(start != mapping->last + 1));
1481
1482	return 0;
1483}
1484
1485/**
1486 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1487 *
1488 * @adev: amdgpu_device pointer
1489 * @bo_va: requested BO and VM object
1490 * @clear: if true clear the entries
1491 *
1492 * Fill in the page table entries for @bo_va.
1493 * Returns 0 for success, -EINVAL for failure.
 
 
1494 */
1495int amdgpu_vm_bo_update(struct amdgpu_device *adev,
1496			struct amdgpu_bo_va *bo_va,
1497			bool clear)
1498{
1499	struct amdgpu_bo *bo = bo_va->base.bo;
1500	struct amdgpu_vm *vm = bo_va->base.vm;
1501	struct amdgpu_bo_va_mapping *mapping;
1502	dma_addr_t *pages_addr = NULL;
1503	struct ttm_mem_reg *mem;
1504	struct drm_mm_node *nodes;
1505	struct dma_fence *exclusive, **last_update;
1506	uint64_t flags;
 
1507	int r;
1508
1509	if (clear || !bo_va->base.bo) {
1510		mem = NULL;
1511		nodes = NULL;
1512		exclusive = NULL;
1513	} else {
1514		struct ttm_dma_tt *ttm;
1515
1516		mem = &bo_va->base.bo->tbo.mem;
1517		nodes = mem->mm_node;
1518		if (mem->mem_type == TTM_PL_TT) {
1519			ttm = container_of(bo_va->base.bo->tbo.ttm,
1520					   struct ttm_dma_tt, ttm);
1521			pages_addr = ttm->dma_address;
1522		}
1523		exclusive = reservation_object_get_excl(bo->tbo.resv);
1524	}
1525
1526	if (bo)
1527		flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1528	else
 
1529		flags = 0x0;
 
1530
1531	if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
1532		last_update = &vm->last_update;
1533	else
1534		last_update = &bo_va->last_pt_update;
1535
1536	if (!clear && bo_va->base.moved) {
1537		bo_va->base.moved = false;
1538		list_splice_init(&bo_va->valids, &bo_va->invalids);
1539
1540	} else if (bo_va->cleared != clear) {
1541		list_splice_init(&bo_va->valids, &bo_va->invalids);
1542	}
1543
1544	list_for_each_entry(mapping, &bo_va->invalids, list) {
1545		r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm,
1546					       mapping, flags, nodes,
1547					       last_update);
1548		if (r)
1549			return r;
1550	}
1551
1552	if (vm->use_cpu_for_update) {
1553		/* Flush HDP */
1554		mb();
1555		amdgpu_asic_flush_hdp(adev, NULL);
1556	}
1557
1558	spin_lock(&vm->status_lock);
1559	list_del_init(&bo_va->base.vm_status);
1560	spin_unlock(&vm->status_lock);
 
 
 
 
 
 
 
 
 
 
 
1561
1562	list_splice_init(&bo_va->invalids, &bo_va->valids);
1563	bo_va->cleared = clear;
1564
1565	if (trace_amdgpu_vm_bo_mapping_enabled()) {
1566		list_for_each_entry(mapping, &bo_va->valids, list)
1567			trace_amdgpu_vm_bo_mapping(mapping);
1568	}
1569
1570	return 0;
1571}
1572
1573/**
1574 * amdgpu_vm_update_prt_state - update the global PRT state
 
 
1575 */
1576static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1577{
1578	unsigned long flags;
1579	bool enable;
1580
1581	spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1582	enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1583	adev->gmc.gmc_funcs->set_prt(adev, enable);
1584	spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1585}
1586
1587/**
1588 * amdgpu_vm_prt_get - add a PRT user
 
 
1589 */
1590static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1591{
1592	if (!adev->gmc.gmc_funcs->set_prt)
1593		return;
1594
1595	if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1596		amdgpu_vm_update_prt_state(adev);
1597}
1598
1599/**
1600 * amdgpu_vm_prt_put - drop a PRT user
 
 
1601 */
1602static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1603{
1604	if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1605		amdgpu_vm_update_prt_state(adev);
1606}
1607
1608/**
1609 * amdgpu_vm_prt_cb - callback for updating the PRT status
 
 
 
1610 */
1611static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1612{
1613	struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1614
1615	amdgpu_vm_prt_put(cb->adev);
1616	kfree(cb);
1617}
1618
1619/**
1620 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
 
 
 
1621 */
1622static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1623				 struct dma_fence *fence)
1624{
1625	struct amdgpu_prt_cb *cb;
1626
1627	if (!adev->gmc.gmc_funcs->set_prt)
1628		return;
1629
1630	cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1631	if (!cb) {
1632		/* Last resort when we are OOM */
1633		if (fence)
1634			dma_fence_wait(fence, false);
1635
1636		amdgpu_vm_prt_put(adev);
1637	} else {
1638		cb->adev = adev;
1639		if (!fence || dma_fence_add_callback(fence, &cb->cb,
1640						     amdgpu_vm_prt_cb))
1641			amdgpu_vm_prt_cb(fence, &cb->cb);
1642	}
1643}
1644
1645/**
1646 * amdgpu_vm_free_mapping - free a mapping
1647 *
1648 * @adev: amdgpu_device pointer
1649 * @vm: requested vm
1650 * @mapping: mapping to be freed
1651 * @fence: fence of the unmap operation
1652 *
1653 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1654 */
1655static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1656				   struct amdgpu_vm *vm,
1657				   struct amdgpu_bo_va_mapping *mapping,
1658				   struct dma_fence *fence)
1659{
1660	if (mapping->flags & AMDGPU_PTE_PRT)
1661		amdgpu_vm_add_prt_cb(adev, fence);
1662	kfree(mapping);
1663}
1664
1665/**
1666 * amdgpu_vm_prt_fini - finish all prt mappings
1667 *
1668 * @adev: amdgpu_device pointer
1669 * @vm: requested vm
1670 *
1671 * Register a cleanup callback to disable PRT support after VM dies.
1672 */
1673static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1674{
1675	struct reservation_object *resv = vm->root.base.bo->tbo.resv;
1676	struct dma_fence *excl, **shared;
1677	unsigned i, shared_count;
1678	int r;
1679
1680	r = reservation_object_get_fences_rcu(resv, &excl,
1681					      &shared_count, &shared);
1682	if (r) {
1683		/* Not enough memory to grab the fence list, as last resort
1684		 * block for all the fences to complete.
1685		 */
1686		reservation_object_wait_timeout_rcu(resv, true, false,
1687						    MAX_SCHEDULE_TIMEOUT);
1688		return;
1689	}
1690
1691	/* Add a callback for each fence in the reservation object */
1692	amdgpu_vm_prt_get(adev);
1693	amdgpu_vm_add_prt_cb(adev, excl);
1694
1695	for (i = 0; i < shared_count; ++i) {
1696		amdgpu_vm_prt_get(adev);
1697		amdgpu_vm_add_prt_cb(adev, shared[i]);
1698	}
1699
1700	kfree(shared);
1701}
1702
1703/**
1704 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1705 *
1706 * @adev: amdgpu_device pointer
1707 * @vm: requested vm
1708 * @fence: optional resulting fence (unchanged if no work needed to be done
1709 * or if an error occurred)
1710 *
1711 * Make sure all freed BOs are cleared in the PT.
1712 * Returns 0 for success.
1713 *
1714 * PTs have to be reserved and mutex must be locked!
 
 
 
 
1715 */
1716int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1717			  struct amdgpu_vm *vm,
1718			  struct dma_fence **fence)
1719{
1720	struct amdgpu_bo_va_mapping *mapping;
1721	uint64_t init_pte_value = 0;
1722	struct dma_fence *f = NULL;
1723	int r;
1724
1725	while (!list_empty(&vm->freed)) {
1726		mapping = list_first_entry(&vm->freed,
1727			struct amdgpu_bo_va_mapping, list);
1728		list_del(&mapping->list);
1729
1730		if (vm->pte_support_ats && mapping->start < AMDGPU_VA_HOLE_START)
 
1731			init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
1732
1733		r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm,
1734						mapping->start, mapping->last,
1735						init_pte_value, 0, &f);
1736		amdgpu_vm_free_mapping(adev, vm, mapping, f);
1737		if (r) {
1738			dma_fence_put(f);
1739			return r;
1740		}
1741	}
1742
1743	if (fence && f) {
1744		dma_fence_put(*fence);
1745		*fence = f;
1746	} else {
1747		dma_fence_put(f);
1748	}
1749
1750	return 0;
1751
1752}
1753
1754/**
1755 * amdgpu_vm_handle_moved - handle moved BOs in the PT
1756 *
1757 * @adev: amdgpu_device pointer
1758 * @vm: requested vm
1759 * @sync: sync object to add fences to
1760 *
1761 * Make sure all BOs which are moved are updated in the PTs.
1762 * Returns 0 for success.
 
 
1763 *
1764 * PTs have to be reserved!
1765 */
1766int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
1767			   struct amdgpu_vm *vm)
1768{
 
 
1769	bool clear;
1770	int r = 0;
1771
1772	spin_lock(&vm->status_lock);
1773	while (!list_empty(&vm->moved)) {
1774		struct amdgpu_bo_va *bo_va;
1775		struct reservation_object *resv;
1776
1777		bo_va = list_first_entry(&vm->moved,
1778			struct amdgpu_bo_va, base.vm_status);
1779		spin_unlock(&vm->status_lock);
1780
1781		resv = bo_va->base.bo->tbo.resv;
 
 
 
 
 
1782
1783		/* Per VM BOs never need to bo cleared in the page tables */
1784		if (resv == vm->root.base.bo->tbo.resv)
1785			clear = false;
1786		/* Try to reserve the BO to avoid clearing its ptes */
1787		else if (!amdgpu_vm_debug && reservation_object_trylock(resv))
1788			clear = false;
1789		/* Somebody else is using the BO right now */
1790		else
1791			clear = true;
1792
1793		r = amdgpu_vm_bo_update(adev, bo_va, clear);
1794		if (r)
1795			return r;
1796
1797		if (!clear && resv != vm->root.base.bo->tbo.resv)
1798			reservation_object_unlock(resv);
1799
1800		spin_lock(&vm->status_lock);
1801	}
1802	spin_unlock(&vm->status_lock);
1803
1804	return r;
1805}
1806
1807/**
1808 * amdgpu_vm_bo_add - add a bo to a specific vm
1809 *
1810 * @adev: amdgpu_device pointer
1811 * @vm: requested vm
1812 * @bo: amdgpu buffer object
1813 *
1814 * Add @bo into the requested vm.
1815 * Add @bo to the list of bos associated with the vm
1816 * Returns newly added bo_va or NULL for failure
 
 
1817 *
1818 * Object has to be reserved!
1819 */
1820struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1821				      struct amdgpu_vm *vm,
1822				      struct amdgpu_bo *bo)
1823{
1824	struct amdgpu_bo_va *bo_va;
1825
1826	bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
1827	if (bo_va == NULL) {
1828		return NULL;
1829	}
1830	bo_va->base.vm = vm;
1831	bo_va->base.bo = bo;
1832	INIT_LIST_HEAD(&bo_va->base.bo_list);
1833	INIT_LIST_HEAD(&bo_va->base.vm_status);
1834
1835	bo_va->ref_count = 1;
1836	INIT_LIST_HEAD(&bo_va->valids);
1837	INIT_LIST_HEAD(&bo_va->invalids);
1838
1839	if (!bo)
1840		return bo_va;
1841
1842	list_add_tail(&bo_va->base.bo_list, &bo->va);
1843
1844	if (bo->tbo.resv != vm->root.base.bo->tbo.resv)
1845		return bo_va;
1846
1847	if (bo->preferred_domains &
1848	    amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type))
1849		return bo_va;
1850
1851	/*
1852	 * We checked all the prerequisites, but it looks like this per VM BO
1853	 * is currently evicted. add the BO to the evicted list to make sure it
1854	 * is validated on next VM use to avoid fault.
1855	 * */
1856	spin_lock(&vm->status_lock);
1857	list_move_tail(&bo_va->base.vm_status, &vm->evicted);
1858	spin_unlock(&vm->status_lock);
1859
1860	return bo_va;
1861}
1862
1863
1864/**
1865 * amdgpu_vm_bo_insert_mapping - insert a new mapping
1866 *
1867 * @adev: amdgpu_device pointer
1868 * @bo_va: bo_va to store the address
1869 * @mapping: the mapping to insert
1870 *
1871 * Insert a new mapping into all structures.
1872 */
1873static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
1874				    struct amdgpu_bo_va *bo_va,
1875				    struct amdgpu_bo_va_mapping *mapping)
1876{
1877	struct amdgpu_vm *vm = bo_va->base.vm;
1878	struct amdgpu_bo *bo = bo_va->base.bo;
1879
1880	mapping->bo_va = bo_va;
1881	list_add(&mapping->list, &bo_va->invalids);
1882	amdgpu_vm_it_insert(mapping, &vm->va);
1883
1884	if (mapping->flags & AMDGPU_PTE_PRT)
1885		amdgpu_vm_prt_get(adev);
1886
1887	if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
1888		spin_lock(&vm->status_lock);
1889		if (list_empty(&bo_va->base.vm_status))
1890			list_add(&bo_va->base.vm_status, &vm->moved);
1891		spin_unlock(&vm->status_lock);
1892	}
1893	trace_amdgpu_vm_bo_map(bo_va, mapping);
1894}
1895
1896/**
1897 * amdgpu_vm_bo_map - map bo inside a vm
1898 *
1899 * @adev: amdgpu_device pointer
1900 * @bo_va: bo_va to store the address
1901 * @saddr: where to map the BO
1902 * @offset: requested offset in the BO
 
1903 * @flags: attributes of pages (read/write/valid/etc.)
1904 *
1905 * Add a mapping of the BO at the specefied addr into the VM.
1906 * Returns 0 for success, error for failure.
 
 
1907 *
1908 * Object has to be reserved and unreserved outside!
1909 */
1910int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1911		     struct amdgpu_bo_va *bo_va,
1912		     uint64_t saddr, uint64_t offset,
1913		     uint64_t size, uint64_t flags)
1914{
1915	struct amdgpu_bo_va_mapping *mapping, *tmp;
1916	struct amdgpu_bo *bo = bo_va->base.bo;
1917	struct amdgpu_vm *vm = bo_va->base.vm;
1918	uint64_t eaddr;
1919
1920	/* validate the parameters */
1921	if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
1922	    size == 0 || size & AMDGPU_GPU_PAGE_MASK)
1923		return -EINVAL;
1924
1925	/* make sure object fit at this offset */
1926	eaddr = saddr + size - 1;
1927	if (saddr >= eaddr ||
1928	    (bo && offset + size > amdgpu_bo_size(bo)))
1929		return -EINVAL;
1930
1931	saddr /= AMDGPU_GPU_PAGE_SIZE;
1932	eaddr /= AMDGPU_GPU_PAGE_SIZE;
1933
1934	tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1935	if (tmp) {
1936		/* bo and tmp overlap, invalid addr */
1937		dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1938			"0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
1939			tmp->start, tmp->last + 1);
1940		return -EINVAL;
1941	}
1942
1943	mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1944	if (!mapping)
1945		return -ENOMEM;
1946
1947	mapping->start = saddr;
1948	mapping->last = eaddr;
1949	mapping->offset = offset;
1950	mapping->flags = flags;
1951
1952	amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
1953
1954	return 0;
1955}
1956
1957/**
1958 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
1959 *
1960 * @adev: amdgpu_device pointer
1961 * @bo_va: bo_va to store the address
1962 * @saddr: where to map the BO
1963 * @offset: requested offset in the BO
 
1964 * @flags: attributes of pages (read/write/valid/etc.)
1965 *
1966 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
1967 * mappings as we do so.
1968 * Returns 0 for success, error for failure.
 
 
1969 *
1970 * Object has to be reserved and unreserved outside!
1971 */
1972int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
1973			     struct amdgpu_bo_va *bo_va,
1974			     uint64_t saddr, uint64_t offset,
1975			     uint64_t size, uint64_t flags)
1976{
1977	struct amdgpu_bo_va_mapping *mapping;
1978	struct amdgpu_bo *bo = bo_va->base.bo;
1979	uint64_t eaddr;
1980	int r;
1981
1982	/* validate the parameters */
1983	if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
1984	    size == 0 || size & AMDGPU_GPU_PAGE_MASK)
1985		return -EINVAL;
1986
1987	/* make sure object fit at this offset */
1988	eaddr = saddr + size - 1;
1989	if (saddr >= eaddr ||
1990	    (bo && offset + size > amdgpu_bo_size(bo)))
1991		return -EINVAL;
1992
1993	/* Allocate all the needed memory */
1994	mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1995	if (!mapping)
1996		return -ENOMEM;
1997
1998	r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
1999	if (r) {
2000		kfree(mapping);
2001		return r;
2002	}
2003
2004	saddr /= AMDGPU_GPU_PAGE_SIZE;
2005	eaddr /= AMDGPU_GPU_PAGE_SIZE;
2006
2007	mapping->start = saddr;
2008	mapping->last = eaddr;
2009	mapping->offset = offset;
2010	mapping->flags = flags;
2011
2012	amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2013
2014	return 0;
2015}
2016
2017/**
2018 * amdgpu_vm_bo_unmap - remove bo mapping from vm
2019 *
2020 * @adev: amdgpu_device pointer
2021 * @bo_va: bo_va to remove the address from
2022 * @saddr: where to the BO is mapped
2023 *
2024 * Remove a mapping of the BO at the specefied addr from the VM.
2025 * Returns 0 for success, error for failure.
 
 
2026 *
2027 * Object has to be reserved and unreserved outside!
2028 */
2029int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2030		       struct amdgpu_bo_va *bo_va,
2031		       uint64_t saddr)
2032{
2033	struct amdgpu_bo_va_mapping *mapping;
2034	struct amdgpu_vm *vm = bo_va->base.vm;
2035	bool valid = true;
2036
2037	saddr /= AMDGPU_GPU_PAGE_SIZE;
2038
2039	list_for_each_entry(mapping, &bo_va->valids, list) {
2040		if (mapping->start == saddr)
2041			break;
2042	}
2043
2044	if (&mapping->list == &bo_va->valids) {
2045		valid = false;
2046
2047		list_for_each_entry(mapping, &bo_va->invalids, list) {
2048			if (mapping->start == saddr)
2049				break;
2050		}
2051
2052		if (&mapping->list == &bo_va->invalids)
2053			return -ENOENT;
2054	}
2055
2056	list_del(&mapping->list);
2057	amdgpu_vm_it_remove(mapping, &vm->va);
2058	mapping->bo_va = NULL;
2059	trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2060
2061	if (valid)
2062		list_add(&mapping->list, &vm->freed);
2063	else
2064		amdgpu_vm_free_mapping(adev, vm, mapping,
2065				       bo_va->last_pt_update);
2066
2067	return 0;
2068}
2069
2070/**
2071 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
2072 *
2073 * @adev: amdgpu_device pointer
2074 * @vm: VM structure to use
2075 * @saddr: start of the range
2076 * @size: size of the range
2077 *
2078 * Remove all mappings in a range, split them as appropriate.
2079 * Returns 0 for success, error for failure.
 
 
2080 */
2081int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
2082				struct amdgpu_vm *vm,
2083				uint64_t saddr, uint64_t size)
2084{
2085	struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
2086	LIST_HEAD(removed);
2087	uint64_t eaddr;
2088
2089	eaddr = saddr + size - 1;
2090	saddr /= AMDGPU_GPU_PAGE_SIZE;
2091	eaddr /= AMDGPU_GPU_PAGE_SIZE;
2092
2093	/* Allocate all the needed memory */
2094	before = kzalloc(sizeof(*before), GFP_KERNEL);
2095	if (!before)
2096		return -ENOMEM;
2097	INIT_LIST_HEAD(&before->list);
2098
2099	after = kzalloc(sizeof(*after), GFP_KERNEL);
2100	if (!after) {
2101		kfree(before);
2102		return -ENOMEM;
2103	}
2104	INIT_LIST_HEAD(&after->list);
2105
2106	/* Now gather all removed mappings */
2107	tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2108	while (tmp) {
2109		/* Remember mapping split at the start */
2110		if (tmp->start < saddr) {
2111			before->start = tmp->start;
2112			before->last = saddr - 1;
2113			before->offset = tmp->offset;
2114			before->flags = tmp->flags;
2115			list_add(&before->list, &tmp->list);
 
2116		}
2117
2118		/* Remember mapping split at the end */
2119		if (tmp->last > eaddr) {
2120			after->start = eaddr + 1;
2121			after->last = tmp->last;
2122			after->offset = tmp->offset;
2123			after->offset += after->start - tmp->start;
2124			after->flags = tmp->flags;
2125			list_add(&after->list, &tmp->list);
 
2126		}
2127
2128		list_del(&tmp->list);
2129		list_add(&tmp->list, &removed);
2130
2131		tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
2132	}
2133
2134	/* And free them up */
2135	list_for_each_entry_safe(tmp, next, &removed, list) {
2136		amdgpu_vm_it_remove(tmp, &vm->va);
2137		list_del(&tmp->list);
2138
2139		if (tmp->start < saddr)
2140		    tmp->start = saddr;
2141		if (tmp->last > eaddr)
2142		    tmp->last = eaddr;
2143
2144		tmp->bo_va = NULL;
2145		list_add(&tmp->list, &vm->freed);
2146		trace_amdgpu_vm_bo_unmap(NULL, tmp);
2147	}
2148
2149	/* Insert partial mapping before the range */
2150	if (!list_empty(&before->list)) {
2151		amdgpu_vm_it_insert(before, &vm->va);
2152		if (before->flags & AMDGPU_PTE_PRT)
2153			amdgpu_vm_prt_get(adev);
2154	} else {
2155		kfree(before);
2156	}
2157
2158	/* Insert partial mapping after the range */
2159	if (!list_empty(&after->list)) {
2160		amdgpu_vm_it_insert(after, &vm->va);
2161		if (after->flags & AMDGPU_PTE_PRT)
2162			amdgpu_vm_prt_get(adev);
2163	} else {
2164		kfree(after);
2165	}
2166
2167	return 0;
2168}
2169
2170/**
2171 * amdgpu_vm_bo_lookup_mapping - find mapping by address
2172 *
2173 * @vm: the requested VM
 
2174 *
2175 * Find a mapping by it's address.
 
 
 
 
2176 */
2177struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
2178							 uint64_t addr)
2179{
2180	return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
2181}
2182
2183/**
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2184 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
2185 *
2186 * @adev: amdgpu_device pointer
2187 * @bo_va: requested bo_va
2188 *
2189 * Remove @bo_va->bo from the requested vm.
2190 *
2191 * Object have to be reserved!
2192 */
2193void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2194		      struct amdgpu_bo_va *bo_va)
2195{
2196	struct amdgpu_bo_va_mapping *mapping, *next;
 
2197	struct amdgpu_vm *vm = bo_va->base.vm;
 
2198
2199	list_del(&bo_va->base.bo_list);
 
 
 
 
 
 
 
2200
2201	spin_lock(&vm->status_lock);
 
 
 
 
 
2202	list_del(&bo_va->base.vm_status);
2203	spin_unlock(&vm->status_lock);
2204
2205	list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2206		list_del(&mapping->list);
2207		amdgpu_vm_it_remove(mapping, &vm->va);
2208		mapping->bo_va = NULL;
2209		trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2210		list_add(&mapping->list, &vm->freed);
2211	}
2212	list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2213		list_del(&mapping->list);
2214		amdgpu_vm_it_remove(mapping, &vm->va);
2215		amdgpu_vm_free_mapping(adev, vm, mapping,
2216				       bo_va->last_pt_update);
2217	}
2218
2219	dma_fence_put(bo_va->last_pt_update);
 
 
 
 
 
 
 
 
2220	kfree(bo_va);
2221}
2222
2223/**
2224 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2225 *
2226 * @adev: amdgpu_device pointer
2227 * @vm: requested vm
2228 * @bo: amdgpu buffer object
 
2229 *
2230 * Mark @bo as invalid.
2231 */
2232void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2233			     struct amdgpu_bo *bo, bool evicted)
2234{
2235	struct amdgpu_vm_bo_base *bo_base;
2236
2237	list_for_each_entry(bo_base, &bo->va, bo_list) {
 
 
 
 
2238		struct amdgpu_vm *vm = bo_base->vm;
2239
2240		bo_base->moved = true;
2241		if (evicted && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
2242			spin_lock(&bo_base->vm->status_lock);
2243			if (bo->tbo.type == ttm_bo_type_kernel)
2244				list_move(&bo_base->vm_status, &vm->evicted);
2245			else
2246				list_move_tail(&bo_base->vm_status,
2247					       &vm->evicted);
2248			spin_unlock(&bo_base->vm->status_lock);
2249			continue;
2250		}
2251
2252		if (bo->tbo.type == ttm_bo_type_kernel) {
2253			spin_lock(&bo_base->vm->status_lock);
2254			if (list_empty(&bo_base->vm_status))
2255				list_add(&bo_base->vm_status, &vm->relocated);
2256			spin_unlock(&bo_base->vm->status_lock);
2257			continue;
2258		}
2259
2260		spin_lock(&bo_base->vm->status_lock);
2261		if (list_empty(&bo_base->vm_status))
2262			list_add(&bo_base->vm_status, &vm->moved);
2263		spin_unlock(&bo_base->vm->status_lock);
 
 
2264	}
2265}
2266
 
 
 
 
 
 
 
 
2267static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2268{
2269	/* Total bits covered by PD + PTs */
2270	unsigned bits = ilog2(vm_size) + 18;
2271
2272	/* Make sure the PD is 4K in size up to 8GB address space.
2273	   Above that split equal between PD and PTs */
2274	if (vm_size <= 8)
2275		return (bits - 9);
2276	else
2277		return ((bits + 3) / 2);
2278}
2279
2280/**
2281 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2282 *
2283 * @adev: amdgpu_device pointer
2284 * @vm_size: the default vm size if it's set auto
 
 
 
 
2285 */
2286void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
2287			   uint32_t fragment_size_default, unsigned max_level,
2288			   unsigned max_bits)
2289{
 
 
2290	uint64_t tmp;
2291
2292	/* adjust vm size first */
2293	if (amdgpu_vm_size != -1) {
2294		unsigned max_size = 1 << (max_bits - 30);
2295
2296		vm_size = amdgpu_vm_size;
2297		if (vm_size > max_size) {
2298			dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2299				 amdgpu_vm_size, max_size);
2300			vm_size = max_size;
2301		}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2302	}
2303
2304	adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2305
2306	tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2307	if (amdgpu_vm_block_size != -1)
2308		tmp >>= amdgpu_vm_block_size - 9;
2309	tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2310	adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
2311	switch (adev->vm_manager.num_level) {
2312	case 3:
2313		adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2314		break;
2315	case 2:
2316		adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2317		break;
2318	case 1:
2319		adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2320		break;
2321	default:
2322		dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2323	}
2324	/* block size depends on vm size and hw setup*/
2325	if (amdgpu_vm_block_size != -1)
2326		adev->vm_manager.block_size =
2327			min((unsigned)amdgpu_vm_block_size, max_bits
2328			    - AMDGPU_GPU_PAGE_SHIFT
2329			    - 9 * adev->vm_manager.num_level);
2330	else if (adev->vm_manager.num_level > 1)
2331		adev->vm_manager.block_size = 9;
2332	else
2333		adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2334
2335	if (amdgpu_vm_fragment_size == -1)
2336		adev->vm_manager.fragment_size = fragment_size_default;
2337	else
2338		adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2339
2340	DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2341		 vm_size, adev->vm_manager.num_level + 1,
2342		 adev->vm_manager.block_size,
2343		 adev->vm_manager.fragment_size);
2344}
2345
2346/**
 
 
 
 
 
 
 
 
 
 
 
 
2347 * amdgpu_vm_init - initialize a vm instance
2348 *
2349 * @adev: amdgpu_device pointer
2350 * @vm: requested vm
2351 * @vm_context: Indicates if it GFX or Compute context
 
2352 *
2353 * Init @vm fields.
 
 
 
2354 */
2355int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
2356		   int vm_context, unsigned int pasid)
2357{
2358	const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
2359		AMDGPU_VM_PTE_COUNT(adev) * 8);
2360	unsigned ring_instance;
2361	struct amdgpu_ring *ring;
2362	struct drm_sched_rq *rq;
2363	unsigned long size;
2364	uint64_t flags;
2365	int r, i;
2366
2367	vm->va = RB_ROOT_CACHED;
2368	for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2369		vm->reserved_vmid[i] = NULL;
2370	spin_lock_init(&vm->status_lock);
2371	INIT_LIST_HEAD(&vm->evicted);
2372	INIT_LIST_HEAD(&vm->relocated);
2373	INIT_LIST_HEAD(&vm->moved);
 
 
 
2374	INIT_LIST_HEAD(&vm->freed);
2375
2376	/* create scheduler entity for page table updates */
2377
2378	ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring);
2379	ring_instance %= adev->vm_manager.vm_pte_num_rings;
2380	ring = adev->vm_manager.vm_pte_rings[ring_instance];
2381	rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
2382	r = drm_sched_entity_init(&ring->sched, &vm->entity,
2383				  rq, amdgpu_sched_jobs, NULL);
2384	if (r)
2385		return r;
2386
2387	vm->pte_support_ats = false;
2388
2389	if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) {
2390		vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2391						AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2392
2393		if (adev->asic_type == CHIP_RAVEN)
2394			vm->pte_support_ats = true;
2395	} else {
2396		vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2397						AMDGPU_VM_USE_CPU_FOR_GFX);
2398	}
2399	DRM_DEBUG_DRIVER("VM update mode is %s\n",
2400			 vm->use_cpu_for_update ? "CPU" : "SDMA");
2401	WARN_ONCE((vm->use_cpu_for_update & !amdgpu_vm_is_large_bar(adev)),
2402		  "CPU update of VM recommended only for large BAR system\n");
2403	vm->last_update = NULL;
2404
2405	flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
2406	if (vm->use_cpu_for_update)
2407		flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
2408	else
2409		flags |= AMDGPU_GEM_CREATE_SHADOW;
 
2410
2411	size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);
2412	r = amdgpu_bo_create(adev, size, align, AMDGPU_GEM_DOMAIN_VRAM, flags,
2413			     ttm_bo_type_kernel, NULL, &vm->root.base.bo);
 
2414	if (r)
2415		goto error_free_sched_entity;
2416
2417	r = amdgpu_bo_reserve(vm->root.base.bo, true);
2418	if (r)
2419		goto error_free_root;
2420
2421	r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo,
2422			       adev->vm_manager.root_level,
2423			       vm->pte_support_ats);
 
 
 
 
2424	if (r)
2425		goto error_unreserve;
2426
2427	vm->root.base.vm = vm;
2428	list_add_tail(&vm->root.base.bo_list, &vm->root.base.bo->va);
2429	list_add_tail(&vm->root.base.vm_status, &vm->evicted);
2430	amdgpu_bo_unreserve(vm->root.base.bo);
2431
2432	if (pasid) {
2433		unsigned long flags;
2434
2435		spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2436		r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
2437			      GFP_ATOMIC);
2438		spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2439		if (r < 0)
2440			goto error_free_root;
2441
2442		vm->pasid = pasid;
2443	}
2444
2445	INIT_KFIFO(vm->faults);
2446	vm->fault_credit = 16;
2447
2448	return 0;
2449
2450error_unreserve:
2451	amdgpu_bo_unreserve(vm->root.base.bo);
2452
2453error_free_root:
2454	amdgpu_bo_unref(&vm->root.base.bo->shadow);
2455	amdgpu_bo_unref(&vm->root.base.bo);
2456	vm->root.base.bo = NULL;
2457
2458error_free_sched_entity:
2459	drm_sched_entity_fini(&ring->sched, &vm->entity);
2460
2461	return r;
2462}
2463
2464/**
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2465 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
2466 *
 
 
 
2467 * This only works on GFX VMs that don't have any BOs added and no
2468 * page tables allocated yet.
2469 *
2470 * Changes the following VM parameters:
2471 * - use_cpu_for_update
2472 * - pte_supports_ats
2473 * - pasid (old PASID is released, because compute manages its own PASIDs)
2474 *
2475 * Reinitializes the page directory to reflect the changed ATS
2476 * setting. May leave behind an unused shadow BO for the page
2477 * directory when switching from SDMA updates to CPU updates.
2478 *
2479 * Returns 0 for success, -errno for errors.
 
2480 */
2481int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2482{
2483	bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
2484	int r;
2485
2486	r = amdgpu_bo_reserve(vm->root.base.bo, true);
2487	if (r)
2488		return r;
2489
2490	/* Sanity checks */
2491	if (!RB_EMPTY_ROOT(&vm->va.rb_root) || vm->root.entries) {
2492		r = -EINVAL;
2493		goto error;
 
 
 
 
 
 
 
 
 
 
 
 
2494	}
2495
2496	/* Check if PD needs to be reinitialized and do it before
2497	 * changing any other state, in case it fails.
2498	 */
2499	if (pte_support_ats != vm->pte_support_ats) {
2500		r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo,
2501			       adev->vm_manager.root_level,
2502			       pte_support_ats);
2503		if (r)
2504			goto error;
2505	}
2506
2507	/* Update VM state */
2508	vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2509				    AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2510	vm->pte_support_ats = pte_support_ats;
2511	DRM_DEBUG_DRIVER("VM update mode is %s\n",
2512			 vm->use_cpu_for_update ? "CPU" : "SDMA");
2513	WARN_ONCE((vm->use_cpu_for_update & !amdgpu_vm_is_large_bar(adev)),
2514		  "CPU update of VM recommended only for large BAR system\n");
2515
 
 
 
 
 
 
 
2516	if (vm->pasid) {
2517		unsigned long flags;
2518
2519		spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2520		idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
2521		spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2522
 
 
 
 
2523		vm->pasid = 0;
2524	}
2525
2526error:
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2527	amdgpu_bo_unreserve(vm->root.base.bo);
2528	return r;
2529}
2530
2531/**
2532 * amdgpu_vm_free_levels - free PD/PT levels
2533 *
2534 * @adev: amdgpu device structure
2535 * @parent: PD/PT starting level to free
2536 * @level: level of parent structure
2537 *
2538 * Free the page directory or page table level and all sub levels.
 
2539 */
2540static void amdgpu_vm_free_levels(struct amdgpu_device *adev,
2541				  struct amdgpu_vm_pt *parent,
2542				  unsigned level)
2543{
2544	unsigned i, num_entries = amdgpu_vm_num_entries(adev, level);
 
2545
2546	if (parent->base.bo) {
2547		list_del(&parent->base.bo_list);
2548		list_del(&parent->base.vm_status);
2549		amdgpu_bo_unref(&parent->base.bo->shadow);
2550		amdgpu_bo_unref(&parent->base.bo);
2551	}
2552
2553	if (parent->entries)
2554		for (i = 0; i < num_entries; i++)
2555			amdgpu_vm_free_levels(adev, &parent->entries[i],
2556					      level + 1);
2557
2558	kvfree(parent->entries);
2559}
2560
2561/**
2562 * amdgpu_vm_fini - tear down a vm instance
2563 *
2564 * @adev: amdgpu_device pointer
2565 * @vm: requested vm
2566 *
2567 * Tear down @vm.
2568 * Unbind the VM and remove all bos from the vm bo list
2569 */
2570void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2571{
2572	struct amdgpu_bo_va_mapping *mapping, *tmp;
2573	bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
2574	struct amdgpu_bo *root;
2575	u64 fault;
2576	int i, r;
2577
2578	amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
2579
2580	/* Clear pending page faults from IH when the VM is destroyed */
2581	while (kfifo_get(&vm->faults, &fault))
2582		amdgpu_ih_clear_fault(adev, fault);
2583
2584	if (vm->pasid) {
2585		unsigned long flags;
2586
2587		spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2588		idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
2589		spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2590	}
2591
2592	drm_sched_entity_fini(vm->entity.sched, &vm->entity);
2593
2594	if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
2595		dev_err(adev->dev, "still active bo inside vm\n");
2596	}
2597	rbtree_postorder_for_each_entry_safe(mapping, tmp,
2598					     &vm->va.rb_root, rb) {
 
 
 
2599		list_del(&mapping->list);
2600		amdgpu_vm_it_remove(mapping, &vm->va);
2601		kfree(mapping);
2602	}
2603	list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
2604		if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
2605			amdgpu_vm_prt_fini(adev, vm);
2606			prt_fini_needed = false;
2607		}
2608
2609		list_del(&mapping->list);
2610		amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
2611	}
2612
2613	root = amdgpu_bo_ref(vm->root.base.bo);
2614	r = amdgpu_bo_reserve(root, true);
2615	if (r) {
2616		dev_err(adev->dev, "Leaking page tables because BO reservation failed\n");
2617	} else {
2618		amdgpu_vm_free_levels(adev, &vm->root,
2619				      adev->vm_manager.root_level);
2620		amdgpu_bo_unreserve(root);
2621	}
2622	amdgpu_bo_unref(&root);
 
2623	dma_fence_put(vm->last_update);
2624	for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2625		amdgpu_vmid_free_reserved(adev, vm, i);
2626}
2627
2628/**
2629 * amdgpu_vm_pasid_fault_credit - Check fault credit for given PASID
2630 *
2631 * @adev: amdgpu_device pointer
2632 * @pasid: PASID do identify the VM
2633 *
2634 * This function is expected to be called in interrupt context. Returns
2635 * true if there was fault credit, false otherwise
2636 */
2637bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev,
2638				  unsigned int pasid)
2639{
2640	struct amdgpu_vm *vm;
2641
2642	spin_lock(&adev->vm_manager.pasid_lock);
2643	vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
2644	if (!vm) {
2645		/* VM not found, can't track fault credit */
2646		spin_unlock(&adev->vm_manager.pasid_lock);
2647		return true;
2648	}
2649
2650	/* No lock needed. only accessed by IRQ handler */
2651	if (!vm->fault_credit) {
2652		/* Too many faults in this VM */
2653		spin_unlock(&adev->vm_manager.pasid_lock);
2654		return false;
2655	}
2656
2657	vm->fault_credit--;
2658	spin_unlock(&adev->vm_manager.pasid_lock);
2659	return true;
2660}
2661
2662/**
2663 * amdgpu_vm_manager_init - init the VM manager
2664 *
2665 * @adev: amdgpu_device pointer
2666 *
2667 * Initialize the VM manager structures
2668 */
2669void amdgpu_vm_manager_init(struct amdgpu_device *adev)
2670{
2671	unsigned i;
2672
2673	amdgpu_vmid_mgr_init(adev);
2674
2675	adev->vm_manager.fence_context =
2676		dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2677	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
2678		adev->vm_manager.seqno[i] = 0;
2679
2680	atomic_set(&adev->vm_manager.vm_pte_next_ring, 0);
2681	spin_lock_init(&adev->vm_manager.prt_lock);
2682	atomic_set(&adev->vm_manager.num_prt_users, 0);
2683
2684	/* If not overridden by the user, by default, only in large BAR systems
2685	 * Compute VM tables will be updated by CPU
2686	 */
2687#ifdef CONFIG_X86_64
2688	if (amdgpu_vm_update_mode == -1) {
2689		if (amdgpu_vm_is_large_bar(adev))
2690			adev->vm_manager.vm_update_mode =
2691				AMDGPU_VM_USE_CPU_FOR_COMPUTE;
2692		else
2693			adev->vm_manager.vm_update_mode = 0;
2694	} else
2695		adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
2696#else
2697	adev->vm_manager.vm_update_mode = 0;
2698#endif
2699
2700	idr_init(&adev->vm_manager.pasid_idr);
2701	spin_lock_init(&adev->vm_manager.pasid_lock);
 
 
 
2702}
2703
2704/**
2705 * amdgpu_vm_manager_fini - cleanup VM manager
2706 *
2707 * @adev: amdgpu_device pointer
2708 *
2709 * Cleanup the VM manager and free resources.
2710 */
2711void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
2712{
2713	WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr));
2714	idr_destroy(&adev->vm_manager.pasid_idr);
2715
2716	amdgpu_vmid_mgr_fini(adev);
2717}
2718
 
 
 
 
 
 
 
 
 
 
2719int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
2720{
2721	union drm_amdgpu_vm *args = data;
2722	struct amdgpu_device *adev = dev->dev_private;
2723	struct amdgpu_fpriv *fpriv = filp->driver_priv;
2724	int r;
2725
2726	switch (args->in.op) {
2727	case AMDGPU_VM_OP_RESERVE_VMID:
2728		/* current, we only have requirement to reserve vmid from gfxhub */
2729		r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
2730		if (r)
2731			return r;
2732		break;
2733	case AMDGPU_VM_OP_UNRESERVE_VMID:
2734		amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
2735		break;
2736	default:
2737		return -EINVAL;
2738	}
2739
2740	return 0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2741}
v5.4
   1/*
   2 * Copyright 2008 Advanced Micro Devices, Inc.
   3 * Copyright 2008 Red Hat Inc.
   4 * Copyright 2009 Jerome Glisse.
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a
   7 * copy of this software and associated documentation files (the "Software"),
   8 * to deal in the Software without restriction, including without limitation
   9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10 * and/or sell copies of the Software, and to permit persons to whom the
  11 * Software is furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22 * OTHER DEALINGS IN THE SOFTWARE.
  23 *
  24 * Authors: Dave Airlie
  25 *          Alex Deucher
  26 *          Jerome Glisse
  27 */
  28#include <linux/dma-fence-array.h>
  29#include <linux/interval_tree_generic.h>
  30#include <linux/idr.h>
  31
  32#include <drm/amdgpu_drm.h>
  33#include "amdgpu.h"
  34#include "amdgpu_trace.h"
  35#include "amdgpu_amdkfd.h"
  36#include "amdgpu_gmc.h"
  37#include "amdgpu_xgmi.h"
  38
  39/**
  40 * DOC: GPUVM
  41 *
  42 * GPUVM is similar to the legacy gart on older asics, however
  43 * rather than there being a single global gart table
  44 * for the entire GPU, there are multiple VM page tables active
  45 * at any given time.  The VM page tables can contain a mix
  46 * vram pages and system memory pages and system memory pages
  47 * can be mapped as snooped (cached system pages) or unsnooped
  48 * (uncached system pages).
  49 * Each VM has an ID associated with it and there is a page table
  50 * associated with each VMID.  When execting a command buffer,
  51 * the kernel tells the the ring what VMID to use for that command
  52 * buffer.  VMIDs are allocated dynamically as commands are submitted.
  53 * The userspace drivers maintain their own address space and the kernel
  54 * sets up their pages tables accordingly when they submit their
  55 * command buffers and a VMID is assigned.
  56 * Cayman/Trinity support up to 8 active VMs at any given time;
  57 * SI supports 16.
  58 */
  59
  60#define START(node) ((node)->start)
  61#define LAST(node) ((node)->last)
  62
  63INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
  64		     START, LAST, static, amdgpu_vm_it)
  65
  66#undef START
  67#undef LAST
  68
  69/**
  70 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
  71 */
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
  72struct amdgpu_prt_cb {
  73
  74	/**
  75	 * @adev: amdgpu device
  76	 */
  77	struct amdgpu_device *adev;
  78
  79	/**
  80	 * @cb: callback
  81	 */
  82	struct dma_fence_cb cb;
  83};
  84
  85/**
  86 * amdgpu_vm_level_shift - return the addr shift for each level
  87 *
  88 * @adev: amdgpu_device pointer
  89 * @level: VMPT level
  90 *
  91 * Returns:
  92 * The number of bits the pfn needs to be right shifted for a level.
  93 */
  94static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
  95				      unsigned level)
  96{
  97	unsigned shift = 0xff;
  98
  99	switch (level) {
 100	case AMDGPU_VM_PDB2:
 101	case AMDGPU_VM_PDB1:
 102	case AMDGPU_VM_PDB0:
 103		shift = 9 * (AMDGPU_VM_PDB0 - level) +
 104			adev->vm_manager.block_size;
 105		break;
 106	case AMDGPU_VM_PTB:
 107		shift = 0;
 108		break;
 109	default:
 110		dev_err(adev->dev, "the level%d isn't supported.\n", level);
 111	}
 112
 113	return shift;
 114}
 115
 116/**
 117 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
 118 *
 119 * @adev: amdgpu_device pointer
 120 * @level: VMPT level
 121 *
 122 * Returns:
 123 * The number of entries in a page directory or page table.
 124 */
 125static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
 126				      unsigned level)
 127{
 128	unsigned shift = amdgpu_vm_level_shift(adev,
 129					       adev->vm_manager.root_level);
 130
 131	if (level == adev->vm_manager.root_level)
 132		/* For the root directory */
 133		return round_up(adev->vm_manager.max_pfn, 1ULL << shift) >> shift;
 134	else if (level != AMDGPU_VM_PTB)
 135		/* Everything in between */
 136		return 512;
 137	else
 138		/* For the page tables on the leaves */
 139		return AMDGPU_VM_PTE_COUNT(adev);
 140}
 141
 142/**
 143 * amdgpu_vm_num_ats_entries - return the number of ATS entries in the root PD
 144 *
 145 * @adev: amdgpu_device pointer
 146 *
 147 * Returns:
 148 * The number of entries in the root page directory which needs the ATS setting.
 149 */
 150static unsigned amdgpu_vm_num_ats_entries(struct amdgpu_device *adev)
 151{
 152	unsigned shift;
 153
 154	shift = amdgpu_vm_level_shift(adev, adev->vm_manager.root_level);
 155	return AMDGPU_GMC_HOLE_START >> (shift + AMDGPU_GPU_PAGE_SHIFT);
 156}
 157
 158/**
 159 * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT
 160 *
 161 * @adev: amdgpu_device pointer
 162 * @level: VMPT level
 163 *
 164 * Returns:
 165 * The mask to extract the entry number of a PD/PT from an address.
 166 */
 167static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
 168				       unsigned int level)
 169{
 170	if (level <= adev->vm_manager.root_level)
 171		return 0xffffffff;
 172	else if (level != AMDGPU_VM_PTB)
 173		return 0x1ff;
 174	else
 175		return AMDGPU_VM_PTE_COUNT(adev) - 1;
 176}
 177
 178/**
 179 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
 180 *
 181 * @adev: amdgpu_device pointer
 182 * @level: VMPT level
 183 *
 184 * Returns:
 185 * The size of the BO for a page directory or page table in bytes.
 186 */
 187static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
 188{
 189	return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
 190}
 191
 192/**
 193 * amdgpu_vm_bo_evicted - vm_bo is evicted
 194 *
 195 * @vm_bo: vm_bo which is evicted
 196 *
 197 * State for PDs/PTs and per VM BOs which are not at the location they should
 198 * be.
 199 */
 200static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
 201{
 202	struct amdgpu_vm *vm = vm_bo->vm;
 203	struct amdgpu_bo *bo = vm_bo->bo;
 204
 205	vm_bo->moved = true;
 206	if (bo->tbo.type == ttm_bo_type_kernel)
 207		list_move(&vm_bo->vm_status, &vm->evicted);
 208	else
 209		list_move_tail(&vm_bo->vm_status, &vm->evicted);
 210}
 211
 212/**
 213 * amdgpu_vm_bo_relocated - vm_bo is reloacted
 214 *
 215 * @vm_bo: vm_bo which is relocated
 216 *
 217 * State for PDs/PTs which needs to update their parent PD.
 218 */
 219static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
 220{
 221	list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
 222}
 223
 224/**
 225 * amdgpu_vm_bo_moved - vm_bo is moved
 226 *
 227 * @vm_bo: vm_bo which is moved
 228 *
 229 * State for per VM BOs which are moved, but that change is not yet reflected
 230 * in the page tables.
 231 */
 232static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
 233{
 234	list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
 235}
 236
 237/**
 238 * amdgpu_vm_bo_idle - vm_bo is idle
 239 *
 240 * @vm_bo: vm_bo which is now idle
 241 *
 242 * State for PDs/PTs and per VM BOs which have gone through the state machine
 243 * and are now idle.
 244 */
 245static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
 246{
 247	list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
 248	vm_bo->moved = false;
 249}
 250
 251/**
 252 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
 253 *
 254 * @vm_bo: vm_bo which is now invalidated
 255 *
 256 * State for normal BOs which are invalidated and that change not yet reflected
 257 * in the PTs.
 258 */
 259static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
 260{
 261	spin_lock(&vm_bo->vm->invalidated_lock);
 262	list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
 263	spin_unlock(&vm_bo->vm->invalidated_lock);
 264}
 265
 266/**
 267 * amdgpu_vm_bo_done - vm_bo is done
 268 *
 269 * @vm_bo: vm_bo which is now done
 270 *
 271 * State for normal BOs which are invalidated and that change has been updated
 272 * in the PTs.
 273 */
 274static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
 275{
 276	spin_lock(&vm_bo->vm->invalidated_lock);
 277	list_del_init(&vm_bo->vm_status);
 278	spin_unlock(&vm_bo->vm->invalidated_lock);
 279}
 280
 281/**
 282 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
 283 *
 284 * @base: base structure for tracking BO usage in a VM
 285 * @vm: vm to which bo is to be added
 286 * @bo: amdgpu buffer object
 287 *
 288 * Initialize a bo_va_base structure and add it to the appropriate lists
 289 *
 290 */
 291static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
 292				   struct amdgpu_vm *vm,
 293				   struct amdgpu_bo *bo)
 294{
 295	base->vm = vm;
 296	base->bo = bo;
 297	base->next = NULL;
 298	INIT_LIST_HEAD(&base->vm_status);
 299
 300	if (!bo)
 301		return;
 302	base->next = bo->vm_bo;
 303	bo->vm_bo = base;
 304
 305	if (bo->tbo.base.resv != vm->root.base.bo->tbo.base.resv)
 306		return;
 307
 308	vm->bulk_moveable = false;
 309	if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)
 310		amdgpu_vm_bo_relocated(base);
 311	else
 312		amdgpu_vm_bo_idle(base);
 313
 314	if (bo->preferred_domains &
 315	    amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type))
 316		return;
 317
 318	/*
 319	 * we checked all the prerequisites, but it looks like this per vm bo
 320	 * is currently evicted. add the bo to the evicted list to make sure it
 321	 * is validated on next vm use to avoid fault.
 322	 * */
 323	amdgpu_vm_bo_evicted(base);
 324}
 325
 326/**
 327 * amdgpu_vm_pt_parent - get the parent page directory
 328 *
 329 * @pt: child page table
 330 *
 331 * Helper to get the parent entry for the child page table. NULL if we are at
 332 * the root page directory.
 333 */
 334static struct amdgpu_vm_pt *amdgpu_vm_pt_parent(struct amdgpu_vm_pt *pt)
 335{
 336	struct amdgpu_bo *parent = pt->base.bo->parent;
 337
 338	if (!parent)
 339		return NULL;
 340
 341	return container_of(parent->vm_bo, struct amdgpu_vm_pt, base);
 342}
 343
 344/**
 345 * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt
 346 */
 347struct amdgpu_vm_pt_cursor {
 348	uint64_t pfn;
 349	struct amdgpu_vm_pt *parent;
 350	struct amdgpu_vm_pt *entry;
 351	unsigned level;
 352};
 353
 354/**
 355 * amdgpu_vm_pt_start - start PD/PT walk
 356 *
 357 * @adev: amdgpu_device pointer
 358 * @vm: amdgpu_vm structure
 359 * @start: start address of the walk
 360 * @cursor: state to initialize
 361 *
 362 * Initialize a amdgpu_vm_pt_cursor to start a walk.
 363 */
 364static void amdgpu_vm_pt_start(struct amdgpu_device *adev,
 365			       struct amdgpu_vm *vm, uint64_t start,
 366			       struct amdgpu_vm_pt_cursor *cursor)
 367{
 368	cursor->pfn = start;
 369	cursor->parent = NULL;
 370	cursor->entry = &vm->root;
 371	cursor->level = adev->vm_manager.root_level;
 372}
 373
 374/**
 375 * amdgpu_vm_pt_descendant - go to child node
 376 *
 377 * @adev: amdgpu_device pointer
 378 * @cursor: current state
 379 *
 380 * Walk to the child node of the current node.
 381 * Returns:
 382 * True if the walk was possible, false otherwise.
 383 */
 384static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev,
 385				    struct amdgpu_vm_pt_cursor *cursor)
 386{
 387	unsigned mask, shift, idx;
 388
 389	if (!cursor->entry->entries)
 390		return false;
 391
 392	BUG_ON(!cursor->entry->base.bo);
 393	mask = amdgpu_vm_entries_mask(adev, cursor->level);
 394	shift = amdgpu_vm_level_shift(adev, cursor->level);
 395
 396	++cursor->level;
 397	idx = (cursor->pfn >> shift) & mask;
 398	cursor->parent = cursor->entry;
 399	cursor->entry = &cursor->entry->entries[idx];
 400	return true;
 401}
 402
 403/**
 404 * amdgpu_vm_pt_sibling - go to sibling node
 405 *
 406 * @adev: amdgpu_device pointer
 407 * @cursor: current state
 408 *
 409 * Walk to the sibling node of the current node.
 410 * Returns:
 411 * True if the walk was possible, false otherwise.
 412 */
 413static bool amdgpu_vm_pt_sibling(struct amdgpu_device *adev,
 414				 struct amdgpu_vm_pt_cursor *cursor)
 415{
 416	unsigned shift, num_entries;
 417
 418	/* Root doesn't have a sibling */
 419	if (!cursor->parent)
 420		return false;
 421
 422	/* Go to our parents and see if we got a sibling */
 423	shift = amdgpu_vm_level_shift(adev, cursor->level - 1);
 424	num_entries = amdgpu_vm_num_entries(adev, cursor->level - 1);
 425
 426	if (cursor->entry == &cursor->parent->entries[num_entries - 1])
 427		return false;
 428
 429	cursor->pfn += 1ULL << shift;
 430	cursor->pfn &= ~((1ULL << shift) - 1);
 431	++cursor->entry;
 432	return true;
 433}
 434
 435/**
 436 * amdgpu_vm_pt_ancestor - go to parent node
 437 *
 438 * @cursor: current state
 439 *
 440 * Walk to the parent node of the current node.
 441 * Returns:
 442 * True if the walk was possible, false otherwise.
 443 */
 444static bool amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor *cursor)
 445{
 446	if (!cursor->parent)
 447		return false;
 448
 449	--cursor->level;
 450	cursor->entry = cursor->parent;
 451	cursor->parent = amdgpu_vm_pt_parent(cursor->parent);
 452	return true;
 453}
 454
 455/**
 456 * amdgpu_vm_pt_next - get next PD/PT in hieratchy
 457 *
 458 * @adev: amdgpu_device pointer
 459 * @cursor: current state
 460 *
 461 * Walk the PD/PT tree to the next node.
 462 */
 463static void amdgpu_vm_pt_next(struct amdgpu_device *adev,
 464			      struct amdgpu_vm_pt_cursor *cursor)
 465{
 466	/* First try a newborn child */
 467	if (amdgpu_vm_pt_descendant(adev, cursor))
 468		return;
 469
 470	/* If that didn't worked try to find a sibling */
 471	while (!amdgpu_vm_pt_sibling(adev, cursor)) {
 472		/* No sibling, go to our parents and grandparents */
 473		if (!amdgpu_vm_pt_ancestor(cursor)) {
 474			cursor->pfn = ~0ll;
 475			return;
 476		}
 477	}
 478}
 479
 480/**
 481 * amdgpu_vm_pt_first_dfs - start a deep first search
 482 *
 483 * @adev: amdgpu_device structure
 484 * @vm: amdgpu_vm structure
 485 * @cursor: state to initialize
 486 *
 487 * Starts a deep first traversal of the PD/PT tree.
 488 */
 489static void amdgpu_vm_pt_first_dfs(struct amdgpu_device *adev,
 490				   struct amdgpu_vm *vm,
 491				   struct amdgpu_vm_pt_cursor *start,
 492				   struct amdgpu_vm_pt_cursor *cursor)
 493{
 494	if (start)
 495		*cursor = *start;
 496	else
 497		amdgpu_vm_pt_start(adev, vm, 0, cursor);
 498	while (amdgpu_vm_pt_descendant(adev, cursor));
 499}
 500
 501/**
 502 * amdgpu_vm_pt_continue_dfs - check if the deep first search should continue
 503 *
 504 * @start: starting point for the search
 505 * @entry: current entry
 506 *
 507 * Returns:
 508 * True when the search should continue, false otherwise.
 509 */
 510static bool amdgpu_vm_pt_continue_dfs(struct amdgpu_vm_pt_cursor *start,
 511				      struct amdgpu_vm_pt *entry)
 512{
 513	return entry && (!start || entry != start->entry);
 514}
 515
 516/**
 517 * amdgpu_vm_pt_next_dfs - get the next node for a deep first search
 518 *
 519 * @adev: amdgpu_device structure
 520 * @cursor: current state
 521 *
 522 * Move the cursor to the next node in a deep first search.
 523 */
 524static void amdgpu_vm_pt_next_dfs(struct amdgpu_device *adev,
 525				  struct amdgpu_vm_pt_cursor *cursor)
 526{
 527	if (!cursor->entry)
 528		return;
 529
 530	if (!cursor->parent)
 531		cursor->entry = NULL;
 532	else if (amdgpu_vm_pt_sibling(adev, cursor))
 533		while (amdgpu_vm_pt_descendant(adev, cursor));
 534	else
 535		amdgpu_vm_pt_ancestor(cursor);
 536}
 537
 538/**
 539 * for_each_amdgpu_vm_pt_dfs_safe - safe deep first search of all PDs/PTs
 540 */
 541#define for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry)		\
 542	for (amdgpu_vm_pt_first_dfs((adev), (vm), (start), &(cursor)),		\
 543	     (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor));\
 544	     amdgpu_vm_pt_continue_dfs((start), (entry));			\
 545	     (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor)))
 546
 547/**
 548 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
 549 *
 550 * @vm: vm providing the BOs
 551 * @validated: head of validation list
 552 * @entry: entry to add
 553 *
 554 * Add the page directory to the list of BOs to
 555 * validate for command submission.
 556 */
 557void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
 558			 struct list_head *validated,
 559			 struct amdgpu_bo_list_entry *entry)
 560{
 
 561	entry->priority = 0;
 562	entry->tv.bo = &vm->root.base.bo->tbo;
 563	/* One for the VM updates, one for TTM and one for the CS job */
 564	entry->tv.num_shared = 3;
 565	entry->user_pages = NULL;
 566	list_add(&entry->tv.head, validated);
 567}
 568
 569void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo)
 570{
 571	struct amdgpu_bo *abo;
 572	struct amdgpu_vm_bo_base *bo_base;
 573
 574	if (!amdgpu_bo_is_amdgpu_bo(bo))
 575		return;
 576
 577	if (bo->mem.placement & TTM_PL_FLAG_NO_EVICT)
 578		return;
 579
 580	abo = ttm_to_amdgpu_bo(bo);
 581	if (!abo->parent)
 582		return;
 583	for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) {
 584		struct amdgpu_vm *vm = bo_base->vm;
 585
 586		if (abo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)
 587			vm->bulk_moveable = false;
 588	}
 589
 590}
 591/**
 592 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
 593 *
 594 * @adev: amdgpu device pointer
 595 * @vm: vm providing the BOs
 596 *
 597 * Move all BOs to the end of LRU and remember their positions to put them
 598 * together.
 599 */
 600void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
 601				struct amdgpu_vm *vm)
 602{
 603	struct ttm_bo_global *glob = adev->mman.bdev.glob;
 604	struct amdgpu_vm_bo_base *bo_base;
 605
 606	if (vm->bulk_moveable) {
 607		spin_lock(&glob->lru_lock);
 608		ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move);
 609		spin_unlock(&glob->lru_lock);
 610		return;
 611	}
 612
 613	memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move));
 614
 615	spin_lock(&glob->lru_lock);
 616	list_for_each_entry(bo_base, &vm->idle, vm_status) {
 617		struct amdgpu_bo *bo = bo_base->bo;
 618
 619		if (!bo->parent)
 620			continue;
 621
 622		ttm_bo_move_to_lru_tail(&bo->tbo, &vm->lru_bulk_move);
 623		if (bo->shadow)
 624			ttm_bo_move_to_lru_tail(&bo->shadow->tbo,
 625						&vm->lru_bulk_move);
 626	}
 627	spin_unlock(&glob->lru_lock);
 628
 629	vm->bulk_moveable = true;
 630}
 631
 632/**
 633 * amdgpu_vm_validate_pt_bos - validate the page table BOs
 634 *
 635 * @adev: amdgpu device pointer
 636 * @vm: vm providing the BOs
 637 * @validate: callback to do the validation
 638 * @param: parameter for the validation callback
 639 *
 640 * Validate the page table BOs on command submission if neccessary.
 641 *
 642 * Returns:
 643 * Validation result.
 644 */
 645int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 646			      int (*validate)(void *p, struct amdgpu_bo *bo),
 647			      void *param)
 648{
 649	struct amdgpu_vm_bo_base *bo_base, *tmp;
 650	int r = 0;
 651
 652	vm->bulk_moveable &= list_empty(&vm->evicted);
 653
 654	list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
 655		struct amdgpu_bo *bo = bo_base->bo;
 656
 657		r = validate(param, bo);
 658		if (r)
 659			break;
 660
 661		if (bo->tbo.type != ttm_bo_type_kernel) {
 662			amdgpu_vm_bo_moved(bo_base);
 663		} else {
 664			vm->update_funcs->map_table(bo);
 665			if (bo->parent)
 666				amdgpu_vm_bo_relocated(bo_base);
 667			else
 668				amdgpu_vm_bo_idle(bo_base);
 669		}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 670	}
 
 671
 672	return r;
 673}
 674
 675/**
 676 * amdgpu_vm_ready - check VM is ready for updates
 677 *
 678 * @vm: VM to check
 679 *
 680 * Check if all VM PDs/PTs are ready for updates
 681 *
 682 * Returns:
 683 * True if eviction list is empty.
 684 */
 685bool amdgpu_vm_ready(struct amdgpu_vm *vm)
 686{
 687	return list_empty(&vm->evicted);
 
 
 
 
 
 
 688}
 689
 690/**
 691 * amdgpu_vm_clear_bo - initially clear the PDs/PTs
 692 *
 693 * @adev: amdgpu_device pointer
 694 * @vm: VM to clear BO from
 695 * @bo: BO to clear
 
 696 *
 697 * Root PD needs to be reserved when calling this.
 698 *
 699 * Returns:
 700 * 0 on success, errno otherwise.
 701 */
 702static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
 703			      struct amdgpu_vm *vm,
 704			      struct amdgpu_bo *bo)
 705{
 706	struct ttm_operation_ctx ctx = { true, false };
 707	unsigned level = adev->vm_manager.root_level;
 708	struct amdgpu_vm_update_params params;
 709	struct amdgpu_bo *ancestor = bo;
 710	unsigned entries, ats_entries;
 
 
 711	uint64_t addr;
 712	int r;
 713
 714	/* Figure out our place in the hierarchy */
 715	if (ancestor->parent) {
 716		++level;
 717		while (ancestor->parent->parent) {
 718			++level;
 719			ancestor = ancestor->parent;
 720		}
 721	}
 722
 723	entries = amdgpu_bo_size(bo) / 8;
 724	if (!vm->pte_support_ats) {
 725		ats_entries = 0;
 726
 727	} else if (!bo->parent) {
 728		ats_entries = amdgpu_vm_num_ats_entries(adev);
 729		ats_entries = min(ats_entries, entries);
 730		entries -= ats_entries;
 731
 732	} else {
 733		struct amdgpu_vm_pt *pt;
 734
 735		pt = container_of(ancestor->vm_bo, struct amdgpu_vm_pt, base);
 736		ats_entries = amdgpu_vm_num_ats_entries(adev);
 737		if ((pt - vm->root.entries) >= ats_entries) {
 738			ats_entries = 0;
 739		} else {
 740			ats_entries = entries;
 741			entries = 0;
 742		}
 
 
 743	}
 744
 745	r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 
 
 746	if (r)
 747		return r;
 748
 749	if (bo->shadow) {
 750		r = ttm_bo_validate(&bo->shadow->tbo, &bo->shadow->placement,
 751				    &ctx);
 752		if (r)
 753			return r;
 754	}
 755
 756	r = vm->update_funcs->map_table(bo);
 757	if (r)
 758		return r;
 759
 760	memset(&params, 0, sizeof(params));
 761	params.adev = adev;
 762	params.vm = vm;
 763
 764	r = vm->update_funcs->prepare(&params, AMDGPU_FENCE_OWNER_KFD, NULL);
 765	if (r)
 766		return r;
 767
 768	addr = 0;
 769	if (ats_entries) {
 770		uint64_t value = 0, flags;
 771
 772		flags = AMDGPU_PTE_DEFAULT_ATC;
 773		if (level != AMDGPU_VM_PTB) {
 774			/* Handle leaf PDEs as PTEs */
 775			flags |= AMDGPU_PDE_PTE;
 776			amdgpu_gmc_get_vm_pde(adev, level, &value, &flags);
 777		}
 778
 779		r = vm->update_funcs->update(&params, bo, addr, 0, ats_entries,
 780					     value, flags);
 781		if (r)
 782			return r;
 783
 
 
 784		addr += ats_entries * 8;
 785	}
 786
 787	if (entries) {
 788		uint64_t value = 0, flags = 0;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 789
 790		if (adev->asic_type >= CHIP_VEGA10) {
 791			if (level != AMDGPU_VM_PTB) {
 792				/* Handle leaf PDEs as PTEs */
 793				flags |= AMDGPU_PDE_PTE;
 794				amdgpu_gmc_get_vm_pde(adev, level,
 795						      &value, &flags);
 796			} else {
 797				/* Workaround for fault priority problem on GMC9 */
 798				flags = AMDGPU_PTE_EXECUTABLE;
 799			}
 800		}
 801
 802		r = vm->update_funcs->update(&params, bo, addr, 0, entries,
 803					     value, flags);
 804		if (r)
 805			return r;
 806	}
 807
 808	return vm->update_funcs->commit(&params, NULL);
 809}
 810
 811/**
 812 * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation
 813 *
 814 * @adev: amdgpu_device pointer
 815 * @vm: requesting vm
 816 * @bp: resulting BO allocation parameters
 817 */
 818static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 819			       int level, struct amdgpu_bo_param *bp)
 820{
 821	memset(bp, 0, sizeof(*bp));
 822
 823	bp->size = amdgpu_vm_bo_size(adev, level);
 824	bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
 825	bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
 826	bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain);
 827	bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
 828		AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 829	if (vm->use_cpu_for_update)
 830		bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 831	else if (!vm->root.base.bo || vm->root.base.bo->shadow)
 832		bp->flags |= AMDGPU_GEM_CREATE_SHADOW;
 833	bp->type = ttm_bo_type_kernel;
 834	if (vm->root.base.bo)
 835		bp->resv = vm->root.base.bo->tbo.base.resv;
 836}
 837
 838/**
 839 * amdgpu_vm_alloc_pts - Allocate a specific page table
 840 *
 841 * @adev: amdgpu_device pointer
 842 * @vm: VM to allocate page tables for
 843 * @cursor: Which page table to allocate
 844 *
 845 * Make sure a specific page table or directory is allocated.
 846 *
 847 * Returns:
 848 * 1 if page table needed to be allocated, 0 if page table was already
 849 * allocated, negative errno if an error occurred.
 850 */
 851static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
 852			       struct amdgpu_vm *vm,
 853			       struct amdgpu_vm_pt_cursor *cursor)
 854{
 855	struct amdgpu_vm_pt *entry = cursor->entry;
 856	struct amdgpu_bo_param bp;
 857	struct amdgpu_bo *pt;
 
 
 858	int r;
 859
 860	if (cursor->level < AMDGPU_VM_PTB && !entry->entries) {
 861		unsigned num_entries;
 862
 863		num_entries = amdgpu_vm_num_entries(adev, cursor->level);
 864		entry->entries = kvmalloc_array(num_entries,
 865						sizeof(*entry->entries),
 866						GFP_KERNEL | __GFP_ZERO);
 867		if (!entry->entries)
 868			return -ENOMEM;
 
 869	}
 870
 871	if (entry->base.bo)
 872		return 0;
 
 
 
 873
 874	amdgpu_vm_bo_param(adev, vm, cursor->level, &bp);
 
 
 875
 876	r = amdgpu_bo_create(adev, &bp, &pt);
 877	if (r)
 878		return r;
 
 
 
 879
 880	/* Keep a reference to the root directory to avoid
 881	 * freeing them up in the wrong order.
 882	 */
 883	pt->parent = amdgpu_bo_ref(cursor->parent->base.bo);
 884	amdgpu_vm_bo_base_init(&entry->base, vm, pt);
 885
 886	r = amdgpu_vm_clear_bo(adev, vm, pt);
 887	if (r)
 888		goto error_free_pt;
 
 
 
 
 
 
 
 
 
 
 
 
 889
 890	return 0;
 
 
 
 
 
 
 
 891
 892error_free_pt:
 893	amdgpu_bo_unref(&pt->shadow);
 894	amdgpu_bo_unref(&pt);
 895	return r;
 896}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 897
 898/**
 899 * amdgpu_vm_free_table - fre one PD/PT
 900 *
 901 * @entry: PDE to free
 902 */
 903static void amdgpu_vm_free_table(struct amdgpu_vm_pt *entry)
 904{
 905	if (entry->base.bo) {
 906		entry->base.bo->vm_bo = NULL;
 907		list_del(&entry->base.vm_status);
 908		amdgpu_bo_unref(&entry->base.bo->shadow);
 909		amdgpu_bo_unref(&entry->base.bo);
 910	}
 911	kvfree(entry->entries);
 912	entry->entries = NULL;
 913}
 914
 915/**
 916 * amdgpu_vm_free_pts - free PD/PT levels
 917 *
 918 * @adev: amdgpu device structure
 919 * @vm: amdgpu vm structure
 920 * @start: optional cursor where to start freeing PDs/PTs
 
 921 *
 922 * Free the page directory or page table level and all sub levels.
 923 */
 924static void amdgpu_vm_free_pts(struct amdgpu_device *adev,
 925			       struct amdgpu_vm *vm,
 926			       struct amdgpu_vm_pt_cursor *start)
 927{
 928	struct amdgpu_vm_pt_cursor cursor;
 929	struct amdgpu_vm_pt *entry;
 
 
 
 
 
 
 930
 931	vm->bulk_moveable = false;
 
 932
 933	for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry)
 934		amdgpu_vm_free_table(entry);
 935
 936	if (start)
 937		amdgpu_vm_free_table(start->entry);
 
 
 
 
 
 
 938}
 939
 940/**
 941 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
 942 *
 943 * @adev: amdgpu_device pointer
 944 */
 945void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
 946{
 947	const struct amdgpu_ip_block *ip_block;
 948	bool has_compute_vm_bug;
 949	struct amdgpu_ring *ring;
 950	int i;
 951
 952	has_compute_vm_bug = false;
 953
 954	ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
 955	if (ip_block) {
 956		/* Compute has a VM bug for GFX version < 7.
 957		   Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
 958		if (ip_block->version->major <= 7)
 959			has_compute_vm_bug = true;
 960		else if (ip_block->version->major == 8)
 961			if (adev->gfx.mec_fw_version < 673)
 962				has_compute_vm_bug = true;
 963	}
 964
 965	for (i = 0; i < adev->num_rings; i++) {
 966		ring = adev->rings[i];
 967		if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
 968			/* only compute rings */
 969			ring->has_compute_vm_bug = has_compute_vm_bug;
 970		else
 971			ring->has_compute_vm_bug = false;
 972	}
 973}
 974
 975/**
 976 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
 977 *
 978 * @ring: ring on which the job will be submitted
 979 * @job: job to submit
 980 *
 981 * Returns:
 982 * True if sync is needed.
 983 */
 984bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
 985				  struct amdgpu_job *job)
 986{
 987	struct amdgpu_device *adev = ring->adev;
 988	unsigned vmhub = ring->funcs->vmhub;
 989	struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
 990	struct amdgpu_vmid *id;
 991	bool gds_switch_needed;
 992	bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
 993
 994	if (job->vmid == 0)
 995		return false;
 996	id = &id_mgr->ids[job->vmid];
 997	gds_switch_needed = ring->funcs->emit_gds_switch && (
 998		id->gds_base != job->gds_base ||
 999		id->gds_size != job->gds_size ||
1000		id->gws_base != job->gws_base ||
1001		id->gws_size != job->gws_size ||
1002		id->oa_base != job->oa_base ||
1003		id->oa_size != job->oa_size);
1004
1005	if (amdgpu_vmid_had_gpu_reset(adev, id))
1006		return true;
1007
1008	return vm_flush_needed || gds_switch_needed;
1009}
1010
 
 
 
 
 
1011/**
1012 * amdgpu_vm_flush - hardware flush the vm
1013 *
1014 * @ring: ring to use for flush
1015 * @job:  related job
1016 * @need_pipe_sync: is pipe sync needed
1017 *
1018 * Emit a VM flush when it is necessary.
1019 *
1020 * Returns:
1021 * 0 on success, errno otherwise.
1022 */
1023int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync)
1024{
1025	struct amdgpu_device *adev = ring->adev;
1026	unsigned vmhub = ring->funcs->vmhub;
1027	struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1028	struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
1029	bool gds_switch_needed = ring->funcs->emit_gds_switch && (
1030		id->gds_base != job->gds_base ||
1031		id->gds_size != job->gds_size ||
1032		id->gws_base != job->gws_base ||
1033		id->gws_size != job->gws_size ||
1034		id->oa_base != job->oa_base ||
1035		id->oa_size != job->oa_size);
1036	bool vm_flush_needed = job->vm_needs_flush;
1037	bool pasid_mapping_needed = id->pasid != job->pasid ||
1038		!id->pasid_mapping ||
1039		!dma_fence_is_signaled(id->pasid_mapping);
1040	struct dma_fence *fence = NULL;
1041	unsigned patch_offset = 0;
1042	int r;
1043
1044	if (amdgpu_vmid_had_gpu_reset(adev, id)) {
1045		gds_switch_needed = true;
1046		vm_flush_needed = true;
1047		pasid_mapping_needed = true;
1048	}
1049
1050	gds_switch_needed &= !!ring->funcs->emit_gds_switch;
1051	vm_flush_needed &= !!ring->funcs->emit_vm_flush  &&
1052			job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
1053	pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
1054		ring->funcs->emit_wreg;
1055
1056	if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
1057		return 0;
1058
1059	if (ring->funcs->init_cond_exec)
1060		patch_offset = amdgpu_ring_init_cond_exec(ring);
1061
1062	if (need_pipe_sync)
1063		amdgpu_ring_emit_pipeline_sync(ring);
1064
1065	if (vm_flush_needed) {
1066		trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
1067		amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
1068	}
1069
1070	if (pasid_mapping_needed)
1071		amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
1072
1073	if (vm_flush_needed || pasid_mapping_needed) {
1074		r = amdgpu_fence_emit(ring, &fence, 0);
1075		if (r)
1076			return r;
1077	}
1078
1079	if (vm_flush_needed) {
1080		mutex_lock(&id_mgr->lock);
1081		dma_fence_put(id->last_flush);
1082		id->last_flush = dma_fence_get(fence);
1083		id->current_gpu_reset_count =
1084			atomic_read(&adev->gpu_reset_counter);
1085		mutex_unlock(&id_mgr->lock);
1086	}
1087
1088	if (pasid_mapping_needed) {
1089		id->pasid = job->pasid;
1090		dma_fence_put(id->pasid_mapping);
1091		id->pasid_mapping = dma_fence_get(fence);
1092	}
1093	dma_fence_put(fence);
1094
1095	if (ring->funcs->emit_gds_switch && gds_switch_needed) {
1096		id->gds_base = job->gds_base;
1097		id->gds_size = job->gds_size;
1098		id->gws_base = job->gws_base;
1099		id->gws_size = job->gws_size;
1100		id->oa_base = job->oa_base;
1101		id->oa_size = job->oa_size;
1102		amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
1103					    job->gds_size, job->gws_base,
1104					    job->gws_size, job->oa_base,
1105					    job->oa_size);
1106	}
1107
1108	if (ring->funcs->patch_cond_exec)
1109		amdgpu_ring_patch_cond_exec(ring, patch_offset);
1110
1111	/* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
1112	if (ring->funcs->emit_switch_buffer) {
1113		amdgpu_ring_emit_switch_buffer(ring);
1114		amdgpu_ring_emit_switch_buffer(ring);
1115	}
1116	return 0;
1117}
1118
1119/**
1120 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
1121 *
1122 * @vm: requested vm
1123 * @bo: requested buffer object
1124 *
1125 * Find @bo inside the requested vm.
1126 * Search inside the @bos vm list for the requested vm
1127 * Returns the found bo_va or NULL if none is found
1128 *
1129 * Object has to be reserved!
1130 *
1131 * Returns:
1132 * Found bo_va or NULL.
1133 */
1134struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
1135				       struct amdgpu_bo *bo)
1136{
1137	struct amdgpu_vm_bo_base *base;
1138
1139	for (base = bo->vm_bo; base; base = base->next) {
1140		if (base->vm != vm)
1141			continue;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1142
1143		return container_of(base, struct amdgpu_bo_va, base);
 
 
1144	}
1145	return NULL;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1146}
1147
1148/**
1149 * amdgpu_vm_map_gart - Resolve gart mapping of addr
1150 *
1151 * @pages_addr: optional DMA address to use for lookup
1152 * @addr: the unmapped addr
1153 *
1154 * Look up the physical address of the page that the pte resolves
1155 * to.
1156 *
1157 * Returns:
1158 * The pointer for the page table entry.
1159 */
1160uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
1161{
1162	uint64_t result;
1163
1164	/* page table offset */
1165	result = pages_addr[addr >> PAGE_SHIFT];
1166
1167	/* in case cpu page size != gpu page size*/
1168	result |= addr & (~PAGE_MASK);
1169
1170	result &= 0xFFFFFFFFFFFFF000ULL;
1171
1172	return result;
1173}
1174
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1175/*
1176 * amdgpu_vm_update_pde - update a single level in the hierarchy
1177 *
1178 * @param: parameters for the update
1179 * @vm: requested vm
 
1180 * @entry: entry to update
1181 *
1182 * Makes sure the requested entry in parent is up to date.
1183 */
1184static int amdgpu_vm_update_pde(struct amdgpu_vm_update_params *params,
1185				struct amdgpu_vm *vm,
1186				struct amdgpu_vm_pt *entry)
 
1187{
1188	struct amdgpu_vm_pt *parent = amdgpu_vm_pt_parent(entry);
1189	struct amdgpu_bo *bo = parent->base.bo, *pbo;
1190	uint64_t pde, pt, flags;
1191	unsigned level;
1192
 
 
 
 
1193	for (level = 0, pbo = bo->parent; pbo; ++level)
1194		pbo = pbo->parent;
1195
1196	level += params->adev->vm_manager.root_level;
1197	amdgpu_gmc_get_pde_for_bo(entry->base.bo, level, &pt, &flags);
 
 
1198	pde = (entry - parent->entries) * 8;
1199	return vm->update_funcs->update(params, bo, pde, pt, 1, 0, flags);
 
 
1200}
1201
1202/*
1203 * amdgpu_vm_invalidate_pds - mark all PDs as invalid
1204 *
1205 * @adev: amdgpu_device pointer
1206 * @vm: related vm
1207 *
1208 * Mark all PD level as invalid after an error.
1209 */
1210static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev,
1211				     struct amdgpu_vm *vm)
 
 
1212{
1213	struct amdgpu_vm_pt_cursor cursor;
1214	struct amdgpu_vm_pt *entry;
1215
1216	for_each_amdgpu_vm_pt_dfs_safe(adev, vm, NULL, cursor, entry)
1217		if (entry->base.bo && !entry->base.moved)
1218			amdgpu_vm_bo_relocated(&entry->base);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1219}
1220
1221/*
1222 * amdgpu_vm_update_directories - make sure that all directories are valid
1223 *
1224 * @adev: amdgpu_device pointer
1225 * @vm: requested vm
1226 *
1227 * Makes sure all directories are up to date.
1228 *
1229 * Returns:
1230 * 0 for success, error for failure.
1231 */
1232int amdgpu_vm_update_directories(struct amdgpu_device *adev,
1233				 struct amdgpu_vm *vm)
1234{
1235	struct amdgpu_vm_update_params params;
1236	int r;
 
 
1237
1238	if (list_empty(&vm->relocated))
1239		return 0;
1240
 
1241	memset(&params, 0, sizeof(params));
1242	params.adev = adev;
1243	params.vm = vm;
1244
1245	r = vm->update_funcs->prepare(&params, AMDGPU_FENCE_OWNER_VM, NULL);
1246	if (r)
1247		return r;
 
 
 
 
 
 
 
 
 
 
 
 
1248
 
1249	while (!list_empty(&vm->relocated)) {
1250		struct amdgpu_vm_pt *entry;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1251
1252		entry = list_first_entry(&vm->relocated, struct amdgpu_vm_pt,
1253					 base.vm_status);
1254		amdgpu_vm_bo_idle(&entry->base);
 
 
 
 
 
 
 
 
 
 
1255
1256		r = amdgpu_vm_update_pde(&params, vm, entry);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1257		if (r)
1258			goto error;
 
 
 
 
1259	}
1260
1261	r = vm->update_funcs->commit(&params, &vm->last_update);
1262	if (r)
1263		goto error;
1264	return 0;
1265
1266error:
1267	amdgpu_vm_invalidate_pds(adev, vm);
 
 
1268	return r;
1269}
1270
1271/**
1272 * amdgpu_vm_update_flags - figure out flags for PTE updates
 
 
 
 
 
1273 *
1274 * Make sure to set the right flags for the PTEs at the desired level.
1275 */
1276static void amdgpu_vm_update_flags(struct amdgpu_vm_update_params *params,
1277				   struct amdgpu_bo *bo, unsigned level,
1278				   uint64_t pe, uint64_t addr,
1279				   unsigned count, uint32_t incr,
1280				   uint64_t flags)
1281
1282{
1283	if (level != AMDGPU_VM_PTB) {
1284		flags |= AMDGPU_PDE_PTE;
1285		amdgpu_gmc_get_vm_pde(params->adev, level, &addr, &flags);
1286
1287	} else if (params->adev->asic_type >= CHIP_VEGA10 &&
1288		   !(flags & AMDGPU_PTE_VALID) &&
1289		   !(flags & AMDGPU_PTE_PRT)) {
 
1290
1291		/* Workaround for fault priority problem on GMC9 */
1292		flags |= AMDGPU_PTE_EXECUTABLE;
 
1293	}
1294
1295	params->vm->update_funcs->update(params, bo, pe, addr, count, incr,
1296					 flags);
1297}
1298
1299/**
1300 * amdgpu_vm_fragment - get fragment for PTEs
1301 *
1302 * @params: see amdgpu_vm_update_params definition
1303 * @start: first PTE to handle
1304 * @end: last PTE to handle
1305 * @flags: hw mapping flags
1306 * @frag: resulting fragment size
1307 * @frag_end: end of this fragment
1308 *
1309 * Returns the first possible fragment for the start and end address.
1310 */
1311static void amdgpu_vm_fragment(struct amdgpu_vm_update_params *params,
1312			       uint64_t start, uint64_t end, uint64_t flags,
1313			       unsigned int *frag, uint64_t *frag_end)
 
 
1314{
1315	/**
1316	 * The MC L1 TLB supports variable sized pages, based on a fragment
1317	 * field in the PTE. When this field is set to a non-zero value, page
1318	 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
1319	 * flags are considered valid for all PTEs within the fragment range
1320	 * and corresponding mappings are assumed to be physically contiguous.
1321	 *
1322	 * The L1 TLB can store a single PTE for the whole fragment,
1323	 * significantly increasing the space available for translation
1324	 * caching. This leads to large improvements in throughput when the
1325	 * TLB is under pressure.
1326	 *
1327	 * The L2 TLB distributes small and large fragments into two
1328	 * asymmetric partitions. The large fragment cache is significantly
1329	 * larger. Thus, we try to use large fragments wherever possible.
1330	 * Userspace can support this by aligning virtual base address and
1331	 * allocation size to the fragment size.
1332	 *
1333	 * Starting with Vega10 the fragment size only controls the L1. The L2
1334	 * is now directly feed with small/huge/giant pages from the walker.
1335	 */
1336	unsigned max_frag;
1337
1338	if (params->adev->asic_type < CHIP_VEGA10)
1339		max_frag = params->adev->vm_manager.fragment_size;
1340	else
1341		max_frag = 31;
 
 
1342
1343	/* system pages are non continuously */
1344	if (params->pages_addr) {
1345		*frag = 0;
1346		*frag_end = end;
 
 
 
 
1347		return;
1348	}
1349
1350	/* This intentionally wraps around if no bit is set */
1351	*frag = min((unsigned)ffs(start) - 1, (unsigned)fls64(end - start) - 1);
1352	if (*frag >= max_frag) {
1353		*frag = max_frag;
1354		*frag_end = end & ~((1ULL << max_frag) - 1);
1355	} else {
1356		*frag_end = start + (1 << *frag);
1357	}
1358}
1359
1360/**
1361 * amdgpu_vm_update_ptes - make sure that page tables are valid
1362 *
1363 * @params: see amdgpu_vm_update_params definition
 
1364 * @start: start of GPU address range
1365 * @end: end of GPU address range
1366 * @dst: destination address to map to, the next dst inside the function
1367 * @flags: mapping flags
1368 *
1369 * Update the page tables in the range @start - @end.
1370 *
1371 * Returns:
1372 * 0 for success, -EINVAL for failure.
1373 */
1374static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
1375				 uint64_t start, uint64_t end,
1376				 uint64_t dst, uint64_t flags)
1377{
1378	struct amdgpu_device *adev = params->adev;
1379	struct amdgpu_vm_pt_cursor cursor;
1380	uint64_t frag_start = start, frag_end;
1381	unsigned int frag;
1382	int r;
1383
1384	/* figure out the initial fragment */
1385	amdgpu_vm_fragment(params, frag_start, end, flags, &frag, &frag_end);
 
1386
1387	/* walk over the address space and update the PTs */
1388	amdgpu_vm_pt_start(adev, params->vm, start, &cursor);
1389	while (cursor.pfn < end) {
1390		unsigned shift, parent_shift, mask;
1391		uint64_t incr, entry_end, pe_start;
1392		struct amdgpu_bo *pt;
1393
1394		r = amdgpu_vm_alloc_pts(params->adev, params->vm, &cursor);
1395		if (r)
1396			return r;
1397
1398		pt = cursor.entry->base.bo;
 
 
 
1399
1400		/* The root level can't be a huge page */
1401		if (cursor.level == adev->vm_manager.root_level) {
1402			if (!amdgpu_vm_pt_descendant(adev, &cursor))
1403				return -ENOENT;
1404			continue;
1405		}
1406
1407		shift = amdgpu_vm_level_shift(adev, cursor.level);
1408		parent_shift = amdgpu_vm_level_shift(adev, cursor.level - 1);
1409		if (adev->asic_type < CHIP_VEGA10 &&
1410		    (flags & AMDGPU_PTE_VALID)) {
1411			/* No huge page support before GMC v9 */
1412			if (cursor.level != AMDGPU_VM_PTB) {
1413				if (!amdgpu_vm_pt_descendant(adev, &cursor))
1414					return -ENOENT;
1415				continue;
1416			}
1417		} else if (frag < shift) {
1418			/* We can't use this level when the fragment size is
1419			 * smaller than the address shift. Go to the next
1420			 * child entry and try again.
1421			 */
1422			if (!amdgpu_vm_pt_descendant(adev, &cursor))
1423				return -ENOENT;
1424			continue;
1425		} else if (frag >= parent_shift &&
1426			   cursor.level - 1 != adev->vm_manager.root_level) {
1427			/* If the fragment size is even larger than the parent
1428			 * shift we should go up one level and check it again
1429			 * unless one level up is the root level.
1430			 */
1431			if (!amdgpu_vm_pt_ancestor(&cursor))
1432				return -ENOENT;
1433			continue;
1434		}
1435
1436		/* Looks good so far, calculate parameters for the update */
1437		incr = (uint64_t)AMDGPU_GPU_PAGE_SIZE << shift;
1438		mask = amdgpu_vm_entries_mask(adev, cursor.level);
1439		pe_start = ((cursor.pfn >> shift) & mask) * 8;
1440		entry_end = (uint64_t)(mask + 1) << shift;
1441		entry_end += cursor.pfn & ~(entry_end - 1);
1442		entry_end = min(entry_end, end);
1443
1444		do {
1445			uint64_t upd_end = min(entry_end, frag_end);
1446			unsigned nptes = (upd_end - frag_start) >> shift;
1447
1448			amdgpu_vm_update_flags(params, pt, cursor.level,
1449					       pe_start, dst, nptes, incr,
1450					       flags | AMDGPU_PTE_FRAG(frag));
1451
1452			pe_start += nptes * 8;
1453			dst += (uint64_t)nptes * AMDGPU_GPU_PAGE_SIZE << shift;
1454
1455			frag_start = upd_end;
1456			if (frag_start >= frag_end) {
1457				/* figure out the next fragment */
1458				amdgpu_vm_fragment(params, frag_start, end,
1459						   flags, &frag, &frag_end);
1460				if (frag < shift)
1461					break;
1462			}
1463		} while (frag_start < entry_end);
 
 
 
 
 
 
 
1464
1465		if (amdgpu_vm_pt_descendant(adev, &cursor)) {
1466			/* Free all child entries */
1467			while (cursor.pfn < frag_start) {
1468				amdgpu_vm_free_pts(adev, params->vm, &cursor);
1469				amdgpu_vm_pt_next(adev, &cursor);
1470			}
1471
1472		} else if (frag >= shift) {
1473			/* or just move on to the next on the same level. */
1474			amdgpu_vm_pt_next(adev, &cursor);
 
 
 
 
 
 
 
 
 
 
1475		}
 
 
 
 
 
 
 
 
1476	}
1477
1478	return 0;
1479}
1480
1481/**
1482 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
1483 *
1484 * @adev: amdgpu_device pointer
1485 * @exclusive: fence we need to sync to
1486 * @pages_addr: DMA addresses to use for mapping
1487 * @vm: requested vm
1488 * @start: start of mapped range
1489 * @last: last mapped entry
1490 * @flags: flags for the entries
1491 * @addr: addr to set the area to
1492 * @fence: optional resulting fence
1493 *
1494 * Fill in the page table entries between @start and @last.
1495 *
1496 * Returns:
1497 * 0 for success, -EINVAL for failure.
1498 */
1499static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1500				       struct dma_fence *exclusive,
1501				       dma_addr_t *pages_addr,
1502				       struct amdgpu_vm *vm,
1503				       uint64_t start, uint64_t last,
1504				       uint64_t flags, uint64_t addr,
1505				       struct dma_fence **fence)
1506{
1507	struct amdgpu_vm_update_params params;
1508	void *owner = AMDGPU_FENCE_OWNER_VM;
 
 
 
 
1509	int r;
1510
1511	memset(&params, 0, sizeof(params));
1512	params.adev = adev;
1513	params.vm = vm;
1514	params.pages_addr = pages_addr;
1515
1516	/* sync to everything except eviction fences on unmapping */
1517	if (!(flags & AMDGPU_PTE_VALID))
1518		owner = AMDGPU_FENCE_OWNER_KFD;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1519
1520	r = vm->update_funcs->prepare(&params, owner, exclusive);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1521	if (r)
1522		return r;
1523
1524	r = amdgpu_vm_update_ptes(&params, start, last + 1, addr, flags);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1525	if (r)
1526		return r;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1527
1528	return vm->update_funcs->commit(&params, fence);
 
 
1529}
1530
1531/**
1532 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
1533 *
1534 * @adev: amdgpu_device pointer
1535 * @exclusive: fence we need to sync to
1536 * @pages_addr: DMA addresses to use for mapping
1537 * @vm: requested vm
1538 * @mapping: mapped range and flags to use for the update
1539 * @flags: HW flags for the mapping
1540 * @bo_adev: amdgpu_device pointer that bo actually been allocated
1541 * @nodes: array of drm_mm_nodes with the MC addresses
1542 * @fence: optional resulting fence
1543 *
1544 * Split the mapping into smaller chunks so that each update fits
1545 * into a SDMA IB.
1546 *
1547 * Returns:
1548 * 0 for success, -EINVAL for failure.
1549 */
1550static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
1551				      struct dma_fence *exclusive,
1552				      dma_addr_t *pages_addr,
1553				      struct amdgpu_vm *vm,
1554				      struct amdgpu_bo_va_mapping *mapping,
1555				      uint64_t flags,
1556				      struct amdgpu_device *bo_adev,
1557				      struct drm_mm_node *nodes,
1558				      struct dma_fence **fence)
1559{
1560	unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size;
1561	uint64_t pfn, start = mapping->start;
1562	int r;
1563
1564	/* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1565	 * but in case of something, we filter the flags in first place
1566	 */
1567	if (!(mapping->flags & AMDGPU_PTE_READABLE))
1568		flags &= ~AMDGPU_PTE_READABLE;
1569	if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1570		flags &= ~AMDGPU_PTE_WRITEABLE;
1571
1572	flags &= ~AMDGPU_PTE_EXECUTABLE;
1573	flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
1574
1575	if (adev->asic_type >= CHIP_NAVI10) {
1576		flags &= ~AMDGPU_PTE_MTYPE_NV10_MASK;
1577		flags |= (mapping->flags & AMDGPU_PTE_MTYPE_NV10_MASK);
1578	} else {
1579		flags &= ~AMDGPU_PTE_MTYPE_VG10_MASK;
1580		flags |= (mapping->flags & AMDGPU_PTE_MTYPE_VG10_MASK);
1581	}
1582
1583	if ((mapping->flags & AMDGPU_PTE_PRT) &&
1584	    (adev->asic_type >= CHIP_VEGA10)) {
1585		flags |= AMDGPU_PTE_PRT;
1586		if (adev->asic_type >= CHIP_NAVI10) {
1587			flags |= AMDGPU_PTE_SNOOPED;
1588			flags |= AMDGPU_PTE_LOG;
1589			flags |= AMDGPU_PTE_SYSTEM;
1590		}
1591		flags &= ~AMDGPU_PTE_VALID;
1592	}
1593
1594	trace_amdgpu_vm_bo_update(mapping);
1595
1596	pfn = mapping->offset >> PAGE_SHIFT;
1597	if (nodes) {
1598		while (pfn >= nodes->size) {
1599			pfn -= nodes->size;
1600			++nodes;
1601		}
1602	}
1603
1604	do {
1605		dma_addr_t *dma_addr = NULL;
1606		uint64_t max_entries;
1607		uint64_t addr, last;
1608
1609		if (nodes) {
1610			addr = nodes->start << PAGE_SHIFT;
1611			max_entries = (nodes->size - pfn) *
1612				AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1613		} else {
1614			addr = 0;
1615			max_entries = S64_MAX;
1616		}
1617
1618		if (pages_addr) {
1619			uint64_t count;
1620
1621			for (count = 1;
1622			     count < max_entries / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1623			     ++count) {
1624				uint64_t idx = pfn + count;
1625
1626				if (pages_addr[idx] !=
1627				    (pages_addr[idx - 1] + PAGE_SIZE))
1628					break;
1629			}
1630
1631			if (count < min_linear_pages) {
1632				addr = pfn << PAGE_SHIFT;
1633				dma_addr = pages_addr;
1634			} else {
1635				addr = pages_addr[pfn];
1636				max_entries = count * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1637			}
1638
1639		} else if (flags & AMDGPU_PTE_VALID) {
1640			addr += bo_adev->vm_manager.vram_base_offset;
1641			addr += pfn << PAGE_SHIFT;
1642		}
1643
1644		last = min((uint64_t)mapping->last, start + max_entries - 1);
1645		r = amdgpu_vm_bo_update_mapping(adev, exclusive, dma_addr, vm,
1646						start, last, flags, addr,
1647						fence);
1648		if (r)
1649			return r;
1650
1651		pfn += (last - start + 1) / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1652		if (nodes && nodes->size == pfn) {
1653			pfn = 0;
1654			++nodes;
1655		}
1656		start = last + 1;
1657
1658	} while (unlikely(start != mapping->last + 1));
1659
1660	return 0;
1661}
1662
1663/**
1664 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1665 *
1666 * @adev: amdgpu_device pointer
1667 * @bo_va: requested BO and VM object
1668 * @clear: if true clear the entries
1669 *
1670 * Fill in the page table entries for @bo_va.
1671 *
1672 * Returns:
1673 * 0 for success, -EINVAL for failure.
1674 */
1675int amdgpu_vm_bo_update(struct amdgpu_device *adev,
1676			struct amdgpu_bo_va *bo_va,
1677			bool clear)
1678{
1679	struct amdgpu_bo *bo = bo_va->base.bo;
1680	struct amdgpu_vm *vm = bo_va->base.vm;
1681	struct amdgpu_bo_va_mapping *mapping;
1682	dma_addr_t *pages_addr = NULL;
1683	struct ttm_mem_reg *mem;
1684	struct drm_mm_node *nodes;
1685	struct dma_fence *exclusive, **last_update;
1686	uint64_t flags;
1687	struct amdgpu_device *bo_adev = adev;
1688	int r;
1689
1690	if (clear || !bo) {
1691		mem = NULL;
1692		nodes = NULL;
1693		exclusive = NULL;
1694	} else {
1695		struct ttm_dma_tt *ttm;
1696
1697		mem = &bo->tbo.mem;
1698		nodes = mem->mm_node;
1699		if (mem->mem_type == TTM_PL_TT) {
1700			ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm);
 
1701			pages_addr = ttm->dma_address;
1702		}
1703		exclusive = dma_resv_get_excl(bo->tbo.base.resv);
1704	}
1705
1706	if (bo) {
1707		flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1708		bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1709	} else {
1710		flags = 0x0;
1711	}
1712
1713	if (clear || (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv))
1714		last_update = &vm->last_update;
1715	else
1716		last_update = &bo_va->last_pt_update;
1717
1718	if (!clear && bo_va->base.moved) {
1719		bo_va->base.moved = false;
1720		list_splice_init(&bo_va->valids, &bo_va->invalids);
1721
1722	} else if (bo_va->cleared != clear) {
1723		list_splice_init(&bo_va->valids, &bo_va->invalids);
1724	}
1725
1726	list_for_each_entry(mapping, &bo_va->invalids, list) {
1727		r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm,
1728					       mapping, flags, bo_adev, nodes,
1729					       last_update);
1730		if (r)
1731			return r;
1732	}
1733
1734	if (vm->use_cpu_for_update) {
1735		/* Flush HDP */
1736		mb();
1737		amdgpu_asic_flush_hdp(adev, NULL);
1738	}
1739
1740	/* If the BO is not in its preferred location add it back to
1741	 * the evicted list so that it gets validated again on the
1742	 * next command submission.
1743	 */
1744	if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) {
1745		uint32_t mem_type = bo->tbo.mem.mem_type;
1746
1747		if (!(bo->preferred_domains & amdgpu_mem_type_to_domain(mem_type)))
1748			amdgpu_vm_bo_evicted(&bo_va->base);
1749		else
1750			amdgpu_vm_bo_idle(&bo_va->base);
1751	} else {
1752		amdgpu_vm_bo_done(&bo_va->base);
1753	}
1754
1755	list_splice_init(&bo_va->invalids, &bo_va->valids);
1756	bo_va->cleared = clear;
1757
1758	if (trace_amdgpu_vm_bo_mapping_enabled()) {
1759		list_for_each_entry(mapping, &bo_va->valids, list)
1760			trace_amdgpu_vm_bo_mapping(mapping);
1761	}
1762
1763	return 0;
1764}
1765
1766/**
1767 * amdgpu_vm_update_prt_state - update the global PRT state
1768 *
1769 * @adev: amdgpu_device pointer
1770 */
1771static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1772{
1773	unsigned long flags;
1774	bool enable;
1775
1776	spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1777	enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1778	adev->gmc.gmc_funcs->set_prt(adev, enable);
1779	spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1780}
1781
1782/**
1783 * amdgpu_vm_prt_get - add a PRT user
1784 *
1785 * @adev: amdgpu_device pointer
1786 */
1787static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1788{
1789	if (!adev->gmc.gmc_funcs->set_prt)
1790		return;
1791
1792	if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1793		amdgpu_vm_update_prt_state(adev);
1794}
1795
1796/**
1797 * amdgpu_vm_prt_put - drop a PRT user
1798 *
1799 * @adev: amdgpu_device pointer
1800 */
1801static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1802{
1803	if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1804		amdgpu_vm_update_prt_state(adev);
1805}
1806
1807/**
1808 * amdgpu_vm_prt_cb - callback for updating the PRT status
1809 *
1810 * @fence: fence for the callback
1811 * @_cb: the callback function
1812 */
1813static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1814{
1815	struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1816
1817	amdgpu_vm_prt_put(cb->adev);
1818	kfree(cb);
1819}
1820
1821/**
1822 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1823 *
1824 * @adev: amdgpu_device pointer
1825 * @fence: fence for the callback
1826 */
1827static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1828				 struct dma_fence *fence)
1829{
1830	struct amdgpu_prt_cb *cb;
1831
1832	if (!adev->gmc.gmc_funcs->set_prt)
1833		return;
1834
1835	cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1836	if (!cb) {
1837		/* Last resort when we are OOM */
1838		if (fence)
1839			dma_fence_wait(fence, false);
1840
1841		amdgpu_vm_prt_put(adev);
1842	} else {
1843		cb->adev = adev;
1844		if (!fence || dma_fence_add_callback(fence, &cb->cb,
1845						     amdgpu_vm_prt_cb))
1846			amdgpu_vm_prt_cb(fence, &cb->cb);
1847	}
1848}
1849
1850/**
1851 * amdgpu_vm_free_mapping - free a mapping
1852 *
1853 * @adev: amdgpu_device pointer
1854 * @vm: requested vm
1855 * @mapping: mapping to be freed
1856 * @fence: fence of the unmap operation
1857 *
1858 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1859 */
1860static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1861				   struct amdgpu_vm *vm,
1862				   struct amdgpu_bo_va_mapping *mapping,
1863				   struct dma_fence *fence)
1864{
1865	if (mapping->flags & AMDGPU_PTE_PRT)
1866		amdgpu_vm_add_prt_cb(adev, fence);
1867	kfree(mapping);
1868}
1869
1870/**
1871 * amdgpu_vm_prt_fini - finish all prt mappings
1872 *
1873 * @adev: amdgpu_device pointer
1874 * @vm: requested vm
1875 *
1876 * Register a cleanup callback to disable PRT support after VM dies.
1877 */
1878static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1879{
1880	struct dma_resv *resv = vm->root.base.bo->tbo.base.resv;
1881	struct dma_fence *excl, **shared;
1882	unsigned i, shared_count;
1883	int r;
1884
1885	r = dma_resv_get_fences_rcu(resv, &excl,
1886					      &shared_count, &shared);
1887	if (r) {
1888		/* Not enough memory to grab the fence list, as last resort
1889		 * block for all the fences to complete.
1890		 */
1891		dma_resv_wait_timeout_rcu(resv, true, false,
1892						    MAX_SCHEDULE_TIMEOUT);
1893		return;
1894	}
1895
1896	/* Add a callback for each fence in the reservation object */
1897	amdgpu_vm_prt_get(adev);
1898	amdgpu_vm_add_prt_cb(adev, excl);
1899
1900	for (i = 0; i < shared_count; ++i) {
1901		amdgpu_vm_prt_get(adev);
1902		amdgpu_vm_add_prt_cb(adev, shared[i]);
1903	}
1904
1905	kfree(shared);
1906}
1907
1908/**
1909 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1910 *
1911 * @adev: amdgpu_device pointer
1912 * @vm: requested vm
1913 * @fence: optional resulting fence (unchanged if no work needed to be done
1914 * or if an error occurred)
1915 *
1916 * Make sure all freed BOs are cleared in the PT.
 
 
1917 * PTs have to be reserved and mutex must be locked!
1918 *
1919 * Returns:
1920 * 0 for success.
1921 *
1922 */
1923int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1924			  struct amdgpu_vm *vm,
1925			  struct dma_fence **fence)
1926{
1927	struct amdgpu_bo_va_mapping *mapping;
1928	uint64_t init_pte_value = 0;
1929	struct dma_fence *f = NULL;
1930	int r;
1931
1932	while (!list_empty(&vm->freed)) {
1933		mapping = list_first_entry(&vm->freed,
1934			struct amdgpu_bo_va_mapping, list);
1935		list_del(&mapping->list);
1936
1937		if (vm->pte_support_ats &&
1938		    mapping->start < AMDGPU_GMC_HOLE_START)
1939			init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
1940
1941		r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm,
1942						mapping->start, mapping->last,
1943						init_pte_value, 0, &f);
1944		amdgpu_vm_free_mapping(adev, vm, mapping, f);
1945		if (r) {
1946			dma_fence_put(f);
1947			return r;
1948		}
1949	}
1950
1951	if (fence && f) {
1952		dma_fence_put(*fence);
1953		*fence = f;
1954	} else {
1955		dma_fence_put(f);
1956	}
1957
1958	return 0;
1959
1960}
1961
1962/**
1963 * amdgpu_vm_handle_moved - handle moved BOs in the PT
1964 *
1965 * @adev: amdgpu_device pointer
1966 * @vm: requested vm
 
1967 *
1968 * Make sure all BOs which are moved are updated in the PTs.
1969 *
1970 * Returns:
1971 * 0 for success.
1972 *
1973 * PTs have to be reserved!
1974 */
1975int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
1976			   struct amdgpu_vm *vm)
1977{
1978	struct amdgpu_bo_va *bo_va, *tmp;
1979	struct dma_resv *resv;
1980	bool clear;
1981	int r;
1982
1983	list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
1984		/* Per VM BOs never need to bo cleared in the page tables */
1985		r = amdgpu_vm_bo_update(adev, bo_va, false);
1986		if (r)
1987			return r;
1988	}
 
 
1989
1990	spin_lock(&vm->invalidated_lock);
1991	while (!list_empty(&vm->invalidated)) {
1992		bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
1993					 base.vm_status);
1994		resv = bo_va->base.bo->tbo.base.resv;
1995		spin_unlock(&vm->invalidated_lock);
1996
 
 
 
1997		/* Try to reserve the BO to avoid clearing its ptes */
1998		if (!amdgpu_vm_debug && dma_resv_trylock(resv))
1999			clear = false;
2000		/* Somebody else is using the BO right now */
2001		else
2002			clear = true;
2003
2004		r = amdgpu_vm_bo_update(adev, bo_va, clear);
2005		if (r)
2006			return r;
2007
2008		if (!clear)
2009			dma_resv_unlock(resv);
2010		spin_lock(&vm->invalidated_lock);
 
2011	}
2012	spin_unlock(&vm->invalidated_lock);
2013
2014	return 0;
2015}
2016
2017/**
2018 * amdgpu_vm_bo_add - add a bo to a specific vm
2019 *
2020 * @adev: amdgpu_device pointer
2021 * @vm: requested vm
2022 * @bo: amdgpu buffer object
2023 *
2024 * Add @bo into the requested vm.
2025 * Add @bo to the list of bos associated with the vm
2026 *
2027 * Returns:
2028 * Newly added bo_va or NULL for failure
2029 *
2030 * Object has to be reserved!
2031 */
2032struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2033				      struct amdgpu_vm *vm,
2034				      struct amdgpu_bo *bo)
2035{
2036	struct amdgpu_bo_va *bo_va;
2037
2038	bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
2039	if (bo_va == NULL) {
2040		return NULL;
2041	}
2042	amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
 
 
 
2043
2044	bo_va->ref_count = 1;
2045	INIT_LIST_HEAD(&bo_va->valids);
2046	INIT_LIST_HEAD(&bo_va->invalids);
2047
2048	if (bo && amdgpu_xgmi_same_hive(adev, amdgpu_ttm_adev(bo->tbo.bdev)) &&
2049	    (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM)) {
2050		bo_va->is_xgmi = true;
2051		mutex_lock(&adev->vm_manager.lock_pstate);
2052		/* Power up XGMI if it can be potentially used */
2053		if (++adev->vm_manager.xgmi_map_counter == 1)
2054			amdgpu_xgmi_set_pstate(adev, 1);
2055		mutex_unlock(&adev->vm_manager.lock_pstate);
2056	}
 
 
 
 
 
 
 
 
 
 
 
2057
2058	return bo_va;
2059}
2060
2061
2062/**
2063 * amdgpu_vm_bo_insert_mapping - insert a new mapping
2064 *
2065 * @adev: amdgpu_device pointer
2066 * @bo_va: bo_va to store the address
2067 * @mapping: the mapping to insert
2068 *
2069 * Insert a new mapping into all structures.
2070 */
2071static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
2072				    struct amdgpu_bo_va *bo_va,
2073				    struct amdgpu_bo_va_mapping *mapping)
2074{
2075	struct amdgpu_vm *vm = bo_va->base.vm;
2076	struct amdgpu_bo *bo = bo_va->base.bo;
2077
2078	mapping->bo_va = bo_va;
2079	list_add(&mapping->list, &bo_va->invalids);
2080	amdgpu_vm_it_insert(mapping, &vm->va);
2081
2082	if (mapping->flags & AMDGPU_PTE_PRT)
2083		amdgpu_vm_prt_get(adev);
2084
2085	if (bo && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv &&
2086	    !bo_va->base.moved) {
2087		list_move(&bo_va->base.vm_status, &vm->moved);
 
 
2088	}
2089	trace_amdgpu_vm_bo_map(bo_va, mapping);
2090}
2091
2092/**
2093 * amdgpu_vm_bo_map - map bo inside a vm
2094 *
2095 * @adev: amdgpu_device pointer
2096 * @bo_va: bo_va to store the address
2097 * @saddr: where to map the BO
2098 * @offset: requested offset in the BO
2099 * @size: BO size in bytes
2100 * @flags: attributes of pages (read/write/valid/etc.)
2101 *
2102 * Add a mapping of the BO at the specefied addr into the VM.
2103 *
2104 * Returns:
2105 * 0 for success, error for failure.
2106 *
2107 * Object has to be reserved and unreserved outside!
2108 */
2109int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2110		     struct amdgpu_bo_va *bo_va,
2111		     uint64_t saddr, uint64_t offset,
2112		     uint64_t size, uint64_t flags)
2113{
2114	struct amdgpu_bo_va_mapping *mapping, *tmp;
2115	struct amdgpu_bo *bo = bo_va->base.bo;
2116	struct amdgpu_vm *vm = bo_va->base.vm;
2117	uint64_t eaddr;
2118
2119	/* validate the parameters */
2120	if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
2121	    size == 0 || size & AMDGPU_GPU_PAGE_MASK)
2122		return -EINVAL;
2123
2124	/* make sure object fit at this offset */
2125	eaddr = saddr + size - 1;
2126	if (saddr >= eaddr ||
2127	    (bo && offset + size > amdgpu_bo_size(bo)))
2128		return -EINVAL;
2129
2130	saddr /= AMDGPU_GPU_PAGE_SIZE;
2131	eaddr /= AMDGPU_GPU_PAGE_SIZE;
2132
2133	tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2134	if (tmp) {
2135		/* bo and tmp overlap, invalid addr */
2136		dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
2137			"0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
2138			tmp->start, tmp->last + 1);
2139		return -EINVAL;
2140	}
2141
2142	mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2143	if (!mapping)
2144		return -ENOMEM;
2145
2146	mapping->start = saddr;
2147	mapping->last = eaddr;
2148	mapping->offset = offset;
2149	mapping->flags = flags;
2150
2151	amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2152
2153	return 0;
2154}
2155
2156/**
2157 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
2158 *
2159 * @adev: amdgpu_device pointer
2160 * @bo_va: bo_va to store the address
2161 * @saddr: where to map the BO
2162 * @offset: requested offset in the BO
2163 * @size: BO size in bytes
2164 * @flags: attributes of pages (read/write/valid/etc.)
2165 *
2166 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
2167 * mappings as we do so.
2168 *
2169 * Returns:
2170 * 0 for success, error for failure.
2171 *
2172 * Object has to be reserved and unreserved outside!
2173 */
2174int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
2175			     struct amdgpu_bo_va *bo_va,
2176			     uint64_t saddr, uint64_t offset,
2177			     uint64_t size, uint64_t flags)
2178{
2179	struct amdgpu_bo_va_mapping *mapping;
2180	struct amdgpu_bo *bo = bo_va->base.bo;
2181	uint64_t eaddr;
2182	int r;
2183
2184	/* validate the parameters */
2185	if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
2186	    size == 0 || size & AMDGPU_GPU_PAGE_MASK)
2187		return -EINVAL;
2188
2189	/* make sure object fit at this offset */
2190	eaddr = saddr + size - 1;
2191	if (saddr >= eaddr ||
2192	    (bo && offset + size > amdgpu_bo_size(bo)))
2193		return -EINVAL;
2194
2195	/* Allocate all the needed memory */
2196	mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2197	if (!mapping)
2198		return -ENOMEM;
2199
2200	r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
2201	if (r) {
2202		kfree(mapping);
2203		return r;
2204	}
2205
2206	saddr /= AMDGPU_GPU_PAGE_SIZE;
2207	eaddr /= AMDGPU_GPU_PAGE_SIZE;
2208
2209	mapping->start = saddr;
2210	mapping->last = eaddr;
2211	mapping->offset = offset;
2212	mapping->flags = flags;
2213
2214	amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2215
2216	return 0;
2217}
2218
2219/**
2220 * amdgpu_vm_bo_unmap - remove bo mapping from vm
2221 *
2222 * @adev: amdgpu_device pointer
2223 * @bo_va: bo_va to remove the address from
2224 * @saddr: where to the BO is mapped
2225 *
2226 * Remove a mapping of the BO at the specefied addr from the VM.
2227 *
2228 * Returns:
2229 * 0 for success, error for failure.
2230 *
2231 * Object has to be reserved and unreserved outside!
2232 */
2233int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2234		       struct amdgpu_bo_va *bo_va,
2235		       uint64_t saddr)
2236{
2237	struct amdgpu_bo_va_mapping *mapping;
2238	struct amdgpu_vm *vm = bo_va->base.vm;
2239	bool valid = true;
2240
2241	saddr /= AMDGPU_GPU_PAGE_SIZE;
2242
2243	list_for_each_entry(mapping, &bo_va->valids, list) {
2244		if (mapping->start == saddr)
2245			break;
2246	}
2247
2248	if (&mapping->list == &bo_va->valids) {
2249		valid = false;
2250
2251		list_for_each_entry(mapping, &bo_va->invalids, list) {
2252			if (mapping->start == saddr)
2253				break;
2254		}
2255
2256		if (&mapping->list == &bo_va->invalids)
2257			return -ENOENT;
2258	}
2259
2260	list_del(&mapping->list);
2261	amdgpu_vm_it_remove(mapping, &vm->va);
2262	mapping->bo_va = NULL;
2263	trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2264
2265	if (valid)
2266		list_add(&mapping->list, &vm->freed);
2267	else
2268		amdgpu_vm_free_mapping(adev, vm, mapping,
2269				       bo_va->last_pt_update);
2270
2271	return 0;
2272}
2273
2274/**
2275 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
2276 *
2277 * @adev: amdgpu_device pointer
2278 * @vm: VM structure to use
2279 * @saddr: start of the range
2280 * @size: size of the range
2281 *
2282 * Remove all mappings in a range, split them as appropriate.
2283 *
2284 * Returns:
2285 * 0 for success, error for failure.
2286 */
2287int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
2288				struct amdgpu_vm *vm,
2289				uint64_t saddr, uint64_t size)
2290{
2291	struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
2292	LIST_HEAD(removed);
2293	uint64_t eaddr;
2294
2295	eaddr = saddr + size - 1;
2296	saddr /= AMDGPU_GPU_PAGE_SIZE;
2297	eaddr /= AMDGPU_GPU_PAGE_SIZE;
2298
2299	/* Allocate all the needed memory */
2300	before = kzalloc(sizeof(*before), GFP_KERNEL);
2301	if (!before)
2302		return -ENOMEM;
2303	INIT_LIST_HEAD(&before->list);
2304
2305	after = kzalloc(sizeof(*after), GFP_KERNEL);
2306	if (!after) {
2307		kfree(before);
2308		return -ENOMEM;
2309	}
2310	INIT_LIST_HEAD(&after->list);
2311
2312	/* Now gather all removed mappings */
2313	tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2314	while (tmp) {
2315		/* Remember mapping split at the start */
2316		if (tmp->start < saddr) {
2317			before->start = tmp->start;
2318			before->last = saddr - 1;
2319			before->offset = tmp->offset;
2320			before->flags = tmp->flags;
2321			before->bo_va = tmp->bo_va;
2322			list_add(&before->list, &tmp->bo_va->invalids);
2323		}
2324
2325		/* Remember mapping split at the end */
2326		if (tmp->last > eaddr) {
2327			after->start = eaddr + 1;
2328			after->last = tmp->last;
2329			after->offset = tmp->offset;
2330			after->offset += after->start - tmp->start;
2331			after->flags = tmp->flags;
2332			after->bo_va = tmp->bo_va;
2333			list_add(&after->list, &tmp->bo_va->invalids);
2334		}
2335
2336		list_del(&tmp->list);
2337		list_add(&tmp->list, &removed);
2338
2339		tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
2340	}
2341
2342	/* And free them up */
2343	list_for_each_entry_safe(tmp, next, &removed, list) {
2344		amdgpu_vm_it_remove(tmp, &vm->va);
2345		list_del(&tmp->list);
2346
2347		if (tmp->start < saddr)
2348		    tmp->start = saddr;
2349		if (tmp->last > eaddr)
2350		    tmp->last = eaddr;
2351
2352		tmp->bo_va = NULL;
2353		list_add(&tmp->list, &vm->freed);
2354		trace_amdgpu_vm_bo_unmap(NULL, tmp);
2355	}
2356
2357	/* Insert partial mapping before the range */
2358	if (!list_empty(&before->list)) {
2359		amdgpu_vm_it_insert(before, &vm->va);
2360		if (before->flags & AMDGPU_PTE_PRT)
2361			amdgpu_vm_prt_get(adev);
2362	} else {
2363		kfree(before);
2364	}
2365
2366	/* Insert partial mapping after the range */
2367	if (!list_empty(&after->list)) {
2368		amdgpu_vm_it_insert(after, &vm->va);
2369		if (after->flags & AMDGPU_PTE_PRT)
2370			amdgpu_vm_prt_get(adev);
2371	} else {
2372		kfree(after);
2373	}
2374
2375	return 0;
2376}
2377
2378/**
2379 * amdgpu_vm_bo_lookup_mapping - find mapping by address
2380 *
2381 * @vm: the requested VM
2382 * @addr: the address
2383 *
2384 * Find a mapping by it's address.
2385 *
2386 * Returns:
2387 * The amdgpu_bo_va_mapping matching for addr or NULL
2388 *
2389 */
2390struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
2391							 uint64_t addr)
2392{
2393	return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
2394}
2395
2396/**
2397 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
2398 *
2399 * @vm: the requested vm
2400 * @ticket: CS ticket
2401 *
2402 * Trace all mappings of BOs reserved during a command submission.
2403 */
2404void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
2405{
2406	struct amdgpu_bo_va_mapping *mapping;
2407
2408	if (!trace_amdgpu_vm_bo_cs_enabled())
2409		return;
2410
2411	for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
2412	     mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
2413		if (mapping->bo_va && mapping->bo_va->base.bo) {
2414			struct amdgpu_bo *bo;
2415
2416			bo = mapping->bo_va->base.bo;
2417			if (dma_resv_locking_ctx(bo->tbo.base.resv) !=
2418			    ticket)
2419				continue;
2420		}
2421
2422		trace_amdgpu_vm_bo_cs(mapping);
2423	}
2424}
2425
2426/**
2427 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
2428 *
2429 * @adev: amdgpu_device pointer
2430 * @bo_va: requested bo_va
2431 *
2432 * Remove @bo_va->bo from the requested vm.
2433 *
2434 * Object have to be reserved!
2435 */
2436void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2437		      struct amdgpu_bo_va *bo_va)
2438{
2439	struct amdgpu_bo_va_mapping *mapping, *next;
2440	struct amdgpu_bo *bo = bo_va->base.bo;
2441	struct amdgpu_vm *vm = bo_va->base.vm;
2442	struct amdgpu_vm_bo_base **base;
2443
2444	if (bo) {
2445		if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)
2446			vm->bulk_moveable = false;
2447
2448		for (base = &bo_va->base.bo->vm_bo; *base;
2449		     base = &(*base)->next) {
2450			if (*base != &bo_va->base)
2451				continue;
2452
2453			*base = bo_va->base.next;
2454			break;
2455		}
2456	}
2457
2458	spin_lock(&vm->invalidated_lock);
2459	list_del(&bo_va->base.vm_status);
2460	spin_unlock(&vm->invalidated_lock);
2461
2462	list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2463		list_del(&mapping->list);
2464		amdgpu_vm_it_remove(mapping, &vm->va);
2465		mapping->bo_va = NULL;
2466		trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2467		list_add(&mapping->list, &vm->freed);
2468	}
2469	list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2470		list_del(&mapping->list);
2471		amdgpu_vm_it_remove(mapping, &vm->va);
2472		amdgpu_vm_free_mapping(adev, vm, mapping,
2473				       bo_va->last_pt_update);
2474	}
2475
2476	dma_fence_put(bo_va->last_pt_update);
2477
2478	if (bo && bo_va->is_xgmi) {
2479		mutex_lock(&adev->vm_manager.lock_pstate);
2480		if (--adev->vm_manager.xgmi_map_counter == 0)
2481			amdgpu_xgmi_set_pstate(adev, 0);
2482		mutex_unlock(&adev->vm_manager.lock_pstate);
2483	}
2484
2485	kfree(bo_va);
2486}
2487
2488/**
2489 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2490 *
2491 * @adev: amdgpu_device pointer
 
2492 * @bo: amdgpu buffer object
2493 * @evicted: is the BO evicted
2494 *
2495 * Mark @bo as invalid.
2496 */
2497void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2498			     struct amdgpu_bo *bo, bool evicted)
2499{
2500	struct amdgpu_vm_bo_base *bo_base;
2501
2502	/* shadow bo doesn't have bo base, its validation needs its parent */
2503	if (bo->parent && bo->parent->shadow == bo)
2504		bo = bo->parent;
2505
2506	for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
2507		struct amdgpu_vm *vm = bo_base->vm;
2508
2509		if (evicted && bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv) {
2510			amdgpu_vm_bo_evicted(bo_base);
 
 
 
 
 
 
 
2511			continue;
2512		}
2513
2514		if (bo_base->moved)
 
 
 
 
2515			continue;
2516		bo_base->moved = true;
2517
2518		if (bo->tbo.type == ttm_bo_type_kernel)
2519			amdgpu_vm_bo_relocated(bo_base);
2520		else if (bo->tbo.base.resv == vm->root.base.bo->tbo.base.resv)
2521			amdgpu_vm_bo_moved(bo_base);
2522		else
2523			amdgpu_vm_bo_invalidated(bo_base);
2524	}
2525}
2526
2527/**
2528 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
2529 *
2530 * @vm_size: VM size
2531 *
2532 * Returns:
2533 * VM page table as power of two
2534 */
2535static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2536{
2537	/* Total bits covered by PD + PTs */
2538	unsigned bits = ilog2(vm_size) + 18;
2539
2540	/* Make sure the PD is 4K in size up to 8GB address space.
2541	   Above that split equal between PD and PTs */
2542	if (vm_size <= 8)
2543		return (bits - 9);
2544	else
2545		return ((bits + 3) / 2);
2546}
2547
2548/**
2549 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2550 *
2551 * @adev: amdgpu_device pointer
2552 * @min_vm_size: the minimum vm size in GB if it's set auto
2553 * @fragment_size_default: Default PTE fragment size
2554 * @max_level: max VMPT level
2555 * @max_bits: max address space size in bits
2556 *
2557 */
2558void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2559			   uint32_t fragment_size_default, unsigned max_level,
2560			   unsigned max_bits)
2561{
2562	unsigned int max_size = 1 << (max_bits - 30);
2563	unsigned int vm_size;
2564	uint64_t tmp;
2565
2566	/* adjust vm size first */
2567	if (amdgpu_vm_size != -1) {
 
 
2568		vm_size = amdgpu_vm_size;
2569		if (vm_size > max_size) {
2570			dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2571				 amdgpu_vm_size, max_size);
2572			vm_size = max_size;
2573		}
2574	} else {
2575		struct sysinfo si;
2576		unsigned int phys_ram_gb;
2577
2578		/* Optimal VM size depends on the amount of physical
2579		 * RAM available. Underlying requirements and
2580		 * assumptions:
2581		 *
2582		 *  - Need to map system memory and VRAM from all GPUs
2583		 *     - VRAM from other GPUs not known here
2584		 *     - Assume VRAM <= system memory
2585		 *  - On GFX8 and older, VM space can be segmented for
2586		 *    different MTYPEs
2587		 *  - Need to allow room for fragmentation, guard pages etc.
2588		 *
2589		 * This adds up to a rough guess of system memory x3.
2590		 * Round up to power of two to maximize the available
2591		 * VM size with the given page table size.
2592		 */
2593		si_meminfo(&si);
2594		phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2595			       (1 << 30) - 1) >> 30;
2596		vm_size = roundup_pow_of_two(
2597			min(max(phys_ram_gb * 3, min_vm_size), max_size));
2598	}
2599
2600	adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2601
2602	tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2603	if (amdgpu_vm_block_size != -1)
2604		tmp >>= amdgpu_vm_block_size - 9;
2605	tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2606	adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
2607	switch (adev->vm_manager.num_level) {
2608	case 3:
2609		adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2610		break;
2611	case 2:
2612		adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2613		break;
2614	case 1:
2615		adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2616		break;
2617	default:
2618		dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2619	}
2620	/* block size depends on vm size and hw setup*/
2621	if (amdgpu_vm_block_size != -1)
2622		adev->vm_manager.block_size =
2623			min((unsigned)amdgpu_vm_block_size, max_bits
2624			    - AMDGPU_GPU_PAGE_SHIFT
2625			    - 9 * adev->vm_manager.num_level);
2626	else if (adev->vm_manager.num_level > 1)
2627		adev->vm_manager.block_size = 9;
2628	else
2629		adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2630
2631	if (amdgpu_vm_fragment_size == -1)
2632		adev->vm_manager.fragment_size = fragment_size_default;
2633	else
2634		adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2635
2636	DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2637		 vm_size, adev->vm_manager.num_level + 1,
2638		 adev->vm_manager.block_size,
2639		 adev->vm_manager.fragment_size);
2640}
2641
2642/**
2643 * amdgpu_vm_wait_idle - wait for the VM to become idle
2644 *
2645 * @vm: VM object to wait for
2646 * @timeout: timeout to wait for VM to become idle
2647 */
2648long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
2649{
2650	return dma_resv_wait_timeout_rcu(vm->root.base.bo->tbo.base.resv,
2651						   true, true, timeout);
2652}
2653
2654/**
2655 * amdgpu_vm_init - initialize a vm instance
2656 *
2657 * @adev: amdgpu_device pointer
2658 * @vm: requested vm
2659 * @vm_context: Indicates if it GFX or Compute context
2660 * @pasid: Process address space identifier
2661 *
2662 * Init @vm fields.
2663 *
2664 * Returns:
2665 * 0 for success, error for failure.
2666 */
2667int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
2668		   int vm_context, unsigned int pasid)
2669{
2670	struct amdgpu_bo_param bp;
2671	struct amdgpu_bo *root;
 
 
 
 
 
2672	int r, i;
2673
2674	vm->va = RB_ROOT_CACHED;
2675	for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2676		vm->reserved_vmid[i] = NULL;
 
2677	INIT_LIST_HEAD(&vm->evicted);
2678	INIT_LIST_HEAD(&vm->relocated);
2679	INIT_LIST_HEAD(&vm->moved);
2680	INIT_LIST_HEAD(&vm->idle);
2681	INIT_LIST_HEAD(&vm->invalidated);
2682	spin_lock_init(&vm->invalidated_lock);
2683	INIT_LIST_HEAD(&vm->freed);
2684
2685	/* create scheduler entity for page table updates */
2686	r = drm_sched_entity_init(&vm->entity, adev->vm_manager.vm_pte_rqs,
2687				  adev->vm_manager.vm_pte_num_rqs, NULL);
 
 
 
 
 
2688	if (r)
2689		return r;
2690
2691	vm->pte_support_ats = false;
2692
2693	if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) {
2694		vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2695						AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2696
2697		if (adev->asic_type == CHIP_RAVEN)
2698			vm->pte_support_ats = true;
2699	} else {
2700		vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2701						AMDGPU_VM_USE_CPU_FOR_GFX);
2702	}
2703	DRM_DEBUG_DRIVER("VM update mode is %s\n",
2704			 vm->use_cpu_for_update ? "CPU" : "SDMA");
2705	WARN_ONCE((vm->use_cpu_for_update && !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2706		  "CPU update of VM recommended only for large BAR system\n");
 
2707
 
2708	if (vm->use_cpu_for_update)
2709		vm->update_funcs = &amdgpu_vm_cpu_funcs;
2710	else
2711		vm->update_funcs = &amdgpu_vm_sdma_funcs;
2712	vm->last_update = NULL;
2713
2714	amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, &bp);
2715	if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE)
2716		bp.flags &= ~AMDGPU_GEM_CREATE_SHADOW;
2717	r = amdgpu_bo_create(adev, &bp, &root);
2718	if (r)
2719		goto error_free_sched_entity;
2720
2721	r = amdgpu_bo_reserve(root, true);
2722	if (r)
2723		goto error_free_root;
2724
2725	r = dma_resv_reserve_shared(root->tbo.base.resv, 1);
2726	if (r)
2727		goto error_unreserve;
2728
2729	amdgpu_vm_bo_base_init(&vm->root.base, vm, root);
2730
2731	r = amdgpu_vm_clear_bo(adev, vm, root);
2732	if (r)
2733		goto error_unreserve;
2734
 
 
 
2735	amdgpu_bo_unreserve(vm->root.base.bo);
2736
2737	if (pasid) {
2738		unsigned long flags;
2739
2740		spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2741		r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
2742			      GFP_ATOMIC);
2743		spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2744		if (r < 0)
2745			goto error_free_root;
2746
2747		vm->pasid = pasid;
2748	}
2749
2750	INIT_KFIFO(vm->faults);
 
2751
2752	return 0;
2753
2754error_unreserve:
2755	amdgpu_bo_unreserve(vm->root.base.bo);
2756
2757error_free_root:
2758	amdgpu_bo_unref(&vm->root.base.bo->shadow);
2759	amdgpu_bo_unref(&vm->root.base.bo);
2760	vm->root.base.bo = NULL;
2761
2762error_free_sched_entity:
2763	drm_sched_entity_destroy(&vm->entity);
2764
2765	return r;
2766}
2767
2768/**
2769 * amdgpu_vm_check_clean_reserved - check if a VM is clean
2770 *
2771 * @adev: amdgpu_device pointer
2772 * @vm: the VM to check
2773 *
2774 * check all entries of the root PD, if any subsequent PDs are allocated,
2775 * it means there are page table creating and filling, and is no a clean
2776 * VM
2777 *
2778 * Returns:
2779 *	0 if this VM is clean
2780 */
2781static int amdgpu_vm_check_clean_reserved(struct amdgpu_device *adev,
2782	struct amdgpu_vm *vm)
2783{
2784	enum amdgpu_vm_level root = adev->vm_manager.root_level;
2785	unsigned int entries = amdgpu_vm_num_entries(adev, root);
2786	unsigned int i = 0;
2787
2788	if (!(vm->root.entries))
2789		return 0;
2790
2791	for (i = 0; i < entries; i++) {
2792		if (vm->root.entries[i].base.bo)
2793			return -EINVAL;
2794	}
2795
2796	return 0;
2797}
2798
2799/**
2800 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
2801 *
2802 * @adev: amdgpu_device pointer
2803 * @vm: requested vm
2804 *
2805 * This only works on GFX VMs that don't have any BOs added and no
2806 * page tables allocated yet.
2807 *
2808 * Changes the following VM parameters:
2809 * - use_cpu_for_update
2810 * - pte_supports_ats
2811 * - pasid (old PASID is released, because compute manages its own PASIDs)
2812 *
2813 * Reinitializes the page directory to reflect the changed ATS
2814 * setting.
 
2815 *
2816 * Returns:
2817 * 0 for success, -errno for errors.
2818 */
2819int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm, unsigned int pasid)
2820{
2821	bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
2822	int r;
2823
2824	r = amdgpu_bo_reserve(vm->root.base.bo, true);
2825	if (r)
2826		return r;
2827
2828	/* Sanity checks */
2829	r = amdgpu_vm_check_clean_reserved(adev, vm);
2830	if (r)
2831		goto unreserve_bo;
2832
2833	if (pasid) {
2834		unsigned long flags;
2835
2836		spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2837		r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
2838			      GFP_ATOMIC);
2839		spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2840
2841		if (r == -ENOSPC)
2842			goto unreserve_bo;
2843		r = 0;
2844	}
2845
2846	/* Check if PD needs to be reinitialized and do it before
2847	 * changing any other state, in case it fails.
2848	 */
2849	if (pte_support_ats != vm->pte_support_ats) {
2850		vm->pte_support_ats = pte_support_ats;
2851		r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo);
 
2852		if (r)
2853			goto free_idr;
2854	}
2855
2856	/* Update VM state */
2857	vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2858				    AMDGPU_VM_USE_CPU_FOR_COMPUTE);
 
2859	DRM_DEBUG_DRIVER("VM update mode is %s\n",
2860			 vm->use_cpu_for_update ? "CPU" : "SDMA");
2861	WARN_ONCE((vm->use_cpu_for_update && !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2862		  "CPU update of VM recommended only for large BAR system\n");
2863
2864	if (vm->use_cpu_for_update)
2865		vm->update_funcs = &amdgpu_vm_cpu_funcs;
2866	else
2867		vm->update_funcs = &amdgpu_vm_sdma_funcs;
2868	dma_fence_put(vm->last_update);
2869	vm->last_update = NULL;
2870
2871	if (vm->pasid) {
2872		unsigned long flags;
2873
2874		spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2875		idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
2876		spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2877
2878		/* Free the original amdgpu allocated pasid
2879		 * Will be replaced with kfd allocated pasid
2880		 */
2881		amdgpu_pasid_free(vm->pasid);
2882		vm->pasid = 0;
2883	}
2884
2885	/* Free the shadow bo for compute VM */
2886	amdgpu_bo_unref(&vm->root.base.bo->shadow);
2887
2888	if (pasid)
2889		vm->pasid = pasid;
2890
2891	goto unreserve_bo;
2892
2893free_idr:
2894	if (pasid) {
2895		unsigned long flags;
2896
2897		spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2898		idr_remove(&adev->vm_manager.pasid_idr, pasid);
2899		spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2900	}
2901unreserve_bo:
2902	amdgpu_bo_unreserve(vm->root.base.bo);
2903	return r;
2904}
2905
2906/**
2907 * amdgpu_vm_release_compute - release a compute vm
2908 * @adev: amdgpu_device pointer
2909 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
 
 
2910 *
2911 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
2912 * pasid from vm. Compute should stop use of vm after this call.
2913 */
2914void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
 
 
2915{
2916	if (vm->pasid) {
2917		unsigned long flags;
2918
2919		spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2920		idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
2921		spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
 
 
2922	}
2923	vm->pasid = 0;
 
 
 
 
 
 
2924}
2925
2926/**
2927 * amdgpu_vm_fini - tear down a vm instance
2928 *
2929 * @adev: amdgpu_device pointer
2930 * @vm: requested vm
2931 *
2932 * Tear down @vm.
2933 * Unbind the VM and remove all bos from the vm bo list
2934 */
2935void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2936{
2937	struct amdgpu_bo_va_mapping *mapping, *tmp;
2938	bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
2939	struct amdgpu_bo *root;
 
2940	int i, r;
2941
2942	amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
2943
 
 
 
 
2944	if (vm->pasid) {
2945		unsigned long flags;
2946
2947		spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2948		idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
2949		spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2950	}
2951
2952	drm_sched_entity_destroy(&vm->entity);
2953
2954	if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
2955		dev_err(adev->dev, "still active bo inside vm\n");
2956	}
2957	rbtree_postorder_for_each_entry_safe(mapping, tmp,
2958					     &vm->va.rb_root, rb) {
2959		/* Don't remove the mapping here, we don't want to trigger a
2960		 * rebalance and the tree is about to be destroyed anyway.
2961		 */
2962		list_del(&mapping->list);
 
2963		kfree(mapping);
2964	}
2965	list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
2966		if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
2967			amdgpu_vm_prt_fini(adev, vm);
2968			prt_fini_needed = false;
2969		}
2970
2971		list_del(&mapping->list);
2972		amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
2973	}
2974
2975	root = amdgpu_bo_ref(vm->root.base.bo);
2976	r = amdgpu_bo_reserve(root, true);
2977	if (r) {
2978		dev_err(adev->dev, "Leaking page tables because BO reservation failed\n");
2979	} else {
2980		amdgpu_vm_free_pts(adev, vm, NULL);
 
2981		amdgpu_bo_unreserve(root);
2982	}
2983	amdgpu_bo_unref(&root);
2984	WARN_ON(vm->root.base.bo);
2985	dma_fence_put(vm->last_update);
2986	for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2987		amdgpu_vmid_free_reserved(adev, vm, i);
2988}
2989
2990/**
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2991 * amdgpu_vm_manager_init - init the VM manager
2992 *
2993 * @adev: amdgpu_device pointer
2994 *
2995 * Initialize the VM manager structures
2996 */
2997void amdgpu_vm_manager_init(struct amdgpu_device *adev)
2998{
2999	unsigned i;
3000
3001	amdgpu_vmid_mgr_init(adev);
3002
3003	adev->vm_manager.fence_context =
3004		dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3005	for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
3006		adev->vm_manager.seqno[i] = 0;
3007
 
3008	spin_lock_init(&adev->vm_manager.prt_lock);
3009	atomic_set(&adev->vm_manager.num_prt_users, 0);
3010
3011	/* If not overridden by the user, by default, only in large BAR systems
3012	 * Compute VM tables will be updated by CPU
3013	 */
3014#ifdef CONFIG_X86_64
3015	if (amdgpu_vm_update_mode == -1) {
3016		if (amdgpu_gmc_vram_full_visible(&adev->gmc))
3017			adev->vm_manager.vm_update_mode =
3018				AMDGPU_VM_USE_CPU_FOR_COMPUTE;
3019		else
3020			adev->vm_manager.vm_update_mode = 0;
3021	} else
3022		adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
3023#else
3024	adev->vm_manager.vm_update_mode = 0;
3025#endif
3026
3027	idr_init(&adev->vm_manager.pasid_idr);
3028	spin_lock_init(&adev->vm_manager.pasid_lock);
3029
3030	adev->vm_manager.xgmi_map_counter = 0;
3031	mutex_init(&adev->vm_manager.lock_pstate);
3032}
3033
3034/**
3035 * amdgpu_vm_manager_fini - cleanup VM manager
3036 *
3037 * @adev: amdgpu_device pointer
3038 *
3039 * Cleanup the VM manager and free resources.
3040 */
3041void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
3042{
3043	WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr));
3044	idr_destroy(&adev->vm_manager.pasid_idr);
3045
3046	amdgpu_vmid_mgr_fini(adev);
3047}
3048
3049/**
3050 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
3051 *
3052 * @dev: drm device pointer
3053 * @data: drm_amdgpu_vm
3054 * @filp: drm file pointer
3055 *
3056 * Returns:
3057 * 0 for success, -errno for errors.
3058 */
3059int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
3060{
3061	union drm_amdgpu_vm *args = data;
3062	struct amdgpu_device *adev = dev->dev_private;
3063	struct amdgpu_fpriv *fpriv = filp->driver_priv;
3064	int r;
3065
3066	switch (args->in.op) {
3067	case AMDGPU_VM_OP_RESERVE_VMID:
3068		/* current, we only have requirement to reserve vmid from gfxhub */
3069		r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);
3070		if (r)
3071			return r;
3072		break;
3073	case AMDGPU_VM_OP_UNRESERVE_VMID:
3074		amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);
3075		break;
3076	default:
3077		return -EINVAL;
3078	}
3079
3080	return 0;
3081}
3082
3083/**
3084 * amdgpu_vm_get_task_info - Extracts task info for a PASID.
3085 *
3086 * @adev: drm device pointer
3087 * @pasid: PASID identifier for VM
3088 * @task_info: task_info to fill.
3089 */
3090void amdgpu_vm_get_task_info(struct amdgpu_device *adev, unsigned int pasid,
3091			 struct amdgpu_task_info *task_info)
3092{
3093	struct amdgpu_vm *vm;
3094	unsigned long flags;
3095
3096	spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3097
3098	vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3099	if (vm)
3100		*task_info = vm->task_info;
3101
3102	spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3103}
3104
3105/**
3106 * amdgpu_vm_set_task_info - Sets VMs task info.
3107 *
3108 * @vm: vm for which to set the info
3109 */
3110void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
3111{
3112	if (!vm->task_info.pid) {
3113		vm->task_info.pid = current->pid;
3114		get_task_comm(vm->task_info.task_name, current);
3115
3116		if (current->group_leader->mm == current->mm) {
3117			vm->task_info.tgid = current->group_leader->pid;
3118			get_task_comm(vm->task_info.process_name, current->group_leader);
3119		}
3120	}
3121}