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1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#include <linux/dma-fence-array.h>
29#include <linux/interval_tree_generic.h>
30#include <linux/idr.h>
31#include <drm/drmP.h>
32#include <drm/amdgpu_drm.h>
33#include "amdgpu.h"
34#include "amdgpu_trace.h"
35#include "amdgpu_amdkfd.h"
36
37/*
38 * GPUVM
39 * GPUVM is similar to the legacy gart on older asics, however
40 * rather than there being a single global gart table
41 * for the entire GPU, there are multiple VM page tables active
42 * at any given time. The VM page tables can contain a mix
43 * vram pages and system memory pages and system memory pages
44 * can be mapped as snooped (cached system pages) or unsnooped
45 * (uncached system pages).
46 * Each VM has an ID associated with it and there is a page table
47 * associated with each VMID. When execting a command buffer,
48 * the kernel tells the the ring what VMID to use for that command
49 * buffer. VMIDs are allocated dynamically as commands are submitted.
50 * The userspace drivers maintain their own address space and the kernel
51 * sets up their pages tables accordingly when they submit their
52 * command buffers and a VMID is assigned.
53 * Cayman/Trinity support up to 8 active VMs at any given time;
54 * SI supports 16.
55 */
56
57#define START(node) ((node)->start)
58#define LAST(node) ((node)->last)
59
60INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
61 START, LAST, static, amdgpu_vm_it)
62
63#undef START
64#undef LAST
65
66/* Local structure. Encapsulate some VM table update parameters to reduce
67 * the number of function parameters
68 */
69struct amdgpu_pte_update_params {
70 /* amdgpu device we do this update for */
71 struct amdgpu_device *adev;
72 /* optional amdgpu_vm we do this update for */
73 struct amdgpu_vm *vm;
74 /* address where to copy page table entries from */
75 uint64_t src;
76 /* indirect buffer to fill with commands */
77 struct amdgpu_ib *ib;
78 /* Function which actually does the update */
79 void (*func)(struct amdgpu_pte_update_params *params,
80 struct amdgpu_bo *bo, uint64_t pe,
81 uint64_t addr, unsigned count, uint32_t incr,
82 uint64_t flags);
83 /* The next two are used during VM update by CPU
84 * DMA addresses to use for mapping
85 * Kernel pointer of PD/PT BO that needs to be updated
86 */
87 dma_addr_t *pages_addr;
88 void *kptr;
89};
90
91/* Helper to disable partial resident texture feature from a fence callback */
92struct amdgpu_prt_cb {
93 struct amdgpu_device *adev;
94 struct dma_fence_cb cb;
95};
96
97/**
98 * amdgpu_vm_level_shift - return the addr shift for each level
99 *
100 * @adev: amdgpu_device pointer
101 *
102 * Returns the number of bits the pfn needs to be right shifted for a level.
103 */
104static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
105 unsigned level)
106{
107 unsigned shift = 0xff;
108
109 switch (level) {
110 case AMDGPU_VM_PDB2:
111 case AMDGPU_VM_PDB1:
112 case AMDGPU_VM_PDB0:
113 shift = 9 * (AMDGPU_VM_PDB0 - level) +
114 adev->vm_manager.block_size;
115 break;
116 case AMDGPU_VM_PTB:
117 shift = 0;
118 break;
119 default:
120 dev_err(adev->dev, "the level%d isn't supported.\n", level);
121 }
122
123 return shift;
124}
125
126/**
127 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
128 *
129 * @adev: amdgpu_device pointer
130 *
131 * Calculate the number of entries in a page directory or page table.
132 */
133static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
134 unsigned level)
135{
136 unsigned shift = amdgpu_vm_level_shift(adev,
137 adev->vm_manager.root_level);
138
139 if (level == adev->vm_manager.root_level)
140 /* For the root directory */
141 return round_up(adev->vm_manager.max_pfn, 1 << shift) >> shift;
142 else if (level != AMDGPU_VM_PTB)
143 /* Everything in between */
144 return 512;
145 else
146 /* For the page tables on the leaves */
147 return AMDGPU_VM_PTE_COUNT(adev);
148}
149
150/**
151 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
152 *
153 * @adev: amdgpu_device pointer
154 *
155 * Calculate the size of the BO for a page directory or page table in bytes.
156 */
157static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
158{
159 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
160}
161
162/**
163 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
164 *
165 * @vm: vm providing the BOs
166 * @validated: head of validation list
167 * @entry: entry to add
168 *
169 * Add the page directory to the list of BOs to
170 * validate for command submission.
171 */
172void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
173 struct list_head *validated,
174 struct amdgpu_bo_list_entry *entry)
175{
176 entry->robj = vm->root.base.bo;
177 entry->priority = 0;
178 entry->tv.bo = &entry->robj->tbo;
179 entry->tv.shared = true;
180 entry->user_pages = NULL;
181 list_add(&entry->tv.head, validated);
182}
183
184/**
185 * amdgpu_vm_validate_pt_bos - validate the page table BOs
186 *
187 * @adev: amdgpu device pointer
188 * @vm: vm providing the BOs
189 * @validate: callback to do the validation
190 * @param: parameter for the validation callback
191 *
192 * Validate the page table BOs on command submission if neccessary.
193 */
194int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
195 int (*validate)(void *p, struct amdgpu_bo *bo),
196 void *param)
197{
198 struct ttm_bo_global *glob = adev->mman.bdev.glob;
199 int r;
200
201 spin_lock(&vm->status_lock);
202 while (!list_empty(&vm->evicted)) {
203 struct amdgpu_vm_bo_base *bo_base;
204 struct amdgpu_bo *bo;
205
206 bo_base = list_first_entry(&vm->evicted,
207 struct amdgpu_vm_bo_base,
208 vm_status);
209 spin_unlock(&vm->status_lock);
210
211 bo = bo_base->bo;
212 BUG_ON(!bo);
213 if (bo->parent) {
214 r = validate(param, bo);
215 if (r)
216 return r;
217
218 spin_lock(&glob->lru_lock);
219 ttm_bo_move_to_lru_tail(&bo->tbo);
220 if (bo->shadow)
221 ttm_bo_move_to_lru_tail(&bo->shadow->tbo);
222 spin_unlock(&glob->lru_lock);
223 }
224
225 if (bo->tbo.type == ttm_bo_type_kernel &&
226 vm->use_cpu_for_update) {
227 r = amdgpu_bo_kmap(bo, NULL);
228 if (r)
229 return r;
230 }
231
232 spin_lock(&vm->status_lock);
233 if (bo->tbo.type != ttm_bo_type_kernel)
234 list_move(&bo_base->vm_status, &vm->moved);
235 else
236 list_move(&bo_base->vm_status, &vm->relocated);
237 }
238 spin_unlock(&vm->status_lock);
239
240 return 0;
241}
242
243/**
244 * amdgpu_vm_ready - check VM is ready for updates
245 *
246 * @vm: VM to check
247 *
248 * Check if all VM PDs/PTs are ready for updates
249 */
250bool amdgpu_vm_ready(struct amdgpu_vm *vm)
251{
252 bool ready;
253
254 spin_lock(&vm->status_lock);
255 ready = list_empty(&vm->evicted);
256 spin_unlock(&vm->status_lock);
257
258 return ready;
259}
260
261/**
262 * amdgpu_vm_clear_bo - initially clear the PDs/PTs
263 *
264 * @adev: amdgpu_device pointer
265 * @bo: BO to clear
266 * @level: level this BO is at
267 *
268 * Root PD needs to be reserved when calling this.
269 */
270static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
271 struct amdgpu_vm *vm, struct amdgpu_bo *bo,
272 unsigned level, bool pte_support_ats)
273{
274 struct ttm_operation_ctx ctx = { true, false };
275 struct dma_fence *fence = NULL;
276 unsigned entries, ats_entries;
277 struct amdgpu_ring *ring;
278 struct amdgpu_job *job;
279 uint64_t addr;
280 int r;
281
282 addr = amdgpu_bo_gpu_offset(bo);
283 entries = amdgpu_bo_size(bo) / 8;
284
285 if (pte_support_ats) {
286 if (level == adev->vm_manager.root_level) {
287 ats_entries = amdgpu_vm_level_shift(adev, level);
288 ats_entries += AMDGPU_GPU_PAGE_SHIFT;
289 ats_entries = AMDGPU_VA_HOLE_START >> ats_entries;
290 ats_entries = min(ats_entries, entries);
291 entries -= ats_entries;
292 } else {
293 ats_entries = entries;
294 entries = 0;
295 }
296 } else {
297 ats_entries = 0;
298 }
299
300 ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
301
302 r = reservation_object_reserve_shared(bo->tbo.resv);
303 if (r)
304 return r;
305
306 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
307 if (r)
308 goto error;
309
310 r = amdgpu_job_alloc_with_ib(adev, 64, &job);
311 if (r)
312 goto error;
313
314 if (ats_entries) {
315 uint64_t ats_value;
316
317 ats_value = AMDGPU_PTE_DEFAULT_ATC;
318 if (level != AMDGPU_VM_PTB)
319 ats_value |= AMDGPU_PDE_PTE;
320
321 amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
322 ats_entries, 0, ats_value);
323 addr += ats_entries * 8;
324 }
325
326 if (entries)
327 amdgpu_vm_set_pte_pde(adev, &job->ibs[0], addr, 0,
328 entries, 0, 0);
329
330 amdgpu_ring_pad_ib(ring, &job->ibs[0]);
331
332 WARN_ON(job->ibs[0].length_dw > 64);
333 r = amdgpu_sync_resv(adev, &job->sync, bo->tbo.resv,
334 AMDGPU_FENCE_OWNER_UNDEFINED, false);
335 if (r)
336 goto error_free;
337
338 r = amdgpu_job_submit(job, ring, &vm->entity,
339 AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
340 if (r)
341 goto error_free;
342
343 amdgpu_bo_fence(bo, fence, true);
344 dma_fence_put(fence);
345
346 if (bo->shadow)
347 return amdgpu_vm_clear_bo(adev, vm, bo->shadow,
348 level, pte_support_ats);
349
350 return 0;
351
352error_free:
353 amdgpu_job_free(job);
354
355error:
356 return r;
357}
358
359/**
360 * amdgpu_vm_alloc_levels - allocate the PD/PT levels
361 *
362 * @adev: amdgpu_device pointer
363 * @vm: requested vm
364 * @saddr: start of the address range
365 * @eaddr: end of the address range
366 *
367 * Make sure the page directories and page tables are allocated
368 */
369static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
370 struct amdgpu_vm *vm,
371 struct amdgpu_vm_pt *parent,
372 uint64_t saddr, uint64_t eaddr,
373 unsigned level, bool ats)
374{
375 unsigned shift = amdgpu_vm_level_shift(adev, level);
376 unsigned pt_idx, from, to;
377 u64 flags;
378 int r;
379
380 if (!parent->entries) {
381 unsigned num_entries = amdgpu_vm_num_entries(adev, level);
382
383 parent->entries = kvmalloc_array(num_entries,
384 sizeof(struct amdgpu_vm_pt),
385 GFP_KERNEL | __GFP_ZERO);
386 if (!parent->entries)
387 return -ENOMEM;
388 memset(parent->entries, 0 , sizeof(struct amdgpu_vm_pt));
389 }
390
391 from = saddr >> shift;
392 to = eaddr >> shift;
393 if (from >= amdgpu_vm_num_entries(adev, level) ||
394 to >= amdgpu_vm_num_entries(adev, level))
395 return -EINVAL;
396
397 ++level;
398 saddr = saddr & ((1 << shift) - 1);
399 eaddr = eaddr & ((1 << shift) - 1);
400
401 flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
402 if (vm->use_cpu_for_update)
403 flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
404 else
405 flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
406 AMDGPU_GEM_CREATE_SHADOW);
407
408 /* walk over the address space and allocate the page tables */
409 for (pt_idx = from; pt_idx <= to; ++pt_idx) {
410 struct reservation_object *resv = vm->root.base.bo->tbo.resv;
411 struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
412 struct amdgpu_bo *pt;
413
414 if (!entry->base.bo) {
415 r = amdgpu_bo_create(adev,
416 amdgpu_vm_bo_size(adev, level),
417 AMDGPU_GPU_PAGE_SIZE,
418 AMDGPU_GEM_DOMAIN_VRAM, flags,
419 ttm_bo_type_kernel, resv, &pt);
420 if (r)
421 return r;
422
423 r = amdgpu_vm_clear_bo(adev, vm, pt, level, ats);
424 if (r) {
425 amdgpu_bo_unref(&pt->shadow);
426 amdgpu_bo_unref(&pt);
427 return r;
428 }
429
430 if (vm->use_cpu_for_update) {
431 r = amdgpu_bo_kmap(pt, NULL);
432 if (r) {
433 amdgpu_bo_unref(&pt->shadow);
434 amdgpu_bo_unref(&pt);
435 return r;
436 }
437 }
438
439 /* Keep a reference to the root directory to avoid
440 * freeing them up in the wrong order.
441 */
442 pt->parent = amdgpu_bo_ref(parent->base.bo);
443
444 entry->base.vm = vm;
445 entry->base.bo = pt;
446 list_add_tail(&entry->base.bo_list, &pt->va);
447 spin_lock(&vm->status_lock);
448 list_add(&entry->base.vm_status, &vm->relocated);
449 spin_unlock(&vm->status_lock);
450 }
451
452 if (level < AMDGPU_VM_PTB) {
453 uint64_t sub_saddr = (pt_idx == from) ? saddr : 0;
454 uint64_t sub_eaddr = (pt_idx == to) ? eaddr :
455 ((1 << shift) - 1);
456 r = amdgpu_vm_alloc_levels(adev, vm, entry, sub_saddr,
457 sub_eaddr, level, ats);
458 if (r)
459 return r;
460 }
461 }
462
463 return 0;
464}
465
466/**
467 * amdgpu_vm_alloc_pts - Allocate page tables.
468 *
469 * @adev: amdgpu_device pointer
470 * @vm: VM to allocate page tables for
471 * @saddr: Start address which needs to be allocated
472 * @size: Size from start address we need.
473 *
474 * Make sure the page tables are allocated.
475 */
476int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
477 struct amdgpu_vm *vm,
478 uint64_t saddr, uint64_t size)
479{
480 uint64_t eaddr;
481 bool ats = false;
482
483 /* validate the parameters */
484 if (saddr & AMDGPU_GPU_PAGE_MASK || size & AMDGPU_GPU_PAGE_MASK)
485 return -EINVAL;
486
487 eaddr = saddr + size - 1;
488
489 if (vm->pte_support_ats)
490 ats = saddr < AMDGPU_VA_HOLE_START;
491
492 saddr /= AMDGPU_GPU_PAGE_SIZE;
493 eaddr /= AMDGPU_GPU_PAGE_SIZE;
494
495 if (eaddr >= adev->vm_manager.max_pfn) {
496 dev_err(adev->dev, "va above limit (0x%08llX >= 0x%08llX)\n",
497 eaddr, adev->vm_manager.max_pfn);
498 return -EINVAL;
499 }
500
501 return amdgpu_vm_alloc_levels(adev, vm, &vm->root, saddr, eaddr,
502 adev->vm_manager.root_level, ats);
503}
504
505/**
506 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
507 *
508 * @adev: amdgpu_device pointer
509 */
510void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
511{
512 const struct amdgpu_ip_block *ip_block;
513 bool has_compute_vm_bug;
514 struct amdgpu_ring *ring;
515 int i;
516
517 has_compute_vm_bug = false;
518
519 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
520 if (ip_block) {
521 /* Compute has a VM bug for GFX version < 7.
522 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
523 if (ip_block->version->major <= 7)
524 has_compute_vm_bug = true;
525 else if (ip_block->version->major == 8)
526 if (adev->gfx.mec_fw_version < 673)
527 has_compute_vm_bug = true;
528 }
529
530 for (i = 0; i < adev->num_rings; i++) {
531 ring = adev->rings[i];
532 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
533 /* only compute rings */
534 ring->has_compute_vm_bug = has_compute_vm_bug;
535 else
536 ring->has_compute_vm_bug = false;
537 }
538}
539
540bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
541 struct amdgpu_job *job)
542{
543 struct amdgpu_device *adev = ring->adev;
544 unsigned vmhub = ring->funcs->vmhub;
545 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
546 struct amdgpu_vmid *id;
547 bool gds_switch_needed;
548 bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
549
550 if (job->vmid == 0)
551 return false;
552 id = &id_mgr->ids[job->vmid];
553 gds_switch_needed = ring->funcs->emit_gds_switch && (
554 id->gds_base != job->gds_base ||
555 id->gds_size != job->gds_size ||
556 id->gws_base != job->gws_base ||
557 id->gws_size != job->gws_size ||
558 id->oa_base != job->oa_base ||
559 id->oa_size != job->oa_size);
560
561 if (amdgpu_vmid_had_gpu_reset(adev, id))
562 return true;
563
564 return vm_flush_needed || gds_switch_needed;
565}
566
567static bool amdgpu_vm_is_large_bar(struct amdgpu_device *adev)
568{
569 return (adev->gmc.real_vram_size == adev->gmc.visible_vram_size);
570}
571
572/**
573 * amdgpu_vm_flush - hardware flush the vm
574 *
575 * @ring: ring to use for flush
576 * @vmid: vmid number to use
577 * @pd_addr: address of the page directory
578 *
579 * Emit a VM flush when it is necessary.
580 */
581int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_pipe_sync)
582{
583 struct amdgpu_device *adev = ring->adev;
584 unsigned vmhub = ring->funcs->vmhub;
585 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
586 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
587 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
588 id->gds_base != job->gds_base ||
589 id->gds_size != job->gds_size ||
590 id->gws_base != job->gws_base ||
591 id->gws_size != job->gws_size ||
592 id->oa_base != job->oa_base ||
593 id->oa_size != job->oa_size);
594 bool vm_flush_needed = job->vm_needs_flush;
595 bool pasid_mapping_needed = id->pasid != job->pasid ||
596 !id->pasid_mapping ||
597 !dma_fence_is_signaled(id->pasid_mapping);
598 struct dma_fence *fence = NULL;
599 unsigned patch_offset = 0;
600 int r;
601
602 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
603 gds_switch_needed = true;
604 vm_flush_needed = true;
605 pasid_mapping_needed = true;
606 }
607
608 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
609 vm_flush_needed &= !!ring->funcs->emit_vm_flush;
610 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
611 ring->funcs->emit_wreg;
612
613 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
614 return 0;
615
616 if (ring->funcs->init_cond_exec)
617 patch_offset = amdgpu_ring_init_cond_exec(ring);
618
619 if (need_pipe_sync)
620 amdgpu_ring_emit_pipeline_sync(ring);
621
622 if (vm_flush_needed) {
623 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
624 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
625 }
626
627 if (pasid_mapping_needed)
628 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
629
630 if (vm_flush_needed || pasid_mapping_needed) {
631 r = amdgpu_fence_emit(ring, &fence);
632 if (r)
633 return r;
634 }
635
636 if (vm_flush_needed) {
637 mutex_lock(&id_mgr->lock);
638 dma_fence_put(id->last_flush);
639 id->last_flush = dma_fence_get(fence);
640 id->current_gpu_reset_count =
641 atomic_read(&adev->gpu_reset_counter);
642 mutex_unlock(&id_mgr->lock);
643 }
644
645 if (pasid_mapping_needed) {
646 id->pasid = job->pasid;
647 dma_fence_put(id->pasid_mapping);
648 id->pasid_mapping = dma_fence_get(fence);
649 }
650 dma_fence_put(fence);
651
652 if (ring->funcs->emit_gds_switch && gds_switch_needed) {
653 id->gds_base = job->gds_base;
654 id->gds_size = job->gds_size;
655 id->gws_base = job->gws_base;
656 id->gws_size = job->gws_size;
657 id->oa_base = job->oa_base;
658 id->oa_size = job->oa_size;
659 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
660 job->gds_size, job->gws_base,
661 job->gws_size, job->oa_base,
662 job->oa_size);
663 }
664
665 if (ring->funcs->patch_cond_exec)
666 amdgpu_ring_patch_cond_exec(ring, patch_offset);
667
668 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
669 if (ring->funcs->emit_switch_buffer) {
670 amdgpu_ring_emit_switch_buffer(ring);
671 amdgpu_ring_emit_switch_buffer(ring);
672 }
673 return 0;
674}
675
676/**
677 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
678 *
679 * @vm: requested vm
680 * @bo: requested buffer object
681 *
682 * Find @bo inside the requested vm.
683 * Search inside the @bos vm list for the requested vm
684 * Returns the found bo_va or NULL if none is found
685 *
686 * Object has to be reserved!
687 */
688struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
689 struct amdgpu_bo *bo)
690{
691 struct amdgpu_bo_va *bo_va;
692
693 list_for_each_entry(bo_va, &bo->va, base.bo_list) {
694 if (bo_va->base.vm == vm) {
695 return bo_va;
696 }
697 }
698 return NULL;
699}
700
701/**
702 * amdgpu_vm_do_set_ptes - helper to call the right asic function
703 *
704 * @params: see amdgpu_pte_update_params definition
705 * @bo: PD/PT to update
706 * @pe: addr of the page entry
707 * @addr: dst addr to write into pe
708 * @count: number of page entries to update
709 * @incr: increase next addr by incr bytes
710 * @flags: hw access flags
711 *
712 * Traces the parameters and calls the right asic functions
713 * to setup the page table using the DMA.
714 */
715static void amdgpu_vm_do_set_ptes(struct amdgpu_pte_update_params *params,
716 struct amdgpu_bo *bo,
717 uint64_t pe, uint64_t addr,
718 unsigned count, uint32_t incr,
719 uint64_t flags)
720{
721 pe += amdgpu_bo_gpu_offset(bo);
722 trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
723
724 if (count < 3) {
725 amdgpu_vm_write_pte(params->adev, params->ib, pe,
726 addr | flags, count, incr);
727
728 } else {
729 amdgpu_vm_set_pte_pde(params->adev, params->ib, pe, addr,
730 count, incr, flags);
731 }
732}
733
734/**
735 * amdgpu_vm_do_copy_ptes - copy the PTEs from the GART
736 *
737 * @params: see amdgpu_pte_update_params definition
738 * @bo: PD/PT to update
739 * @pe: addr of the page entry
740 * @addr: dst addr to write into pe
741 * @count: number of page entries to update
742 * @incr: increase next addr by incr bytes
743 * @flags: hw access flags
744 *
745 * Traces the parameters and calls the DMA function to copy the PTEs.
746 */
747static void amdgpu_vm_do_copy_ptes(struct amdgpu_pte_update_params *params,
748 struct amdgpu_bo *bo,
749 uint64_t pe, uint64_t addr,
750 unsigned count, uint32_t incr,
751 uint64_t flags)
752{
753 uint64_t src = (params->src + (addr >> 12) * 8);
754
755 pe += amdgpu_bo_gpu_offset(bo);
756 trace_amdgpu_vm_copy_ptes(pe, src, count);
757
758 amdgpu_vm_copy_pte(params->adev, params->ib, pe, src, count);
759}
760
761/**
762 * amdgpu_vm_map_gart - Resolve gart mapping of addr
763 *
764 * @pages_addr: optional DMA address to use for lookup
765 * @addr: the unmapped addr
766 *
767 * Look up the physical address of the page that the pte resolves
768 * to and return the pointer for the page table entry.
769 */
770static uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
771{
772 uint64_t result;
773
774 /* page table offset */
775 result = pages_addr[addr >> PAGE_SHIFT];
776
777 /* in case cpu page size != gpu page size*/
778 result |= addr & (~PAGE_MASK);
779
780 result &= 0xFFFFFFFFFFFFF000ULL;
781
782 return result;
783}
784
785/**
786 * amdgpu_vm_cpu_set_ptes - helper to update page tables via CPU
787 *
788 * @params: see amdgpu_pte_update_params definition
789 * @bo: PD/PT to update
790 * @pe: kmap addr of the page entry
791 * @addr: dst addr to write into pe
792 * @count: number of page entries to update
793 * @incr: increase next addr by incr bytes
794 * @flags: hw access flags
795 *
796 * Write count number of PT/PD entries directly.
797 */
798static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params,
799 struct amdgpu_bo *bo,
800 uint64_t pe, uint64_t addr,
801 unsigned count, uint32_t incr,
802 uint64_t flags)
803{
804 unsigned int i;
805 uint64_t value;
806
807 pe += (unsigned long)amdgpu_bo_kptr(bo);
808
809 trace_amdgpu_vm_set_ptes(pe, addr, count, incr, flags);
810
811 for (i = 0; i < count; i++) {
812 value = params->pages_addr ?
813 amdgpu_vm_map_gart(params->pages_addr, addr) :
814 addr;
815 amdgpu_gmc_set_pte_pde(params->adev, (void *)(uintptr_t)pe,
816 i, value, flags);
817 addr += incr;
818 }
819}
820
821static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm,
822 void *owner)
823{
824 struct amdgpu_sync sync;
825 int r;
826
827 amdgpu_sync_create(&sync);
828 amdgpu_sync_resv(adev, &sync, vm->root.base.bo->tbo.resv, owner, false);
829 r = amdgpu_sync_wait(&sync, true);
830 amdgpu_sync_free(&sync);
831
832 return r;
833}
834
835/*
836 * amdgpu_vm_update_pde - update a single level in the hierarchy
837 *
838 * @param: parameters for the update
839 * @vm: requested vm
840 * @parent: parent directory
841 * @entry: entry to update
842 *
843 * Makes sure the requested entry in parent is up to date.
844 */
845static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params,
846 struct amdgpu_vm *vm,
847 struct amdgpu_vm_pt *parent,
848 struct amdgpu_vm_pt *entry)
849{
850 struct amdgpu_bo *bo = parent->base.bo, *pbo;
851 uint64_t pde, pt, flags;
852 unsigned level;
853
854 /* Don't update huge pages here */
855 if (entry->huge)
856 return;
857
858 for (level = 0, pbo = bo->parent; pbo; ++level)
859 pbo = pbo->parent;
860
861 level += params->adev->vm_manager.root_level;
862 pt = amdgpu_bo_gpu_offset(entry->base.bo);
863 flags = AMDGPU_PTE_VALID;
864 amdgpu_gmc_get_vm_pde(params->adev, level, &pt, &flags);
865 pde = (entry - parent->entries) * 8;
866 if (bo->shadow)
867 params->func(params, bo->shadow, pde, pt, 1, 0, flags);
868 params->func(params, bo, pde, pt, 1, 0, flags);
869}
870
871/*
872 * amdgpu_vm_invalidate_level - mark all PD levels as invalid
873 *
874 * @parent: parent PD
875 *
876 * Mark all PD level as invalid after an error.
877 */
878static void amdgpu_vm_invalidate_level(struct amdgpu_device *adev,
879 struct amdgpu_vm *vm,
880 struct amdgpu_vm_pt *parent,
881 unsigned level)
882{
883 unsigned pt_idx, num_entries;
884
885 /*
886 * Recurse into the subdirectories. This recursion is harmless because
887 * we only have a maximum of 5 layers.
888 */
889 num_entries = amdgpu_vm_num_entries(adev, level);
890 for (pt_idx = 0; pt_idx < num_entries; ++pt_idx) {
891 struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
892
893 if (!entry->base.bo)
894 continue;
895
896 spin_lock(&vm->status_lock);
897 if (list_empty(&entry->base.vm_status))
898 list_add(&entry->base.vm_status, &vm->relocated);
899 spin_unlock(&vm->status_lock);
900 amdgpu_vm_invalidate_level(adev, vm, entry, level + 1);
901 }
902}
903
904/*
905 * amdgpu_vm_update_directories - make sure that all directories are valid
906 *
907 * @adev: amdgpu_device pointer
908 * @vm: requested vm
909 *
910 * Makes sure all directories are up to date.
911 * Returns 0 for success, error for failure.
912 */
913int amdgpu_vm_update_directories(struct amdgpu_device *adev,
914 struct amdgpu_vm *vm)
915{
916 struct amdgpu_pte_update_params params;
917 struct amdgpu_job *job;
918 unsigned ndw = 0;
919 int r = 0;
920
921 if (list_empty(&vm->relocated))
922 return 0;
923
924restart:
925 memset(¶ms, 0, sizeof(params));
926 params.adev = adev;
927
928 if (vm->use_cpu_for_update) {
929 r = amdgpu_vm_wait_pd(adev, vm, AMDGPU_FENCE_OWNER_VM);
930 if (unlikely(r))
931 return r;
932
933 params.func = amdgpu_vm_cpu_set_ptes;
934 } else {
935 ndw = 512 * 8;
936 r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
937 if (r)
938 return r;
939
940 params.ib = &job->ibs[0];
941 params.func = amdgpu_vm_do_set_ptes;
942 }
943
944 spin_lock(&vm->status_lock);
945 while (!list_empty(&vm->relocated)) {
946 struct amdgpu_vm_bo_base *bo_base, *parent;
947 struct amdgpu_vm_pt *pt, *entry;
948 struct amdgpu_bo *bo;
949
950 bo_base = list_first_entry(&vm->relocated,
951 struct amdgpu_vm_bo_base,
952 vm_status);
953 list_del_init(&bo_base->vm_status);
954 spin_unlock(&vm->status_lock);
955
956 bo = bo_base->bo->parent;
957 if (!bo) {
958 spin_lock(&vm->status_lock);
959 continue;
960 }
961
962 parent = list_first_entry(&bo->va, struct amdgpu_vm_bo_base,
963 bo_list);
964 pt = container_of(parent, struct amdgpu_vm_pt, base);
965 entry = container_of(bo_base, struct amdgpu_vm_pt, base);
966
967 amdgpu_vm_update_pde(¶ms, vm, pt, entry);
968
969 spin_lock(&vm->status_lock);
970 if (!vm->use_cpu_for_update &&
971 (ndw - params.ib->length_dw) < 32)
972 break;
973 }
974 spin_unlock(&vm->status_lock);
975
976 if (vm->use_cpu_for_update) {
977 /* Flush HDP */
978 mb();
979 amdgpu_asic_flush_hdp(adev, NULL);
980 } else if (params.ib->length_dw == 0) {
981 amdgpu_job_free(job);
982 } else {
983 struct amdgpu_bo *root = vm->root.base.bo;
984 struct amdgpu_ring *ring;
985 struct dma_fence *fence;
986
987 ring = container_of(vm->entity.sched, struct amdgpu_ring,
988 sched);
989
990 amdgpu_ring_pad_ib(ring, params.ib);
991 amdgpu_sync_resv(adev, &job->sync, root->tbo.resv,
992 AMDGPU_FENCE_OWNER_VM, false);
993 WARN_ON(params.ib->length_dw > ndw);
994 r = amdgpu_job_submit(job, ring, &vm->entity,
995 AMDGPU_FENCE_OWNER_VM, &fence);
996 if (r)
997 goto error;
998
999 amdgpu_bo_fence(root, fence, true);
1000 dma_fence_put(vm->last_update);
1001 vm->last_update = fence;
1002 }
1003
1004 if (!list_empty(&vm->relocated))
1005 goto restart;
1006
1007 return 0;
1008
1009error:
1010 amdgpu_vm_invalidate_level(adev, vm, &vm->root,
1011 adev->vm_manager.root_level);
1012 amdgpu_job_free(job);
1013 return r;
1014}
1015
1016/**
1017 * amdgpu_vm_find_entry - find the entry for an address
1018 *
1019 * @p: see amdgpu_pte_update_params definition
1020 * @addr: virtual address in question
1021 * @entry: resulting entry or NULL
1022 * @parent: parent entry
1023 *
1024 * Find the vm_pt entry and it's parent for the given address.
1025 */
1026void amdgpu_vm_get_entry(struct amdgpu_pte_update_params *p, uint64_t addr,
1027 struct amdgpu_vm_pt **entry,
1028 struct amdgpu_vm_pt **parent)
1029{
1030 unsigned level = p->adev->vm_manager.root_level;
1031
1032 *parent = NULL;
1033 *entry = &p->vm->root;
1034 while ((*entry)->entries) {
1035 unsigned shift = amdgpu_vm_level_shift(p->adev, level++);
1036
1037 *parent = *entry;
1038 *entry = &(*entry)->entries[addr >> shift];
1039 addr &= (1ULL << shift) - 1;
1040 }
1041
1042 if (level != AMDGPU_VM_PTB)
1043 *entry = NULL;
1044}
1045
1046/**
1047 * amdgpu_vm_handle_huge_pages - handle updating the PD with huge pages
1048 *
1049 * @p: see amdgpu_pte_update_params definition
1050 * @entry: vm_pt entry to check
1051 * @parent: parent entry
1052 * @nptes: number of PTEs updated with this operation
1053 * @dst: destination address where the PTEs should point to
1054 * @flags: access flags fro the PTEs
1055 *
1056 * Check if we can update the PD with a huge page.
1057 */
1058static void amdgpu_vm_handle_huge_pages(struct amdgpu_pte_update_params *p,
1059 struct amdgpu_vm_pt *entry,
1060 struct amdgpu_vm_pt *parent,
1061 unsigned nptes, uint64_t dst,
1062 uint64_t flags)
1063{
1064 uint64_t pde;
1065
1066 /* In the case of a mixed PT the PDE must point to it*/
1067 if (p->adev->asic_type >= CHIP_VEGA10 && !p->src &&
1068 nptes == AMDGPU_VM_PTE_COUNT(p->adev)) {
1069 /* Set the huge page flag to stop scanning at this PDE */
1070 flags |= AMDGPU_PDE_PTE;
1071 }
1072
1073 if (!(flags & AMDGPU_PDE_PTE)) {
1074 if (entry->huge) {
1075 /* Add the entry to the relocated list to update it. */
1076 entry->huge = false;
1077 spin_lock(&p->vm->status_lock);
1078 list_move(&entry->base.vm_status, &p->vm->relocated);
1079 spin_unlock(&p->vm->status_lock);
1080 }
1081 return;
1082 }
1083
1084 entry->huge = true;
1085 amdgpu_gmc_get_vm_pde(p->adev, AMDGPU_VM_PDB0, &dst, &flags);
1086
1087 pde = (entry - parent->entries) * 8;
1088 if (parent->base.bo->shadow)
1089 p->func(p, parent->base.bo->shadow, pde, dst, 1, 0, flags);
1090 p->func(p, parent->base.bo, pde, dst, 1, 0, flags);
1091}
1092
1093/**
1094 * amdgpu_vm_update_ptes - make sure that page tables are valid
1095 *
1096 * @params: see amdgpu_pte_update_params definition
1097 * @vm: requested vm
1098 * @start: start of GPU address range
1099 * @end: end of GPU address range
1100 * @dst: destination address to map to, the next dst inside the function
1101 * @flags: mapping flags
1102 *
1103 * Update the page tables in the range @start - @end.
1104 * Returns 0 for success, -EINVAL for failure.
1105 */
1106static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params,
1107 uint64_t start, uint64_t end,
1108 uint64_t dst, uint64_t flags)
1109{
1110 struct amdgpu_device *adev = params->adev;
1111 const uint64_t mask = AMDGPU_VM_PTE_COUNT(adev) - 1;
1112
1113 uint64_t addr, pe_start;
1114 struct amdgpu_bo *pt;
1115 unsigned nptes;
1116
1117 /* walk over the address space and update the page tables */
1118 for (addr = start; addr < end; addr += nptes,
1119 dst += nptes * AMDGPU_GPU_PAGE_SIZE) {
1120 struct amdgpu_vm_pt *entry, *parent;
1121
1122 amdgpu_vm_get_entry(params, addr, &entry, &parent);
1123 if (!entry)
1124 return -ENOENT;
1125
1126 if ((addr & ~mask) == (end & ~mask))
1127 nptes = end - addr;
1128 else
1129 nptes = AMDGPU_VM_PTE_COUNT(adev) - (addr & mask);
1130
1131 amdgpu_vm_handle_huge_pages(params, entry, parent,
1132 nptes, dst, flags);
1133 /* We don't need to update PTEs for huge pages */
1134 if (entry->huge)
1135 continue;
1136
1137 pt = entry->base.bo;
1138 pe_start = (addr & mask) * 8;
1139 if (pt->shadow)
1140 params->func(params, pt->shadow, pe_start, dst, nptes,
1141 AMDGPU_GPU_PAGE_SIZE, flags);
1142 params->func(params, pt, pe_start, dst, nptes,
1143 AMDGPU_GPU_PAGE_SIZE, flags);
1144 }
1145
1146 return 0;
1147}
1148
1149/*
1150 * amdgpu_vm_frag_ptes - add fragment information to PTEs
1151 *
1152 * @params: see amdgpu_pte_update_params definition
1153 * @vm: requested vm
1154 * @start: first PTE to handle
1155 * @end: last PTE to handle
1156 * @dst: addr those PTEs should point to
1157 * @flags: hw mapping flags
1158 * Returns 0 for success, -EINVAL for failure.
1159 */
1160static int amdgpu_vm_frag_ptes(struct amdgpu_pte_update_params *params,
1161 uint64_t start, uint64_t end,
1162 uint64_t dst, uint64_t flags)
1163{
1164 /**
1165 * The MC L1 TLB supports variable sized pages, based on a fragment
1166 * field in the PTE. When this field is set to a non-zero value, page
1167 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
1168 * flags are considered valid for all PTEs within the fragment range
1169 * and corresponding mappings are assumed to be physically contiguous.
1170 *
1171 * The L1 TLB can store a single PTE for the whole fragment,
1172 * significantly increasing the space available for translation
1173 * caching. This leads to large improvements in throughput when the
1174 * TLB is under pressure.
1175 *
1176 * The L2 TLB distributes small and large fragments into two
1177 * asymmetric partitions. The large fragment cache is significantly
1178 * larger. Thus, we try to use large fragments wherever possible.
1179 * Userspace can support this by aligning virtual base address and
1180 * allocation size to the fragment size.
1181 */
1182 unsigned max_frag = params->adev->vm_manager.fragment_size;
1183 int r;
1184
1185 /* system pages are non continuously */
1186 if (params->src || !(flags & AMDGPU_PTE_VALID))
1187 return amdgpu_vm_update_ptes(params, start, end, dst, flags);
1188
1189 while (start != end) {
1190 uint64_t frag_flags, frag_end;
1191 unsigned frag;
1192
1193 /* This intentionally wraps around if no bit is set */
1194 frag = min((unsigned)ffs(start) - 1,
1195 (unsigned)fls64(end - start) - 1);
1196 if (frag >= max_frag) {
1197 frag_flags = AMDGPU_PTE_FRAG(max_frag);
1198 frag_end = end & ~((1ULL << max_frag) - 1);
1199 } else {
1200 frag_flags = AMDGPU_PTE_FRAG(frag);
1201 frag_end = start + (1 << frag);
1202 }
1203
1204 r = amdgpu_vm_update_ptes(params, start, frag_end, dst,
1205 flags | frag_flags);
1206 if (r)
1207 return r;
1208
1209 dst += (frag_end - start) * AMDGPU_GPU_PAGE_SIZE;
1210 start = frag_end;
1211 }
1212
1213 return 0;
1214}
1215
1216/**
1217 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
1218 *
1219 * @adev: amdgpu_device pointer
1220 * @exclusive: fence we need to sync to
1221 * @pages_addr: DMA addresses to use for mapping
1222 * @vm: requested vm
1223 * @start: start of mapped range
1224 * @last: last mapped entry
1225 * @flags: flags for the entries
1226 * @addr: addr to set the area to
1227 * @fence: optional resulting fence
1228 *
1229 * Fill in the page table entries between @start and @last.
1230 * Returns 0 for success, -EINVAL for failure.
1231 */
1232static int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1233 struct dma_fence *exclusive,
1234 dma_addr_t *pages_addr,
1235 struct amdgpu_vm *vm,
1236 uint64_t start, uint64_t last,
1237 uint64_t flags, uint64_t addr,
1238 struct dma_fence **fence)
1239{
1240 struct amdgpu_ring *ring;
1241 void *owner = AMDGPU_FENCE_OWNER_VM;
1242 unsigned nptes, ncmds, ndw;
1243 struct amdgpu_job *job;
1244 struct amdgpu_pte_update_params params;
1245 struct dma_fence *f = NULL;
1246 int r;
1247
1248 memset(¶ms, 0, sizeof(params));
1249 params.adev = adev;
1250 params.vm = vm;
1251
1252 /* sync to everything on unmapping */
1253 if (!(flags & AMDGPU_PTE_VALID))
1254 owner = AMDGPU_FENCE_OWNER_UNDEFINED;
1255
1256 if (vm->use_cpu_for_update) {
1257 /* params.src is used as flag to indicate system Memory */
1258 if (pages_addr)
1259 params.src = ~0;
1260
1261 /* Wait for PT BOs to be free. PTs share the same resv. object
1262 * as the root PD BO
1263 */
1264 r = amdgpu_vm_wait_pd(adev, vm, owner);
1265 if (unlikely(r))
1266 return r;
1267
1268 params.func = amdgpu_vm_cpu_set_ptes;
1269 params.pages_addr = pages_addr;
1270 return amdgpu_vm_frag_ptes(¶ms, start, last + 1,
1271 addr, flags);
1272 }
1273
1274 ring = container_of(vm->entity.sched, struct amdgpu_ring, sched);
1275
1276 nptes = last - start + 1;
1277
1278 /*
1279 * reserve space for two commands every (1 << BLOCK_SIZE)
1280 * entries or 2k dwords (whatever is smaller)
1281 *
1282 * The second command is for the shadow pagetables.
1283 */
1284 if (vm->root.base.bo->shadow)
1285 ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1) * 2;
1286 else
1287 ncmds = ((nptes >> min(adev->vm_manager.block_size, 11u)) + 1);
1288
1289 /* padding, etc. */
1290 ndw = 64;
1291
1292 if (pages_addr) {
1293 /* copy commands needed */
1294 ndw += ncmds * adev->vm_manager.vm_pte_funcs->copy_pte_num_dw;
1295
1296 /* and also PTEs */
1297 ndw += nptes * 2;
1298
1299 params.func = amdgpu_vm_do_copy_ptes;
1300
1301 } else {
1302 /* set page commands needed */
1303 ndw += ncmds * 10;
1304
1305 /* extra commands for begin/end fragments */
1306 ndw += 2 * 10 * adev->vm_manager.fragment_size;
1307
1308 params.func = amdgpu_vm_do_set_ptes;
1309 }
1310
1311 r = amdgpu_job_alloc_with_ib(adev, ndw * 4, &job);
1312 if (r)
1313 return r;
1314
1315 params.ib = &job->ibs[0];
1316
1317 if (pages_addr) {
1318 uint64_t *pte;
1319 unsigned i;
1320
1321 /* Put the PTEs at the end of the IB. */
1322 i = ndw - nptes * 2;
1323 pte= (uint64_t *)&(job->ibs->ptr[i]);
1324 params.src = job->ibs->gpu_addr + i * 4;
1325
1326 for (i = 0; i < nptes; ++i) {
1327 pte[i] = amdgpu_vm_map_gart(pages_addr, addr + i *
1328 AMDGPU_GPU_PAGE_SIZE);
1329 pte[i] |= flags;
1330 }
1331 addr = 0;
1332 }
1333
1334 r = amdgpu_sync_fence(adev, &job->sync, exclusive, false);
1335 if (r)
1336 goto error_free;
1337
1338 r = amdgpu_sync_resv(adev, &job->sync, vm->root.base.bo->tbo.resv,
1339 owner, false);
1340 if (r)
1341 goto error_free;
1342
1343 r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv);
1344 if (r)
1345 goto error_free;
1346
1347 r = amdgpu_vm_frag_ptes(¶ms, start, last + 1, addr, flags);
1348 if (r)
1349 goto error_free;
1350
1351 amdgpu_ring_pad_ib(ring, params.ib);
1352 WARN_ON(params.ib->length_dw > ndw);
1353 r = amdgpu_job_submit(job, ring, &vm->entity,
1354 AMDGPU_FENCE_OWNER_VM, &f);
1355 if (r)
1356 goto error_free;
1357
1358 amdgpu_bo_fence(vm->root.base.bo, f, true);
1359 dma_fence_put(*fence);
1360 *fence = f;
1361 return 0;
1362
1363error_free:
1364 amdgpu_job_free(job);
1365 return r;
1366}
1367
1368/**
1369 * amdgpu_vm_bo_split_mapping - split a mapping into smaller chunks
1370 *
1371 * @adev: amdgpu_device pointer
1372 * @exclusive: fence we need to sync to
1373 * @pages_addr: DMA addresses to use for mapping
1374 * @vm: requested vm
1375 * @mapping: mapped range and flags to use for the update
1376 * @flags: HW flags for the mapping
1377 * @nodes: array of drm_mm_nodes with the MC addresses
1378 * @fence: optional resulting fence
1379 *
1380 * Split the mapping into smaller chunks so that each update fits
1381 * into a SDMA IB.
1382 * Returns 0 for success, -EINVAL for failure.
1383 */
1384static int amdgpu_vm_bo_split_mapping(struct amdgpu_device *adev,
1385 struct dma_fence *exclusive,
1386 dma_addr_t *pages_addr,
1387 struct amdgpu_vm *vm,
1388 struct amdgpu_bo_va_mapping *mapping,
1389 uint64_t flags,
1390 struct drm_mm_node *nodes,
1391 struct dma_fence **fence)
1392{
1393 unsigned min_linear_pages = 1 << adev->vm_manager.fragment_size;
1394 uint64_t pfn, start = mapping->start;
1395 int r;
1396
1397 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1398 * but in case of something, we filter the flags in first place
1399 */
1400 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1401 flags &= ~AMDGPU_PTE_READABLE;
1402 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1403 flags &= ~AMDGPU_PTE_WRITEABLE;
1404
1405 flags &= ~AMDGPU_PTE_EXECUTABLE;
1406 flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE;
1407
1408 flags &= ~AMDGPU_PTE_MTYPE_MASK;
1409 flags |= (mapping->flags & AMDGPU_PTE_MTYPE_MASK);
1410
1411 if ((mapping->flags & AMDGPU_PTE_PRT) &&
1412 (adev->asic_type >= CHIP_VEGA10)) {
1413 flags |= AMDGPU_PTE_PRT;
1414 flags &= ~AMDGPU_PTE_VALID;
1415 }
1416
1417 trace_amdgpu_vm_bo_update(mapping);
1418
1419 pfn = mapping->offset >> PAGE_SHIFT;
1420 if (nodes) {
1421 while (pfn >= nodes->size) {
1422 pfn -= nodes->size;
1423 ++nodes;
1424 }
1425 }
1426
1427 do {
1428 dma_addr_t *dma_addr = NULL;
1429 uint64_t max_entries;
1430 uint64_t addr, last;
1431
1432 if (nodes) {
1433 addr = nodes->start << PAGE_SHIFT;
1434 max_entries = (nodes->size - pfn) *
1435 (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE);
1436 } else {
1437 addr = 0;
1438 max_entries = S64_MAX;
1439 }
1440
1441 if (pages_addr) {
1442 uint64_t count;
1443
1444 max_entries = min(max_entries, 16ull * 1024ull);
1445 for (count = 1; count < max_entries; ++count) {
1446 uint64_t idx = pfn + count;
1447
1448 if (pages_addr[idx] !=
1449 (pages_addr[idx - 1] + PAGE_SIZE))
1450 break;
1451 }
1452
1453 if (count < min_linear_pages) {
1454 addr = pfn << PAGE_SHIFT;
1455 dma_addr = pages_addr;
1456 } else {
1457 addr = pages_addr[pfn];
1458 max_entries = count;
1459 }
1460
1461 } else if (flags & AMDGPU_PTE_VALID) {
1462 addr += adev->vm_manager.vram_base_offset;
1463 addr += pfn << PAGE_SHIFT;
1464 }
1465
1466 last = min((uint64_t)mapping->last, start + max_entries - 1);
1467 r = amdgpu_vm_bo_update_mapping(adev, exclusive, dma_addr, vm,
1468 start, last, flags, addr,
1469 fence);
1470 if (r)
1471 return r;
1472
1473 pfn += last - start + 1;
1474 if (nodes && nodes->size == pfn) {
1475 pfn = 0;
1476 ++nodes;
1477 }
1478 start = last + 1;
1479
1480 } while (unlikely(start != mapping->last + 1));
1481
1482 return 0;
1483}
1484
1485/**
1486 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1487 *
1488 * @adev: amdgpu_device pointer
1489 * @bo_va: requested BO and VM object
1490 * @clear: if true clear the entries
1491 *
1492 * Fill in the page table entries for @bo_va.
1493 * Returns 0 for success, -EINVAL for failure.
1494 */
1495int amdgpu_vm_bo_update(struct amdgpu_device *adev,
1496 struct amdgpu_bo_va *bo_va,
1497 bool clear)
1498{
1499 struct amdgpu_bo *bo = bo_va->base.bo;
1500 struct amdgpu_vm *vm = bo_va->base.vm;
1501 struct amdgpu_bo_va_mapping *mapping;
1502 dma_addr_t *pages_addr = NULL;
1503 struct ttm_mem_reg *mem;
1504 struct drm_mm_node *nodes;
1505 struct dma_fence *exclusive, **last_update;
1506 uint64_t flags;
1507 int r;
1508
1509 if (clear || !bo_va->base.bo) {
1510 mem = NULL;
1511 nodes = NULL;
1512 exclusive = NULL;
1513 } else {
1514 struct ttm_dma_tt *ttm;
1515
1516 mem = &bo_va->base.bo->tbo.mem;
1517 nodes = mem->mm_node;
1518 if (mem->mem_type == TTM_PL_TT) {
1519 ttm = container_of(bo_va->base.bo->tbo.ttm,
1520 struct ttm_dma_tt, ttm);
1521 pages_addr = ttm->dma_address;
1522 }
1523 exclusive = reservation_object_get_excl(bo->tbo.resv);
1524 }
1525
1526 if (bo)
1527 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1528 else
1529 flags = 0x0;
1530
1531 if (clear || (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv))
1532 last_update = &vm->last_update;
1533 else
1534 last_update = &bo_va->last_pt_update;
1535
1536 if (!clear && bo_va->base.moved) {
1537 bo_va->base.moved = false;
1538 list_splice_init(&bo_va->valids, &bo_va->invalids);
1539
1540 } else if (bo_va->cleared != clear) {
1541 list_splice_init(&bo_va->valids, &bo_va->invalids);
1542 }
1543
1544 list_for_each_entry(mapping, &bo_va->invalids, list) {
1545 r = amdgpu_vm_bo_split_mapping(adev, exclusive, pages_addr, vm,
1546 mapping, flags, nodes,
1547 last_update);
1548 if (r)
1549 return r;
1550 }
1551
1552 if (vm->use_cpu_for_update) {
1553 /* Flush HDP */
1554 mb();
1555 amdgpu_asic_flush_hdp(adev, NULL);
1556 }
1557
1558 spin_lock(&vm->status_lock);
1559 list_del_init(&bo_va->base.vm_status);
1560 spin_unlock(&vm->status_lock);
1561
1562 list_splice_init(&bo_va->invalids, &bo_va->valids);
1563 bo_va->cleared = clear;
1564
1565 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1566 list_for_each_entry(mapping, &bo_va->valids, list)
1567 trace_amdgpu_vm_bo_mapping(mapping);
1568 }
1569
1570 return 0;
1571}
1572
1573/**
1574 * amdgpu_vm_update_prt_state - update the global PRT state
1575 */
1576static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1577{
1578 unsigned long flags;
1579 bool enable;
1580
1581 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1582 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1583 adev->gmc.gmc_funcs->set_prt(adev, enable);
1584 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1585}
1586
1587/**
1588 * amdgpu_vm_prt_get - add a PRT user
1589 */
1590static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1591{
1592 if (!adev->gmc.gmc_funcs->set_prt)
1593 return;
1594
1595 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1596 amdgpu_vm_update_prt_state(adev);
1597}
1598
1599/**
1600 * amdgpu_vm_prt_put - drop a PRT user
1601 */
1602static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1603{
1604 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1605 amdgpu_vm_update_prt_state(adev);
1606}
1607
1608/**
1609 * amdgpu_vm_prt_cb - callback for updating the PRT status
1610 */
1611static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1612{
1613 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1614
1615 amdgpu_vm_prt_put(cb->adev);
1616 kfree(cb);
1617}
1618
1619/**
1620 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1621 */
1622static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1623 struct dma_fence *fence)
1624{
1625 struct amdgpu_prt_cb *cb;
1626
1627 if (!adev->gmc.gmc_funcs->set_prt)
1628 return;
1629
1630 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
1631 if (!cb) {
1632 /* Last resort when we are OOM */
1633 if (fence)
1634 dma_fence_wait(fence, false);
1635
1636 amdgpu_vm_prt_put(adev);
1637 } else {
1638 cb->adev = adev;
1639 if (!fence || dma_fence_add_callback(fence, &cb->cb,
1640 amdgpu_vm_prt_cb))
1641 amdgpu_vm_prt_cb(fence, &cb->cb);
1642 }
1643}
1644
1645/**
1646 * amdgpu_vm_free_mapping - free a mapping
1647 *
1648 * @adev: amdgpu_device pointer
1649 * @vm: requested vm
1650 * @mapping: mapping to be freed
1651 * @fence: fence of the unmap operation
1652 *
1653 * Free a mapping and make sure we decrease the PRT usage count if applicable.
1654 */
1655static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
1656 struct amdgpu_vm *vm,
1657 struct amdgpu_bo_va_mapping *mapping,
1658 struct dma_fence *fence)
1659{
1660 if (mapping->flags & AMDGPU_PTE_PRT)
1661 amdgpu_vm_add_prt_cb(adev, fence);
1662 kfree(mapping);
1663}
1664
1665/**
1666 * amdgpu_vm_prt_fini - finish all prt mappings
1667 *
1668 * @adev: amdgpu_device pointer
1669 * @vm: requested vm
1670 *
1671 * Register a cleanup callback to disable PRT support after VM dies.
1672 */
1673static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
1674{
1675 struct reservation_object *resv = vm->root.base.bo->tbo.resv;
1676 struct dma_fence *excl, **shared;
1677 unsigned i, shared_count;
1678 int r;
1679
1680 r = reservation_object_get_fences_rcu(resv, &excl,
1681 &shared_count, &shared);
1682 if (r) {
1683 /* Not enough memory to grab the fence list, as last resort
1684 * block for all the fences to complete.
1685 */
1686 reservation_object_wait_timeout_rcu(resv, true, false,
1687 MAX_SCHEDULE_TIMEOUT);
1688 return;
1689 }
1690
1691 /* Add a callback for each fence in the reservation object */
1692 amdgpu_vm_prt_get(adev);
1693 amdgpu_vm_add_prt_cb(adev, excl);
1694
1695 for (i = 0; i < shared_count; ++i) {
1696 amdgpu_vm_prt_get(adev);
1697 amdgpu_vm_add_prt_cb(adev, shared[i]);
1698 }
1699
1700 kfree(shared);
1701}
1702
1703/**
1704 * amdgpu_vm_clear_freed - clear freed BOs in the PT
1705 *
1706 * @adev: amdgpu_device pointer
1707 * @vm: requested vm
1708 * @fence: optional resulting fence (unchanged if no work needed to be done
1709 * or if an error occurred)
1710 *
1711 * Make sure all freed BOs are cleared in the PT.
1712 * Returns 0 for success.
1713 *
1714 * PTs have to be reserved and mutex must be locked!
1715 */
1716int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
1717 struct amdgpu_vm *vm,
1718 struct dma_fence **fence)
1719{
1720 struct amdgpu_bo_va_mapping *mapping;
1721 uint64_t init_pte_value = 0;
1722 struct dma_fence *f = NULL;
1723 int r;
1724
1725 while (!list_empty(&vm->freed)) {
1726 mapping = list_first_entry(&vm->freed,
1727 struct amdgpu_bo_va_mapping, list);
1728 list_del(&mapping->list);
1729
1730 if (vm->pte_support_ats && mapping->start < AMDGPU_VA_HOLE_START)
1731 init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
1732
1733 r = amdgpu_vm_bo_update_mapping(adev, NULL, NULL, vm,
1734 mapping->start, mapping->last,
1735 init_pte_value, 0, &f);
1736 amdgpu_vm_free_mapping(adev, vm, mapping, f);
1737 if (r) {
1738 dma_fence_put(f);
1739 return r;
1740 }
1741 }
1742
1743 if (fence && f) {
1744 dma_fence_put(*fence);
1745 *fence = f;
1746 } else {
1747 dma_fence_put(f);
1748 }
1749
1750 return 0;
1751
1752}
1753
1754/**
1755 * amdgpu_vm_handle_moved - handle moved BOs in the PT
1756 *
1757 * @adev: amdgpu_device pointer
1758 * @vm: requested vm
1759 * @sync: sync object to add fences to
1760 *
1761 * Make sure all BOs which are moved are updated in the PTs.
1762 * Returns 0 for success.
1763 *
1764 * PTs have to be reserved!
1765 */
1766int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
1767 struct amdgpu_vm *vm)
1768{
1769 bool clear;
1770 int r = 0;
1771
1772 spin_lock(&vm->status_lock);
1773 while (!list_empty(&vm->moved)) {
1774 struct amdgpu_bo_va *bo_va;
1775 struct reservation_object *resv;
1776
1777 bo_va = list_first_entry(&vm->moved,
1778 struct amdgpu_bo_va, base.vm_status);
1779 spin_unlock(&vm->status_lock);
1780
1781 resv = bo_va->base.bo->tbo.resv;
1782
1783 /* Per VM BOs never need to bo cleared in the page tables */
1784 if (resv == vm->root.base.bo->tbo.resv)
1785 clear = false;
1786 /* Try to reserve the BO to avoid clearing its ptes */
1787 else if (!amdgpu_vm_debug && reservation_object_trylock(resv))
1788 clear = false;
1789 /* Somebody else is using the BO right now */
1790 else
1791 clear = true;
1792
1793 r = amdgpu_vm_bo_update(adev, bo_va, clear);
1794 if (r)
1795 return r;
1796
1797 if (!clear && resv != vm->root.base.bo->tbo.resv)
1798 reservation_object_unlock(resv);
1799
1800 spin_lock(&vm->status_lock);
1801 }
1802 spin_unlock(&vm->status_lock);
1803
1804 return r;
1805}
1806
1807/**
1808 * amdgpu_vm_bo_add - add a bo to a specific vm
1809 *
1810 * @adev: amdgpu_device pointer
1811 * @vm: requested vm
1812 * @bo: amdgpu buffer object
1813 *
1814 * Add @bo into the requested vm.
1815 * Add @bo to the list of bos associated with the vm
1816 * Returns newly added bo_va or NULL for failure
1817 *
1818 * Object has to be reserved!
1819 */
1820struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
1821 struct amdgpu_vm *vm,
1822 struct amdgpu_bo *bo)
1823{
1824 struct amdgpu_bo_va *bo_va;
1825
1826 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
1827 if (bo_va == NULL) {
1828 return NULL;
1829 }
1830 bo_va->base.vm = vm;
1831 bo_va->base.bo = bo;
1832 INIT_LIST_HEAD(&bo_va->base.bo_list);
1833 INIT_LIST_HEAD(&bo_va->base.vm_status);
1834
1835 bo_va->ref_count = 1;
1836 INIT_LIST_HEAD(&bo_va->valids);
1837 INIT_LIST_HEAD(&bo_va->invalids);
1838
1839 if (!bo)
1840 return bo_va;
1841
1842 list_add_tail(&bo_va->base.bo_list, &bo->va);
1843
1844 if (bo->tbo.resv != vm->root.base.bo->tbo.resv)
1845 return bo_va;
1846
1847 if (bo->preferred_domains &
1848 amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type))
1849 return bo_va;
1850
1851 /*
1852 * We checked all the prerequisites, but it looks like this per VM BO
1853 * is currently evicted. add the BO to the evicted list to make sure it
1854 * is validated on next VM use to avoid fault.
1855 * */
1856 spin_lock(&vm->status_lock);
1857 list_move_tail(&bo_va->base.vm_status, &vm->evicted);
1858 spin_unlock(&vm->status_lock);
1859
1860 return bo_va;
1861}
1862
1863
1864/**
1865 * amdgpu_vm_bo_insert_mapping - insert a new mapping
1866 *
1867 * @adev: amdgpu_device pointer
1868 * @bo_va: bo_va to store the address
1869 * @mapping: the mapping to insert
1870 *
1871 * Insert a new mapping into all structures.
1872 */
1873static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
1874 struct amdgpu_bo_va *bo_va,
1875 struct amdgpu_bo_va_mapping *mapping)
1876{
1877 struct amdgpu_vm *vm = bo_va->base.vm;
1878 struct amdgpu_bo *bo = bo_va->base.bo;
1879
1880 mapping->bo_va = bo_va;
1881 list_add(&mapping->list, &bo_va->invalids);
1882 amdgpu_vm_it_insert(mapping, &vm->va);
1883
1884 if (mapping->flags & AMDGPU_PTE_PRT)
1885 amdgpu_vm_prt_get(adev);
1886
1887 if (bo && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
1888 spin_lock(&vm->status_lock);
1889 if (list_empty(&bo_va->base.vm_status))
1890 list_add(&bo_va->base.vm_status, &vm->moved);
1891 spin_unlock(&vm->status_lock);
1892 }
1893 trace_amdgpu_vm_bo_map(bo_va, mapping);
1894}
1895
1896/**
1897 * amdgpu_vm_bo_map - map bo inside a vm
1898 *
1899 * @adev: amdgpu_device pointer
1900 * @bo_va: bo_va to store the address
1901 * @saddr: where to map the BO
1902 * @offset: requested offset in the BO
1903 * @flags: attributes of pages (read/write/valid/etc.)
1904 *
1905 * Add a mapping of the BO at the specefied addr into the VM.
1906 * Returns 0 for success, error for failure.
1907 *
1908 * Object has to be reserved and unreserved outside!
1909 */
1910int amdgpu_vm_bo_map(struct amdgpu_device *adev,
1911 struct amdgpu_bo_va *bo_va,
1912 uint64_t saddr, uint64_t offset,
1913 uint64_t size, uint64_t flags)
1914{
1915 struct amdgpu_bo_va_mapping *mapping, *tmp;
1916 struct amdgpu_bo *bo = bo_va->base.bo;
1917 struct amdgpu_vm *vm = bo_va->base.vm;
1918 uint64_t eaddr;
1919
1920 /* validate the parameters */
1921 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
1922 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
1923 return -EINVAL;
1924
1925 /* make sure object fit at this offset */
1926 eaddr = saddr + size - 1;
1927 if (saddr >= eaddr ||
1928 (bo && offset + size > amdgpu_bo_size(bo)))
1929 return -EINVAL;
1930
1931 saddr /= AMDGPU_GPU_PAGE_SIZE;
1932 eaddr /= AMDGPU_GPU_PAGE_SIZE;
1933
1934 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
1935 if (tmp) {
1936 /* bo and tmp overlap, invalid addr */
1937 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
1938 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
1939 tmp->start, tmp->last + 1);
1940 return -EINVAL;
1941 }
1942
1943 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1944 if (!mapping)
1945 return -ENOMEM;
1946
1947 mapping->start = saddr;
1948 mapping->last = eaddr;
1949 mapping->offset = offset;
1950 mapping->flags = flags;
1951
1952 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
1953
1954 return 0;
1955}
1956
1957/**
1958 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
1959 *
1960 * @adev: amdgpu_device pointer
1961 * @bo_va: bo_va to store the address
1962 * @saddr: where to map the BO
1963 * @offset: requested offset in the BO
1964 * @flags: attributes of pages (read/write/valid/etc.)
1965 *
1966 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
1967 * mappings as we do so.
1968 * Returns 0 for success, error for failure.
1969 *
1970 * Object has to be reserved and unreserved outside!
1971 */
1972int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
1973 struct amdgpu_bo_va *bo_va,
1974 uint64_t saddr, uint64_t offset,
1975 uint64_t size, uint64_t flags)
1976{
1977 struct amdgpu_bo_va_mapping *mapping;
1978 struct amdgpu_bo *bo = bo_va->base.bo;
1979 uint64_t eaddr;
1980 int r;
1981
1982 /* validate the parameters */
1983 if (saddr & AMDGPU_GPU_PAGE_MASK || offset & AMDGPU_GPU_PAGE_MASK ||
1984 size == 0 || size & AMDGPU_GPU_PAGE_MASK)
1985 return -EINVAL;
1986
1987 /* make sure object fit at this offset */
1988 eaddr = saddr + size - 1;
1989 if (saddr >= eaddr ||
1990 (bo && offset + size > amdgpu_bo_size(bo)))
1991 return -EINVAL;
1992
1993 /* Allocate all the needed memory */
1994 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
1995 if (!mapping)
1996 return -ENOMEM;
1997
1998 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
1999 if (r) {
2000 kfree(mapping);
2001 return r;
2002 }
2003
2004 saddr /= AMDGPU_GPU_PAGE_SIZE;
2005 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2006
2007 mapping->start = saddr;
2008 mapping->last = eaddr;
2009 mapping->offset = offset;
2010 mapping->flags = flags;
2011
2012 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2013
2014 return 0;
2015}
2016
2017/**
2018 * amdgpu_vm_bo_unmap - remove bo mapping from vm
2019 *
2020 * @adev: amdgpu_device pointer
2021 * @bo_va: bo_va to remove the address from
2022 * @saddr: where to the BO is mapped
2023 *
2024 * Remove a mapping of the BO at the specefied addr from the VM.
2025 * Returns 0 for success, error for failure.
2026 *
2027 * Object has to be reserved and unreserved outside!
2028 */
2029int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2030 struct amdgpu_bo_va *bo_va,
2031 uint64_t saddr)
2032{
2033 struct amdgpu_bo_va_mapping *mapping;
2034 struct amdgpu_vm *vm = bo_va->base.vm;
2035 bool valid = true;
2036
2037 saddr /= AMDGPU_GPU_PAGE_SIZE;
2038
2039 list_for_each_entry(mapping, &bo_va->valids, list) {
2040 if (mapping->start == saddr)
2041 break;
2042 }
2043
2044 if (&mapping->list == &bo_va->valids) {
2045 valid = false;
2046
2047 list_for_each_entry(mapping, &bo_va->invalids, list) {
2048 if (mapping->start == saddr)
2049 break;
2050 }
2051
2052 if (&mapping->list == &bo_va->invalids)
2053 return -ENOENT;
2054 }
2055
2056 list_del(&mapping->list);
2057 amdgpu_vm_it_remove(mapping, &vm->va);
2058 mapping->bo_va = NULL;
2059 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2060
2061 if (valid)
2062 list_add(&mapping->list, &vm->freed);
2063 else
2064 amdgpu_vm_free_mapping(adev, vm, mapping,
2065 bo_va->last_pt_update);
2066
2067 return 0;
2068}
2069
2070/**
2071 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
2072 *
2073 * @adev: amdgpu_device pointer
2074 * @vm: VM structure to use
2075 * @saddr: start of the range
2076 * @size: size of the range
2077 *
2078 * Remove all mappings in a range, split them as appropriate.
2079 * Returns 0 for success, error for failure.
2080 */
2081int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
2082 struct amdgpu_vm *vm,
2083 uint64_t saddr, uint64_t size)
2084{
2085 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
2086 LIST_HEAD(removed);
2087 uint64_t eaddr;
2088
2089 eaddr = saddr + size - 1;
2090 saddr /= AMDGPU_GPU_PAGE_SIZE;
2091 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2092
2093 /* Allocate all the needed memory */
2094 before = kzalloc(sizeof(*before), GFP_KERNEL);
2095 if (!before)
2096 return -ENOMEM;
2097 INIT_LIST_HEAD(&before->list);
2098
2099 after = kzalloc(sizeof(*after), GFP_KERNEL);
2100 if (!after) {
2101 kfree(before);
2102 return -ENOMEM;
2103 }
2104 INIT_LIST_HEAD(&after->list);
2105
2106 /* Now gather all removed mappings */
2107 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2108 while (tmp) {
2109 /* Remember mapping split at the start */
2110 if (tmp->start < saddr) {
2111 before->start = tmp->start;
2112 before->last = saddr - 1;
2113 before->offset = tmp->offset;
2114 before->flags = tmp->flags;
2115 list_add(&before->list, &tmp->list);
2116 }
2117
2118 /* Remember mapping split at the end */
2119 if (tmp->last > eaddr) {
2120 after->start = eaddr + 1;
2121 after->last = tmp->last;
2122 after->offset = tmp->offset;
2123 after->offset += after->start - tmp->start;
2124 after->flags = tmp->flags;
2125 list_add(&after->list, &tmp->list);
2126 }
2127
2128 list_del(&tmp->list);
2129 list_add(&tmp->list, &removed);
2130
2131 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
2132 }
2133
2134 /* And free them up */
2135 list_for_each_entry_safe(tmp, next, &removed, list) {
2136 amdgpu_vm_it_remove(tmp, &vm->va);
2137 list_del(&tmp->list);
2138
2139 if (tmp->start < saddr)
2140 tmp->start = saddr;
2141 if (tmp->last > eaddr)
2142 tmp->last = eaddr;
2143
2144 tmp->bo_va = NULL;
2145 list_add(&tmp->list, &vm->freed);
2146 trace_amdgpu_vm_bo_unmap(NULL, tmp);
2147 }
2148
2149 /* Insert partial mapping before the range */
2150 if (!list_empty(&before->list)) {
2151 amdgpu_vm_it_insert(before, &vm->va);
2152 if (before->flags & AMDGPU_PTE_PRT)
2153 amdgpu_vm_prt_get(adev);
2154 } else {
2155 kfree(before);
2156 }
2157
2158 /* Insert partial mapping after the range */
2159 if (!list_empty(&after->list)) {
2160 amdgpu_vm_it_insert(after, &vm->va);
2161 if (after->flags & AMDGPU_PTE_PRT)
2162 amdgpu_vm_prt_get(adev);
2163 } else {
2164 kfree(after);
2165 }
2166
2167 return 0;
2168}
2169
2170/**
2171 * amdgpu_vm_bo_lookup_mapping - find mapping by address
2172 *
2173 * @vm: the requested VM
2174 *
2175 * Find a mapping by it's address.
2176 */
2177struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
2178 uint64_t addr)
2179{
2180 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
2181}
2182
2183/**
2184 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
2185 *
2186 * @adev: amdgpu_device pointer
2187 * @bo_va: requested bo_va
2188 *
2189 * Remove @bo_va->bo from the requested vm.
2190 *
2191 * Object have to be reserved!
2192 */
2193void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2194 struct amdgpu_bo_va *bo_va)
2195{
2196 struct amdgpu_bo_va_mapping *mapping, *next;
2197 struct amdgpu_vm *vm = bo_va->base.vm;
2198
2199 list_del(&bo_va->base.bo_list);
2200
2201 spin_lock(&vm->status_lock);
2202 list_del(&bo_va->base.vm_status);
2203 spin_unlock(&vm->status_lock);
2204
2205 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2206 list_del(&mapping->list);
2207 amdgpu_vm_it_remove(mapping, &vm->va);
2208 mapping->bo_va = NULL;
2209 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2210 list_add(&mapping->list, &vm->freed);
2211 }
2212 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2213 list_del(&mapping->list);
2214 amdgpu_vm_it_remove(mapping, &vm->va);
2215 amdgpu_vm_free_mapping(adev, vm, mapping,
2216 bo_va->last_pt_update);
2217 }
2218
2219 dma_fence_put(bo_va->last_pt_update);
2220 kfree(bo_va);
2221}
2222
2223/**
2224 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2225 *
2226 * @adev: amdgpu_device pointer
2227 * @vm: requested vm
2228 * @bo: amdgpu buffer object
2229 *
2230 * Mark @bo as invalid.
2231 */
2232void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2233 struct amdgpu_bo *bo, bool evicted)
2234{
2235 struct amdgpu_vm_bo_base *bo_base;
2236
2237 list_for_each_entry(bo_base, &bo->va, bo_list) {
2238 struct amdgpu_vm *vm = bo_base->vm;
2239
2240 bo_base->moved = true;
2241 if (evicted && bo->tbo.resv == vm->root.base.bo->tbo.resv) {
2242 spin_lock(&bo_base->vm->status_lock);
2243 if (bo->tbo.type == ttm_bo_type_kernel)
2244 list_move(&bo_base->vm_status, &vm->evicted);
2245 else
2246 list_move_tail(&bo_base->vm_status,
2247 &vm->evicted);
2248 spin_unlock(&bo_base->vm->status_lock);
2249 continue;
2250 }
2251
2252 if (bo->tbo.type == ttm_bo_type_kernel) {
2253 spin_lock(&bo_base->vm->status_lock);
2254 if (list_empty(&bo_base->vm_status))
2255 list_add(&bo_base->vm_status, &vm->relocated);
2256 spin_unlock(&bo_base->vm->status_lock);
2257 continue;
2258 }
2259
2260 spin_lock(&bo_base->vm->status_lock);
2261 if (list_empty(&bo_base->vm_status))
2262 list_add(&bo_base->vm_status, &vm->moved);
2263 spin_unlock(&bo_base->vm->status_lock);
2264 }
2265}
2266
2267static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2268{
2269 /* Total bits covered by PD + PTs */
2270 unsigned bits = ilog2(vm_size) + 18;
2271
2272 /* Make sure the PD is 4K in size up to 8GB address space.
2273 Above that split equal between PD and PTs */
2274 if (vm_size <= 8)
2275 return (bits - 9);
2276 else
2277 return ((bits + 3) / 2);
2278}
2279
2280/**
2281 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2282 *
2283 * @adev: amdgpu_device pointer
2284 * @vm_size: the default vm size if it's set auto
2285 */
2286void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t vm_size,
2287 uint32_t fragment_size_default, unsigned max_level,
2288 unsigned max_bits)
2289{
2290 uint64_t tmp;
2291
2292 /* adjust vm size first */
2293 if (amdgpu_vm_size != -1) {
2294 unsigned max_size = 1 << (max_bits - 30);
2295
2296 vm_size = amdgpu_vm_size;
2297 if (vm_size > max_size) {
2298 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2299 amdgpu_vm_size, max_size);
2300 vm_size = max_size;
2301 }
2302 }
2303
2304 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2305
2306 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2307 if (amdgpu_vm_block_size != -1)
2308 tmp >>= amdgpu_vm_block_size - 9;
2309 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2310 adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
2311 switch (adev->vm_manager.num_level) {
2312 case 3:
2313 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2314 break;
2315 case 2:
2316 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2317 break;
2318 case 1:
2319 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2320 break;
2321 default:
2322 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2323 }
2324 /* block size depends on vm size and hw setup*/
2325 if (amdgpu_vm_block_size != -1)
2326 adev->vm_manager.block_size =
2327 min((unsigned)amdgpu_vm_block_size, max_bits
2328 - AMDGPU_GPU_PAGE_SHIFT
2329 - 9 * adev->vm_manager.num_level);
2330 else if (adev->vm_manager.num_level > 1)
2331 adev->vm_manager.block_size = 9;
2332 else
2333 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2334
2335 if (amdgpu_vm_fragment_size == -1)
2336 adev->vm_manager.fragment_size = fragment_size_default;
2337 else
2338 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2339
2340 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2341 vm_size, adev->vm_manager.num_level + 1,
2342 adev->vm_manager.block_size,
2343 adev->vm_manager.fragment_size);
2344}
2345
2346/**
2347 * amdgpu_vm_init - initialize a vm instance
2348 *
2349 * @adev: amdgpu_device pointer
2350 * @vm: requested vm
2351 * @vm_context: Indicates if it GFX or Compute context
2352 *
2353 * Init @vm fields.
2354 */
2355int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
2356 int vm_context, unsigned int pasid)
2357{
2358 const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
2359 AMDGPU_VM_PTE_COUNT(adev) * 8);
2360 unsigned ring_instance;
2361 struct amdgpu_ring *ring;
2362 struct drm_sched_rq *rq;
2363 unsigned long size;
2364 uint64_t flags;
2365 int r, i;
2366
2367 vm->va = RB_ROOT_CACHED;
2368 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2369 vm->reserved_vmid[i] = NULL;
2370 spin_lock_init(&vm->status_lock);
2371 INIT_LIST_HEAD(&vm->evicted);
2372 INIT_LIST_HEAD(&vm->relocated);
2373 INIT_LIST_HEAD(&vm->moved);
2374 INIT_LIST_HEAD(&vm->freed);
2375
2376 /* create scheduler entity for page table updates */
2377
2378 ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring);
2379 ring_instance %= adev->vm_manager.vm_pte_num_rings;
2380 ring = adev->vm_manager.vm_pte_rings[ring_instance];
2381 rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
2382 r = drm_sched_entity_init(&ring->sched, &vm->entity,
2383 rq, amdgpu_sched_jobs, NULL);
2384 if (r)
2385 return r;
2386
2387 vm->pte_support_ats = false;
2388
2389 if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) {
2390 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2391 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2392
2393 if (adev->asic_type == CHIP_RAVEN)
2394 vm->pte_support_ats = true;
2395 } else {
2396 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2397 AMDGPU_VM_USE_CPU_FOR_GFX);
2398 }
2399 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2400 vm->use_cpu_for_update ? "CPU" : "SDMA");
2401 WARN_ONCE((vm->use_cpu_for_update & !amdgpu_vm_is_large_bar(adev)),
2402 "CPU update of VM recommended only for large BAR system\n");
2403 vm->last_update = NULL;
2404
2405 flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
2406 if (vm->use_cpu_for_update)
2407 flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
2408 else
2409 flags |= AMDGPU_GEM_CREATE_SHADOW;
2410
2411 size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);
2412 r = amdgpu_bo_create(adev, size, align, AMDGPU_GEM_DOMAIN_VRAM, flags,
2413 ttm_bo_type_kernel, NULL, &vm->root.base.bo);
2414 if (r)
2415 goto error_free_sched_entity;
2416
2417 r = amdgpu_bo_reserve(vm->root.base.bo, true);
2418 if (r)
2419 goto error_free_root;
2420
2421 r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo,
2422 adev->vm_manager.root_level,
2423 vm->pte_support_ats);
2424 if (r)
2425 goto error_unreserve;
2426
2427 vm->root.base.vm = vm;
2428 list_add_tail(&vm->root.base.bo_list, &vm->root.base.bo->va);
2429 list_add_tail(&vm->root.base.vm_status, &vm->evicted);
2430 amdgpu_bo_unreserve(vm->root.base.bo);
2431
2432 if (pasid) {
2433 unsigned long flags;
2434
2435 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2436 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
2437 GFP_ATOMIC);
2438 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2439 if (r < 0)
2440 goto error_free_root;
2441
2442 vm->pasid = pasid;
2443 }
2444
2445 INIT_KFIFO(vm->faults);
2446 vm->fault_credit = 16;
2447
2448 return 0;
2449
2450error_unreserve:
2451 amdgpu_bo_unreserve(vm->root.base.bo);
2452
2453error_free_root:
2454 amdgpu_bo_unref(&vm->root.base.bo->shadow);
2455 amdgpu_bo_unref(&vm->root.base.bo);
2456 vm->root.base.bo = NULL;
2457
2458error_free_sched_entity:
2459 drm_sched_entity_fini(&ring->sched, &vm->entity);
2460
2461 return r;
2462}
2463
2464/**
2465 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
2466 *
2467 * This only works on GFX VMs that don't have any BOs added and no
2468 * page tables allocated yet.
2469 *
2470 * Changes the following VM parameters:
2471 * - use_cpu_for_update
2472 * - pte_supports_ats
2473 * - pasid (old PASID is released, because compute manages its own PASIDs)
2474 *
2475 * Reinitializes the page directory to reflect the changed ATS
2476 * setting. May leave behind an unused shadow BO for the page
2477 * directory when switching from SDMA updates to CPU updates.
2478 *
2479 * Returns 0 for success, -errno for errors.
2480 */
2481int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2482{
2483 bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
2484 int r;
2485
2486 r = amdgpu_bo_reserve(vm->root.base.bo, true);
2487 if (r)
2488 return r;
2489
2490 /* Sanity checks */
2491 if (!RB_EMPTY_ROOT(&vm->va.rb_root) || vm->root.entries) {
2492 r = -EINVAL;
2493 goto error;
2494 }
2495
2496 /* Check if PD needs to be reinitialized and do it before
2497 * changing any other state, in case it fails.
2498 */
2499 if (pte_support_ats != vm->pte_support_ats) {
2500 r = amdgpu_vm_clear_bo(adev, vm, vm->root.base.bo,
2501 adev->vm_manager.root_level,
2502 pte_support_ats);
2503 if (r)
2504 goto error;
2505 }
2506
2507 /* Update VM state */
2508 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2509 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
2510 vm->pte_support_ats = pte_support_ats;
2511 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2512 vm->use_cpu_for_update ? "CPU" : "SDMA");
2513 WARN_ONCE((vm->use_cpu_for_update & !amdgpu_vm_is_large_bar(adev)),
2514 "CPU update of VM recommended only for large BAR system\n");
2515
2516 if (vm->pasid) {
2517 unsigned long flags;
2518
2519 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2520 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
2521 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2522
2523 vm->pasid = 0;
2524 }
2525
2526error:
2527 amdgpu_bo_unreserve(vm->root.base.bo);
2528 return r;
2529}
2530
2531/**
2532 * amdgpu_vm_free_levels - free PD/PT levels
2533 *
2534 * @adev: amdgpu device structure
2535 * @parent: PD/PT starting level to free
2536 * @level: level of parent structure
2537 *
2538 * Free the page directory or page table level and all sub levels.
2539 */
2540static void amdgpu_vm_free_levels(struct amdgpu_device *adev,
2541 struct amdgpu_vm_pt *parent,
2542 unsigned level)
2543{
2544 unsigned i, num_entries = amdgpu_vm_num_entries(adev, level);
2545
2546 if (parent->base.bo) {
2547 list_del(&parent->base.bo_list);
2548 list_del(&parent->base.vm_status);
2549 amdgpu_bo_unref(&parent->base.bo->shadow);
2550 amdgpu_bo_unref(&parent->base.bo);
2551 }
2552
2553 if (parent->entries)
2554 for (i = 0; i < num_entries; i++)
2555 amdgpu_vm_free_levels(adev, &parent->entries[i],
2556 level + 1);
2557
2558 kvfree(parent->entries);
2559}
2560
2561/**
2562 * amdgpu_vm_fini - tear down a vm instance
2563 *
2564 * @adev: amdgpu_device pointer
2565 * @vm: requested vm
2566 *
2567 * Tear down @vm.
2568 * Unbind the VM and remove all bos from the vm bo list
2569 */
2570void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2571{
2572 struct amdgpu_bo_va_mapping *mapping, *tmp;
2573 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
2574 struct amdgpu_bo *root;
2575 u64 fault;
2576 int i, r;
2577
2578 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
2579
2580 /* Clear pending page faults from IH when the VM is destroyed */
2581 while (kfifo_get(&vm->faults, &fault))
2582 amdgpu_ih_clear_fault(adev, fault);
2583
2584 if (vm->pasid) {
2585 unsigned long flags;
2586
2587 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2588 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
2589 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2590 }
2591
2592 drm_sched_entity_fini(vm->entity.sched, &vm->entity);
2593
2594 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
2595 dev_err(adev->dev, "still active bo inside vm\n");
2596 }
2597 rbtree_postorder_for_each_entry_safe(mapping, tmp,
2598 &vm->va.rb_root, rb) {
2599 list_del(&mapping->list);
2600 amdgpu_vm_it_remove(mapping, &vm->va);
2601 kfree(mapping);
2602 }
2603 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
2604 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
2605 amdgpu_vm_prt_fini(adev, vm);
2606 prt_fini_needed = false;
2607 }
2608
2609 list_del(&mapping->list);
2610 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
2611 }
2612
2613 root = amdgpu_bo_ref(vm->root.base.bo);
2614 r = amdgpu_bo_reserve(root, true);
2615 if (r) {
2616 dev_err(adev->dev, "Leaking page tables because BO reservation failed\n");
2617 } else {
2618 amdgpu_vm_free_levels(adev, &vm->root,
2619 adev->vm_manager.root_level);
2620 amdgpu_bo_unreserve(root);
2621 }
2622 amdgpu_bo_unref(&root);
2623 dma_fence_put(vm->last_update);
2624 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2625 amdgpu_vmid_free_reserved(adev, vm, i);
2626}
2627
2628/**
2629 * amdgpu_vm_pasid_fault_credit - Check fault credit for given PASID
2630 *
2631 * @adev: amdgpu_device pointer
2632 * @pasid: PASID do identify the VM
2633 *
2634 * This function is expected to be called in interrupt context. Returns
2635 * true if there was fault credit, false otherwise
2636 */
2637bool amdgpu_vm_pasid_fault_credit(struct amdgpu_device *adev,
2638 unsigned int pasid)
2639{
2640 struct amdgpu_vm *vm;
2641
2642 spin_lock(&adev->vm_manager.pasid_lock);
2643 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
2644 if (!vm) {
2645 /* VM not found, can't track fault credit */
2646 spin_unlock(&adev->vm_manager.pasid_lock);
2647 return true;
2648 }
2649
2650 /* No lock needed. only accessed by IRQ handler */
2651 if (!vm->fault_credit) {
2652 /* Too many faults in this VM */
2653 spin_unlock(&adev->vm_manager.pasid_lock);
2654 return false;
2655 }
2656
2657 vm->fault_credit--;
2658 spin_unlock(&adev->vm_manager.pasid_lock);
2659 return true;
2660}
2661
2662/**
2663 * amdgpu_vm_manager_init - init the VM manager
2664 *
2665 * @adev: amdgpu_device pointer
2666 *
2667 * Initialize the VM manager structures
2668 */
2669void amdgpu_vm_manager_init(struct amdgpu_device *adev)
2670{
2671 unsigned i;
2672
2673 amdgpu_vmid_mgr_init(adev);
2674
2675 adev->vm_manager.fence_context =
2676 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
2677 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
2678 adev->vm_manager.seqno[i] = 0;
2679
2680 atomic_set(&adev->vm_manager.vm_pte_next_ring, 0);
2681 spin_lock_init(&adev->vm_manager.prt_lock);
2682 atomic_set(&adev->vm_manager.num_prt_users, 0);
2683
2684 /* If not overridden by the user, by default, only in large BAR systems
2685 * Compute VM tables will be updated by CPU
2686 */
2687#ifdef CONFIG_X86_64
2688 if (amdgpu_vm_update_mode == -1) {
2689 if (amdgpu_vm_is_large_bar(adev))
2690 adev->vm_manager.vm_update_mode =
2691 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
2692 else
2693 adev->vm_manager.vm_update_mode = 0;
2694 } else
2695 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
2696#else
2697 adev->vm_manager.vm_update_mode = 0;
2698#endif
2699
2700 idr_init(&adev->vm_manager.pasid_idr);
2701 spin_lock_init(&adev->vm_manager.pasid_lock);
2702}
2703
2704/**
2705 * amdgpu_vm_manager_fini - cleanup VM manager
2706 *
2707 * @adev: amdgpu_device pointer
2708 *
2709 * Cleanup the VM manager and free resources.
2710 */
2711void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
2712{
2713 WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr));
2714 idr_destroy(&adev->vm_manager.pasid_idr);
2715
2716 amdgpu_vmid_mgr_fini(adev);
2717}
2718
2719int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
2720{
2721 union drm_amdgpu_vm *args = data;
2722 struct amdgpu_device *adev = dev->dev_private;
2723 struct amdgpu_fpriv *fpriv = filp->driver_priv;
2724 int r;
2725
2726 switch (args->in.op) {
2727 case AMDGPU_VM_OP_RESERVE_VMID:
2728 /* current, we only have requirement to reserve vmid from gfxhub */
2729 r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
2730 if (r)
2731 return r;
2732 break;
2733 case AMDGPU_VM_OP_UNRESERVE_VMID:
2734 amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB);
2735 break;
2736 default:
2737 return -EINVAL;
2738 }
2739
2740 return 0;
2741}
1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29#include <linux/dma-fence-array.h>
30#include <linux/interval_tree_generic.h>
31#include <linux/idr.h>
32#include <linux/dma-buf.h>
33
34#include <drm/amdgpu_drm.h>
35#include <drm/drm_drv.h>
36#include "amdgpu.h"
37#include "amdgpu_trace.h"
38#include "amdgpu_amdkfd.h"
39#include "amdgpu_gmc.h"
40#include "amdgpu_xgmi.h"
41#include "amdgpu_dma_buf.h"
42#include "amdgpu_res_cursor.h"
43#include "kfd_svm.h"
44
45/**
46 * DOC: GPUVM
47 *
48 * GPUVM is similar to the legacy gart on older asics, however
49 * rather than there being a single global gart table
50 * for the entire GPU, there are multiple VM page tables active
51 * at any given time. The VM page tables can contain a mix
52 * vram pages and system memory pages and system memory pages
53 * can be mapped as snooped (cached system pages) or unsnooped
54 * (uncached system pages).
55 * Each VM has an ID associated with it and there is a page table
56 * associated with each VMID. When execting a command buffer,
57 * the kernel tells the the ring what VMID to use for that command
58 * buffer. VMIDs are allocated dynamically as commands are submitted.
59 * The userspace drivers maintain their own address space and the kernel
60 * sets up their pages tables accordingly when they submit their
61 * command buffers and a VMID is assigned.
62 * Cayman/Trinity support up to 8 active VMs at any given time;
63 * SI supports 16.
64 */
65
66#define START(node) ((node)->start)
67#define LAST(node) ((node)->last)
68
69INTERVAL_TREE_DEFINE(struct amdgpu_bo_va_mapping, rb, uint64_t, __subtree_last,
70 START, LAST, static, amdgpu_vm_it)
71
72#undef START
73#undef LAST
74
75/**
76 * struct amdgpu_prt_cb - Helper to disable partial resident texture feature from a fence callback
77 */
78struct amdgpu_prt_cb {
79
80 /**
81 * @adev: amdgpu device
82 */
83 struct amdgpu_device *adev;
84
85 /**
86 * @cb: callback
87 */
88 struct dma_fence_cb cb;
89};
90
91/*
92 * vm eviction_lock can be taken in MMU notifiers. Make sure no reclaim-FS
93 * happens while holding this lock anywhere to prevent deadlocks when
94 * an MMU notifier runs in reclaim-FS context.
95 */
96static inline void amdgpu_vm_eviction_lock(struct amdgpu_vm *vm)
97{
98 mutex_lock(&vm->eviction_lock);
99 vm->saved_flags = memalloc_noreclaim_save();
100}
101
102static inline int amdgpu_vm_eviction_trylock(struct amdgpu_vm *vm)
103{
104 if (mutex_trylock(&vm->eviction_lock)) {
105 vm->saved_flags = memalloc_noreclaim_save();
106 return 1;
107 }
108 return 0;
109}
110
111static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm)
112{
113 memalloc_noreclaim_restore(vm->saved_flags);
114 mutex_unlock(&vm->eviction_lock);
115}
116
117/**
118 * amdgpu_vm_level_shift - return the addr shift for each level
119 *
120 * @adev: amdgpu_device pointer
121 * @level: VMPT level
122 *
123 * Returns:
124 * The number of bits the pfn needs to be right shifted for a level.
125 */
126static unsigned amdgpu_vm_level_shift(struct amdgpu_device *adev,
127 unsigned level)
128{
129 switch (level) {
130 case AMDGPU_VM_PDB2:
131 case AMDGPU_VM_PDB1:
132 case AMDGPU_VM_PDB0:
133 return 9 * (AMDGPU_VM_PDB0 - level) +
134 adev->vm_manager.block_size;
135 case AMDGPU_VM_PTB:
136 return 0;
137 default:
138 return ~0;
139 }
140}
141
142/**
143 * amdgpu_vm_num_entries - return the number of entries in a PD/PT
144 *
145 * @adev: amdgpu_device pointer
146 * @level: VMPT level
147 *
148 * Returns:
149 * The number of entries in a page directory or page table.
150 */
151static unsigned amdgpu_vm_num_entries(struct amdgpu_device *adev,
152 unsigned level)
153{
154 unsigned shift = amdgpu_vm_level_shift(adev,
155 adev->vm_manager.root_level);
156
157 if (level == adev->vm_manager.root_level)
158 /* For the root directory */
159 return round_up(adev->vm_manager.max_pfn, 1ULL << shift)
160 >> shift;
161 else if (level != AMDGPU_VM_PTB)
162 /* Everything in between */
163 return 512;
164 else
165 /* For the page tables on the leaves */
166 return AMDGPU_VM_PTE_COUNT(adev);
167}
168
169/**
170 * amdgpu_vm_num_ats_entries - return the number of ATS entries in the root PD
171 *
172 * @adev: amdgpu_device pointer
173 *
174 * Returns:
175 * The number of entries in the root page directory which needs the ATS setting.
176 */
177static unsigned amdgpu_vm_num_ats_entries(struct amdgpu_device *adev)
178{
179 unsigned shift;
180
181 shift = amdgpu_vm_level_shift(adev, adev->vm_manager.root_level);
182 return AMDGPU_GMC_HOLE_START >> (shift + AMDGPU_GPU_PAGE_SHIFT);
183}
184
185/**
186 * amdgpu_vm_entries_mask - the mask to get the entry number of a PD/PT
187 *
188 * @adev: amdgpu_device pointer
189 * @level: VMPT level
190 *
191 * Returns:
192 * The mask to extract the entry number of a PD/PT from an address.
193 */
194static uint32_t amdgpu_vm_entries_mask(struct amdgpu_device *adev,
195 unsigned int level)
196{
197 if (level <= adev->vm_manager.root_level)
198 return 0xffffffff;
199 else if (level != AMDGPU_VM_PTB)
200 return 0x1ff;
201 else
202 return AMDGPU_VM_PTE_COUNT(adev) - 1;
203}
204
205/**
206 * amdgpu_vm_bo_size - returns the size of the BOs in bytes
207 *
208 * @adev: amdgpu_device pointer
209 * @level: VMPT level
210 *
211 * Returns:
212 * The size of the BO for a page directory or page table in bytes.
213 */
214static unsigned amdgpu_vm_bo_size(struct amdgpu_device *adev, unsigned level)
215{
216 return AMDGPU_GPU_PAGE_ALIGN(amdgpu_vm_num_entries(adev, level) * 8);
217}
218
219/**
220 * amdgpu_vm_bo_evicted - vm_bo is evicted
221 *
222 * @vm_bo: vm_bo which is evicted
223 *
224 * State for PDs/PTs and per VM BOs which are not at the location they should
225 * be.
226 */
227static void amdgpu_vm_bo_evicted(struct amdgpu_vm_bo_base *vm_bo)
228{
229 struct amdgpu_vm *vm = vm_bo->vm;
230 struct amdgpu_bo *bo = vm_bo->bo;
231
232 vm_bo->moved = true;
233 if (bo->tbo.type == ttm_bo_type_kernel)
234 list_move(&vm_bo->vm_status, &vm->evicted);
235 else
236 list_move_tail(&vm_bo->vm_status, &vm->evicted);
237}
238/**
239 * amdgpu_vm_bo_moved - vm_bo is moved
240 *
241 * @vm_bo: vm_bo which is moved
242 *
243 * State for per VM BOs which are moved, but that change is not yet reflected
244 * in the page tables.
245 */
246static void amdgpu_vm_bo_moved(struct amdgpu_vm_bo_base *vm_bo)
247{
248 list_move(&vm_bo->vm_status, &vm_bo->vm->moved);
249}
250
251/**
252 * amdgpu_vm_bo_idle - vm_bo is idle
253 *
254 * @vm_bo: vm_bo which is now idle
255 *
256 * State for PDs/PTs and per VM BOs which have gone through the state machine
257 * and are now idle.
258 */
259static void amdgpu_vm_bo_idle(struct amdgpu_vm_bo_base *vm_bo)
260{
261 list_move(&vm_bo->vm_status, &vm_bo->vm->idle);
262 vm_bo->moved = false;
263}
264
265/**
266 * amdgpu_vm_bo_invalidated - vm_bo is invalidated
267 *
268 * @vm_bo: vm_bo which is now invalidated
269 *
270 * State for normal BOs which are invalidated and that change not yet reflected
271 * in the PTs.
272 */
273static void amdgpu_vm_bo_invalidated(struct amdgpu_vm_bo_base *vm_bo)
274{
275 spin_lock(&vm_bo->vm->invalidated_lock);
276 list_move(&vm_bo->vm_status, &vm_bo->vm->invalidated);
277 spin_unlock(&vm_bo->vm->invalidated_lock);
278}
279
280/**
281 * amdgpu_vm_bo_relocated - vm_bo is reloacted
282 *
283 * @vm_bo: vm_bo which is relocated
284 *
285 * State for PDs/PTs which needs to update their parent PD.
286 * For the root PD, just move to idle state.
287 */
288static void amdgpu_vm_bo_relocated(struct amdgpu_vm_bo_base *vm_bo)
289{
290 if (vm_bo->bo->parent)
291 list_move(&vm_bo->vm_status, &vm_bo->vm->relocated);
292 else
293 amdgpu_vm_bo_idle(vm_bo);
294}
295
296/**
297 * amdgpu_vm_bo_done - vm_bo is done
298 *
299 * @vm_bo: vm_bo which is now done
300 *
301 * State for normal BOs which are invalidated and that change has been updated
302 * in the PTs.
303 */
304static void amdgpu_vm_bo_done(struct amdgpu_vm_bo_base *vm_bo)
305{
306 spin_lock(&vm_bo->vm->invalidated_lock);
307 list_move(&vm_bo->vm_status, &vm_bo->vm->done);
308 spin_unlock(&vm_bo->vm->invalidated_lock);
309}
310
311/**
312 * amdgpu_vm_bo_base_init - Adds bo to the list of bos associated with the vm
313 *
314 * @base: base structure for tracking BO usage in a VM
315 * @vm: vm to which bo is to be added
316 * @bo: amdgpu buffer object
317 *
318 * Initialize a bo_va_base structure and add it to the appropriate lists
319 *
320 */
321static void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base,
322 struct amdgpu_vm *vm,
323 struct amdgpu_bo *bo)
324{
325 base->vm = vm;
326 base->bo = bo;
327 base->next = NULL;
328 INIT_LIST_HEAD(&base->vm_status);
329
330 if (!bo)
331 return;
332 base->next = bo->vm_bo;
333 bo->vm_bo = base;
334
335 if (bo->tbo.base.resv != vm->root.bo->tbo.base.resv)
336 return;
337
338 vm->bulk_moveable = false;
339 if (bo->tbo.type == ttm_bo_type_kernel && bo->parent)
340 amdgpu_vm_bo_relocated(base);
341 else
342 amdgpu_vm_bo_idle(base);
343
344 if (bo->preferred_domains &
345 amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type))
346 return;
347
348 /*
349 * we checked all the prerequisites, but it looks like this per vm bo
350 * is currently evicted. add the bo to the evicted list to make sure it
351 * is validated on next vm use to avoid fault.
352 * */
353 amdgpu_vm_bo_evicted(base);
354}
355
356/**
357 * amdgpu_vm_pt_parent - get the parent page directory
358 *
359 * @pt: child page table
360 *
361 * Helper to get the parent entry for the child page table. NULL if we are at
362 * the root page directory.
363 */
364static struct amdgpu_vm_bo_base *amdgpu_vm_pt_parent(struct amdgpu_vm_bo_base *pt)
365{
366 struct amdgpu_bo *parent = pt->bo->parent;
367
368 if (!parent)
369 return NULL;
370
371 return parent->vm_bo;
372}
373
374/*
375 * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt
376 */
377struct amdgpu_vm_pt_cursor {
378 uint64_t pfn;
379 struct amdgpu_vm_bo_base *parent;
380 struct amdgpu_vm_bo_base *entry;
381 unsigned level;
382};
383
384/**
385 * amdgpu_vm_pt_start - start PD/PT walk
386 *
387 * @adev: amdgpu_device pointer
388 * @vm: amdgpu_vm structure
389 * @start: start address of the walk
390 * @cursor: state to initialize
391 *
392 * Initialize a amdgpu_vm_pt_cursor to start a walk.
393 */
394static void amdgpu_vm_pt_start(struct amdgpu_device *adev,
395 struct amdgpu_vm *vm, uint64_t start,
396 struct amdgpu_vm_pt_cursor *cursor)
397{
398 cursor->pfn = start;
399 cursor->parent = NULL;
400 cursor->entry = &vm->root;
401 cursor->level = adev->vm_manager.root_level;
402}
403
404/**
405 * amdgpu_vm_pt_descendant - go to child node
406 *
407 * @adev: amdgpu_device pointer
408 * @cursor: current state
409 *
410 * Walk to the child node of the current node.
411 * Returns:
412 * True if the walk was possible, false otherwise.
413 */
414static bool amdgpu_vm_pt_descendant(struct amdgpu_device *adev,
415 struct amdgpu_vm_pt_cursor *cursor)
416{
417 unsigned mask, shift, idx;
418
419 if ((cursor->level == AMDGPU_VM_PTB) || !cursor->entry ||
420 !cursor->entry->bo)
421 return false;
422
423 mask = amdgpu_vm_entries_mask(adev, cursor->level);
424 shift = amdgpu_vm_level_shift(adev, cursor->level);
425
426 ++cursor->level;
427 idx = (cursor->pfn >> shift) & mask;
428 cursor->parent = cursor->entry;
429 cursor->entry = &to_amdgpu_bo_vm(cursor->entry->bo)->entries[idx];
430 return true;
431}
432
433/**
434 * amdgpu_vm_pt_sibling - go to sibling node
435 *
436 * @adev: amdgpu_device pointer
437 * @cursor: current state
438 *
439 * Walk to the sibling node of the current node.
440 * Returns:
441 * True if the walk was possible, false otherwise.
442 */
443static bool amdgpu_vm_pt_sibling(struct amdgpu_device *adev,
444 struct amdgpu_vm_pt_cursor *cursor)
445{
446 unsigned shift, num_entries;
447
448 /* Root doesn't have a sibling */
449 if (!cursor->parent)
450 return false;
451
452 /* Go to our parents and see if we got a sibling */
453 shift = amdgpu_vm_level_shift(adev, cursor->level - 1);
454 num_entries = amdgpu_vm_num_entries(adev, cursor->level - 1);
455
456 if (cursor->entry == &to_amdgpu_bo_vm(cursor->parent->bo)->entries[num_entries - 1])
457 return false;
458
459 cursor->pfn += 1ULL << shift;
460 cursor->pfn &= ~((1ULL << shift) - 1);
461 ++cursor->entry;
462 return true;
463}
464
465/**
466 * amdgpu_vm_pt_ancestor - go to parent node
467 *
468 * @cursor: current state
469 *
470 * Walk to the parent node of the current node.
471 * Returns:
472 * True if the walk was possible, false otherwise.
473 */
474static bool amdgpu_vm_pt_ancestor(struct amdgpu_vm_pt_cursor *cursor)
475{
476 if (!cursor->parent)
477 return false;
478
479 --cursor->level;
480 cursor->entry = cursor->parent;
481 cursor->parent = amdgpu_vm_pt_parent(cursor->parent);
482 return true;
483}
484
485/**
486 * amdgpu_vm_pt_next - get next PD/PT in hieratchy
487 *
488 * @adev: amdgpu_device pointer
489 * @cursor: current state
490 *
491 * Walk the PD/PT tree to the next node.
492 */
493static void amdgpu_vm_pt_next(struct amdgpu_device *adev,
494 struct amdgpu_vm_pt_cursor *cursor)
495{
496 /* First try a newborn child */
497 if (amdgpu_vm_pt_descendant(adev, cursor))
498 return;
499
500 /* If that didn't worked try to find a sibling */
501 while (!amdgpu_vm_pt_sibling(adev, cursor)) {
502 /* No sibling, go to our parents and grandparents */
503 if (!amdgpu_vm_pt_ancestor(cursor)) {
504 cursor->pfn = ~0ll;
505 return;
506 }
507 }
508}
509
510/**
511 * amdgpu_vm_pt_first_dfs - start a deep first search
512 *
513 * @adev: amdgpu_device structure
514 * @vm: amdgpu_vm structure
515 * @start: optional cursor to start with
516 * @cursor: state to initialize
517 *
518 * Starts a deep first traversal of the PD/PT tree.
519 */
520static void amdgpu_vm_pt_first_dfs(struct amdgpu_device *adev,
521 struct amdgpu_vm *vm,
522 struct amdgpu_vm_pt_cursor *start,
523 struct amdgpu_vm_pt_cursor *cursor)
524{
525 if (start)
526 *cursor = *start;
527 else
528 amdgpu_vm_pt_start(adev, vm, 0, cursor);
529 while (amdgpu_vm_pt_descendant(adev, cursor));
530}
531
532/**
533 * amdgpu_vm_pt_continue_dfs - check if the deep first search should continue
534 *
535 * @start: starting point for the search
536 * @entry: current entry
537 *
538 * Returns:
539 * True when the search should continue, false otherwise.
540 */
541static bool amdgpu_vm_pt_continue_dfs(struct amdgpu_vm_pt_cursor *start,
542 struct amdgpu_vm_bo_base *entry)
543{
544 return entry && (!start || entry != start->entry);
545}
546
547/**
548 * amdgpu_vm_pt_next_dfs - get the next node for a deep first search
549 *
550 * @adev: amdgpu_device structure
551 * @cursor: current state
552 *
553 * Move the cursor to the next node in a deep first search.
554 */
555static void amdgpu_vm_pt_next_dfs(struct amdgpu_device *adev,
556 struct amdgpu_vm_pt_cursor *cursor)
557{
558 if (!cursor->entry)
559 return;
560
561 if (!cursor->parent)
562 cursor->entry = NULL;
563 else if (amdgpu_vm_pt_sibling(adev, cursor))
564 while (amdgpu_vm_pt_descendant(adev, cursor));
565 else
566 amdgpu_vm_pt_ancestor(cursor);
567}
568
569/*
570 * for_each_amdgpu_vm_pt_dfs_safe - safe deep first search of all PDs/PTs
571 */
572#define for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry) \
573 for (amdgpu_vm_pt_first_dfs((adev), (vm), (start), &(cursor)), \
574 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor));\
575 amdgpu_vm_pt_continue_dfs((start), (entry)); \
576 (entry) = (cursor).entry, amdgpu_vm_pt_next_dfs((adev), &(cursor)))
577
578/**
579 * amdgpu_vm_get_pd_bo - add the VM PD to a validation list
580 *
581 * @vm: vm providing the BOs
582 * @validated: head of validation list
583 * @entry: entry to add
584 *
585 * Add the page directory to the list of BOs to
586 * validate for command submission.
587 */
588void amdgpu_vm_get_pd_bo(struct amdgpu_vm *vm,
589 struct list_head *validated,
590 struct amdgpu_bo_list_entry *entry)
591{
592 entry->priority = 0;
593 entry->tv.bo = &vm->root.bo->tbo;
594 /* Two for VM updates, one for TTM and one for the CS job */
595 entry->tv.num_shared = 4;
596 entry->user_pages = NULL;
597 list_add(&entry->tv.head, validated);
598}
599
600/**
601 * amdgpu_vm_del_from_lru_notify - update bulk_moveable flag
602 *
603 * @bo: BO which was removed from the LRU
604 *
605 * Make sure the bulk_moveable flag is updated when a BO is removed from the
606 * LRU.
607 */
608void amdgpu_vm_del_from_lru_notify(struct ttm_buffer_object *bo)
609{
610 struct amdgpu_bo *abo;
611 struct amdgpu_vm_bo_base *bo_base;
612
613 if (!amdgpu_bo_is_amdgpu_bo(bo))
614 return;
615
616 if (bo->pin_count)
617 return;
618
619 abo = ttm_to_amdgpu_bo(bo);
620 if (!abo->parent)
621 return;
622 for (bo_base = abo->vm_bo; bo_base; bo_base = bo_base->next) {
623 struct amdgpu_vm *vm = bo_base->vm;
624
625 if (abo->tbo.base.resv == vm->root.bo->tbo.base.resv)
626 vm->bulk_moveable = false;
627 }
628
629}
630/**
631 * amdgpu_vm_move_to_lru_tail - move all BOs to the end of LRU
632 *
633 * @adev: amdgpu device pointer
634 * @vm: vm providing the BOs
635 *
636 * Move all BOs to the end of LRU and remember their positions to put them
637 * together.
638 */
639void amdgpu_vm_move_to_lru_tail(struct amdgpu_device *adev,
640 struct amdgpu_vm *vm)
641{
642 struct amdgpu_vm_bo_base *bo_base;
643
644 if (vm->bulk_moveable) {
645 spin_lock(&adev->mman.bdev.lru_lock);
646 ttm_bo_bulk_move_lru_tail(&vm->lru_bulk_move);
647 spin_unlock(&adev->mman.bdev.lru_lock);
648 return;
649 }
650
651 memset(&vm->lru_bulk_move, 0, sizeof(vm->lru_bulk_move));
652
653 spin_lock(&adev->mman.bdev.lru_lock);
654 list_for_each_entry(bo_base, &vm->idle, vm_status) {
655 struct amdgpu_bo *bo = bo_base->bo;
656 struct amdgpu_bo *shadow = amdgpu_bo_shadowed(bo);
657
658 if (!bo->parent)
659 continue;
660
661 ttm_bo_move_to_lru_tail(&bo->tbo, bo->tbo.resource,
662 &vm->lru_bulk_move);
663 if (shadow)
664 ttm_bo_move_to_lru_tail(&shadow->tbo,
665 shadow->tbo.resource,
666 &vm->lru_bulk_move);
667 }
668 spin_unlock(&adev->mman.bdev.lru_lock);
669
670 vm->bulk_moveable = true;
671}
672
673/**
674 * amdgpu_vm_validate_pt_bos - validate the page table BOs
675 *
676 * @adev: amdgpu device pointer
677 * @vm: vm providing the BOs
678 * @validate: callback to do the validation
679 * @param: parameter for the validation callback
680 *
681 * Validate the page table BOs on command submission if neccessary.
682 *
683 * Returns:
684 * Validation result.
685 */
686int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
687 int (*validate)(void *p, struct amdgpu_bo *bo),
688 void *param)
689{
690 struct amdgpu_vm_bo_base *bo_base, *tmp;
691 int r;
692
693 vm->bulk_moveable &= list_empty(&vm->evicted);
694
695 list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
696 struct amdgpu_bo *bo = bo_base->bo;
697 struct amdgpu_bo *shadow = amdgpu_bo_shadowed(bo);
698
699 r = validate(param, bo);
700 if (r)
701 return r;
702 if (shadow) {
703 r = validate(param, shadow);
704 if (r)
705 return r;
706 }
707
708 if (bo->tbo.type != ttm_bo_type_kernel) {
709 amdgpu_vm_bo_moved(bo_base);
710 } else {
711 vm->update_funcs->map_table(to_amdgpu_bo_vm(bo));
712 amdgpu_vm_bo_relocated(bo_base);
713 }
714 }
715
716 amdgpu_vm_eviction_lock(vm);
717 vm->evicting = false;
718 amdgpu_vm_eviction_unlock(vm);
719
720 return 0;
721}
722
723/**
724 * amdgpu_vm_ready - check VM is ready for updates
725 *
726 * @vm: VM to check
727 *
728 * Check if all VM PDs/PTs are ready for updates
729 *
730 * Returns:
731 * True if eviction list is empty.
732 */
733bool amdgpu_vm_ready(struct amdgpu_vm *vm)
734{
735 return list_empty(&vm->evicted);
736}
737
738/**
739 * amdgpu_vm_clear_bo - initially clear the PDs/PTs
740 *
741 * @adev: amdgpu_device pointer
742 * @vm: VM to clear BO from
743 * @vmbo: BO to clear
744 * @immediate: use an immediate update
745 *
746 * Root PD needs to be reserved when calling this.
747 *
748 * Returns:
749 * 0 on success, errno otherwise.
750 */
751static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
752 struct amdgpu_vm *vm,
753 struct amdgpu_bo_vm *vmbo,
754 bool immediate)
755{
756 struct ttm_operation_ctx ctx = { true, false };
757 unsigned level = adev->vm_manager.root_level;
758 struct amdgpu_vm_update_params params;
759 struct amdgpu_bo *ancestor = &vmbo->bo;
760 struct amdgpu_bo *bo = &vmbo->bo;
761 unsigned entries, ats_entries;
762 uint64_t addr;
763 int r;
764
765 /* Figure out our place in the hierarchy */
766 if (ancestor->parent) {
767 ++level;
768 while (ancestor->parent->parent) {
769 ++level;
770 ancestor = ancestor->parent;
771 }
772 }
773
774 entries = amdgpu_bo_size(bo) / 8;
775 if (!vm->pte_support_ats) {
776 ats_entries = 0;
777
778 } else if (!bo->parent) {
779 ats_entries = amdgpu_vm_num_ats_entries(adev);
780 ats_entries = min(ats_entries, entries);
781 entries -= ats_entries;
782
783 } else {
784 struct amdgpu_vm_bo_base *pt;
785
786 pt = ancestor->vm_bo;
787 ats_entries = amdgpu_vm_num_ats_entries(adev);
788 if ((pt - to_amdgpu_bo_vm(vm->root.bo)->entries) >= ats_entries) {
789 ats_entries = 0;
790 } else {
791 ats_entries = entries;
792 entries = 0;
793 }
794 }
795
796 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
797 if (r)
798 return r;
799
800 if (vmbo->shadow) {
801 struct amdgpu_bo *shadow = vmbo->shadow;
802
803 r = ttm_bo_validate(&shadow->tbo, &shadow->placement, &ctx);
804 if (r)
805 return r;
806 }
807
808 r = vm->update_funcs->map_table(vmbo);
809 if (r)
810 return r;
811
812 memset(¶ms, 0, sizeof(params));
813 params.adev = adev;
814 params.vm = vm;
815 params.immediate = immediate;
816
817 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
818 if (r)
819 return r;
820
821 addr = 0;
822 if (ats_entries) {
823 uint64_t value = 0, flags;
824
825 flags = AMDGPU_PTE_DEFAULT_ATC;
826 if (level != AMDGPU_VM_PTB) {
827 /* Handle leaf PDEs as PTEs */
828 flags |= AMDGPU_PDE_PTE;
829 amdgpu_gmc_get_vm_pde(adev, level, &value, &flags);
830 }
831
832 r = vm->update_funcs->update(¶ms, vmbo, addr, 0, ats_entries,
833 value, flags);
834 if (r)
835 return r;
836
837 addr += ats_entries * 8;
838 }
839
840 if (entries) {
841 uint64_t value = 0, flags = 0;
842
843 if (adev->asic_type >= CHIP_VEGA10) {
844 if (level != AMDGPU_VM_PTB) {
845 /* Handle leaf PDEs as PTEs */
846 flags |= AMDGPU_PDE_PTE;
847 amdgpu_gmc_get_vm_pde(adev, level,
848 &value, &flags);
849 } else {
850 /* Workaround for fault priority problem on GMC9 */
851 flags = AMDGPU_PTE_EXECUTABLE;
852 }
853 }
854
855 r = vm->update_funcs->update(¶ms, vmbo, addr, 0, entries,
856 value, flags);
857 if (r)
858 return r;
859 }
860
861 return vm->update_funcs->commit(¶ms, NULL);
862}
863
864/**
865 * amdgpu_vm_pt_create - create bo for PD/PT
866 *
867 * @adev: amdgpu_device pointer
868 * @vm: requesting vm
869 * @level: the page table level
870 * @immediate: use a immediate update
871 * @vmbo: pointer to the buffer object pointer
872 */
873static int amdgpu_vm_pt_create(struct amdgpu_device *adev,
874 struct amdgpu_vm *vm,
875 int level, bool immediate,
876 struct amdgpu_bo_vm **vmbo)
877{
878 struct amdgpu_bo_param bp;
879 struct amdgpu_bo *bo;
880 struct dma_resv *resv;
881 unsigned int num_entries;
882 int r;
883
884 memset(&bp, 0, sizeof(bp));
885
886 bp.size = amdgpu_vm_bo_size(adev, level);
887 bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
888 bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
889 bp.domain = amdgpu_bo_get_preferred_pin_domain(adev, bp.domain);
890 bp.flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
891 AMDGPU_GEM_CREATE_CPU_GTT_USWC;
892
893 if (level < AMDGPU_VM_PTB)
894 num_entries = amdgpu_vm_num_entries(adev, level);
895 else
896 num_entries = 0;
897
898 bp.bo_ptr_size = struct_size((*vmbo), entries, num_entries);
899
900 if (vm->use_cpu_for_update)
901 bp.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
902
903 bp.type = ttm_bo_type_kernel;
904 bp.no_wait_gpu = immediate;
905 if (vm->root.bo)
906 bp.resv = vm->root.bo->tbo.base.resv;
907
908 r = amdgpu_bo_create_vm(adev, &bp, vmbo);
909 if (r)
910 return r;
911
912 bo = &(*vmbo)->bo;
913 if (vm->is_compute_context || (adev->flags & AMD_IS_APU)) {
914 (*vmbo)->shadow = NULL;
915 return 0;
916 }
917
918 if (!bp.resv)
919 WARN_ON(dma_resv_lock(bo->tbo.base.resv,
920 NULL));
921 resv = bp.resv;
922 memset(&bp, 0, sizeof(bp));
923 bp.size = amdgpu_vm_bo_size(adev, level);
924 bp.domain = AMDGPU_GEM_DOMAIN_GTT;
925 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
926 bp.type = ttm_bo_type_kernel;
927 bp.resv = bo->tbo.base.resv;
928 bp.bo_ptr_size = sizeof(struct amdgpu_bo);
929
930 r = amdgpu_bo_create(adev, &bp, &(*vmbo)->shadow);
931
932 if (!resv)
933 dma_resv_unlock(bo->tbo.base.resv);
934
935 if (r) {
936 amdgpu_bo_unref(&bo);
937 return r;
938 }
939
940 (*vmbo)->shadow->parent = amdgpu_bo_ref(bo);
941 amdgpu_bo_add_to_shadow_list(*vmbo);
942
943 return 0;
944}
945
946/**
947 * amdgpu_vm_alloc_pts - Allocate a specific page table
948 *
949 * @adev: amdgpu_device pointer
950 * @vm: VM to allocate page tables for
951 * @cursor: Which page table to allocate
952 * @immediate: use an immediate update
953 *
954 * Make sure a specific page table or directory is allocated.
955 *
956 * Returns:
957 * 1 if page table needed to be allocated, 0 if page table was already
958 * allocated, negative errno if an error occurred.
959 */
960static int amdgpu_vm_alloc_pts(struct amdgpu_device *adev,
961 struct amdgpu_vm *vm,
962 struct amdgpu_vm_pt_cursor *cursor,
963 bool immediate)
964{
965 struct amdgpu_vm_bo_base *entry = cursor->entry;
966 struct amdgpu_bo *pt_bo;
967 struct amdgpu_bo_vm *pt;
968 int r;
969
970 if (entry->bo)
971 return 0;
972
973 r = amdgpu_vm_pt_create(adev, vm, cursor->level, immediate, &pt);
974 if (r)
975 return r;
976
977 /* Keep a reference to the root directory to avoid
978 * freeing them up in the wrong order.
979 */
980 pt_bo = &pt->bo;
981 pt_bo->parent = amdgpu_bo_ref(cursor->parent->bo);
982 amdgpu_vm_bo_base_init(entry, vm, pt_bo);
983 r = amdgpu_vm_clear_bo(adev, vm, pt, immediate);
984 if (r)
985 goto error_free_pt;
986
987 return 0;
988
989error_free_pt:
990 amdgpu_bo_unref(&pt->shadow);
991 amdgpu_bo_unref(&pt_bo);
992 return r;
993}
994
995/**
996 * amdgpu_vm_free_table - fre one PD/PT
997 *
998 * @entry: PDE to free
999 */
1000static void amdgpu_vm_free_table(struct amdgpu_vm_bo_base *entry)
1001{
1002 struct amdgpu_bo *shadow;
1003
1004 if (!entry->bo)
1005 return;
1006 shadow = amdgpu_bo_shadowed(entry->bo);
1007 entry->bo->vm_bo = NULL;
1008 list_del(&entry->vm_status);
1009 amdgpu_bo_unref(&shadow);
1010 amdgpu_bo_unref(&entry->bo);
1011}
1012
1013/**
1014 * amdgpu_vm_free_pts - free PD/PT levels
1015 *
1016 * @adev: amdgpu device structure
1017 * @vm: amdgpu vm structure
1018 * @start: optional cursor where to start freeing PDs/PTs
1019 *
1020 * Free the page directory or page table level and all sub levels.
1021 */
1022static void amdgpu_vm_free_pts(struct amdgpu_device *adev,
1023 struct amdgpu_vm *vm,
1024 struct amdgpu_vm_pt_cursor *start)
1025{
1026 struct amdgpu_vm_pt_cursor cursor;
1027 struct amdgpu_vm_bo_base *entry;
1028
1029 vm->bulk_moveable = false;
1030
1031 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, start, cursor, entry)
1032 amdgpu_vm_free_table(entry);
1033
1034 if (start)
1035 amdgpu_vm_free_table(start->entry);
1036}
1037
1038/**
1039 * amdgpu_vm_check_compute_bug - check whether asic has compute vm bug
1040 *
1041 * @adev: amdgpu_device pointer
1042 */
1043void amdgpu_vm_check_compute_bug(struct amdgpu_device *adev)
1044{
1045 const struct amdgpu_ip_block *ip_block;
1046 bool has_compute_vm_bug;
1047 struct amdgpu_ring *ring;
1048 int i;
1049
1050 has_compute_vm_bug = false;
1051
1052 ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX);
1053 if (ip_block) {
1054 /* Compute has a VM bug for GFX version < 7.
1055 Compute has a VM bug for GFX 8 MEC firmware version < 673.*/
1056 if (ip_block->version->major <= 7)
1057 has_compute_vm_bug = true;
1058 else if (ip_block->version->major == 8)
1059 if (adev->gfx.mec_fw_version < 673)
1060 has_compute_vm_bug = true;
1061 }
1062
1063 for (i = 0; i < adev->num_rings; i++) {
1064 ring = adev->rings[i];
1065 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
1066 /* only compute rings */
1067 ring->has_compute_vm_bug = has_compute_vm_bug;
1068 else
1069 ring->has_compute_vm_bug = false;
1070 }
1071}
1072
1073/**
1074 * amdgpu_vm_need_pipeline_sync - Check if pipe sync is needed for job.
1075 *
1076 * @ring: ring on which the job will be submitted
1077 * @job: job to submit
1078 *
1079 * Returns:
1080 * True if sync is needed.
1081 */
1082bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
1083 struct amdgpu_job *job)
1084{
1085 struct amdgpu_device *adev = ring->adev;
1086 unsigned vmhub = ring->funcs->vmhub;
1087 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1088 struct amdgpu_vmid *id;
1089 bool gds_switch_needed;
1090 bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
1091
1092 if (job->vmid == 0)
1093 return false;
1094 id = &id_mgr->ids[job->vmid];
1095 gds_switch_needed = ring->funcs->emit_gds_switch && (
1096 id->gds_base != job->gds_base ||
1097 id->gds_size != job->gds_size ||
1098 id->gws_base != job->gws_base ||
1099 id->gws_size != job->gws_size ||
1100 id->oa_base != job->oa_base ||
1101 id->oa_size != job->oa_size);
1102
1103 if (amdgpu_vmid_had_gpu_reset(adev, id))
1104 return true;
1105
1106 return vm_flush_needed || gds_switch_needed;
1107}
1108
1109/**
1110 * amdgpu_vm_flush - hardware flush the vm
1111 *
1112 * @ring: ring to use for flush
1113 * @job: related job
1114 * @need_pipe_sync: is pipe sync needed
1115 *
1116 * Emit a VM flush when it is necessary.
1117 *
1118 * Returns:
1119 * 0 on success, errno otherwise.
1120 */
1121int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job,
1122 bool need_pipe_sync)
1123{
1124 struct amdgpu_device *adev = ring->adev;
1125 unsigned vmhub = ring->funcs->vmhub;
1126 struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
1127 struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
1128 bool gds_switch_needed = ring->funcs->emit_gds_switch && (
1129 id->gds_base != job->gds_base ||
1130 id->gds_size != job->gds_size ||
1131 id->gws_base != job->gws_base ||
1132 id->gws_size != job->gws_size ||
1133 id->oa_base != job->oa_base ||
1134 id->oa_size != job->oa_size);
1135 bool vm_flush_needed = job->vm_needs_flush;
1136 struct dma_fence *fence = NULL;
1137 bool pasid_mapping_needed = false;
1138 unsigned patch_offset = 0;
1139 bool update_spm_vmid_needed = (job->vm && (job->vm->reserved_vmid[vmhub] != NULL));
1140 int r;
1141
1142 if (update_spm_vmid_needed && adev->gfx.rlc.funcs->update_spm_vmid)
1143 adev->gfx.rlc.funcs->update_spm_vmid(adev, job->vmid);
1144
1145 if (amdgpu_vmid_had_gpu_reset(adev, id)) {
1146 gds_switch_needed = true;
1147 vm_flush_needed = true;
1148 pasid_mapping_needed = true;
1149 }
1150
1151 mutex_lock(&id_mgr->lock);
1152 if (id->pasid != job->pasid || !id->pasid_mapping ||
1153 !dma_fence_is_signaled(id->pasid_mapping))
1154 pasid_mapping_needed = true;
1155 mutex_unlock(&id_mgr->lock);
1156
1157 gds_switch_needed &= !!ring->funcs->emit_gds_switch;
1158 vm_flush_needed &= !!ring->funcs->emit_vm_flush &&
1159 job->vm_pd_addr != AMDGPU_BO_INVALID_OFFSET;
1160 pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping &&
1161 ring->funcs->emit_wreg;
1162
1163 if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync)
1164 return 0;
1165
1166 if (ring->funcs->init_cond_exec)
1167 patch_offset = amdgpu_ring_init_cond_exec(ring);
1168
1169 if (need_pipe_sync)
1170 amdgpu_ring_emit_pipeline_sync(ring);
1171
1172 if (vm_flush_needed) {
1173 trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
1174 amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
1175 }
1176
1177 if (pasid_mapping_needed)
1178 amdgpu_gmc_emit_pasid_mapping(ring, job->vmid, job->pasid);
1179
1180 if (vm_flush_needed || pasid_mapping_needed) {
1181 r = amdgpu_fence_emit(ring, &fence, 0);
1182 if (r)
1183 return r;
1184 }
1185
1186 if (vm_flush_needed) {
1187 mutex_lock(&id_mgr->lock);
1188 dma_fence_put(id->last_flush);
1189 id->last_flush = dma_fence_get(fence);
1190 id->current_gpu_reset_count =
1191 atomic_read(&adev->gpu_reset_counter);
1192 mutex_unlock(&id_mgr->lock);
1193 }
1194
1195 if (pasid_mapping_needed) {
1196 mutex_lock(&id_mgr->lock);
1197 id->pasid = job->pasid;
1198 dma_fence_put(id->pasid_mapping);
1199 id->pasid_mapping = dma_fence_get(fence);
1200 mutex_unlock(&id_mgr->lock);
1201 }
1202 dma_fence_put(fence);
1203
1204 if (ring->funcs->emit_gds_switch && gds_switch_needed) {
1205 id->gds_base = job->gds_base;
1206 id->gds_size = job->gds_size;
1207 id->gws_base = job->gws_base;
1208 id->gws_size = job->gws_size;
1209 id->oa_base = job->oa_base;
1210 id->oa_size = job->oa_size;
1211 amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
1212 job->gds_size, job->gws_base,
1213 job->gws_size, job->oa_base,
1214 job->oa_size);
1215 }
1216
1217 if (ring->funcs->patch_cond_exec)
1218 amdgpu_ring_patch_cond_exec(ring, patch_offset);
1219
1220 /* the double SWITCH_BUFFER here *cannot* be skipped by COND_EXEC */
1221 if (ring->funcs->emit_switch_buffer) {
1222 amdgpu_ring_emit_switch_buffer(ring);
1223 amdgpu_ring_emit_switch_buffer(ring);
1224 }
1225 return 0;
1226}
1227
1228/**
1229 * amdgpu_vm_bo_find - find the bo_va for a specific vm & bo
1230 *
1231 * @vm: requested vm
1232 * @bo: requested buffer object
1233 *
1234 * Find @bo inside the requested vm.
1235 * Search inside the @bos vm list for the requested vm
1236 * Returns the found bo_va or NULL if none is found
1237 *
1238 * Object has to be reserved!
1239 *
1240 * Returns:
1241 * Found bo_va or NULL.
1242 */
1243struct amdgpu_bo_va *amdgpu_vm_bo_find(struct amdgpu_vm *vm,
1244 struct amdgpu_bo *bo)
1245{
1246 struct amdgpu_vm_bo_base *base;
1247
1248 for (base = bo->vm_bo; base; base = base->next) {
1249 if (base->vm != vm)
1250 continue;
1251
1252 return container_of(base, struct amdgpu_bo_va, base);
1253 }
1254 return NULL;
1255}
1256
1257/**
1258 * amdgpu_vm_map_gart - Resolve gart mapping of addr
1259 *
1260 * @pages_addr: optional DMA address to use for lookup
1261 * @addr: the unmapped addr
1262 *
1263 * Look up the physical address of the page that the pte resolves
1264 * to.
1265 *
1266 * Returns:
1267 * The pointer for the page table entry.
1268 */
1269uint64_t amdgpu_vm_map_gart(const dma_addr_t *pages_addr, uint64_t addr)
1270{
1271 uint64_t result;
1272
1273 /* page table offset */
1274 result = pages_addr[addr >> PAGE_SHIFT];
1275
1276 /* in case cpu page size != gpu page size*/
1277 result |= addr & (~PAGE_MASK);
1278
1279 result &= 0xFFFFFFFFFFFFF000ULL;
1280
1281 return result;
1282}
1283
1284/**
1285 * amdgpu_vm_update_pde - update a single level in the hierarchy
1286 *
1287 * @params: parameters for the update
1288 * @vm: requested vm
1289 * @entry: entry to update
1290 *
1291 * Makes sure the requested entry in parent is up to date.
1292 */
1293static int amdgpu_vm_update_pde(struct amdgpu_vm_update_params *params,
1294 struct amdgpu_vm *vm,
1295 struct amdgpu_vm_bo_base *entry)
1296{
1297 struct amdgpu_vm_bo_base *parent = amdgpu_vm_pt_parent(entry);
1298 struct amdgpu_bo *bo = parent->bo, *pbo;
1299 uint64_t pde, pt, flags;
1300 unsigned level;
1301
1302 for (level = 0, pbo = bo->parent; pbo; ++level)
1303 pbo = pbo->parent;
1304
1305 level += params->adev->vm_manager.root_level;
1306 amdgpu_gmc_get_pde_for_bo(entry->bo, level, &pt, &flags);
1307 pde = (entry - to_amdgpu_bo_vm(parent->bo)->entries) * 8;
1308 return vm->update_funcs->update(params, to_amdgpu_bo_vm(bo), pde, pt,
1309 1, 0, flags);
1310}
1311
1312/**
1313 * amdgpu_vm_invalidate_pds - mark all PDs as invalid
1314 *
1315 * @adev: amdgpu_device pointer
1316 * @vm: related vm
1317 *
1318 * Mark all PD level as invalid after an error.
1319 */
1320static void amdgpu_vm_invalidate_pds(struct amdgpu_device *adev,
1321 struct amdgpu_vm *vm)
1322{
1323 struct amdgpu_vm_pt_cursor cursor;
1324 struct amdgpu_vm_bo_base *entry;
1325
1326 for_each_amdgpu_vm_pt_dfs_safe(adev, vm, NULL, cursor, entry)
1327 if (entry->bo && !entry->moved)
1328 amdgpu_vm_bo_relocated(entry);
1329}
1330
1331/**
1332 * amdgpu_vm_update_pdes - make sure that all directories are valid
1333 *
1334 * @adev: amdgpu_device pointer
1335 * @vm: requested vm
1336 * @immediate: submit immediately to the paging queue
1337 *
1338 * Makes sure all directories are up to date.
1339 *
1340 * Returns:
1341 * 0 for success, error for failure.
1342 */
1343int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
1344 struct amdgpu_vm *vm, bool immediate)
1345{
1346 struct amdgpu_vm_update_params params;
1347 int r;
1348
1349 if (list_empty(&vm->relocated))
1350 return 0;
1351
1352 memset(¶ms, 0, sizeof(params));
1353 params.adev = adev;
1354 params.vm = vm;
1355 params.immediate = immediate;
1356
1357 r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT);
1358 if (r)
1359 return r;
1360
1361 while (!list_empty(&vm->relocated)) {
1362 struct amdgpu_vm_bo_base *entry;
1363
1364 entry = list_first_entry(&vm->relocated,
1365 struct amdgpu_vm_bo_base,
1366 vm_status);
1367 amdgpu_vm_bo_idle(entry);
1368
1369 r = amdgpu_vm_update_pde(¶ms, vm, entry);
1370 if (r)
1371 goto error;
1372 }
1373
1374 r = vm->update_funcs->commit(¶ms, &vm->last_update);
1375 if (r)
1376 goto error;
1377 return 0;
1378
1379error:
1380 amdgpu_vm_invalidate_pds(adev, vm);
1381 return r;
1382}
1383
1384/*
1385 * amdgpu_vm_update_flags - figure out flags for PTE updates
1386 *
1387 * Make sure to set the right flags for the PTEs at the desired level.
1388 */
1389static void amdgpu_vm_update_flags(struct amdgpu_vm_update_params *params,
1390 struct amdgpu_bo_vm *pt, unsigned int level,
1391 uint64_t pe, uint64_t addr,
1392 unsigned int count, uint32_t incr,
1393 uint64_t flags)
1394
1395{
1396 if (level != AMDGPU_VM_PTB) {
1397 flags |= AMDGPU_PDE_PTE;
1398 amdgpu_gmc_get_vm_pde(params->adev, level, &addr, &flags);
1399
1400 } else if (params->adev->asic_type >= CHIP_VEGA10 &&
1401 !(flags & AMDGPU_PTE_VALID) &&
1402 !(flags & AMDGPU_PTE_PRT)) {
1403
1404 /* Workaround for fault priority problem on GMC9 */
1405 flags |= AMDGPU_PTE_EXECUTABLE;
1406 }
1407
1408 params->vm->update_funcs->update(params, pt, pe, addr, count, incr,
1409 flags);
1410}
1411
1412/**
1413 * amdgpu_vm_fragment - get fragment for PTEs
1414 *
1415 * @params: see amdgpu_vm_update_params definition
1416 * @start: first PTE to handle
1417 * @end: last PTE to handle
1418 * @flags: hw mapping flags
1419 * @frag: resulting fragment size
1420 * @frag_end: end of this fragment
1421 *
1422 * Returns the first possible fragment for the start and end address.
1423 */
1424static void amdgpu_vm_fragment(struct amdgpu_vm_update_params *params,
1425 uint64_t start, uint64_t end, uint64_t flags,
1426 unsigned int *frag, uint64_t *frag_end)
1427{
1428 /**
1429 * The MC L1 TLB supports variable sized pages, based on a fragment
1430 * field in the PTE. When this field is set to a non-zero value, page
1431 * granularity is increased from 4KB to (1 << (12 + frag)). The PTE
1432 * flags are considered valid for all PTEs within the fragment range
1433 * and corresponding mappings are assumed to be physically contiguous.
1434 *
1435 * The L1 TLB can store a single PTE for the whole fragment,
1436 * significantly increasing the space available for translation
1437 * caching. This leads to large improvements in throughput when the
1438 * TLB is under pressure.
1439 *
1440 * The L2 TLB distributes small and large fragments into two
1441 * asymmetric partitions. The large fragment cache is significantly
1442 * larger. Thus, we try to use large fragments wherever possible.
1443 * Userspace can support this by aligning virtual base address and
1444 * allocation size to the fragment size.
1445 *
1446 * Starting with Vega10 the fragment size only controls the L1. The L2
1447 * is now directly feed with small/huge/giant pages from the walker.
1448 */
1449 unsigned max_frag;
1450
1451 if (params->adev->asic_type < CHIP_VEGA10)
1452 max_frag = params->adev->vm_manager.fragment_size;
1453 else
1454 max_frag = 31;
1455
1456 /* system pages are non continuously */
1457 if (params->pages_addr) {
1458 *frag = 0;
1459 *frag_end = end;
1460 return;
1461 }
1462
1463 /* This intentionally wraps around if no bit is set */
1464 *frag = min((unsigned)ffs(start) - 1, (unsigned)fls64(end - start) - 1);
1465 if (*frag >= max_frag) {
1466 *frag = max_frag;
1467 *frag_end = end & ~((1ULL << max_frag) - 1);
1468 } else {
1469 *frag_end = start + (1 << *frag);
1470 }
1471}
1472
1473/**
1474 * amdgpu_vm_update_ptes - make sure that page tables are valid
1475 *
1476 * @params: see amdgpu_vm_update_params definition
1477 * @start: start of GPU address range
1478 * @end: end of GPU address range
1479 * @dst: destination address to map to, the next dst inside the function
1480 * @flags: mapping flags
1481 *
1482 * Update the page tables in the range @start - @end.
1483 *
1484 * Returns:
1485 * 0 for success, -EINVAL for failure.
1486 */
1487static int amdgpu_vm_update_ptes(struct amdgpu_vm_update_params *params,
1488 uint64_t start, uint64_t end,
1489 uint64_t dst, uint64_t flags)
1490{
1491 struct amdgpu_device *adev = params->adev;
1492 struct amdgpu_vm_pt_cursor cursor;
1493 uint64_t frag_start = start, frag_end;
1494 unsigned int frag;
1495 int r;
1496
1497 /* figure out the initial fragment */
1498 amdgpu_vm_fragment(params, frag_start, end, flags, &frag, &frag_end);
1499
1500 /* walk over the address space and update the PTs */
1501 amdgpu_vm_pt_start(adev, params->vm, start, &cursor);
1502 while (cursor.pfn < end) {
1503 unsigned shift, parent_shift, mask;
1504 uint64_t incr, entry_end, pe_start;
1505 struct amdgpu_bo *pt;
1506
1507 if (!params->unlocked) {
1508 /* make sure that the page tables covering the
1509 * address range are actually allocated
1510 */
1511 r = amdgpu_vm_alloc_pts(params->adev, params->vm,
1512 &cursor, params->immediate);
1513 if (r)
1514 return r;
1515 }
1516
1517 shift = amdgpu_vm_level_shift(adev, cursor.level);
1518 parent_shift = amdgpu_vm_level_shift(adev, cursor.level - 1);
1519 if (params->unlocked) {
1520 /* Unlocked updates are only allowed on the leaves */
1521 if (amdgpu_vm_pt_descendant(adev, &cursor))
1522 continue;
1523 } else if (adev->asic_type < CHIP_VEGA10 &&
1524 (flags & AMDGPU_PTE_VALID)) {
1525 /* No huge page support before GMC v9 */
1526 if (cursor.level != AMDGPU_VM_PTB) {
1527 if (!amdgpu_vm_pt_descendant(adev, &cursor))
1528 return -ENOENT;
1529 continue;
1530 }
1531 } else if (frag < shift) {
1532 /* We can't use this level when the fragment size is
1533 * smaller than the address shift. Go to the next
1534 * child entry and try again.
1535 */
1536 if (amdgpu_vm_pt_descendant(adev, &cursor))
1537 continue;
1538 } else if (frag >= parent_shift) {
1539 /* If the fragment size is even larger than the parent
1540 * shift we should go up one level and check it again.
1541 */
1542 if (!amdgpu_vm_pt_ancestor(&cursor))
1543 return -EINVAL;
1544 continue;
1545 }
1546
1547 pt = cursor.entry->bo;
1548 if (!pt) {
1549 /* We need all PDs and PTs for mapping something, */
1550 if (flags & AMDGPU_PTE_VALID)
1551 return -ENOENT;
1552
1553 /* but unmapping something can happen at a higher
1554 * level.
1555 */
1556 if (!amdgpu_vm_pt_ancestor(&cursor))
1557 return -EINVAL;
1558
1559 pt = cursor.entry->bo;
1560 shift = parent_shift;
1561 frag_end = max(frag_end, ALIGN(frag_start + 1,
1562 1ULL << shift));
1563 }
1564
1565 /* Looks good so far, calculate parameters for the update */
1566 incr = (uint64_t)AMDGPU_GPU_PAGE_SIZE << shift;
1567 mask = amdgpu_vm_entries_mask(adev, cursor.level);
1568 pe_start = ((cursor.pfn >> shift) & mask) * 8;
1569 entry_end = ((uint64_t)mask + 1) << shift;
1570 entry_end += cursor.pfn & ~(entry_end - 1);
1571 entry_end = min(entry_end, end);
1572
1573 do {
1574 struct amdgpu_vm *vm = params->vm;
1575 uint64_t upd_end = min(entry_end, frag_end);
1576 unsigned nptes = (upd_end - frag_start) >> shift;
1577 uint64_t upd_flags = flags | AMDGPU_PTE_FRAG(frag);
1578
1579 /* This can happen when we set higher level PDs to
1580 * silent to stop fault floods.
1581 */
1582 nptes = max(nptes, 1u);
1583
1584 trace_amdgpu_vm_update_ptes(params, frag_start, upd_end,
1585 nptes, dst, incr, upd_flags,
1586 vm->task_info.pid,
1587 vm->immediate.fence_context);
1588 amdgpu_vm_update_flags(params, to_amdgpu_bo_vm(pt),
1589 cursor.level, pe_start, dst,
1590 nptes, incr, upd_flags);
1591
1592 pe_start += nptes * 8;
1593 dst += nptes * incr;
1594
1595 frag_start = upd_end;
1596 if (frag_start >= frag_end) {
1597 /* figure out the next fragment */
1598 amdgpu_vm_fragment(params, frag_start, end,
1599 flags, &frag, &frag_end);
1600 if (frag < shift)
1601 break;
1602 }
1603 } while (frag_start < entry_end);
1604
1605 if (amdgpu_vm_pt_descendant(adev, &cursor)) {
1606 /* Free all child entries.
1607 * Update the tables with the flags and addresses and free up subsequent
1608 * tables in the case of huge pages or freed up areas.
1609 * This is the maximum you can free, because all other page tables are not
1610 * completely covered by the range and so potentially still in use.
1611 */
1612 while (cursor.pfn < frag_start) {
1613 /* Make sure previous mapping is freed */
1614 if (cursor.entry->bo) {
1615 params->table_freed = true;
1616 amdgpu_vm_free_pts(adev, params->vm, &cursor);
1617 }
1618 amdgpu_vm_pt_next(adev, &cursor);
1619 }
1620
1621 } else if (frag >= shift) {
1622 /* or just move on to the next on the same level. */
1623 amdgpu_vm_pt_next(adev, &cursor);
1624 }
1625 }
1626
1627 return 0;
1628}
1629
1630/**
1631 * amdgpu_vm_bo_update_mapping - update a mapping in the vm page table
1632 *
1633 * @adev: amdgpu_device pointer of the VM
1634 * @bo_adev: amdgpu_device pointer of the mapped BO
1635 * @vm: requested vm
1636 * @immediate: immediate submission in a page fault
1637 * @unlocked: unlocked invalidation during MM callback
1638 * @resv: fences we need to sync to
1639 * @start: start of mapped range
1640 * @last: last mapped entry
1641 * @flags: flags for the entries
1642 * @offset: offset into nodes and pages_addr
1643 * @res: ttm_resource to map
1644 * @pages_addr: DMA addresses to use for mapping
1645 * @fence: optional resulting fence
1646 * @table_freed: return true if page table is freed
1647 *
1648 * Fill in the page table entries between @start and @last.
1649 *
1650 * Returns:
1651 * 0 for success, -EINVAL for failure.
1652 */
1653int amdgpu_vm_bo_update_mapping(struct amdgpu_device *adev,
1654 struct amdgpu_device *bo_adev,
1655 struct amdgpu_vm *vm, bool immediate,
1656 bool unlocked, struct dma_resv *resv,
1657 uint64_t start, uint64_t last,
1658 uint64_t flags, uint64_t offset,
1659 struct ttm_resource *res,
1660 dma_addr_t *pages_addr,
1661 struct dma_fence **fence,
1662 bool *table_freed)
1663{
1664 struct amdgpu_vm_update_params params;
1665 struct amdgpu_res_cursor cursor;
1666 enum amdgpu_sync_mode sync_mode;
1667 int r, idx;
1668
1669 if (!drm_dev_enter(&adev->ddev, &idx))
1670 return -ENODEV;
1671
1672 memset(¶ms, 0, sizeof(params));
1673 params.adev = adev;
1674 params.vm = vm;
1675 params.immediate = immediate;
1676 params.pages_addr = pages_addr;
1677 params.unlocked = unlocked;
1678
1679 /* Implicitly sync to command submissions in the same VM before
1680 * unmapping. Sync to moving fences before mapping.
1681 */
1682 if (!(flags & AMDGPU_PTE_VALID))
1683 sync_mode = AMDGPU_SYNC_EQ_OWNER;
1684 else
1685 sync_mode = AMDGPU_SYNC_EXPLICIT;
1686
1687 amdgpu_vm_eviction_lock(vm);
1688 if (vm->evicting) {
1689 r = -EBUSY;
1690 goto error_unlock;
1691 }
1692
1693 if (!unlocked && !dma_fence_is_signaled(vm->last_unlocked)) {
1694 struct dma_fence *tmp = dma_fence_get_stub();
1695
1696 amdgpu_bo_fence(vm->root.bo, vm->last_unlocked, true);
1697 swap(vm->last_unlocked, tmp);
1698 dma_fence_put(tmp);
1699 }
1700
1701 r = vm->update_funcs->prepare(¶ms, resv, sync_mode);
1702 if (r)
1703 goto error_unlock;
1704
1705 amdgpu_res_first(pages_addr ? NULL : res, offset,
1706 (last - start + 1) * AMDGPU_GPU_PAGE_SIZE, &cursor);
1707 while (cursor.remaining) {
1708 uint64_t tmp, num_entries, addr;
1709
1710 num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT;
1711 if (pages_addr) {
1712 bool contiguous = true;
1713
1714 if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) {
1715 uint64_t pfn = cursor.start >> PAGE_SHIFT;
1716 uint64_t count;
1717
1718 contiguous = pages_addr[pfn + 1] ==
1719 pages_addr[pfn] + PAGE_SIZE;
1720
1721 tmp = num_entries /
1722 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1723 for (count = 2; count < tmp; ++count) {
1724 uint64_t idx = pfn + count;
1725
1726 if (contiguous != (pages_addr[idx] ==
1727 pages_addr[idx - 1] + PAGE_SIZE))
1728 break;
1729 }
1730 num_entries = count *
1731 AMDGPU_GPU_PAGES_IN_CPU_PAGE;
1732 }
1733
1734 if (!contiguous) {
1735 addr = cursor.start;
1736 params.pages_addr = pages_addr;
1737 } else {
1738 addr = pages_addr[cursor.start >> PAGE_SHIFT];
1739 params.pages_addr = NULL;
1740 }
1741
1742 } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT)) {
1743 addr = bo_adev->vm_manager.vram_base_offset +
1744 cursor.start;
1745 } else {
1746 addr = 0;
1747 }
1748
1749 tmp = start + num_entries;
1750 r = amdgpu_vm_update_ptes(¶ms, start, tmp, addr, flags);
1751 if (r)
1752 goto error_unlock;
1753
1754 amdgpu_res_next(&cursor, num_entries * AMDGPU_GPU_PAGE_SIZE);
1755 start = tmp;
1756 }
1757
1758 r = vm->update_funcs->commit(¶ms, fence);
1759
1760 if (table_freed)
1761 *table_freed = params.table_freed;
1762
1763error_unlock:
1764 amdgpu_vm_eviction_unlock(vm);
1765 drm_dev_exit(idx);
1766 return r;
1767}
1768
1769void amdgpu_vm_get_memory(struct amdgpu_vm *vm, uint64_t *vram_mem,
1770 uint64_t *gtt_mem, uint64_t *cpu_mem)
1771{
1772 struct amdgpu_bo_va *bo_va, *tmp;
1773
1774 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
1775 if (!bo_va->base.bo)
1776 continue;
1777 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1778 gtt_mem, cpu_mem);
1779 }
1780 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
1781 if (!bo_va->base.bo)
1782 continue;
1783 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1784 gtt_mem, cpu_mem);
1785 }
1786 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
1787 if (!bo_va->base.bo)
1788 continue;
1789 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1790 gtt_mem, cpu_mem);
1791 }
1792 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
1793 if (!bo_va->base.bo)
1794 continue;
1795 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1796 gtt_mem, cpu_mem);
1797 }
1798 spin_lock(&vm->invalidated_lock);
1799 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
1800 if (!bo_va->base.bo)
1801 continue;
1802 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1803 gtt_mem, cpu_mem);
1804 }
1805 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
1806 if (!bo_va->base.bo)
1807 continue;
1808 amdgpu_bo_get_memory(bo_va->base.bo, vram_mem,
1809 gtt_mem, cpu_mem);
1810 }
1811 spin_unlock(&vm->invalidated_lock);
1812}
1813/**
1814 * amdgpu_vm_bo_update - update all BO mappings in the vm page table
1815 *
1816 * @adev: amdgpu_device pointer
1817 * @bo_va: requested BO and VM object
1818 * @clear: if true clear the entries
1819 *
1820 * Fill in the page table entries for @bo_va.
1821 *
1822 * Returns:
1823 * 0 for success, -EINVAL for failure.
1824 */
1825int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va,
1826 bool clear)
1827{
1828 struct amdgpu_bo *bo = bo_va->base.bo;
1829 struct amdgpu_vm *vm = bo_va->base.vm;
1830 struct amdgpu_bo_va_mapping *mapping;
1831 dma_addr_t *pages_addr = NULL;
1832 struct ttm_resource *mem;
1833 struct dma_fence **last_update;
1834 struct dma_resv *resv;
1835 uint64_t flags;
1836 struct amdgpu_device *bo_adev = adev;
1837 int r;
1838
1839 if (clear || !bo) {
1840 mem = NULL;
1841 resv = vm->root.bo->tbo.base.resv;
1842 } else {
1843 struct drm_gem_object *obj = &bo->tbo.base;
1844
1845 resv = bo->tbo.base.resv;
1846 if (obj->import_attach && bo_va->is_xgmi) {
1847 struct dma_buf *dma_buf = obj->import_attach->dmabuf;
1848 struct drm_gem_object *gobj = dma_buf->priv;
1849 struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj);
1850
1851 if (abo->tbo.resource->mem_type == TTM_PL_VRAM)
1852 bo = gem_to_amdgpu_bo(gobj);
1853 }
1854 mem = bo->tbo.resource;
1855 if (mem->mem_type == TTM_PL_TT ||
1856 mem->mem_type == AMDGPU_PL_PREEMPT)
1857 pages_addr = bo->tbo.ttm->dma_address;
1858 }
1859
1860 if (bo) {
1861 flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem);
1862
1863 if (amdgpu_bo_encrypted(bo))
1864 flags |= AMDGPU_PTE_TMZ;
1865
1866 bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1867 } else {
1868 flags = 0x0;
1869 }
1870
1871 if (clear || (bo && bo->tbo.base.resv ==
1872 vm->root.bo->tbo.base.resv))
1873 last_update = &vm->last_update;
1874 else
1875 last_update = &bo_va->last_pt_update;
1876
1877 if (!clear && bo_va->base.moved) {
1878 bo_va->base.moved = false;
1879 list_splice_init(&bo_va->valids, &bo_va->invalids);
1880
1881 } else if (bo_va->cleared != clear) {
1882 list_splice_init(&bo_va->valids, &bo_va->invalids);
1883 }
1884
1885 list_for_each_entry(mapping, &bo_va->invalids, list) {
1886 uint64_t update_flags = flags;
1887
1888 /* normally,bo_va->flags only contians READABLE and WIRTEABLE bit go here
1889 * but in case of something, we filter the flags in first place
1890 */
1891 if (!(mapping->flags & AMDGPU_PTE_READABLE))
1892 update_flags &= ~AMDGPU_PTE_READABLE;
1893 if (!(mapping->flags & AMDGPU_PTE_WRITEABLE))
1894 update_flags &= ~AMDGPU_PTE_WRITEABLE;
1895
1896 /* Apply ASIC specific mapping flags */
1897 amdgpu_gmc_get_vm_pte(adev, mapping, &update_flags);
1898
1899 trace_amdgpu_vm_bo_update(mapping);
1900
1901 r = amdgpu_vm_bo_update_mapping(adev, bo_adev, vm, false, false,
1902 resv, mapping->start,
1903 mapping->last, update_flags,
1904 mapping->offset, mem,
1905 pages_addr, last_update, NULL);
1906 if (r)
1907 return r;
1908 }
1909
1910 /* If the BO is not in its preferred location add it back to
1911 * the evicted list so that it gets validated again on the
1912 * next command submission.
1913 */
1914 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
1915 uint32_t mem_type = bo->tbo.resource->mem_type;
1916
1917 if (!(bo->preferred_domains &
1918 amdgpu_mem_type_to_domain(mem_type)))
1919 amdgpu_vm_bo_evicted(&bo_va->base);
1920 else
1921 amdgpu_vm_bo_idle(&bo_va->base);
1922 } else {
1923 amdgpu_vm_bo_done(&bo_va->base);
1924 }
1925
1926 list_splice_init(&bo_va->invalids, &bo_va->valids);
1927 bo_va->cleared = clear;
1928
1929 if (trace_amdgpu_vm_bo_mapping_enabled()) {
1930 list_for_each_entry(mapping, &bo_va->valids, list)
1931 trace_amdgpu_vm_bo_mapping(mapping);
1932 }
1933
1934 return 0;
1935}
1936
1937/**
1938 * amdgpu_vm_update_prt_state - update the global PRT state
1939 *
1940 * @adev: amdgpu_device pointer
1941 */
1942static void amdgpu_vm_update_prt_state(struct amdgpu_device *adev)
1943{
1944 unsigned long flags;
1945 bool enable;
1946
1947 spin_lock_irqsave(&adev->vm_manager.prt_lock, flags);
1948 enable = !!atomic_read(&adev->vm_manager.num_prt_users);
1949 adev->gmc.gmc_funcs->set_prt(adev, enable);
1950 spin_unlock_irqrestore(&adev->vm_manager.prt_lock, flags);
1951}
1952
1953/**
1954 * amdgpu_vm_prt_get - add a PRT user
1955 *
1956 * @adev: amdgpu_device pointer
1957 */
1958static void amdgpu_vm_prt_get(struct amdgpu_device *adev)
1959{
1960 if (!adev->gmc.gmc_funcs->set_prt)
1961 return;
1962
1963 if (atomic_inc_return(&adev->vm_manager.num_prt_users) == 1)
1964 amdgpu_vm_update_prt_state(adev);
1965}
1966
1967/**
1968 * amdgpu_vm_prt_put - drop a PRT user
1969 *
1970 * @adev: amdgpu_device pointer
1971 */
1972static void amdgpu_vm_prt_put(struct amdgpu_device *adev)
1973{
1974 if (atomic_dec_return(&adev->vm_manager.num_prt_users) == 0)
1975 amdgpu_vm_update_prt_state(adev);
1976}
1977
1978/**
1979 * amdgpu_vm_prt_cb - callback for updating the PRT status
1980 *
1981 * @fence: fence for the callback
1982 * @_cb: the callback function
1983 */
1984static void amdgpu_vm_prt_cb(struct dma_fence *fence, struct dma_fence_cb *_cb)
1985{
1986 struct amdgpu_prt_cb *cb = container_of(_cb, struct amdgpu_prt_cb, cb);
1987
1988 amdgpu_vm_prt_put(cb->adev);
1989 kfree(cb);
1990}
1991
1992/**
1993 * amdgpu_vm_add_prt_cb - add callback for updating the PRT status
1994 *
1995 * @adev: amdgpu_device pointer
1996 * @fence: fence for the callback
1997 */
1998static void amdgpu_vm_add_prt_cb(struct amdgpu_device *adev,
1999 struct dma_fence *fence)
2000{
2001 struct amdgpu_prt_cb *cb;
2002
2003 if (!adev->gmc.gmc_funcs->set_prt)
2004 return;
2005
2006 cb = kmalloc(sizeof(struct amdgpu_prt_cb), GFP_KERNEL);
2007 if (!cb) {
2008 /* Last resort when we are OOM */
2009 if (fence)
2010 dma_fence_wait(fence, false);
2011
2012 amdgpu_vm_prt_put(adev);
2013 } else {
2014 cb->adev = adev;
2015 if (!fence || dma_fence_add_callback(fence, &cb->cb,
2016 amdgpu_vm_prt_cb))
2017 amdgpu_vm_prt_cb(fence, &cb->cb);
2018 }
2019}
2020
2021/**
2022 * amdgpu_vm_free_mapping - free a mapping
2023 *
2024 * @adev: amdgpu_device pointer
2025 * @vm: requested vm
2026 * @mapping: mapping to be freed
2027 * @fence: fence of the unmap operation
2028 *
2029 * Free a mapping and make sure we decrease the PRT usage count if applicable.
2030 */
2031static void amdgpu_vm_free_mapping(struct amdgpu_device *adev,
2032 struct amdgpu_vm *vm,
2033 struct amdgpu_bo_va_mapping *mapping,
2034 struct dma_fence *fence)
2035{
2036 if (mapping->flags & AMDGPU_PTE_PRT)
2037 amdgpu_vm_add_prt_cb(adev, fence);
2038 kfree(mapping);
2039}
2040
2041/**
2042 * amdgpu_vm_prt_fini - finish all prt mappings
2043 *
2044 * @adev: amdgpu_device pointer
2045 * @vm: requested vm
2046 *
2047 * Register a cleanup callback to disable PRT support after VM dies.
2048 */
2049static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
2050{
2051 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
2052 struct dma_fence *excl, **shared;
2053 unsigned i, shared_count;
2054 int r;
2055
2056 r = dma_resv_get_fences(resv, &excl, &shared_count, &shared);
2057 if (r) {
2058 /* Not enough memory to grab the fence list, as last resort
2059 * block for all the fences to complete.
2060 */
2061 dma_resv_wait_timeout(resv, true, false,
2062 MAX_SCHEDULE_TIMEOUT);
2063 return;
2064 }
2065
2066 /* Add a callback for each fence in the reservation object */
2067 amdgpu_vm_prt_get(adev);
2068 amdgpu_vm_add_prt_cb(adev, excl);
2069
2070 for (i = 0; i < shared_count; ++i) {
2071 amdgpu_vm_prt_get(adev);
2072 amdgpu_vm_add_prt_cb(adev, shared[i]);
2073 }
2074
2075 kfree(shared);
2076}
2077
2078/**
2079 * amdgpu_vm_clear_freed - clear freed BOs in the PT
2080 *
2081 * @adev: amdgpu_device pointer
2082 * @vm: requested vm
2083 * @fence: optional resulting fence (unchanged if no work needed to be done
2084 * or if an error occurred)
2085 *
2086 * Make sure all freed BOs are cleared in the PT.
2087 * PTs have to be reserved and mutex must be locked!
2088 *
2089 * Returns:
2090 * 0 for success.
2091 *
2092 */
2093int amdgpu_vm_clear_freed(struct amdgpu_device *adev,
2094 struct amdgpu_vm *vm,
2095 struct dma_fence **fence)
2096{
2097 struct dma_resv *resv = vm->root.bo->tbo.base.resv;
2098 struct amdgpu_bo_va_mapping *mapping;
2099 uint64_t init_pte_value = 0;
2100 struct dma_fence *f = NULL;
2101 int r;
2102
2103 while (!list_empty(&vm->freed)) {
2104 mapping = list_first_entry(&vm->freed,
2105 struct amdgpu_bo_va_mapping, list);
2106 list_del(&mapping->list);
2107
2108 if (vm->pte_support_ats &&
2109 mapping->start < AMDGPU_GMC_HOLE_START)
2110 init_pte_value = AMDGPU_PTE_DEFAULT_ATC;
2111
2112 r = amdgpu_vm_bo_update_mapping(adev, adev, vm, false, false,
2113 resv, mapping->start,
2114 mapping->last, init_pte_value,
2115 0, NULL, NULL, &f, NULL);
2116 amdgpu_vm_free_mapping(adev, vm, mapping, f);
2117 if (r) {
2118 dma_fence_put(f);
2119 return r;
2120 }
2121 }
2122
2123 if (fence && f) {
2124 dma_fence_put(*fence);
2125 *fence = f;
2126 } else {
2127 dma_fence_put(f);
2128 }
2129
2130 return 0;
2131
2132}
2133
2134/**
2135 * amdgpu_vm_handle_moved - handle moved BOs in the PT
2136 *
2137 * @adev: amdgpu_device pointer
2138 * @vm: requested vm
2139 *
2140 * Make sure all BOs which are moved are updated in the PTs.
2141 *
2142 * Returns:
2143 * 0 for success.
2144 *
2145 * PTs have to be reserved!
2146 */
2147int amdgpu_vm_handle_moved(struct amdgpu_device *adev,
2148 struct amdgpu_vm *vm)
2149{
2150 struct amdgpu_bo_va *bo_va, *tmp;
2151 struct dma_resv *resv;
2152 bool clear;
2153 int r;
2154
2155 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
2156 /* Per VM BOs never need to bo cleared in the page tables */
2157 r = amdgpu_vm_bo_update(adev, bo_va, false);
2158 if (r)
2159 return r;
2160 }
2161
2162 spin_lock(&vm->invalidated_lock);
2163 while (!list_empty(&vm->invalidated)) {
2164 bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va,
2165 base.vm_status);
2166 resv = bo_va->base.bo->tbo.base.resv;
2167 spin_unlock(&vm->invalidated_lock);
2168
2169 /* Try to reserve the BO to avoid clearing its ptes */
2170 if (!amdgpu_vm_debug && dma_resv_trylock(resv))
2171 clear = false;
2172 /* Somebody else is using the BO right now */
2173 else
2174 clear = true;
2175
2176 r = amdgpu_vm_bo_update(adev, bo_va, clear);
2177 if (r)
2178 return r;
2179
2180 if (!clear)
2181 dma_resv_unlock(resv);
2182 spin_lock(&vm->invalidated_lock);
2183 }
2184 spin_unlock(&vm->invalidated_lock);
2185
2186 return 0;
2187}
2188
2189/**
2190 * amdgpu_vm_bo_add - add a bo to a specific vm
2191 *
2192 * @adev: amdgpu_device pointer
2193 * @vm: requested vm
2194 * @bo: amdgpu buffer object
2195 *
2196 * Add @bo into the requested vm.
2197 * Add @bo to the list of bos associated with the vm
2198 *
2199 * Returns:
2200 * Newly added bo_va or NULL for failure
2201 *
2202 * Object has to be reserved!
2203 */
2204struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev,
2205 struct amdgpu_vm *vm,
2206 struct amdgpu_bo *bo)
2207{
2208 struct amdgpu_bo_va *bo_va;
2209
2210 bo_va = kzalloc(sizeof(struct amdgpu_bo_va), GFP_KERNEL);
2211 if (bo_va == NULL) {
2212 return NULL;
2213 }
2214 amdgpu_vm_bo_base_init(&bo_va->base, vm, bo);
2215
2216 bo_va->ref_count = 1;
2217 INIT_LIST_HEAD(&bo_va->valids);
2218 INIT_LIST_HEAD(&bo_va->invalids);
2219
2220 if (!bo)
2221 return bo_va;
2222
2223 if (amdgpu_dmabuf_is_xgmi_accessible(adev, bo)) {
2224 bo_va->is_xgmi = true;
2225 /* Power up XGMI if it can be potentially used */
2226 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MAX_VEGA20);
2227 }
2228
2229 return bo_va;
2230}
2231
2232
2233/**
2234 * amdgpu_vm_bo_insert_map - insert a new mapping
2235 *
2236 * @adev: amdgpu_device pointer
2237 * @bo_va: bo_va to store the address
2238 * @mapping: the mapping to insert
2239 *
2240 * Insert a new mapping into all structures.
2241 */
2242static void amdgpu_vm_bo_insert_map(struct amdgpu_device *adev,
2243 struct amdgpu_bo_va *bo_va,
2244 struct amdgpu_bo_va_mapping *mapping)
2245{
2246 struct amdgpu_vm *vm = bo_va->base.vm;
2247 struct amdgpu_bo *bo = bo_va->base.bo;
2248
2249 mapping->bo_va = bo_va;
2250 list_add(&mapping->list, &bo_va->invalids);
2251 amdgpu_vm_it_insert(mapping, &vm->va);
2252
2253 if (mapping->flags & AMDGPU_PTE_PRT)
2254 amdgpu_vm_prt_get(adev);
2255
2256 if (bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv &&
2257 !bo_va->base.moved) {
2258 list_move(&bo_va->base.vm_status, &vm->moved);
2259 }
2260 trace_amdgpu_vm_bo_map(bo_va, mapping);
2261}
2262
2263/**
2264 * amdgpu_vm_bo_map - map bo inside a vm
2265 *
2266 * @adev: amdgpu_device pointer
2267 * @bo_va: bo_va to store the address
2268 * @saddr: where to map the BO
2269 * @offset: requested offset in the BO
2270 * @size: BO size in bytes
2271 * @flags: attributes of pages (read/write/valid/etc.)
2272 *
2273 * Add a mapping of the BO at the specefied addr into the VM.
2274 *
2275 * Returns:
2276 * 0 for success, error for failure.
2277 *
2278 * Object has to be reserved and unreserved outside!
2279 */
2280int amdgpu_vm_bo_map(struct amdgpu_device *adev,
2281 struct amdgpu_bo_va *bo_va,
2282 uint64_t saddr, uint64_t offset,
2283 uint64_t size, uint64_t flags)
2284{
2285 struct amdgpu_bo_va_mapping *mapping, *tmp;
2286 struct amdgpu_bo *bo = bo_va->base.bo;
2287 struct amdgpu_vm *vm = bo_va->base.vm;
2288 uint64_t eaddr;
2289
2290 /* validate the parameters */
2291 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK ||
2292 size == 0 || size & ~PAGE_MASK)
2293 return -EINVAL;
2294
2295 /* make sure object fit at this offset */
2296 eaddr = saddr + size - 1;
2297 if (saddr >= eaddr ||
2298 (bo && offset + size > amdgpu_bo_size(bo)) ||
2299 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
2300 return -EINVAL;
2301
2302 saddr /= AMDGPU_GPU_PAGE_SIZE;
2303 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2304
2305 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2306 if (tmp) {
2307 /* bo and tmp overlap, invalid addr */
2308 dev_err(adev->dev, "bo %p va 0x%010Lx-0x%010Lx conflict with "
2309 "0x%010Lx-0x%010Lx\n", bo, saddr, eaddr,
2310 tmp->start, tmp->last + 1);
2311 return -EINVAL;
2312 }
2313
2314 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2315 if (!mapping)
2316 return -ENOMEM;
2317
2318 mapping->start = saddr;
2319 mapping->last = eaddr;
2320 mapping->offset = offset;
2321 mapping->flags = flags;
2322
2323 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2324
2325 return 0;
2326}
2327
2328/**
2329 * amdgpu_vm_bo_replace_map - map bo inside a vm, replacing existing mappings
2330 *
2331 * @adev: amdgpu_device pointer
2332 * @bo_va: bo_va to store the address
2333 * @saddr: where to map the BO
2334 * @offset: requested offset in the BO
2335 * @size: BO size in bytes
2336 * @flags: attributes of pages (read/write/valid/etc.)
2337 *
2338 * Add a mapping of the BO at the specefied addr into the VM. Replace existing
2339 * mappings as we do so.
2340 *
2341 * Returns:
2342 * 0 for success, error for failure.
2343 *
2344 * Object has to be reserved and unreserved outside!
2345 */
2346int amdgpu_vm_bo_replace_map(struct amdgpu_device *adev,
2347 struct amdgpu_bo_va *bo_va,
2348 uint64_t saddr, uint64_t offset,
2349 uint64_t size, uint64_t flags)
2350{
2351 struct amdgpu_bo_va_mapping *mapping;
2352 struct amdgpu_bo *bo = bo_va->base.bo;
2353 uint64_t eaddr;
2354 int r;
2355
2356 /* validate the parameters */
2357 if (saddr & ~PAGE_MASK || offset & ~PAGE_MASK ||
2358 size == 0 || size & ~PAGE_MASK)
2359 return -EINVAL;
2360
2361 /* make sure object fit at this offset */
2362 eaddr = saddr + size - 1;
2363 if (saddr >= eaddr ||
2364 (bo && offset + size > amdgpu_bo_size(bo)) ||
2365 (eaddr >= adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT))
2366 return -EINVAL;
2367
2368 /* Allocate all the needed memory */
2369 mapping = kmalloc(sizeof(*mapping), GFP_KERNEL);
2370 if (!mapping)
2371 return -ENOMEM;
2372
2373 r = amdgpu_vm_bo_clear_mappings(adev, bo_va->base.vm, saddr, size);
2374 if (r) {
2375 kfree(mapping);
2376 return r;
2377 }
2378
2379 saddr /= AMDGPU_GPU_PAGE_SIZE;
2380 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2381
2382 mapping->start = saddr;
2383 mapping->last = eaddr;
2384 mapping->offset = offset;
2385 mapping->flags = flags;
2386
2387 amdgpu_vm_bo_insert_map(adev, bo_va, mapping);
2388
2389 return 0;
2390}
2391
2392/**
2393 * amdgpu_vm_bo_unmap - remove bo mapping from vm
2394 *
2395 * @adev: amdgpu_device pointer
2396 * @bo_va: bo_va to remove the address from
2397 * @saddr: where to the BO is mapped
2398 *
2399 * Remove a mapping of the BO at the specefied addr from the VM.
2400 *
2401 * Returns:
2402 * 0 for success, error for failure.
2403 *
2404 * Object has to be reserved and unreserved outside!
2405 */
2406int amdgpu_vm_bo_unmap(struct amdgpu_device *adev,
2407 struct amdgpu_bo_va *bo_va,
2408 uint64_t saddr)
2409{
2410 struct amdgpu_bo_va_mapping *mapping;
2411 struct amdgpu_vm *vm = bo_va->base.vm;
2412 bool valid = true;
2413
2414 saddr /= AMDGPU_GPU_PAGE_SIZE;
2415
2416 list_for_each_entry(mapping, &bo_va->valids, list) {
2417 if (mapping->start == saddr)
2418 break;
2419 }
2420
2421 if (&mapping->list == &bo_va->valids) {
2422 valid = false;
2423
2424 list_for_each_entry(mapping, &bo_va->invalids, list) {
2425 if (mapping->start == saddr)
2426 break;
2427 }
2428
2429 if (&mapping->list == &bo_va->invalids)
2430 return -ENOENT;
2431 }
2432
2433 list_del(&mapping->list);
2434 amdgpu_vm_it_remove(mapping, &vm->va);
2435 mapping->bo_va = NULL;
2436 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2437
2438 if (valid)
2439 list_add(&mapping->list, &vm->freed);
2440 else
2441 amdgpu_vm_free_mapping(adev, vm, mapping,
2442 bo_va->last_pt_update);
2443
2444 return 0;
2445}
2446
2447/**
2448 * amdgpu_vm_bo_clear_mappings - remove all mappings in a specific range
2449 *
2450 * @adev: amdgpu_device pointer
2451 * @vm: VM structure to use
2452 * @saddr: start of the range
2453 * @size: size of the range
2454 *
2455 * Remove all mappings in a range, split them as appropriate.
2456 *
2457 * Returns:
2458 * 0 for success, error for failure.
2459 */
2460int amdgpu_vm_bo_clear_mappings(struct amdgpu_device *adev,
2461 struct amdgpu_vm *vm,
2462 uint64_t saddr, uint64_t size)
2463{
2464 struct amdgpu_bo_va_mapping *before, *after, *tmp, *next;
2465 LIST_HEAD(removed);
2466 uint64_t eaddr;
2467
2468 eaddr = saddr + size - 1;
2469 saddr /= AMDGPU_GPU_PAGE_SIZE;
2470 eaddr /= AMDGPU_GPU_PAGE_SIZE;
2471
2472 /* Allocate all the needed memory */
2473 before = kzalloc(sizeof(*before), GFP_KERNEL);
2474 if (!before)
2475 return -ENOMEM;
2476 INIT_LIST_HEAD(&before->list);
2477
2478 after = kzalloc(sizeof(*after), GFP_KERNEL);
2479 if (!after) {
2480 kfree(before);
2481 return -ENOMEM;
2482 }
2483 INIT_LIST_HEAD(&after->list);
2484
2485 /* Now gather all removed mappings */
2486 tmp = amdgpu_vm_it_iter_first(&vm->va, saddr, eaddr);
2487 while (tmp) {
2488 /* Remember mapping split at the start */
2489 if (tmp->start < saddr) {
2490 before->start = tmp->start;
2491 before->last = saddr - 1;
2492 before->offset = tmp->offset;
2493 before->flags = tmp->flags;
2494 before->bo_va = tmp->bo_va;
2495 list_add(&before->list, &tmp->bo_va->invalids);
2496 }
2497
2498 /* Remember mapping split at the end */
2499 if (tmp->last > eaddr) {
2500 after->start = eaddr + 1;
2501 after->last = tmp->last;
2502 after->offset = tmp->offset;
2503 after->offset += (after->start - tmp->start) << PAGE_SHIFT;
2504 after->flags = tmp->flags;
2505 after->bo_va = tmp->bo_va;
2506 list_add(&after->list, &tmp->bo_va->invalids);
2507 }
2508
2509 list_del(&tmp->list);
2510 list_add(&tmp->list, &removed);
2511
2512 tmp = amdgpu_vm_it_iter_next(tmp, saddr, eaddr);
2513 }
2514
2515 /* And free them up */
2516 list_for_each_entry_safe(tmp, next, &removed, list) {
2517 amdgpu_vm_it_remove(tmp, &vm->va);
2518 list_del(&tmp->list);
2519
2520 if (tmp->start < saddr)
2521 tmp->start = saddr;
2522 if (tmp->last > eaddr)
2523 tmp->last = eaddr;
2524
2525 tmp->bo_va = NULL;
2526 list_add(&tmp->list, &vm->freed);
2527 trace_amdgpu_vm_bo_unmap(NULL, tmp);
2528 }
2529
2530 /* Insert partial mapping before the range */
2531 if (!list_empty(&before->list)) {
2532 amdgpu_vm_it_insert(before, &vm->va);
2533 if (before->flags & AMDGPU_PTE_PRT)
2534 amdgpu_vm_prt_get(adev);
2535 } else {
2536 kfree(before);
2537 }
2538
2539 /* Insert partial mapping after the range */
2540 if (!list_empty(&after->list)) {
2541 amdgpu_vm_it_insert(after, &vm->va);
2542 if (after->flags & AMDGPU_PTE_PRT)
2543 amdgpu_vm_prt_get(adev);
2544 } else {
2545 kfree(after);
2546 }
2547
2548 return 0;
2549}
2550
2551/**
2552 * amdgpu_vm_bo_lookup_mapping - find mapping by address
2553 *
2554 * @vm: the requested VM
2555 * @addr: the address
2556 *
2557 * Find a mapping by it's address.
2558 *
2559 * Returns:
2560 * The amdgpu_bo_va_mapping matching for addr or NULL
2561 *
2562 */
2563struct amdgpu_bo_va_mapping *amdgpu_vm_bo_lookup_mapping(struct amdgpu_vm *vm,
2564 uint64_t addr)
2565{
2566 return amdgpu_vm_it_iter_first(&vm->va, addr, addr);
2567}
2568
2569/**
2570 * amdgpu_vm_bo_trace_cs - trace all reserved mappings
2571 *
2572 * @vm: the requested vm
2573 * @ticket: CS ticket
2574 *
2575 * Trace all mappings of BOs reserved during a command submission.
2576 */
2577void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket)
2578{
2579 struct amdgpu_bo_va_mapping *mapping;
2580
2581 if (!trace_amdgpu_vm_bo_cs_enabled())
2582 return;
2583
2584 for (mapping = amdgpu_vm_it_iter_first(&vm->va, 0, U64_MAX); mapping;
2585 mapping = amdgpu_vm_it_iter_next(mapping, 0, U64_MAX)) {
2586 if (mapping->bo_va && mapping->bo_va->base.bo) {
2587 struct amdgpu_bo *bo;
2588
2589 bo = mapping->bo_va->base.bo;
2590 if (dma_resv_locking_ctx(bo->tbo.base.resv) !=
2591 ticket)
2592 continue;
2593 }
2594
2595 trace_amdgpu_vm_bo_cs(mapping);
2596 }
2597}
2598
2599/**
2600 * amdgpu_vm_bo_rmv - remove a bo to a specific vm
2601 *
2602 * @adev: amdgpu_device pointer
2603 * @bo_va: requested bo_va
2604 *
2605 * Remove @bo_va->bo from the requested vm.
2606 *
2607 * Object have to be reserved!
2608 */
2609void amdgpu_vm_bo_rmv(struct amdgpu_device *adev,
2610 struct amdgpu_bo_va *bo_va)
2611{
2612 struct amdgpu_bo_va_mapping *mapping, *next;
2613 struct amdgpu_bo *bo = bo_va->base.bo;
2614 struct amdgpu_vm *vm = bo_va->base.vm;
2615 struct amdgpu_vm_bo_base **base;
2616
2617 if (bo) {
2618 if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
2619 vm->bulk_moveable = false;
2620
2621 for (base = &bo_va->base.bo->vm_bo; *base;
2622 base = &(*base)->next) {
2623 if (*base != &bo_va->base)
2624 continue;
2625
2626 *base = bo_va->base.next;
2627 break;
2628 }
2629 }
2630
2631 spin_lock(&vm->invalidated_lock);
2632 list_del(&bo_va->base.vm_status);
2633 spin_unlock(&vm->invalidated_lock);
2634
2635 list_for_each_entry_safe(mapping, next, &bo_va->valids, list) {
2636 list_del(&mapping->list);
2637 amdgpu_vm_it_remove(mapping, &vm->va);
2638 mapping->bo_va = NULL;
2639 trace_amdgpu_vm_bo_unmap(bo_va, mapping);
2640 list_add(&mapping->list, &vm->freed);
2641 }
2642 list_for_each_entry_safe(mapping, next, &bo_va->invalids, list) {
2643 list_del(&mapping->list);
2644 amdgpu_vm_it_remove(mapping, &vm->va);
2645 amdgpu_vm_free_mapping(adev, vm, mapping,
2646 bo_va->last_pt_update);
2647 }
2648
2649 dma_fence_put(bo_va->last_pt_update);
2650
2651 if (bo && bo_va->is_xgmi)
2652 amdgpu_xgmi_set_pstate(adev, AMDGPU_XGMI_PSTATE_MIN);
2653
2654 kfree(bo_va);
2655}
2656
2657/**
2658 * amdgpu_vm_evictable - check if we can evict a VM
2659 *
2660 * @bo: A page table of the VM.
2661 *
2662 * Check if it is possible to evict a VM.
2663 */
2664bool amdgpu_vm_evictable(struct amdgpu_bo *bo)
2665{
2666 struct amdgpu_vm_bo_base *bo_base = bo->vm_bo;
2667
2668 /* Page tables of a destroyed VM can go away immediately */
2669 if (!bo_base || !bo_base->vm)
2670 return true;
2671
2672 /* Don't evict VM page tables while they are busy */
2673 if (!dma_resv_test_signaled(bo->tbo.base.resv, true))
2674 return false;
2675
2676 /* Try to block ongoing updates */
2677 if (!amdgpu_vm_eviction_trylock(bo_base->vm))
2678 return false;
2679
2680 /* Don't evict VM page tables while they are updated */
2681 if (!dma_fence_is_signaled(bo_base->vm->last_unlocked)) {
2682 amdgpu_vm_eviction_unlock(bo_base->vm);
2683 return false;
2684 }
2685
2686 bo_base->vm->evicting = true;
2687 amdgpu_vm_eviction_unlock(bo_base->vm);
2688 return true;
2689}
2690
2691/**
2692 * amdgpu_vm_bo_invalidate - mark the bo as invalid
2693 *
2694 * @adev: amdgpu_device pointer
2695 * @bo: amdgpu buffer object
2696 * @evicted: is the BO evicted
2697 *
2698 * Mark @bo as invalid.
2699 */
2700void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev,
2701 struct amdgpu_bo *bo, bool evicted)
2702{
2703 struct amdgpu_vm_bo_base *bo_base;
2704
2705 /* shadow bo doesn't have bo base, its validation needs its parent */
2706 if (bo->parent && (amdgpu_bo_shadowed(bo->parent) == bo))
2707 bo = bo->parent;
2708
2709 for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
2710 struct amdgpu_vm *vm = bo_base->vm;
2711
2712 if (evicted && bo->tbo.base.resv == vm->root.bo->tbo.base.resv) {
2713 amdgpu_vm_bo_evicted(bo_base);
2714 continue;
2715 }
2716
2717 if (bo_base->moved)
2718 continue;
2719 bo_base->moved = true;
2720
2721 if (bo->tbo.type == ttm_bo_type_kernel)
2722 amdgpu_vm_bo_relocated(bo_base);
2723 else if (bo->tbo.base.resv == vm->root.bo->tbo.base.resv)
2724 amdgpu_vm_bo_moved(bo_base);
2725 else
2726 amdgpu_vm_bo_invalidated(bo_base);
2727 }
2728}
2729
2730/**
2731 * amdgpu_vm_get_block_size - calculate VM page table size as power of two
2732 *
2733 * @vm_size: VM size
2734 *
2735 * Returns:
2736 * VM page table as power of two
2737 */
2738static uint32_t amdgpu_vm_get_block_size(uint64_t vm_size)
2739{
2740 /* Total bits covered by PD + PTs */
2741 unsigned bits = ilog2(vm_size) + 18;
2742
2743 /* Make sure the PD is 4K in size up to 8GB address space.
2744 Above that split equal between PD and PTs */
2745 if (vm_size <= 8)
2746 return (bits - 9);
2747 else
2748 return ((bits + 3) / 2);
2749}
2750
2751/**
2752 * amdgpu_vm_adjust_size - adjust vm size, block size and fragment size
2753 *
2754 * @adev: amdgpu_device pointer
2755 * @min_vm_size: the minimum vm size in GB if it's set auto
2756 * @fragment_size_default: Default PTE fragment size
2757 * @max_level: max VMPT level
2758 * @max_bits: max address space size in bits
2759 *
2760 */
2761void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size,
2762 uint32_t fragment_size_default, unsigned max_level,
2763 unsigned max_bits)
2764{
2765 unsigned int max_size = 1 << (max_bits - 30);
2766 unsigned int vm_size;
2767 uint64_t tmp;
2768
2769 /* adjust vm size first */
2770 if (amdgpu_vm_size != -1) {
2771 vm_size = amdgpu_vm_size;
2772 if (vm_size > max_size) {
2773 dev_warn(adev->dev, "VM size (%d) too large, max is %u GB\n",
2774 amdgpu_vm_size, max_size);
2775 vm_size = max_size;
2776 }
2777 } else {
2778 struct sysinfo si;
2779 unsigned int phys_ram_gb;
2780
2781 /* Optimal VM size depends on the amount of physical
2782 * RAM available. Underlying requirements and
2783 * assumptions:
2784 *
2785 * - Need to map system memory and VRAM from all GPUs
2786 * - VRAM from other GPUs not known here
2787 * - Assume VRAM <= system memory
2788 * - On GFX8 and older, VM space can be segmented for
2789 * different MTYPEs
2790 * - Need to allow room for fragmentation, guard pages etc.
2791 *
2792 * This adds up to a rough guess of system memory x3.
2793 * Round up to power of two to maximize the available
2794 * VM size with the given page table size.
2795 */
2796 si_meminfo(&si);
2797 phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit +
2798 (1 << 30) - 1) >> 30;
2799 vm_size = roundup_pow_of_two(
2800 min(max(phys_ram_gb * 3, min_vm_size), max_size));
2801 }
2802
2803 adev->vm_manager.max_pfn = (uint64_t)vm_size << 18;
2804
2805 tmp = roundup_pow_of_two(adev->vm_manager.max_pfn);
2806 if (amdgpu_vm_block_size != -1)
2807 tmp >>= amdgpu_vm_block_size - 9;
2808 tmp = DIV_ROUND_UP(fls64(tmp) - 1, 9) - 1;
2809 adev->vm_manager.num_level = min(max_level, (unsigned)tmp);
2810 switch (adev->vm_manager.num_level) {
2811 case 3:
2812 adev->vm_manager.root_level = AMDGPU_VM_PDB2;
2813 break;
2814 case 2:
2815 adev->vm_manager.root_level = AMDGPU_VM_PDB1;
2816 break;
2817 case 1:
2818 adev->vm_manager.root_level = AMDGPU_VM_PDB0;
2819 break;
2820 default:
2821 dev_err(adev->dev, "VMPT only supports 2~4+1 levels\n");
2822 }
2823 /* block size depends on vm size and hw setup*/
2824 if (amdgpu_vm_block_size != -1)
2825 adev->vm_manager.block_size =
2826 min((unsigned)amdgpu_vm_block_size, max_bits
2827 - AMDGPU_GPU_PAGE_SHIFT
2828 - 9 * adev->vm_manager.num_level);
2829 else if (adev->vm_manager.num_level > 1)
2830 adev->vm_manager.block_size = 9;
2831 else
2832 adev->vm_manager.block_size = amdgpu_vm_get_block_size(tmp);
2833
2834 if (amdgpu_vm_fragment_size == -1)
2835 adev->vm_manager.fragment_size = fragment_size_default;
2836 else
2837 adev->vm_manager.fragment_size = amdgpu_vm_fragment_size;
2838
2839 DRM_INFO("vm size is %u GB, %u levels, block size is %u-bit, fragment size is %u-bit\n",
2840 vm_size, adev->vm_manager.num_level + 1,
2841 adev->vm_manager.block_size,
2842 adev->vm_manager.fragment_size);
2843}
2844
2845/**
2846 * amdgpu_vm_wait_idle - wait for the VM to become idle
2847 *
2848 * @vm: VM object to wait for
2849 * @timeout: timeout to wait for VM to become idle
2850 */
2851long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout)
2852{
2853 timeout = dma_resv_wait_timeout(vm->root.bo->tbo.base.resv, true,
2854 true, timeout);
2855 if (timeout <= 0)
2856 return timeout;
2857
2858 return dma_fence_wait_timeout(vm->last_unlocked, true, timeout);
2859}
2860
2861/**
2862 * amdgpu_vm_init - initialize a vm instance
2863 *
2864 * @adev: amdgpu_device pointer
2865 * @vm: requested vm
2866 * @pasid: Process address space identifier
2867 *
2868 * Init @vm fields.
2869 *
2870 * Returns:
2871 * 0 for success, error for failure.
2872 */
2873int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32 pasid)
2874{
2875 struct amdgpu_bo *root_bo;
2876 struct amdgpu_bo_vm *root;
2877 int r, i;
2878
2879 vm->va = RB_ROOT_CACHED;
2880 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
2881 vm->reserved_vmid[i] = NULL;
2882 INIT_LIST_HEAD(&vm->evicted);
2883 INIT_LIST_HEAD(&vm->relocated);
2884 INIT_LIST_HEAD(&vm->moved);
2885 INIT_LIST_HEAD(&vm->idle);
2886 INIT_LIST_HEAD(&vm->invalidated);
2887 spin_lock_init(&vm->invalidated_lock);
2888 INIT_LIST_HEAD(&vm->freed);
2889 INIT_LIST_HEAD(&vm->done);
2890
2891 /* create scheduler entities for page table updates */
2892 r = drm_sched_entity_init(&vm->immediate, DRM_SCHED_PRIORITY_NORMAL,
2893 adev->vm_manager.vm_pte_scheds,
2894 adev->vm_manager.vm_pte_num_scheds, NULL);
2895 if (r)
2896 return r;
2897
2898 r = drm_sched_entity_init(&vm->delayed, DRM_SCHED_PRIORITY_NORMAL,
2899 adev->vm_manager.vm_pte_scheds,
2900 adev->vm_manager.vm_pte_num_scheds, NULL);
2901 if (r)
2902 goto error_free_immediate;
2903
2904 vm->pte_support_ats = false;
2905 vm->is_compute_context = false;
2906
2907 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
2908 AMDGPU_VM_USE_CPU_FOR_GFX);
2909
2910 DRM_DEBUG_DRIVER("VM update mode is %s\n",
2911 vm->use_cpu_for_update ? "CPU" : "SDMA");
2912 WARN_ONCE((vm->use_cpu_for_update &&
2913 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
2914 "CPU update of VM recommended only for large BAR system\n");
2915
2916 if (vm->use_cpu_for_update)
2917 vm->update_funcs = &amdgpu_vm_cpu_funcs;
2918 else
2919 vm->update_funcs = &amdgpu_vm_sdma_funcs;
2920 vm->last_update = NULL;
2921 vm->last_unlocked = dma_fence_get_stub();
2922
2923 mutex_init(&vm->eviction_lock);
2924 vm->evicting = false;
2925
2926 r = amdgpu_vm_pt_create(adev, vm, adev->vm_manager.root_level,
2927 false, &root);
2928 if (r)
2929 goto error_free_delayed;
2930 root_bo = &root->bo;
2931 r = amdgpu_bo_reserve(root_bo, true);
2932 if (r)
2933 goto error_free_root;
2934
2935 r = dma_resv_reserve_shared(root_bo->tbo.base.resv, 1);
2936 if (r)
2937 goto error_unreserve;
2938
2939 amdgpu_vm_bo_base_init(&vm->root, vm, root_bo);
2940
2941 r = amdgpu_vm_clear_bo(adev, vm, root, false);
2942 if (r)
2943 goto error_unreserve;
2944
2945 amdgpu_bo_unreserve(vm->root.bo);
2946
2947 if (pasid) {
2948 unsigned long flags;
2949
2950 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
2951 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
2952 GFP_ATOMIC);
2953 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
2954 if (r < 0)
2955 goto error_free_root;
2956
2957 vm->pasid = pasid;
2958 }
2959
2960 INIT_KFIFO(vm->faults);
2961
2962 return 0;
2963
2964error_unreserve:
2965 amdgpu_bo_unreserve(vm->root.bo);
2966
2967error_free_root:
2968 amdgpu_bo_unref(&root->shadow);
2969 amdgpu_bo_unref(&root_bo);
2970 vm->root.bo = NULL;
2971
2972error_free_delayed:
2973 dma_fence_put(vm->last_unlocked);
2974 drm_sched_entity_destroy(&vm->delayed);
2975
2976error_free_immediate:
2977 drm_sched_entity_destroy(&vm->immediate);
2978
2979 return r;
2980}
2981
2982/**
2983 * amdgpu_vm_check_clean_reserved - check if a VM is clean
2984 *
2985 * @adev: amdgpu_device pointer
2986 * @vm: the VM to check
2987 *
2988 * check all entries of the root PD, if any subsequent PDs are allocated,
2989 * it means there are page table creating and filling, and is no a clean
2990 * VM
2991 *
2992 * Returns:
2993 * 0 if this VM is clean
2994 */
2995static int amdgpu_vm_check_clean_reserved(struct amdgpu_device *adev,
2996 struct amdgpu_vm *vm)
2997{
2998 enum amdgpu_vm_level root = adev->vm_manager.root_level;
2999 unsigned int entries = amdgpu_vm_num_entries(adev, root);
3000 unsigned int i = 0;
3001
3002 for (i = 0; i < entries; i++) {
3003 if (to_amdgpu_bo_vm(vm->root.bo)->entries[i].bo)
3004 return -EINVAL;
3005 }
3006
3007 return 0;
3008}
3009
3010/**
3011 * amdgpu_vm_make_compute - Turn a GFX VM into a compute VM
3012 *
3013 * @adev: amdgpu_device pointer
3014 * @vm: requested vm
3015 * @pasid: pasid to use
3016 *
3017 * This only works on GFX VMs that don't have any BOs added and no
3018 * page tables allocated yet.
3019 *
3020 * Changes the following VM parameters:
3021 * - use_cpu_for_update
3022 * - pte_supports_ats
3023 * - pasid (old PASID is released, because compute manages its own PASIDs)
3024 *
3025 * Reinitializes the page directory to reflect the changed ATS
3026 * setting.
3027 *
3028 * Returns:
3029 * 0 for success, -errno for errors.
3030 */
3031int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm,
3032 u32 pasid)
3033{
3034 bool pte_support_ats = (adev->asic_type == CHIP_RAVEN);
3035 int r;
3036
3037 r = amdgpu_bo_reserve(vm->root.bo, true);
3038 if (r)
3039 return r;
3040
3041 /* Sanity checks */
3042 r = amdgpu_vm_check_clean_reserved(adev, vm);
3043 if (r)
3044 goto unreserve_bo;
3045
3046 if (pasid) {
3047 unsigned long flags;
3048
3049 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3050 r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1,
3051 GFP_ATOMIC);
3052 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3053
3054 if (r == -ENOSPC)
3055 goto unreserve_bo;
3056 r = 0;
3057 }
3058
3059 /* Check if PD needs to be reinitialized and do it before
3060 * changing any other state, in case it fails.
3061 */
3062 if (pte_support_ats != vm->pte_support_ats) {
3063 vm->pte_support_ats = pte_support_ats;
3064 r = amdgpu_vm_clear_bo(adev, vm,
3065 to_amdgpu_bo_vm(vm->root.bo),
3066 false);
3067 if (r)
3068 goto free_idr;
3069 }
3070
3071 /* Update VM state */
3072 vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode &
3073 AMDGPU_VM_USE_CPU_FOR_COMPUTE);
3074 DRM_DEBUG_DRIVER("VM update mode is %s\n",
3075 vm->use_cpu_for_update ? "CPU" : "SDMA");
3076 WARN_ONCE((vm->use_cpu_for_update &&
3077 !amdgpu_gmc_vram_full_visible(&adev->gmc)),
3078 "CPU update of VM recommended only for large BAR system\n");
3079
3080 if (vm->use_cpu_for_update) {
3081 /* Sync with last SDMA update/clear before switching to CPU */
3082 r = amdgpu_bo_sync_wait(vm->root.bo,
3083 AMDGPU_FENCE_OWNER_UNDEFINED, true);
3084 if (r)
3085 goto free_idr;
3086
3087 vm->update_funcs = &amdgpu_vm_cpu_funcs;
3088 } else {
3089 vm->update_funcs = &amdgpu_vm_sdma_funcs;
3090 }
3091 dma_fence_put(vm->last_update);
3092 vm->last_update = NULL;
3093 vm->is_compute_context = true;
3094
3095 if (vm->pasid) {
3096 unsigned long flags;
3097
3098 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3099 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3100 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3101
3102 /* Free the original amdgpu allocated pasid
3103 * Will be replaced with kfd allocated pasid
3104 */
3105 amdgpu_pasid_free(vm->pasid);
3106 vm->pasid = 0;
3107 }
3108
3109 /* Free the shadow bo for compute VM */
3110 amdgpu_bo_unref(&to_amdgpu_bo_vm(vm->root.bo)->shadow);
3111
3112 if (pasid)
3113 vm->pasid = pasid;
3114
3115 goto unreserve_bo;
3116
3117free_idr:
3118 if (pasid) {
3119 unsigned long flags;
3120
3121 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3122 idr_remove(&adev->vm_manager.pasid_idr, pasid);
3123 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3124 }
3125unreserve_bo:
3126 amdgpu_bo_unreserve(vm->root.bo);
3127 return r;
3128}
3129
3130/**
3131 * amdgpu_vm_release_compute - release a compute vm
3132 * @adev: amdgpu_device pointer
3133 * @vm: a vm turned into compute vm by calling amdgpu_vm_make_compute
3134 *
3135 * This is a correspondant of amdgpu_vm_make_compute. It decouples compute
3136 * pasid from vm. Compute should stop use of vm after this call.
3137 */
3138void amdgpu_vm_release_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm)
3139{
3140 if (vm->pasid) {
3141 unsigned long flags;
3142
3143 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3144 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3145 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3146 }
3147 vm->pasid = 0;
3148 vm->is_compute_context = false;
3149}
3150
3151/**
3152 * amdgpu_vm_fini - tear down a vm instance
3153 *
3154 * @adev: amdgpu_device pointer
3155 * @vm: requested vm
3156 *
3157 * Tear down @vm.
3158 * Unbind the VM and remove all bos from the vm bo list
3159 */
3160void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm)
3161{
3162 struct amdgpu_bo_va_mapping *mapping, *tmp;
3163 bool prt_fini_needed = !!adev->gmc.gmc_funcs->set_prt;
3164 struct amdgpu_bo *root;
3165 int i;
3166
3167 amdgpu_amdkfd_gpuvm_destroy_cb(adev, vm);
3168
3169 root = amdgpu_bo_ref(vm->root.bo);
3170 amdgpu_bo_reserve(root, true);
3171 if (vm->pasid) {
3172 unsigned long flags;
3173
3174 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3175 idr_remove(&adev->vm_manager.pasid_idr, vm->pasid);
3176 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3177 vm->pasid = 0;
3178 }
3179
3180 dma_fence_wait(vm->last_unlocked, false);
3181 dma_fence_put(vm->last_unlocked);
3182
3183 list_for_each_entry_safe(mapping, tmp, &vm->freed, list) {
3184 if (mapping->flags & AMDGPU_PTE_PRT && prt_fini_needed) {
3185 amdgpu_vm_prt_fini(adev, vm);
3186 prt_fini_needed = false;
3187 }
3188
3189 list_del(&mapping->list);
3190 amdgpu_vm_free_mapping(adev, vm, mapping, NULL);
3191 }
3192
3193 amdgpu_vm_free_pts(adev, vm, NULL);
3194 amdgpu_bo_unreserve(root);
3195 amdgpu_bo_unref(&root);
3196 WARN_ON(vm->root.bo);
3197
3198 drm_sched_entity_destroy(&vm->immediate);
3199 drm_sched_entity_destroy(&vm->delayed);
3200
3201 if (!RB_EMPTY_ROOT(&vm->va.rb_root)) {
3202 dev_err(adev->dev, "still active bo inside vm\n");
3203 }
3204 rbtree_postorder_for_each_entry_safe(mapping, tmp,
3205 &vm->va.rb_root, rb) {
3206 /* Don't remove the mapping here, we don't want to trigger a
3207 * rebalance and the tree is about to be destroyed anyway.
3208 */
3209 list_del(&mapping->list);
3210 kfree(mapping);
3211 }
3212
3213 dma_fence_put(vm->last_update);
3214 for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
3215 amdgpu_vmid_free_reserved(adev, vm, i);
3216}
3217
3218/**
3219 * amdgpu_vm_manager_init - init the VM manager
3220 *
3221 * @adev: amdgpu_device pointer
3222 *
3223 * Initialize the VM manager structures
3224 */
3225void amdgpu_vm_manager_init(struct amdgpu_device *adev)
3226{
3227 unsigned i;
3228
3229 /* Concurrent flushes are only possible starting with Vega10 and
3230 * are broken on Navi10 and Navi14.
3231 */
3232 adev->vm_manager.concurrent_flush = !(adev->asic_type < CHIP_VEGA10 ||
3233 adev->asic_type == CHIP_NAVI10 ||
3234 adev->asic_type == CHIP_NAVI14);
3235 amdgpu_vmid_mgr_init(adev);
3236
3237 adev->vm_manager.fence_context =
3238 dma_fence_context_alloc(AMDGPU_MAX_RINGS);
3239 for (i = 0; i < AMDGPU_MAX_RINGS; ++i)
3240 adev->vm_manager.seqno[i] = 0;
3241
3242 spin_lock_init(&adev->vm_manager.prt_lock);
3243 atomic_set(&adev->vm_manager.num_prt_users, 0);
3244
3245 /* If not overridden by the user, by default, only in large BAR systems
3246 * Compute VM tables will be updated by CPU
3247 */
3248#ifdef CONFIG_X86_64
3249 if (amdgpu_vm_update_mode == -1) {
3250 if (amdgpu_gmc_vram_full_visible(&adev->gmc))
3251 adev->vm_manager.vm_update_mode =
3252 AMDGPU_VM_USE_CPU_FOR_COMPUTE;
3253 else
3254 adev->vm_manager.vm_update_mode = 0;
3255 } else
3256 adev->vm_manager.vm_update_mode = amdgpu_vm_update_mode;
3257#else
3258 adev->vm_manager.vm_update_mode = 0;
3259#endif
3260
3261 idr_init(&adev->vm_manager.pasid_idr);
3262 spin_lock_init(&adev->vm_manager.pasid_lock);
3263}
3264
3265/**
3266 * amdgpu_vm_manager_fini - cleanup VM manager
3267 *
3268 * @adev: amdgpu_device pointer
3269 *
3270 * Cleanup the VM manager and free resources.
3271 */
3272void amdgpu_vm_manager_fini(struct amdgpu_device *adev)
3273{
3274 WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr));
3275 idr_destroy(&adev->vm_manager.pasid_idr);
3276
3277 amdgpu_vmid_mgr_fini(adev);
3278}
3279
3280/**
3281 * amdgpu_vm_ioctl - Manages VMID reservation for vm hubs.
3282 *
3283 * @dev: drm device pointer
3284 * @data: drm_amdgpu_vm
3285 * @filp: drm file pointer
3286 *
3287 * Returns:
3288 * 0 for success, -errno for errors.
3289 */
3290int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
3291{
3292 union drm_amdgpu_vm *args = data;
3293 struct amdgpu_device *adev = drm_to_adev(dev);
3294 struct amdgpu_fpriv *fpriv = filp->driver_priv;
3295 long timeout = msecs_to_jiffies(2000);
3296 int r;
3297
3298 switch (args->in.op) {
3299 case AMDGPU_VM_OP_RESERVE_VMID:
3300 /* We only have requirement to reserve vmid from gfxhub */
3301 r = amdgpu_vmid_alloc_reserved(adev, &fpriv->vm,
3302 AMDGPU_GFXHUB_0);
3303 if (r)
3304 return r;
3305 break;
3306 case AMDGPU_VM_OP_UNRESERVE_VMID:
3307 if (amdgpu_sriov_runtime(adev))
3308 timeout = 8 * timeout;
3309
3310 /* Wait vm idle to make sure the vmid set in SPM_VMID is
3311 * not referenced anymore.
3312 */
3313 r = amdgpu_bo_reserve(fpriv->vm.root.bo, true);
3314 if (r)
3315 return r;
3316
3317 r = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
3318 if (r < 0)
3319 return r;
3320
3321 amdgpu_bo_unreserve(fpriv->vm.root.bo);
3322 amdgpu_vmid_free_reserved(adev, &fpriv->vm, AMDGPU_GFXHUB_0);
3323 break;
3324 default:
3325 return -EINVAL;
3326 }
3327
3328 return 0;
3329}
3330
3331/**
3332 * amdgpu_vm_get_task_info - Extracts task info for a PASID.
3333 *
3334 * @adev: drm device pointer
3335 * @pasid: PASID identifier for VM
3336 * @task_info: task_info to fill.
3337 */
3338void amdgpu_vm_get_task_info(struct amdgpu_device *adev, u32 pasid,
3339 struct amdgpu_task_info *task_info)
3340{
3341 struct amdgpu_vm *vm;
3342 unsigned long flags;
3343
3344 spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
3345
3346 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3347 if (vm)
3348 *task_info = vm->task_info;
3349
3350 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
3351}
3352
3353/**
3354 * amdgpu_vm_set_task_info - Sets VMs task info.
3355 *
3356 * @vm: vm for which to set the info
3357 */
3358void amdgpu_vm_set_task_info(struct amdgpu_vm *vm)
3359{
3360 if (vm->task_info.pid)
3361 return;
3362
3363 vm->task_info.pid = current->pid;
3364 get_task_comm(vm->task_info.task_name, current);
3365
3366 if (current->group_leader->mm != current->mm)
3367 return;
3368
3369 vm->task_info.tgid = current->group_leader->pid;
3370 get_task_comm(vm->task_info.process_name, current->group_leader);
3371}
3372
3373/**
3374 * amdgpu_vm_handle_fault - graceful handling of VM faults.
3375 * @adev: amdgpu device pointer
3376 * @pasid: PASID of the VM
3377 * @addr: Address of the fault
3378 *
3379 * Try to gracefully handle a VM fault. Return true if the fault was handled and
3380 * shouldn't be reported any more.
3381 */
3382bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
3383 uint64_t addr)
3384{
3385 bool is_compute_context = false;
3386 struct amdgpu_bo *root;
3387 unsigned long irqflags;
3388 uint64_t value, flags;
3389 struct amdgpu_vm *vm;
3390 int r;
3391
3392 spin_lock_irqsave(&adev->vm_manager.pasid_lock, irqflags);
3393 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3394 if (vm) {
3395 root = amdgpu_bo_ref(vm->root.bo);
3396 is_compute_context = vm->is_compute_context;
3397 } else {
3398 root = NULL;
3399 }
3400 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, irqflags);
3401
3402 if (!root)
3403 return false;
3404
3405 addr /= AMDGPU_GPU_PAGE_SIZE;
3406
3407 if (is_compute_context &&
3408 !svm_range_restore_pages(adev, pasid, addr)) {
3409 amdgpu_bo_unref(&root);
3410 return true;
3411 }
3412
3413 r = amdgpu_bo_reserve(root, true);
3414 if (r)
3415 goto error_unref;
3416
3417 /* Double check that the VM still exists */
3418 spin_lock_irqsave(&adev->vm_manager.pasid_lock, irqflags);
3419 vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
3420 if (vm && vm->root.bo != root)
3421 vm = NULL;
3422 spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, irqflags);
3423 if (!vm)
3424 goto error_unlock;
3425
3426 flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SNOOPED |
3427 AMDGPU_PTE_SYSTEM;
3428
3429 if (is_compute_context) {
3430 /* Intentionally setting invalid PTE flag
3431 * combination to force a no-retry-fault
3432 */
3433 flags = AMDGPU_PTE_EXECUTABLE | AMDGPU_PDE_PTE |
3434 AMDGPU_PTE_TF;
3435 value = 0;
3436 } else if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_NEVER) {
3437 /* Redirect the access to the dummy page */
3438 value = adev->dummy_page_addr;
3439 flags |= AMDGPU_PTE_EXECUTABLE | AMDGPU_PTE_READABLE |
3440 AMDGPU_PTE_WRITEABLE;
3441
3442 } else {
3443 /* Let the hw retry silently on the PTE */
3444 value = 0;
3445 }
3446
3447 r = dma_resv_reserve_shared(root->tbo.base.resv, 1);
3448 if (r) {
3449 pr_debug("failed %d to reserve fence slot\n", r);
3450 goto error_unlock;
3451 }
3452
3453 r = amdgpu_vm_bo_update_mapping(adev, adev, vm, true, false, NULL, addr,
3454 addr, flags, value, NULL, NULL, NULL,
3455 NULL);
3456 if (r)
3457 goto error_unlock;
3458
3459 r = amdgpu_vm_update_pdes(adev, vm, true);
3460
3461error_unlock:
3462 amdgpu_bo_unreserve(root);
3463 if (r < 0)
3464 DRM_ERROR("Can't handle page fault (%d)\n", r);
3465
3466error_unref:
3467 amdgpu_bo_unref(&root);
3468
3469 return false;
3470}
3471
3472#if defined(CONFIG_DEBUG_FS)
3473/**
3474 * amdgpu_debugfs_vm_bo_info - print BO info for the VM
3475 *
3476 * @vm: Requested VM for printing BO info
3477 * @m: debugfs file
3478 *
3479 * Print BO information in debugfs file for the VM
3480 */
3481void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m)
3482{
3483 struct amdgpu_bo_va *bo_va, *tmp;
3484 u64 total_idle = 0;
3485 u64 total_evicted = 0;
3486 u64 total_relocated = 0;
3487 u64 total_moved = 0;
3488 u64 total_invalidated = 0;
3489 u64 total_done = 0;
3490 unsigned int total_idle_objs = 0;
3491 unsigned int total_evicted_objs = 0;
3492 unsigned int total_relocated_objs = 0;
3493 unsigned int total_moved_objs = 0;
3494 unsigned int total_invalidated_objs = 0;
3495 unsigned int total_done_objs = 0;
3496 unsigned int id = 0;
3497
3498 seq_puts(m, "\tIdle BOs:\n");
3499 list_for_each_entry_safe(bo_va, tmp, &vm->idle, base.vm_status) {
3500 if (!bo_va->base.bo)
3501 continue;
3502 total_idle += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3503 }
3504 total_idle_objs = id;
3505 id = 0;
3506
3507 seq_puts(m, "\tEvicted BOs:\n");
3508 list_for_each_entry_safe(bo_va, tmp, &vm->evicted, base.vm_status) {
3509 if (!bo_va->base.bo)
3510 continue;
3511 total_evicted += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3512 }
3513 total_evicted_objs = id;
3514 id = 0;
3515
3516 seq_puts(m, "\tRelocated BOs:\n");
3517 list_for_each_entry_safe(bo_va, tmp, &vm->relocated, base.vm_status) {
3518 if (!bo_va->base.bo)
3519 continue;
3520 total_relocated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3521 }
3522 total_relocated_objs = id;
3523 id = 0;
3524
3525 seq_puts(m, "\tMoved BOs:\n");
3526 list_for_each_entry_safe(bo_va, tmp, &vm->moved, base.vm_status) {
3527 if (!bo_va->base.bo)
3528 continue;
3529 total_moved += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3530 }
3531 total_moved_objs = id;
3532 id = 0;
3533
3534 seq_puts(m, "\tInvalidated BOs:\n");
3535 spin_lock(&vm->invalidated_lock);
3536 list_for_each_entry_safe(bo_va, tmp, &vm->invalidated, base.vm_status) {
3537 if (!bo_va->base.bo)
3538 continue;
3539 total_invalidated += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3540 }
3541 total_invalidated_objs = id;
3542 id = 0;
3543
3544 seq_puts(m, "\tDone BOs:\n");
3545 list_for_each_entry_safe(bo_va, tmp, &vm->done, base.vm_status) {
3546 if (!bo_va->base.bo)
3547 continue;
3548 total_done += amdgpu_bo_print_info(id++, bo_va->base.bo, m);
3549 }
3550 spin_unlock(&vm->invalidated_lock);
3551 total_done_objs = id;
3552
3553 seq_printf(m, "\tTotal idle size: %12lld\tobjs:\t%d\n", total_idle,
3554 total_idle_objs);
3555 seq_printf(m, "\tTotal evicted size: %12lld\tobjs:\t%d\n", total_evicted,
3556 total_evicted_objs);
3557 seq_printf(m, "\tTotal relocated size: %12lld\tobjs:\t%d\n", total_relocated,
3558 total_relocated_objs);
3559 seq_printf(m, "\tTotal moved size: %12lld\tobjs:\t%d\n", total_moved,
3560 total_moved_objs);
3561 seq_printf(m, "\tTotal invalidated size: %12lld\tobjs:\t%d\n", total_invalidated,
3562 total_invalidated_objs);
3563 seq_printf(m, "\tTotal done size: %12lld\tobjs:\t%d\n", total_done,
3564 total_done_objs);
3565}
3566#endif