Loading...
1/*
2 * Rockchip emmc PHY driver
3 *
4 * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
5 * Copyright (C) 2016 ROCKCHIP, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/clk.h>
18#include <linux/delay.h>
19#include <linux/mfd/syscon.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/phy/phy.h>
24#include <linux/platform_device.h>
25#include <linux/regmap.h>
26
27/*
28 * The higher 16-bit of this register is used for write protection
29 * only if BIT(x + 16) set to 1 the BIT(x) can be written.
30 */
31#define HIWORD_UPDATE(val, mask, shift) \
32 ((val) << (shift) | (mask) << ((shift) + 16))
33
34/* Register definition */
35#define GRF_EMMCPHY_CON0 0x0
36#define GRF_EMMCPHY_CON1 0x4
37#define GRF_EMMCPHY_CON2 0x8
38#define GRF_EMMCPHY_CON3 0xc
39#define GRF_EMMCPHY_CON4 0x10
40#define GRF_EMMCPHY_CON5 0x14
41#define GRF_EMMCPHY_CON6 0x18
42#define GRF_EMMCPHY_STATUS 0x20
43
44#define PHYCTRL_PDB_MASK 0x1
45#define PHYCTRL_PDB_SHIFT 0x0
46#define PHYCTRL_PDB_PWR_ON 0x1
47#define PHYCTRL_PDB_PWR_OFF 0x0
48#define PHYCTRL_ENDLL_MASK 0x1
49#define PHYCTRL_ENDLL_SHIFT 0x1
50#define PHYCTRL_ENDLL_ENABLE 0x1
51#define PHYCTRL_ENDLL_DISABLE 0x0
52#define PHYCTRL_CALDONE_MASK 0x1
53#define PHYCTRL_CALDONE_SHIFT 0x6
54#define PHYCTRL_CALDONE_DONE 0x1
55#define PHYCTRL_CALDONE_GOING 0x0
56#define PHYCTRL_DLLRDY_MASK 0x1
57#define PHYCTRL_DLLRDY_SHIFT 0x5
58#define PHYCTRL_DLLRDY_DONE 0x1
59#define PHYCTRL_DLLRDY_GOING 0x0
60#define PHYCTRL_FREQSEL_200M 0x0
61#define PHYCTRL_FREQSEL_50M 0x1
62#define PHYCTRL_FREQSEL_100M 0x2
63#define PHYCTRL_FREQSEL_150M 0x3
64#define PHYCTRL_FREQSEL_MASK 0x3
65#define PHYCTRL_FREQSEL_SHIFT 0xc
66#define PHYCTRL_DR_MASK 0x7
67#define PHYCTRL_DR_SHIFT 0x4
68#define PHYCTRL_DR_50OHM 0x0
69#define PHYCTRL_DR_33OHM 0x1
70#define PHYCTRL_DR_66OHM 0x2
71#define PHYCTRL_DR_100OHM 0x3
72#define PHYCTRL_DR_40OHM 0x4
73#define PHYCTRL_OTAPDLYENA 0x1
74#define PHYCTRL_OTAPDLYENA_MASK 0x1
75#define PHYCTRL_OTAPDLYENA_SHIFT 0xb
76#define PHYCTRL_OTAPDLYSEL_MASK 0xf
77#define PHYCTRL_OTAPDLYSEL_SHIFT 0x7
78
79#define PHYCTRL_IS_CALDONE(x) \
80 ((((x) >> PHYCTRL_CALDONE_SHIFT) & \
81 PHYCTRL_CALDONE_MASK) == PHYCTRL_CALDONE_DONE)
82#define PHYCTRL_IS_DLLRDY(x) \
83 ((((x) >> PHYCTRL_DLLRDY_SHIFT) & \
84 PHYCTRL_DLLRDY_MASK) == PHYCTRL_DLLRDY_DONE)
85
86struct rockchip_emmc_phy {
87 unsigned int reg_offset;
88 struct regmap *reg_base;
89 struct clk *emmcclk;
90};
91
92static int rockchip_emmc_phy_power(struct phy *phy, bool on_off)
93{
94 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
95 unsigned int caldone;
96 unsigned int dllrdy;
97 unsigned int freqsel = PHYCTRL_FREQSEL_200M;
98 unsigned long rate;
99 int ret;
100
101 /*
102 * Keep phyctrl_pdb and phyctrl_endll low to allow
103 * initialization of CALIO state M/C DFFs
104 */
105 regmap_write(rk_phy->reg_base,
106 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
107 HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF,
108 PHYCTRL_PDB_MASK,
109 PHYCTRL_PDB_SHIFT));
110 regmap_write(rk_phy->reg_base,
111 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
112 HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE,
113 PHYCTRL_ENDLL_MASK,
114 PHYCTRL_ENDLL_SHIFT));
115
116 /* Already finish power_off above */
117 if (on_off == PHYCTRL_PDB_PWR_OFF)
118 return 0;
119
120 rate = clk_get_rate(rk_phy->emmcclk);
121
122 if (rate != 0) {
123 unsigned long ideal_rate;
124 unsigned long diff;
125
126 switch (rate) {
127 case 1 ... 74999999:
128 ideal_rate = 50000000;
129 freqsel = PHYCTRL_FREQSEL_50M;
130 break;
131 case 75000000 ... 124999999:
132 ideal_rate = 100000000;
133 freqsel = PHYCTRL_FREQSEL_100M;
134 break;
135 case 125000000 ... 174999999:
136 ideal_rate = 150000000;
137 freqsel = PHYCTRL_FREQSEL_150M;
138 break;
139 default:
140 ideal_rate = 200000000;
141 break;
142 }
143
144 diff = (rate > ideal_rate) ?
145 rate - ideal_rate : ideal_rate - rate;
146
147 /*
148 * In order for tuning delays to be accurate we need to be
149 * pretty spot on for the DLL range, so warn if we're too
150 * far off. Also warn if we're above the 200 MHz max. Don't
151 * warn for really slow rates since we won't be tuning then.
152 */
153 if ((rate > 50000000 && diff > 15000000) || (rate > 200000000))
154 dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate);
155 }
156
157 /*
158 * According to the user manual, calpad calibration
159 * cycle takes more than 2us without the minimal recommended
160 * value, so we may need a little margin here
161 */
162 udelay(3);
163 regmap_write(rk_phy->reg_base,
164 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
165 HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON,
166 PHYCTRL_PDB_MASK,
167 PHYCTRL_PDB_SHIFT));
168
169 /*
170 * According to the user manual, it asks driver to wait 5us for
171 * calpad busy trimming. However it is documented that this value is
172 * PVT(A.K.A process,voltage and temperature) relevant, so some
173 * failure cases are found which indicates we should be more tolerant
174 * to calpad busy trimming.
175 */
176 ret = regmap_read_poll_timeout(rk_phy->reg_base,
177 rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
178 caldone, PHYCTRL_IS_CALDONE(caldone),
179 0, 50);
180 if (ret) {
181 pr_err("%s: caldone failed, ret=%d\n", __func__, ret);
182 return ret;
183 }
184
185 /* Set the frequency of the DLL operation */
186 regmap_write(rk_phy->reg_base,
187 rk_phy->reg_offset + GRF_EMMCPHY_CON0,
188 HIWORD_UPDATE(freqsel, PHYCTRL_FREQSEL_MASK,
189 PHYCTRL_FREQSEL_SHIFT));
190
191 /* Turn on the DLL */
192 regmap_write(rk_phy->reg_base,
193 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
194 HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE,
195 PHYCTRL_ENDLL_MASK,
196 PHYCTRL_ENDLL_SHIFT));
197
198 /*
199 * We turned on the DLL even though the rate was 0 because we the
200 * clock might be turned on later. ...but we can't wait for the DLL
201 * to lock when the rate is 0 because it will never lock with no
202 * input clock.
203 *
204 * Technically we should be checking the lock later when the clock
205 * is turned on, but for now we won't.
206 */
207 if (rate == 0)
208 return 0;
209
210 /*
211 * After enabling analog DLL circuits docs say that we need 10.2 us if
212 * our source clock is at 50 MHz and that lock time scales linearly
213 * with clock speed. If we are powering on the PHY and the card clock
214 * is super slow (like 100 kHZ) this could take as long as 5.1 ms as
215 * per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms
216 * Hopefully we won't be running at 100 kHz, but we should still make
217 * sure we wait long enough.
218 *
219 * NOTE: There appear to be corner cases where the DLL seems to take
220 * extra long to lock for reasons that aren't understood. In some
221 * extreme cases we've seen it take up to over 10ms (!). We'll be
222 * generous and give it 50ms.
223 */
224 ret = regmap_read_poll_timeout(rk_phy->reg_base,
225 rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
226 dllrdy, PHYCTRL_IS_DLLRDY(dllrdy),
227 0, 50 * USEC_PER_MSEC);
228 if (ret) {
229 pr_err("%s: dllrdy failed. ret=%d\n", __func__, ret);
230 return ret;
231 }
232
233 return 0;
234}
235
236static int rockchip_emmc_phy_init(struct phy *phy)
237{
238 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
239 int ret = 0;
240
241 /*
242 * We purposely get the clock here and not in probe to avoid the
243 * circular dependency problem. We expect:
244 * - PHY driver to probe
245 * - SDHCI driver to start probe
246 * - SDHCI driver to register it's clock
247 * - SDHCI driver to get the PHY
248 * - SDHCI driver to init the PHY
249 *
250 * The clock is optional, so upon any error we just set to NULL.
251 *
252 * NOTE: we don't do anything special for EPROBE_DEFER here. Given the
253 * above expected use case, EPROBE_DEFER isn't sensible to expect, so
254 * it's just like any other error.
255 */
256 rk_phy->emmcclk = clk_get(&phy->dev, "emmcclk");
257 if (IS_ERR(rk_phy->emmcclk)) {
258 dev_dbg(&phy->dev, "Error getting emmcclk: %d\n", ret);
259 rk_phy->emmcclk = NULL;
260 }
261
262 return ret;
263}
264
265static int rockchip_emmc_phy_exit(struct phy *phy)
266{
267 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
268
269 clk_put(rk_phy->emmcclk);
270
271 return 0;
272}
273
274static int rockchip_emmc_phy_power_off(struct phy *phy)
275{
276 /* Power down emmc phy analog blocks */
277 return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_OFF);
278}
279
280static int rockchip_emmc_phy_power_on(struct phy *phy)
281{
282 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
283
284 /* Drive impedance: 50 Ohm */
285 regmap_write(rk_phy->reg_base,
286 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
287 HIWORD_UPDATE(PHYCTRL_DR_50OHM,
288 PHYCTRL_DR_MASK,
289 PHYCTRL_DR_SHIFT));
290
291 /* Output tap delay: enable */
292 regmap_write(rk_phy->reg_base,
293 rk_phy->reg_offset + GRF_EMMCPHY_CON0,
294 HIWORD_UPDATE(PHYCTRL_OTAPDLYENA,
295 PHYCTRL_OTAPDLYENA_MASK,
296 PHYCTRL_OTAPDLYENA_SHIFT));
297
298 /* Output tap delay */
299 regmap_write(rk_phy->reg_base,
300 rk_phy->reg_offset + GRF_EMMCPHY_CON0,
301 HIWORD_UPDATE(4,
302 PHYCTRL_OTAPDLYSEL_MASK,
303 PHYCTRL_OTAPDLYSEL_SHIFT));
304
305 /* Power up emmc phy analog blocks */
306 return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_ON);
307}
308
309static const struct phy_ops ops = {
310 .init = rockchip_emmc_phy_init,
311 .exit = rockchip_emmc_phy_exit,
312 .power_on = rockchip_emmc_phy_power_on,
313 .power_off = rockchip_emmc_phy_power_off,
314 .owner = THIS_MODULE,
315};
316
317static int rockchip_emmc_phy_probe(struct platform_device *pdev)
318{
319 struct device *dev = &pdev->dev;
320 struct rockchip_emmc_phy *rk_phy;
321 struct phy *generic_phy;
322 struct phy_provider *phy_provider;
323 struct regmap *grf;
324 unsigned int reg_offset;
325
326 if (!dev->parent || !dev->parent->of_node)
327 return -ENODEV;
328
329 grf = syscon_node_to_regmap(dev->parent->of_node);
330 if (IS_ERR(grf)) {
331 dev_err(dev, "Missing rockchip,grf property\n");
332 return PTR_ERR(grf);
333 }
334
335 rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
336 if (!rk_phy)
337 return -ENOMEM;
338
339 if (of_property_read_u32(dev->of_node, "reg", ®_offset)) {
340 dev_err(dev, "missing reg property in node %s\n",
341 dev->of_node->name);
342 return -EINVAL;
343 }
344
345 rk_phy->reg_offset = reg_offset;
346 rk_phy->reg_base = grf;
347
348 generic_phy = devm_phy_create(dev, dev->of_node, &ops);
349 if (IS_ERR(generic_phy)) {
350 dev_err(dev, "failed to create PHY\n");
351 return PTR_ERR(generic_phy);
352 }
353
354 phy_set_drvdata(generic_phy, rk_phy);
355 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
356
357 return PTR_ERR_OR_ZERO(phy_provider);
358}
359
360static const struct of_device_id rockchip_emmc_phy_dt_ids[] = {
361 { .compatible = "rockchip,rk3399-emmc-phy" },
362 {}
363};
364
365MODULE_DEVICE_TABLE(of, rockchip_emmc_phy_dt_ids);
366
367static struct platform_driver rockchip_emmc_driver = {
368 .probe = rockchip_emmc_phy_probe,
369 .driver = {
370 .name = "rockchip-emmc-phy",
371 .of_match_table = rockchip_emmc_phy_dt_ids,
372 },
373};
374
375module_platform_driver(rockchip_emmc_driver);
376
377MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");
378MODULE_DESCRIPTION("Rockchip EMMC PHY driver");
379MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Rockchip emmc PHY driver
4 *
5 * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
6 * Copyright (C) 2016 ROCKCHIP, Inc.
7 */
8
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/mfd/syscon.h>
12#include <linux/module.h>
13#include <linux/of.h>
14#include <linux/of_address.h>
15#include <linux/phy/phy.h>
16#include <linux/platform_device.h>
17#include <linux/regmap.h>
18
19/*
20 * The higher 16-bit of this register is used for write protection
21 * only if BIT(x + 16) set to 1 the BIT(x) can be written.
22 */
23#define HIWORD_UPDATE(val, mask, shift) \
24 ((val) << (shift) | (mask) << ((shift) + 16))
25
26/* Register definition */
27#define GRF_EMMCPHY_CON0 0x0
28#define GRF_EMMCPHY_CON1 0x4
29#define GRF_EMMCPHY_CON2 0x8
30#define GRF_EMMCPHY_CON3 0xc
31#define GRF_EMMCPHY_CON4 0x10
32#define GRF_EMMCPHY_CON5 0x14
33#define GRF_EMMCPHY_CON6 0x18
34#define GRF_EMMCPHY_STATUS 0x20
35
36#define PHYCTRL_PDB_MASK 0x1
37#define PHYCTRL_PDB_SHIFT 0x0
38#define PHYCTRL_PDB_PWR_ON 0x1
39#define PHYCTRL_PDB_PWR_OFF 0x0
40#define PHYCTRL_ENDLL_MASK 0x1
41#define PHYCTRL_ENDLL_SHIFT 0x1
42#define PHYCTRL_ENDLL_ENABLE 0x1
43#define PHYCTRL_ENDLL_DISABLE 0x0
44#define PHYCTRL_CALDONE_MASK 0x1
45#define PHYCTRL_CALDONE_SHIFT 0x6
46#define PHYCTRL_CALDONE_DONE 0x1
47#define PHYCTRL_CALDONE_GOING 0x0
48#define PHYCTRL_DLLRDY_MASK 0x1
49#define PHYCTRL_DLLRDY_SHIFT 0x5
50#define PHYCTRL_DLLRDY_DONE 0x1
51#define PHYCTRL_DLLRDY_GOING 0x0
52#define PHYCTRL_FREQSEL_200M 0x0
53#define PHYCTRL_FREQSEL_50M 0x1
54#define PHYCTRL_FREQSEL_100M 0x2
55#define PHYCTRL_FREQSEL_150M 0x3
56#define PHYCTRL_FREQSEL_MASK 0x3
57#define PHYCTRL_FREQSEL_SHIFT 0xc
58#define PHYCTRL_DR_MASK 0x7
59#define PHYCTRL_DR_SHIFT 0x4
60#define PHYCTRL_DR_50OHM 0x0
61#define PHYCTRL_DR_33OHM 0x1
62#define PHYCTRL_DR_66OHM 0x2
63#define PHYCTRL_DR_100OHM 0x3
64#define PHYCTRL_DR_40OHM 0x4
65#define PHYCTRL_OTAPDLYENA 0x1
66#define PHYCTRL_OTAPDLYENA_MASK 0x1
67#define PHYCTRL_OTAPDLYENA_SHIFT 0xb
68#define PHYCTRL_OTAPDLYSEL_DEFAULT 0x4
69#define PHYCTRL_OTAPDLYSEL_MAXVALUE 0xf
70#define PHYCTRL_OTAPDLYSEL_MASK 0xf
71#define PHYCTRL_OTAPDLYSEL_SHIFT 0x7
72#define PHYCTRL_REN_STRB_DISABLE 0x0
73#define PHYCTRL_REN_STRB_ENABLE 0x1
74#define PHYCTRL_REN_STRB_MASK 0x1
75#define PHYCTRL_REN_STRB_SHIFT 0x9
76
77#define PHYCTRL_IS_CALDONE(x) \
78 ((((x) >> PHYCTRL_CALDONE_SHIFT) & \
79 PHYCTRL_CALDONE_MASK) == PHYCTRL_CALDONE_DONE)
80#define PHYCTRL_IS_DLLRDY(x) \
81 ((((x) >> PHYCTRL_DLLRDY_SHIFT) & \
82 PHYCTRL_DLLRDY_MASK) == PHYCTRL_DLLRDY_DONE)
83
84struct rockchip_emmc_phy {
85 unsigned int reg_offset;
86 struct regmap *reg_base;
87 struct clk *emmcclk;
88 unsigned int drive_impedance;
89 unsigned int enable_strobe_pulldown;
90 unsigned int output_tapdelay_select;
91};
92
93static int rockchip_emmc_phy_power(struct phy *phy, bool on_off)
94{
95 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
96 unsigned int caldone;
97 unsigned int dllrdy;
98 unsigned int freqsel = PHYCTRL_FREQSEL_200M;
99 unsigned long rate;
100 int ret;
101
102 /*
103 * Keep phyctrl_pdb and phyctrl_endll low to allow
104 * initialization of CALIO state M/C DFFs
105 */
106 regmap_write(rk_phy->reg_base,
107 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
108 HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF,
109 PHYCTRL_PDB_MASK,
110 PHYCTRL_PDB_SHIFT));
111 regmap_write(rk_phy->reg_base,
112 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
113 HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE,
114 PHYCTRL_ENDLL_MASK,
115 PHYCTRL_ENDLL_SHIFT));
116
117 /* Already finish power_off above */
118 if (on_off == PHYCTRL_PDB_PWR_OFF)
119 return 0;
120
121 rate = clk_get_rate(rk_phy->emmcclk);
122
123 if (rate != 0) {
124 unsigned long ideal_rate;
125 unsigned long diff;
126
127 switch (rate) {
128 case 1 ... 74999999:
129 ideal_rate = 50000000;
130 freqsel = PHYCTRL_FREQSEL_50M;
131 break;
132 case 75000000 ... 124999999:
133 ideal_rate = 100000000;
134 freqsel = PHYCTRL_FREQSEL_100M;
135 break;
136 case 125000000 ... 174999999:
137 ideal_rate = 150000000;
138 freqsel = PHYCTRL_FREQSEL_150M;
139 break;
140 default:
141 ideal_rate = 200000000;
142 break;
143 }
144
145 diff = (rate > ideal_rate) ?
146 rate - ideal_rate : ideal_rate - rate;
147
148 /*
149 * In order for tuning delays to be accurate we need to be
150 * pretty spot on for the DLL range, so warn if we're too
151 * far off. Also warn if we're above the 200 MHz max. Don't
152 * warn for really slow rates since we won't be tuning then.
153 */
154 if ((rate > 50000000 && diff > 15000000) || (rate > 200000000))
155 dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate);
156 }
157
158 /*
159 * According to the user manual, calpad calibration
160 * cycle takes more than 2us without the minimal recommended
161 * value, so we may need a little margin here
162 */
163 udelay(3);
164 regmap_write(rk_phy->reg_base,
165 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
166 HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON,
167 PHYCTRL_PDB_MASK,
168 PHYCTRL_PDB_SHIFT));
169
170 /*
171 * According to the user manual, it asks driver to wait 5us for
172 * calpad busy trimming. However it is documented that this value is
173 * PVT(A.K.A process,voltage and temperature) relevant, so some
174 * failure cases are found which indicates we should be more tolerant
175 * to calpad busy trimming.
176 */
177 ret = regmap_read_poll_timeout(rk_phy->reg_base,
178 rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
179 caldone, PHYCTRL_IS_CALDONE(caldone),
180 0, 50);
181 if (ret) {
182 pr_err("%s: caldone failed, ret=%d\n", __func__, ret);
183 return ret;
184 }
185
186 /* Set the frequency of the DLL operation */
187 regmap_write(rk_phy->reg_base,
188 rk_phy->reg_offset + GRF_EMMCPHY_CON0,
189 HIWORD_UPDATE(freqsel, PHYCTRL_FREQSEL_MASK,
190 PHYCTRL_FREQSEL_SHIFT));
191
192 /* Turn on the DLL */
193 regmap_write(rk_phy->reg_base,
194 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
195 HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE,
196 PHYCTRL_ENDLL_MASK,
197 PHYCTRL_ENDLL_SHIFT));
198
199 /*
200 * We turned on the DLL even though the rate was 0 because we the
201 * clock might be turned on later. ...but we can't wait for the DLL
202 * to lock when the rate is 0 because it will never lock with no
203 * input clock.
204 *
205 * Technically we should be checking the lock later when the clock
206 * is turned on, but for now we won't.
207 */
208 if (rate == 0)
209 return 0;
210
211 /*
212 * After enabling analog DLL circuits docs say that we need 10.2 us if
213 * our source clock is at 50 MHz and that lock time scales linearly
214 * with clock speed. If we are powering on the PHY and the card clock
215 * is super slow (like 100 kHZ) this could take as long as 5.1 ms as
216 * per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms
217 * Hopefully we won't be running at 100 kHz, but we should still make
218 * sure we wait long enough.
219 *
220 * NOTE: There appear to be corner cases where the DLL seems to take
221 * extra long to lock for reasons that aren't understood. In some
222 * extreme cases we've seen it take up to over 10ms (!). We'll be
223 * generous and give it 50ms.
224 */
225 ret = regmap_read_poll_timeout(rk_phy->reg_base,
226 rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
227 dllrdy, PHYCTRL_IS_DLLRDY(dllrdy),
228 0, 50 * USEC_PER_MSEC);
229 if (ret) {
230 pr_err("%s: dllrdy failed. ret=%d\n", __func__, ret);
231 return ret;
232 }
233
234 return 0;
235}
236
237static int rockchip_emmc_phy_init(struct phy *phy)
238{
239 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
240 int ret = 0;
241
242 /*
243 * We purposely get the clock here and not in probe to avoid the
244 * circular dependency problem. We expect:
245 * - PHY driver to probe
246 * - SDHCI driver to start probe
247 * - SDHCI driver to register it's clock
248 * - SDHCI driver to get the PHY
249 * - SDHCI driver to init the PHY
250 *
251 * The clock is optional, using clk_get_optional() to get the clock
252 * and do error processing if the return value != NULL
253 *
254 * NOTE: we don't do anything special for EPROBE_DEFER here. Given the
255 * above expected use case, EPROBE_DEFER isn't sensible to expect, so
256 * it's just like any other error.
257 */
258 rk_phy->emmcclk = clk_get_optional(&phy->dev, "emmcclk");
259 if (IS_ERR(rk_phy->emmcclk)) {
260 ret = PTR_ERR(rk_phy->emmcclk);
261 dev_err(&phy->dev, "Error getting emmcclk: %d\n", ret);
262 rk_phy->emmcclk = NULL;
263 }
264
265 return ret;
266}
267
268static int rockchip_emmc_phy_exit(struct phy *phy)
269{
270 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
271
272 clk_put(rk_phy->emmcclk);
273
274 return 0;
275}
276
277static int rockchip_emmc_phy_power_off(struct phy *phy)
278{
279 /* Power down emmc phy analog blocks */
280 return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_OFF);
281}
282
283static int rockchip_emmc_phy_power_on(struct phy *phy)
284{
285 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
286
287 /* Drive impedance: from DTS */
288 regmap_write(rk_phy->reg_base,
289 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
290 HIWORD_UPDATE(rk_phy->drive_impedance,
291 PHYCTRL_DR_MASK,
292 PHYCTRL_DR_SHIFT));
293
294 /* Output tap delay: enable */
295 regmap_write(rk_phy->reg_base,
296 rk_phy->reg_offset + GRF_EMMCPHY_CON0,
297 HIWORD_UPDATE(PHYCTRL_OTAPDLYENA,
298 PHYCTRL_OTAPDLYENA_MASK,
299 PHYCTRL_OTAPDLYENA_SHIFT));
300
301 /* Output tap delay */
302 regmap_write(rk_phy->reg_base,
303 rk_phy->reg_offset + GRF_EMMCPHY_CON0,
304 HIWORD_UPDATE(rk_phy->output_tapdelay_select,
305 PHYCTRL_OTAPDLYSEL_MASK,
306 PHYCTRL_OTAPDLYSEL_SHIFT));
307
308 /* Internal pull-down for strobe line */
309 regmap_write(rk_phy->reg_base,
310 rk_phy->reg_offset + GRF_EMMCPHY_CON2,
311 HIWORD_UPDATE(rk_phy->enable_strobe_pulldown,
312 PHYCTRL_REN_STRB_MASK,
313 PHYCTRL_REN_STRB_SHIFT));
314
315 /* Power up emmc phy analog blocks */
316 return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_ON);
317}
318
319static const struct phy_ops ops = {
320 .init = rockchip_emmc_phy_init,
321 .exit = rockchip_emmc_phy_exit,
322 .power_on = rockchip_emmc_phy_power_on,
323 .power_off = rockchip_emmc_phy_power_off,
324 .owner = THIS_MODULE,
325};
326
327static u32 convert_drive_impedance_ohm(struct platform_device *pdev, u32 dr_ohm)
328{
329 switch (dr_ohm) {
330 case 100:
331 return PHYCTRL_DR_100OHM;
332 case 66:
333 return PHYCTRL_DR_66OHM;
334 case 50:
335 return PHYCTRL_DR_50OHM;
336 case 40:
337 return PHYCTRL_DR_40OHM;
338 case 33:
339 return PHYCTRL_DR_33OHM;
340 }
341
342 dev_warn(&pdev->dev, "Invalid value %u for drive-impedance-ohm.\n",
343 dr_ohm);
344 return PHYCTRL_DR_50OHM;
345}
346
347static int rockchip_emmc_phy_probe(struct platform_device *pdev)
348{
349 struct device *dev = &pdev->dev;
350 struct rockchip_emmc_phy *rk_phy;
351 struct phy *generic_phy;
352 struct phy_provider *phy_provider;
353 struct regmap *grf;
354 unsigned int reg_offset;
355 u32 val;
356
357 if (!dev->parent || !dev->parent->of_node)
358 return -ENODEV;
359
360 grf = syscon_node_to_regmap(dev->parent->of_node);
361 if (IS_ERR(grf)) {
362 dev_err(dev, "Missing rockchip,grf property\n");
363 return PTR_ERR(grf);
364 }
365
366 rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
367 if (!rk_phy)
368 return -ENOMEM;
369
370 if (of_property_read_u32(dev->of_node, "reg", ®_offset)) {
371 dev_err(dev, "missing reg property in node %pOFn\n",
372 dev->of_node);
373 return -EINVAL;
374 }
375
376 rk_phy->reg_offset = reg_offset;
377 rk_phy->reg_base = grf;
378 rk_phy->drive_impedance = PHYCTRL_DR_50OHM;
379 rk_phy->enable_strobe_pulldown = PHYCTRL_REN_STRB_DISABLE;
380 rk_phy->output_tapdelay_select = PHYCTRL_OTAPDLYSEL_DEFAULT;
381
382 if (!of_property_read_u32(dev->of_node, "drive-impedance-ohm", &val))
383 rk_phy->drive_impedance = convert_drive_impedance_ohm(pdev, val);
384
385 if (of_property_read_bool(dev->of_node, "rockchip,enable-strobe-pulldown"))
386 rk_phy->enable_strobe_pulldown = PHYCTRL_REN_STRB_ENABLE;
387
388 if (!of_property_read_u32(dev->of_node, "rockchip,output-tapdelay-select", &val)) {
389 if (val <= PHYCTRL_OTAPDLYSEL_MAXVALUE)
390 rk_phy->output_tapdelay_select = val;
391 else
392 dev_err(dev, "output-tapdelay-select exceeds limit, apply default\n");
393 }
394
395 generic_phy = devm_phy_create(dev, dev->of_node, &ops);
396 if (IS_ERR(generic_phy)) {
397 dev_err(dev, "failed to create PHY\n");
398 return PTR_ERR(generic_phy);
399 }
400
401 phy_set_drvdata(generic_phy, rk_phy);
402 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
403
404 return PTR_ERR_OR_ZERO(phy_provider);
405}
406
407static const struct of_device_id rockchip_emmc_phy_dt_ids[] = {
408 { .compatible = "rockchip,rk3399-emmc-phy" },
409 {}
410};
411
412MODULE_DEVICE_TABLE(of, rockchip_emmc_phy_dt_ids);
413
414static struct platform_driver rockchip_emmc_driver = {
415 .probe = rockchip_emmc_phy_probe,
416 .driver = {
417 .name = "rockchip-emmc-phy",
418 .of_match_table = rockchip_emmc_phy_dt_ids,
419 },
420};
421
422module_platform_driver(rockchip_emmc_driver);
423
424MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");
425MODULE_DESCRIPTION("Rockchip EMMC PHY driver");
426MODULE_LICENSE("GPL v2");