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1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/input/gpio-keys.h>
5#include <dt-bindings/input/input.h>
6#include <dt-bindings/thermal/thermal.h>
7
8#include "tegra20.dtsi"
9#include "tegra20-cpu-opp.dtsi"
10#include "tegra20-cpu-opp-microvolt.dtsi"
11
12/ {
13 model = "Acer Iconia Tab A500";
14 compatible = "acer,picasso", "nvidia,tegra20";
15
16 aliases {
17 mmc0 = &sdmmc4; /* eMMC */
18 mmc1 = &sdmmc3; /* MicroSD */
19 mmc2 = &sdmmc1; /* WiFi */
20
21 rtc0 = &pmic;
22 rtc1 = "/rtc@7000e000";
23
24 serial0 = &uartd; /* Docking station */
25 serial1 = &uartc; /* Bluetooth */
26 serial2 = &uartb; /* GPS */
27 };
28
29 /*
30 * The decompressor and also some bootloaders rely on a
31 * pre-existing /chosen node to be available to insert the
32 * command line and merge other ATAGS info.
33 */
34 chosen {};
35
36 memory@0 {
37 reg = <0x00000000 0x40000000>;
38 };
39
40 reserved-memory {
41 #address-cells = <1>;
42 #size-cells = <1>;
43 ranges;
44
45 ramoops@2ffe0000 {
46 compatible = "ramoops";
47 reg = <0x2ffe0000 0x10000>; /* 64kB */
48 console-size = <0x8000>; /* 32kB */
49 record-size = <0x400>; /* 1kB */
50 ecc-size = <16>;
51 };
52
53 linux,cma@30000000 {
54 compatible = "shared-dma-pool";
55 alloc-ranges = <0x30000000 0x10000000>;
56 size = <0x10000000>; /* 256MiB */
57 linux,cma-default;
58 reusable;
59 };
60 };
61
62 host1x@50000000 {
63 dc@54200000 {
64 rgb {
65 status = "okay";
66
67 port@0 {
68 lcd_output: endpoint {
69 remote-endpoint = <&lvds_encoder_input>;
70 bus-width = <18>;
71 };
72 };
73 };
74 };
75
76 hdmi@54280000 {
77 status = "okay";
78
79 vdd-supply = <&hdmi_vdd_reg>;
80 pll-supply = <&hdmi_pll_reg>;
81 hdmi-supply = <&vdd_5v0_sys>;
82
83 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
84 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
85 GPIO_ACTIVE_HIGH>;
86 };
87 };
88
89 pinmux@70000014 {
90 pinctrl-names = "default";
91 pinctrl-0 = <&state_default>;
92
93 state_default: pinmux {
94 ata {
95 nvidia,pins = "ata";
96 nvidia,function = "ide";
97 };
98 atb {
99 nvidia,pins = "atb", "gma", "gme";
100 nvidia,function = "sdio4";
101 };
102 atc {
103 nvidia,pins = "atc";
104 nvidia,function = "nand";
105 };
106 atd {
107 nvidia,pins = "atd", "ate", "gmb", "spia",
108 "spib", "spic";
109 nvidia,function = "gmi";
110 };
111 cdev1 {
112 nvidia,pins = "cdev1";
113 nvidia,function = "plla_out";
114 };
115 cdev2 {
116 nvidia,pins = "cdev2";
117 nvidia,function = "pllp_out4";
118 };
119 crtp {
120 nvidia,pins = "crtp", "lm1";
121 nvidia,function = "crt";
122 };
123 csus {
124 nvidia,pins = "csus";
125 nvidia,function = "vi_sensor_clk";
126 };
127 dap1 {
128 nvidia,pins = "dap1";
129 nvidia,function = "dap1";
130 };
131 dap2 {
132 nvidia,pins = "dap2";
133 nvidia,function = "dap2";
134 };
135 dap3 {
136 nvidia,pins = "dap3";
137 nvidia,function = "dap3";
138 };
139 dap4 {
140 nvidia,pins = "dap4";
141 nvidia,function = "dap4";
142 };
143 dta {
144 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
145 nvidia,function = "vi";
146 };
147 dtf {
148 nvidia,pins = "dtf";
149 nvidia,function = "i2c3";
150 };
151 gmc {
152 nvidia,pins = "gmc";
153 nvidia,function = "uartd";
154 };
155 gmd {
156 nvidia,pins = "gmd";
157 nvidia,function = "sflash";
158 };
159 gpu {
160 nvidia,pins = "gpu";
161 nvidia,function = "pwm";
162 };
163 gpu7 {
164 nvidia,pins = "gpu7";
165 nvidia,function = "rtck";
166 };
167 gpv {
168 nvidia,pins = "gpv", "slxa";
169 nvidia,function = "pcie";
170 };
171 hdint {
172 nvidia,pins = "hdint";
173 nvidia,function = "hdmi";
174 };
175 i2cp {
176 nvidia,pins = "i2cp";
177 nvidia,function = "i2cp";
178 };
179 irrx {
180 nvidia,pins = "irrx", "irtx";
181 nvidia,function = "uartb";
182 };
183 kbca {
184 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
185 "kbce", "kbcf";
186 nvidia,function = "kbc";
187 };
188 lcsn {
189 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
190 "lsdi", "lvp0";
191 nvidia,function = "rsvd4";
192 };
193 ld0 {
194 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
195 "ld5", "ld6", "ld7", "ld8", "ld9",
196 "ld10", "ld11", "ld12", "ld13", "ld14",
197 "ld15", "ld16", "ld17", "ldi", "lhp0",
198 "lhp1", "lhp2", "lhs", "lpp", "lsc0",
199 "lsc1", "lsck", "lsda", "lspi", "lvp1",
200 "lvs";
201 nvidia,function = "displaya";
202 };
203 owc {
204 nvidia,pins = "owc", "spdi", "spdo", "uac";
205 nvidia,function = "rsvd2";
206 };
207 pmc {
208 nvidia,pins = "pmc";
209 nvidia,function = "pwr_on";
210 };
211 rm {
212 nvidia,pins = "rm";
213 nvidia,function = "i2c1";
214 };
215 sdb {
216 nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk";
217 nvidia,function = "sdio3";
218 };
219 sdio1 {
220 nvidia,pins = "sdio1";
221 nvidia,function = "sdio1";
222 };
223 slxd {
224 nvidia,pins = "slxd";
225 nvidia,function = "spdif";
226 };
227 spid {
228 nvidia,pins = "spid", "spie", "spif";
229 nvidia,function = "spi1";
230 };
231 spig {
232 nvidia,pins = "spig", "spih";
233 nvidia,function = "spi2_alt";
234 };
235 uaa {
236 nvidia,pins = "uaa", "uab", "uda";
237 nvidia,function = "ulpi";
238 };
239 uad {
240 nvidia,pins = "uad";
241 nvidia,function = "irda";
242 };
243 uca {
244 nvidia,pins = "uca", "ucb";
245 nvidia,function = "uartc";
246 };
247 conf_ata {
248 nvidia,pins = "ata", "atb", "atc", "atd",
249 "cdev1", "cdev2", "csus", "dap1",
250 "dap4", "dte", "dtf", "gma", "gmc",
251 "gme", "gpu", "gpu7", "gpv", "i2cp",
252 "irrx", "irtx", "pta", "rm",
253 "sdc", "sdd", "slxc", "slxd", "slxk",
254 "spdi", "spdo", "uac", "uad", "uda";
255 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
256 nvidia,tristate = <TEGRA_PIN_DISABLE>;
257 };
258 conf_ate {
259 nvidia,pins = "ate", "dap2", "dap3",
260 "gmd", "owc", "spia", "spib", "spic",
261 "spid", "spie";
262 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
263 nvidia,tristate = <TEGRA_PIN_ENABLE>;
264 };
265 conf_ck32 {
266 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
267 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
268 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
269 };
270 conf_crtp {
271 nvidia,pins = "crtp", "gmb", "slxa", "spig",
272 "spih";
273 nvidia,pull = <TEGRA_PIN_PULL_UP>;
274 nvidia,tristate = <TEGRA_PIN_ENABLE>;
275 };
276 conf_dta {
277 nvidia,pins = "dta", "dtb", "dtc", "dtd", "kbcb";
278 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
279 nvidia,tristate = <TEGRA_PIN_DISABLE>;
280 };
281 conf_dte {
282 nvidia,pins = "spif";
283 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
284 nvidia,tristate = <TEGRA_PIN_ENABLE>;
285 };
286 conf_hdint {
287 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
288 "lpw1", "lsck", "lsda", "lsdi",
289 "lvp0";
290 nvidia,tristate = <TEGRA_PIN_ENABLE>;
291 };
292 conf_kbca {
293 nvidia,pins = "kbca", "kbcc", "kbcd",
294 "kbce", "kbcf", "sdio1", "uaa",
295 "uab", "uca", "ucb";
296 nvidia,pull = <TEGRA_PIN_PULL_UP>;
297 nvidia,tristate = <TEGRA_PIN_DISABLE>;
298 };
299 conf_lc {
300 nvidia,pins = "lc", "ls";
301 nvidia,pull = <TEGRA_PIN_PULL_UP>;
302 };
303 conf_ld0 {
304 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
305 "ld5", "ld6", "ld7", "ld8", "ld9",
306 "ld10", "ld11", "ld12", "ld13", "ld14",
307 "ld15", "ld16", "ld17", "ldi", "lhp0",
308 "lhp1", "lhp2", "lhs", "lm0", "lpp",
309 "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
310 "lvp1", "lvs", "pmc", "sdb";
311 nvidia,tristate = <TEGRA_PIN_DISABLE>;
312 };
313 conf_ld17_0 {
314 nvidia,pins = "ld17_0";
315 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
316 };
317 drive_ddc {
318 nvidia,pins = "drive_ddc",
319 "drive_vi1",
320 "drive_sdio1";
321 nvidia,pull-up-strength = <31>;
322 nvidia,pull-down-strength = <31>;
323 nvidia,schmitt = <TEGRA_PIN_ENABLE>;
324 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
325 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
326 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
327 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>;
328 };
329 drive_dbg {
330 nvidia,pins = "drive_dbg",
331 "drive_vi2",
332 "drive_at1",
333 "drive_ao1";
334 nvidia,pull-up-strength = <31>;
335 nvidia,pull-down-strength = <31>;
336 nvidia,schmitt = <TEGRA_PIN_ENABLE>;
337 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
338 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>;
339 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
340 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
341 };
342 };
343
344 state_i2cmux_ddc: pinmux_i2cmux_ddc {
345 ddc {
346 nvidia,pins = "ddc";
347 nvidia,function = "i2c2";
348 };
349 pta {
350 nvidia,pins = "pta";
351 nvidia,function = "rsvd4";
352 };
353 };
354
355 state_i2cmux_pta: pinmux_i2cmux_pta {
356 ddc {
357 nvidia,pins = "ddc";
358 nvidia,function = "rsvd4";
359 };
360 pta {
361 nvidia,pins = "pta";
362 nvidia,function = "i2c2";
363 };
364 };
365
366 state_i2cmux_idle: pinmux_i2cmux_idle {
367 ddc {
368 nvidia,pins = "ddc";
369 nvidia,function = "rsvd4";
370 };
371 pta {
372 nvidia,pins = "pta";
373 nvidia,function = "rsvd4";
374 };
375 };
376 };
377
378 tegra_i2s1: i2s@70002800 {
379 status = "okay";
380 };
381
382 uartb: serial@70006040 {
383 compatible = "nvidia,tegra20-hsuart";
384 /* GPS BCM4751 */
385 };
386
387 uartc: serial@70006200 {
388 compatible = "nvidia,tegra20-hsuart";
389 status = "okay";
390
391 /* Azurewave AW-NH665 BCM4329B1 */
392 bluetooth {
393 compatible = "brcm,bcm4329-bt";
394
395 /* PLLP 216MHz / 16 / 4 */
396 max-speed = <3375000>;
397
398 clocks = <&rtc_32k_wifi>;
399 clock-names = "txco";
400
401 vbat-supply = <&vdd_3v3_sys>;
402 vddio-supply = <&vdd_1v8_sys>;
403
404 device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
405 host-wakeup-gpios = <&gpio TEGRA_GPIO(U, 6) GPIO_ACTIVE_HIGH>;
406 shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
407 };
408 };
409
410 uartd: serial@70006300 {
411 /* Docking station */
412 };
413
414 i2c@7000c000 {
415 clock-frequency = <400000>;
416 status = "okay";
417
418 wm8903: audio-codec@1a {
419 compatible = "wlf,wm8903";
420 reg = <0x1a>;
421
422 interrupt-parent = <&gpio>;
423 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_EDGE_BOTH>;
424
425 gpio-controller;
426 #gpio-cells = <2>;
427
428 micdet-cfg = <0>;
429 micdet-delay = <100>;
430
431 gpio-cfg = <
432 0x0000 /* MIC_LR_OUT# GPIO, output, low */
433 0x0000 /* FM2018-enable GPIO, output, low */
434 0x0000 /* Speaker-enable GPIO, output, low */
435 0x0200 /* Interrupt, output */
436 0x01a0 /* BCLK, input, active high */
437 >;
438
439 AVDD-supply = <&vdd_1v8_sys>;
440 CPVDD-supply = <&vdd_1v8_sys>;
441 DBVDD-supply = <&vdd_1v8_sys>;
442 DCVDD-supply = <&vdd_1v8_sys>;
443 };
444
445 touchscreen@4c {
446 compatible = "atmel,maxtouch";
447 reg = <0x4c>;
448
449 interrupt-parent = <&gpio>;
450 interrupts = <TEGRA_GPIO(V, 6) IRQ_TYPE_LEVEL_LOW>;
451
452 reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_LOW>;
453
454 vdda-supply = <&vdd_3v3_sys>;
455 vdd-supply = <&vdd_3v3_sys>;
456
457 atmel,wakeup-method = <1>;
458 };
459
460 gyroscope@68 {
461 compatible = "invensense,mpu3050";
462 reg = <0x68>;
463
464 interrupt-parent = <&gpio>;
465 interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_EDGE_RISING>;
466
467 vdd-supply = <&vdd_3v3_sys>;
468 vlogic-supply = <&vdd_1v8_sys>;
469
470 mount-matrix = "0", "1", "0",
471 "1", "0", "0",
472 "0", "0", "-1";
473
474 i2c-gate {
475 #address-cells = <1>;
476 #size-cells = <0>;
477
478 accelerometer@f {
479 compatible = "kionix,kxtf9";
480 reg = <0x0f>;
481
482 interrupt-parent = <&gpio>;
483 interrupts = <TEGRA_GPIO(S, 7) IRQ_TYPE_EDGE_RISING>;
484
485 mount-matrix = "0", "1", "0",
486 "1", "0", "0",
487 "0", "0", "-1";
488 };
489 };
490 };
491 };
492
493 i2c@7000c400 {
494 clock-frequency = <10000>;
495 status = "okay";
496 };
497
498 i2cmux {
499 compatible = "i2c-mux-pinctrl";
500 #address-cells = <1>;
501 #size-cells = <0>;
502
503 i2c-parent = <&{/i2c@7000c400}>;
504
505 pinctrl-names = "ddc", "pta", "idle";
506 pinctrl-0 = <&state_i2cmux_ddc>;
507 pinctrl-1 = <&state_i2cmux_pta>;
508 pinctrl-2 = <&state_i2cmux_idle>;
509
510 hdmi_ddc: i2c@0 {
511 reg = <0>;
512 #address-cells = <1>;
513 #size-cells = <0>;
514 };
515
516 panel_ddc: i2c@1 {
517 reg = <1>;
518 #address-cells = <1>;
519 #size-cells = <0>;
520
521 embedded-controller@58 {
522 compatible = "acer,a500-iconia-ec", "ene,kb930";
523 reg = <0x58>;
524
525 system-power-controller;
526
527 monitored-battery = <&bat1010>;
528 power-supplies = <&mains>;
529 };
530 };
531 };
532
533 pwm: pwm@7000a000 {
534 status = "okay";
535 };
536
537 i2c@7000d000 {
538 clock-frequency = <100000>;
539 status = "okay";
540
541 magnetometer@c {
542 compatible = "ak,ak8975";
543 reg = <0x0c>;
544
545 interrupt-parent = <&gpio>;
546 interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_EDGE_RISING>;
547
548 vdd-supply = <&vdd_3v3_sys>;
549 vid-supply = <&vdd_1v8_sys>;
550
551 mount-matrix = "1", "0", "0",
552 "0", "-1", "0",
553 "0", "0", "-1";
554 };
555
556 pmic: pmic@34 {
557 compatible = "ti,tps6586x";
558 reg = <0x34>;
559
560 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
561
562 #gpio-cells = <2>;
563 gpio-controller;
564
565 sys-supply = <&vdd_5v0_sys>;
566 vin-sm0-supply = <&sys_reg>;
567 vin-sm1-supply = <&sys_reg>;
568 vin-sm2-supply = <&sys_reg>;
569 vinldo01-supply = <&sm2_reg>;
570 vinldo23-supply = <&sm2_reg>;
571 vinldo4-supply = <&sm2_reg>;
572 vinldo678-supply = <&sm2_reg>;
573 vinldo9-supply = <&sm2_reg>;
574
575 regulators {
576 sys_reg: sys {
577 regulator-name = "vdd_sys";
578 regulator-always-on;
579 };
580
581 vdd_core: sm0 {
582 regulator-name = "vdd_sm0,vdd_core";
583 regulator-min-microvolt = <950000>;
584 regulator-max-microvolt = <1300000>;
585 regulator-coupled-with = <&rtc_vdd &vdd_cpu>;
586 regulator-coupled-max-spread = <170000 550000>;
587 regulator-always-on;
588 regulator-boot-on;
589
590 nvidia,tegra-core-regulator;
591 };
592
593 vdd_cpu: sm1 {
594 regulator-name = "vdd_sm1,vdd_cpu";
595 regulator-min-microvolt = <750000>;
596 regulator-max-microvolt = <1125000>;
597 regulator-coupled-with = <&vdd_core &rtc_vdd>;
598 regulator-coupled-max-spread = <550000 550000>;
599 regulator-always-on;
600 regulator-boot-on;
601
602 nvidia,tegra-cpu-regulator;
603 };
604
605 sm2_reg: sm2 {
606 regulator-name = "vdd_sm2,vin_ldo*";
607 regulator-min-microvolt = <3700000>;
608 regulator-max-microvolt = <3700000>;
609 regulator-always-on;
610 };
611
612 /* LDO0 is not connected to anything */
613
614 ldo1 {
615 regulator-name = "vdd_ldo1,avdd_pll*";
616 regulator-min-microvolt = <1100000>;
617 regulator-max-microvolt = <1100000>;
618 regulator-always-on;
619 regulator-boot-on;
620 };
621
622 rtc_vdd: ldo2 {
623 regulator-name = "vdd_ldo2,vdd_rtc";
624 regulator-min-microvolt = <950000>;
625 regulator-max-microvolt = <1300000>;
626 regulator-coupled-with = <&vdd_core &vdd_cpu>;
627 regulator-coupled-max-spread = <170000 550000>;
628 regulator-always-on;
629 regulator-boot-on;
630
631 nvidia,tegra-rtc-regulator;
632 };
633
634 ldo3 {
635 regulator-name = "vdd_ldo3,avdd_usb*";
636 regulator-min-microvolt = <3300000>;
637 regulator-max-microvolt = <3300000>;
638 regulator-always-on;
639 };
640
641 ldo4 {
642 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
643 regulator-min-microvolt = <1800000>;
644 regulator-max-microvolt = <1800000>;
645 regulator-always-on;
646 regulator-boot-on;
647 };
648
649 vcore_emmc: ldo5 {
650 regulator-name = "vdd_ldo5,vcore_mmc";
651 regulator-min-microvolt = <2850000>;
652 regulator-max-microvolt = <2850000>;
653 regulator-always-on;
654 };
655
656 avdd_vdac_reg: ldo6 {
657 regulator-name = "vdd_ldo6,avdd_vdac";
658 regulator-min-microvolt = <2850000>;
659 regulator-max-microvolt = <2850000>;
660 };
661
662 hdmi_vdd_reg: ldo7 {
663 regulator-name = "vdd_ldo7,avdd_hdmi";
664 regulator-min-microvolt = <3300000>;
665 regulator-max-microvolt = <3300000>;
666 };
667
668 hdmi_pll_reg: ldo8 {
669 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
670 regulator-min-microvolt = <1800000>;
671 regulator-max-microvolt = <1800000>;
672 };
673
674 ldo9 {
675 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
676 regulator-min-microvolt = <2850000>;
677 regulator-max-microvolt = <2850000>;
678 regulator-always-on;
679 regulator-boot-on;
680 };
681
682 ldo_rtc {
683 regulator-name = "vdd_rtc_out,vdd_cell";
684 regulator-min-microvolt = <3300000>;
685 regulator-max-microvolt = <3300000>;
686 regulator-always-on;
687 regulator-boot-on;
688 };
689 };
690 };
691
692 nct1008: temperature-sensor@4c {
693 compatible = "onnn,nct1008";
694 reg = <0x4c>;
695 vcc-supply = <&vdd_3v3_sys>;
696 #thermal-sensor-cells = <1>;
697 };
698 };
699
700 pmc@7000e400 {
701 nvidia,invert-interrupt;
702 nvidia,suspend-mode = <1>;
703 nvidia,cpu-pwr-good-time = <2000>;
704 nvidia,cpu-pwr-off-time = <100>;
705 nvidia,core-pwr-good-time = <3845 3845>;
706 nvidia,core-pwr-off-time = <458>;
707 nvidia,sys-clock-req-active-high;
708 };
709
710 usb@c5000000 {
711 compatible = "nvidia,tegra20-udc";
712 status = "okay";
713 dr_mode = "peripheral";
714 };
715
716 usb-phy@c5000000 {
717 status = "okay";
718 dr_mode = "peripheral";
719 nvidia,xcvr-setup-use-fuses;
720 nvidia,xcvr-lsfslew = <2>;
721 nvidia,xcvr-lsrslew = <2>;
722 };
723
724 usb@c5008000 {
725 status = "okay";
726 };
727
728 usb-phy@c5008000 {
729 status = "okay";
730 nvidia,xcvr-setup-use-fuses;
731 nvidia,xcvr-lsfslew = <2>;
732 nvidia,xcvr-lsrslew = <2>;
733 vbus-supply = <&vdd_5v0_sys>;
734 };
735
736 brcm_wifi_pwrseq: wifi-pwrseq {
737 compatible = "mmc-pwrseq-simple";
738
739 clocks = <&rtc_32k_wifi>;
740 clock-names = "ext_clock";
741
742 reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>;
743 post-power-on-delay-ms = <300>;
744 power-off-delay-us = <300>;
745 };
746
747 sdmmc1: mmc@c8000000 {
748 status = "okay";
749
750 #address-cells = <1>;
751 #size-cells = <0>;
752
753 assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
754 assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>;
755 assigned-clock-rates = <50000000>;
756
757 max-frequency = <50000000>;
758 keep-power-in-suspend;
759 bus-width = <4>;
760 non-removable;
761
762 mmc-pwrseq = <&brcm_wifi_pwrseq>;
763 vmmc-supply = <&vdd_3v3_sys>;
764 vqmmc-supply = <&vdd_1v8_sys>;
765
766 /* Azurewave AW-NH611 BCM4329 */
767 wifi@1 {
768 reg = <1>;
769 compatible = "brcm,bcm4329-fmac";
770 interrupt-parent = <&gpio>;
771 interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_LEVEL_HIGH>;
772 interrupt-names = "host-wake";
773 };
774 };
775
776 sdmmc3: mmc@c8000400 {
777 status = "okay";
778 bus-width = <4>;
779 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
780 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
781 vmmc-supply = <&vdd_3v3_sys>;
782 vqmmc-supply = <&vdd_3v3_sys>;
783 };
784
785 sdmmc4: mmc@c8000600 {
786 status = "okay";
787 bus-width = <8>;
788 vmmc-supply = <&vcore_emmc>;
789 vqmmc-supply = <&vdd_3v3_sys>;
790 non-removable;
791 };
792
793 mains: ac-adapter-detect {
794 compatible = "gpio-charger";
795 charger-type = "mains";
796 gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
797 };
798
799 backlight: backlight {
800 compatible = "pwm-backlight";
801
802 enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
803 power-supply = <&vdd_3v3_sys>;
804 pwms = <&pwm 2 41667>;
805
806 brightness-levels = <7 255>;
807 num-interpolated-steps = <248>;
808 default-brightness-level = <20>;
809 };
810
811 bat1010: battery-2s1p {
812 compatible = "simple-battery";
813 charge-full-design-microamp-hours = <3260000>;
814 energy-full-design-microwatt-hours = <24000000>;
815 operating-range-celsius = <0 40>;
816 };
817
818 /* PMIC has a built-in 32KHz oscillator which is used by PMC */
819 clk32k_in: clock@0 {
820 compatible = "fixed-clock";
821 #clock-cells = <0>;
822 clock-frequency = <32768>;
823 clock-output-names = "tps658621-out32k";
824 };
825
826 /*
827 * This standalone onboard fixed-clock always-ON 32KHz
828 * oscillator is used as a reference clock-source by the
829 * Azurewave WiFi/BT module.
830 */
831 rtc_32k_wifi: clock@1 {
832 compatible = "fixed-clock";
833 #clock-cells = <0>;
834 clock-frequency = <32768>;
835 clock-output-names = "kk3270032";
836 };
837
838 cpus {
839 cpu0: cpu@0 {
840 cpu-supply = <&vdd_cpu>;
841 operating-points-v2 = <&cpu0_opp_table>;
842 #cooling-cells = <2>;
843 };
844
845 cpu1: cpu@1 {
846 cpu-supply = <&vdd_cpu>;
847 operating-points-v2 = <&cpu0_opp_table>;
848 #cooling-cells = <2>;
849 };
850 };
851
852 display-panel {
853 compatible = "auo,b101ew05", "panel-lvds";
854
855 ddc-i2c-bus = <&panel_ddc>;
856 power-supply = <&vdd_pnl>;
857 backlight = <&backlight>;
858
859 width-mm = <218>;
860 height-mm = <135>;
861
862 data-mapping = "jeida-18";
863
864 panel-timing {
865 clock-frequency = <71200000>;
866 hactive = <1280>;
867 vactive = <800>;
868 hfront-porch = <8>;
869 hback-porch = <18>;
870 hsync-len = <184>;
871 vsync-len = <3>;
872 vfront-porch = <4>;
873 vback-porch = <8>;
874 };
875
876 port {
877 panel_input: endpoint {
878 remote-endpoint = <&lvds_encoder_output>;
879 };
880 };
881 };
882
883 gpio-keys {
884 compatible = "gpio-keys";
885
886 power {
887 label = "Power";
888 gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
889 linux,code = <KEY_POWER>;
890 debounce-interval = <10>;
891 wakeup-event-action = <EV_ACT_ASSERTED>;
892 wakeup-source;
893 };
894
895 rotation-lock {
896 label = "Rotate-lock";
897 gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>;
898 linux,code = <SW_ROTATE_LOCK>;
899 linux,input-type = <EV_SW>;
900 debounce-interval = <10>;
901 };
902
903 volume-up {
904 label = "Volume Up";
905 gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
906 linux,code = <KEY_VOLUMEUP>;
907 debounce-interval = <10>;
908 wakeup-event-action = <EV_ACT_ASSERTED>;
909 wakeup-source;
910 };
911
912 volume-down {
913 label = "Volume Down";
914 gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
915 linux,code = <KEY_VOLUMEDOWN>;
916 debounce-interval = <10>;
917 wakeup-event-action = <EV_ACT_ASSERTED>;
918 wakeup-source;
919 };
920 };
921
922 haptic-feedback {
923 compatible = "gpio-vibrator";
924 enable-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
925 vcc-supply = <&vdd_3v3_sys>;
926 };
927
928 lvds-encoder {
929 compatible = "ti,sn75lvds83", "lvds-encoder";
930
931 powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>;
932 power-supply = <&vdd_3v3_sys>;
933
934 ports {
935 #address-cells = <1>;
936 #size-cells = <0>;
937
938 port@0 {
939 reg = <0>;
940
941 lvds_encoder_input: endpoint {
942 remote-endpoint = <&lcd_output>;
943 };
944 };
945
946 port@1 {
947 reg = <1>;
948
949 lvds_encoder_output: endpoint {
950 remote-endpoint = <&panel_input>;
951 };
952 };
953 };
954 };
955
956 vdd_5v0_sys: regulator@0 {
957 compatible = "regulator-fixed";
958 regulator-name = "vdd_5v0";
959 regulator-min-microvolt = <5000000>;
960 regulator-max-microvolt = <5000000>;
961 regulator-always-on;
962 };
963
964 vdd_3v3_sys: regulator@1 {
965 compatible = "regulator-fixed";
966 regulator-name = "vdd_3v3_vs";
967 regulator-min-microvolt = <3300000>;
968 regulator-max-microvolt = <3300000>;
969 regulator-always-on;
970 vin-supply = <&vdd_5v0_sys>;
971 };
972
973 vdd_1v8_sys: regulator@2 {
974 compatible = "regulator-fixed";
975 regulator-name = "vdd_1v8_vs";
976 regulator-min-microvolt = <1800000>;
977 regulator-max-microvolt = <1800000>;
978 regulator-always-on;
979 vin-supply = <&vdd_5v0_sys>;
980 };
981
982 vdd_pnl: regulator@3 {
983 compatible = "regulator-fixed";
984 regulator-name = "vdd_panel";
985 regulator-min-microvolt = <3300000>;
986 regulator-max-microvolt = <3300000>;
987 regulator-enable-ramp-delay = <300000>;
988 gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
989 enable-active-high;
990 vin-supply = <&vdd_5v0_sys>;
991 };
992
993 sound {
994 compatible = "nvidia,tegra-audio-wm8903-picasso",
995 "nvidia,tegra-audio-wm8903";
996 nvidia,model = "Acer Iconia Tab A500 WM8903";
997
998 nvidia,audio-routing =
999 "Headphone Jack", "HPOUTR",
1000 "Headphone Jack", "HPOUTL",
1001 "Int Spk", "LINEOUTL",
1002 "Int Spk", "LINEOUTR",
1003 "Mic Jack", "MICBIAS",
1004 "IN2L", "Mic Jack",
1005 "IN2R", "Mic Jack",
1006 "IN1L", "Int Mic",
1007 "IN1R", "Int Mic";
1008
1009 nvidia,i2s-controller = <&tegra_i2s1>;
1010 nvidia,audio-codec = <&wm8903>;
1011
1012 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
1013 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>;
1014 nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>;
1015 nvidia,headset;
1016
1017 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
1018 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
1019 <&tegra_car TEGRA20_CLK_CDEV1>;
1020 clock-names = "pll_a", "pll_a_out0", "mclk";
1021 };
1022
1023 thermal-zones {
1024 skin-thermal {
1025 polling-delay-passive = <1000>; /* milliseconds */
1026 polling-delay = <0>; /* milliseconds */
1027
1028 thermal-sensors = <&nct1008 0>;
1029 };
1030
1031 cpu-thermal {
1032 polling-delay-passive = <1000>; /* milliseconds */
1033 polling-delay = <5000>; /* milliseconds */
1034
1035 thermal-sensors = <&nct1008 1>;
1036
1037 trips {
1038 trip0: cpu-alert0 {
1039 /* start throttling at 60C */
1040 temperature = <60000>;
1041 hysteresis = <200>;
1042 type = "passive";
1043 };
1044
1045 trip1: cpu-crit {
1046 /* shut down at 70C */
1047 temperature = <70000>;
1048 hysteresis = <2000>;
1049 type = "critical";
1050 };
1051 };
1052
1053 cooling-maps {
1054 map0 {
1055 trip = <&trip0>;
1056 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1057 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1058 };
1059 };
1060 };
1061 };
1062
1063 memory-controller@7000f400 {
1064 nvidia,use-ram-code;
1065
1066 emc-tables@0 {
1067 nvidia,ram-code = <0>; /* elpida-8gb */
1068 reg = <0>;
1069
1070 #address-cells = <1>;
1071 #size-cells = <0>;
1072
1073 emc-table@25000 {
1074 reg = <25000>;
1075 compatible = "nvidia,tegra20-emc-table";
1076 clock-frequency = <25000>;
1077 nvidia,emc-registers = <0x00000002 0x00000006
1078 0x00000003 0x00000003 0x00000006 0x00000004
1079 0x00000002 0x00000009 0x00000003 0x00000003
1080 0x00000002 0x00000002 0x00000002 0x00000004
1081 0x00000003 0x00000008 0x0000000b 0x0000004d
1082 0x00000000 0x00000003 0x00000003 0x00000003
1083 0x00000008 0x00000001 0x0000000a 0x00000004
1084 0x00000003 0x00000008 0x00000004 0x00000006
1085 0x00000002 0x00000068 0x00000000 0x00000003
1086 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1087 0x00070000 0x00000000 0x00000000 0x00000003
1088 0x00000000 0x00000000 0x00000000 0x00000000>;
1089 };
1090
1091 emc-table@50000 {
1092 reg = <50000>;
1093 compatible = "nvidia,tegra20-emc-table";
1094 clock-frequency = <50000>;
1095 nvidia,emc-registers = <0x00000003 0x00000007
1096 0x00000003 0x00000003 0x00000006 0x00000004
1097 0x00000002 0x00000009 0x00000003 0x00000003
1098 0x00000002 0x00000002 0x00000002 0x00000005
1099 0x00000003 0x00000008 0x0000000b 0x0000009f
1100 0x00000000 0x00000003 0x00000003 0x00000003
1101 0x00000008 0x00000001 0x0000000a 0x00000007
1102 0x00000003 0x00000008 0x00000004 0x00000006
1103 0x00000002 0x000000d0 0x00000000 0x00000000
1104 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1105 0x00070000 0x00000000 0x00000000 0x00000005
1106 0x00000000 0x00000000 0x00000000 0x00000000>;
1107 };
1108
1109 emc-table@75000 {
1110 reg = <75000>;
1111 compatible = "nvidia,tegra20-emc-table";
1112 clock-frequency = <75000>;
1113 nvidia,emc-registers = <0x00000005 0x0000000a
1114 0x00000004 0x00000003 0x00000006 0x00000004
1115 0x00000002 0x00000009 0x00000003 0x00000003
1116 0x00000002 0x00000002 0x00000002 0x00000005
1117 0x00000003 0x00000008 0x0000000b 0x000000ff
1118 0x00000000 0x00000003 0x00000003 0x00000003
1119 0x00000008 0x00000001 0x0000000a 0x0000000b
1120 0x00000003 0x00000008 0x00000004 0x00000006
1121 0x00000002 0x00000138 0x00000000 0x00000000
1122 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1123 0x00070000 0x00000000 0x00000000 0x00000007
1124 0x00000000 0x00000000 0x00000000 0x00000000>;
1125 };
1126
1127 emc-table@150000 {
1128 reg = <150000>;
1129 compatible = "nvidia,tegra20-emc-table";
1130 clock-frequency = <150000>;
1131 nvidia,emc-registers = <0x00000009 0x00000014
1132 0x00000007 0x00000003 0x00000006 0x00000004
1133 0x00000002 0x00000009 0x00000003 0x00000003
1134 0x00000002 0x00000002 0x00000002 0x00000005
1135 0x00000003 0x00000008 0x0000000b 0x0000021f
1136 0x00000000 0x00000003 0x00000003 0x00000003
1137 0x00000008 0x00000001 0x0000000a 0x00000015
1138 0x00000003 0x00000008 0x00000004 0x00000006
1139 0x00000002 0x00000270 0x00000000 0x00000001
1140 0x00000000 0x00000000 0x00000282 0xa07c04ae
1141 0x007dd510 0x00000000 0x00000000 0x0000000e
1142 0x00000000 0x00000000 0x00000000 0x00000000>;
1143 };
1144
1145 emc-table@300000 {
1146 reg = <300000>;
1147 compatible = "nvidia,tegra20-emc-table";
1148 clock-frequency = <300000>;
1149 nvidia,emc-registers = <0x00000012 0x00000027
1150 0x0000000d 0x00000006 0x00000007 0x00000005
1151 0x00000003 0x00000009 0x00000006 0x00000006
1152 0x00000003 0x00000003 0x00000002 0x00000006
1153 0x00000003 0x00000009 0x0000000c 0x0000045f
1154 0x00000000 0x00000004 0x00000004 0x00000006
1155 0x00000008 0x00000001 0x0000000e 0x0000002a
1156 0x00000003 0x0000000f 0x00000007 0x00000005
1157 0x00000002 0x000004e1 0x00000005 0x00000002
1158 0x00000000 0x00000000 0x00000282 0xe059048b
1159 0x007e1510 0x00000000 0x00000000 0x0000001b
1160 0x00000000 0x00000000 0x00000000 0x00000000>;
1161 };
1162 };
1163
1164 emc-tables@1 {
1165 nvidia,ram-code = <1>; /* elpida-4gb */
1166 reg = <1>;
1167
1168 #address-cells = <1>;
1169 #size-cells = <0>;
1170
1171 emc-table@25000 {
1172 reg = <25000>;
1173 compatible = "nvidia,tegra20-emc-table";
1174 clock-frequency = <25000>;
1175 nvidia,emc-registers = <0x00000002 0x00000006
1176 0x00000003 0x00000003 0x00000006 0x00000004
1177 0x00000002 0x00000009 0x00000003 0x00000003
1178 0x00000002 0x00000002 0x00000002 0x00000004
1179 0x00000003 0x00000008 0x0000000b 0x0000004d
1180 0x00000000 0x00000003 0x00000003 0x00000003
1181 0x00000008 0x00000001 0x0000000a 0x00000004
1182 0x00000003 0x00000008 0x00000004 0x00000006
1183 0x00000002 0x00000068 0x00000000 0x00000003
1184 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1185 0x0007c000 0x00000000 0x00000000 0x00000003
1186 0x00000000 0x00000000 0x00000000 0x00000000>;
1187 };
1188
1189 emc-table@50000 {
1190 reg = <50000>;
1191 compatible = "nvidia,tegra20-emc-table";
1192 clock-frequency = <50000>;
1193 nvidia,emc-registers = <0x00000003 0x00000007
1194 0x00000003 0x00000003 0x00000006 0x00000004
1195 0x00000002 0x00000009 0x00000003 0x00000003
1196 0x00000002 0x00000002 0x00000002 0x00000005
1197 0x00000003 0x00000008 0x0000000b 0x0000009f
1198 0x00000000 0x00000003 0x00000003 0x00000003
1199 0x00000008 0x00000001 0x0000000a 0x00000007
1200 0x00000003 0x00000008 0x00000004 0x00000006
1201 0x00000002 0x000000d0 0x00000000 0x00000000
1202 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1203 0x0007c000 0x00000000 0x00000000 0x00000005
1204 0x00000000 0x00000000 0x00000000 0x00000000>;
1205 };
1206
1207 emc-table@75000 {
1208 reg = <75000>;
1209 compatible = "nvidia,tegra20-emc-table";
1210 clock-frequency = <75000>;
1211 nvidia,emc-registers = <0x00000005 0x0000000a
1212 0x00000004 0x00000003 0x00000006 0x00000004
1213 0x00000002 0x00000009 0x00000003 0x00000003
1214 0x00000002 0x00000002 0x00000002 0x00000005
1215 0x00000003 0x00000008 0x0000000b 0x000000ff
1216 0x00000000 0x00000003 0x00000003 0x00000003
1217 0x00000008 0x00000001 0x0000000a 0x0000000b
1218 0x00000003 0x00000008 0x00000004 0x00000006
1219 0x00000002 0x00000138 0x00000000 0x00000000
1220 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1221 0x0007c000 0x00000000 0x00000000 0x00000007
1222 0x00000000 0x00000000 0x00000000 0x00000000>;
1223 };
1224
1225 emc-table@150000 {
1226 reg = <150000>;
1227 compatible = "nvidia,tegra20-emc-table";
1228 clock-frequency = <150000>;
1229 nvidia,emc-registers = <0x00000009 0x00000014
1230 0x00000007 0x00000003 0x00000006 0x00000004
1231 0x00000002 0x00000009 0x00000003 0x00000003
1232 0x00000002 0x00000002 0x00000002 0x00000005
1233 0x00000003 0x00000008 0x0000000b 0x0000021f
1234 0x00000000 0x00000003 0x00000003 0x00000003
1235 0x00000008 0x00000001 0x0000000a 0x00000015
1236 0x00000003 0x00000008 0x00000004 0x00000006
1237 0x00000002 0x00000270 0x00000000 0x00000001
1238 0x00000000 0x00000000 0x00000282 0xa07c04ae
1239 0x007e4010 0x00000000 0x00000000 0x0000000e
1240 0x00000000 0x00000000 0x00000000 0x00000000>;
1241 };
1242
1243 emc-table@300000 {
1244 reg = <300000>;
1245 compatible = "nvidia,tegra20-emc-table";
1246 clock-frequency = <300000>;
1247 nvidia,emc-registers = <0x00000012 0x00000027
1248 0x0000000d 0x00000006 0x00000007 0x00000005
1249 0x00000003 0x00000009 0x00000006 0x00000006
1250 0x00000003 0x00000003 0x00000002 0x00000006
1251 0x00000003 0x00000009 0x0000000c 0x0000045f
1252 0x00000000 0x00000004 0x00000004 0x00000006
1253 0x00000008 0x00000001 0x0000000e 0x0000002a
1254 0x00000003 0x0000000f 0x00000007 0x00000005
1255 0x00000002 0x000004e1 0x00000005 0x00000002
1256 0x00000000 0x00000000 0x00000282 0xe059048b
1257 0x007e0010 0x00000000 0x00000000 0x0000001b
1258 0x00000000 0x00000000 0x00000000 0x00000000>;
1259 };
1260 };
1261
1262 emc-tables@2 {
1263 nvidia,ram-code = <2>; /* hynix-8gb */
1264 reg = <2>;
1265
1266 #address-cells = <1>;
1267 #size-cells = <0>;
1268
1269 emc-table@25000 {
1270 reg = <25000>;
1271 compatible = "nvidia,tegra20-emc-table";
1272 clock-frequency = <25000>;
1273 nvidia,emc-registers = <0x00000002 0x00000006
1274 0x00000003 0x00000003 0x00000006 0x00000004
1275 0x00000002 0x00000009 0x00000003 0x00000003
1276 0x00000002 0x00000002 0x00000002 0x00000004
1277 0x00000003 0x00000008 0x0000000b 0x0000004d
1278 0x00000000 0x00000003 0x00000003 0x00000003
1279 0x00000008 0x00000001 0x0000000a 0x00000004
1280 0x00000003 0x00000008 0x00000004 0x00000006
1281 0x00000002 0x00000068 0x00000000 0x00000003
1282 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1283 0x00070000 0x00000000 0x00000000 0x00000003
1284 0x00000000 0x00000000 0x00000000 0x00000000>;
1285 };
1286
1287 emc-table@50000 {
1288 reg = <50000>;
1289 compatible = "nvidia,tegra20-emc-table";
1290 clock-frequency = <50000>;
1291 nvidia,emc-registers = <0x00000003 0x00000007
1292 0x00000003 0x00000003 0x00000006 0x00000004
1293 0x00000002 0x00000009 0x00000003 0x00000003
1294 0x00000002 0x00000002 0x00000002 0x00000005
1295 0x00000003 0x00000008 0x0000000b 0x0000009f
1296 0x00000000 0x00000003 0x00000003 0x00000003
1297 0x00000008 0x00000001 0x0000000a 0x00000007
1298 0x00000003 0x00000008 0x00000004 0x00000006
1299 0x00000002 0x000000d0 0x00000000 0x00000000
1300 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1301 0x00070000 0x00000000 0x00000000 0x00000005
1302 0x00000000 0x00000000 0x00000000 0x00000000>;
1303 };
1304
1305 emc-table@75000 {
1306 reg = <75000>;
1307 compatible = "nvidia,tegra20-emc-table";
1308 clock-frequency = <75000>;
1309 nvidia,emc-registers = <0x00000005 0x0000000a
1310 0x00000004 0x00000003 0x00000006 0x00000004
1311 0x00000002 0x00000009 0x00000003 0x00000003
1312 0x00000002 0x00000002 0x00000002 0x00000005
1313 0x00000003 0x00000008 0x0000000b 0x000000ff
1314 0x00000000 0x00000003 0x00000003 0x00000003
1315 0x00000008 0x00000001 0x0000000a 0x0000000b
1316 0x00000003 0x00000008 0x00000004 0x00000006
1317 0x00000002 0x00000138 0x00000000 0x00000000
1318 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1319 0x00070000 0x00000000 0x00000000 0x00000007
1320 0x00000000 0x00000000 0x00000000 0x00000000>;
1321 };
1322
1323 emc-table@150000 {
1324 reg = <150000>;
1325 compatible = "nvidia,tegra20-emc-table";
1326 clock-frequency = <150000>;
1327 nvidia,emc-registers = <0x00000009 0x00000014
1328 0x00000007 0x00000003 0x00000006 0x00000004
1329 0x00000002 0x00000009 0x00000003 0x00000003
1330 0x00000002 0x00000002 0x00000002 0x00000005
1331 0x00000003 0x00000008 0x0000000b 0x0000021f
1332 0x00000000 0x00000003 0x00000003 0x00000003
1333 0x00000008 0x00000001 0x0000000a 0x00000015
1334 0x00000003 0x00000008 0x00000004 0x00000006
1335 0x00000002 0x00000270 0x00000000 0x00000001
1336 0x00000000 0x00000000 0x00000282 0xa07c04ae
1337 0x007dd010 0x00000000 0x00000000 0x0000000e
1338 0x00000000 0x00000000 0x00000000 0x00000000>;
1339 };
1340
1341 emc-table@300000 {
1342 reg = <300000>;
1343 compatible = "nvidia,tegra20-emc-table";
1344 clock-frequency = <300000>;
1345 nvidia,emc-registers = <0x00000012 0x00000027
1346 0x0000000d 0x00000006 0x00000007 0x00000005
1347 0x00000003 0x00000009 0x00000006 0x00000006
1348 0x00000003 0x00000003 0x00000002 0x00000006
1349 0x00000003 0x00000009 0x0000000c 0x0000045f
1350 0x00000000 0x00000004 0x00000004 0x00000006
1351 0x00000008 0x00000001 0x0000000e 0x0000002a
1352 0x00000003 0x0000000f 0x00000007 0x00000005
1353 0x00000002 0x000004e1 0x00000005 0x00000002
1354 0x00000000 0x00000000 0x00000282 0xe059048b
1355 0x007e2010 0x00000000 0x00000000 0x0000001b
1356 0x00000000 0x00000000 0x00000000 0x00000000>;
1357 };
1358 };
1359
1360 emc-tables@3 {
1361 nvidia,ram-code = <3>; /* hynix-4gb */
1362 reg = <3>;
1363
1364 #address-cells = <1>;
1365 #size-cells = <0>;
1366
1367 emc-table@25000 {
1368 reg = <25000>;
1369 compatible = "nvidia,tegra20-emc-table";
1370 clock-frequency = <25000>;
1371 nvidia,emc-registers = <0x00000002 0x00000006
1372 0x00000003 0x00000003 0x00000006 0x00000004
1373 0x00000002 0x00000009 0x00000003 0x00000003
1374 0x00000002 0x00000002 0x00000002 0x00000004
1375 0x00000003 0x00000008 0x0000000b 0x0000004d
1376 0x00000000 0x00000003 0x00000003 0x00000003
1377 0x00000008 0x00000001 0x0000000a 0x00000004
1378 0x00000003 0x00000008 0x00000004 0x00000006
1379 0x00000002 0x00000068 0x00000000 0x00000003
1380 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1381 0x0007c000 0x00000000 0x00000000 0x00000003
1382 0x00000000 0x00000000 0x00000000 0x00000000>;
1383 };
1384
1385 emc-table@50000 {
1386 reg = <50000>;
1387 compatible = "nvidia,tegra20-emc-table";
1388 clock-frequency = <50000>;
1389 nvidia,emc-registers = <0x00000003 0x00000007
1390 0x00000003 0x00000003 0x00000006 0x00000004
1391 0x00000002 0x00000009 0x00000003 0x00000003
1392 0x00000002 0x00000002 0x00000002 0x00000005
1393 0x00000003 0x00000008 0x0000000b 0x0000009f
1394 0x00000000 0x00000003 0x00000003 0x00000003
1395 0x00000008 0x00000001 0x0000000a 0x00000007
1396 0x00000003 0x00000008 0x00000004 0x00000006
1397 0x00000002 0x000000d0 0x00000000 0x00000000
1398 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1399 0x0007c000 0x00078000 0x00000000 0x00000005
1400 0x00000000 0x00000000 0x00000000 0x00000000>;
1401 };
1402
1403 emc-table@75000 {
1404 reg = <75000>;
1405 compatible = "nvidia,tegra20-emc-table";
1406 clock-frequency = <75000>;
1407 nvidia,emc-registers = <0x00000005 0x0000000a
1408 0x00000004 0x00000003 0x00000006 0x00000004
1409 0x00000002 0x00000009 0x00000003 0x00000003
1410 0x00000002 0x00000002 0x00000002 0x00000005
1411 0x00000003 0x00000008 0x0000000b 0x000000ff
1412 0x00000000 0x00000003 0x00000003 0x00000003
1413 0x00000008 0x00000001 0x0000000a 0x0000000b
1414 0x00000003 0x00000008 0x00000004 0x00000006
1415 0x00000002 0x00000138 0x00000000 0x00000000
1416 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1417 0x0007c000 0x00000000 0x00000000 0x00000007
1418 0x00000000 0x00000000 0x00000000 0x00000000>;
1419 };
1420
1421 emc-table@150000 {
1422 reg = <150000>;
1423 compatible = "nvidia,tegra20-emc-table";
1424 clock-frequency = <150000>;
1425 nvidia,emc-registers = <0x00000009 0x00000014
1426 0x00000007 0x00000003 0x00000006 0x00000004
1427 0x00000002 0x00000009 0x00000003 0x00000003
1428 0x00000002 0x00000002 0x00000002 0x00000005
1429 0x00000003 0x00000008 0x0000000b 0x0000021f
1430 0x00000000 0x00000003 0x00000003 0x00000003
1431 0x00000008 0x00000001 0x0000000a 0x00000015
1432 0x00000003 0x00000008 0x00000004 0x00000006
1433 0x00000002 0x00000270 0x00000000 0x00000001
1434 0x00000000 0x00000000 0x00000282 0xa07c04ae
1435 0x007e4010 0x00000000 0x00000000 0x0000000e
1436 0x00000000 0x00000000 0x00000000 0x00000000>;
1437 };
1438
1439 emc-table@300000 {
1440 reg = <300000>;
1441 compatible = "nvidia,tegra20-emc-table";
1442 clock-frequency = <300000>;
1443 nvidia,emc-registers = <0x00000012 0x00000027
1444 0x0000000d 0x00000006 0x00000007 0x00000005
1445 0x00000003 0x00000009 0x00000006 0x00000006
1446 0x00000003 0x00000003 0x00000002 0x00000006
1447 0x00000003 0x00000009 0x0000000c 0x0000045f
1448 0x00000000 0x00000004 0x00000004 0x00000006
1449 0x00000008 0x00000001 0x0000000e 0x0000002a
1450 0x00000003 0x0000000f 0x00000007 0x00000005
1451 0x00000002 0x000004e1 0x00000005 0x00000002
1452 0x00000000 0x00000000 0x00000282 0xe059048b
1453 0x007e0010 0x00000000 0x00000000 0x0000001b
1454 0x00000000 0x00000000 0x00000000 0x00000000>;
1455 };
1456 };
1457 };
1458};
1459
1460&emc_icc_dvfs_opp_table {
1461 /delete-node/ opp@666000000;
1462 /delete-node/ opp@760000000;
1463};