Loading...
Note: File does not exist in v4.17.
1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/input/gpio-keys.h>
5#include <dt-bindings/input/input.h>
6#include <dt-bindings/thermal/thermal.h>
7
8#include "tegra20.dtsi"
9#include "tegra20-cpu-opp.dtsi"
10#include "tegra20-cpu-opp-microvolt.dtsi"
11
12/ {
13 model = "Acer Iconia Tab A500";
14 compatible = "acer,picasso", "nvidia,tegra20";
15
16 aliases {
17 rtc0 = &pmic;
18 rtc1 = "/rtc@7000e000";
19
20 serial0 = &uartd; /* Docking station */
21 serial1 = &uartc; /* Bluetooth */
22 serial2 = &uartb; /* GPS */
23 };
24
25 /*
26 * The decompressor and also some bootloaders rely on a
27 * pre-existing /chosen node to be available to insert the
28 * command line and merge other ATAGS info.
29 */
30 chosen {};
31
32 memory@0 {
33 reg = <0x00000000 0x40000000>;
34 };
35
36 reserved-memory {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 ranges;
40
41 ramoops@2ffe0000 {
42 compatible = "ramoops";
43 reg = <0x2ffe0000 0x10000>; /* 64kB */
44 console-size = <0x8000>; /* 32kB */
45 record-size = <0x400>; /* 1kB */
46 ecc-size = <16>;
47 };
48
49 linux,cma@30000000 {
50 compatible = "shared-dma-pool";
51 alloc-ranges = <0x30000000 0x10000000>;
52 size = <0x10000000>; /* 256MiB */
53 linux,cma-default;
54 reusable;
55 };
56 };
57
58 host1x@50000000 {
59 dc@54200000 {
60 rgb {
61 status = "okay";
62
63 port@0 {
64 lcd_output: endpoint {
65 remote-endpoint = <&lvds_encoder_input>;
66 bus-width = <18>;
67 };
68 };
69 };
70 };
71
72 hdmi@54280000 {
73 status = "okay";
74
75 vdd-supply = <&hdmi_vdd_reg>;
76 pll-supply = <&hdmi_pll_reg>;
77 hdmi-supply = <&vdd_5v0_sys>;
78
79 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
80 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
81 GPIO_ACTIVE_HIGH>;
82 };
83 };
84
85 pinmux@70000014 {
86 pinctrl-names = "default";
87 pinctrl-0 = <&state_default>;
88
89 state_default: pinmux {
90 ata {
91 nvidia,pins = "ata";
92 nvidia,function = "ide";
93 };
94 atb {
95 nvidia,pins = "atb", "gma", "gme";
96 nvidia,function = "sdio4";
97 };
98 atc {
99 nvidia,pins = "atc";
100 nvidia,function = "nand";
101 };
102 atd {
103 nvidia,pins = "atd", "ate", "gmb", "spia",
104 "spib", "spic";
105 nvidia,function = "gmi";
106 };
107 cdev1 {
108 nvidia,pins = "cdev1";
109 nvidia,function = "plla_out";
110 };
111 cdev2 {
112 nvidia,pins = "cdev2";
113 nvidia,function = "pllp_out4";
114 };
115 crtp {
116 nvidia,pins = "crtp", "lm1";
117 nvidia,function = "crt";
118 };
119 csus {
120 nvidia,pins = "csus";
121 nvidia,function = "vi_sensor_clk";
122 };
123 dap1 {
124 nvidia,pins = "dap1";
125 nvidia,function = "dap1";
126 };
127 dap2 {
128 nvidia,pins = "dap2";
129 nvidia,function = "dap2";
130 };
131 dap3 {
132 nvidia,pins = "dap3";
133 nvidia,function = "dap3";
134 };
135 dap4 {
136 nvidia,pins = "dap4";
137 nvidia,function = "dap4";
138 };
139 dta {
140 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
141 nvidia,function = "vi";
142 };
143 dtf {
144 nvidia,pins = "dtf";
145 nvidia,function = "i2c3";
146 };
147 gmc {
148 nvidia,pins = "gmc";
149 nvidia,function = "uartd";
150 };
151 gmd {
152 nvidia,pins = "gmd";
153 nvidia,function = "sflash";
154 };
155 gpu {
156 nvidia,pins = "gpu";
157 nvidia,function = "pwm";
158 };
159 gpu7 {
160 nvidia,pins = "gpu7";
161 nvidia,function = "rtck";
162 };
163 gpv {
164 nvidia,pins = "gpv", "slxa";
165 nvidia,function = "pcie";
166 };
167 hdint {
168 nvidia,pins = "hdint";
169 nvidia,function = "hdmi";
170 };
171 i2cp {
172 nvidia,pins = "i2cp";
173 nvidia,function = "i2cp";
174 };
175 irrx {
176 nvidia,pins = "irrx", "irtx";
177 nvidia,function = "uartb";
178 };
179 kbca {
180 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
181 "kbce", "kbcf";
182 nvidia,function = "kbc";
183 };
184 lcsn {
185 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
186 "lsdi", "lvp0";
187 nvidia,function = "rsvd4";
188 };
189 ld0 {
190 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
191 "ld5", "ld6", "ld7", "ld8", "ld9",
192 "ld10", "ld11", "ld12", "ld13", "ld14",
193 "ld15", "ld16", "ld17", "ldi", "lhp0",
194 "lhp1", "lhp2", "lhs", "lpp", "lsc0",
195 "lsc1", "lsck", "lsda", "lspi", "lvp1",
196 "lvs";
197 nvidia,function = "displaya";
198 };
199 owc {
200 nvidia,pins = "owc", "spdi", "spdo", "uac";
201 nvidia,function = "rsvd2";
202 };
203 pmc {
204 nvidia,pins = "pmc";
205 nvidia,function = "pwr_on";
206 };
207 rm {
208 nvidia,pins = "rm";
209 nvidia,function = "i2c1";
210 };
211 sdb {
212 nvidia,pins = "sdb", "sdc", "sdd", "slxc", "slxk";
213 nvidia,function = "sdio3";
214 };
215 sdio1 {
216 nvidia,pins = "sdio1";
217 nvidia,function = "sdio1";
218 };
219 slxd {
220 nvidia,pins = "slxd";
221 nvidia,function = "spdif";
222 };
223 spid {
224 nvidia,pins = "spid", "spie", "spif";
225 nvidia,function = "spi1";
226 };
227 spig {
228 nvidia,pins = "spig", "spih";
229 nvidia,function = "spi2_alt";
230 };
231 uaa {
232 nvidia,pins = "uaa", "uab", "uda";
233 nvidia,function = "ulpi";
234 };
235 uad {
236 nvidia,pins = "uad";
237 nvidia,function = "irda";
238 };
239 uca {
240 nvidia,pins = "uca", "ucb";
241 nvidia,function = "uartc";
242 };
243 conf_ata {
244 nvidia,pins = "ata", "atb", "atc", "atd",
245 "cdev1", "cdev2", "csus", "dap1",
246 "dap4", "dte", "dtf", "gma", "gmc",
247 "gme", "gpu", "gpu7", "gpv", "i2cp",
248 "irrx", "irtx", "pta", "rm",
249 "sdc", "sdd", "slxc", "slxd", "slxk",
250 "spdi", "spdo", "uac", "uad", "uda";
251 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
252 nvidia,tristate = <TEGRA_PIN_DISABLE>;
253 };
254 conf_ate {
255 nvidia,pins = "ate", "dap2", "dap3",
256 "gmd", "owc", "spia", "spib", "spic",
257 "spid", "spie";
258 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
259 nvidia,tristate = <TEGRA_PIN_ENABLE>;
260 };
261 conf_ck32 {
262 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
263 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
264 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
265 };
266 conf_crtp {
267 nvidia,pins = "crtp", "gmb", "slxa", "spig",
268 "spih";
269 nvidia,pull = <TEGRA_PIN_PULL_UP>;
270 nvidia,tristate = <TEGRA_PIN_ENABLE>;
271 };
272 conf_dta {
273 nvidia,pins = "dta", "dtb", "dtc", "dtd", "kbcb";
274 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
275 nvidia,tristate = <TEGRA_PIN_DISABLE>;
276 };
277 conf_dte {
278 nvidia,pins = "spif";
279 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
280 nvidia,tristate = <TEGRA_PIN_ENABLE>;
281 };
282 conf_hdint {
283 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
284 "lpw1", "lsck", "lsda", "lsdi",
285 "lvp0";
286 nvidia,tristate = <TEGRA_PIN_ENABLE>;
287 };
288 conf_kbca {
289 nvidia,pins = "kbca", "kbcc", "kbcd",
290 "kbce", "kbcf", "sdio1", "uaa",
291 "uab", "uca", "ucb";
292 nvidia,pull = <TEGRA_PIN_PULL_UP>;
293 nvidia,tristate = <TEGRA_PIN_DISABLE>;
294 };
295 conf_lc {
296 nvidia,pins = "lc", "ls";
297 nvidia,pull = <TEGRA_PIN_PULL_UP>;
298 };
299 conf_ld0 {
300 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
301 "ld5", "ld6", "ld7", "ld8", "ld9",
302 "ld10", "ld11", "ld12", "ld13", "ld14",
303 "ld15", "ld16", "ld17", "ldi", "lhp0",
304 "lhp1", "lhp2", "lhs", "lm0", "lpp",
305 "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
306 "lvp1", "lvs", "pmc", "sdb";
307 nvidia,tristate = <TEGRA_PIN_DISABLE>;
308 };
309 conf_ld17_0 {
310 nvidia,pins = "ld17_0";
311 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
312 };
313 drive_ddc {
314 nvidia,pins = "drive_ddc",
315 "drive_vi1",
316 "drive_sdio1";
317 nvidia,schmitt = <TEGRA_PIN_ENABLE>;
318 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_4>;
319 };
320 drive_dbg {
321 nvidia,pins = "drive_dbg",
322 "drive_vi2",
323 "drive_at1",
324 "drive_ao1";
325 nvidia,schmitt = <TEGRA_PIN_ENABLE>;
326 nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_4>;
327 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
328 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
329 };
330 };
331
332 state_i2cmux_ddc: pinmux_i2cmux_ddc {
333 ddc {
334 nvidia,pins = "ddc";
335 nvidia,function = "i2c2";
336 };
337 pta {
338 nvidia,pins = "pta";
339 nvidia,function = "rsvd4";
340 };
341 };
342
343 state_i2cmux_pta: pinmux_i2cmux_pta {
344 ddc {
345 nvidia,pins = "ddc";
346 nvidia,function = "rsvd4";
347 };
348 pta {
349 nvidia,pins = "pta";
350 nvidia,function = "i2c2";
351 };
352 };
353
354 state_i2cmux_idle: pinmux_i2cmux_idle {
355 ddc {
356 nvidia,pins = "ddc";
357 nvidia,function = "rsvd4";
358 };
359 pta {
360 nvidia,pins = "pta";
361 nvidia,function = "rsvd4";
362 };
363 };
364 };
365
366 tegra_i2s1: i2s@70002800 {
367 status = "okay";
368 };
369
370 uartb: serial@70006040 {
371 compatible = "nvidia,tegra20-hsuart";
372 /* GPS BCM4751 */
373 };
374
375 uartc: serial@70006200 {
376 compatible = "nvidia,tegra20-hsuart";
377 status = "okay";
378
379 /* Azurewave AW-NH665 BCM4329B1 */
380 bluetooth {
381 compatible = "brcm,bcm4329-bt";
382
383 /* PLLP 216MHz / 16 / 4 */
384 max-speed = <3375000>;
385
386 clocks = <&rtc_32k_wifi>;
387 clock-names = "txco";
388
389 vbat-supply = <&vdd_3v3_sys>;
390 vddio-supply = <&vdd_1v8_sys>;
391
392 device-wakeup-gpios = <&gpio TEGRA_GPIO(U, 1) GPIO_ACTIVE_HIGH>;
393 host-wakeup-gpios = <&gpio TEGRA_GPIO(U, 6) GPIO_ACTIVE_HIGH>;
394 shutdown-gpios = <&gpio TEGRA_GPIO(U, 0) GPIO_ACTIVE_HIGH>;
395 };
396 };
397
398 uartd: serial@70006300 {
399 /* Docking station */
400 };
401
402 i2c@7000c000 {
403 clock-frequency = <400000>;
404 status = "okay";
405
406 wm8903: audio-codec@1a {
407 compatible = "wlf,wm8903";
408 reg = <0x1a>;
409
410 interrupt-parent = <&gpio>;
411 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
412
413 gpio-controller;
414 #gpio-cells = <2>;
415
416 gpio-cfg = <
417 0x0000 /* MIC_LR_OUT# GPIO, output, low */
418 0x0000 /* FM2018-enable GPIO, output, low */
419 0x0000 /* Speaker-enable GPIO, output, low */
420 0x0200 /* Interrupt, output */
421 0x01a0 /* BCLK, input, active high */
422 >;
423
424 AVDD-supply = <&vdd_1v8_sys>;
425 CPVDD-supply = <&vdd_1v8_sys>;
426 DBVDD-supply = <&vdd_1v8_sys>;
427 DCVDD-supply = <&vdd_1v8_sys>;
428 };
429
430 touchscreen@4c {
431 compatible = "atmel,maxtouch";
432 reg = <0x4c>;
433
434 atmel,cfg_name = "maxtouch-acer-iconia-tab-a500.cfg";
435
436 interrupt-parent = <&gpio>;
437 interrupts = <TEGRA_GPIO(V, 6) IRQ_TYPE_LEVEL_LOW>;
438
439 reset-gpios = <&gpio TEGRA_GPIO(Q, 7) GPIO_ACTIVE_HIGH>;
440
441 avdd-supply = <&vdd_3v3_sys>;
442 vdd-supply = <&vdd_3v3_sys>;
443 };
444
445 gyroscope@68 {
446 compatible = "invensense,mpu3050";
447 reg = <0x68>;
448
449 interrupt-parent = <&gpio>;
450 interrupts = <TEGRA_GPIO(Z, 4) IRQ_TYPE_EDGE_RISING>;
451
452 vdd-supply = <&vdd_3v3_sys>;
453 vlogic-supply = <&vdd_1v8_sys>;
454
455 mount-matrix = "0", "1", "0",
456 "1", "0", "0",
457 "0", "0", "-1";
458
459 i2c-gate {
460 #address-cells = <1>;
461 #size-cells = <0>;
462
463 accelerometer@f {
464 compatible = "kionix,kxtf9";
465 reg = <0x0f>;
466
467 interrupt-parent = <&gpio>;
468 interrupts = <TEGRA_GPIO(S, 7) IRQ_TYPE_EDGE_RISING>;
469
470 mount-matrix = "0", "1", "0",
471 "1", "0", "0",
472 "0", "0", "-1";
473 };
474 };
475 };
476 };
477
478 i2c@7000c400 {
479 clock-frequency = <10000>;
480 status = "okay";
481 };
482
483 i2cmux {
484 compatible = "i2c-mux-pinctrl";
485 #address-cells = <1>;
486 #size-cells = <0>;
487
488 i2c-parent = <&{/i2c@7000c400}>;
489
490 pinctrl-names = "ddc", "pta", "idle";
491 pinctrl-0 = <&state_i2cmux_ddc>;
492 pinctrl-1 = <&state_i2cmux_pta>;
493 pinctrl-2 = <&state_i2cmux_idle>;
494
495 hdmi_ddc: i2c@0 {
496 reg = <0>;
497 #address-cells = <1>;
498 #size-cells = <0>;
499 };
500
501 panel_ddc: i2c@1 {
502 reg = <1>;
503 #address-cells = <1>;
504 #size-cells = <0>;
505 };
506 };
507
508 pwm: pwm@7000a000 {
509 status = "okay";
510 };
511
512 i2c@7000d000 {
513 clock-frequency = <100000>;
514 status = "okay";
515
516 magnetometer@c {
517 compatible = "ak,ak8975";
518 reg = <0x0c>;
519
520 interrupt-parent = <&gpio>;
521 interrupts = <TEGRA_GPIO(N, 5) IRQ_TYPE_EDGE_RISING>;
522
523 vdd-supply = <&vdd_3v3_sys>;
524 vid-supply = <&vdd_1v8_sys>;
525
526 mount-matrix = "1", "0", "0",
527 "0", "-1", "0",
528 "0", "0", "-1";
529 };
530
531 pmic: pmic@34 {
532 compatible = "ti,tps6586x";
533 reg = <0x34>;
534
535 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
536
537 #gpio-cells = <2>;
538 gpio-controller;
539
540 sys-supply = <&vdd_5v0_sys>;
541 vin-sm0-supply = <&sys_reg>;
542 vin-sm1-supply = <&sys_reg>;
543 vin-sm2-supply = <&sys_reg>;
544 vinldo01-supply = <&sm2_reg>;
545 vinldo23-supply = <&sm2_reg>;
546 vinldo4-supply = <&sm2_reg>;
547 vinldo678-supply = <&sm2_reg>;
548 vinldo9-supply = <&sm2_reg>;
549
550 regulators {
551 sys_reg: sys {
552 regulator-name = "vdd_sys";
553 regulator-always-on;
554 };
555
556 vdd_core: sm0 {
557 regulator-name = "vdd_sm0,vdd_core";
558 regulator-min-microvolt = <1200000>;
559 regulator-max-microvolt = <1300000>;
560 regulator-coupled-with = <&rtc_vdd &vdd_cpu>;
561 regulator-coupled-max-spread = <170000 550000>;
562 regulator-always-on;
563 regulator-boot-on;
564
565 nvidia,tegra-core-regulator;
566 };
567
568 vdd_cpu: sm1 {
569 regulator-name = "vdd_sm1,vdd_cpu";
570 regulator-min-microvolt = <750000>;
571 regulator-max-microvolt = <1125000>;
572 regulator-coupled-with = <&vdd_core &rtc_vdd>;
573 regulator-coupled-max-spread = <550000 550000>;
574 regulator-always-on;
575 regulator-boot-on;
576
577 nvidia,tegra-cpu-regulator;
578 };
579
580 sm2_reg: sm2 {
581 regulator-name = "vdd_sm2,vin_ldo*";
582 regulator-min-microvolt = <3700000>;
583 regulator-max-microvolt = <3700000>;
584 regulator-always-on;
585 };
586
587 /* LDO0 is not connected to anything */
588
589 ldo1 {
590 regulator-name = "vdd_ldo1,avdd_pll*";
591 regulator-min-microvolt = <1100000>;
592 regulator-max-microvolt = <1100000>;
593 regulator-always-on;
594 regulator-boot-on;
595 };
596
597 rtc_vdd: ldo2 {
598 regulator-name = "vdd_ldo2,vdd_rtc";
599 regulator-min-microvolt = <1200000>;
600 regulator-max-microvolt = <1300000>;
601 regulator-coupled-with = <&vdd_core &vdd_cpu>;
602 regulator-coupled-max-spread = <170000 550000>;
603 regulator-always-on;
604 regulator-boot-on;
605
606 nvidia,tegra-rtc-regulator;
607 };
608
609 ldo3 {
610 regulator-name = "vdd_ldo3,avdd_usb*";
611 regulator-min-microvolt = <3300000>;
612 regulator-max-microvolt = <3300000>;
613 regulator-always-on;
614 };
615
616 ldo4 {
617 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
618 regulator-min-microvolt = <1800000>;
619 regulator-max-microvolt = <1800000>;
620 regulator-always-on;
621 regulator-boot-on;
622 };
623
624 vcore_emmc: ldo5 {
625 regulator-name = "vdd_ldo5,vcore_mmc";
626 regulator-min-microvolt = <2850000>;
627 regulator-max-microvolt = <2850000>;
628 regulator-always-on;
629 };
630
631 avdd_vdac_reg: ldo6 {
632 regulator-name = "vdd_ldo6,avdd_vdac";
633 regulator-min-microvolt = <2850000>;
634 regulator-max-microvolt = <2850000>;
635 };
636
637 hdmi_vdd_reg: ldo7 {
638 regulator-name = "vdd_ldo7,avdd_hdmi";
639 regulator-min-microvolt = <3300000>;
640 regulator-max-microvolt = <3300000>;
641 };
642
643 hdmi_pll_reg: ldo8 {
644 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
645 regulator-min-microvolt = <1800000>;
646 regulator-max-microvolt = <1800000>;
647 };
648
649 ldo9 {
650 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
651 regulator-min-microvolt = <2850000>;
652 regulator-max-microvolt = <2850000>;
653 regulator-always-on;
654 regulator-boot-on;
655 };
656
657 ldo_rtc {
658 regulator-name = "vdd_rtc_out,vdd_cell";
659 regulator-min-microvolt = <3300000>;
660 regulator-max-microvolt = <3300000>;
661 regulator-always-on;
662 regulator-boot-on;
663 };
664 };
665 };
666
667 nct1008: temperature-sensor@4c {
668 compatible = "onnn,nct1008";
669 reg = <0x4c>;
670 vcc-supply = <&vdd_3v3_sys>;
671 #thermal-sensor-cells = <1>;
672 };
673 };
674
675 pmc@7000e400 {
676 nvidia,invert-interrupt;
677 nvidia,suspend-mode = <1>;
678 nvidia,cpu-pwr-good-time = <2000>;
679 nvidia,cpu-pwr-off-time = <100>;
680 nvidia,core-pwr-good-time = <3845 3845>;
681 nvidia,core-pwr-off-time = <458>;
682 nvidia,sys-clock-req-active-high;
683 };
684
685 usb@c5000000 {
686 compatible = "nvidia,tegra20-udc";
687 status = "okay";
688 dr_mode = "peripheral";
689 };
690
691 usb-phy@c5000000 {
692 status = "okay";
693 dr_mode = "peripheral";
694 nvidia,xcvr-setup-use-fuses;
695 nvidia,xcvr-lsfslew = <2>;
696 nvidia,xcvr-lsrslew = <2>;
697 vbus-supply = <&vdd_vbus1>;
698 };
699
700 usb@c5008000 {
701 status = "okay";
702 };
703
704 usb-phy@c5008000 {
705 status = "okay";
706 nvidia,xcvr-setup-use-fuses;
707 nvidia,xcvr-lsfslew = <2>;
708 nvidia,xcvr-lsrslew = <2>;
709 vbus-supply = <&vdd_vbus3>;
710 };
711
712 brcm_wifi_pwrseq: wifi-pwrseq {
713 compatible = "mmc-pwrseq-simple";
714
715 clocks = <&rtc_32k_wifi>;
716 clock-names = "ext_clock";
717
718 reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>;
719 post-power-on-delay-ms = <300>;
720 power-off-delay-us = <300>;
721 };
722
723 mmc@c8000000 {
724 status = "okay";
725
726 #address-cells = <1>;
727 #size-cells = <0>;
728
729 max-frequency = <25000000>;
730 keep-power-in-suspend;
731 bus-width = <4>;
732 non-removable;
733
734 mmc-pwrseq = <&brcm_wifi_pwrseq>;
735 vmmc-supply = <&vdd_3v3_sys>;
736 vqmmc-supply = <&vdd_3v3_sys>;
737
738 /* Azurewave AW-NH611 BCM4329 */
739 wifi@1 {
740 reg = <1>;
741 compatible = "brcm,bcm4329-fmac";
742 interrupt-parent = <&gpio>;
743 interrupts = <TEGRA_GPIO(S, 0) IRQ_TYPE_LEVEL_HIGH>;
744 interrupt-names = "host-wake";
745 };
746 };
747
748 mmc@c8000400 {
749 status = "okay";
750 bus-width = <4>;
751 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
752 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
753 vmmc-supply = <&vdd_3v3_sys>;
754 vqmmc-supply = <&vdd_3v3_sys>;
755 };
756
757 mmc@c8000600 {
758 status = "okay";
759 bus-width = <8>;
760 vmmc-supply = <&vcore_emmc>;
761 vqmmc-supply = <&vdd_3v3_sys>;
762 non-removable;
763 };
764
765 mains: ac-adapter-detect {
766 compatible = "gpio-charger";
767 charger-type = "mains";
768 gpios = <&gpio TEGRA_GPIO(V, 3) GPIO_ACTIVE_LOW>;
769 };
770
771 backlight: backlight {
772 compatible = "pwm-backlight";
773
774 enable-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_HIGH>;
775 power-supply = <&vdd_3v3_sys>;
776 pwms = <&pwm 2 41667>;
777
778 brightness-levels = <7 255>;
779 num-interpolated-steps = <248>;
780 default-brightness-level = <20>;
781 };
782
783 /* PMIC has a built-in 32KHz oscillator which is used by PMC */
784 clk32k_in: clock@0 {
785 compatible = "fixed-clock";
786 #clock-cells = <0>;
787 clock-frequency = <32768>;
788 clock-output-names = "tps658621-out32k";
789 };
790
791 /*
792 * This standalone onboard fixed-clock always-ON 32KHz
793 * oscillator is used as a reference clock-source by the
794 * Azurewave WiFi/BT module.
795 */
796 rtc_32k_wifi: clock@1 {
797 compatible = "fixed-clock";
798 #clock-cells = <0>;
799 clock-frequency = <32768>;
800 clock-output-names = "kk3270032";
801 };
802
803 cpus {
804 cpu0: cpu@0 {
805 cpu-supply = <&vdd_cpu>;
806 operating-points-v2 = <&cpu0_opp_table>;
807 #cooling-cells = <2>;
808 };
809
810 cpu@1 {
811 cpu-supply = <&vdd_cpu>;
812 operating-points-v2 = <&cpu0_opp_table>;
813 };
814 };
815
816 display-panel {
817 compatible = "auo,b101ew05", "panel-lvds";
818
819 ddc-i2c-bus = <&panel_ddc>;
820 power-supply = <&vdd_pnl>;
821 backlight = <&backlight>;
822
823 width-mm = <218>;
824 height-mm = <135>;
825
826 data-mapping = "jeida-18";
827
828 panel-timing {
829 clock-frequency = <71200000>;
830 hactive = <1280>;
831 vactive = <800>;
832 hfront-porch = <8>;
833 hback-porch = <18>;
834 hsync-len = <184>;
835 vsync-len = <3>;
836 vfront-porch = <4>;
837 vback-porch = <8>;
838 };
839
840 port {
841 panel_input: endpoint {
842 remote-endpoint = <&lvds_encoder_output>;
843 };
844 };
845 };
846
847 gpio-keys {
848 compatible = "gpio-keys";
849
850 power {
851 label = "Power";
852 gpios = <&gpio TEGRA_GPIO(I, 3) GPIO_ACTIVE_HIGH>;
853 linux,code = <KEY_POWER>;
854 debounce-interval = <10>;
855 wakeup-event-action = <EV_ACT_ASSERTED>;
856 wakeup-source;
857 };
858
859 rotation-lock {
860 label = "Rotate-lock";
861 gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_HIGH>;
862 linux,code = <SW_ROTATE_LOCK>;
863 linux,input-type = <EV_SW>;
864 debounce-interval = <10>;
865 };
866
867 volume-up {
868 label = "Volume Up";
869 gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>;
870 linux,code = <KEY_VOLUMEUP>;
871 debounce-interval = <10>;
872 wakeup-event-action = <EV_ACT_ASSERTED>;
873 wakeup-source;
874 };
875
876 volume-down {
877 label = "Volume Down";
878 gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
879 linux,code = <KEY_VOLUMEDOWN>;
880 debounce-interval = <10>;
881 wakeup-event-action = <EV_ACT_ASSERTED>;
882 wakeup-source;
883 };
884 };
885
886 haptic-feedback {
887 compatible = "gpio-vibrator";
888 enable-gpios = <&gpio TEGRA_GPIO(V, 5) GPIO_ACTIVE_HIGH>;
889 vcc-supply = <&vdd_3v3_sys>;
890 };
891
892 lvds-encoder {
893 compatible = "ti,sn75lvds83", "lvds-encoder";
894
895 powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>;
896
897 ports {
898 #address-cells = <1>;
899 #size-cells = <0>;
900
901 port@0 {
902 reg = <0>;
903
904 lvds_encoder_input: endpoint {
905 remote-endpoint = <&lcd_output>;
906 };
907 };
908
909 port@1 {
910 reg = <1>;
911
912 lvds_encoder_output: endpoint {
913 remote-endpoint = <&panel_input>;
914 };
915 };
916 };
917 };
918
919 vdd_5v0_sys: regulator@0 {
920 compatible = "regulator-fixed";
921 regulator-name = "vdd_5v0";
922 regulator-min-microvolt = <5000000>;
923 regulator-max-microvolt = <5000000>;
924 regulator-always-on;
925 };
926
927 vdd_3v3_sys: regulator@1 {
928 compatible = "regulator-fixed";
929 regulator-name = "vdd_3v3_vs";
930 regulator-min-microvolt = <3300000>;
931 regulator-max-microvolt = <3300000>;
932 regulator-always-on;
933 vin-supply = <&vdd_5v0_sys>;
934 };
935
936 vdd_1v8_sys: regulator@2 {
937 compatible = "regulator-fixed";
938 regulator-name = "vdd_1v8_vs";
939 regulator-min-microvolt = <1800000>;
940 regulator-max-microvolt = <1800000>;
941 regulator-always-on;
942 vin-supply = <&vdd_5v0_sys>;
943 };
944
945 vdd_pnl: regulator@3 {
946 compatible = "regulator-fixed";
947 regulator-name = "vdd_panel";
948 regulator-min-microvolt = <3300000>;
949 regulator-max-microvolt = <3300000>;
950 regulator-enable-ramp-delay = <300000>;
951 gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
952 enable-active-high;
953 vin-supply = <&vdd_5v0_sys>;
954 };
955
956 vdd_vbus1: regulator@4 {
957 compatible = "regulator-fixed";
958 regulator-name = "vdd_usb1_vbus";
959 regulator-min-microvolt = <5000000>;
960 regulator-max-microvolt = <5000000>;
961 regulator-always-on;
962 gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
963 enable-active-high;
964 vin-supply = <&vdd_5v0_sys>;
965 };
966
967 vdd_vbus3: regulator@5 {
968 compatible = "regulator-fixed";
969 regulator-name = "vdd_usb3_vbus";
970 regulator-min-microvolt = <5000000>;
971 regulator-max-microvolt = <5000000>;
972 regulator-always-on;
973 gpio = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_HIGH>;
974 enable-active-high;
975 vin-supply = <&vdd_5v0_sys>;
976 };
977
978 sound {
979 compatible = "nvidia,tegra-audio-wm8903-picasso",
980 "nvidia,tegra-audio-wm8903";
981 nvidia,model = "Acer Iconia Tab A500 WM8903";
982
983 nvidia,audio-routing =
984 "Headphone Jack", "HPOUTR",
985 "Headphone Jack", "HPOUTL",
986 "Int Spk", "LINEOUTL",
987 "Int Spk", "LINEOUTR",
988 "Mic Jack", "MICBIAS",
989 "IN2L", "Mic Jack",
990 "IN2R", "Mic Jack",
991 "IN1L", "Int Mic",
992 "IN1R", "Int Mic";
993
994 nvidia,i2s-controller = <&tegra_i2s1>;
995 nvidia,audio-codec = <&wm8903>;
996
997 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
998 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>;
999 nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>;
1000 nvidia,headset;
1001
1002 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
1003 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
1004 <&tegra_car TEGRA20_CLK_CDEV1>;
1005 clock-names = "pll_a", "pll_a_out0", "mclk";
1006 };
1007
1008 thermal-zones {
1009 nct1008-local {
1010 polling-delay-passive = <1000>; /* milliseconds */
1011 polling-delay = <0>; /* milliseconds */
1012
1013 thermal-sensors = <&nct1008 0>;
1014 };
1015
1016 nct1008-remote {
1017 polling-delay-passive = <1000>; /* milliseconds */
1018 polling-delay = <5000>; /* milliseconds */
1019
1020 thermal-sensors = <&nct1008 1>;
1021
1022 trips {
1023 trip0: cpu-alert0 {
1024 /* start throttling at 50C */
1025 temperature = <50000>;
1026 hysteresis = <3000>;
1027 type = "passive";
1028 };
1029
1030 trip1: cpu-crit {
1031 /* shut down at 60C */
1032 temperature = <60000>;
1033 hysteresis = <2000>;
1034 type = "critical";
1035 };
1036 };
1037
1038 cooling-maps {
1039 map0 {
1040 trip = <&trip0>;
1041 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1042 };
1043 };
1044 };
1045 };
1046
1047 memory-controller@7000f400 {
1048 nvidia,use-ram-code;
1049
1050 emc-tables@0 {
1051 nvidia,ram-code = <0>; /* elpida-8gb */
1052
1053 #address-cells = <1>;
1054 #size-cells = <0>;
1055
1056 emc-table@25000 {
1057 reg = <25000>;
1058 compatible = "nvidia,tegra20-emc-table";
1059 clock-frequency = <25000>;
1060 nvidia,emc-registers = <0x00000002 0x00000006
1061 0x00000003 0x00000003 0x00000006 0x00000004
1062 0x00000002 0x00000009 0x00000003 0x00000003
1063 0x00000002 0x00000002 0x00000002 0x00000004
1064 0x00000003 0x00000008 0x0000000b 0x0000004d
1065 0x00000000 0x00000003 0x00000003 0x00000003
1066 0x00000008 0x00000001 0x0000000a 0x00000004
1067 0x00000003 0x00000008 0x00000004 0x00000006
1068 0x00000002 0x00000068 0x00000000 0x00000003
1069 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1070 0x00070000 0x00000000 0x00000000 0x00000003
1071 0x00000000 0x00000000 0x00000000 0x00000000>;
1072 };
1073
1074 emc-table@50000 {
1075 reg = <50000>;
1076 compatible = "nvidia,tegra20-emc-table";
1077 clock-frequency = <50000>;
1078 nvidia,emc-registers = <0x00000003 0x00000007
1079 0x00000003 0x00000003 0x00000006 0x00000004
1080 0x00000002 0x00000009 0x00000003 0x00000003
1081 0x00000002 0x00000002 0x00000002 0x00000005
1082 0x00000003 0x00000008 0x0000000b 0x0000009f
1083 0x00000000 0x00000003 0x00000003 0x00000003
1084 0x00000008 0x00000001 0x0000000a 0x00000007
1085 0x00000003 0x00000008 0x00000004 0x00000006
1086 0x00000002 0x000000d0 0x00000000 0x00000000
1087 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1088 0x00070000 0x00000000 0x00000000 0x00000005
1089 0x00000000 0x00000000 0x00000000 0x00000000>;
1090 };
1091
1092 emc-table@75000 {
1093 reg = <75000>;
1094 compatible = "nvidia,tegra20-emc-table";
1095 clock-frequency = <75000>;
1096 nvidia,emc-registers = <0x00000005 0x0000000a
1097 0x00000004 0x00000003 0x00000006 0x00000004
1098 0x00000002 0x00000009 0x00000003 0x00000003
1099 0x00000002 0x00000002 0x00000002 0x00000005
1100 0x00000003 0x00000008 0x0000000b 0x000000ff
1101 0x00000000 0x00000003 0x00000003 0x00000003
1102 0x00000008 0x00000001 0x0000000a 0x0000000b
1103 0x00000003 0x00000008 0x00000004 0x00000006
1104 0x00000002 0x00000138 0x00000000 0x00000000
1105 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1106 0x00070000 0x00000000 0x00000000 0x00000007
1107 0x00000000 0x00000000 0x00000000 0x00000000>;
1108 };
1109
1110 emc-table@150000 {
1111 reg = <150000>;
1112 compatible = "nvidia,tegra20-emc-table";
1113 clock-frequency = <150000>;
1114 nvidia,emc-registers = <0x00000009 0x00000014
1115 0x00000007 0x00000003 0x00000006 0x00000004
1116 0x00000002 0x00000009 0x00000003 0x00000003
1117 0x00000002 0x00000002 0x00000002 0x00000005
1118 0x00000003 0x00000008 0x0000000b 0x0000021f
1119 0x00000000 0x00000003 0x00000003 0x00000003
1120 0x00000008 0x00000001 0x0000000a 0x00000015
1121 0x00000003 0x00000008 0x00000004 0x00000006
1122 0x00000002 0x00000270 0x00000000 0x00000001
1123 0x00000000 0x00000000 0x00000282 0xa07c04ae
1124 0x007dd510 0x00000000 0x00000000 0x0000000e
1125 0x00000000 0x00000000 0x00000000 0x00000000>;
1126 };
1127
1128 emc-table@300000 {
1129 reg = <300000>;
1130 compatible = "nvidia,tegra20-emc-table";
1131 clock-frequency = <300000>;
1132 nvidia,emc-registers = <0x00000012 0x00000027
1133 0x0000000d 0x00000006 0x00000007 0x00000005
1134 0x00000003 0x00000009 0x00000006 0x00000006
1135 0x00000003 0x00000003 0x00000002 0x00000006
1136 0x00000003 0x00000009 0x0000000c 0x0000045f
1137 0x00000000 0x00000004 0x00000004 0x00000006
1138 0x00000008 0x00000001 0x0000000e 0x0000002a
1139 0x00000003 0x0000000f 0x00000007 0x00000005
1140 0x00000002 0x000004e1 0x00000005 0x00000002
1141 0x00000000 0x00000000 0x00000282 0xe059048b
1142 0x007e1510 0x00000000 0x00000000 0x0000001b
1143 0x00000000 0x00000000 0x00000000 0x00000000>;
1144 };
1145 };
1146
1147 emc-tables@1 {
1148 nvidia,ram-code = <1>; /* elpida-4gb */
1149
1150 #address-cells = <1>;
1151 #size-cells = <0>;
1152
1153 emc-table@25000 {
1154 reg = <25000>;
1155 compatible = "nvidia,tegra20-emc-table";
1156 clock-frequency = <25000>;
1157 nvidia,emc-registers = <0x00000002 0x00000006
1158 0x00000003 0x00000003 0x00000006 0x00000004
1159 0x00000002 0x00000009 0x00000003 0x00000003
1160 0x00000002 0x00000002 0x00000002 0x00000004
1161 0x00000003 0x00000008 0x0000000b 0x0000004d
1162 0x00000000 0x00000003 0x00000003 0x00000003
1163 0x00000008 0x00000001 0x0000000a 0x00000004
1164 0x00000003 0x00000008 0x00000004 0x00000006
1165 0x00000002 0x00000068 0x00000000 0x00000003
1166 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1167 0x0007c000 0x00000000 0x00000000 0x00000003
1168 0x00000000 0x00000000 0x00000000 0x00000000>;
1169 };
1170
1171 emc-table@50000 {
1172 reg = <50000>;
1173 compatible = "nvidia,tegra20-emc-table";
1174 clock-frequency = <50000>;
1175 nvidia,emc-registers = <0x00000003 0x00000007
1176 0x00000003 0x00000003 0x00000006 0x00000004
1177 0x00000002 0x00000009 0x00000003 0x00000003
1178 0x00000002 0x00000002 0x00000002 0x00000005
1179 0x00000003 0x00000008 0x0000000b 0x0000009f
1180 0x00000000 0x00000003 0x00000003 0x00000003
1181 0x00000008 0x00000001 0x0000000a 0x00000007
1182 0x00000003 0x00000008 0x00000004 0x00000006
1183 0x00000002 0x000000d0 0x00000000 0x00000000
1184 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1185 0x0007c000 0x00000000 0x00000000 0x00000005
1186 0x00000000 0x00000000 0x00000000 0x00000000>;
1187 };
1188
1189 emc-table@75000 {
1190 reg = <75000>;
1191 compatible = "nvidia,tegra20-emc-table";
1192 clock-frequency = <75000>;
1193 nvidia,emc-registers = <0x00000005 0x0000000a
1194 0x00000004 0x00000003 0x00000006 0x00000004
1195 0x00000002 0x00000009 0x00000003 0x00000003
1196 0x00000002 0x00000002 0x00000002 0x00000005
1197 0x00000003 0x00000008 0x0000000b 0x000000ff
1198 0x00000000 0x00000003 0x00000003 0x00000003
1199 0x00000008 0x00000001 0x0000000a 0x0000000b
1200 0x00000003 0x00000008 0x00000004 0x00000006
1201 0x00000002 0x00000138 0x00000000 0x00000000
1202 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1203 0x0007c000 0x00000000 0x00000000 0x00000007
1204 0x00000000 0x00000000 0x00000000 0x00000000>;
1205 };
1206
1207 emc-table@150000 {
1208 reg = <150000>;
1209 compatible = "nvidia,tegra20-emc-table";
1210 clock-frequency = <150000>;
1211 nvidia,emc-registers = <0x00000009 0x00000014
1212 0x00000007 0x00000003 0x00000006 0x00000004
1213 0x00000002 0x00000009 0x00000003 0x00000003
1214 0x00000002 0x00000002 0x00000002 0x00000005
1215 0x00000003 0x00000008 0x0000000b 0x0000021f
1216 0x00000000 0x00000003 0x00000003 0x00000003
1217 0x00000008 0x00000001 0x0000000a 0x00000015
1218 0x00000003 0x00000008 0x00000004 0x00000006
1219 0x00000002 0x00000270 0x00000000 0x00000001
1220 0x00000000 0x00000000 0x00000282 0xa07c04ae
1221 0x007e4010 0x00000000 0x00000000 0x0000000e
1222 0x00000000 0x00000000 0x00000000 0x00000000>;
1223 };
1224
1225 emc-table@300000 {
1226 reg = <300000>;
1227 compatible = "nvidia,tegra20-emc-table";
1228 clock-frequency = <300000>;
1229 nvidia,emc-registers = <0x00000012 0x00000027
1230 0x0000000d 0x00000006 0x00000007 0x00000005
1231 0x00000003 0x00000009 0x00000006 0x00000006
1232 0x00000003 0x00000003 0x00000002 0x00000006
1233 0x00000003 0x00000009 0x0000000c 0x0000045f
1234 0x00000000 0x00000004 0x00000004 0x00000006
1235 0x00000008 0x00000001 0x0000000e 0x0000002a
1236 0x00000003 0x0000000f 0x00000007 0x00000005
1237 0x00000002 0x000004e1 0x00000005 0x00000002
1238 0x00000000 0x00000000 0x00000282 0xe059048b
1239 0x007e0010 0x00000000 0x00000000 0x0000001b
1240 0x00000000 0x00000000 0x00000000 0x00000000>;
1241 };
1242 };
1243
1244 emc-tables@2 {
1245 nvidia,ram-code = <2>; /* hynix-8gb */
1246
1247 #address-cells = <1>;
1248 #size-cells = <0>;
1249
1250 emc-table@25000 {
1251 reg = <25000>;
1252 compatible = "nvidia,tegra20-emc-table";
1253 clock-frequency = <25000>;
1254 nvidia,emc-registers = <0x00000002 0x00000006
1255 0x00000003 0x00000003 0x00000006 0x00000004
1256 0x00000002 0x00000009 0x00000003 0x00000003
1257 0x00000002 0x00000002 0x00000002 0x00000004
1258 0x00000003 0x00000008 0x0000000b 0x0000004d
1259 0x00000000 0x00000003 0x00000003 0x00000003
1260 0x00000008 0x00000001 0x0000000a 0x00000004
1261 0x00000003 0x00000008 0x00000004 0x00000006
1262 0x00000002 0x00000068 0x00000000 0x00000003
1263 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1264 0x00070000 0x00000000 0x00000000 0x00000003
1265 0x00000000 0x00000000 0x00000000 0x00000000>;
1266 };
1267
1268 emc-table@50000 {
1269 reg = <50000>;
1270 compatible = "nvidia,tegra20-emc-table";
1271 clock-frequency = <50000>;
1272 nvidia,emc-registers = <0x00000003 0x00000007
1273 0x00000003 0x00000003 0x00000006 0x00000004
1274 0x00000002 0x00000009 0x00000003 0x00000003
1275 0x00000002 0x00000002 0x00000002 0x00000005
1276 0x00000003 0x00000008 0x0000000b 0x0000009f
1277 0x00000000 0x00000003 0x00000003 0x00000003
1278 0x00000008 0x00000001 0x0000000a 0x00000007
1279 0x00000003 0x00000008 0x00000004 0x00000006
1280 0x00000002 0x000000d0 0x00000000 0x00000000
1281 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1282 0x00070000 0x00000000 0x00000000 0x00000005
1283 0x00000000 0x00000000 0x00000000 0x00000000>;
1284 };
1285
1286 emc-table@75000 {
1287 reg = <75000>;
1288 compatible = "nvidia,tegra20-emc-table";
1289 clock-frequency = <75000>;
1290 nvidia,emc-registers = <0x00000005 0x0000000a
1291 0x00000004 0x00000003 0x00000006 0x00000004
1292 0x00000002 0x00000009 0x00000003 0x00000003
1293 0x00000002 0x00000002 0x00000002 0x00000005
1294 0x00000003 0x00000008 0x0000000b 0x000000ff
1295 0x00000000 0x00000003 0x00000003 0x00000003
1296 0x00000008 0x00000001 0x0000000a 0x0000000b
1297 0x00000003 0x00000008 0x00000004 0x00000006
1298 0x00000002 0x00000138 0x00000000 0x00000000
1299 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1300 0x00070000 0x00000000 0x00000000 0x00000007
1301 0x00000000 0x00000000 0x00000000 0x00000000>;
1302 };
1303
1304 emc-table@150000 {
1305 reg = <150000>;
1306 compatible = "nvidia,tegra20-emc-table";
1307 clock-frequency = <150000>;
1308 nvidia,emc-registers = <0x00000009 0x00000014
1309 0x00000007 0x00000003 0x00000006 0x00000004
1310 0x00000002 0x00000009 0x00000003 0x00000003
1311 0x00000002 0x00000002 0x00000002 0x00000005
1312 0x00000003 0x00000008 0x0000000b 0x0000021f
1313 0x00000000 0x00000003 0x00000003 0x00000003
1314 0x00000008 0x00000001 0x0000000a 0x00000015
1315 0x00000003 0x00000008 0x00000004 0x00000006
1316 0x00000002 0x00000270 0x00000000 0x00000001
1317 0x00000000 0x00000000 0x00000282 0xa07c04ae
1318 0x007dd010 0x00000000 0x00000000 0x0000000e
1319 0x00000000 0x00000000 0x00000000 0x00000000>;
1320 };
1321
1322 emc-table@300000 {
1323 reg = <300000>;
1324 compatible = "nvidia,tegra20-emc-table";
1325 clock-frequency = <300000>;
1326 nvidia,emc-registers = <0x00000012 0x00000027
1327 0x0000000d 0x00000006 0x00000007 0x00000005
1328 0x00000003 0x00000009 0x00000006 0x00000006
1329 0x00000003 0x00000003 0x00000002 0x00000006
1330 0x00000003 0x00000009 0x0000000c 0x0000045f
1331 0x00000000 0x00000004 0x00000004 0x00000006
1332 0x00000008 0x00000001 0x0000000e 0x0000002a
1333 0x00000003 0x0000000f 0x00000007 0x00000005
1334 0x00000002 0x000004e1 0x00000005 0x00000002
1335 0x00000000 0x00000000 0x00000282 0xe059048b
1336 0x007e2010 0x00000000 0x00000000 0x0000001b
1337 0x00000000 0x00000000 0x00000000 0x00000000>;
1338 };
1339 };
1340
1341 emc-tables@3 {
1342 nvidia,ram-code = <3>; /* hynix-4gb */
1343
1344 #address-cells = <1>;
1345 #size-cells = <0>;
1346
1347 emc-table@25000 {
1348 reg = <25000>;
1349 compatible = "nvidia,tegra20-emc-table";
1350 clock-frequency = <25000>;
1351 nvidia,emc-registers = <0x00000002 0x00000006
1352 0x00000003 0x00000003 0x00000006 0x00000004
1353 0x00000002 0x00000009 0x00000003 0x00000003
1354 0x00000002 0x00000002 0x00000002 0x00000004
1355 0x00000003 0x00000008 0x0000000b 0x0000004d
1356 0x00000000 0x00000003 0x00000003 0x00000003
1357 0x00000008 0x00000001 0x0000000a 0x00000004
1358 0x00000003 0x00000008 0x00000004 0x00000006
1359 0x00000002 0x00000068 0x00000000 0x00000003
1360 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1361 0x0007c000 0x00000000 0x00000000 0x00000003
1362 0x00000000 0x00000000 0x00000000 0x00000000>;
1363 };
1364
1365 emc-table@50000 {
1366 reg = <50000>;
1367 compatible = "nvidia,tegra20-emc-table";
1368 clock-frequency = <50000>;
1369 nvidia,emc-registers = <0x00000003 0x00000007
1370 0x00000003 0x00000003 0x00000006 0x00000004
1371 0x00000002 0x00000009 0x00000003 0x00000003
1372 0x00000002 0x00000002 0x00000002 0x00000005
1373 0x00000003 0x00000008 0x0000000b 0x0000009f
1374 0x00000000 0x00000003 0x00000003 0x00000003
1375 0x00000008 0x00000001 0x0000000a 0x00000007
1376 0x00000003 0x00000008 0x00000004 0x00000006
1377 0x00000002 0x000000d0 0x00000000 0x00000000
1378 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1379 0x0007c000 0x00078000 0x00000000 0x00000005
1380 0x00000000 0x00000000 0x00000000 0x00000000>;
1381 };
1382
1383 emc-table@75000 {
1384 reg = <75000>;
1385 compatible = "nvidia,tegra20-emc-table";
1386 clock-frequency = <75000>;
1387 nvidia,emc-registers = <0x00000005 0x0000000a
1388 0x00000004 0x00000003 0x00000006 0x00000004
1389 0x00000002 0x00000009 0x00000003 0x00000003
1390 0x00000002 0x00000002 0x00000002 0x00000005
1391 0x00000003 0x00000008 0x0000000b 0x000000ff
1392 0x00000000 0x00000003 0x00000003 0x00000003
1393 0x00000008 0x00000001 0x0000000a 0x0000000b
1394 0x00000003 0x00000008 0x00000004 0x00000006
1395 0x00000002 0x00000138 0x00000000 0x00000000
1396 0x00000000 0x00000000 0x00000282 0xa0ae04ae
1397 0x0007c000 0x00000000 0x00000000 0x00000007
1398 0x00000000 0x00000000 0x00000000 0x00000000>;
1399 };
1400
1401 emc-table@150000 {
1402 reg = <150000>;
1403 compatible = "nvidia,tegra20-emc-table";
1404 clock-frequency = <150000>;
1405 nvidia,emc-registers = <0x00000009 0x00000014
1406 0x00000007 0x00000003 0x00000006 0x00000004
1407 0x00000002 0x00000009 0x00000003 0x00000003
1408 0x00000002 0x00000002 0x00000002 0x00000005
1409 0x00000003 0x00000008 0x0000000b 0x0000021f
1410 0x00000000 0x00000003 0x00000003 0x00000003
1411 0x00000008 0x00000001 0x0000000a 0x00000015
1412 0x00000003 0x00000008 0x00000004 0x00000006
1413 0x00000002 0x00000270 0x00000000 0x00000001
1414 0x00000000 0x00000000 0x00000282 0xa07c04ae
1415 0x007e4010 0x00000000 0x00000000 0x0000000e
1416 0x00000000 0x00000000 0x00000000 0x00000000>;
1417 };
1418
1419 emc-table@300000 {
1420 reg = <300000>;
1421 compatible = "nvidia,tegra20-emc-table";
1422 clock-frequency = <300000>;
1423 nvidia,emc-registers = <0x00000012 0x00000027
1424 0x0000000d 0x00000006 0x00000007 0x00000005
1425 0x00000003 0x00000009 0x00000006 0x00000006
1426 0x00000003 0x00000003 0x00000002 0x00000006
1427 0x00000003 0x00000009 0x0000000c 0x0000045f
1428 0x00000000 0x00000004 0x00000004 0x00000006
1429 0x00000008 0x00000001 0x0000000e 0x0000002a
1430 0x00000003 0x0000000f 0x00000007 0x00000005
1431 0x00000002 0x000004e1 0x00000005 0x00000002
1432 0x00000000 0x00000000 0x00000282 0xe059048b
1433 0x007e0010 0x00000000 0x00000000 0x0000001b
1434 0x00000000 0x00000000 0x00000000 0x00000000>;
1435 };
1436 };
1437 };
1438};