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1/*
2 * Device Tree Source for OMAP2420 SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include "omap2.dtsi"
12
13/ {
14 compatible = "ti,omap2420", "ti,omap2";
15
16 ocp {
17 l4: l4@48000000 {
18 compatible = "ti,omap2-l4", "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 ranges = <0 0x48000000 0x100000>;
22
23 prcm: prcm@8000 {
24 compatible = "ti,omap2-prcm";
25 reg = <0x8000 0x1000>;
26
27 prcm_clocks: clocks {
28 #address-cells = <1>;
29 #size-cells = <0>;
30 };
31
32 prcm_clockdomains: clockdomains {
33 };
34 };
35
36 scm: scm@0 {
37 compatible = "ti,omap2-scm", "simple-bus";
38 reg = <0x0 0x1000>;
39 #address-cells = <1>;
40 #size-cells = <1>;
41 #pinctrl-cells = <1>;
42 ranges = <0 0x0 0x1000>;
43
44 omap2420_pmx: pinmux@30 {
45 compatible = "ti,omap2420-padconf",
46 "pinctrl-single";
47 reg = <0x30 0x0113>;
48 #address-cells = <1>;
49 #size-cells = <0>;
50 #pinctrl-cells = <1>;
51 pinctrl-single,register-width = <8>;
52 pinctrl-single,function-mask = <0x3f>;
53 };
54
55 scm_conf: scm_conf@270 {
56 compatible = "syscon";
57 reg = <0x270 0x100>;
58 #address-cells = <1>;
59 #size-cells = <1>;
60
61 scm_clocks: clocks {
62 #address-cells = <1>;
63 #size-cells = <0>;
64 };
65 };
66
67 scm_clockdomains: clockdomains {
68 };
69 };
70
71 counter32k: counter@4000 {
72 compatible = "ti,omap-counter32k";
73 reg = <0x4000 0x20>;
74 ti,hwmods = "counter_32k";
75 };
76 };
77
78 gpio1: gpio@48018000 {
79 compatible = "ti,omap2-gpio";
80 reg = <0x48018000 0x200>;
81 interrupts = <29>;
82 ti,hwmods = "gpio1";
83 ti,gpio-always-on;
84 #gpio-cells = <2>;
85 gpio-controller;
86 #interrupt-cells = <2>;
87 interrupt-controller;
88 };
89
90 gpio2: gpio@4801a000 {
91 compatible = "ti,omap2-gpio";
92 reg = <0x4801a000 0x200>;
93 interrupts = <30>;
94 ti,hwmods = "gpio2";
95 ti,gpio-always-on;
96 #gpio-cells = <2>;
97 gpio-controller;
98 #interrupt-cells = <2>;
99 interrupt-controller;
100 };
101
102 gpio3: gpio@4801c000 {
103 compatible = "ti,omap2-gpio";
104 reg = <0x4801c000 0x200>;
105 interrupts = <31>;
106 ti,hwmods = "gpio3";
107 ti,gpio-always-on;
108 #gpio-cells = <2>;
109 gpio-controller;
110 #interrupt-cells = <2>;
111 interrupt-controller;
112 };
113
114 gpio4: gpio@4801e000 {
115 compatible = "ti,omap2-gpio";
116 reg = <0x4801e000 0x200>;
117 interrupts = <32>;
118 ti,hwmods = "gpio4";
119 ti,gpio-always-on;
120 #gpio-cells = <2>;
121 gpio-controller;
122 #interrupt-cells = <2>;
123 interrupt-controller;
124 };
125
126 gpmc: gpmc@6800a000 {
127 compatible = "ti,omap2420-gpmc";
128 reg = <0x6800a000 0x1000>;
129 #address-cells = <2>;
130 #size-cells = <1>;
131 interrupts = <20>;
132 gpmc,num-cs = <8>;
133 gpmc,num-waitpins = <4>;
134 ti,hwmods = "gpmc";
135 interrupt-controller;
136 #interrupt-cells = <2>;
137 gpio-controller;
138 #gpio-cells = <2>;
139 };
140
141 mcbsp1: mcbsp@48074000 {
142 compatible = "ti,omap2420-mcbsp";
143 reg = <0x48074000 0xff>;
144 reg-names = "mpu";
145 interrupts = <59>, /* TX interrupt */
146 <60>; /* RX interrupt */
147 interrupt-names = "tx", "rx";
148 ti,hwmods = "mcbsp1";
149 dmas = <&sdma 31>,
150 <&sdma 32>;
151 dma-names = "tx", "rx";
152 status = "disabled";
153 };
154
155 mcbsp2: mcbsp@48076000 {
156 compatible = "ti,omap2420-mcbsp";
157 reg = <0x48076000 0xff>;
158 reg-names = "mpu";
159 interrupts = <62>, /* TX interrupt */
160 <63>; /* RX interrupt */
161 interrupt-names = "tx", "rx";
162 ti,hwmods = "mcbsp2";
163 dmas = <&sdma 33>,
164 <&sdma 34>;
165 dma-names = "tx", "rx";
166 status = "disabled";
167 };
168
169 msdi1: mmc@4809c000 {
170 compatible = "ti,omap2420-mmc";
171 ti,hwmods = "msdi1";
172 reg = <0x4809c000 0x80>;
173 interrupts = <83>;
174 dmas = <&sdma 61 &sdma 62>;
175 dma-names = "tx", "rx";
176 };
177
178 mailbox: mailbox@48094000 {
179 compatible = "ti,omap2-mailbox";
180 reg = <0x48094000 0x200>;
181 interrupts = <26>, <34>;
182 interrupt-names = "dsp", "iva";
183 ti,hwmods = "mailbox";
184 #mbox-cells = <1>;
185 ti,mbox-num-users = <4>;
186 ti,mbox-num-fifos = <6>;
187 mbox_dsp: dsp {
188 ti,mbox-tx = <0 0 0>;
189 ti,mbox-rx = <1 0 0>;
190 };
191 mbox_iva: iva {
192 ti,mbox-tx = <2 1 3>;
193 ti,mbox-rx = <3 1 3>;
194 };
195 };
196
197 timer1: timer@48028000 {
198 compatible = "ti,omap2420-timer";
199 reg = <0x48028000 0x400>;
200 interrupts = <37>;
201 ti,hwmods = "timer1";
202 ti,timer-alwon;
203 };
204
205 wd_timer2: wdt@48022000 {
206 compatible = "ti,omap2-wdt";
207 ti,hwmods = "wd_timer2";
208 reg = <0x48022000 0x80>;
209 };
210 };
211};
212
213&i2c1 {
214 compatible = "ti,omap2420-i2c";
215};
216
217&i2c2 {
218 compatible = "ti,omap2420-i2c";
219};
220
221/include/ "omap24xx-clocks.dtsi"
222/include/ "omap2420-clocks.dtsi"
1/*
2 * Device Tree Source for OMAP2420 SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include "omap2.dtsi"
12
13/ {
14 compatible = "ti,omap2420", "ti,omap2";
15
16 ocp {
17 l4: l4@48000000 {
18 compatible = "ti,omap2-l4", "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
21 ranges = <0 0x48000000 0x100000>;
22
23 prcm: prcm@8000 {
24 compatible = "ti,omap2-prcm";
25 reg = <0x8000 0x1000>;
26
27 prcm_clocks: clocks {
28 #address-cells = <1>;
29 #size-cells = <0>;
30 };
31
32 prcm_clockdomains: clockdomains {
33 };
34 };
35
36 scm: scm@0 {
37 compatible = "ti,omap2-scm", "simple-bus";
38 reg = <0x0 0x1000>;
39 #address-cells = <1>;
40 #size-cells = <1>;
41 #pinctrl-cells = <1>;
42 ranges = <0 0x0 0x1000>;
43
44 omap2420_pmx: pinmux@30 {
45 compatible = "ti,omap2420-padconf",
46 "pinctrl-single";
47 reg = <0x30 0x0113>;
48 #address-cells = <1>;
49 #size-cells = <0>;
50 #pinctrl-cells = <1>;
51 pinctrl-single,register-width = <8>;
52 pinctrl-single,function-mask = <0x3f>;
53 };
54
55 scm_conf: scm_conf@270 {
56 compatible = "syscon";
57 reg = <0x270 0x100>;
58 #address-cells = <1>;
59 #size-cells = <1>;
60
61 scm_clocks: clocks {
62 #address-cells = <1>;
63 #size-cells = <0>;
64 };
65 };
66
67 scm_clockdomains: clockdomains {
68 };
69 };
70
71 target-module@4000 {
72 compatible = "ti,sysc-omap2", "ti,sysc";
73 reg = <0x4000 0x4>,
74 <0x4004 0x4>;
75 reg-names = "rev", "sysc";
76 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
77 <SYSC_IDLE_NO>;
78 clocks = <&func_32k_ck>;
79 clock-names = "fck";
80 #address-cells = <1>;
81 #size-cells = <1>;
82 ranges = <0x0 0x4000 0x1000>;
83
84 counter32k: counter@0 {
85 compatible = "ti,omap-counter32k";
86 reg = <0 0x20>;
87 };
88 };
89 };
90
91 gpio1: gpio@48018000 {
92 compatible = "ti,omap2-gpio";
93 reg = <0x48018000 0x200>;
94 interrupts = <29>;
95 ti,hwmods = "gpio1";
96 ti,gpio-always-on;
97 #gpio-cells = <2>;
98 gpio-controller;
99 #interrupt-cells = <2>;
100 interrupt-controller;
101 };
102
103 gpio2: gpio@4801a000 {
104 compatible = "ti,omap2-gpio";
105 reg = <0x4801a000 0x200>;
106 interrupts = <30>;
107 ti,hwmods = "gpio2";
108 ti,gpio-always-on;
109 #gpio-cells = <2>;
110 gpio-controller;
111 #interrupt-cells = <2>;
112 interrupt-controller;
113 };
114
115 gpio3: gpio@4801c000 {
116 compatible = "ti,omap2-gpio";
117 reg = <0x4801c000 0x200>;
118 interrupts = <31>;
119 ti,hwmods = "gpio3";
120 ti,gpio-always-on;
121 #gpio-cells = <2>;
122 gpio-controller;
123 #interrupt-cells = <2>;
124 interrupt-controller;
125 };
126
127 gpio4: gpio@4801e000 {
128 compatible = "ti,omap2-gpio";
129 reg = <0x4801e000 0x200>;
130 interrupts = <32>;
131 ti,hwmods = "gpio4";
132 ti,gpio-always-on;
133 #gpio-cells = <2>;
134 gpio-controller;
135 #interrupt-cells = <2>;
136 interrupt-controller;
137 };
138
139 gpmc: gpmc@6800a000 {
140 compatible = "ti,omap2420-gpmc";
141 reg = <0x6800a000 0x1000>;
142 #address-cells = <2>;
143 #size-cells = <1>;
144 interrupts = <20>;
145 gpmc,num-cs = <8>;
146 gpmc,num-waitpins = <4>;
147 ti,hwmods = "gpmc";
148 interrupt-controller;
149 #interrupt-cells = <2>;
150 gpio-controller;
151 #gpio-cells = <2>;
152 };
153
154 mcbsp1: mcbsp@48074000 {
155 compatible = "ti,omap2420-mcbsp";
156 reg = <0x48074000 0xff>;
157 reg-names = "mpu";
158 interrupts = <59>, /* TX interrupt */
159 <60>; /* RX interrupt */
160 interrupt-names = "tx", "rx";
161 ti,hwmods = "mcbsp1";
162 dmas = <&sdma 31>,
163 <&sdma 32>;
164 dma-names = "tx", "rx";
165 status = "disabled";
166 };
167
168 mcbsp2: mcbsp@48076000 {
169 compatible = "ti,omap2420-mcbsp";
170 reg = <0x48076000 0xff>;
171 reg-names = "mpu";
172 interrupts = <62>, /* TX interrupt */
173 <63>; /* RX interrupt */
174 interrupt-names = "tx", "rx";
175 ti,hwmods = "mcbsp2";
176 dmas = <&sdma 33>,
177 <&sdma 34>;
178 dma-names = "tx", "rx";
179 status = "disabled";
180 };
181
182 msdi1: mmc@4809c000 {
183 compatible = "ti,omap2420-mmc";
184 ti,hwmods = "msdi1";
185 reg = <0x4809c000 0x80>;
186 interrupts = <83>;
187 dmas = <&sdma 61 &sdma 62>;
188 dma-names = "tx", "rx";
189 };
190
191 mailbox: mailbox@48094000 {
192 compatible = "ti,omap2-mailbox";
193 reg = <0x48094000 0x200>;
194 interrupts = <26>, <34>;
195 ti,hwmods = "mailbox";
196 #mbox-cells = <1>;
197 ti,mbox-num-users = <4>;
198 ti,mbox-num-fifos = <6>;
199 mbox_dsp: mbox-dsp {
200 ti,mbox-tx = <0 0 0>;
201 ti,mbox-rx = <1 0 0>;
202 };
203 mbox_iva: mbox-iva {
204 ti,mbox-tx = <2 1 3>;
205 ti,mbox-rx = <3 1 3>;
206 };
207 };
208
209 timer1_target: target-module@48028000 {
210 compatible = "ti,sysc-omap2-timer", "ti,sysc";
211 reg = <0x48028000 0x4>,
212 <0x48028010 0x4>,
213 <0x48028014 0x4>;
214 reg-names = "rev", "sysc", "syss";
215 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
216 SYSC_OMAP2_EMUFREE |
217 SYSC_OMAP2_ENAWAKEUP |
218 SYSC_OMAP2_SOFTRESET |
219 SYSC_OMAP2_AUTOIDLE)>;
220 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
221 <SYSC_IDLE_NO>,
222 <SYSC_IDLE_SMART>;
223 ti,syss-mask = <1>;
224 clocks = <&gpt1_fck>, <&gpt1_ick>;
225 clock-names = "fck", "ick";
226 #address-cells = <1>;
227 #size-cells = <1>;
228 ranges = <0x0 0x48028000 0x1000>;
229
230 timer1: timer@0 {
231 compatible = "ti,omap2420-timer";
232 reg = <0 0x400>;
233 interrupts = <37>;
234 ti,timer-alwon;
235 };
236 };
237
238 wd_timer2: wdt@48022000 {
239 compatible = "ti,omap2-wdt";
240 ti,hwmods = "wd_timer2";
241 reg = <0x48022000 0x80>;
242 };
243 };
244};
245
246&i2c1 {
247 compatible = "ti,omap2420-i2c";
248};
249
250&i2c2 {
251 compatible = "ti,omap2420-i2c";
252};
253
254#include "omap24xx-clocks.dtsi"
255#include "omap2420-clocks.dtsi"
256
257/* Preferred always-on timer for clockevent */
258&timer1_target {
259 ti,no-reset-on-init;
260 ti,no-idle;
261 timer@0 {
262 assigned-clocks = <&gpt1_fck>;
263 assigned-clock-parents = <&func_32k_ck>;
264 };
265};