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1/*
2 * Copyright (c) 2015 Neil Armstrong <narmstrong@baylibre.com>
3 * Copyright (c) 2014 Joachim Eastwood <manabian@gmail.com>
4 * Copyright (c) 2012 NeilBrown <neilb@suse.de>
5 * Heavily based on earlier code which is:
6 * Copyright (c) 2010 Grant Erickson <marathon96@gmail.com>
7 *
8 * Also based on pwm-samsung.c
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * Description:
15 * This file is the core OMAP support for the generic, Linux
16 * PWM driver / controller, using the OMAP's dual-mode timers.
17 */
18
19#include <linux/clk.h>
20#include <linux/err.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/mutex.h>
24#include <linux/of.h>
25#include <linux/of_platform.h>
26#include <linux/platform_data/dmtimer-omap.h>
27#include <linux/platform_data/pwm_omap_dmtimer.h>
28#include <linux/platform_device.h>
29#include <linux/pm_runtime.h>
30#include <linux/pwm.h>
31#include <linux/slab.h>
32#include <linux/time.h>
33
34#define DM_TIMER_LOAD_MIN 0xfffffffe
35#define DM_TIMER_MAX 0xffffffff
36
37struct pwm_omap_dmtimer_chip {
38 struct pwm_chip chip;
39 struct mutex mutex;
40 pwm_omap_dmtimer *dm_timer;
41 const struct omap_dm_timer_ops *pdata;
42 struct platform_device *dm_timer_pdev;
43};
44
45static inline struct pwm_omap_dmtimer_chip *
46to_pwm_omap_dmtimer_chip(struct pwm_chip *chip)
47{
48 return container_of(chip, struct pwm_omap_dmtimer_chip, chip);
49}
50
51static u32 pwm_omap_dmtimer_get_clock_cycles(unsigned long clk_rate, int ns)
52{
53 return DIV_ROUND_CLOSEST_ULL((u64)clk_rate * ns, NSEC_PER_SEC);
54}
55
56static void pwm_omap_dmtimer_start(struct pwm_omap_dmtimer_chip *omap)
57{
58 /*
59 * According to OMAP 4 TRM section 22.2.4.10 the counter should be
60 * started at 0xFFFFFFFE when overflow and match is used to ensure
61 * that the PWM line is toggled on the first event.
62 *
63 * Note that omap_dm_timer_enable/disable is for register access and
64 * not the timer counter itself.
65 */
66 omap->pdata->enable(omap->dm_timer);
67 omap->pdata->write_counter(omap->dm_timer, DM_TIMER_LOAD_MIN);
68 omap->pdata->disable(omap->dm_timer);
69
70 omap->pdata->start(omap->dm_timer);
71}
72
73static int pwm_omap_dmtimer_enable(struct pwm_chip *chip,
74 struct pwm_device *pwm)
75{
76 struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
77
78 mutex_lock(&omap->mutex);
79 pwm_omap_dmtimer_start(omap);
80 mutex_unlock(&omap->mutex);
81
82 return 0;
83}
84
85static void pwm_omap_dmtimer_disable(struct pwm_chip *chip,
86 struct pwm_device *pwm)
87{
88 struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
89
90 mutex_lock(&omap->mutex);
91 omap->pdata->stop(omap->dm_timer);
92 mutex_unlock(&omap->mutex);
93}
94
95static int pwm_omap_dmtimer_config(struct pwm_chip *chip,
96 struct pwm_device *pwm,
97 int duty_ns, int period_ns)
98{
99 struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
100 u32 period_cycles, duty_cycles;
101 u32 load_value, match_value;
102 struct clk *fclk;
103 unsigned long clk_rate;
104 bool timer_active;
105
106 dev_dbg(chip->dev, "requested duty cycle: %d ns, period: %d ns\n",
107 duty_ns, period_ns);
108
109 mutex_lock(&omap->mutex);
110 if (duty_ns == pwm_get_duty_cycle(pwm) &&
111 period_ns == pwm_get_period(pwm)) {
112 /* No change - don't cause any transients. */
113 mutex_unlock(&omap->mutex);
114 return 0;
115 }
116
117 fclk = omap->pdata->get_fclk(omap->dm_timer);
118 if (!fclk) {
119 dev_err(chip->dev, "invalid pmtimer fclk\n");
120 goto err_einval;
121 }
122
123 clk_rate = clk_get_rate(fclk);
124 if (!clk_rate) {
125 dev_err(chip->dev, "invalid pmtimer fclk rate\n");
126 goto err_einval;
127 }
128
129 dev_dbg(chip->dev, "clk rate: %luHz\n", clk_rate);
130
131 /*
132 * Calculate the appropriate load and match values based on the
133 * specified period and duty cycle. The load value determines the
134 * period time and the match value determines the duty time.
135 *
136 * The period lasts for (DM_TIMER_MAX-load_value+1) clock cycles.
137 * Similarly, the active time lasts (match_value-load_value+1) cycles.
138 * The non-active time is the remainder: (DM_TIMER_MAX-match_value)
139 * clock cycles.
140 *
141 * NOTE: It is required that: load_value <= match_value < DM_TIMER_MAX
142 *
143 * References:
144 * OMAP4430/60/70 TRM sections 22.2.4.10 and 22.2.4.11
145 * AM335x Sitara TRM sections 20.1.3.5 and 20.1.3.6
146 */
147 period_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, period_ns);
148 duty_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, duty_ns);
149
150 if (period_cycles < 2) {
151 dev_info(chip->dev,
152 "period %d ns too short for clock rate %lu Hz\n",
153 period_ns, clk_rate);
154 goto err_einval;
155 }
156
157 if (duty_cycles < 1) {
158 dev_dbg(chip->dev,
159 "duty cycle %d ns is too short for clock rate %lu Hz\n",
160 duty_ns, clk_rate);
161 dev_dbg(chip->dev, "using minimum of 1 clock cycle\n");
162 duty_cycles = 1;
163 } else if (duty_cycles >= period_cycles) {
164 dev_dbg(chip->dev,
165 "duty cycle %d ns is too long for period %d ns at clock rate %lu Hz\n",
166 duty_ns, period_ns, clk_rate);
167 dev_dbg(chip->dev, "using maximum of 1 clock cycle less than period\n");
168 duty_cycles = period_cycles - 1;
169 }
170
171 dev_dbg(chip->dev, "effective duty cycle: %lld ns, period: %lld ns\n",
172 DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * duty_cycles,
173 clk_rate),
174 DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * period_cycles,
175 clk_rate));
176
177 load_value = (DM_TIMER_MAX - period_cycles) + 1;
178 match_value = load_value + duty_cycles - 1;
179
180 /*
181 * We MUST stop the associated dual-mode timer before attempting to
182 * write its registers, but calls to omap_dm_timer_start/stop must
183 * be balanced so check if timer is active before calling timer_stop.
184 */
185 timer_active = pm_runtime_active(&omap->dm_timer_pdev->dev);
186 if (timer_active)
187 omap->pdata->stop(omap->dm_timer);
188
189 omap->pdata->set_load(omap->dm_timer, true, load_value);
190 omap->pdata->set_match(omap->dm_timer, true, match_value);
191
192 dev_dbg(chip->dev, "load value: %#08x (%d), match value: %#08x (%d)\n",
193 load_value, load_value, match_value, match_value);
194
195 omap->pdata->set_pwm(omap->dm_timer,
196 pwm_get_polarity(pwm) == PWM_POLARITY_INVERSED,
197 true,
198 PWM_OMAP_DMTIMER_TRIGGER_OVERFLOW_AND_COMPARE);
199
200 /* If config was called while timer was running it must be reenabled. */
201 if (timer_active)
202 pwm_omap_dmtimer_start(omap);
203
204 mutex_unlock(&omap->mutex);
205
206 return 0;
207
208err_einval:
209 mutex_unlock(&omap->mutex);
210
211 return -EINVAL;
212}
213
214static int pwm_omap_dmtimer_set_polarity(struct pwm_chip *chip,
215 struct pwm_device *pwm,
216 enum pwm_polarity polarity)
217{
218 struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
219
220 /*
221 * PWM core will not call set_polarity while PWM is enabled so it's
222 * safe to reconfigure the timer here without stopping it first.
223 */
224 mutex_lock(&omap->mutex);
225 omap->pdata->set_pwm(omap->dm_timer,
226 polarity == PWM_POLARITY_INVERSED,
227 true,
228 PWM_OMAP_DMTIMER_TRIGGER_OVERFLOW_AND_COMPARE);
229 mutex_unlock(&omap->mutex);
230
231 return 0;
232}
233
234static const struct pwm_ops pwm_omap_dmtimer_ops = {
235 .enable = pwm_omap_dmtimer_enable,
236 .disable = pwm_omap_dmtimer_disable,
237 .config = pwm_omap_dmtimer_config,
238 .set_polarity = pwm_omap_dmtimer_set_polarity,
239 .owner = THIS_MODULE,
240};
241
242static int pwm_omap_dmtimer_probe(struct platform_device *pdev)
243{
244 struct device_node *np = pdev->dev.of_node;
245 struct device_node *timer;
246 struct platform_device *timer_pdev;
247 struct pwm_omap_dmtimer_chip *omap;
248 struct dmtimer_platform_data *timer_pdata;
249 const struct omap_dm_timer_ops *pdata;
250 pwm_omap_dmtimer *dm_timer;
251 u32 v;
252 int ret = 0;
253
254 timer = of_parse_phandle(np, "ti,timers", 0);
255 if (!timer)
256 return -ENODEV;
257
258 timer_pdev = of_find_device_by_node(timer);
259 if (!timer_pdev) {
260 dev_err(&pdev->dev, "Unable to find Timer pdev\n");
261 ret = -ENODEV;
262 goto put;
263 }
264
265 timer_pdata = dev_get_platdata(&timer_pdev->dev);
266 if (!timer_pdata) {
267 dev_err(&pdev->dev, "dmtimer pdata structure NULL\n");
268 ret = -EINVAL;
269 goto put;
270 }
271
272 pdata = timer_pdata->timer_ops;
273
274 if (!pdata || !pdata->request_by_node ||
275 !pdata->free ||
276 !pdata->enable ||
277 !pdata->disable ||
278 !pdata->get_fclk ||
279 !pdata->start ||
280 !pdata->stop ||
281 !pdata->set_load ||
282 !pdata->set_match ||
283 !pdata->set_pwm ||
284 !pdata->set_prescaler ||
285 !pdata->write_counter) {
286 dev_err(&pdev->dev, "Incomplete dmtimer pdata structure\n");
287 ret = -EINVAL;
288 goto put;
289 }
290
291 if (!of_get_property(timer, "ti,timer-pwm", NULL)) {
292 dev_err(&pdev->dev, "Missing ti,timer-pwm capability\n");
293 ret = -ENODEV;
294 goto put;
295 }
296
297 dm_timer = pdata->request_by_node(timer);
298 if (!dm_timer) {
299 ret = -EPROBE_DEFER;
300 goto put;
301 }
302
303put:
304 of_node_put(timer);
305 if (ret < 0)
306 return ret;
307
308 omap = devm_kzalloc(&pdev->dev, sizeof(*omap), GFP_KERNEL);
309 if (!omap) {
310 pdata->free(dm_timer);
311 return -ENOMEM;
312 }
313
314 omap->pdata = pdata;
315 omap->dm_timer = dm_timer;
316 omap->dm_timer_pdev = timer_pdev;
317
318 /*
319 * Ensure that the timer is stopped before we allow PWM core to call
320 * pwm_enable.
321 */
322 if (pm_runtime_active(&omap->dm_timer_pdev->dev))
323 omap->pdata->stop(omap->dm_timer);
324
325 if (!of_property_read_u32(pdev->dev.of_node, "ti,prescaler", &v))
326 omap->pdata->set_prescaler(omap->dm_timer, v);
327
328 /* setup dmtimer clock source */
329 if (!of_property_read_u32(pdev->dev.of_node, "ti,clock-source", &v))
330 omap->pdata->set_source(omap->dm_timer, v);
331
332 omap->chip.dev = &pdev->dev;
333 omap->chip.ops = &pwm_omap_dmtimer_ops;
334 omap->chip.base = -1;
335 omap->chip.npwm = 1;
336 omap->chip.of_xlate = of_pwm_xlate_with_flags;
337 omap->chip.of_pwm_n_cells = 3;
338
339 mutex_init(&omap->mutex);
340
341 ret = pwmchip_add(&omap->chip);
342 if (ret < 0) {
343 dev_err(&pdev->dev, "failed to register PWM\n");
344 omap->pdata->free(omap->dm_timer);
345 return ret;
346 }
347
348 platform_set_drvdata(pdev, omap);
349
350 return 0;
351}
352
353static int pwm_omap_dmtimer_remove(struct platform_device *pdev)
354{
355 struct pwm_omap_dmtimer_chip *omap = platform_get_drvdata(pdev);
356
357 if (pm_runtime_active(&omap->dm_timer_pdev->dev))
358 omap->pdata->stop(omap->dm_timer);
359
360 omap->pdata->free(omap->dm_timer);
361
362 mutex_destroy(&omap->mutex);
363
364 return pwmchip_remove(&omap->chip);
365}
366
367static const struct of_device_id pwm_omap_dmtimer_of_match[] = {
368 {.compatible = "ti,omap-dmtimer-pwm"},
369 {}
370};
371MODULE_DEVICE_TABLE(of, pwm_omap_dmtimer_of_match);
372
373static struct platform_driver pwm_omap_dmtimer_driver = {
374 .driver = {
375 .name = "omap-dmtimer-pwm",
376 .of_match_table = of_match_ptr(pwm_omap_dmtimer_of_match),
377 },
378 .probe = pwm_omap_dmtimer_probe,
379 .remove = pwm_omap_dmtimer_remove,
380};
381module_platform_driver(pwm_omap_dmtimer_driver);
382
383MODULE_AUTHOR("Grant Erickson <marathon96@gmail.com>");
384MODULE_AUTHOR("NeilBrown <neilb@suse.de>");
385MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
386MODULE_LICENSE("GPL v2");
387MODULE_DESCRIPTION("OMAP PWM Driver using Dual-mode Timers");
1/*
2 * Copyright (c) 2015 Neil Armstrong <narmstrong@baylibre.com>
3 * Copyright (c) 2014 Joachim Eastwood <manabian@gmail.com>
4 * Copyright (c) 2012 NeilBrown <neilb@suse.de>
5 * Heavily based on earlier code which is:
6 * Copyright (c) 2010 Grant Erickson <marathon96@gmail.com>
7 *
8 * Also based on pwm-samsung.c
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * Description:
15 * This file is the core OMAP support for the generic, Linux
16 * PWM driver / controller, using the OMAP's dual-mode timers.
17 */
18
19#include <linux/clk.h>
20#include <linux/err.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/mutex.h>
24#include <linux/of.h>
25#include <linux/of_platform.h>
26#include <linux/platform_data/pwm_omap_dmtimer.h>
27#include <linux/platform_device.h>
28#include <linux/pm_runtime.h>
29#include <linux/pwm.h>
30#include <linux/slab.h>
31#include <linux/time.h>
32
33#define DM_TIMER_LOAD_MIN 0xfffffffe
34#define DM_TIMER_MAX 0xffffffff
35
36struct pwm_omap_dmtimer_chip {
37 struct pwm_chip chip;
38 struct mutex mutex;
39 pwm_omap_dmtimer *dm_timer;
40 struct pwm_omap_dmtimer_pdata *pdata;
41 struct platform_device *dm_timer_pdev;
42};
43
44static inline struct pwm_omap_dmtimer_chip *
45to_pwm_omap_dmtimer_chip(struct pwm_chip *chip)
46{
47 return container_of(chip, struct pwm_omap_dmtimer_chip, chip);
48}
49
50static u32 pwm_omap_dmtimer_get_clock_cycles(unsigned long clk_rate, int ns)
51{
52 return DIV_ROUND_CLOSEST_ULL((u64)clk_rate * ns, NSEC_PER_SEC);
53}
54
55static void pwm_omap_dmtimer_start(struct pwm_omap_dmtimer_chip *omap)
56{
57 /*
58 * According to OMAP 4 TRM section 22.2.4.10 the counter should be
59 * started at 0xFFFFFFFE when overflow and match is used to ensure
60 * that the PWM line is toggled on the first event.
61 *
62 * Note that omap_dm_timer_enable/disable is for register access and
63 * not the timer counter itself.
64 */
65 omap->pdata->enable(omap->dm_timer);
66 omap->pdata->write_counter(omap->dm_timer, DM_TIMER_LOAD_MIN);
67 omap->pdata->disable(omap->dm_timer);
68
69 omap->pdata->start(omap->dm_timer);
70}
71
72static int pwm_omap_dmtimer_enable(struct pwm_chip *chip,
73 struct pwm_device *pwm)
74{
75 struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
76
77 mutex_lock(&omap->mutex);
78 pwm_omap_dmtimer_start(omap);
79 mutex_unlock(&omap->mutex);
80
81 return 0;
82}
83
84static void pwm_omap_dmtimer_disable(struct pwm_chip *chip,
85 struct pwm_device *pwm)
86{
87 struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
88
89 mutex_lock(&omap->mutex);
90 omap->pdata->stop(omap->dm_timer);
91 mutex_unlock(&omap->mutex);
92}
93
94static int pwm_omap_dmtimer_config(struct pwm_chip *chip,
95 struct pwm_device *pwm,
96 int duty_ns, int period_ns)
97{
98 struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
99 u32 period_cycles, duty_cycles;
100 u32 load_value, match_value;
101 struct clk *fclk;
102 unsigned long clk_rate;
103 bool timer_active;
104
105 dev_dbg(chip->dev, "requested duty cycle: %d ns, period: %d ns\n",
106 duty_ns, period_ns);
107
108 mutex_lock(&omap->mutex);
109 if (duty_ns == pwm_get_duty_cycle(pwm) &&
110 period_ns == pwm_get_period(pwm)) {
111 /* No change - don't cause any transients. */
112 mutex_unlock(&omap->mutex);
113 return 0;
114 }
115
116 fclk = omap->pdata->get_fclk(omap->dm_timer);
117 if (!fclk) {
118 dev_err(chip->dev, "invalid pmtimer fclk\n");
119 goto err_einval;
120 }
121
122 clk_rate = clk_get_rate(fclk);
123 if (!clk_rate) {
124 dev_err(chip->dev, "invalid pmtimer fclk rate\n");
125 goto err_einval;
126 }
127
128 dev_dbg(chip->dev, "clk rate: %luHz\n", clk_rate);
129
130 /*
131 * Calculate the appropriate load and match values based on the
132 * specified period and duty cycle. The load value determines the
133 * period time and the match value determines the duty time.
134 *
135 * The period lasts for (DM_TIMER_MAX-load_value+1) clock cycles.
136 * Similarly, the active time lasts (match_value-load_value+1) cycles.
137 * The non-active time is the remainder: (DM_TIMER_MAX-match_value)
138 * clock cycles.
139 *
140 * NOTE: It is required that: load_value <= match_value < DM_TIMER_MAX
141 *
142 * References:
143 * OMAP4430/60/70 TRM sections 22.2.4.10 and 22.2.4.11
144 * AM335x Sitara TRM sections 20.1.3.5 and 20.1.3.6
145 */
146 period_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, period_ns);
147 duty_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, duty_ns);
148
149 if (period_cycles < 2) {
150 dev_info(chip->dev,
151 "period %d ns too short for clock rate %lu Hz\n",
152 period_ns, clk_rate);
153 goto err_einval;
154 }
155
156 if (duty_cycles < 1) {
157 dev_dbg(chip->dev,
158 "duty cycle %d ns is too short for clock rate %lu Hz\n",
159 duty_ns, clk_rate);
160 dev_dbg(chip->dev, "using minimum of 1 clock cycle\n");
161 duty_cycles = 1;
162 } else if (duty_cycles >= period_cycles) {
163 dev_dbg(chip->dev,
164 "duty cycle %d ns is too long for period %d ns at clock rate %lu Hz\n",
165 duty_ns, period_ns, clk_rate);
166 dev_dbg(chip->dev, "using maximum of 1 clock cycle less than period\n");
167 duty_cycles = period_cycles - 1;
168 }
169
170 dev_dbg(chip->dev, "effective duty cycle: %lld ns, period: %lld ns\n",
171 DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * duty_cycles,
172 clk_rate),
173 DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * period_cycles,
174 clk_rate));
175
176 load_value = (DM_TIMER_MAX - period_cycles) + 1;
177 match_value = load_value + duty_cycles - 1;
178
179 /*
180 * We MUST stop the associated dual-mode timer before attempting to
181 * write its registers, but calls to omap_dm_timer_start/stop must
182 * be balanced so check if timer is active before calling timer_stop.
183 */
184 timer_active = pm_runtime_active(&omap->dm_timer_pdev->dev);
185 if (timer_active)
186 omap->pdata->stop(omap->dm_timer);
187
188 omap->pdata->set_load(omap->dm_timer, true, load_value);
189 omap->pdata->set_match(omap->dm_timer, true, match_value);
190
191 dev_dbg(chip->dev, "load value: %#08x (%d), match value: %#08x (%d)\n",
192 load_value, load_value, match_value, match_value);
193
194 omap->pdata->set_pwm(omap->dm_timer,
195 pwm_get_polarity(pwm) == PWM_POLARITY_INVERSED,
196 true,
197 PWM_OMAP_DMTIMER_TRIGGER_OVERFLOW_AND_COMPARE);
198
199 /* If config was called while timer was running it must be reenabled. */
200 if (timer_active)
201 pwm_omap_dmtimer_start(omap);
202
203 mutex_unlock(&omap->mutex);
204
205 return 0;
206
207err_einval:
208 mutex_unlock(&omap->mutex);
209
210 return -EINVAL;
211}
212
213static int pwm_omap_dmtimer_set_polarity(struct pwm_chip *chip,
214 struct pwm_device *pwm,
215 enum pwm_polarity polarity)
216{
217 struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
218
219 /*
220 * PWM core will not call set_polarity while PWM is enabled so it's
221 * safe to reconfigure the timer here without stopping it first.
222 */
223 mutex_lock(&omap->mutex);
224 omap->pdata->set_pwm(omap->dm_timer,
225 polarity == PWM_POLARITY_INVERSED,
226 true,
227 PWM_OMAP_DMTIMER_TRIGGER_OVERFLOW_AND_COMPARE);
228 mutex_unlock(&omap->mutex);
229
230 return 0;
231}
232
233static const struct pwm_ops pwm_omap_dmtimer_ops = {
234 .enable = pwm_omap_dmtimer_enable,
235 .disable = pwm_omap_dmtimer_disable,
236 .config = pwm_omap_dmtimer_config,
237 .set_polarity = pwm_omap_dmtimer_set_polarity,
238 .owner = THIS_MODULE,
239};
240
241static int pwm_omap_dmtimer_probe(struct platform_device *pdev)
242{
243 struct device_node *np = pdev->dev.of_node;
244 struct device_node *timer;
245 struct pwm_omap_dmtimer_chip *omap;
246 struct pwm_omap_dmtimer_pdata *pdata;
247 pwm_omap_dmtimer *dm_timer;
248 u32 v;
249 int status;
250
251 pdata = dev_get_platdata(&pdev->dev);
252 if (!pdata) {
253 dev_err(&pdev->dev, "Missing dmtimer platform data\n");
254 return -EINVAL;
255 }
256
257 if (!pdata->request_by_node ||
258 !pdata->free ||
259 !pdata->enable ||
260 !pdata->disable ||
261 !pdata->get_fclk ||
262 !pdata->start ||
263 !pdata->stop ||
264 !pdata->set_load ||
265 !pdata->set_match ||
266 !pdata->set_pwm ||
267 !pdata->set_prescaler ||
268 !pdata->write_counter) {
269 dev_err(&pdev->dev, "Incomplete dmtimer pdata structure\n");
270 return -EINVAL;
271 }
272
273 timer = of_parse_phandle(np, "ti,timers", 0);
274 if (!timer)
275 return -ENODEV;
276
277 if (!of_get_property(timer, "ti,timer-pwm", NULL)) {
278 dev_err(&pdev->dev, "Missing ti,timer-pwm capability\n");
279 return -ENODEV;
280 }
281
282 dm_timer = pdata->request_by_node(timer);
283 if (!dm_timer)
284 return -EPROBE_DEFER;
285
286 omap = devm_kzalloc(&pdev->dev, sizeof(*omap), GFP_KERNEL);
287 if (!omap) {
288 pdata->free(dm_timer);
289 return -ENOMEM;
290 }
291
292 omap->pdata = pdata;
293 omap->dm_timer = dm_timer;
294
295 omap->dm_timer_pdev = of_find_device_by_node(timer);
296 if (!omap->dm_timer_pdev) {
297 dev_err(&pdev->dev, "Unable to find timer pdev\n");
298 omap->pdata->free(dm_timer);
299 return -EINVAL;
300 }
301
302 /*
303 * Ensure that the timer is stopped before we allow PWM core to call
304 * pwm_enable.
305 */
306 if (pm_runtime_active(&omap->dm_timer_pdev->dev))
307 omap->pdata->stop(omap->dm_timer);
308
309 if (!of_property_read_u32(pdev->dev.of_node, "ti,prescaler", &v))
310 omap->pdata->set_prescaler(omap->dm_timer, v);
311
312 /* setup dmtimer clock source */
313 if (!of_property_read_u32(pdev->dev.of_node, "ti,clock-source", &v))
314 omap->pdata->set_source(omap->dm_timer, v);
315
316 omap->chip.dev = &pdev->dev;
317 omap->chip.ops = &pwm_omap_dmtimer_ops;
318 omap->chip.base = -1;
319 omap->chip.npwm = 1;
320 omap->chip.of_xlate = of_pwm_xlate_with_flags;
321 omap->chip.of_pwm_n_cells = 3;
322
323 mutex_init(&omap->mutex);
324
325 status = pwmchip_add(&omap->chip);
326 if (status < 0) {
327 dev_err(&pdev->dev, "failed to register PWM\n");
328 omap->pdata->free(omap->dm_timer);
329 return status;
330 }
331
332 platform_set_drvdata(pdev, omap);
333
334 return 0;
335}
336
337static int pwm_omap_dmtimer_remove(struct platform_device *pdev)
338{
339 struct pwm_omap_dmtimer_chip *omap = platform_get_drvdata(pdev);
340
341 if (pm_runtime_active(&omap->dm_timer_pdev->dev))
342 omap->pdata->stop(omap->dm_timer);
343
344 omap->pdata->free(omap->dm_timer);
345
346 mutex_destroy(&omap->mutex);
347
348 return pwmchip_remove(&omap->chip);
349}
350
351static const struct of_device_id pwm_omap_dmtimer_of_match[] = {
352 {.compatible = "ti,omap-dmtimer-pwm"},
353 {}
354};
355MODULE_DEVICE_TABLE(of, pwm_omap_dmtimer_of_match);
356
357static struct platform_driver pwm_omap_dmtimer_driver = {
358 .driver = {
359 .name = "omap-dmtimer-pwm",
360 .of_match_table = of_match_ptr(pwm_omap_dmtimer_of_match),
361 },
362 .probe = pwm_omap_dmtimer_probe,
363 .remove = pwm_omap_dmtimer_remove,
364};
365module_platform_driver(pwm_omap_dmtimer_driver);
366
367MODULE_AUTHOR("Grant Erickson <marathon96@gmail.com>");
368MODULE_AUTHOR("NeilBrown <neilb@suse.de>");
369MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
370MODULE_LICENSE("GPL v2");
371MODULE_DESCRIPTION("OMAP PWM Driver using Dual-mode Timers");