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1/*
2 * Copyright (c) 2015 Neil Armstrong <narmstrong@baylibre.com>
3 * Copyright (c) 2014 Joachim Eastwood <manabian@gmail.com>
4 * Copyright (c) 2012 NeilBrown <neilb@suse.de>
5 * Heavily based on earlier code which is:
6 * Copyright (c) 2010 Grant Erickson <marathon96@gmail.com>
7 *
8 * Also based on pwm-samsung.c
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * Description:
15 * This file is the core OMAP support for the generic, Linux
16 * PWM driver / controller, using the OMAP's dual-mode timers.
17 */
18
19#include <linux/clk.h>
20#include <linux/err.h>
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/mutex.h>
24#include <linux/of.h>
25#include <linux/of_platform.h>
26#include <linux/platform_data/dmtimer-omap.h>
27#include <linux/platform_data/pwm_omap_dmtimer.h>
28#include <linux/platform_device.h>
29#include <linux/pm_runtime.h>
30#include <linux/pwm.h>
31#include <linux/slab.h>
32#include <linux/time.h>
33
34#define DM_TIMER_LOAD_MIN 0xfffffffe
35#define DM_TIMER_MAX 0xffffffff
36
37struct pwm_omap_dmtimer_chip {
38 struct pwm_chip chip;
39 struct mutex mutex;
40 pwm_omap_dmtimer *dm_timer;
41 const struct omap_dm_timer_ops *pdata;
42 struct platform_device *dm_timer_pdev;
43};
44
45static inline struct pwm_omap_dmtimer_chip *
46to_pwm_omap_dmtimer_chip(struct pwm_chip *chip)
47{
48 return container_of(chip, struct pwm_omap_dmtimer_chip, chip);
49}
50
51static u32 pwm_omap_dmtimer_get_clock_cycles(unsigned long clk_rate, int ns)
52{
53 return DIV_ROUND_CLOSEST_ULL((u64)clk_rate * ns, NSEC_PER_SEC);
54}
55
56static void pwm_omap_dmtimer_start(struct pwm_omap_dmtimer_chip *omap)
57{
58 /*
59 * According to OMAP 4 TRM section 22.2.4.10 the counter should be
60 * started at 0xFFFFFFFE when overflow and match is used to ensure
61 * that the PWM line is toggled on the first event.
62 *
63 * Note that omap_dm_timer_enable/disable is for register access and
64 * not the timer counter itself.
65 */
66 omap->pdata->enable(omap->dm_timer);
67 omap->pdata->write_counter(omap->dm_timer, DM_TIMER_LOAD_MIN);
68 omap->pdata->disable(omap->dm_timer);
69
70 omap->pdata->start(omap->dm_timer);
71}
72
73static int pwm_omap_dmtimer_enable(struct pwm_chip *chip,
74 struct pwm_device *pwm)
75{
76 struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
77
78 mutex_lock(&omap->mutex);
79 pwm_omap_dmtimer_start(omap);
80 mutex_unlock(&omap->mutex);
81
82 return 0;
83}
84
85static void pwm_omap_dmtimer_disable(struct pwm_chip *chip,
86 struct pwm_device *pwm)
87{
88 struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
89
90 mutex_lock(&omap->mutex);
91 omap->pdata->stop(omap->dm_timer);
92 mutex_unlock(&omap->mutex);
93}
94
95static int pwm_omap_dmtimer_config(struct pwm_chip *chip,
96 struct pwm_device *pwm,
97 int duty_ns, int period_ns)
98{
99 struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
100 u32 period_cycles, duty_cycles;
101 u32 load_value, match_value;
102 struct clk *fclk;
103 unsigned long clk_rate;
104 bool timer_active;
105
106 dev_dbg(chip->dev, "requested duty cycle: %d ns, period: %d ns\n",
107 duty_ns, period_ns);
108
109 mutex_lock(&omap->mutex);
110 if (duty_ns == pwm_get_duty_cycle(pwm) &&
111 period_ns == pwm_get_period(pwm)) {
112 /* No change - don't cause any transients. */
113 mutex_unlock(&omap->mutex);
114 return 0;
115 }
116
117 fclk = omap->pdata->get_fclk(omap->dm_timer);
118 if (!fclk) {
119 dev_err(chip->dev, "invalid pmtimer fclk\n");
120 goto err_einval;
121 }
122
123 clk_rate = clk_get_rate(fclk);
124 if (!clk_rate) {
125 dev_err(chip->dev, "invalid pmtimer fclk rate\n");
126 goto err_einval;
127 }
128
129 dev_dbg(chip->dev, "clk rate: %luHz\n", clk_rate);
130
131 /*
132 * Calculate the appropriate load and match values based on the
133 * specified period and duty cycle. The load value determines the
134 * period time and the match value determines the duty time.
135 *
136 * The period lasts for (DM_TIMER_MAX-load_value+1) clock cycles.
137 * Similarly, the active time lasts (match_value-load_value+1) cycles.
138 * The non-active time is the remainder: (DM_TIMER_MAX-match_value)
139 * clock cycles.
140 *
141 * NOTE: It is required that: load_value <= match_value < DM_TIMER_MAX
142 *
143 * References:
144 * OMAP4430/60/70 TRM sections 22.2.4.10 and 22.2.4.11
145 * AM335x Sitara TRM sections 20.1.3.5 and 20.1.3.6
146 */
147 period_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, period_ns);
148 duty_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, duty_ns);
149
150 if (period_cycles < 2) {
151 dev_info(chip->dev,
152 "period %d ns too short for clock rate %lu Hz\n",
153 period_ns, clk_rate);
154 goto err_einval;
155 }
156
157 if (duty_cycles < 1) {
158 dev_dbg(chip->dev,
159 "duty cycle %d ns is too short for clock rate %lu Hz\n",
160 duty_ns, clk_rate);
161 dev_dbg(chip->dev, "using minimum of 1 clock cycle\n");
162 duty_cycles = 1;
163 } else if (duty_cycles >= period_cycles) {
164 dev_dbg(chip->dev,
165 "duty cycle %d ns is too long for period %d ns at clock rate %lu Hz\n",
166 duty_ns, period_ns, clk_rate);
167 dev_dbg(chip->dev, "using maximum of 1 clock cycle less than period\n");
168 duty_cycles = period_cycles - 1;
169 }
170
171 dev_dbg(chip->dev, "effective duty cycle: %lld ns, period: %lld ns\n",
172 DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * duty_cycles,
173 clk_rate),
174 DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * period_cycles,
175 clk_rate));
176
177 load_value = (DM_TIMER_MAX - period_cycles) + 1;
178 match_value = load_value + duty_cycles - 1;
179
180 /*
181 * We MUST stop the associated dual-mode timer before attempting to
182 * write its registers, but calls to omap_dm_timer_start/stop must
183 * be balanced so check if timer is active before calling timer_stop.
184 */
185 timer_active = pm_runtime_active(&omap->dm_timer_pdev->dev);
186 if (timer_active)
187 omap->pdata->stop(omap->dm_timer);
188
189 omap->pdata->set_load(omap->dm_timer, true, load_value);
190 omap->pdata->set_match(omap->dm_timer, true, match_value);
191
192 dev_dbg(chip->dev, "load value: %#08x (%d), match value: %#08x (%d)\n",
193 load_value, load_value, match_value, match_value);
194
195 omap->pdata->set_pwm(omap->dm_timer,
196 pwm_get_polarity(pwm) == PWM_POLARITY_INVERSED,
197 true,
198 PWM_OMAP_DMTIMER_TRIGGER_OVERFLOW_AND_COMPARE);
199
200 /* If config was called while timer was running it must be reenabled. */
201 if (timer_active)
202 pwm_omap_dmtimer_start(omap);
203
204 mutex_unlock(&omap->mutex);
205
206 return 0;
207
208err_einval:
209 mutex_unlock(&omap->mutex);
210
211 return -EINVAL;
212}
213
214static int pwm_omap_dmtimer_set_polarity(struct pwm_chip *chip,
215 struct pwm_device *pwm,
216 enum pwm_polarity polarity)
217{
218 struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
219
220 /*
221 * PWM core will not call set_polarity while PWM is enabled so it's
222 * safe to reconfigure the timer here without stopping it first.
223 */
224 mutex_lock(&omap->mutex);
225 omap->pdata->set_pwm(omap->dm_timer,
226 polarity == PWM_POLARITY_INVERSED,
227 true,
228 PWM_OMAP_DMTIMER_TRIGGER_OVERFLOW_AND_COMPARE);
229 mutex_unlock(&omap->mutex);
230
231 return 0;
232}
233
234static const struct pwm_ops pwm_omap_dmtimer_ops = {
235 .enable = pwm_omap_dmtimer_enable,
236 .disable = pwm_omap_dmtimer_disable,
237 .config = pwm_omap_dmtimer_config,
238 .set_polarity = pwm_omap_dmtimer_set_polarity,
239 .owner = THIS_MODULE,
240};
241
242static int pwm_omap_dmtimer_probe(struct platform_device *pdev)
243{
244 struct device_node *np = pdev->dev.of_node;
245 struct device_node *timer;
246 struct platform_device *timer_pdev;
247 struct pwm_omap_dmtimer_chip *omap;
248 struct dmtimer_platform_data *timer_pdata;
249 const struct omap_dm_timer_ops *pdata;
250 pwm_omap_dmtimer *dm_timer;
251 u32 v;
252 int ret = 0;
253
254 timer = of_parse_phandle(np, "ti,timers", 0);
255 if (!timer)
256 return -ENODEV;
257
258 timer_pdev = of_find_device_by_node(timer);
259 if (!timer_pdev) {
260 dev_err(&pdev->dev, "Unable to find Timer pdev\n");
261 ret = -ENODEV;
262 goto put;
263 }
264
265 timer_pdata = dev_get_platdata(&timer_pdev->dev);
266 if (!timer_pdata) {
267 dev_err(&pdev->dev, "dmtimer pdata structure NULL\n");
268 ret = -EINVAL;
269 goto put;
270 }
271
272 pdata = timer_pdata->timer_ops;
273
274 if (!pdata || !pdata->request_by_node ||
275 !pdata->free ||
276 !pdata->enable ||
277 !pdata->disable ||
278 !pdata->get_fclk ||
279 !pdata->start ||
280 !pdata->stop ||
281 !pdata->set_load ||
282 !pdata->set_match ||
283 !pdata->set_pwm ||
284 !pdata->set_prescaler ||
285 !pdata->write_counter) {
286 dev_err(&pdev->dev, "Incomplete dmtimer pdata structure\n");
287 ret = -EINVAL;
288 goto put;
289 }
290
291 if (!of_get_property(timer, "ti,timer-pwm", NULL)) {
292 dev_err(&pdev->dev, "Missing ti,timer-pwm capability\n");
293 ret = -ENODEV;
294 goto put;
295 }
296
297 dm_timer = pdata->request_by_node(timer);
298 if (!dm_timer) {
299 ret = -EPROBE_DEFER;
300 goto put;
301 }
302
303put:
304 of_node_put(timer);
305 if (ret < 0)
306 return ret;
307
308 omap = devm_kzalloc(&pdev->dev, sizeof(*omap), GFP_KERNEL);
309 if (!omap) {
310 pdata->free(dm_timer);
311 return -ENOMEM;
312 }
313
314 omap->pdata = pdata;
315 omap->dm_timer = dm_timer;
316 omap->dm_timer_pdev = timer_pdev;
317
318 /*
319 * Ensure that the timer is stopped before we allow PWM core to call
320 * pwm_enable.
321 */
322 if (pm_runtime_active(&omap->dm_timer_pdev->dev))
323 omap->pdata->stop(omap->dm_timer);
324
325 if (!of_property_read_u32(pdev->dev.of_node, "ti,prescaler", &v))
326 omap->pdata->set_prescaler(omap->dm_timer, v);
327
328 /* setup dmtimer clock source */
329 if (!of_property_read_u32(pdev->dev.of_node, "ti,clock-source", &v))
330 omap->pdata->set_source(omap->dm_timer, v);
331
332 omap->chip.dev = &pdev->dev;
333 omap->chip.ops = &pwm_omap_dmtimer_ops;
334 omap->chip.base = -1;
335 omap->chip.npwm = 1;
336 omap->chip.of_xlate = of_pwm_xlate_with_flags;
337 omap->chip.of_pwm_n_cells = 3;
338
339 mutex_init(&omap->mutex);
340
341 ret = pwmchip_add(&omap->chip);
342 if (ret < 0) {
343 dev_err(&pdev->dev, "failed to register PWM\n");
344 omap->pdata->free(omap->dm_timer);
345 return ret;
346 }
347
348 platform_set_drvdata(pdev, omap);
349
350 return 0;
351}
352
353static int pwm_omap_dmtimer_remove(struct platform_device *pdev)
354{
355 struct pwm_omap_dmtimer_chip *omap = platform_get_drvdata(pdev);
356
357 if (pm_runtime_active(&omap->dm_timer_pdev->dev))
358 omap->pdata->stop(omap->dm_timer);
359
360 omap->pdata->free(omap->dm_timer);
361
362 mutex_destroy(&omap->mutex);
363
364 return pwmchip_remove(&omap->chip);
365}
366
367static const struct of_device_id pwm_omap_dmtimer_of_match[] = {
368 {.compatible = "ti,omap-dmtimer-pwm"},
369 {}
370};
371MODULE_DEVICE_TABLE(of, pwm_omap_dmtimer_of_match);
372
373static struct platform_driver pwm_omap_dmtimer_driver = {
374 .driver = {
375 .name = "omap-dmtimer-pwm",
376 .of_match_table = of_match_ptr(pwm_omap_dmtimer_of_match),
377 },
378 .probe = pwm_omap_dmtimer_probe,
379 .remove = pwm_omap_dmtimer_remove,
380};
381module_platform_driver(pwm_omap_dmtimer_driver);
382
383MODULE_AUTHOR("Grant Erickson <marathon96@gmail.com>");
384MODULE_AUTHOR("NeilBrown <neilb@suse.de>");
385MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
386MODULE_LICENSE("GPL v2");
387MODULE_DESCRIPTION("OMAP PWM Driver using Dual-mode Timers");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2015 Neil Armstrong <narmstrong@baylibre.com>
4 * Copyright (c) 2014 Joachim Eastwood <manabian@gmail.com>
5 * Copyright (c) 2012 NeilBrown <neilb@suse.de>
6 * Heavily based on earlier code which is:
7 * Copyright (c) 2010 Grant Erickson <marathon96@gmail.com>
8 *
9 * Also based on pwm-samsung.c
10 *
11 * Description:
12 * This file is the core OMAP support for the generic, Linux
13 * PWM driver / controller, using the OMAP's dual-mode timers
14 * with a timer counter that goes up. When it overflows it gets
15 * reloaded with the load value and the pwm output goes up.
16 * When counter matches with match register, the output goes down.
17 * Reference Manual: https://www.ti.com/lit/ug/spruh73q/spruh73q.pdf
18 *
19 * Limitations:
20 * - When PWM is stopped, timer counter gets stopped immediately. This
21 * doesn't allow the current PWM period to complete and stops abruptly.
22 * - When PWM is running and changing both duty cycle and period,
23 * we cannot prevent in software that the output might produce
24 * a period with mixed settings. Especially when period/duty_cyle
25 * is updated while the pwm pin is high, current pwm period/duty_cycle
26 * can get updated as below based on the current timer counter:
27 * - period for current cycle = current_period + new period
28 * - duty_cycle for current period = current period + new duty_cycle.
29 * - PWM OMAP DM timer cannot change the polarity when pwm is active. When
30 * user requests a change in polarity when in active state:
31 * - PWM is stopped abruptly(without completing the current cycle)
32 * - Polarity is changed
33 * - A fresh cycle is started.
34 */
35
36#include <linux/clk.h>
37#include <linux/err.h>
38#include <linux/kernel.h>
39#include <linux/module.h>
40#include <linux/mutex.h>
41#include <linux/of.h>
42#include <linux/of_platform.h>
43#include <clocksource/timer-ti-dm.h>
44#include <linux/platform_data/dmtimer-omap.h>
45#include <linux/platform_device.h>
46#include <linux/pm_runtime.h>
47#include <linux/pwm.h>
48#include <linux/slab.h>
49#include <linux/time.h>
50
51#define DM_TIMER_LOAD_MIN 0xfffffffe
52#define DM_TIMER_MAX 0xffffffff
53
54/**
55 * struct pwm_omap_dmtimer_chip - Structure representing a pwm chip
56 * corresponding to omap dmtimer.
57 * @chip: PWM chip structure representing PWM controller
58 * @mutex: Mutex to protect pwm apply state
59 * @dm_timer: Pointer to omap dm timer.
60 * @pdata: Pointer to omap dm timer ops.
61 * @dm_timer_pdev: Pointer to omap dm timer platform device
62 */
63struct pwm_omap_dmtimer_chip {
64 struct pwm_chip chip;
65 /* Mutex to protect pwm apply state */
66 struct mutex mutex;
67 struct omap_dm_timer *dm_timer;
68 const struct omap_dm_timer_ops *pdata;
69 struct platform_device *dm_timer_pdev;
70};
71
72static inline struct pwm_omap_dmtimer_chip *
73to_pwm_omap_dmtimer_chip(struct pwm_chip *chip)
74{
75 return container_of(chip, struct pwm_omap_dmtimer_chip, chip);
76}
77
78/**
79 * pwm_omap_dmtimer_get_clock_cycles() - Get clock cycles in a time frame
80 * @clk_rate: pwm timer clock rate
81 * @ns: time frame in nano seconds.
82 *
83 * Return number of clock cycles in a given period(ins ns).
84 */
85static u32 pwm_omap_dmtimer_get_clock_cycles(unsigned long clk_rate, int ns)
86{
87 return DIV_ROUND_CLOSEST_ULL((u64)clk_rate * ns, NSEC_PER_SEC);
88}
89
90/**
91 * pwm_omap_dmtimer_start() - Start the pwm omap dm timer in pwm mode
92 * @omap: Pointer to pwm omap dm timer chip
93 */
94static void pwm_omap_dmtimer_start(struct pwm_omap_dmtimer_chip *omap)
95{
96 /*
97 * According to OMAP 4 TRM section 22.2.4.10 the counter should be
98 * started at 0xFFFFFFFE when overflow and match is used to ensure
99 * that the PWM line is toggled on the first event.
100 *
101 * Note that omap_dm_timer_enable/disable is for register access and
102 * not the timer counter itself.
103 */
104 omap->pdata->enable(omap->dm_timer);
105 omap->pdata->write_counter(omap->dm_timer, DM_TIMER_LOAD_MIN);
106 omap->pdata->disable(omap->dm_timer);
107
108 omap->pdata->start(omap->dm_timer);
109}
110
111/**
112 * pwm_omap_dmtimer_is_enabled() - Detect if the pwm is enabled.
113 * @omap: Pointer to pwm omap dm timer chip
114 *
115 * Return true if pwm is enabled else false.
116 */
117static bool pwm_omap_dmtimer_is_enabled(struct pwm_omap_dmtimer_chip *omap)
118{
119 u32 status;
120
121 status = omap->pdata->get_pwm_status(omap->dm_timer);
122
123 return !!(status & OMAP_TIMER_CTRL_ST);
124}
125
126/**
127 * pwm_omap_dmtimer_polarity() - Detect the polarity of pwm.
128 * @omap: Pointer to pwm omap dm timer chip
129 *
130 * Return the polarity of pwm.
131 */
132static int pwm_omap_dmtimer_polarity(struct pwm_omap_dmtimer_chip *omap)
133{
134 u32 status;
135
136 status = omap->pdata->get_pwm_status(omap->dm_timer);
137
138 return !!(status & OMAP_TIMER_CTRL_SCPWM);
139}
140
141/**
142 * pwm_omap_dmtimer_config() - Update the configuration of pwm omap dm timer
143 * @chip: Pointer to PWM controller
144 * @pwm: Pointer to PWM channel
145 * @duty_ns: New duty cycle in nano seconds
146 * @period_ns: New period in nano seconds
147 *
148 * Return 0 if successfully changed the period/duty_cycle else appropriate
149 * error.
150 */
151static int pwm_omap_dmtimer_config(struct pwm_chip *chip,
152 struct pwm_device *pwm,
153 int duty_ns, int period_ns)
154{
155 struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
156 u32 period_cycles, duty_cycles;
157 u32 load_value, match_value;
158 unsigned long clk_rate;
159 struct clk *fclk;
160
161 dev_dbg(chip->dev, "requested duty cycle: %d ns, period: %d ns\n",
162 duty_ns, period_ns);
163
164 if (duty_ns == pwm_get_duty_cycle(pwm) &&
165 period_ns == pwm_get_period(pwm))
166 return 0;
167
168 fclk = omap->pdata->get_fclk(omap->dm_timer);
169 if (!fclk) {
170 dev_err(chip->dev, "invalid pmtimer fclk\n");
171 return -EINVAL;
172 }
173
174 clk_rate = clk_get_rate(fclk);
175 if (!clk_rate) {
176 dev_err(chip->dev, "invalid pmtimer fclk rate\n");
177 return -EINVAL;
178 }
179
180 dev_dbg(chip->dev, "clk rate: %luHz\n", clk_rate);
181
182 /*
183 * Calculate the appropriate load and match values based on the
184 * specified period and duty cycle. The load value determines the
185 * period time and the match value determines the duty time.
186 *
187 * The period lasts for (DM_TIMER_MAX-load_value+1) clock cycles.
188 * Similarly, the active time lasts (match_value-load_value+1) cycles.
189 * The non-active time is the remainder: (DM_TIMER_MAX-match_value)
190 * clock cycles.
191 *
192 * NOTE: It is required that: load_value <= match_value < DM_TIMER_MAX
193 *
194 * References:
195 * OMAP4430/60/70 TRM sections 22.2.4.10 and 22.2.4.11
196 * AM335x Sitara TRM sections 20.1.3.5 and 20.1.3.6
197 */
198 period_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, period_ns);
199 duty_cycles = pwm_omap_dmtimer_get_clock_cycles(clk_rate, duty_ns);
200
201 if (period_cycles < 2) {
202 dev_info(chip->dev,
203 "period %d ns too short for clock rate %lu Hz\n",
204 period_ns, clk_rate);
205 return -EINVAL;
206 }
207
208 if (duty_cycles < 1) {
209 dev_dbg(chip->dev,
210 "duty cycle %d ns is too short for clock rate %lu Hz\n",
211 duty_ns, clk_rate);
212 dev_dbg(chip->dev, "using minimum of 1 clock cycle\n");
213 duty_cycles = 1;
214 } else if (duty_cycles >= period_cycles) {
215 dev_dbg(chip->dev,
216 "duty cycle %d ns is too long for period %d ns at clock rate %lu Hz\n",
217 duty_ns, period_ns, clk_rate);
218 dev_dbg(chip->dev, "using maximum of 1 clock cycle less than period\n");
219 duty_cycles = period_cycles - 1;
220 }
221
222 dev_dbg(chip->dev, "effective duty cycle: %lld ns, period: %lld ns\n",
223 DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * duty_cycles,
224 clk_rate),
225 DIV_ROUND_CLOSEST_ULL((u64)NSEC_PER_SEC * period_cycles,
226 clk_rate));
227
228 load_value = (DM_TIMER_MAX - period_cycles) + 1;
229 match_value = load_value + duty_cycles - 1;
230
231 omap->pdata->set_load(omap->dm_timer, load_value);
232 omap->pdata->set_match(omap->dm_timer, true, match_value);
233
234 dev_dbg(chip->dev, "load value: %#08x (%d), match value: %#08x (%d)\n",
235 load_value, load_value, match_value, match_value);
236
237 return 0;
238}
239
240/**
241 * pwm_omap_dmtimer_set_polarity() - Changes the polarity of the pwm dm timer.
242 * @chip: Pointer to PWM controller
243 * @pwm: Pointer to PWM channel
244 * @polarity: New pwm polarity to be set
245 */
246static void pwm_omap_dmtimer_set_polarity(struct pwm_chip *chip,
247 struct pwm_device *pwm,
248 enum pwm_polarity polarity)
249{
250 struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
251 bool enabled;
252
253 /* Disable the PWM before changing the polarity. */
254 enabled = pwm_omap_dmtimer_is_enabled(omap);
255 if (enabled)
256 omap->pdata->stop(omap->dm_timer);
257
258 omap->pdata->set_pwm(omap->dm_timer,
259 polarity == PWM_POLARITY_INVERSED,
260 true, OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE,
261 true);
262
263 if (enabled)
264 pwm_omap_dmtimer_start(omap);
265}
266
267/**
268 * pwm_omap_dmtimer_apply() - Changes the state of the pwm omap dm timer.
269 * @chip: Pointer to PWM controller
270 * @pwm: Pointer to PWM channel
271 * @state: New state to apply
272 *
273 * Return 0 if successfully changed the state else appropriate error.
274 */
275static int pwm_omap_dmtimer_apply(struct pwm_chip *chip,
276 struct pwm_device *pwm,
277 const struct pwm_state *state)
278{
279 struct pwm_omap_dmtimer_chip *omap = to_pwm_omap_dmtimer_chip(chip);
280 int ret = 0;
281
282 mutex_lock(&omap->mutex);
283
284 if (pwm_omap_dmtimer_is_enabled(omap) && !state->enabled) {
285 omap->pdata->stop(omap->dm_timer);
286 goto unlock_mutex;
287 }
288
289 if (pwm_omap_dmtimer_polarity(omap) != state->polarity)
290 pwm_omap_dmtimer_set_polarity(chip, pwm, state->polarity);
291
292 ret = pwm_omap_dmtimer_config(chip, pwm, state->duty_cycle,
293 state->period);
294 if (ret)
295 goto unlock_mutex;
296
297 if (!pwm_omap_dmtimer_is_enabled(omap) && state->enabled) {
298 omap->pdata->set_pwm(omap->dm_timer,
299 state->polarity == PWM_POLARITY_INVERSED,
300 true,
301 OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE,
302 true);
303 pwm_omap_dmtimer_start(omap);
304 }
305
306unlock_mutex:
307 mutex_unlock(&omap->mutex);
308
309 return ret;
310}
311
312static const struct pwm_ops pwm_omap_dmtimer_ops = {
313 .apply = pwm_omap_dmtimer_apply,
314 .owner = THIS_MODULE,
315};
316
317static int pwm_omap_dmtimer_probe(struct platform_device *pdev)
318{
319 struct device_node *np = pdev->dev.of_node;
320 struct dmtimer_platform_data *timer_pdata;
321 const struct omap_dm_timer_ops *pdata;
322 struct platform_device *timer_pdev;
323 struct pwm_omap_dmtimer_chip *omap;
324 struct omap_dm_timer *dm_timer;
325 struct device_node *timer;
326 int ret = 0;
327 u32 v;
328
329 timer = of_parse_phandle(np, "ti,timers", 0);
330 if (!timer)
331 return -ENODEV;
332
333 timer_pdev = of_find_device_by_node(timer);
334 if (!timer_pdev) {
335 dev_err(&pdev->dev, "Unable to find Timer pdev\n");
336 ret = -ENODEV;
337 goto err_find_timer_pdev;
338 }
339
340 timer_pdata = dev_get_platdata(&timer_pdev->dev);
341 if (!timer_pdata) {
342 dev_dbg(&pdev->dev,
343 "dmtimer pdata structure NULL, deferring probe\n");
344 ret = -EPROBE_DEFER;
345 goto err_platdata;
346 }
347
348 pdata = timer_pdata->timer_ops;
349
350 if (!pdata || !pdata->request_by_node ||
351 !pdata->free ||
352 !pdata->enable ||
353 !pdata->disable ||
354 !pdata->get_fclk ||
355 !pdata->start ||
356 !pdata->stop ||
357 !pdata->set_load ||
358 !pdata->set_match ||
359 !pdata->set_pwm ||
360 !pdata->get_pwm_status ||
361 !pdata->set_prescaler ||
362 !pdata->write_counter) {
363 dev_err(&pdev->dev, "Incomplete dmtimer pdata structure\n");
364 ret = -EINVAL;
365 goto err_platdata;
366 }
367
368 if (!of_get_property(timer, "ti,timer-pwm", NULL)) {
369 dev_err(&pdev->dev, "Missing ti,timer-pwm capability\n");
370 ret = -ENODEV;
371 goto err_timer_property;
372 }
373
374 dm_timer = pdata->request_by_node(timer);
375 if (!dm_timer) {
376 ret = -EPROBE_DEFER;
377 goto err_request_timer;
378 }
379
380 omap = devm_kzalloc(&pdev->dev, sizeof(*omap), GFP_KERNEL);
381 if (!omap) {
382 ret = -ENOMEM;
383 goto err_alloc_omap;
384 }
385
386 omap->pdata = pdata;
387 omap->dm_timer = dm_timer;
388 omap->dm_timer_pdev = timer_pdev;
389
390 /*
391 * Ensure that the timer is stopped before we allow PWM core to call
392 * pwm_enable.
393 */
394 if (pm_runtime_active(&omap->dm_timer_pdev->dev))
395 omap->pdata->stop(omap->dm_timer);
396
397 if (!of_property_read_u32(pdev->dev.of_node, "ti,prescaler", &v))
398 omap->pdata->set_prescaler(omap->dm_timer, v);
399
400 /* setup dmtimer clock source */
401 if (!of_property_read_u32(pdev->dev.of_node, "ti,clock-source", &v))
402 omap->pdata->set_source(omap->dm_timer, v);
403
404 omap->chip.dev = &pdev->dev;
405 omap->chip.ops = &pwm_omap_dmtimer_ops;
406 omap->chip.npwm = 1;
407
408 mutex_init(&omap->mutex);
409
410 ret = pwmchip_add(&omap->chip);
411 if (ret < 0) {
412 dev_err(&pdev->dev, "failed to register PWM\n");
413 goto err_pwmchip_add;
414 }
415
416 of_node_put(timer);
417
418 platform_set_drvdata(pdev, omap);
419
420 return 0;
421
422err_pwmchip_add:
423
424 /*
425 * *omap is allocated using devm_kzalloc,
426 * so no free necessary here
427 */
428err_alloc_omap:
429
430 pdata->free(dm_timer);
431err_request_timer:
432
433err_timer_property:
434err_platdata:
435
436 put_device(&timer_pdev->dev);
437err_find_timer_pdev:
438
439 of_node_put(timer);
440
441 return ret;
442}
443
444static int pwm_omap_dmtimer_remove(struct platform_device *pdev)
445{
446 struct pwm_omap_dmtimer_chip *omap = platform_get_drvdata(pdev);
447
448 pwmchip_remove(&omap->chip);
449
450 if (pm_runtime_active(&omap->dm_timer_pdev->dev))
451 omap->pdata->stop(omap->dm_timer);
452
453 omap->pdata->free(omap->dm_timer);
454
455 put_device(&omap->dm_timer_pdev->dev);
456
457 mutex_destroy(&omap->mutex);
458
459 return 0;
460}
461
462static const struct of_device_id pwm_omap_dmtimer_of_match[] = {
463 {.compatible = "ti,omap-dmtimer-pwm"},
464 {}
465};
466MODULE_DEVICE_TABLE(of, pwm_omap_dmtimer_of_match);
467
468static struct platform_driver pwm_omap_dmtimer_driver = {
469 .driver = {
470 .name = "omap-dmtimer-pwm",
471 .of_match_table = of_match_ptr(pwm_omap_dmtimer_of_match),
472 },
473 .probe = pwm_omap_dmtimer_probe,
474 .remove = pwm_omap_dmtimer_remove,
475};
476module_platform_driver(pwm_omap_dmtimer_driver);
477
478MODULE_AUTHOR("Grant Erickson <marathon96@gmail.com>");
479MODULE_AUTHOR("NeilBrown <neilb@suse.de>");
480MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
481MODULE_LICENSE("GPL v2");
482MODULE_DESCRIPTION("OMAP PWM Driver using Dual-mode Timers");