1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Support routines for initializing a PCI subsystem
   4 *
   5 * Extruded from code written by
   6 *      Dave Rusling (david.rusling@reo.mts.dec.com)
   7 *      David Mosberger (davidm@cs.arizona.edu)
   8 *	David Miller (davem@redhat.com)
   9 *
 
 
 
 
  10 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
  11 *	     PCI-PCI bridges cleanup, sorted resource allocation.
  12 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
  13 *	     Converted to allocation in 3 passes, which gives
  14 *	     tighter packing. Prefetchable range support.
  15 */
  16
  17#include <linux/init.h>
  18#include <linux/kernel.h>
  19#include <linux/module.h>
  20#include <linux/pci.h>
  21#include <linux/errno.h>
  22#include <linux/ioport.h>
  23#include <linux/cache.h>
  24#include <linux/slab.h>
  25#include <linux/acpi.h>
  26#include "pci.h"
  27
  28unsigned int pci_flags;
  29
  30struct pci_dev_resource {
  31	struct list_head list;
  32	struct resource *res;
  33	struct pci_dev *dev;
  34	resource_size_t start;
  35	resource_size_t end;
  36	resource_size_t add_size;
  37	resource_size_t min_align;
  38	unsigned long flags;
  39};
  40
  41static void free_list(struct list_head *head)
  42{
  43	struct pci_dev_resource *dev_res, *tmp;
  44
  45	list_for_each_entry_safe(dev_res, tmp, head, list) {
  46		list_del(&dev_res->list);
  47		kfree(dev_res);
  48	}
  49}
  50
  51/**
  52 * add_to_list() - add a new resource tracker to the list
  53 * @head:	Head of the list
  54 * @dev:	device corresponding to which the resource
  55 *		belongs
  56 * @res:	The resource to be tracked
  57 * @add_size:	additional size to be optionally added
  58 *              to the resource
  59 */
  60static int add_to_list(struct list_head *head,
  61		 struct pci_dev *dev, struct resource *res,
  62		 resource_size_t add_size, resource_size_t min_align)
  63{
  64	struct pci_dev_resource *tmp;
  65
  66	tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
  67	if (!tmp)
 
  68		return -ENOMEM;
 
  69
  70	tmp->res = res;
  71	tmp->dev = dev;
  72	tmp->start = res->start;
  73	tmp->end = res->end;
  74	tmp->flags = res->flags;
  75	tmp->add_size = add_size;
  76	tmp->min_align = min_align;
  77
  78	list_add(&tmp->list, head);
  79
  80	return 0;
  81}
  82
  83static void remove_from_list(struct list_head *head,
  84				 struct resource *res)
  85{
  86	struct pci_dev_resource *dev_res, *tmp;
  87
  88	list_for_each_entry_safe(dev_res, tmp, head, list) {
  89		if (dev_res->res == res) {
  90			list_del(&dev_res->list);
  91			kfree(dev_res);
  92			break;
  93		}
  94	}
  95}
  96
  97static struct pci_dev_resource *res_to_dev_res(struct list_head *head,
  98					       struct resource *res)
  99{
 100	struct pci_dev_resource *dev_res;
 101
 102	list_for_each_entry(dev_res, head, list) {
 103		if (dev_res->res == res)
 
 
 
 
 
 
 
 
 104			return dev_res;
 
 105	}
 106
 107	return NULL;
 108}
 109
 110static resource_size_t get_res_add_size(struct list_head *head,
 111					struct resource *res)
 112{
 113	struct pci_dev_resource *dev_res;
 114
 115	dev_res = res_to_dev_res(head, res);
 116	return dev_res ? dev_res->add_size : 0;
 117}
 118
 119static resource_size_t get_res_add_align(struct list_head *head,
 120					 struct resource *res)
 121{
 122	struct pci_dev_resource *dev_res;
 123
 124	dev_res = res_to_dev_res(head, res);
 125	return dev_res ? dev_res->min_align : 0;
 126}
 127
 128
 129/* Sort resources by alignment */
 130static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
 131{
 132	int i;
 133
 134	for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 135		struct resource *r;
 136		struct pci_dev_resource *dev_res, *tmp;
 137		resource_size_t r_align;
 138		struct list_head *n;
 139
 140		r = &dev->resource[i];
 141
 142		if (r->flags & IORESOURCE_PCI_FIXED)
 143			continue;
 144
 145		if (!(r->flags) || r->parent)
 146			continue;
 147
 148		r_align = pci_resource_alignment(dev, r);
 149		if (!r_align) {
 150			pci_warn(dev, "BAR %d: %pR has bogus alignment\n",
 151				 i, r);
 152			continue;
 153		}
 154
 155		tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
 156		if (!tmp)
 157			panic("pdev_sort_resources(): kmalloc() failed!\n");
 158		tmp->res = r;
 159		tmp->dev = dev;
 160
 161		/* fallback is smallest one or list is empty*/
 162		n = head;
 163		list_for_each_entry(dev_res, head, list) {
 164			resource_size_t align;
 165
 166			align = pci_resource_alignment(dev_res->dev,
 167							 dev_res->res);
 168
 169			if (r_align > align) {
 170				n = &dev_res->list;
 171				break;
 172			}
 173		}
 174		/* Insert it just before n*/
 175		list_add_tail(&tmp->list, n);
 176	}
 177}
 178
 179static void __dev_sort_resources(struct pci_dev *dev,
 180				 struct list_head *head)
 181{
 182	u16 class = dev->class >> 8;
 183
 184	/* Don't touch classless devices or host bridges or ioapics.  */
 185	if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
 186		return;
 187
 188	/* Don't touch ioapic devices already enabled by firmware */
 189	if (class == PCI_CLASS_SYSTEM_PIC) {
 190		u16 command;
 191		pci_read_config_word(dev, PCI_COMMAND, &command);
 192		if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
 193			return;
 194	}
 195
 196	pdev_sort_resources(dev, head);
 197}
 198
 199static inline void reset_resource(struct resource *res)
 200{
 201	res->start = 0;
 202	res->end = 0;
 203	res->flags = 0;
 204}
 205
 206/**
 207 * reassign_resources_sorted() - satisfy any additional resource requests
 208 *
 209 * @realloc_head : head of the list tracking requests requiring additional
 210 *             resources
 211 * @head     : head of the list tracking requests with allocated
 212 *             resources
 213 *
 214 * Walk through each element of the realloc_head and try to procure
 215 * additional resources for the element, provided the element
 216 * is in the head list.
 217 */
 218static void reassign_resources_sorted(struct list_head *realloc_head,
 219		struct list_head *head)
 220{
 221	struct resource *res;
 222	struct pci_dev_resource *add_res, *tmp;
 223	struct pci_dev_resource *dev_res;
 224	resource_size_t add_size, align;
 225	int idx;
 226
 227	list_for_each_entry_safe(add_res, tmp, realloc_head, list) {
 228		bool found_match = false;
 229
 230		res = add_res->res;
 231		/* skip resource that has been reset */
 232		if (!res->flags)
 233			goto out;
 234
 235		/* skip this resource if not found in head list */
 236		list_for_each_entry(dev_res, head, list) {
 237			if (dev_res->res == res) {
 238				found_match = true;
 239				break;
 240			}
 241		}
 242		if (!found_match)/* just skip */
 243			continue;
 244
 245		idx = res - &add_res->dev->resource[0];
 246		add_size = add_res->add_size;
 247		align = add_res->min_align;
 248		if (!resource_size(res)) {
 249			res->start = align;
 250			res->end = res->start + add_size - 1;
 251			if (pci_assign_resource(add_res->dev, idx))
 252				reset_resource(res);
 253		} else {
 254			res->flags |= add_res->flags &
 255				 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
 256			if (pci_reassign_resource(add_res->dev, idx,
 257						  add_size, align))
 258				pci_printk(KERN_DEBUG, add_res->dev,
 259					   "failed to add %llx res[%d]=%pR\n",
 260					   (unsigned long long)add_size,
 261					   idx, res);
 262		}
 263out:
 264		list_del(&add_res->list);
 265		kfree(add_res);
 266	}
 267}
 268
 269/**
 270 * assign_requested_resources_sorted() - satisfy resource requests
 271 *
 272 * @head : head of the list tracking requests for resources
 273 * @fail_head : head of the list tracking requests that could
 274 *		not be allocated
 275 *
 276 * Satisfy resource requests of each element in the list. Add
 277 * requests that could not satisfied to the failed_list.
 278 */
 279static void assign_requested_resources_sorted(struct list_head *head,
 280				 struct list_head *fail_head)
 281{
 282	struct resource *res;
 283	struct pci_dev_resource *dev_res;
 284	int idx;
 285
 286	list_for_each_entry(dev_res, head, list) {
 287		res = dev_res->res;
 288		idx = res - &dev_res->dev->resource[0];
 289		if (resource_size(res) &&
 290		    pci_assign_resource(dev_res->dev, idx)) {
 291			if (fail_head) {
 292				/*
 293				 * if the failed res is for ROM BAR, and it will
 294				 * be enabled later, don't add it to the list
 295				 */
 296				if (!((idx == PCI_ROM_RESOURCE) &&
 297				      (!(res->flags & IORESOURCE_ROM_ENABLE))))
 298					add_to_list(fail_head,
 299						    dev_res->dev, res,
 300						    0 /* don't care */,
 301						    0 /* don't care */);
 302			}
 303			reset_resource(res);
 304		}
 305	}
 306}
 307
 308static unsigned long pci_fail_res_type_mask(struct list_head *fail_head)
 309{
 310	struct pci_dev_resource *fail_res;
 311	unsigned long mask = 0;
 312
 313	/* check failed type */
 314	list_for_each_entry(fail_res, fail_head, list)
 315		mask |= fail_res->flags;
 316
 317	/*
 318	 * one pref failed resource will set IORESOURCE_MEM,
 319	 * as we can allocate pref in non-pref range.
 320	 * Will release all assigned non-pref sibling resources
 321	 * according to that bit.
 322	 */
 323	return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
 324}
 325
 326static bool pci_need_to_release(unsigned long mask, struct resource *res)
 327{
 328	if (res->flags & IORESOURCE_IO)
 329		return !!(mask & IORESOURCE_IO);
 330
 331	/* check pref at first */
 332	if (res->flags & IORESOURCE_PREFETCH) {
 333		if (mask & IORESOURCE_PREFETCH)
 334			return true;
 335		/* count pref if its parent is non-pref */
 336		else if ((mask & IORESOURCE_MEM) &&
 337			 !(res->parent->flags & IORESOURCE_PREFETCH))
 338			return true;
 339		else
 340			return false;
 341	}
 342
 343	if (res->flags & IORESOURCE_MEM)
 344		return !!(mask & IORESOURCE_MEM);
 345
 346	return false;	/* should not get here */
 347}
 348
 349static void __assign_resources_sorted(struct list_head *head,
 350				 struct list_head *realloc_head,
 351				 struct list_head *fail_head)
 352{
 353	/*
 354	 * Should not assign requested resources at first.
 355	 *   they could be adjacent, so later reassign can not reallocate
 356	 *   them one by one in parent resource window.
 357	 * Try to assign requested + add_size at beginning
 358	 *  if could do that, could get out early.
 359	 *  if could not do that, we still try to assign requested at first,
 360	 *    then try to reassign add_size for some resources.
 361	 *
 362	 * Separate three resource type checking if we need to release
 363	 * assigned resource after requested + add_size try.
 364	 *	1. if there is io port assign fail, will release assigned
 365	 *	   io port.
 366	 *	2. if there is pref mmio assign fail, release assigned
 367	 *	   pref mmio.
 368	 *	   if assigned pref mmio's parent is non-pref mmio and there
 369	 *	   is non-pref mmio assign fail, will release that assigned
 370	 *	   pref mmio.
 371	 *	3. if there is non-pref mmio assign fail or pref mmio
 372	 *	   assigned fail, will release assigned non-pref mmio.
 373	 */
 374	LIST_HEAD(save_head);
 375	LIST_HEAD(local_fail_head);
 376	struct pci_dev_resource *save_res;
 377	struct pci_dev_resource *dev_res, *tmp_res, *dev_res2;
 378	unsigned long fail_type;
 379	resource_size_t add_align, align;
 380
 381	/* Check if optional add_size is there */
 382	if (!realloc_head || list_empty(realloc_head))
 383		goto requested_and_reassign;
 384
 385	/* Save original start, end, flags etc at first */
 386	list_for_each_entry(dev_res, head, list) {
 387		if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) {
 388			free_list(&save_head);
 389			goto requested_and_reassign;
 390		}
 391	}
 392
 393	/* Update res in head list with add_size in realloc_head list */
 394	list_for_each_entry_safe(dev_res, tmp_res, head, list) {
 395		dev_res->res->end += get_res_add_size(realloc_head,
 396							dev_res->res);
 397
 398		/*
 399		 * There are two kinds of additional resources in the list:
 400		 * 1. bridge resource  -- IORESOURCE_STARTALIGN
 401		 * 2. SR-IOV resource   -- IORESOURCE_SIZEALIGN
 402		 * Here just fix the additional alignment for bridge
 403		 */
 404		if (!(dev_res->res->flags & IORESOURCE_STARTALIGN))
 405			continue;
 406
 407		add_align = get_res_add_align(realloc_head, dev_res->res);
 408
 409		/*
 410		 * The "head" list is sorted by the alignment to make sure
 411		 * resources with bigger alignment will be assigned first.
 412		 * After we change the alignment of a dev_res in "head" list,
 413		 * we need to reorder the list by alignment to make it
 414		 * consistent.
 415		 */
 416		if (add_align > dev_res->res->start) {
 417			resource_size_t r_size = resource_size(dev_res->res);
 418
 419			dev_res->res->start = add_align;
 420			dev_res->res->end = add_align + r_size - 1;
 421
 422			list_for_each_entry(dev_res2, head, list) {
 423				align = pci_resource_alignment(dev_res2->dev,
 424							       dev_res2->res);
 425				if (add_align > align) {
 426					list_move_tail(&dev_res->list,
 427						       &dev_res2->list);
 428					break;
 429				}
 430			}
 431		}
 432
 433	}
 434
 435	/* Try updated head list with add_size added */
 436	assign_requested_resources_sorted(head, &local_fail_head);
 437
 438	/* all assigned with add_size ? */
 439	if (list_empty(&local_fail_head)) {
 440		/* Remove head list from realloc_head list */
 441		list_for_each_entry(dev_res, head, list)
 442			remove_from_list(realloc_head, dev_res->res);
 443		free_list(&save_head);
 444		free_list(head);
 445		return;
 446	}
 447
 448	/* check failed type */
 449	fail_type = pci_fail_res_type_mask(&local_fail_head);
 450	/* remove not need to be released assigned res from head list etc */
 451	list_for_each_entry_safe(dev_res, tmp_res, head, list)
 452		if (dev_res->res->parent &&
 453		    !pci_need_to_release(fail_type, dev_res->res)) {
 454			/* remove it from realloc_head list */
 455			remove_from_list(realloc_head, dev_res->res);
 456			remove_from_list(&save_head, dev_res->res);
 457			list_del(&dev_res->list);
 458			kfree(dev_res);
 459		}
 460
 461	free_list(&local_fail_head);
 462	/* Release assigned resource */
 463	list_for_each_entry(dev_res, head, list)
 464		if (dev_res->res->parent)
 465			release_resource(dev_res->res);
 466	/* Restore start/end/flags from saved list */
 467	list_for_each_entry(save_res, &save_head, list) {
 468		struct resource *res = save_res->res;
 469
 470		res->start = save_res->start;
 471		res->end = save_res->end;
 472		res->flags = save_res->flags;
 473	}
 474	free_list(&save_head);
 475
 476requested_and_reassign:
 477	/* Satisfy the must-have resource requests */
 478	assign_requested_resources_sorted(head, fail_head);
 479
 480	/* Try to satisfy any additional optional resource
 481		requests */
 482	if (realloc_head)
 483		reassign_resources_sorted(realloc_head, head);
 484	free_list(head);
 485}
 486
 487static void pdev_assign_resources_sorted(struct pci_dev *dev,
 488				 struct list_head *add_head,
 489				 struct list_head *fail_head)
 490{
 491	LIST_HEAD(head);
 492
 493	__dev_sort_resources(dev, &head);
 494	__assign_resources_sorted(&head, add_head, fail_head);
 495
 496}
 497
 498static void pbus_assign_resources_sorted(const struct pci_bus *bus,
 499					 struct list_head *realloc_head,
 500					 struct list_head *fail_head)
 501{
 502	struct pci_dev *dev;
 503	LIST_HEAD(head);
 504
 505	list_for_each_entry(dev, &bus->devices, bus_list)
 506		__dev_sort_resources(dev, &head);
 507
 508	__assign_resources_sorted(&head, realloc_head, fail_head);
 509}
 510
 511void pci_setup_cardbus(struct pci_bus *bus)
 512{
 513	struct pci_dev *bridge = bus->self;
 514	struct resource *res;
 515	struct pci_bus_region region;
 516
 517	pci_info(bridge, "CardBus bridge to %pR\n",
 518		 &bus->busn_res);
 519
 520	res = bus->resource[0];
 521	pcibios_resource_to_bus(bridge->bus, &region, res);
 522	if (res->flags & IORESOURCE_IO) {
 523		/*
 524		 * The IO resource is allocated a range twice as large as it
 525		 * would normally need.  This allows us to set both IO regs.
 526		 */
 527		pci_info(bridge, "  bridge window %pR\n", res);
 528		pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
 529					region.start);
 530		pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
 531					region.end);
 532	}
 533
 534	res = bus->resource[1];
 535	pcibios_resource_to_bus(bridge->bus, &region, res);
 536	if (res->flags & IORESOURCE_IO) {
 537		pci_info(bridge, "  bridge window %pR\n", res);
 538		pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
 539					region.start);
 540		pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
 541					region.end);
 542	}
 543
 544	res = bus->resource[2];
 545	pcibios_resource_to_bus(bridge->bus, &region, res);
 546	if (res->flags & IORESOURCE_MEM) {
 547		pci_info(bridge, "  bridge window %pR\n", res);
 548		pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
 549					region.start);
 550		pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
 551					region.end);
 552	}
 553
 554	res = bus->resource[3];
 555	pcibios_resource_to_bus(bridge->bus, &region, res);
 556	if (res->flags & IORESOURCE_MEM) {
 557		pci_info(bridge, "  bridge window %pR\n", res);
 558		pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
 559					region.start);
 560		pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
 561					region.end);
 562	}
 563}
 564EXPORT_SYMBOL(pci_setup_cardbus);
 565
 566/* Initialize bridges with base/limit values we have collected.
 567   PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
 568   requires that if there is no I/O ports or memory behind the
 569   bridge, corresponding range must be turned off by writing base
 570   value greater than limit to the bridge's base/limit registers.
 571
 572   Note: care must be taken when updating I/O base/limit registers
 573   of bridges which support 32-bit I/O. This update requires two
 574   config space writes, so it's quite possible that an I/O window of
 575   the bridge will have some undesirable address (e.g. 0) after the
 576   first write. Ditto 64-bit prefetchable MMIO.  */
 577static void pci_setup_bridge_io(struct pci_dev *bridge)
 578{
 579	struct resource *res;
 580	struct pci_bus_region region;
 581	unsigned long io_mask;
 582	u8 io_base_lo, io_limit_lo;
 583	u16 l;
 584	u32 io_upper16;
 585
 586	io_mask = PCI_IO_RANGE_MASK;
 587	if (bridge->io_window_1k)
 588		io_mask = PCI_IO_1K_RANGE_MASK;
 589
 590	/* Set up the top and bottom of the PCI I/O segment for this bus. */
 591	res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
 592	pcibios_resource_to_bus(bridge->bus, &region, res);
 593	if (res->flags & IORESOURCE_IO) {
 594		pci_read_config_word(bridge, PCI_IO_BASE, &l);
 595		io_base_lo = (region.start >> 8) & io_mask;
 596		io_limit_lo = (region.end >> 8) & io_mask;
 597		l = ((u16) io_limit_lo << 8) | io_base_lo;
 598		/* Set up upper 16 bits of I/O base/limit. */
 599		io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
 600		pci_info(bridge, "  bridge window %pR\n", res);
 601	} else {
 602		/* Clear upper 16 bits of I/O base/limit. */
 603		io_upper16 = 0;
 604		l = 0x00f0;
 605	}
 606	/* Temporarily disable the I/O range before updating PCI_IO_BASE. */
 607	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
 608	/* Update lower 16 bits of I/O base/limit. */
 609	pci_write_config_word(bridge, PCI_IO_BASE, l);
 610	/* Update upper 16 bits of I/O base/limit. */
 611	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
 612}
 613
 614static void pci_setup_bridge_mmio(struct pci_dev *bridge)
 615{
 616	struct resource *res;
 617	struct pci_bus_region region;
 618	u32 l;
 619
 620	/* Set up the top and bottom of the PCI Memory segment for this bus. */
 621	res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
 622	pcibios_resource_to_bus(bridge->bus, &region, res);
 623	if (res->flags & IORESOURCE_MEM) {
 624		l = (region.start >> 16) & 0xfff0;
 625		l |= region.end & 0xfff00000;
 626		pci_info(bridge, "  bridge window %pR\n", res);
 627	} else {
 628		l = 0x0000fff0;
 629	}
 630	pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
 631}
 632
 633static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
 634{
 635	struct resource *res;
 636	struct pci_bus_region region;
 637	u32 l, bu, lu;
 638
 639	/* Clear out the upper 32 bits of PREF limit.
 640	   If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
 641	   disables PREF range, which is ok. */
 642	pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
 643
 644	/* Set up PREF base/limit. */
 645	bu = lu = 0;
 646	res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
 647	pcibios_resource_to_bus(bridge->bus, &region, res);
 648	if (res->flags & IORESOURCE_PREFETCH) {
 649		l = (region.start >> 16) & 0xfff0;
 650		l |= region.end & 0xfff00000;
 651		if (res->flags & IORESOURCE_MEM_64) {
 652			bu = upper_32_bits(region.start);
 653			lu = upper_32_bits(region.end);
 654		}
 655		pci_info(bridge, "  bridge window %pR\n", res);
 656	} else {
 657		l = 0x0000fff0;
 658	}
 659	pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
 660
 661	/* Set the upper 32 bits of PREF base & limit. */
 662	pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
 663	pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
 664}
 665
 666static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
 667{
 668	struct pci_dev *bridge = bus->self;
 669
 670	pci_info(bridge, "PCI bridge to %pR\n",
 671		 &bus->busn_res);
 672
 673	if (type & IORESOURCE_IO)
 674		pci_setup_bridge_io(bridge);
 675
 676	if (type & IORESOURCE_MEM)
 677		pci_setup_bridge_mmio(bridge);
 678
 679	if (type & IORESOURCE_PREFETCH)
 680		pci_setup_bridge_mmio_pref(bridge);
 681
 682	pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
 683}
 684
 685void __weak pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
 686{
 687}
 688
 689void pci_setup_bridge(struct pci_bus *bus)
 690{
 691	unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
 692				  IORESOURCE_PREFETCH;
 693
 694	pcibios_setup_bridge(bus, type);
 695	__pci_setup_bridge(bus, type);
 696}
 697
 698
 699int pci_claim_bridge_resource(struct pci_dev *bridge, int i)
 700{
 701	if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END)
 702		return 0;
 703
 704	if (pci_claim_resource(bridge, i) == 0)
 705		return 0;	/* claimed the window */
 706
 707	if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)
 708		return 0;
 709
 710	if (!pci_bus_clip_resource(bridge, i))
 711		return -EINVAL;	/* clipping didn't change anything */
 712
 713	switch (i - PCI_BRIDGE_RESOURCES) {
 714	case 0:
 715		pci_setup_bridge_io(bridge);
 716		break;
 717	case 1:
 718		pci_setup_bridge_mmio(bridge);
 719		break;
 720	case 2:
 721		pci_setup_bridge_mmio_pref(bridge);
 722		break;
 723	default:
 724		return -EINVAL;
 725	}
 726
 727	if (pci_claim_resource(bridge, i) == 0)
 728		return 0;	/* claimed a smaller window */
 729
 730	return -EINVAL;
 731}
 732
 733/* Check whether the bridge supports optional I/O and
 734   prefetchable memory ranges. If not, the respective
 735   base/limit registers must be read-only and read as 0. */
 736static void pci_bridge_check_ranges(struct pci_bus *bus)
 737{
 738	u16 io;
 739	u32 pmem;
 740	struct pci_dev *bridge = bus->self;
 741	struct resource *b_res;
 742
 743	b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
 744	b_res[1].flags |= IORESOURCE_MEM;
 745
 746	pci_read_config_word(bridge, PCI_IO_BASE, &io);
 747	if (!io) {
 748		pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
 749		pci_read_config_word(bridge, PCI_IO_BASE, &io);
 750		pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
 751	}
 752	if (io)
 753		b_res[0].flags |= IORESOURCE_IO;
 754
 755	/*  DECchip 21050 pass 2 errata: the bridge may miss an address
 756	    disconnect boundary by one PCI data phase.
 757	    Workaround: do not use prefetching on this device. */
 758	if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
 759		return;
 760
 761	pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
 762	if (!pmem) {
 763		pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
 764					       0xffe0fff0);
 765		pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
 766		pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
 767	}
 768	if (pmem) {
 769		b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
 770		if ((pmem & PCI_PREF_RANGE_TYPE_MASK) ==
 771		    PCI_PREF_RANGE_TYPE_64) {
 772			b_res[2].flags |= IORESOURCE_MEM_64;
 773			b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
 774		}
 775	}
 776
 777	/* double check if bridge does support 64 bit pref */
 778	if (b_res[2].flags & IORESOURCE_MEM_64) {
 779		u32 mem_base_hi, tmp;
 780		pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
 781					 &mem_base_hi);
 782		pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
 783					       0xffffffff);
 784		pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
 785		if (!tmp)
 786			b_res[2].flags &= ~IORESOURCE_MEM_64;
 787		pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
 788				       mem_base_hi);
 789	}
 790}
 791
 792/* Helper function for sizing routines: find first available
 793   bus resource of a given type. Note: we intentionally skip
 794   the bus resources which have already been assigned (that is,
 795   have non-NULL parent resource). */
 796static struct resource *find_free_bus_resource(struct pci_bus *bus,
 797			 unsigned long type_mask, unsigned long type)
 798{
 799	int i;
 800	struct resource *r;
 801
 802	pci_bus_for_each_resource(bus, r, i) {
 803		if (r == &ioport_resource || r == &iomem_resource)
 804			continue;
 805		if (r && (r->flags & type_mask) == type && !r->parent)
 806			return r;
 807	}
 808	return NULL;
 809}
 810
 811static resource_size_t calculate_iosize(resource_size_t size,
 812		resource_size_t min_size,
 813		resource_size_t size1,
 814		resource_size_t old_size,
 815		resource_size_t align)
 816{
 817	if (size < min_size)
 818		size = min_size;
 819	if (old_size == 1)
 820		old_size = 0;
 821	/* To be fixed in 2.5: we should have sort of HAVE_ISA
 822	   flag in the struct pci_bus. */
 823#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
 824	size = (size & 0xff) + ((size & ~0xffUL) << 2);
 825#endif
 826	size = ALIGN(size + size1, align);
 827	if (size < old_size)
 828		size = old_size;
 829	return size;
 830}
 831
 832static resource_size_t calculate_memsize(resource_size_t size,
 833		resource_size_t min_size,
 834		resource_size_t size1,
 835		resource_size_t old_size,
 836		resource_size_t align)
 837{
 838	if (size < min_size)
 839		size = min_size;
 840	if (old_size == 1)
 841		old_size = 0;
 842	if (size < old_size)
 843		size = old_size;
 844	size = ALIGN(size + size1, align);
 845	return size;
 846}
 847
 848resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus,
 849						unsigned long type)
 850{
 851	return 1;
 852}
 853
 854#define PCI_P2P_DEFAULT_MEM_ALIGN	0x100000	/* 1MiB */
 855#define PCI_P2P_DEFAULT_IO_ALIGN	0x1000		/* 4KiB */
 856#define PCI_P2P_DEFAULT_IO_ALIGN_1K	0x400		/* 1KiB */
 857
 858static resource_size_t window_alignment(struct pci_bus *bus,
 859					unsigned long type)
 860{
 861	resource_size_t align = 1, arch_align;
 862
 863	if (type & IORESOURCE_MEM)
 864		align = PCI_P2P_DEFAULT_MEM_ALIGN;
 865	else if (type & IORESOURCE_IO) {
 866		/*
 867		 * Per spec, I/O windows are 4K-aligned, but some
 868		 * bridges have an extension to support 1K alignment.
 869		 */
 870		if (bus->self->io_window_1k)
 871			align = PCI_P2P_DEFAULT_IO_ALIGN_1K;
 872		else
 873			align = PCI_P2P_DEFAULT_IO_ALIGN;
 874	}
 875
 876	arch_align = pcibios_window_alignment(bus, type);
 877	return max(align, arch_align);
 878}
 879
 880/**
 881 * pbus_size_io() - size the io window of a given bus
 882 *
 883 * @bus : the bus
 884 * @min_size : the minimum io window that must to be allocated
 885 * @add_size : additional optional io window
 886 * @realloc_head : track the additional io window on this list
 887 *
 888 * Sizing the IO windows of the PCI-PCI bridge is trivial,
 889 * since these windows have 1K or 4K granularity and the IO ranges
 890 * of non-bridge PCI devices are limited to 256 bytes.
 891 * We must be careful with the ISA aliasing though.
 892 */
 893static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
 894		resource_size_t add_size, struct list_head *realloc_head)
 895{
 896	struct pci_dev *dev;
 897	struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO,
 898							IORESOURCE_IO);
 899	resource_size_t size = 0, size0 = 0, size1 = 0;
 900	resource_size_t children_add_size = 0;
 901	resource_size_t min_align, align;
 902
 903	if (!b_res)
 904		return;
 905
 906	min_align = window_alignment(bus, IORESOURCE_IO);
 907	list_for_each_entry(dev, &bus->devices, bus_list) {
 908		int i;
 909
 910		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
 911			struct resource *r = &dev->resource[i];
 912			unsigned long r_size;
 913
 914			if (r->parent || !(r->flags & IORESOURCE_IO))
 915				continue;
 916			r_size = resource_size(r);
 917
 918			if (r_size < 0x400)
 919				/* Might be re-aligned for ISA */
 920				size += r_size;
 921			else
 922				size1 += r_size;
 923
 924			align = pci_resource_alignment(dev, r);
 925			if (align > min_align)
 926				min_align = align;
 927
 928			if (realloc_head)
 929				children_add_size += get_res_add_size(realloc_head, r);
 930		}
 931	}
 932
 933	size0 = calculate_iosize(size, min_size, size1,
 934			resource_size(b_res), min_align);
 935	if (children_add_size > add_size)
 936		add_size = children_add_size;
 937	size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
 938		calculate_iosize(size, min_size, add_size + size1,
 939			resource_size(b_res), min_align);
 940	if (!size0 && !size1) {
 941		if (b_res->start || b_res->end)
 942			pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
 943				 b_res, &bus->busn_res);
 944		b_res->flags = 0;
 945		return;
 946	}
 947
 948	b_res->start = min_align;
 949	b_res->end = b_res->start + size0 - 1;
 950	b_res->flags |= IORESOURCE_STARTALIGN;
 951	if (size1 > size0 && realloc_head) {
 952		add_to_list(realloc_head, bus->self, b_res, size1-size0,
 953			    min_align);
 954		pci_printk(KERN_DEBUG, bus->self, "bridge window %pR to %pR add_size %llx\n",
 955			   b_res, &bus->busn_res,
 956			   (unsigned long long)size1-size0);
 957	}
 958}
 959
 960static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
 961						  int max_order)
 962{
 963	resource_size_t align = 0;
 964	resource_size_t min_align = 0;
 965	int order;
 966
 967	for (order = 0; order <= max_order; order++) {
 968		resource_size_t align1 = 1;
 969
 970		align1 <<= (order + 20);
 971
 972		if (!align)
 973			min_align = align1;
 974		else if (ALIGN(align + min_align, min_align) < align1)
 975			min_align = align1 >> 1;
 976		align += aligns[order];
 977	}
 978
 979	return min_align;
 980}
 981
 982/**
 983 * pbus_size_mem() - size the memory window of a given bus
 984 *
 985 * @bus : the bus
 986 * @mask: mask the resource flag, then compare it with type
 987 * @type: the type of free resource from bridge
 988 * @type2: second match type
 989 * @type3: third match type
 990 * @min_size : the minimum memory window that must to be allocated
 991 * @add_size : additional optional memory window
 992 * @realloc_head : track the additional memory window on this list
 993 *
 994 * Calculate the size of the bus and minimal alignment which
 995 * guarantees that all child resources fit in this size.
 996 *
 997 * Returns -ENOSPC if there's no available bus resource of the desired type.
 998 * Otherwise, sets the bus resource start/end to indicate the required
 999 * size, adds things to realloc_head (if supplied), and returns 0.
1000 */
1001static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
1002			 unsigned long type, unsigned long type2,
1003			 unsigned long type3,
1004			 resource_size_t min_size, resource_size_t add_size,
1005			 struct list_head *realloc_head)
1006{
1007	struct pci_dev *dev;
1008	resource_size_t min_align, align, size, size0, size1;
1009	resource_size_t aligns[18];	/* Alignments from 1Mb to 128Gb */
1010	int order, max_order;
1011	struct resource *b_res = find_free_bus_resource(bus,
1012					mask | IORESOURCE_PREFETCH, type);
1013	resource_size_t children_add_size = 0;
1014	resource_size_t children_add_align = 0;
1015	resource_size_t add_align = 0;
1016
1017	if (!b_res)
1018		return -ENOSPC;
1019
1020	memset(aligns, 0, sizeof(aligns));
1021	max_order = 0;
1022	size = 0;
1023
1024	list_for_each_entry(dev, &bus->devices, bus_list) {
1025		int i;
1026
1027		for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1028			struct resource *r = &dev->resource[i];
1029			resource_size_t r_size;
1030
1031			if (r->parent || (r->flags & IORESOURCE_PCI_FIXED) ||
1032			    ((r->flags & mask) != type &&
1033			     (r->flags & mask) != type2 &&
1034			     (r->flags & mask) != type3))
1035				continue;
1036			r_size = resource_size(r);
1037#ifdef CONFIG_PCI_IOV
1038			/* put SRIOV requested res to the optional list */
1039			if (realloc_head && i >= PCI_IOV_RESOURCES &&
1040					i <= PCI_IOV_RESOURCE_END) {
1041				add_align = max(pci_resource_alignment(dev, r), add_align);
1042				r->end = r->start - 1;
1043				add_to_list(realloc_head, dev, r, r_size, 0/* don't care */);
1044				children_add_size += r_size;
1045				continue;
1046			}
1047#endif
1048			/*
1049			 * aligns[0] is for 1MB (since bridge memory
1050			 * windows are always at least 1MB aligned), so
1051			 * keep "order" from being negative for smaller
1052			 * resources.
1053			 */
1054			align = pci_resource_alignment(dev, r);
1055			order = __ffs(align) - 20;
1056			if (order < 0)
1057				order = 0;
1058			if (order >= ARRAY_SIZE(aligns)) {
1059				pci_warn(dev, "disabling BAR %d: %pR (bad alignment %#llx)\n",
1060					 i, r, (unsigned long long) align);
1061				r->flags = 0;
1062				continue;
1063			}
1064			size += max(r_size, align);
1065			/* Exclude ranges with size > align from
1066			   calculation of the alignment. */
1067			if (r_size <= align)
1068				aligns[order] += align;
1069			if (order > max_order)
1070				max_order = order;
1071
1072			if (realloc_head) {
1073				children_add_size += get_res_add_size(realloc_head, r);
1074				children_add_align = get_res_add_align(realloc_head, r);
1075				add_align = max(add_align, children_add_align);
1076			}
1077		}
1078	}
1079
1080	min_align = calculate_mem_align(aligns, max_order);
1081	min_align = max(min_align, window_alignment(bus, b_res->flags));
1082	size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align);
1083	add_align = max(min_align, add_align);
1084	if (children_add_size > add_size)
1085		add_size = children_add_size;
1086	size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
1087		calculate_memsize(size, min_size, add_size,
1088				resource_size(b_res), add_align);
1089	if (!size0 && !size1) {
1090		if (b_res->start || b_res->end)
1091			pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
1092				 b_res, &bus->busn_res);
1093		b_res->flags = 0;
1094		return 0;
1095	}
1096	b_res->start = min_align;
1097	b_res->end = size0 + min_align - 1;
1098	b_res->flags |= IORESOURCE_STARTALIGN;
1099	if (size1 > size0 && realloc_head) {
1100		add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align);
1101		pci_printk(KERN_DEBUG, bus->self, "bridge window %pR to %pR add_size %llx add_align %llx\n",
1102			   b_res, &bus->busn_res,
1103			   (unsigned long long) (size1 - size0),
1104			   (unsigned long long) add_align);
1105	}
1106	return 0;
1107}
1108
1109unsigned long pci_cardbus_resource_alignment(struct resource *res)
1110{
1111	if (res->flags & IORESOURCE_IO)
1112		return pci_cardbus_io_size;
1113	if (res->flags & IORESOURCE_MEM)
1114		return pci_cardbus_mem_size;
1115	return 0;
1116}
1117
1118static void pci_bus_size_cardbus(struct pci_bus *bus,
1119			struct list_head *realloc_head)
1120{
1121	struct pci_dev *bridge = bus->self;
1122	struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
1123	resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
1124	u16 ctrl;
1125
1126	if (b_res[0].parent)
1127		goto handle_b_res_1;
1128	/*
1129	 * Reserve some resources for CardBus.  We reserve
1130	 * a fixed amount of bus space for CardBus bridges.
1131	 */
1132	b_res[0].start = pci_cardbus_io_size;
1133	b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
1134	b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1135	if (realloc_head) {
1136		b_res[0].end -= pci_cardbus_io_size;
1137		add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
1138				pci_cardbus_io_size);
1139	}
1140
1141handle_b_res_1:
1142	if (b_res[1].parent)
1143		goto handle_b_res_2;
1144	b_res[1].start = pci_cardbus_io_size;
1145	b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
1146	b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1147	if (realloc_head) {
1148		b_res[1].end -= pci_cardbus_io_size;
1149		add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size,
1150				 pci_cardbus_io_size);
1151	}
1152
1153handle_b_res_2:
1154	/* MEM1 must not be pref mmio */
1155	pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1156	if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
1157		ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
1158		pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1159		pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1160	}
1161
1162	/*
1163	 * Check whether prefetchable memory is supported
1164	 * by this bridge.
1165	 */
1166	pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1167	if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
1168		ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
1169		pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1170		pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1171	}
1172
1173	if (b_res[2].parent)
1174		goto handle_b_res_3;
1175	/*
1176	 * If we have prefetchable memory support, allocate
1177	 * two regions.  Otherwise, allocate one region of
1178	 * twice the size.
1179	 */
1180	if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
1181		b_res[2].start = pci_cardbus_mem_size;
1182		b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
1183		b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
1184				  IORESOURCE_STARTALIGN;
1185		if (realloc_head) {
1186			b_res[2].end -= pci_cardbus_mem_size;
1187			add_to_list(realloc_head, bridge, b_res+2,
1188				 pci_cardbus_mem_size, pci_cardbus_mem_size);
1189		}
1190
1191		/* reduce that to half */
1192		b_res_3_size = pci_cardbus_mem_size;
1193	}
1194
1195handle_b_res_3:
1196	if (b_res[3].parent)
1197		goto handle_done;
1198	b_res[3].start = pci_cardbus_mem_size;
1199	b_res[3].end = b_res[3].start + b_res_3_size - 1;
1200	b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
1201	if (realloc_head) {
1202		b_res[3].end -= b_res_3_size;
1203		add_to_list(realloc_head, bridge, b_res+3, b_res_3_size,
1204				 pci_cardbus_mem_size);
1205	}
1206
1207handle_done:
1208	;
1209}
1210
1211void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
1212{
1213	struct pci_dev *dev;
1214	unsigned long mask, prefmask, type2 = 0, type3 = 0;
1215	resource_size_t additional_mem_size = 0, additional_io_size = 0;
1216	struct resource *b_res;
1217	int ret;
1218
1219	list_for_each_entry(dev, &bus->devices, bus_list) {
1220		struct pci_bus *b = dev->subordinate;
1221		if (!b)
1222			continue;
1223
1224		switch (dev->class >> 8) {
1225		case PCI_CLASS_BRIDGE_CARDBUS:
1226			pci_bus_size_cardbus(b, realloc_head);
1227			break;
1228
1229		case PCI_CLASS_BRIDGE_PCI:
1230		default:
1231			__pci_bus_size_bridges(b, realloc_head);
1232			break;
1233		}
1234	}
1235
1236	/* The root bus? */
1237	if (pci_is_root_bus(bus))
1238		return;
1239
1240	switch (bus->self->class >> 8) {
1241	case PCI_CLASS_BRIDGE_CARDBUS:
1242		/* don't size cardbuses yet. */
1243		break;
1244
1245	case PCI_CLASS_BRIDGE_PCI:
1246		pci_bridge_check_ranges(bus);
1247		if (bus->self->is_hotplug_bridge) {
1248			additional_io_size  = pci_hotplug_io_size;
1249			additional_mem_size = pci_hotplug_mem_size;
1250		}
1251		/* Fall through */
1252	default:
1253		pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
1254			     additional_io_size, realloc_head);
1255
1256		/*
1257		 * If there's a 64-bit prefetchable MMIO window, compute
1258		 * the size required to put all 64-bit prefetchable
1259		 * resources in it.
1260		 */
1261		b_res = &bus->self->resource[PCI_BRIDGE_RESOURCES];
1262		mask = IORESOURCE_MEM;
1263		prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
1264		if (b_res[2].flags & IORESOURCE_MEM_64) {
1265			prefmask |= IORESOURCE_MEM_64;
1266			ret = pbus_size_mem(bus, prefmask, prefmask,
1267				  prefmask, prefmask,
1268				  realloc_head ? 0 : additional_mem_size,
1269				  additional_mem_size, realloc_head);
1270
1271			/*
1272			 * If successful, all non-prefetchable resources
1273			 * and any 32-bit prefetchable resources will go in
1274			 * the non-prefetchable window.
1275			 */
1276			if (ret == 0) {
1277				mask = prefmask;
1278				type2 = prefmask & ~IORESOURCE_MEM_64;
1279				type3 = prefmask & ~IORESOURCE_PREFETCH;
1280			}
1281		}
1282
1283		/*
1284		 * If there is no 64-bit prefetchable window, compute the
1285		 * size required to put all prefetchable resources in the
1286		 * 32-bit prefetchable window (if there is one).
1287		 */
1288		if (!type2) {
1289			prefmask &= ~IORESOURCE_MEM_64;
1290			ret = pbus_size_mem(bus, prefmask, prefmask,
1291					 prefmask, prefmask,
1292					 realloc_head ? 0 : additional_mem_size,
1293					 additional_mem_size, realloc_head);
1294
1295			/*
1296			 * If successful, only non-prefetchable resources
1297			 * will go in the non-prefetchable window.
1298			 */
1299			if (ret == 0)
1300				mask = prefmask;
1301			else
1302				additional_mem_size += additional_mem_size;
1303
1304			type2 = type3 = IORESOURCE_MEM;
1305		}
1306
1307		/*
1308		 * Compute the size required to put everything else in the
1309		 * non-prefetchable window.  This includes:
1310		 *
1311		 *   - all non-prefetchable resources
1312		 *   - 32-bit prefetchable resources if there's a 64-bit
1313		 *     prefetchable window or no prefetchable window at all
1314		 *   - 64-bit prefetchable resources if there's no
1315		 *     prefetchable window at all
1316		 *
1317		 * Note that the strategy in __pci_assign_resource() must
1318		 * match that used here.  Specifically, we cannot put a
1319		 * 32-bit prefetchable resource in a 64-bit prefetchable
1320		 * window.
1321		 */
1322		pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3,
1323				realloc_head ? 0 : additional_mem_size,
1324				additional_mem_size, realloc_head);
1325		break;
1326	}
1327}
1328
1329void pci_bus_size_bridges(struct pci_bus *bus)
1330{
1331	__pci_bus_size_bridges(bus, NULL);
1332}
1333EXPORT_SYMBOL(pci_bus_size_bridges);
1334
1335static void assign_fixed_resource_on_bus(struct pci_bus *b, struct resource *r)
1336{
1337	int i;
1338	struct resource *parent_r;
1339	unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM |
1340			     IORESOURCE_PREFETCH;
1341
1342	pci_bus_for_each_resource(b, parent_r, i) {
1343		if (!parent_r)
1344			continue;
1345
1346		if ((r->flags & mask) == (parent_r->flags & mask) &&
1347		    resource_contains(parent_r, r))
1348			request_resource(parent_r, r);
1349	}
1350}
1351
1352/*
1353 * Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they
1354 * are skipped by pbus_assign_resources_sorted().
1355 */
1356static void pdev_assign_fixed_resources(struct pci_dev *dev)
1357{
1358	int i;
1359
1360	for (i = 0; i <  PCI_NUM_RESOURCES; i++) {
1361		struct pci_bus *b;
1362		struct resource *r = &dev->resource[i];
1363
1364		if (r->parent || !(r->flags & IORESOURCE_PCI_FIXED) ||
1365		    !(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
1366			continue;
1367
1368		b = dev->bus;
1369		while (b && !r->parent) {
1370			assign_fixed_resource_on_bus(b, r);
1371			b = b->parent;
1372		}
1373	}
1374}
1375
1376void __pci_bus_assign_resources(const struct pci_bus *bus,
1377				struct list_head *realloc_head,
1378				struct list_head *fail_head)
1379{
1380	struct pci_bus *b;
1381	struct pci_dev *dev;
1382
1383	pbus_assign_resources_sorted(bus, realloc_head, fail_head);
1384
1385	list_for_each_entry(dev, &bus->devices, bus_list) {
1386		pdev_assign_fixed_resources(dev);
1387
1388		b = dev->subordinate;
1389		if (!b)
1390			continue;
1391
1392		__pci_bus_assign_resources(b, realloc_head, fail_head);
1393
1394		switch (dev->class >> 8) {
1395		case PCI_CLASS_BRIDGE_PCI:
1396			if (!pci_is_enabled(dev))
1397				pci_setup_bridge(b);
1398			break;
1399
1400		case PCI_CLASS_BRIDGE_CARDBUS:
1401			pci_setup_cardbus(b);
1402			break;
1403
1404		default:
1405			pci_info(dev, "not setting up bridge for bus %04x:%02x\n",
1406				 pci_domain_nr(b), b->number);
1407			break;
1408		}
1409	}
1410}
1411
1412void pci_bus_assign_resources(const struct pci_bus *bus)
1413{
1414	__pci_bus_assign_resources(bus, NULL, NULL);
1415}
1416EXPORT_SYMBOL(pci_bus_assign_resources);
1417
1418static void pci_claim_device_resources(struct pci_dev *dev)
1419{
1420	int i;
1421
1422	for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
1423		struct resource *r = &dev->resource[i];
1424
1425		if (!r->flags || r->parent)
1426			continue;
1427
1428		pci_claim_resource(dev, i);
1429	}
1430}
1431
1432static void pci_claim_bridge_resources(struct pci_dev *dev)
1433{
1434	int i;
1435
1436	for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
1437		struct resource *r = &dev->resource[i];
1438
1439		if (!r->flags || r->parent)
1440			continue;
1441
1442		pci_claim_bridge_resource(dev, i);
1443	}
1444}
1445
1446static void pci_bus_allocate_dev_resources(struct pci_bus *b)
1447{
1448	struct pci_dev *dev;
1449	struct pci_bus *child;
1450
1451	list_for_each_entry(dev, &b->devices, bus_list) {
1452		pci_claim_device_resources(dev);
1453
1454		child = dev->subordinate;
1455		if (child)
1456			pci_bus_allocate_dev_resources(child);
1457	}
1458}
1459
1460static void pci_bus_allocate_resources(struct pci_bus *b)
1461{
1462	struct pci_bus *child;
1463
1464	/*
1465	 * Carry out a depth-first search on the PCI bus
1466	 * tree to allocate bridge apertures. Read the
1467	 * programmed bridge bases and recursively claim
1468	 * the respective bridge resources.
1469	 */
1470	if (b->self) {
1471		pci_read_bridge_bases(b);
1472		pci_claim_bridge_resources(b->self);
1473	}
1474
1475	list_for_each_entry(child, &b->children, node)
1476		pci_bus_allocate_resources(child);
1477}
1478
1479void pci_bus_claim_resources(struct pci_bus *b)
1480{
1481	pci_bus_allocate_resources(b);
1482	pci_bus_allocate_dev_resources(b);
1483}
1484EXPORT_SYMBOL(pci_bus_claim_resources);
1485
1486static void __pci_bridge_assign_resources(const struct pci_dev *bridge,
1487					  struct list_head *add_head,
1488					  struct list_head *fail_head)
1489{
1490	struct pci_bus *b;
1491
1492	pdev_assign_resources_sorted((struct pci_dev *)bridge,
1493					 add_head, fail_head);
1494
1495	b = bridge->subordinate;
1496	if (!b)
1497		return;
1498
1499	__pci_bus_assign_resources(b, add_head, fail_head);
1500
1501	switch (bridge->class >> 8) {
1502	case PCI_CLASS_BRIDGE_PCI:
1503		pci_setup_bridge(b);
1504		break;
1505
1506	case PCI_CLASS_BRIDGE_CARDBUS:
1507		pci_setup_cardbus(b);
1508		break;
1509
1510	default:
1511		pci_info(bridge, "not setting up bridge for bus %04x:%02x\n",
1512			 pci_domain_nr(b), b->number);
1513		break;
1514	}
1515}
1516
1517#define PCI_RES_TYPE_MASK \
1518	(IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH |\
1519	 IORESOURCE_MEM_64)
1520
1521static void pci_bridge_release_resources(struct pci_bus *bus,
1522					  unsigned long type)
1523{
1524	struct pci_dev *dev = bus->self;
1525	struct resource *r;
 
 
1526	unsigned old_flags = 0;
1527	struct resource *b_res;
1528	int idx = 1;
1529
1530	b_res = &dev->resource[PCI_BRIDGE_RESOURCES];
1531
1532	/*
1533	 *     1. if there is io port assign fail, will release bridge
1534	 *	  io port.
1535	 *     2. if there is non pref mmio assign fail, release bridge
1536	 *	  nonpref mmio.
1537	 *     3. if there is 64bit pref mmio assign fail, and bridge pref
1538	 *	  is 64bit, release bridge pref mmio.
1539	 *     4. if there is pref mmio assign fail, and bridge pref is
1540	 *	  32bit mmio, release bridge pref mmio
1541	 *     5. if there is pref mmio assign fail, and bridge pref is not
1542	 *	  assigned, release bridge nonpref mmio.
1543	 */
1544	if (type & IORESOURCE_IO)
1545		idx = 0;
1546	else if (!(type & IORESOURCE_PREFETCH))
1547		idx = 1;
1548	else if ((type & IORESOURCE_MEM_64) &&
1549		 (b_res[2].flags & IORESOURCE_MEM_64))
1550		idx = 2;
1551	else if (!(b_res[2].flags & IORESOURCE_MEM_64) &&
1552		 (b_res[2].flags & IORESOURCE_PREFETCH))
1553		idx = 2;
1554	else
1555		idx = 1;
1556
1557	r = &b_res[idx];
1558
1559	if (!r->parent)
1560		return;
1561
1562	/*
1563	 * if there are children under that, we should release them
1564	 *  all
1565	 */
1566	release_child_resources(r);
1567	if (!release_resource(r)) {
1568		type = old_flags = r->flags & PCI_RES_TYPE_MASK;
1569		pci_printk(KERN_DEBUG, dev, "resource %d %pR released\n",
1570					PCI_BRIDGE_RESOURCES + idx, r);
1571		/* keep the old size */
1572		r->end = resource_size(r) - 1;
1573		r->start = 0;
1574		r->flags = 0;
1575
1576		/* avoiding touch the one without PREF */
1577		if (type & IORESOURCE_PREFETCH)
1578			type = IORESOURCE_PREFETCH;
1579		__pci_setup_bridge(bus, type);
1580		/* for next child res under same bridge */
1581		r->flags = old_flags;
1582	}
1583}
1584
1585enum release_type {
1586	leaf_only,
1587	whole_subtree,
1588};
1589/*
1590 * try to release pci bridge resources that is from leaf bridge,
1591 * so we can allocate big new one later
1592 */
1593static void pci_bus_release_bridge_resources(struct pci_bus *bus,
1594					     unsigned long type,
1595					     enum release_type rel_type)
1596{
1597	struct pci_dev *dev;
1598	bool is_leaf_bridge = true;
1599
1600	list_for_each_entry(dev, &bus->devices, bus_list) {
1601		struct pci_bus *b = dev->subordinate;
1602		if (!b)
1603			continue;
1604
1605		is_leaf_bridge = false;
1606
1607		if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1608			continue;
1609
1610		if (rel_type == whole_subtree)
1611			pci_bus_release_bridge_resources(b, type,
1612						 whole_subtree);
1613	}
1614
1615	if (pci_is_root_bus(bus))
1616		return;
1617
1618	if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1619		return;
1620
1621	if ((rel_type == whole_subtree) || is_leaf_bridge)
1622		pci_bridge_release_resources(bus, type);
1623}
1624
1625static void pci_bus_dump_res(struct pci_bus *bus)
1626{
1627	struct resource *res;
1628	int i;
1629
1630	pci_bus_for_each_resource(bus, res, i) {
1631		if (!res || !res->end || !res->flags)
1632			continue;
1633
1634		dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
1635	}
1636}
1637
1638static void pci_bus_dump_resources(struct pci_bus *bus)
1639{
1640	struct pci_bus *b;
1641	struct pci_dev *dev;
1642
1643
1644	pci_bus_dump_res(bus);
1645
1646	list_for_each_entry(dev, &bus->devices, bus_list) {
1647		b = dev->subordinate;
1648		if (!b)
1649			continue;
1650
1651		pci_bus_dump_resources(b);
1652	}
1653}
1654
1655static int pci_bus_get_depth(struct pci_bus *bus)
1656{
1657	int depth = 0;
1658	struct pci_bus *child_bus;
1659
1660	list_for_each_entry(child_bus, &bus->children, node) {
1661		int ret;
1662
1663		ret = pci_bus_get_depth(child_bus);
1664		if (ret + 1 > depth)
1665			depth = ret + 1;
1666	}
1667
1668	return depth;
1669}
1670
1671/*
1672 * -1: undefined, will auto detect later
1673 *  0: disabled by user
1674 *  1: disabled by auto detect
1675 *  2: enabled by user
1676 *  3: enabled by auto detect
1677 */
1678enum enable_type {
1679	undefined = -1,
1680	user_disabled,
1681	auto_disabled,
1682	user_enabled,
1683	auto_enabled,
1684};
1685
1686static enum enable_type pci_realloc_enable = undefined;
1687void __init pci_realloc_get_opt(char *str)
1688{
1689	if (!strncmp(str, "off", 3))
1690		pci_realloc_enable = user_disabled;
1691	else if (!strncmp(str, "on", 2))
1692		pci_realloc_enable = user_enabled;
1693}
1694static bool pci_realloc_enabled(enum enable_type enable)
1695{
1696	return enable >= user_enabled;
1697}
1698
1699#if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
1700static int iov_resources_unassigned(struct pci_dev *dev, void *data)
1701{
1702	int i;
1703	bool *unassigned = data;
1704
1705	for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) {
1706		struct resource *r = &dev->resource[i];
1707		struct pci_bus_region region;
1708
1709		/* Not assigned or rejected by kernel? */
1710		if (!r->flags)
1711			continue;
1712
1713		pcibios_resource_to_bus(dev->bus, &region, r);
1714		if (!region.start) {
1715			*unassigned = true;
1716			return 1; /* return early from pci_walk_bus() */
1717		}
1718	}
1719
1720	return 0;
1721}
1722
1723static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1724			 enum enable_type enable_local)
1725{
1726	bool unassigned = false;
1727
1728	if (enable_local != undefined)
1729		return enable_local;
1730
1731	pci_walk_bus(bus, iov_resources_unassigned, &unassigned);
1732	if (unassigned)
1733		return auto_enabled;
1734
1735	return enable_local;
1736}
1737#else
1738static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1739			 enum enable_type enable_local)
1740{
1741	return enable_local;
1742}
1743#endif
1744
1745/*
1746 * first try will not touch pci bridge res
1747 * second and later try will clear small leaf bridge res
1748 * will stop till to the max depth if can not find good one
1749 */
1750void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
1751{
1752	LIST_HEAD(realloc_head); /* list of resources that
1753					want additional resources */
1754	struct list_head *add_list = NULL;
1755	int tried_times = 0;
1756	enum release_type rel_type = leaf_only;
1757	LIST_HEAD(fail_head);
1758	struct pci_dev_resource *fail_res;
 
 
1759	int pci_try_num = 1;
1760	enum enable_type enable_local;
1761
1762	/* don't realloc if asked to do so */
1763	enable_local = pci_realloc_detect(bus, pci_realloc_enable);
1764	if (pci_realloc_enabled(enable_local)) {
1765		int max_depth = pci_bus_get_depth(bus);
1766
1767		pci_try_num = max_depth + 1;
1768		dev_printk(KERN_DEBUG, &bus->dev,
1769			   "max bus depth: %d pci_try_num: %d\n",
1770			   max_depth, pci_try_num);
1771	}
1772
1773again:
1774	/*
1775	 * last try will use add_list, otherwise will try good to have as
1776	 * must have, so can realloc parent bridge resource
1777	 */
1778	if (tried_times + 1 == pci_try_num)
1779		add_list = &realloc_head;
1780	/* Depth first, calculate sizes and alignments of all
1781	   subordinate buses. */
1782	__pci_bus_size_bridges(bus, add_list);
1783
1784	/* Depth last, allocate resources and update the hardware. */
1785	__pci_bus_assign_resources(bus, add_list, &fail_head);
1786	if (add_list)
1787		BUG_ON(!list_empty(add_list));
1788	tried_times++;
1789
1790	/* any device complain? */
1791	if (list_empty(&fail_head))
1792		goto dump;
1793
1794	if (tried_times >= pci_try_num) {
1795		if (enable_local == undefined)
1796			dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n");
1797		else if (enable_local == auto_enabled)
1798			dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
1799
1800		free_list(&fail_head);
1801		goto dump;
1802	}
1803
1804	dev_printk(KERN_DEBUG, &bus->dev,
1805		   "No. %d try to assign unassigned res\n", tried_times + 1);
1806
1807	/* third times and later will not check if it is leaf */
1808	if ((tried_times + 1) > 2)
1809		rel_type = whole_subtree;
1810
1811	/*
1812	 * Try to release leaf bridge's resources that doesn't fit resource of
1813	 * child device under that bridge
1814	 */
1815	list_for_each_entry(fail_res, &fail_head, list)
1816		pci_bus_release_bridge_resources(fail_res->dev->bus,
1817						 fail_res->flags & PCI_RES_TYPE_MASK,
1818						 rel_type);
1819
1820	/* restore size and flags */
1821	list_for_each_entry(fail_res, &fail_head, list) {
1822		struct resource *res = fail_res->res;
1823
1824		res->start = fail_res->start;
1825		res->end = fail_res->end;
1826		res->flags = fail_res->flags;
1827		if (fail_res->dev->subordinate)
1828			res->flags = 0;
1829	}
1830	free_list(&fail_head);
1831
1832	goto again;
1833
1834dump:
1835	/* dump the resource on buses */
1836	pci_bus_dump_resources(bus);
1837}
1838
1839void __init pci_assign_unassigned_resources(void)
1840{
1841	struct pci_bus *root_bus;
1842
1843	list_for_each_entry(root_bus, &pci_root_buses, node) {
1844		pci_assign_unassigned_root_bus_resources(root_bus);
1845
1846		/* Make sure the root bridge has a companion ACPI device: */
1847		if (ACPI_HANDLE(root_bus->bridge))
1848			acpi_ioapic_add(ACPI_HANDLE(root_bus->bridge));
1849	}
1850}
1851
1852static void extend_bridge_window(struct pci_dev *bridge, struct resource *res,
1853			struct list_head *add_list, resource_size_t available)
1854{
1855	struct pci_dev_resource *dev_res;
1856
1857	if (res->parent)
1858		return;
1859
1860	if (resource_size(res) >= available)
1861		return;
1862
1863	dev_res = res_to_dev_res(add_list, res);
1864	if (!dev_res)
1865		return;
1866
1867	/* Is there room to extend the window? */
1868	if (available - resource_size(res) <= dev_res->add_size)
1869		return;
1870
1871	dev_res->add_size = available - resource_size(res);
1872	pci_dbg(bridge, "bridge window %pR extended by %pa\n", res,
1873		&dev_res->add_size);
1874}
1875
1876static void pci_bus_distribute_available_resources(struct pci_bus *bus,
1877	struct list_head *add_list, resource_size_t available_io,
1878	resource_size_t available_mmio, resource_size_t available_mmio_pref)
1879{
1880	resource_size_t remaining_io, remaining_mmio, remaining_mmio_pref;
1881	unsigned int normal_bridges = 0, hotplug_bridges = 0;
1882	struct resource *io_res, *mmio_res, *mmio_pref_res;
1883	struct pci_dev *dev, *bridge = bus->self;
1884
1885	io_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
1886	mmio_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
1887	mmio_pref_res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
1888
1889	/*
1890	 * Update additional resource list (add_list) to fill all the
1891	 * extra resource space available for this port except the space
1892	 * calculated in __pci_bus_size_bridges() which covers all the
1893	 * devices currently connected to the port and below.
1894	 */
1895	extend_bridge_window(bridge, io_res, add_list, available_io);
1896	extend_bridge_window(bridge, mmio_res, add_list, available_mmio);
1897	extend_bridge_window(bridge, mmio_pref_res, add_list,
1898			     available_mmio_pref);
1899
1900	/*
1901	 * Calculate the total amount of extra resource space we can
1902	 * pass to bridges below this one. This is basically the
1903	 * extra space reduced by the minimal required space for the
1904	 * non-hotplug bridges.
1905	 */
1906	remaining_io = available_io;
1907	remaining_mmio = available_mmio;
1908	remaining_mmio_pref = available_mmio_pref;
1909
1910	/*
1911	 * Calculate how many hotplug bridges and normal bridges there
1912	 * are on this bus. We will distribute the additional available
1913	 * resources between hotplug bridges.
1914	 */
1915	for_each_pci_bridge(dev, bus) {
1916		if (dev->is_hotplug_bridge)
1917			hotplug_bridges++;
1918		else
1919			normal_bridges++;
1920	}
1921
1922	for_each_pci_bridge(dev, bus) {
1923		const struct resource *res;
1924
1925		if (dev->is_hotplug_bridge)
1926			continue;
1927
1928		/*
1929		 * Reduce the available resource space by what the
1930		 * bridge and devices below it occupy.
1931		 */
1932		res = &dev->resource[PCI_BRIDGE_RESOURCES + 0];
1933		if (!res->parent && available_io > resource_size(res))
1934			remaining_io -= resource_size(res);
1935
1936		res = &dev->resource[PCI_BRIDGE_RESOURCES + 1];
1937		if (!res->parent && available_mmio > resource_size(res))
1938			remaining_mmio -= resource_size(res);
1939
1940		res = &dev->resource[PCI_BRIDGE_RESOURCES + 2];
1941		if (!res->parent && available_mmio_pref > resource_size(res))
1942			remaining_mmio_pref -= resource_size(res);
1943	}
1944
1945	/*
1946	 * Go over devices on this bus and distribute the remaining
1947	 * resource space between hotplug bridges.
1948	 */
1949	for_each_pci_bridge(dev, bus) {
1950		struct pci_bus *b;
1951
1952		b = dev->subordinate;
1953		if (!b)
1954			continue;
1955
1956		if (!hotplug_bridges && normal_bridges == 1) {
1957			/*
1958			 * There is only one bridge on the bus (upstream
1959			 * port) so it gets all available resources
1960			 * which it can then distribute to the possible
1961			 * hotplug bridges below.
1962			 */
1963			pci_bus_distribute_available_resources(b, add_list,
1964				available_io, available_mmio,
1965				available_mmio_pref);
1966		} else if (dev->is_hotplug_bridge) {
1967			resource_size_t align, io, mmio, mmio_pref;
1968
1969			/*
1970			 * Distribute available extra resources equally
1971			 * between hotplug-capable downstream ports
1972			 * taking alignment into account.
1973			 *
1974			 * Here hotplug_bridges is always != 0.
1975			 */
1976			align = pci_resource_alignment(bridge, io_res);
1977			io = div64_ul(available_io, hotplug_bridges);
1978			io = min(ALIGN(io, align), remaining_io);
1979			remaining_io -= io;
1980
1981			align = pci_resource_alignment(bridge, mmio_res);
1982			mmio = div64_ul(available_mmio, hotplug_bridges);
1983			mmio = min(ALIGN(mmio, align), remaining_mmio);
1984			remaining_mmio -= mmio;
1985
1986			align = pci_resource_alignment(bridge, mmio_pref_res);
1987			mmio_pref = div64_ul(available_mmio_pref,
1988					     hotplug_bridges);
1989			mmio_pref = min(ALIGN(mmio_pref, align),
1990					remaining_mmio_pref);
1991			remaining_mmio_pref -= mmio_pref;
1992
1993			pci_bus_distribute_available_resources(b, add_list, io,
1994							       mmio, mmio_pref);
1995		}
1996	}
1997}
1998
1999static void
2000pci_bridge_distribute_available_resources(struct pci_dev *bridge,
2001					  struct list_head *add_list)
2002{
2003	resource_size_t available_io, available_mmio, available_mmio_pref;
2004	const struct resource *res;
2005
2006	if (!bridge->is_hotplug_bridge)
2007		return;
2008
2009	/* Take the initial extra resources from the hotplug port */
2010	res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
2011	available_io = resource_size(res);
2012	res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
2013	available_mmio = resource_size(res);
2014	res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
2015	available_mmio_pref = resource_size(res);
2016
2017	pci_bus_distribute_available_resources(bridge->subordinate,
2018		add_list, available_io, available_mmio, available_mmio_pref);
2019}
2020
2021void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
2022{
2023	struct pci_bus *parent = bridge->subordinate;
2024	LIST_HEAD(add_list); /* list of resources that
2025					want additional resources */
2026	int tried_times = 0;
2027	LIST_HEAD(fail_head);
2028	struct pci_dev_resource *fail_res;
2029	int retval;
 
 
2030
2031again:
2032	__pci_bus_size_bridges(parent, &add_list);
2033
2034	/*
2035	 * Distribute remaining resources (if any) equally between
2036	 * hotplug bridges below. This makes it possible to extend the
2037	 * hierarchy later without running out of resources.
2038	 */
2039	pci_bridge_distribute_available_resources(bridge, &add_list);
2040
2041	__pci_bridge_assign_resources(bridge, &add_list, &fail_head);
2042	BUG_ON(!list_empty(&add_list));
2043	tried_times++;
2044
2045	if (list_empty(&fail_head))
2046		goto enable_all;
2047
2048	if (tried_times >= 2) {
2049		/* still fail, don't need to try more */
2050		free_list(&fail_head);
2051		goto enable_all;
2052	}
2053
2054	printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
2055			 tried_times + 1);
2056
2057	/*
2058	 * Try to release leaf bridge's resources that doesn't fit resource of
2059	 * child device under that bridge
2060	 */
2061	list_for_each_entry(fail_res, &fail_head, list)
2062		pci_bus_release_bridge_resources(fail_res->dev->bus,
2063						 fail_res->flags & PCI_RES_TYPE_MASK,
2064						 whole_subtree);
2065
2066	/* restore size and flags */
2067	list_for_each_entry(fail_res, &fail_head, list) {
2068		struct resource *res = fail_res->res;
2069
2070		res->start = fail_res->start;
2071		res->end = fail_res->end;
2072		res->flags = fail_res->flags;
2073		if (fail_res->dev->subordinate)
2074			res->flags = 0;
2075	}
2076	free_list(&fail_head);
2077
2078	goto again;
2079
2080enable_all:
2081	retval = pci_reenable_device(bridge);
2082	if (retval)
2083		pci_err(bridge, "Error reenabling bridge (%d)\n", retval);
2084	pci_set_master(bridge);
2085}
2086EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
2087
2088int pci_reassign_bridge_resources(struct pci_dev *bridge, unsigned long type)
2089{
2090	struct pci_dev_resource *dev_res;
2091	struct pci_dev *next;
2092	LIST_HEAD(saved);
2093	LIST_HEAD(added);
2094	LIST_HEAD(failed);
2095	unsigned int i;
2096	int ret;
2097
2098	/* Walk to the root hub, releasing bridge BARs when possible */
2099	next = bridge;
2100	do {
2101		bridge = next;
2102		for (i = PCI_BRIDGE_RESOURCES; i < PCI_BRIDGE_RESOURCE_END;
2103		     i++) {
2104			struct resource *res = &bridge->resource[i];
2105
2106			if ((res->flags ^ type) & PCI_RES_TYPE_MASK)
2107				continue;
2108
2109			/* Ignore BARs which are still in use */
2110			if (res->child)
2111				continue;
2112
2113			ret = add_to_list(&saved, bridge, res, 0, 0);
2114			if (ret)
2115				goto cleanup;
2116
2117			pci_info(bridge, "BAR %d: releasing %pR\n",
2118				 i, res);
2119
2120			if (res->parent)
2121				release_resource(res);
2122			res->start = 0;
2123			res->end = 0;
2124			break;
2125		}
2126		if (i == PCI_BRIDGE_RESOURCE_END)
2127			break;
2128
2129		next = bridge->bus ? bridge->bus->self : NULL;
2130	} while (next);
2131
2132	if (list_empty(&saved))
2133		return -ENOENT;
2134
2135	__pci_bus_size_bridges(bridge->subordinate, &added);
2136	__pci_bridge_assign_resources(bridge, &added, &failed);
2137	BUG_ON(!list_empty(&added));
2138
2139	if (!list_empty(&failed)) {
2140		ret = -ENOSPC;
2141		goto cleanup;
2142	}
2143
2144	list_for_each_entry(dev_res, &saved, list) {
2145		/* Skip the bridge we just assigned resources for. */
2146		if (bridge == dev_res->dev)
2147			continue;
2148
2149		bridge = dev_res->dev;
2150		pci_setup_bridge(bridge->subordinate);
2151	}
2152
2153	free_list(&saved);
2154	return 0;
2155
2156cleanup:
2157	/* restore size and flags */
2158	list_for_each_entry(dev_res, &failed, list) {
2159		struct resource *res = dev_res->res;
2160
2161		res->start = dev_res->start;
2162		res->end = dev_res->end;
2163		res->flags = dev_res->flags;
2164	}
2165	free_list(&failed);
2166
2167	/* Revert to the old configuration */
2168	list_for_each_entry(dev_res, &saved, list) {
2169		struct resource *res = dev_res->res;
2170
2171		bridge = dev_res->dev;
2172		i = res - bridge->resource;
2173
2174		res->start = dev_res->start;
2175		res->end = dev_res->end;
2176		res->flags = dev_res->flags;
2177
2178		pci_claim_resource(bridge, i);
2179		pci_setup_bridge(bridge->subordinate);
2180	}
2181	free_list(&saved);
2182
2183	return ret;
2184}
2185
2186void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
2187{
2188	struct pci_dev *dev;
2189	LIST_HEAD(add_list); /* list of resources that
2190					want additional resources */
2191
2192	down_read(&pci_bus_sem);
2193	for_each_pci_bridge(dev, bus)
2194		if (pci_has_subordinate(dev))
2195			__pci_bus_size_bridges(dev->subordinate, &add_list);
 
2196	up_read(&pci_bus_sem);
2197	__pci_bus_assign_resources(bus, &add_list, NULL);
2198	BUG_ON(!list_empty(&add_list));
2199}
2200EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources);