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1/* SPDX-License-Identifier: GPL-2.0 */
2/* Intel(R) Gigabit Ethernet Linux driver
3 * Copyright(c) 2007-2014 Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, see <http://www.gnu.org/licenses/>.
16 *
17 * The full GNU General Public License is included in this distribution in
18 * the file called "COPYING".
19 *
20 * Contact Information:
21 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
22 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
23 */
24
25/* Linux PRO/1000 Ethernet Driver main header file */
26
27#ifndef _IGB_H_
28#define _IGB_H_
29
30#include "e1000_mac.h"
31#include "e1000_82575.h"
32
33#include <linux/timecounter.h>
34#include <linux/net_tstamp.h>
35#include <linux/ptp_clock_kernel.h>
36#include <linux/bitops.h>
37#include <linux/if_vlan.h>
38#include <linux/i2c.h>
39#include <linux/i2c-algo-bit.h>
40#include <linux/pci.h>
41#include <linux/mdio.h>
42
43struct igb_adapter;
44
45#define E1000_PCS_CFG_IGN_SD 1
46
47/* Interrupt defines */
48#define IGB_START_ITR 648 /* ~6000 ints/sec */
49#define IGB_4K_ITR 980
50#define IGB_20K_ITR 196
51#define IGB_70K_ITR 56
52
53/* TX/RX descriptor defines */
54#define IGB_DEFAULT_TXD 256
55#define IGB_DEFAULT_TX_WORK 128
56#define IGB_MIN_TXD 80
57#define IGB_MAX_TXD 4096
58
59#define IGB_DEFAULT_RXD 256
60#define IGB_MIN_RXD 80
61#define IGB_MAX_RXD 4096
62
63#define IGB_DEFAULT_ITR 3 /* dynamic */
64#define IGB_MAX_ITR_USECS 10000
65#define IGB_MIN_ITR_USECS 10
66#define NON_Q_VECTORS 1
67#define MAX_Q_VECTORS 8
68#define MAX_MSIX_ENTRIES 10
69
70/* Transmit and receive queues */
71#define IGB_MAX_RX_QUEUES 8
72#define IGB_MAX_RX_QUEUES_82575 4
73#define IGB_MAX_RX_QUEUES_I211 2
74#define IGB_MAX_TX_QUEUES 8
75#define IGB_MAX_VF_MC_ENTRIES 30
76#define IGB_MAX_VF_FUNCTIONS 8
77#define IGB_MAX_VFTA_ENTRIES 128
78#define IGB_82576_VF_DEV_ID 0x10CA
79#define IGB_I350_VF_DEV_ID 0x1520
80
81/* NVM version defines */
82#define IGB_MAJOR_MASK 0xF000
83#define IGB_MINOR_MASK 0x0FF0
84#define IGB_BUILD_MASK 0x000F
85#define IGB_COMB_VER_MASK 0x00FF
86#define IGB_MAJOR_SHIFT 12
87#define IGB_MINOR_SHIFT 4
88#define IGB_COMB_VER_SHFT 8
89#define IGB_NVM_VER_INVALID 0xFFFF
90#define IGB_ETRACK_SHIFT 16
91#define NVM_ETRACK_WORD 0x0042
92#define NVM_COMB_VER_OFF 0x0083
93#define NVM_COMB_VER_PTR 0x003d
94
95/* Transmit and receive latency (for PTP timestamps) */
96#define IGB_I210_TX_LATENCY_10 9542
97#define IGB_I210_TX_LATENCY_100 1024
98#define IGB_I210_TX_LATENCY_1000 178
99#define IGB_I210_RX_LATENCY_10 20662
100#define IGB_I210_RX_LATENCY_100 2213
101#define IGB_I210_RX_LATENCY_1000 448
102
103struct vf_data_storage {
104 unsigned char vf_mac_addresses[ETH_ALEN];
105 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
106 u16 num_vf_mc_hashes;
107 u32 flags;
108 unsigned long last_nack;
109 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
110 u16 pf_qos;
111 u16 tx_rate;
112 bool spoofchk_enabled;
113 bool trusted;
114};
115
116/* Number of unicast MAC filters reserved for the PF in the RAR registers */
117#define IGB_PF_MAC_FILTERS_RESERVED 3
118
119struct vf_mac_filter {
120 struct list_head l;
121 int vf;
122 bool free;
123 u8 vf_mac[ETH_ALEN];
124};
125
126#define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
127#define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
128#define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
129#define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
130
131/* RX descriptor control thresholds.
132 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
133 * descriptors available in its onboard memory.
134 * Setting this to 0 disables RX descriptor prefetch.
135 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
136 * available in host memory.
137 * If PTHRESH is 0, this should also be 0.
138 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
139 * descriptors until either it has this many to write back, or the
140 * ITR timer expires.
141 */
142#define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
143#define IGB_RX_HTHRESH 8
144#define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
145#define IGB_TX_HTHRESH 1
146#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
147 (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 4)
148#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
149 (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 16)
150
151/* this is the size past which hardware will drop packets when setting LPE=0 */
152#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
153
154/* Supported Rx Buffer Sizes */
155#define IGB_RXBUFFER_256 256
156#define IGB_RXBUFFER_2048 2048
157#define IGB_RXBUFFER_3072 3072
158#define IGB_RX_HDR_LEN IGB_RXBUFFER_256
159#define IGB_TS_HDR_LEN 16
160
161#define IGB_SKB_PAD (NET_SKB_PAD + NET_IP_ALIGN)
162#if (PAGE_SIZE < 8192)
163#define IGB_MAX_FRAME_BUILD_SKB \
164 (SKB_WITH_OVERHEAD(IGB_RXBUFFER_2048) - IGB_SKB_PAD - IGB_TS_HDR_LEN)
165#else
166#define IGB_MAX_FRAME_BUILD_SKB (IGB_RXBUFFER_2048 - IGB_TS_HDR_LEN)
167#endif
168
169/* How many Rx Buffers do we bundle into one write to the hardware ? */
170#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
171
172#define IGB_RX_DMA_ATTR \
173 (DMA_ATTR_SKIP_CPU_SYNC | DMA_ATTR_WEAK_ORDERING)
174
175#define AUTO_ALL_MODES 0
176#define IGB_EEPROM_APME 0x0400
177
178#ifndef IGB_MASTER_SLAVE
179/* Switch to override PHY master/slave setting */
180#define IGB_MASTER_SLAVE e1000_ms_hw_default
181#endif
182
183#define IGB_MNG_VLAN_NONE -1
184
185enum igb_tx_flags {
186 /* cmd_type flags */
187 IGB_TX_FLAGS_VLAN = 0x01,
188 IGB_TX_FLAGS_TSO = 0x02,
189 IGB_TX_FLAGS_TSTAMP = 0x04,
190
191 /* olinfo flags */
192 IGB_TX_FLAGS_IPV4 = 0x10,
193 IGB_TX_FLAGS_CSUM = 0x20,
194};
195
196/* VLAN info */
197#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
198#define IGB_TX_FLAGS_VLAN_SHIFT 16
199
200/* The largest size we can write to the descriptor is 65535. In order to
201 * maintain a power of two alignment we have to limit ourselves to 32K.
202 */
203#define IGB_MAX_TXD_PWR 15
204#define IGB_MAX_DATA_PER_TXD (1u << IGB_MAX_TXD_PWR)
205
206/* Tx Descriptors needed, worst case */
207#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD)
208#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
209
210/* EEPROM byte offsets */
211#define IGB_SFF_8472_SWAP 0x5C
212#define IGB_SFF_8472_COMP 0x5E
213
214/* Bitmasks */
215#define IGB_SFF_ADDRESSING_MODE 0x4
216#define IGB_SFF_8472_UNSUP 0x00
217
218/* wrapper around a pointer to a socket buffer,
219 * so a DMA handle can be stored along with the buffer
220 */
221struct igb_tx_buffer {
222 union e1000_adv_tx_desc *next_to_watch;
223 unsigned long time_stamp;
224 struct sk_buff *skb;
225 unsigned int bytecount;
226 u16 gso_segs;
227 __be16 protocol;
228
229 DEFINE_DMA_UNMAP_ADDR(dma);
230 DEFINE_DMA_UNMAP_LEN(len);
231 u32 tx_flags;
232};
233
234struct igb_rx_buffer {
235 dma_addr_t dma;
236 struct page *page;
237#if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
238 __u32 page_offset;
239#else
240 __u16 page_offset;
241#endif
242 __u16 pagecnt_bias;
243};
244
245struct igb_tx_queue_stats {
246 u64 packets;
247 u64 bytes;
248 u64 restart_queue;
249 u64 restart_queue2;
250};
251
252struct igb_rx_queue_stats {
253 u64 packets;
254 u64 bytes;
255 u64 drops;
256 u64 csum_err;
257 u64 alloc_failed;
258};
259
260struct igb_ring_container {
261 struct igb_ring *ring; /* pointer to linked list of rings */
262 unsigned int total_bytes; /* total bytes processed this int */
263 unsigned int total_packets; /* total packets processed this int */
264 u16 work_limit; /* total work allowed per interrupt */
265 u8 count; /* total number of rings in vector */
266 u8 itr; /* current ITR setting for ring */
267};
268
269struct igb_ring {
270 struct igb_q_vector *q_vector; /* backlink to q_vector */
271 struct net_device *netdev; /* back pointer to net_device */
272 struct device *dev; /* device pointer for dma mapping */
273 union { /* array of buffer info structs */
274 struct igb_tx_buffer *tx_buffer_info;
275 struct igb_rx_buffer *rx_buffer_info;
276 };
277 void *desc; /* descriptor ring memory */
278 unsigned long flags; /* ring specific flags */
279 void __iomem *tail; /* pointer to ring tail register */
280 dma_addr_t dma; /* phys address of the ring */
281 unsigned int size; /* length of desc. ring in bytes */
282
283 u16 count; /* number of desc. in the ring */
284 u8 queue_index; /* logical index of the ring*/
285 u8 reg_idx; /* physical index of the ring */
286 bool cbs_enable; /* indicates if CBS is enabled */
287 s32 idleslope; /* idleSlope in kbps */
288 s32 sendslope; /* sendSlope in kbps */
289 s32 hicredit; /* hiCredit in bytes */
290 s32 locredit; /* loCredit in bytes */
291
292 /* everything past this point are written often */
293 u16 next_to_clean;
294 u16 next_to_use;
295 u16 next_to_alloc;
296
297 union {
298 /* TX */
299 struct {
300 struct igb_tx_queue_stats tx_stats;
301 struct u64_stats_sync tx_syncp;
302 struct u64_stats_sync tx_syncp2;
303 };
304 /* RX */
305 struct {
306 struct sk_buff *skb;
307 struct igb_rx_queue_stats rx_stats;
308 struct u64_stats_sync rx_syncp;
309 };
310 };
311} ____cacheline_internodealigned_in_smp;
312
313struct igb_q_vector {
314 struct igb_adapter *adapter; /* backlink */
315 int cpu; /* CPU for DCA */
316 u32 eims_value; /* EIMS mask value */
317
318 u16 itr_val;
319 u8 set_itr;
320 void __iomem *itr_register;
321
322 struct igb_ring_container rx, tx;
323
324 struct napi_struct napi;
325 struct rcu_head rcu; /* to avoid race with update stats on free */
326 char name[IFNAMSIZ + 9];
327
328 /* for dynamic allocation of rings associated with this q_vector */
329 struct igb_ring ring[0] ____cacheline_internodealigned_in_smp;
330};
331
332enum e1000_ring_flags_t {
333 IGB_RING_FLAG_RX_3K_BUFFER,
334 IGB_RING_FLAG_RX_BUILD_SKB_ENABLED,
335 IGB_RING_FLAG_RX_SCTP_CSUM,
336 IGB_RING_FLAG_RX_LB_VLAN_BSWAP,
337 IGB_RING_FLAG_TX_CTX_IDX,
338 IGB_RING_FLAG_TX_DETECT_HANG
339};
340
341#define ring_uses_large_buffer(ring) \
342 test_bit(IGB_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
343#define set_ring_uses_large_buffer(ring) \
344 set_bit(IGB_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
345#define clear_ring_uses_large_buffer(ring) \
346 clear_bit(IGB_RING_FLAG_RX_3K_BUFFER, &(ring)->flags)
347
348#define ring_uses_build_skb(ring) \
349 test_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
350#define set_ring_build_skb_enabled(ring) \
351 set_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
352#define clear_ring_build_skb_enabled(ring) \
353 clear_bit(IGB_RING_FLAG_RX_BUILD_SKB_ENABLED, &(ring)->flags)
354
355static inline unsigned int igb_rx_bufsz(struct igb_ring *ring)
356{
357#if (PAGE_SIZE < 8192)
358 if (ring_uses_large_buffer(ring))
359 return IGB_RXBUFFER_3072;
360
361 if (ring_uses_build_skb(ring))
362 return IGB_MAX_FRAME_BUILD_SKB + IGB_TS_HDR_LEN;
363#endif
364 return IGB_RXBUFFER_2048;
365}
366
367static inline unsigned int igb_rx_pg_order(struct igb_ring *ring)
368{
369#if (PAGE_SIZE < 8192)
370 if (ring_uses_large_buffer(ring))
371 return 1;
372#endif
373 return 0;
374}
375
376#define igb_rx_pg_size(_ring) (PAGE_SIZE << igb_rx_pg_order(_ring))
377
378#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
379
380#define IGB_RX_DESC(R, i) \
381 (&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
382#define IGB_TX_DESC(R, i) \
383 (&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
384#define IGB_TX_CTXTDESC(R, i) \
385 (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
386
387/* igb_test_staterr - tests bits within Rx descriptor status and error fields */
388static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc,
389 const u32 stat_err_bits)
390{
391 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
392}
393
394/* igb_desc_unused - calculate if we have unused descriptors */
395static inline int igb_desc_unused(struct igb_ring *ring)
396{
397 if (ring->next_to_clean > ring->next_to_use)
398 return ring->next_to_clean - ring->next_to_use - 1;
399
400 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
401}
402
403#ifdef CONFIG_IGB_HWMON
404
405#define IGB_HWMON_TYPE_LOC 0
406#define IGB_HWMON_TYPE_TEMP 1
407#define IGB_HWMON_TYPE_CAUTION 2
408#define IGB_HWMON_TYPE_MAX 3
409
410struct hwmon_attr {
411 struct device_attribute dev_attr;
412 struct e1000_hw *hw;
413 struct e1000_thermal_diode_data *sensor;
414 char name[12];
415 };
416
417struct hwmon_buff {
418 struct attribute_group group;
419 const struct attribute_group *groups[2];
420 struct attribute *attrs[E1000_MAX_SENSORS * 4 + 1];
421 struct hwmon_attr hwmon_list[E1000_MAX_SENSORS * 4];
422 unsigned int n_hwmon;
423 };
424#endif
425
426/* The number of L2 ether-type filter registers, Index 3 is reserved
427 * for PTP 1588 timestamp
428 */
429#define MAX_ETYPE_FILTER (4 - 1)
430/* ETQF filter list: one static filter per filter consumer. This is
431 * to avoid filter collisions later. Add new filters here!!
432 *
433 * Current filters: Filter 3
434 */
435#define IGB_ETQF_FILTER_1588 3
436
437#define IGB_N_EXTTS 2
438#define IGB_N_PEROUT 2
439#define IGB_N_SDP 4
440#define IGB_RETA_SIZE 128
441
442enum igb_filter_match_flags {
443 IGB_FILTER_FLAG_ETHER_TYPE = 0x1,
444 IGB_FILTER_FLAG_VLAN_TCI = 0x2,
445};
446
447#define IGB_MAX_RXNFC_FILTERS 16
448
449/* RX network flow classification data structure */
450struct igb_nfc_input {
451 /* Byte layout in order, all values with MSB first:
452 * match_flags - 1 byte
453 * etype - 2 bytes
454 * vlan_tci - 2 bytes
455 */
456 u8 match_flags;
457 __be16 etype;
458 __be16 vlan_tci;
459};
460
461struct igb_nfc_filter {
462 struct hlist_node nfc_node;
463 struct igb_nfc_input filter;
464 u16 etype_reg_index;
465 u16 sw_idx;
466 u16 action;
467};
468
469struct igb_mac_addr {
470 u8 addr[ETH_ALEN];
471 u8 queue;
472 u8 state; /* bitmask */
473};
474
475#define IGB_MAC_STATE_DEFAULT 0x1
476#define IGB_MAC_STATE_IN_USE 0x2
477
478/* board specific private data structure */
479struct igb_adapter {
480 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
481
482 struct net_device *netdev;
483
484 unsigned long state;
485 unsigned int flags;
486
487 unsigned int num_q_vectors;
488 struct msix_entry msix_entries[MAX_MSIX_ENTRIES];
489
490 /* Interrupt Throttle Rate */
491 u32 rx_itr_setting;
492 u32 tx_itr_setting;
493 u16 tx_itr;
494 u16 rx_itr;
495
496 /* TX */
497 u16 tx_work_limit;
498 u32 tx_timeout_count;
499 int num_tx_queues;
500 struct igb_ring *tx_ring[16];
501
502 /* RX */
503 int num_rx_queues;
504 struct igb_ring *rx_ring[16];
505
506 u32 max_frame_size;
507 u32 min_frame_size;
508
509 struct timer_list watchdog_timer;
510 struct timer_list phy_info_timer;
511
512 u16 mng_vlan_id;
513 u32 bd_number;
514 u32 wol;
515 u32 en_mng_pt;
516 u16 link_speed;
517 u16 link_duplex;
518
519 u8 __iomem *io_addr; /* Mainly for iounmap use */
520
521 struct work_struct reset_task;
522 struct work_struct watchdog_task;
523 bool fc_autoneg;
524 u8 tx_timeout_factor;
525 struct timer_list blink_timer;
526 unsigned long led_status;
527
528 /* OS defined structs */
529 struct pci_dev *pdev;
530
531 spinlock_t stats64_lock;
532 struct rtnl_link_stats64 stats64;
533
534 /* structs defined in e1000_hw.h */
535 struct e1000_hw hw;
536 struct e1000_hw_stats stats;
537 struct e1000_phy_info phy_info;
538
539 u32 test_icr;
540 struct igb_ring test_tx_ring;
541 struct igb_ring test_rx_ring;
542
543 int msg_enable;
544
545 struct igb_q_vector *q_vector[MAX_Q_VECTORS];
546 u32 eims_enable_mask;
547 u32 eims_other;
548
549 /* to not mess up cache alignment, always add to the bottom */
550 u16 tx_ring_count;
551 u16 rx_ring_count;
552 unsigned int vfs_allocated_count;
553 struct vf_data_storage *vf_data;
554 int vf_rate_link_speed;
555 u32 rss_queues;
556 u32 wvbr;
557 u32 *shadow_vfta;
558
559 struct ptp_clock *ptp_clock;
560 struct ptp_clock_info ptp_caps;
561 struct delayed_work ptp_overflow_work;
562 struct work_struct ptp_tx_work;
563 struct sk_buff *ptp_tx_skb;
564 struct hwtstamp_config tstamp_config;
565 unsigned long ptp_tx_start;
566 unsigned long last_rx_ptp_check;
567 unsigned long last_rx_timestamp;
568 unsigned int ptp_flags;
569 spinlock_t tmreg_lock;
570 struct cyclecounter cc;
571 struct timecounter tc;
572 u32 tx_hwtstamp_timeouts;
573 u32 tx_hwtstamp_skipped;
574 u32 rx_hwtstamp_cleared;
575 bool pps_sys_wrap_on;
576
577 struct ptp_pin_desc sdp_config[IGB_N_SDP];
578 struct {
579 struct timespec64 start;
580 struct timespec64 period;
581 } perout[IGB_N_PEROUT];
582
583 char fw_version[32];
584#ifdef CONFIG_IGB_HWMON
585 struct hwmon_buff *igb_hwmon_buff;
586 bool ets;
587#endif
588 struct i2c_algo_bit_data i2c_algo;
589 struct i2c_adapter i2c_adap;
590 struct i2c_client *i2c_client;
591 u32 rss_indir_tbl_init;
592 u8 rss_indir_tbl[IGB_RETA_SIZE];
593
594 unsigned long link_check_timeout;
595 int copper_tries;
596 struct e1000_info ei;
597 u16 eee_advert;
598
599 /* RX network flow classification support */
600 struct hlist_head nfc_filter_list;
601 unsigned int nfc_filter_count;
602 /* lock for RX network flow classification filter */
603 spinlock_t nfc_lock;
604 bool etype_bitmap[MAX_ETYPE_FILTER];
605
606 struct igb_mac_addr *mac_table;
607 struct vf_mac_filter vf_macs;
608 struct vf_mac_filter *vf_mac_list;
609};
610
611/* flags controlling PTP/1588 function */
612#define IGB_PTP_ENABLED BIT(0)
613#define IGB_PTP_OVERFLOW_CHECK BIT(1)
614
615#define IGB_FLAG_HAS_MSI BIT(0)
616#define IGB_FLAG_DCA_ENABLED BIT(1)
617#define IGB_FLAG_QUAD_PORT_A BIT(2)
618#define IGB_FLAG_QUEUE_PAIRS BIT(3)
619#define IGB_FLAG_DMAC BIT(4)
620#define IGB_FLAG_RSS_FIELD_IPV4_UDP BIT(6)
621#define IGB_FLAG_RSS_FIELD_IPV6_UDP BIT(7)
622#define IGB_FLAG_WOL_SUPPORTED BIT(8)
623#define IGB_FLAG_NEED_LINK_UPDATE BIT(9)
624#define IGB_FLAG_MEDIA_RESET BIT(10)
625#define IGB_FLAG_MAS_CAPABLE BIT(11)
626#define IGB_FLAG_MAS_ENABLE BIT(12)
627#define IGB_FLAG_HAS_MSIX BIT(13)
628#define IGB_FLAG_EEE BIT(14)
629#define IGB_FLAG_VLAN_PROMISC BIT(15)
630#define IGB_FLAG_RX_LEGACY BIT(16)
631#define IGB_FLAG_FQTSS BIT(17)
632
633/* Media Auto Sense */
634#define IGB_MAS_ENABLE_0 0X0001
635#define IGB_MAS_ENABLE_1 0X0002
636#define IGB_MAS_ENABLE_2 0X0004
637#define IGB_MAS_ENABLE_3 0X0008
638
639/* DMA Coalescing defines */
640#define IGB_MIN_TXPBSIZE 20408
641#define IGB_TX_BUF_4096 4096
642#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
643
644#define IGB_82576_TSYNC_SHIFT 19
645enum e1000_state_t {
646 __IGB_TESTING,
647 __IGB_RESETTING,
648 __IGB_DOWN,
649 __IGB_PTP_TX_IN_PROGRESS,
650};
651
652enum igb_boards {
653 board_82575,
654};
655
656extern char igb_driver_name[];
657extern char igb_driver_version[];
658
659int igb_open(struct net_device *netdev);
660int igb_close(struct net_device *netdev);
661int igb_up(struct igb_adapter *);
662void igb_down(struct igb_adapter *);
663void igb_reinit_locked(struct igb_adapter *);
664void igb_reset(struct igb_adapter *);
665int igb_reinit_queues(struct igb_adapter *);
666void igb_write_rss_indir_tbl(struct igb_adapter *);
667int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
668int igb_setup_tx_resources(struct igb_ring *);
669int igb_setup_rx_resources(struct igb_ring *);
670void igb_free_tx_resources(struct igb_ring *);
671void igb_free_rx_resources(struct igb_ring *);
672void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
673void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
674void igb_setup_tctl(struct igb_adapter *);
675void igb_setup_rctl(struct igb_adapter *);
676netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);
677void igb_alloc_rx_buffers(struct igb_ring *, u16);
678void igb_update_stats(struct igb_adapter *);
679bool igb_has_link(struct igb_adapter *adapter);
680void igb_set_ethtool_ops(struct net_device *);
681void igb_power_up_link(struct igb_adapter *);
682void igb_set_fw_version(struct igb_adapter *);
683void igb_ptp_init(struct igb_adapter *adapter);
684void igb_ptp_stop(struct igb_adapter *adapter);
685void igb_ptp_reset(struct igb_adapter *adapter);
686void igb_ptp_suspend(struct igb_adapter *adapter);
687void igb_ptp_rx_hang(struct igb_adapter *adapter);
688void igb_ptp_tx_hang(struct igb_adapter *adapter);
689void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb);
690void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, void *va,
691 struct sk_buff *skb);
692int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
693int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
694void igb_set_flag_queue_pairs(struct igb_adapter *, const u32);
695unsigned int igb_get_max_rss_queues(struct igb_adapter *);
696#ifdef CONFIG_IGB_HWMON
697void igb_sysfs_exit(struct igb_adapter *adapter);
698int igb_sysfs_init(struct igb_adapter *adapter);
699#endif
700static inline s32 igb_reset_phy(struct e1000_hw *hw)
701{
702 if (hw->phy.ops.reset)
703 return hw->phy.ops.reset(hw);
704
705 return 0;
706}
707
708static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
709{
710 if (hw->phy.ops.read_reg)
711 return hw->phy.ops.read_reg(hw, offset, data);
712
713 return 0;
714}
715
716static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
717{
718 if (hw->phy.ops.write_reg)
719 return hw->phy.ops.write_reg(hw, offset, data);
720
721 return 0;
722}
723
724static inline s32 igb_get_phy_info(struct e1000_hw *hw)
725{
726 if (hw->phy.ops.get_phy_info)
727 return hw->phy.ops.get_phy_info(hw);
728
729 return 0;
730}
731
732static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring)
733{
734 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
735}
736
737int igb_add_filter(struct igb_adapter *adapter,
738 struct igb_nfc_filter *input);
739int igb_erase_filter(struct igb_adapter *adapter,
740 struct igb_nfc_filter *input);
741
742#endif /* _IGB_H_ */
1/* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
23
24/* Linux PRO/1000 Ethernet Driver main header file */
25
26#ifndef _IGB_H_
27#define _IGB_H_
28
29#include "e1000_mac.h"
30#include "e1000_82575.h"
31
32#include <linux/timecounter.h>
33#include <linux/net_tstamp.h>
34#include <linux/ptp_clock_kernel.h>
35#include <linux/bitops.h>
36#include <linux/if_vlan.h>
37#include <linux/i2c.h>
38#include <linux/i2c-algo-bit.h>
39#include <linux/pci.h>
40#include <linux/mdio.h>
41
42struct igb_adapter;
43
44#define E1000_PCS_CFG_IGN_SD 1
45
46/* Interrupt defines */
47#define IGB_START_ITR 648 /* ~6000 ints/sec */
48#define IGB_4K_ITR 980
49#define IGB_20K_ITR 196
50#define IGB_70K_ITR 56
51
52/* TX/RX descriptor defines */
53#define IGB_DEFAULT_TXD 256
54#define IGB_DEFAULT_TX_WORK 128
55#define IGB_MIN_TXD 80
56#define IGB_MAX_TXD 4096
57
58#define IGB_DEFAULT_RXD 256
59#define IGB_MIN_RXD 80
60#define IGB_MAX_RXD 4096
61
62#define IGB_DEFAULT_ITR 3 /* dynamic */
63#define IGB_MAX_ITR_USECS 10000
64#define IGB_MIN_ITR_USECS 10
65#define NON_Q_VECTORS 1
66#define MAX_Q_VECTORS 8
67#define MAX_MSIX_ENTRIES 10
68
69/* Transmit and receive queues */
70#define IGB_MAX_RX_QUEUES 8
71#define IGB_MAX_RX_QUEUES_82575 4
72#define IGB_MAX_RX_QUEUES_I211 2
73#define IGB_MAX_TX_QUEUES 8
74#define IGB_MAX_VF_MC_ENTRIES 30
75#define IGB_MAX_VF_FUNCTIONS 8
76#define IGB_MAX_VFTA_ENTRIES 128
77#define IGB_82576_VF_DEV_ID 0x10CA
78#define IGB_I350_VF_DEV_ID 0x1520
79
80/* NVM version defines */
81#define IGB_MAJOR_MASK 0xF000
82#define IGB_MINOR_MASK 0x0FF0
83#define IGB_BUILD_MASK 0x000F
84#define IGB_COMB_VER_MASK 0x00FF
85#define IGB_MAJOR_SHIFT 12
86#define IGB_MINOR_SHIFT 4
87#define IGB_COMB_VER_SHFT 8
88#define IGB_NVM_VER_INVALID 0xFFFF
89#define IGB_ETRACK_SHIFT 16
90#define NVM_ETRACK_WORD 0x0042
91#define NVM_COMB_VER_OFF 0x0083
92#define NVM_COMB_VER_PTR 0x003d
93
94/* Transmit and receive latency (for PTP timestamps) */
95#define IGB_I210_TX_LATENCY_10 9542
96#define IGB_I210_TX_LATENCY_100 1024
97#define IGB_I210_TX_LATENCY_1000 178
98#define IGB_I210_RX_LATENCY_10 20662
99#define IGB_I210_RX_LATENCY_100 2213
100#define IGB_I210_RX_LATENCY_1000 448
101
102struct vf_data_storage {
103 unsigned char vf_mac_addresses[ETH_ALEN];
104 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
105 u16 num_vf_mc_hashes;
106 u32 flags;
107 unsigned long last_nack;
108 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
109 u16 pf_qos;
110 u16 tx_rate;
111 bool spoofchk_enabled;
112};
113
114#define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
115#define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
116#define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
117#define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
118
119/* RX descriptor control thresholds.
120 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
121 * descriptors available in its onboard memory.
122 * Setting this to 0 disables RX descriptor prefetch.
123 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
124 * available in host memory.
125 * If PTHRESH is 0, this should also be 0.
126 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
127 * descriptors until either it has this many to write back, or the
128 * ITR timer expires.
129 */
130#define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
131#define IGB_RX_HTHRESH 8
132#define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
133#define IGB_TX_HTHRESH 1
134#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
135 (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 4)
136#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
137 (adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 16)
138
139/* this is the size past which hardware will drop packets when setting LPE=0 */
140#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
141
142/* Supported Rx Buffer Sizes */
143#define IGB_RXBUFFER_256 256
144#define IGB_RXBUFFER_2048 2048
145#define IGB_RX_HDR_LEN IGB_RXBUFFER_256
146#define IGB_RX_BUFSZ IGB_RXBUFFER_2048
147
148/* How many Rx Buffers do we bundle into one write to the hardware ? */
149#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
150
151#define AUTO_ALL_MODES 0
152#define IGB_EEPROM_APME 0x0400
153
154#ifndef IGB_MASTER_SLAVE
155/* Switch to override PHY master/slave setting */
156#define IGB_MASTER_SLAVE e1000_ms_hw_default
157#endif
158
159#define IGB_MNG_VLAN_NONE -1
160
161enum igb_tx_flags {
162 /* cmd_type flags */
163 IGB_TX_FLAGS_VLAN = 0x01,
164 IGB_TX_FLAGS_TSO = 0x02,
165 IGB_TX_FLAGS_TSTAMP = 0x04,
166
167 /* olinfo flags */
168 IGB_TX_FLAGS_IPV4 = 0x10,
169 IGB_TX_FLAGS_CSUM = 0x20,
170};
171
172/* VLAN info */
173#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
174#define IGB_TX_FLAGS_VLAN_SHIFT 16
175
176/* The largest size we can write to the descriptor is 65535. In order to
177 * maintain a power of two alignment we have to limit ourselves to 32K.
178 */
179#define IGB_MAX_TXD_PWR 15
180#define IGB_MAX_DATA_PER_TXD (1u << IGB_MAX_TXD_PWR)
181
182/* Tx Descriptors needed, worst case */
183#define TXD_USE_COUNT(S) DIV_ROUND_UP((S), IGB_MAX_DATA_PER_TXD)
184#define DESC_NEEDED (MAX_SKB_FRAGS + 4)
185
186/* EEPROM byte offsets */
187#define IGB_SFF_8472_SWAP 0x5C
188#define IGB_SFF_8472_COMP 0x5E
189
190/* Bitmasks */
191#define IGB_SFF_ADDRESSING_MODE 0x4
192#define IGB_SFF_8472_UNSUP 0x00
193
194/* wrapper around a pointer to a socket buffer,
195 * so a DMA handle can be stored along with the buffer
196 */
197struct igb_tx_buffer {
198 union e1000_adv_tx_desc *next_to_watch;
199 unsigned long time_stamp;
200 struct sk_buff *skb;
201 unsigned int bytecount;
202 u16 gso_segs;
203 __be16 protocol;
204
205 DEFINE_DMA_UNMAP_ADDR(dma);
206 DEFINE_DMA_UNMAP_LEN(len);
207 u32 tx_flags;
208};
209
210struct igb_rx_buffer {
211 dma_addr_t dma;
212 struct page *page;
213#if (BITS_PER_LONG > 32) || (PAGE_SIZE >= 65536)
214 __u32 page_offset;
215#else
216 __u16 page_offset;
217#endif
218 __u16 pagecnt_bias;
219};
220
221struct igb_tx_queue_stats {
222 u64 packets;
223 u64 bytes;
224 u64 restart_queue;
225 u64 restart_queue2;
226};
227
228struct igb_rx_queue_stats {
229 u64 packets;
230 u64 bytes;
231 u64 drops;
232 u64 csum_err;
233 u64 alloc_failed;
234};
235
236struct igb_ring_container {
237 struct igb_ring *ring; /* pointer to linked list of rings */
238 unsigned int total_bytes; /* total bytes processed this int */
239 unsigned int total_packets; /* total packets processed this int */
240 u16 work_limit; /* total work allowed per interrupt */
241 u8 count; /* total number of rings in vector */
242 u8 itr; /* current ITR setting for ring */
243};
244
245struct igb_ring {
246 struct igb_q_vector *q_vector; /* backlink to q_vector */
247 struct net_device *netdev; /* back pointer to net_device */
248 struct device *dev; /* device pointer for dma mapping */
249 union { /* array of buffer info structs */
250 struct igb_tx_buffer *tx_buffer_info;
251 struct igb_rx_buffer *rx_buffer_info;
252 };
253 void *desc; /* descriptor ring memory */
254 unsigned long flags; /* ring specific flags */
255 void __iomem *tail; /* pointer to ring tail register */
256 dma_addr_t dma; /* phys address of the ring */
257 unsigned int size; /* length of desc. ring in bytes */
258
259 u16 count; /* number of desc. in the ring */
260 u8 queue_index; /* logical index of the ring*/
261 u8 reg_idx; /* physical index of the ring */
262
263 /* everything past this point are written often */
264 u16 next_to_clean;
265 u16 next_to_use;
266 u16 next_to_alloc;
267
268 union {
269 /* TX */
270 struct {
271 struct igb_tx_queue_stats tx_stats;
272 struct u64_stats_sync tx_syncp;
273 struct u64_stats_sync tx_syncp2;
274 };
275 /* RX */
276 struct {
277 struct sk_buff *skb;
278 struct igb_rx_queue_stats rx_stats;
279 struct u64_stats_sync rx_syncp;
280 };
281 };
282} ____cacheline_internodealigned_in_smp;
283
284struct igb_q_vector {
285 struct igb_adapter *adapter; /* backlink */
286 int cpu; /* CPU for DCA */
287 u32 eims_value; /* EIMS mask value */
288
289 u16 itr_val;
290 u8 set_itr;
291 void __iomem *itr_register;
292
293 struct igb_ring_container rx, tx;
294
295 struct napi_struct napi;
296 struct rcu_head rcu; /* to avoid race with update stats on free */
297 char name[IFNAMSIZ + 9];
298
299 /* for dynamic allocation of rings associated with this q_vector */
300 struct igb_ring ring[0] ____cacheline_internodealigned_in_smp;
301};
302
303enum e1000_ring_flags_t {
304 IGB_RING_FLAG_RX_SCTP_CSUM,
305 IGB_RING_FLAG_RX_LB_VLAN_BSWAP,
306 IGB_RING_FLAG_TX_CTX_IDX,
307 IGB_RING_FLAG_TX_DETECT_HANG
308};
309
310#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
311
312#define IGB_RX_DESC(R, i) \
313 (&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
314#define IGB_TX_DESC(R, i) \
315 (&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
316#define IGB_TX_CTXTDESC(R, i) \
317 (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
318
319/* igb_test_staterr - tests bits within Rx descriptor status and error fields */
320static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc,
321 const u32 stat_err_bits)
322{
323 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
324}
325
326/* igb_desc_unused - calculate if we have unused descriptors */
327static inline int igb_desc_unused(struct igb_ring *ring)
328{
329 if (ring->next_to_clean > ring->next_to_use)
330 return ring->next_to_clean - ring->next_to_use - 1;
331
332 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
333}
334
335#ifdef CONFIG_IGB_HWMON
336
337#define IGB_HWMON_TYPE_LOC 0
338#define IGB_HWMON_TYPE_TEMP 1
339#define IGB_HWMON_TYPE_CAUTION 2
340#define IGB_HWMON_TYPE_MAX 3
341
342struct hwmon_attr {
343 struct device_attribute dev_attr;
344 struct e1000_hw *hw;
345 struct e1000_thermal_diode_data *sensor;
346 char name[12];
347 };
348
349struct hwmon_buff {
350 struct attribute_group group;
351 const struct attribute_group *groups[2];
352 struct attribute *attrs[E1000_MAX_SENSORS * 4 + 1];
353 struct hwmon_attr hwmon_list[E1000_MAX_SENSORS * 4];
354 unsigned int n_hwmon;
355 };
356#endif
357
358/* The number of L2 ether-type filter registers, Index 3 is reserved
359 * for PTP 1588 timestamp
360 */
361#define MAX_ETYPE_FILTER (4 - 1)
362/* ETQF filter list: one static filter per filter consumer. This is
363 * to avoid filter collisions later. Add new filters here!!
364 *
365 * Current filters: Filter 3
366 */
367#define IGB_ETQF_FILTER_1588 3
368
369#define IGB_N_EXTTS 2
370#define IGB_N_PEROUT 2
371#define IGB_N_SDP 4
372#define IGB_RETA_SIZE 128
373
374enum igb_filter_match_flags {
375 IGB_FILTER_FLAG_ETHER_TYPE = 0x1,
376 IGB_FILTER_FLAG_VLAN_TCI = 0x2,
377};
378
379#define IGB_MAX_RXNFC_FILTERS 16
380
381/* RX network flow classification data structure */
382struct igb_nfc_input {
383 /* Byte layout in order, all values with MSB first:
384 * match_flags - 1 byte
385 * etype - 2 bytes
386 * vlan_tci - 2 bytes
387 */
388 u8 match_flags;
389 __be16 etype;
390 __be16 vlan_tci;
391};
392
393struct igb_nfc_filter {
394 struct hlist_node nfc_node;
395 struct igb_nfc_input filter;
396 u16 etype_reg_index;
397 u16 sw_idx;
398 u16 action;
399};
400
401/* board specific private data structure */
402struct igb_adapter {
403 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
404
405 struct net_device *netdev;
406
407 unsigned long state;
408 unsigned int flags;
409
410 unsigned int num_q_vectors;
411 struct msix_entry msix_entries[MAX_MSIX_ENTRIES];
412
413 /* Interrupt Throttle Rate */
414 u32 rx_itr_setting;
415 u32 tx_itr_setting;
416 u16 tx_itr;
417 u16 rx_itr;
418
419 /* TX */
420 u16 tx_work_limit;
421 u32 tx_timeout_count;
422 int num_tx_queues;
423 struct igb_ring *tx_ring[16];
424
425 /* RX */
426 int num_rx_queues;
427 struct igb_ring *rx_ring[16];
428
429 u32 max_frame_size;
430 u32 min_frame_size;
431
432 struct timer_list watchdog_timer;
433 struct timer_list phy_info_timer;
434
435 u16 mng_vlan_id;
436 u32 bd_number;
437 u32 wol;
438 u32 en_mng_pt;
439 u16 link_speed;
440 u16 link_duplex;
441
442 u8 __iomem *io_addr; /* Mainly for iounmap use */
443
444 struct work_struct reset_task;
445 struct work_struct watchdog_task;
446 bool fc_autoneg;
447 u8 tx_timeout_factor;
448 struct timer_list blink_timer;
449 unsigned long led_status;
450
451 /* OS defined structs */
452 struct pci_dev *pdev;
453
454 spinlock_t stats64_lock;
455 struct rtnl_link_stats64 stats64;
456
457 /* structs defined in e1000_hw.h */
458 struct e1000_hw hw;
459 struct e1000_hw_stats stats;
460 struct e1000_phy_info phy_info;
461
462 u32 test_icr;
463 struct igb_ring test_tx_ring;
464 struct igb_ring test_rx_ring;
465
466 int msg_enable;
467
468 struct igb_q_vector *q_vector[MAX_Q_VECTORS];
469 u32 eims_enable_mask;
470 u32 eims_other;
471
472 /* to not mess up cache alignment, always add to the bottom */
473 u16 tx_ring_count;
474 u16 rx_ring_count;
475 unsigned int vfs_allocated_count;
476 struct vf_data_storage *vf_data;
477 int vf_rate_link_speed;
478 u32 rss_queues;
479 u32 wvbr;
480 u32 *shadow_vfta;
481
482 struct ptp_clock *ptp_clock;
483 struct ptp_clock_info ptp_caps;
484 struct delayed_work ptp_overflow_work;
485 struct work_struct ptp_tx_work;
486 struct sk_buff *ptp_tx_skb;
487 struct hwtstamp_config tstamp_config;
488 unsigned long ptp_tx_start;
489 unsigned long last_rx_ptp_check;
490 unsigned long last_rx_timestamp;
491 unsigned int ptp_flags;
492 spinlock_t tmreg_lock;
493 struct cyclecounter cc;
494 struct timecounter tc;
495 u32 tx_hwtstamp_timeouts;
496 u32 rx_hwtstamp_cleared;
497 bool pps_sys_wrap_on;
498
499 struct ptp_pin_desc sdp_config[IGB_N_SDP];
500 struct {
501 struct timespec64 start;
502 struct timespec64 period;
503 } perout[IGB_N_PEROUT];
504
505 char fw_version[32];
506#ifdef CONFIG_IGB_HWMON
507 struct hwmon_buff *igb_hwmon_buff;
508 bool ets;
509#endif
510 struct i2c_algo_bit_data i2c_algo;
511 struct i2c_adapter i2c_adap;
512 struct i2c_client *i2c_client;
513 u32 rss_indir_tbl_init;
514 u8 rss_indir_tbl[IGB_RETA_SIZE];
515
516 unsigned long link_check_timeout;
517 int copper_tries;
518 struct e1000_info ei;
519 u16 eee_advert;
520
521 /* RX network flow classification support */
522 struct hlist_head nfc_filter_list;
523 unsigned int nfc_filter_count;
524 /* lock for RX network flow classification filter */
525 spinlock_t nfc_lock;
526 bool etype_bitmap[MAX_ETYPE_FILTER];
527};
528
529/* flags controlling PTP/1588 function */
530#define IGB_PTP_ENABLED BIT(0)
531#define IGB_PTP_OVERFLOW_CHECK BIT(1)
532
533#define IGB_FLAG_HAS_MSI BIT(0)
534#define IGB_FLAG_DCA_ENABLED BIT(1)
535#define IGB_FLAG_QUAD_PORT_A BIT(2)
536#define IGB_FLAG_QUEUE_PAIRS BIT(3)
537#define IGB_FLAG_DMAC BIT(4)
538#define IGB_FLAG_RSS_FIELD_IPV4_UDP BIT(6)
539#define IGB_FLAG_RSS_FIELD_IPV6_UDP BIT(7)
540#define IGB_FLAG_WOL_SUPPORTED BIT(8)
541#define IGB_FLAG_NEED_LINK_UPDATE BIT(9)
542#define IGB_FLAG_MEDIA_RESET BIT(10)
543#define IGB_FLAG_MAS_CAPABLE BIT(11)
544#define IGB_FLAG_MAS_ENABLE BIT(12)
545#define IGB_FLAG_HAS_MSIX BIT(13)
546#define IGB_FLAG_EEE BIT(14)
547#define IGB_FLAG_VLAN_PROMISC BIT(15)
548
549/* Media Auto Sense */
550#define IGB_MAS_ENABLE_0 0X0001
551#define IGB_MAS_ENABLE_1 0X0002
552#define IGB_MAS_ENABLE_2 0X0004
553#define IGB_MAS_ENABLE_3 0X0008
554
555/* DMA Coalescing defines */
556#define IGB_MIN_TXPBSIZE 20408
557#define IGB_TX_BUF_4096 4096
558#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
559
560#define IGB_82576_TSYNC_SHIFT 19
561#define IGB_TS_HDR_LEN 16
562enum e1000_state_t {
563 __IGB_TESTING,
564 __IGB_RESETTING,
565 __IGB_DOWN,
566 __IGB_PTP_TX_IN_PROGRESS,
567};
568
569enum igb_boards {
570 board_82575,
571};
572
573extern char igb_driver_name[];
574extern char igb_driver_version[];
575
576int igb_open(struct net_device *netdev);
577int igb_close(struct net_device *netdev);
578int igb_up(struct igb_adapter *);
579void igb_down(struct igb_adapter *);
580void igb_reinit_locked(struct igb_adapter *);
581void igb_reset(struct igb_adapter *);
582int igb_reinit_queues(struct igb_adapter *);
583void igb_write_rss_indir_tbl(struct igb_adapter *);
584int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
585int igb_setup_tx_resources(struct igb_ring *);
586int igb_setup_rx_resources(struct igb_ring *);
587void igb_free_tx_resources(struct igb_ring *);
588void igb_free_rx_resources(struct igb_ring *);
589void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
590void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
591void igb_setup_tctl(struct igb_adapter *);
592void igb_setup_rctl(struct igb_adapter *);
593netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);
594void igb_unmap_and_free_tx_resource(struct igb_ring *, struct igb_tx_buffer *);
595void igb_alloc_rx_buffers(struct igb_ring *, u16);
596void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
597bool igb_has_link(struct igb_adapter *adapter);
598void igb_set_ethtool_ops(struct net_device *);
599void igb_power_up_link(struct igb_adapter *);
600void igb_set_fw_version(struct igb_adapter *);
601void igb_ptp_init(struct igb_adapter *adapter);
602void igb_ptp_stop(struct igb_adapter *adapter);
603void igb_ptp_reset(struct igb_adapter *adapter);
604void igb_ptp_suspend(struct igb_adapter *adapter);
605void igb_ptp_rx_hang(struct igb_adapter *adapter);
606void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb);
607void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, unsigned char *va,
608 struct sk_buff *skb);
609int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr);
610int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr);
611void igb_set_flag_queue_pairs(struct igb_adapter *, const u32);
612#ifdef CONFIG_IGB_HWMON
613void igb_sysfs_exit(struct igb_adapter *adapter);
614int igb_sysfs_init(struct igb_adapter *adapter);
615#endif
616static inline s32 igb_reset_phy(struct e1000_hw *hw)
617{
618 if (hw->phy.ops.reset)
619 return hw->phy.ops.reset(hw);
620
621 return 0;
622}
623
624static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
625{
626 if (hw->phy.ops.read_reg)
627 return hw->phy.ops.read_reg(hw, offset, data);
628
629 return 0;
630}
631
632static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
633{
634 if (hw->phy.ops.write_reg)
635 return hw->phy.ops.write_reg(hw, offset, data);
636
637 return 0;
638}
639
640static inline s32 igb_get_phy_info(struct e1000_hw *hw)
641{
642 if (hw->phy.ops.get_phy_info)
643 return hw->phy.ops.get_phy_info(hw);
644
645 return 0;
646}
647
648static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring)
649{
650 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
651}
652
653int igb_add_filter(struct igb_adapter *adapter,
654 struct igb_nfc_filter *input);
655int igb_erase_filter(struct igb_adapter *adapter,
656 struct igb_nfc_filter *input);
657
658#endif /* _IGB_H_ */