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1/*******************************************************************************
2
3 Intel(R) Gigabit Ethernet Linux driver
4 Copyright(c) 2007-2012 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28
29/* Linux PRO/1000 Ethernet Driver main header file */
30
31#ifndef _IGB_H_
32#define _IGB_H_
33
34#include "e1000_mac.h"
35#include "e1000_82575.h"
36
37#include <linux/clocksource.h>
38#include <linux/net_tstamp.h>
39#include <linux/ptp_clock_kernel.h>
40#include <linux/bitops.h>
41#include <linux/if_vlan.h>
42
43struct igb_adapter;
44
45/* Interrupt defines */
46#define IGB_START_ITR 648 /* ~6000 ints/sec */
47#define IGB_4K_ITR 980
48#define IGB_20K_ITR 196
49#define IGB_70K_ITR 56
50
51/* TX/RX descriptor defines */
52#define IGB_DEFAULT_TXD 256
53#define IGB_DEFAULT_TX_WORK 128
54#define IGB_MIN_TXD 80
55#define IGB_MAX_TXD 4096
56
57#define IGB_DEFAULT_RXD 256
58#define IGB_MIN_RXD 80
59#define IGB_MAX_RXD 4096
60
61#define IGB_DEFAULT_ITR 3 /* dynamic */
62#define IGB_MAX_ITR_USECS 10000
63#define IGB_MIN_ITR_USECS 10
64#define NON_Q_VECTORS 1
65#define MAX_Q_VECTORS 8
66
67/* Transmit and receive queues */
68#define IGB_MAX_RX_QUEUES ((adapter->vfs_allocated_count ? 2 : \
69 (hw->mac.type > e1000_82575 ? 8 : 4)))
70#define IGB_MAX_RX_QUEUES_I210 4
71#define IGB_MAX_RX_QUEUES_I211 2
72#define IGB_MAX_TX_QUEUES 16
73#define IGB_MAX_TX_QUEUES_I210 4
74#define IGB_MAX_TX_QUEUES_I211 2
75#define IGB_MAX_VF_MC_ENTRIES 30
76#define IGB_MAX_VF_FUNCTIONS 8
77#define IGB_MAX_VFTA_ENTRIES 128
78#define IGB_82576_VF_DEV_ID 0x10CA
79#define IGB_I350_VF_DEV_ID 0x1520
80
81struct vf_data_storage {
82 unsigned char vf_mac_addresses[ETH_ALEN];
83 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
84 u16 num_vf_mc_hashes;
85 u16 vlans_enabled;
86 u32 flags;
87 unsigned long last_nack;
88 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
89 u16 pf_qos;
90 u16 tx_rate;
91 struct pci_dev *vfdev;
92};
93
94#define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
95#define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
96#define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
97#define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
98
99/* RX descriptor control thresholds.
100 * PTHRESH - MAC will consider prefetch if it has fewer than this number of
101 * descriptors available in its onboard memory.
102 * Setting this to 0 disables RX descriptor prefetch.
103 * HTHRESH - MAC will only prefetch if there are at least this many descriptors
104 * available in host memory.
105 * If PTHRESH is 0, this should also be 0.
106 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
107 * descriptors until either it has this many to write back, or the
108 * ITR timer expires.
109 */
110#define IGB_RX_PTHRESH 8
111#define IGB_RX_HTHRESH 8
112#define IGB_TX_PTHRESH 8
113#define IGB_TX_HTHRESH 1
114#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
115 adapter->msix_entries) ? 1 : 4)
116#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
117 adapter->msix_entries) ? 1 : 16)
118
119/* this is the size past which hardware will drop packets when setting LPE=0 */
120#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
121
122/* Supported Rx Buffer Sizes */
123#define IGB_RXBUFFER_512 512
124#define IGB_RXBUFFER_16384 16384
125#define IGB_RX_HDR_LEN IGB_RXBUFFER_512
126
127/* How many Tx Descriptors do we need to call netif_wake_queue ? */
128#define IGB_TX_QUEUE_WAKE 16
129/* How many Rx Buffers do we bundle into one write to the hardware ? */
130#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */
131
132#define AUTO_ALL_MODES 0
133#define IGB_EEPROM_APME 0x0400
134
135#ifndef IGB_MASTER_SLAVE
136/* Switch to override PHY master/slave setting */
137#define IGB_MASTER_SLAVE e1000_ms_hw_default
138#endif
139
140#define IGB_MNG_VLAN_NONE -1
141
142#define IGB_TX_FLAGS_CSUM 0x00000001
143#define IGB_TX_FLAGS_VLAN 0x00000002
144#define IGB_TX_FLAGS_TSO 0x00000004
145#define IGB_TX_FLAGS_IPV4 0x00000008
146#define IGB_TX_FLAGS_TSTAMP 0x00000010
147#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000
148#define IGB_TX_FLAGS_VLAN_SHIFT 16
149
150/* wrapper around a pointer to a socket buffer,
151 * so a DMA handle can be stored along with the buffer */
152struct igb_tx_buffer {
153 union e1000_adv_tx_desc *next_to_watch;
154 unsigned long time_stamp;
155 struct sk_buff *skb;
156 unsigned int bytecount;
157 u16 gso_segs;
158 __be16 protocol;
159 dma_addr_t dma;
160 u32 length;
161 u32 tx_flags;
162};
163
164struct igb_rx_buffer {
165 struct sk_buff *skb;
166 dma_addr_t dma;
167 struct page *page;
168 dma_addr_t page_dma;
169 u32 page_offset;
170};
171
172struct igb_tx_queue_stats {
173 u64 packets;
174 u64 bytes;
175 u64 restart_queue;
176 u64 restart_queue2;
177};
178
179struct igb_rx_queue_stats {
180 u64 packets;
181 u64 bytes;
182 u64 drops;
183 u64 csum_err;
184 u64 alloc_failed;
185};
186
187struct igb_ring_container {
188 struct igb_ring *ring; /* pointer to linked list of rings */
189 unsigned int total_bytes; /* total bytes processed this int */
190 unsigned int total_packets; /* total packets processed this int */
191 u16 work_limit; /* total work allowed per interrupt */
192 u8 count; /* total number of rings in vector */
193 u8 itr; /* current ITR setting for ring */
194};
195
196struct igb_q_vector {
197 struct igb_adapter *adapter; /* backlink */
198 int cpu; /* CPU for DCA */
199 u32 eims_value; /* EIMS mask value */
200
201 struct igb_ring_container rx, tx;
202
203 struct napi_struct napi;
204 int numa_node;
205
206 u16 itr_val;
207 u8 set_itr;
208 void __iomem *itr_register;
209
210 char name[IFNAMSIZ + 9];
211};
212
213struct igb_ring {
214 struct igb_q_vector *q_vector; /* backlink to q_vector */
215 struct net_device *netdev; /* back pointer to net_device */
216 struct device *dev; /* device pointer for dma mapping */
217 union { /* array of buffer info structs */
218 struct igb_tx_buffer *tx_buffer_info;
219 struct igb_rx_buffer *rx_buffer_info;
220 };
221 void *desc; /* descriptor ring memory */
222 unsigned long flags; /* ring specific flags */
223 void __iomem *tail; /* pointer to ring tail register */
224
225 u16 count; /* number of desc. in the ring */
226 u8 queue_index; /* logical index of the ring*/
227 u8 reg_idx; /* physical index of the ring */
228 u32 size; /* length of desc. ring in bytes */
229
230 /* everything past this point are written often */
231 u16 next_to_clean ____cacheline_aligned_in_smp;
232 u16 next_to_use;
233
234 union {
235 /* TX */
236 struct {
237 struct igb_tx_queue_stats tx_stats;
238 struct u64_stats_sync tx_syncp;
239 struct u64_stats_sync tx_syncp2;
240 };
241 /* RX */
242 struct {
243 struct igb_rx_queue_stats rx_stats;
244 struct u64_stats_sync rx_syncp;
245 };
246 };
247 /* Items past this point are only used during ring alloc / free */
248 dma_addr_t dma; /* phys address of the ring */
249 int numa_node; /* node to alloc ring memory on */
250};
251
252enum e1000_ring_flags_t {
253 IGB_RING_FLAG_RX_SCTP_CSUM,
254 IGB_RING_FLAG_RX_LB_VLAN_BSWAP,
255 IGB_RING_FLAG_TX_CTX_IDX,
256 IGB_RING_FLAG_TX_DETECT_HANG
257};
258
259#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS)
260
261#define IGB_RX_DESC(R, i) \
262 (&(((union e1000_adv_rx_desc *)((R)->desc))[i]))
263#define IGB_TX_DESC(R, i) \
264 (&(((union e1000_adv_tx_desc *)((R)->desc))[i]))
265#define IGB_TX_CTXTDESC(R, i) \
266 (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i]))
267
268/* igb_test_staterr - tests bits within Rx descriptor status and error fields */
269static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc,
270 const u32 stat_err_bits)
271{
272 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits);
273}
274
275/* igb_desc_unused - calculate if we have unused descriptors */
276static inline int igb_desc_unused(struct igb_ring *ring)
277{
278 if (ring->next_to_clean > ring->next_to_use)
279 return ring->next_to_clean - ring->next_to_use - 1;
280
281 return ring->count + ring->next_to_clean - ring->next_to_use - 1;
282}
283
284/* board specific private data structure */
285struct igb_adapter {
286 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
287
288 struct net_device *netdev;
289
290 unsigned long state;
291 unsigned int flags;
292
293 unsigned int num_q_vectors;
294 struct msix_entry *msix_entries;
295
296 /* Interrupt Throttle Rate */
297 u32 rx_itr_setting;
298 u32 tx_itr_setting;
299 u16 tx_itr;
300 u16 rx_itr;
301
302 /* TX */
303 u16 tx_work_limit;
304 u32 tx_timeout_count;
305 int num_tx_queues;
306 struct igb_ring *tx_ring[16];
307
308 /* RX */
309 int num_rx_queues;
310 struct igb_ring *rx_ring[16];
311
312 u32 max_frame_size;
313 u32 min_frame_size;
314
315 struct timer_list watchdog_timer;
316 struct timer_list phy_info_timer;
317
318 u16 mng_vlan_id;
319 u32 bd_number;
320 u32 wol;
321 u32 en_mng_pt;
322 u16 link_speed;
323 u16 link_duplex;
324
325 struct work_struct reset_task;
326 struct work_struct watchdog_task;
327 bool fc_autoneg;
328 u8 tx_timeout_factor;
329 struct timer_list blink_timer;
330 unsigned long led_status;
331
332 /* OS defined structs */
333 struct pci_dev *pdev;
334 struct hwtstamp_config hwtstamp_config;
335
336 spinlock_t stats64_lock;
337 struct rtnl_link_stats64 stats64;
338
339 /* structs defined in e1000_hw.h */
340 struct e1000_hw hw;
341 struct e1000_hw_stats stats;
342 struct e1000_phy_info phy_info;
343 struct e1000_phy_stats phy_stats;
344
345 u32 test_icr;
346 struct igb_ring test_tx_ring;
347 struct igb_ring test_rx_ring;
348
349 int msg_enable;
350
351 struct igb_q_vector *q_vector[MAX_Q_VECTORS];
352 u32 eims_enable_mask;
353 u32 eims_other;
354
355 /* to not mess up cache alignment, always add to the bottom */
356 u32 eeprom_wol;
357
358 u16 tx_ring_count;
359 u16 rx_ring_count;
360 unsigned int vfs_allocated_count;
361 struct vf_data_storage *vf_data;
362 int vf_rate_link_speed;
363 u32 rss_queues;
364 u32 wvbr;
365 int node;
366 u32 *shadow_vfta;
367
368 struct ptp_clock *ptp_clock;
369 struct ptp_clock_info caps;
370 struct delayed_work overflow_work;
371 spinlock_t tmreg_lock;
372 struct cyclecounter cc;
373 struct timecounter tc;
374};
375
376#define IGB_FLAG_HAS_MSI (1 << 0)
377#define IGB_FLAG_DCA_ENABLED (1 << 1)
378#define IGB_FLAG_QUAD_PORT_A (1 << 2)
379#define IGB_FLAG_QUEUE_PAIRS (1 << 3)
380#define IGB_FLAG_DMAC (1 << 4)
381
382/* DMA Coalescing defines */
383#define IGB_MIN_TXPBSIZE 20408
384#define IGB_TX_BUF_4096 4096
385#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */
386
387#define IGB_82576_TSYNC_SHIFT 19
388#define IGB_TS_HDR_LEN 16
389enum e1000_state_t {
390 __IGB_TESTING,
391 __IGB_RESETTING,
392 __IGB_DOWN
393};
394
395enum igb_boards {
396 board_82575,
397};
398
399extern char igb_driver_name[];
400extern char igb_driver_version[];
401
402extern int igb_up(struct igb_adapter *);
403extern void igb_down(struct igb_adapter *);
404extern void igb_reinit_locked(struct igb_adapter *);
405extern void igb_reset(struct igb_adapter *);
406extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8);
407extern int igb_setup_tx_resources(struct igb_ring *);
408extern int igb_setup_rx_resources(struct igb_ring *);
409extern void igb_free_tx_resources(struct igb_ring *);
410extern void igb_free_rx_resources(struct igb_ring *);
411extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *);
412extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *);
413extern void igb_setup_tctl(struct igb_adapter *);
414extern void igb_setup_rctl(struct igb_adapter *);
415extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *);
416extern void igb_unmap_and_free_tx_resource(struct igb_ring *,
417 struct igb_tx_buffer *);
418extern void igb_alloc_rx_buffers(struct igb_ring *, u16);
419extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *);
420extern bool igb_has_link(struct igb_adapter *adapter);
421extern void igb_set_ethtool_ops(struct net_device *);
422extern void igb_power_up_link(struct igb_adapter *);
423#ifdef CONFIG_IGB_PTP
424extern void igb_ptp_init(struct igb_adapter *adapter);
425extern void igb_ptp_remove(struct igb_adapter *adapter);
426
427extern void igb_systim_to_hwtstamp(struct igb_adapter *adapter,
428 struct skb_shared_hwtstamps *hwtstamps,
429 u64 systim);
430
431#endif
432static inline s32 igb_reset_phy(struct e1000_hw *hw)
433{
434 if (hw->phy.ops.reset)
435 return hw->phy.ops.reset(hw);
436
437 return 0;
438}
439
440static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data)
441{
442 if (hw->phy.ops.read_reg)
443 return hw->phy.ops.read_reg(hw, offset, data);
444
445 return 0;
446}
447
448static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data)
449{
450 if (hw->phy.ops.write_reg)
451 return hw->phy.ops.write_reg(hw, offset, data);
452
453 return 0;
454}
455
456static inline s32 igb_get_phy_info(struct e1000_hw *hw)
457{
458 if (hw->phy.ops.get_phy_info)
459 return hw->phy.ops.get_phy_info(hw);
460
461 return 0;
462}
463
464static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring)
465{
466 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
467}
468
469#endif /* _IGB_H_ */