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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * arch/sparc64/mm/init.c
4 *
5 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
6 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
7 */
8
9#include <linux/extable.h>
10#include <linux/kernel.h>
11#include <linux/sched.h>
12#include <linux/string.h>
13#include <linux/init.h>
14#include <linux/bootmem.h>
15#include <linux/mm.h>
16#include <linux/hugetlb.h>
17#include <linux/initrd.h>
18#include <linux/swap.h>
19#include <linux/pagemap.h>
20#include <linux/poison.h>
21#include <linux/fs.h>
22#include <linux/seq_file.h>
23#include <linux/kprobes.h>
24#include <linux/cache.h>
25#include <linux/sort.h>
26#include <linux/ioport.h>
27#include <linux/percpu.h>
28#include <linux/memblock.h>
29#include <linux/mmzone.h>
30#include <linux/gfp.h>
31
32#include <asm/head.h>
33#include <asm/page.h>
34#include <asm/pgalloc.h>
35#include <asm/pgtable.h>
36#include <asm/oplib.h>
37#include <asm/iommu.h>
38#include <asm/io.h>
39#include <linux/uaccess.h>
40#include <asm/mmu_context.h>
41#include <asm/tlbflush.h>
42#include <asm/dma.h>
43#include <asm/starfire.h>
44#include <asm/tlb.h>
45#include <asm/spitfire.h>
46#include <asm/sections.h>
47#include <asm/tsb.h>
48#include <asm/hypervisor.h>
49#include <asm/prom.h>
50#include <asm/mdesc.h>
51#include <asm/cpudata.h>
52#include <asm/setup.h>
53#include <asm/irq.h>
54
55#include "init_64.h"
56
57unsigned long kern_linear_pte_xor[4] __read_mostly;
58static unsigned long page_cache4v_flag;
59
60/* A bitmap, two bits for every 256MB of physical memory. These two
61 * bits determine what page size we use for kernel linear
62 * translations. They form an index into kern_linear_pte_xor[]. The
63 * value in the indexed slot is XOR'd with the TLB miss virtual
64 * address to form the resulting TTE. The mapping is:
65 *
66 * 0 ==> 4MB
67 * 1 ==> 256MB
68 * 2 ==> 2GB
69 * 3 ==> 16GB
70 *
71 * All sun4v chips support 256MB pages. Only SPARC-T4 and later
72 * support 2GB pages, and hopefully future cpus will support the 16GB
73 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there
74 * if these larger page sizes are not supported by the cpu.
75 *
76 * It would be nice to determine this from the machine description
77 * 'cpu' properties, but we need to have this table setup before the
78 * MDESC is initialized.
79 */
80
81#ifndef CONFIG_DEBUG_PAGEALLOC
82/* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
83 * Space is allocated for this right after the trap table in
84 * arch/sparc64/kernel/head.S
85 */
86extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
87#endif
88extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
89
90static unsigned long cpu_pgsz_mask;
91
92#define MAX_BANKS 1024
93
94static struct linux_prom64_registers pavail[MAX_BANKS];
95static int pavail_ents;
96
97u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES];
98
99static int cmp_p64(const void *a, const void *b)
100{
101 const struct linux_prom64_registers *x = a, *y = b;
102
103 if (x->phys_addr > y->phys_addr)
104 return 1;
105 if (x->phys_addr < y->phys_addr)
106 return -1;
107 return 0;
108}
109
110static void __init read_obp_memory(const char *property,
111 struct linux_prom64_registers *regs,
112 int *num_ents)
113{
114 phandle node = prom_finddevice("/memory");
115 int prop_size = prom_getproplen(node, property);
116 int ents, ret, i;
117
118 ents = prop_size / sizeof(struct linux_prom64_registers);
119 if (ents > MAX_BANKS) {
120 prom_printf("The machine has more %s property entries than "
121 "this kernel can support (%d).\n",
122 property, MAX_BANKS);
123 prom_halt();
124 }
125
126 ret = prom_getproperty(node, property, (char *) regs, prop_size);
127 if (ret == -1) {
128 prom_printf("Couldn't get %s property from /memory.\n",
129 property);
130 prom_halt();
131 }
132
133 /* Sanitize what we got from the firmware, by page aligning
134 * everything.
135 */
136 for (i = 0; i < ents; i++) {
137 unsigned long base, size;
138
139 base = regs[i].phys_addr;
140 size = regs[i].reg_size;
141
142 size &= PAGE_MASK;
143 if (base & ~PAGE_MASK) {
144 unsigned long new_base = PAGE_ALIGN(base);
145
146 size -= new_base - base;
147 if ((long) size < 0L)
148 size = 0UL;
149 base = new_base;
150 }
151 if (size == 0UL) {
152 /* If it is empty, simply get rid of it.
153 * This simplifies the logic of the other
154 * functions that process these arrays.
155 */
156 memmove(®s[i], ®s[i + 1],
157 (ents - i - 1) * sizeof(regs[0]));
158 i--;
159 ents--;
160 continue;
161 }
162 regs[i].phys_addr = base;
163 regs[i].reg_size = size;
164 }
165
166 *num_ents = ents;
167
168 sort(regs, ents, sizeof(struct linux_prom64_registers),
169 cmp_p64, NULL);
170}
171
172/* Kernel physical address base and size in bytes. */
173unsigned long kern_base __read_mostly;
174unsigned long kern_size __read_mostly;
175
176/* Initial ramdisk setup */
177extern unsigned long sparc_ramdisk_image64;
178extern unsigned int sparc_ramdisk_image;
179extern unsigned int sparc_ramdisk_size;
180
181struct page *mem_map_zero __read_mostly;
182EXPORT_SYMBOL(mem_map_zero);
183
184unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
185
186unsigned long sparc64_kern_pri_context __read_mostly;
187unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
188unsigned long sparc64_kern_sec_context __read_mostly;
189
190int num_kernel_image_mappings;
191
192#ifdef CONFIG_DEBUG_DCFLUSH
193atomic_t dcpage_flushes = ATOMIC_INIT(0);
194#ifdef CONFIG_SMP
195atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
196#endif
197#endif
198
199inline void flush_dcache_page_impl(struct page *page)
200{
201 BUG_ON(tlb_type == hypervisor);
202#ifdef CONFIG_DEBUG_DCFLUSH
203 atomic_inc(&dcpage_flushes);
204#endif
205
206#ifdef DCACHE_ALIASING_POSSIBLE
207 __flush_dcache_page(page_address(page),
208 ((tlb_type == spitfire) &&
209 page_mapping_file(page) != NULL));
210#else
211 if (page_mapping_file(page) != NULL &&
212 tlb_type == spitfire)
213 __flush_icache_page(__pa(page_address(page)));
214#endif
215}
216
217#define PG_dcache_dirty PG_arch_1
218#define PG_dcache_cpu_shift 32UL
219#define PG_dcache_cpu_mask \
220 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
221
222#define dcache_dirty_cpu(page) \
223 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
224
225static inline void set_dcache_dirty(struct page *page, int this_cpu)
226{
227 unsigned long mask = this_cpu;
228 unsigned long non_cpu_bits;
229
230 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
231 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
232
233 __asm__ __volatile__("1:\n\t"
234 "ldx [%2], %%g7\n\t"
235 "and %%g7, %1, %%g1\n\t"
236 "or %%g1, %0, %%g1\n\t"
237 "casx [%2], %%g7, %%g1\n\t"
238 "cmp %%g7, %%g1\n\t"
239 "bne,pn %%xcc, 1b\n\t"
240 " nop"
241 : /* no outputs */
242 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
243 : "g1", "g7");
244}
245
246static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
247{
248 unsigned long mask = (1UL << PG_dcache_dirty);
249
250 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
251 "1:\n\t"
252 "ldx [%2], %%g7\n\t"
253 "srlx %%g7, %4, %%g1\n\t"
254 "and %%g1, %3, %%g1\n\t"
255 "cmp %%g1, %0\n\t"
256 "bne,pn %%icc, 2f\n\t"
257 " andn %%g7, %1, %%g1\n\t"
258 "casx [%2], %%g7, %%g1\n\t"
259 "cmp %%g7, %%g1\n\t"
260 "bne,pn %%xcc, 1b\n\t"
261 " nop\n"
262 "2:"
263 : /* no outputs */
264 : "r" (cpu), "r" (mask), "r" (&page->flags),
265 "i" (PG_dcache_cpu_mask),
266 "i" (PG_dcache_cpu_shift)
267 : "g1", "g7");
268}
269
270static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
271{
272 unsigned long tsb_addr = (unsigned long) ent;
273
274 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
275 tsb_addr = __pa(tsb_addr);
276
277 __tsb_insert(tsb_addr, tag, pte);
278}
279
280unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
281
282static void flush_dcache(unsigned long pfn)
283{
284 struct page *page;
285
286 page = pfn_to_page(pfn);
287 if (page) {
288 unsigned long pg_flags;
289
290 pg_flags = page->flags;
291 if (pg_flags & (1UL << PG_dcache_dirty)) {
292 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
293 PG_dcache_cpu_mask);
294 int this_cpu = get_cpu();
295
296 /* This is just to optimize away some function calls
297 * in the SMP case.
298 */
299 if (cpu == this_cpu)
300 flush_dcache_page_impl(page);
301 else
302 smp_flush_dcache_page_impl(page, cpu);
303
304 clear_dcache_dirty_cpu(page, cpu);
305
306 put_cpu();
307 }
308 }
309}
310
311/* mm->context.lock must be held */
312static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
313 unsigned long tsb_hash_shift, unsigned long address,
314 unsigned long tte)
315{
316 struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
317 unsigned long tag;
318
319 if (unlikely(!tsb))
320 return;
321
322 tsb += ((address >> tsb_hash_shift) &
323 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
324 tag = (address >> 22UL);
325 tsb_insert(tsb, tag, tte);
326}
327
328#ifdef CONFIG_HUGETLB_PAGE
329static void __init add_huge_page_size(unsigned long size)
330{
331 unsigned int order;
332
333 if (size_to_hstate(size))
334 return;
335
336 order = ilog2(size) - PAGE_SHIFT;
337 hugetlb_add_hstate(order);
338}
339
340static int __init hugetlbpage_init(void)
341{
342 add_huge_page_size(1UL << HPAGE_64K_SHIFT);
343 add_huge_page_size(1UL << HPAGE_SHIFT);
344 add_huge_page_size(1UL << HPAGE_256MB_SHIFT);
345 add_huge_page_size(1UL << HPAGE_2GB_SHIFT);
346
347 return 0;
348}
349
350arch_initcall(hugetlbpage_init);
351
352static void __init pud_huge_patch(void)
353{
354 struct pud_huge_patch_entry *p;
355 unsigned long addr;
356
357 p = &__pud_huge_patch;
358 addr = p->addr;
359 *(unsigned int *)addr = p->insn;
360
361 __asm__ __volatile__("flush %0" : : "r" (addr));
362}
363
364static int __init setup_hugepagesz(char *string)
365{
366 unsigned long long hugepage_size;
367 unsigned int hugepage_shift;
368 unsigned short hv_pgsz_idx;
369 unsigned int hv_pgsz_mask;
370 int rc = 0;
371
372 hugepage_size = memparse(string, &string);
373 hugepage_shift = ilog2(hugepage_size);
374
375 switch (hugepage_shift) {
376 case HPAGE_16GB_SHIFT:
377 hv_pgsz_mask = HV_PGSZ_MASK_16GB;
378 hv_pgsz_idx = HV_PGSZ_IDX_16GB;
379 pud_huge_patch();
380 break;
381 case HPAGE_2GB_SHIFT:
382 hv_pgsz_mask = HV_PGSZ_MASK_2GB;
383 hv_pgsz_idx = HV_PGSZ_IDX_2GB;
384 break;
385 case HPAGE_256MB_SHIFT:
386 hv_pgsz_mask = HV_PGSZ_MASK_256MB;
387 hv_pgsz_idx = HV_PGSZ_IDX_256MB;
388 break;
389 case HPAGE_SHIFT:
390 hv_pgsz_mask = HV_PGSZ_MASK_4MB;
391 hv_pgsz_idx = HV_PGSZ_IDX_4MB;
392 break;
393 case HPAGE_64K_SHIFT:
394 hv_pgsz_mask = HV_PGSZ_MASK_64K;
395 hv_pgsz_idx = HV_PGSZ_IDX_64K;
396 break;
397 default:
398 hv_pgsz_mask = 0;
399 }
400
401 if ((hv_pgsz_mask & cpu_pgsz_mask) == 0U) {
402 hugetlb_bad_size();
403 pr_err("hugepagesz=%llu not supported by MMU.\n",
404 hugepage_size);
405 goto out;
406 }
407
408 add_huge_page_size(hugepage_size);
409 rc = 1;
410
411out:
412 return rc;
413}
414__setup("hugepagesz=", setup_hugepagesz);
415#endif /* CONFIG_HUGETLB_PAGE */
416
417void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
418{
419 struct mm_struct *mm;
420 unsigned long flags;
421 bool is_huge_tsb;
422 pte_t pte = *ptep;
423
424 if (tlb_type != hypervisor) {
425 unsigned long pfn = pte_pfn(pte);
426
427 if (pfn_valid(pfn))
428 flush_dcache(pfn);
429 }
430
431 mm = vma->vm_mm;
432
433 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */
434 if (!pte_accessible(mm, pte))
435 return;
436
437 spin_lock_irqsave(&mm->context.lock, flags);
438
439 is_huge_tsb = false;
440#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
441 if (mm->context.hugetlb_pte_count || mm->context.thp_pte_count) {
442 unsigned long hugepage_size = PAGE_SIZE;
443
444 if (is_vm_hugetlb_page(vma))
445 hugepage_size = huge_page_size(hstate_vma(vma));
446
447 if (hugepage_size >= PUD_SIZE) {
448 unsigned long mask = 0x1ffc00000UL;
449
450 /* Transfer bits [32:22] from address to resolve
451 * at 4M granularity.
452 */
453 pte_val(pte) &= ~mask;
454 pte_val(pte) |= (address & mask);
455 } else if (hugepage_size >= PMD_SIZE) {
456 /* We are fabricating 8MB pages using 4MB
457 * real hw pages.
458 */
459 pte_val(pte) |= (address & (1UL << REAL_HPAGE_SHIFT));
460 }
461
462 if (hugepage_size >= PMD_SIZE) {
463 __update_mmu_tsb_insert(mm, MM_TSB_HUGE,
464 REAL_HPAGE_SHIFT, address, pte_val(pte));
465 is_huge_tsb = true;
466 }
467 }
468#endif
469 if (!is_huge_tsb)
470 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
471 address, pte_val(pte));
472
473 spin_unlock_irqrestore(&mm->context.lock, flags);
474}
475
476void flush_dcache_page(struct page *page)
477{
478 struct address_space *mapping;
479 int this_cpu;
480
481 if (tlb_type == hypervisor)
482 return;
483
484 /* Do not bother with the expensive D-cache flush if it
485 * is merely the zero page. The 'bigcore' testcase in GDB
486 * causes this case to run millions of times.
487 */
488 if (page == ZERO_PAGE(0))
489 return;
490
491 this_cpu = get_cpu();
492
493 mapping = page_mapping_file(page);
494 if (mapping && !mapping_mapped(mapping)) {
495 int dirty = test_bit(PG_dcache_dirty, &page->flags);
496 if (dirty) {
497 int dirty_cpu = dcache_dirty_cpu(page);
498
499 if (dirty_cpu == this_cpu)
500 goto out;
501 smp_flush_dcache_page_impl(page, dirty_cpu);
502 }
503 set_dcache_dirty(page, this_cpu);
504 } else {
505 /* We could delay the flush for the !page_mapping
506 * case too. But that case is for exec env/arg
507 * pages and those are %99 certainly going to get
508 * faulted into the tlb (and thus flushed) anyways.
509 */
510 flush_dcache_page_impl(page);
511 }
512
513out:
514 put_cpu();
515}
516EXPORT_SYMBOL(flush_dcache_page);
517
518void __kprobes flush_icache_range(unsigned long start, unsigned long end)
519{
520 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
521 if (tlb_type == spitfire) {
522 unsigned long kaddr;
523
524 /* This code only runs on Spitfire cpus so this is
525 * why we can assume _PAGE_PADDR_4U.
526 */
527 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
528 unsigned long paddr, mask = _PAGE_PADDR_4U;
529
530 if (kaddr >= PAGE_OFFSET)
531 paddr = kaddr & mask;
532 else {
533 pgd_t *pgdp = pgd_offset_k(kaddr);
534 pud_t *pudp = pud_offset(pgdp, kaddr);
535 pmd_t *pmdp = pmd_offset(pudp, kaddr);
536 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
537
538 paddr = pte_val(*ptep) & mask;
539 }
540 __flush_icache_page(paddr);
541 }
542 }
543}
544EXPORT_SYMBOL(flush_icache_range);
545
546void mmu_info(struct seq_file *m)
547{
548 static const char *pgsz_strings[] = {
549 "8K", "64K", "512K", "4MB", "32MB",
550 "256MB", "2GB", "16GB",
551 };
552 int i, printed;
553
554 if (tlb_type == cheetah)
555 seq_printf(m, "MMU Type\t: Cheetah\n");
556 else if (tlb_type == cheetah_plus)
557 seq_printf(m, "MMU Type\t: Cheetah+\n");
558 else if (tlb_type == spitfire)
559 seq_printf(m, "MMU Type\t: Spitfire\n");
560 else if (tlb_type == hypervisor)
561 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
562 else
563 seq_printf(m, "MMU Type\t: ???\n");
564
565 seq_printf(m, "MMU PGSZs\t: ");
566 printed = 0;
567 for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
568 if (cpu_pgsz_mask & (1UL << i)) {
569 seq_printf(m, "%s%s",
570 printed ? "," : "", pgsz_strings[i]);
571 printed++;
572 }
573 }
574 seq_putc(m, '\n');
575
576#ifdef CONFIG_DEBUG_DCFLUSH
577 seq_printf(m, "DCPageFlushes\t: %d\n",
578 atomic_read(&dcpage_flushes));
579#ifdef CONFIG_SMP
580 seq_printf(m, "DCPageFlushesXC\t: %d\n",
581 atomic_read(&dcpage_flushes_xcall));
582#endif /* CONFIG_SMP */
583#endif /* CONFIG_DEBUG_DCFLUSH */
584}
585
586struct linux_prom_translation prom_trans[512] __read_mostly;
587unsigned int prom_trans_ents __read_mostly;
588
589unsigned long kern_locked_tte_data;
590
591/* The obp translations are saved based on 8k pagesize, since obp can
592 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
593 * HI_OBP_ADDRESS range are handled in ktlb.S.
594 */
595static inline int in_obp_range(unsigned long vaddr)
596{
597 return (vaddr >= LOW_OBP_ADDRESS &&
598 vaddr < HI_OBP_ADDRESS);
599}
600
601static int cmp_ptrans(const void *a, const void *b)
602{
603 const struct linux_prom_translation *x = a, *y = b;
604
605 if (x->virt > y->virt)
606 return 1;
607 if (x->virt < y->virt)
608 return -1;
609 return 0;
610}
611
612/* Read OBP translations property into 'prom_trans[]'. */
613static void __init read_obp_translations(void)
614{
615 int n, node, ents, first, last, i;
616
617 node = prom_finddevice("/virtual-memory");
618 n = prom_getproplen(node, "translations");
619 if (unlikely(n == 0 || n == -1)) {
620 prom_printf("prom_mappings: Couldn't get size.\n");
621 prom_halt();
622 }
623 if (unlikely(n > sizeof(prom_trans))) {
624 prom_printf("prom_mappings: Size %d is too big.\n", n);
625 prom_halt();
626 }
627
628 if ((n = prom_getproperty(node, "translations",
629 (char *)&prom_trans[0],
630 sizeof(prom_trans))) == -1) {
631 prom_printf("prom_mappings: Couldn't get property.\n");
632 prom_halt();
633 }
634
635 n = n / sizeof(struct linux_prom_translation);
636
637 ents = n;
638
639 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
640 cmp_ptrans, NULL);
641
642 /* Now kick out all the non-OBP entries. */
643 for (i = 0; i < ents; i++) {
644 if (in_obp_range(prom_trans[i].virt))
645 break;
646 }
647 first = i;
648 for (; i < ents; i++) {
649 if (!in_obp_range(prom_trans[i].virt))
650 break;
651 }
652 last = i;
653
654 for (i = 0; i < (last - first); i++) {
655 struct linux_prom_translation *src = &prom_trans[i + first];
656 struct linux_prom_translation *dest = &prom_trans[i];
657
658 *dest = *src;
659 }
660 for (; i < ents; i++) {
661 struct linux_prom_translation *dest = &prom_trans[i];
662 dest->virt = dest->size = dest->data = 0x0UL;
663 }
664
665 prom_trans_ents = last - first;
666
667 if (tlb_type == spitfire) {
668 /* Clear diag TTE bits. */
669 for (i = 0; i < prom_trans_ents; i++)
670 prom_trans[i].data &= ~0x0003fe0000000000UL;
671 }
672
673 /* Force execute bit on. */
674 for (i = 0; i < prom_trans_ents; i++)
675 prom_trans[i].data |= (tlb_type == hypervisor ?
676 _PAGE_EXEC_4V : _PAGE_EXEC_4U);
677}
678
679static void __init hypervisor_tlb_lock(unsigned long vaddr,
680 unsigned long pte,
681 unsigned long mmu)
682{
683 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
684
685 if (ret != 0) {
686 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
687 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
688 prom_halt();
689 }
690}
691
692static unsigned long kern_large_tte(unsigned long paddr);
693
694static void __init remap_kernel(void)
695{
696 unsigned long phys_page, tte_vaddr, tte_data;
697 int i, tlb_ent = sparc64_highest_locked_tlbent();
698
699 tte_vaddr = (unsigned long) KERNBASE;
700 phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
701 tte_data = kern_large_tte(phys_page);
702
703 kern_locked_tte_data = tte_data;
704
705 /* Now lock us into the TLBs via Hypervisor or OBP. */
706 if (tlb_type == hypervisor) {
707 for (i = 0; i < num_kernel_image_mappings; i++) {
708 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
709 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
710 tte_vaddr += 0x400000;
711 tte_data += 0x400000;
712 }
713 } else {
714 for (i = 0; i < num_kernel_image_mappings; i++) {
715 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
716 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
717 tte_vaddr += 0x400000;
718 tte_data += 0x400000;
719 }
720 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
721 }
722 if (tlb_type == cheetah_plus) {
723 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
724 CTX_CHEETAH_PLUS_NUC);
725 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
726 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
727 }
728}
729
730
731static void __init inherit_prom_mappings(void)
732{
733 /* Now fixup OBP's idea about where we really are mapped. */
734 printk("Remapping the kernel... ");
735 remap_kernel();
736 printk("done.\n");
737}
738
739void prom_world(int enter)
740{
741 if (!enter)
742 set_fs(get_fs());
743
744 __asm__ __volatile__("flushw");
745}
746
747void __flush_dcache_range(unsigned long start, unsigned long end)
748{
749 unsigned long va;
750
751 if (tlb_type == spitfire) {
752 int n = 0;
753
754 for (va = start; va < end; va += 32) {
755 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
756 if (++n >= 512)
757 break;
758 }
759 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
760 start = __pa(start);
761 end = __pa(end);
762 for (va = start; va < end; va += 32)
763 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
764 "membar #Sync"
765 : /* no outputs */
766 : "r" (va),
767 "i" (ASI_DCACHE_INVALIDATE));
768 }
769}
770EXPORT_SYMBOL(__flush_dcache_range);
771
772/* get_new_mmu_context() uses "cache + 1". */
773DEFINE_SPINLOCK(ctx_alloc_lock);
774unsigned long tlb_context_cache = CTX_FIRST_VERSION;
775#define MAX_CTX_NR (1UL << CTX_NR_BITS)
776#define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
777DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
778DEFINE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm) = {0};
779
780static void mmu_context_wrap(void)
781{
782 unsigned long old_ver = tlb_context_cache & CTX_VERSION_MASK;
783 unsigned long new_ver, new_ctx, old_ctx;
784 struct mm_struct *mm;
785 int cpu;
786
787 bitmap_zero(mmu_context_bmap, 1 << CTX_NR_BITS);
788
789 /* Reserve kernel context */
790 set_bit(0, mmu_context_bmap);
791
792 new_ver = (tlb_context_cache & CTX_VERSION_MASK) + CTX_FIRST_VERSION;
793 if (unlikely(new_ver == 0))
794 new_ver = CTX_FIRST_VERSION;
795 tlb_context_cache = new_ver;
796
797 /*
798 * Make sure that any new mm that are added into per_cpu_secondary_mm,
799 * are going to go through get_new_mmu_context() path.
800 */
801 mb();
802
803 /*
804 * Updated versions to current on those CPUs that had valid secondary
805 * contexts
806 */
807 for_each_online_cpu(cpu) {
808 /*
809 * If a new mm is stored after we took this mm from the array,
810 * it will go into get_new_mmu_context() path, because we
811 * already bumped the version in tlb_context_cache.
812 */
813 mm = per_cpu(per_cpu_secondary_mm, cpu);
814
815 if (unlikely(!mm || mm == &init_mm))
816 continue;
817
818 old_ctx = mm->context.sparc64_ctx_val;
819 if (likely((old_ctx & CTX_VERSION_MASK) == old_ver)) {
820 new_ctx = (old_ctx & ~CTX_VERSION_MASK) | new_ver;
821 set_bit(new_ctx & CTX_NR_MASK, mmu_context_bmap);
822 mm->context.sparc64_ctx_val = new_ctx;
823 }
824 }
825}
826
827/* Caller does TLB context flushing on local CPU if necessary.
828 * The caller also ensures that CTX_VALID(mm->context) is false.
829 *
830 * We must be careful about boundary cases so that we never
831 * let the user have CTX 0 (nucleus) or we ever use a CTX
832 * version of zero (and thus NO_CONTEXT would not be caught
833 * by version mis-match tests in mmu_context.h).
834 *
835 * Always invoked with interrupts disabled.
836 */
837void get_new_mmu_context(struct mm_struct *mm)
838{
839 unsigned long ctx, new_ctx;
840 unsigned long orig_pgsz_bits;
841
842 spin_lock(&ctx_alloc_lock);
843retry:
844 /* wrap might have happened, test again if our context became valid */
845 if (unlikely(CTX_VALID(mm->context)))
846 goto out;
847 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
848 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
849 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
850 if (new_ctx >= (1 << CTX_NR_BITS)) {
851 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
852 if (new_ctx >= ctx) {
853 mmu_context_wrap();
854 goto retry;
855 }
856 }
857 if (mm->context.sparc64_ctx_val)
858 cpumask_clear(mm_cpumask(mm));
859 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
860 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
861 tlb_context_cache = new_ctx;
862 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
863out:
864 spin_unlock(&ctx_alloc_lock);
865}
866
867static int numa_enabled = 1;
868static int numa_debug;
869
870static int __init early_numa(char *p)
871{
872 if (!p)
873 return 0;
874
875 if (strstr(p, "off"))
876 numa_enabled = 0;
877
878 if (strstr(p, "debug"))
879 numa_debug = 1;
880
881 return 0;
882}
883early_param("numa", early_numa);
884
885#define numadbg(f, a...) \
886do { if (numa_debug) \
887 printk(KERN_INFO f, ## a); \
888} while (0)
889
890static void __init find_ramdisk(unsigned long phys_base)
891{
892#ifdef CONFIG_BLK_DEV_INITRD
893 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
894 unsigned long ramdisk_image;
895
896 /* Older versions of the bootloader only supported a
897 * 32-bit physical address for the ramdisk image
898 * location, stored at sparc_ramdisk_image. Newer
899 * SILO versions set sparc_ramdisk_image to zero and
900 * provide a full 64-bit physical address at
901 * sparc_ramdisk_image64.
902 */
903 ramdisk_image = sparc_ramdisk_image;
904 if (!ramdisk_image)
905 ramdisk_image = sparc_ramdisk_image64;
906
907 /* Another bootloader quirk. The bootloader normalizes
908 * the physical address to KERNBASE, so we have to
909 * factor that back out and add in the lowest valid
910 * physical page address to get the true physical address.
911 */
912 ramdisk_image -= KERNBASE;
913 ramdisk_image += phys_base;
914
915 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
916 ramdisk_image, sparc_ramdisk_size);
917
918 initrd_start = ramdisk_image;
919 initrd_end = ramdisk_image + sparc_ramdisk_size;
920
921 memblock_reserve(initrd_start, sparc_ramdisk_size);
922
923 initrd_start += PAGE_OFFSET;
924 initrd_end += PAGE_OFFSET;
925 }
926#endif
927}
928
929struct node_mem_mask {
930 unsigned long mask;
931 unsigned long match;
932};
933static struct node_mem_mask node_masks[MAX_NUMNODES];
934static int num_node_masks;
935
936#ifdef CONFIG_NEED_MULTIPLE_NODES
937
938struct mdesc_mlgroup {
939 u64 node;
940 u64 latency;
941 u64 match;
942 u64 mask;
943};
944
945static struct mdesc_mlgroup *mlgroups;
946static int num_mlgroups;
947
948int numa_cpu_lookup_table[NR_CPUS];
949cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
950
951struct mdesc_mblock {
952 u64 base;
953 u64 size;
954 u64 offset; /* RA-to-PA */
955};
956static struct mdesc_mblock *mblocks;
957static int num_mblocks;
958
959static struct mdesc_mblock * __init addr_to_mblock(unsigned long addr)
960{
961 struct mdesc_mblock *m = NULL;
962 int i;
963
964 for (i = 0; i < num_mblocks; i++) {
965 m = &mblocks[i];
966
967 if (addr >= m->base &&
968 addr < (m->base + m->size)) {
969 break;
970 }
971 }
972
973 return m;
974}
975
976static u64 __init memblock_nid_range_sun4u(u64 start, u64 end, int *nid)
977{
978 int prev_nid, new_nid;
979
980 prev_nid = -1;
981 for ( ; start < end; start += PAGE_SIZE) {
982 for (new_nid = 0; new_nid < num_node_masks; new_nid++) {
983 struct node_mem_mask *p = &node_masks[new_nid];
984
985 if ((start & p->mask) == p->match) {
986 if (prev_nid == -1)
987 prev_nid = new_nid;
988 break;
989 }
990 }
991
992 if (new_nid == num_node_masks) {
993 prev_nid = 0;
994 WARN_ONCE(1, "addr[%Lx] doesn't match a NUMA node rule. Some memory will be owned by node 0.",
995 start);
996 break;
997 }
998
999 if (prev_nid != new_nid)
1000 break;
1001 }
1002 *nid = prev_nid;
1003
1004 return start > end ? end : start;
1005}
1006
1007static u64 __init memblock_nid_range(u64 start, u64 end, int *nid)
1008{
1009 u64 ret_end, pa_start, m_mask, m_match, m_end;
1010 struct mdesc_mblock *mblock;
1011 int _nid, i;
1012
1013 if (tlb_type != hypervisor)
1014 return memblock_nid_range_sun4u(start, end, nid);
1015
1016 mblock = addr_to_mblock(start);
1017 if (!mblock) {
1018 WARN_ONCE(1, "memblock_nid_range: Can't find mblock addr[%Lx]",
1019 start);
1020
1021 _nid = 0;
1022 ret_end = end;
1023 goto done;
1024 }
1025
1026 pa_start = start + mblock->offset;
1027 m_match = 0;
1028 m_mask = 0;
1029
1030 for (_nid = 0; _nid < num_node_masks; _nid++) {
1031 struct node_mem_mask *const m = &node_masks[_nid];
1032
1033 if ((pa_start & m->mask) == m->match) {
1034 m_match = m->match;
1035 m_mask = m->mask;
1036 break;
1037 }
1038 }
1039
1040 if (num_node_masks == _nid) {
1041 /* We could not find NUMA group, so default to 0, but lets
1042 * search for latency group, so we could calculate the correct
1043 * end address that we return
1044 */
1045 _nid = 0;
1046
1047 for (i = 0; i < num_mlgroups; i++) {
1048 struct mdesc_mlgroup *const m = &mlgroups[i];
1049
1050 if ((pa_start & m->mask) == m->match) {
1051 m_match = m->match;
1052 m_mask = m->mask;
1053 break;
1054 }
1055 }
1056
1057 if (i == num_mlgroups) {
1058 WARN_ONCE(1, "memblock_nid_range: Can't find latency group addr[%Lx]",
1059 start);
1060
1061 ret_end = end;
1062 goto done;
1063 }
1064 }
1065
1066 /*
1067 * Each latency group has match and mask, and each memory block has an
1068 * offset. An address belongs to a latency group if its address matches
1069 * the following formula: ((addr + offset) & mask) == match
1070 * It is, however, slow to check every single page if it matches a
1071 * particular latency group. As optimization we calculate end value by
1072 * using bit arithmetics.
1073 */
1074 m_end = m_match + (1ul << __ffs(m_mask)) - mblock->offset;
1075 m_end += pa_start & ~((1ul << fls64(m_mask)) - 1);
1076 ret_end = m_end > end ? end : m_end;
1077
1078done:
1079 *nid = _nid;
1080 return ret_end;
1081}
1082#endif
1083
1084/* This must be invoked after performing all of the necessary
1085 * memblock_set_node() calls for 'nid'. We need to be able to get
1086 * correct data from get_pfn_range_for_nid().
1087 */
1088static void __init allocate_node_data(int nid)
1089{
1090 struct pglist_data *p;
1091 unsigned long start_pfn, end_pfn;
1092#ifdef CONFIG_NEED_MULTIPLE_NODES
1093 unsigned long paddr;
1094
1095 paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
1096 if (!paddr) {
1097 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
1098 prom_halt();
1099 }
1100 NODE_DATA(nid) = __va(paddr);
1101 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
1102
1103 NODE_DATA(nid)->node_id = nid;
1104#endif
1105
1106 p = NODE_DATA(nid);
1107
1108 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
1109 p->node_start_pfn = start_pfn;
1110 p->node_spanned_pages = end_pfn - start_pfn;
1111}
1112
1113static void init_node_masks_nonnuma(void)
1114{
1115#ifdef CONFIG_NEED_MULTIPLE_NODES
1116 int i;
1117#endif
1118
1119 numadbg("Initializing tables for non-numa.\n");
1120
1121 node_masks[0].mask = 0;
1122 node_masks[0].match = 0;
1123 num_node_masks = 1;
1124
1125#ifdef CONFIG_NEED_MULTIPLE_NODES
1126 for (i = 0; i < NR_CPUS; i++)
1127 numa_cpu_lookup_table[i] = 0;
1128
1129 cpumask_setall(&numa_cpumask_lookup_table[0]);
1130#endif
1131}
1132
1133#ifdef CONFIG_NEED_MULTIPLE_NODES
1134struct pglist_data *node_data[MAX_NUMNODES];
1135
1136EXPORT_SYMBOL(numa_cpu_lookup_table);
1137EXPORT_SYMBOL(numa_cpumask_lookup_table);
1138EXPORT_SYMBOL(node_data);
1139
1140static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
1141 u32 cfg_handle)
1142{
1143 u64 arc;
1144
1145 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
1146 u64 target = mdesc_arc_target(md, arc);
1147 const u64 *val;
1148
1149 val = mdesc_get_property(md, target,
1150 "cfg-handle", NULL);
1151 if (val && *val == cfg_handle)
1152 return 0;
1153 }
1154 return -ENODEV;
1155}
1156
1157static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
1158 u32 cfg_handle)
1159{
1160 u64 arc, candidate, best_latency = ~(u64)0;
1161
1162 candidate = MDESC_NODE_NULL;
1163 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1164 u64 target = mdesc_arc_target(md, arc);
1165 const char *name = mdesc_node_name(md, target);
1166 const u64 *val;
1167
1168 if (strcmp(name, "pio-latency-group"))
1169 continue;
1170
1171 val = mdesc_get_property(md, target, "latency", NULL);
1172 if (!val)
1173 continue;
1174
1175 if (*val < best_latency) {
1176 candidate = target;
1177 best_latency = *val;
1178 }
1179 }
1180
1181 if (candidate == MDESC_NODE_NULL)
1182 return -ENODEV;
1183
1184 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
1185}
1186
1187int of_node_to_nid(struct device_node *dp)
1188{
1189 const struct linux_prom64_registers *regs;
1190 struct mdesc_handle *md;
1191 u32 cfg_handle;
1192 int count, nid;
1193 u64 grp;
1194
1195 /* This is the right thing to do on currently supported
1196 * SUN4U NUMA platforms as well, as the PCI controller does
1197 * not sit behind any particular memory controller.
1198 */
1199 if (!mlgroups)
1200 return -1;
1201
1202 regs = of_get_property(dp, "reg", NULL);
1203 if (!regs)
1204 return -1;
1205
1206 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1207
1208 md = mdesc_grab();
1209
1210 count = 0;
1211 nid = -1;
1212 mdesc_for_each_node_by_name(md, grp, "group") {
1213 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
1214 nid = count;
1215 break;
1216 }
1217 count++;
1218 }
1219
1220 mdesc_release(md);
1221
1222 return nid;
1223}
1224
1225static void __init add_node_ranges(void)
1226{
1227 struct memblock_region *reg;
1228 unsigned long prev_max;
1229
1230memblock_resized:
1231 prev_max = memblock.memory.max;
1232
1233 for_each_memblock(memory, reg) {
1234 unsigned long size = reg->size;
1235 unsigned long start, end;
1236
1237 start = reg->base;
1238 end = start + size;
1239 while (start < end) {
1240 unsigned long this_end;
1241 int nid;
1242
1243 this_end = memblock_nid_range(start, end, &nid);
1244
1245 numadbg("Setting memblock NUMA node nid[%d] "
1246 "start[%lx] end[%lx]\n",
1247 nid, start, this_end);
1248
1249 memblock_set_node(start, this_end - start,
1250 &memblock.memory, nid);
1251 if (memblock.memory.max != prev_max)
1252 goto memblock_resized;
1253 start = this_end;
1254 }
1255 }
1256}
1257
1258static int __init grab_mlgroups(struct mdesc_handle *md)
1259{
1260 unsigned long paddr;
1261 int count = 0;
1262 u64 node;
1263
1264 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1265 count++;
1266 if (!count)
1267 return -ENOENT;
1268
1269 paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
1270 SMP_CACHE_BYTES);
1271 if (!paddr)
1272 return -ENOMEM;
1273
1274 mlgroups = __va(paddr);
1275 num_mlgroups = count;
1276
1277 count = 0;
1278 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1279 struct mdesc_mlgroup *m = &mlgroups[count++];
1280 const u64 *val;
1281
1282 m->node = node;
1283
1284 val = mdesc_get_property(md, node, "latency", NULL);
1285 m->latency = *val;
1286 val = mdesc_get_property(md, node, "address-match", NULL);
1287 m->match = *val;
1288 val = mdesc_get_property(md, node, "address-mask", NULL);
1289 m->mask = *val;
1290
1291 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1292 "match[%llx] mask[%llx]\n",
1293 count - 1, m->node, m->latency, m->match, m->mask);
1294 }
1295
1296 return 0;
1297}
1298
1299static int __init grab_mblocks(struct mdesc_handle *md)
1300{
1301 unsigned long paddr;
1302 int count = 0;
1303 u64 node;
1304
1305 mdesc_for_each_node_by_name(md, node, "mblock")
1306 count++;
1307 if (!count)
1308 return -ENOENT;
1309
1310 paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
1311 SMP_CACHE_BYTES);
1312 if (!paddr)
1313 return -ENOMEM;
1314
1315 mblocks = __va(paddr);
1316 num_mblocks = count;
1317
1318 count = 0;
1319 mdesc_for_each_node_by_name(md, node, "mblock") {
1320 struct mdesc_mblock *m = &mblocks[count++];
1321 const u64 *val;
1322
1323 val = mdesc_get_property(md, node, "base", NULL);
1324 m->base = *val;
1325 val = mdesc_get_property(md, node, "size", NULL);
1326 m->size = *val;
1327 val = mdesc_get_property(md, node,
1328 "address-congruence-offset", NULL);
1329
1330 /* The address-congruence-offset property is optional.
1331 * Explicity zero it be identifty this.
1332 */
1333 if (val)
1334 m->offset = *val;
1335 else
1336 m->offset = 0UL;
1337
1338 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1339 count - 1, m->base, m->size, m->offset);
1340 }
1341
1342 return 0;
1343}
1344
1345static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1346 u64 grp, cpumask_t *mask)
1347{
1348 u64 arc;
1349
1350 cpumask_clear(mask);
1351
1352 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1353 u64 target = mdesc_arc_target(md, arc);
1354 const char *name = mdesc_node_name(md, target);
1355 const u64 *id;
1356
1357 if (strcmp(name, "cpu"))
1358 continue;
1359 id = mdesc_get_property(md, target, "id", NULL);
1360 if (*id < nr_cpu_ids)
1361 cpumask_set_cpu(*id, mask);
1362 }
1363}
1364
1365static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1366{
1367 int i;
1368
1369 for (i = 0; i < num_mlgroups; i++) {
1370 struct mdesc_mlgroup *m = &mlgroups[i];
1371 if (m->node == node)
1372 return m;
1373 }
1374 return NULL;
1375}
1376
1377int __node_distance(int from, int to)
1378{
1379 if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) {
1380 pr_warn("Returning default NUMA distance value for %d->%d\n",
1381 from, to);
1382 return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE;
1383 }
1384 return numa_latency[from][to];
1385}
1386
1387static int __init find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp)
1388{
1389 int i;
1390
1391 for (i = 0; i < MAX_NUMNODES; i++) {
1392 struct node_mem_mask *n = &node_masks[i];
1393
1394 if ((grp->mask == n->mask) && (grp->match == n->match))
1395 break;
1396 }
1397 return i;
1398}
1399
1400static void __init find_numa_latencies_for_group(struct mdesc_handle *md,
1401 u64 grp, int index)
1402{
1403 u64 arc;
1404
1405 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1406 int tnode;
1407 u64 target = mdesc_arc_target(md, arc);
1408 struct mdesc_mlgroup *m = find_mlgroup(target);
1409
1410 if (!m)
1411 continue;
1412 tnode = find_best_numa_node_for_mlgroup(m);
1413 if (tnode == MAX_NUMNODES)
1414 continue;
1415 numa_latency[index][tnode] = m->latency;
1416 }
1417}
1418
1419static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1420 int index)
1421{
1422 struct mdesc_mlgroup *candidate = NULL;
1423 u64 arc, best_latency = ~(u64)0;
1424 struct node_mem_mask *n;
1425
1426 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1427 u64 target = mdesc_arc_target(md, arc);
1428 struct mdesc_mlgroup *m = find_mlgroup(target);
1429 if (!m)
1430 continue;
1431 if (m->latency < best_latency) {
1432 candidate = m;
1433 best_latency = m->latency;
1434 }
1435 }
1436 if (!candidate)
1437 return -ENOENT;
1438
1439 if (num_node_masks != index) {
1440 printk(KERN_ERR "Inconsistent NUMA state, "
1441 "index[%d] != num_node_masks[%d]\n",
1442 index, num_node_masks);
1443 return -EINVAL;
1444 }
1445
1446 n = &node_masks[num_node_masks++];
1447
1448 n->mask = candidate->mask;
1449 n->match = candidate->match;
1450
1451 numadbg("NUMA NODE[%d]: mask[%lx] match[%lx] (latency[%llx])\n",
1452 index, n->mask, n->match, candidate->latency);
1453
1454 return 0;
1455}
1456
1457static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1458 int index)
1459{
1460 cpumask_t mask;
1461 int cpu;
1462
1463 numa_parse_mdesc_group_cpus(md, grp, &mask);
1464
1465 for_each_cpu(cpu, &mask)
1466 numa_cpu_lookup_table[cpu] = index;
1467 cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1468
1469 if (numa_debug) {
1470 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1471 for_each_cpu(cpu, &mask)
1472 printk("%d ", cpu);
1473 printk("]\n");
1474 }
1475
1476 return numa_attach_mlgroup(md, grp, index);
1477}
1478
1479static int __init numa_parse_mdesc(void)
1480{
1481 struct mdesc_handle *md = mdesc_grab();
1482 int i, j, err, count;
1483 u64 node;
1484
1485 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1486 if (node == MDESC_NODE_NULL) {
1487 mdesc_release(md);
1488 return -ENOENT;
1489 }
1490
1491 err = grab_mblocks(md);
1492 if (err < 0)
1493 goto out;
1494
1495 err = grab_mlgroups(md);
1496 if (err < 0)
1497 goto out;
1498
1499 count = 0;
1500 mdesc_for_each_node_by_name(md, node, "group") {
1501 err = numa_parse_mdesc_group(md, node, count);
1502 if (err < 0)
1503 break;
1504 count++;
1505 }
1506
1507 count = 0;
1508 mdesc_for_each_node_by_name(md, node, "group") {
1509 find_numa_latencies_for_group(md, node, count);
1510 count++;
1511 }
1512
1513 /* Normalize numa latency matrix according to ACPI SLIT spec. */
1514 for (i = 0; i < MAX_NUMNODES; i++) {
1515 u64 self_latency = numa_latency[i][i];
1516
1517 for (j = 0; j < MAX_NUMNODES; j++) {
1518 numa_latency[i][j] =
1519 (numa_latency[i][j] * LOCAL_DISTANCE) /
1520 self_latency;
1521 }
1522 }
1523
1524 add_node_ranges();
1525
1526 for (i = 0; i < num_node_masks; i++) {
1527 allocate_node_data(i);
1528 node_set_online(i);
1529 }
1530
1531 err = 0;
1532out:
1533 mdesc_release(md);
1534 return err;
1535}
1536
1537static int __init numa_parse_jbus(void)
1538{
1539 unsigned long cpu, index;
1540
1541 /* NUMA node id is encoded in bits 36 and higher, and there is
1542 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1543 */
1544 index = 0;
1545 for_each_present_cpu(cpu) {
1546 numa_cpu_lookup_table[cpu] = index;
1547 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1548 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1549 node_masks[index].match = cpu << 36UL;
1550
1551 index++;
1552 }
1553 num_node_masks = index;
1554
1555 add_node_ranges();
1556
1557 for (index = 0; index < num_node_masks; index++) {
1558 allocate_node_data(index);
1559 node_set_online(index);
1560 }
1561
1562 return 0;
1563}
1564
1565static int __init numa_parse_sun4u(void)
1566{
1567 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1568 unsigned long ver;
1569
1570 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1571 if ((ver >> 32UL) == __JALAPENO_ID ||
1572 (ver >> 32UL) == __SERRANO_ID)
1573 return numa_parse_jbus();
1574 }
1575 return -1;
1576}
1577
1578static int __init bootmem_init_numa(void)
1579{
1580 int i, j;
1581 int err = -1;
1582
1583 numadbg("bootmem_init_numa()\n");
1584
1585 /* Some sane defaults for numa latency values */
1586 for (i = 0; i < MAX_NUMNODES; i++) {
1587 for (j = 0; j < MAX_NUMNODES; j++)
1588 numa_latency[i][j] = (i == j) ?
1589 LOCAL_DISTANCE : REMOTE_DISTANCE;
1590 }
1591
1592 if (numa_enabled) {
1593 if (tlb_type == hypervisor)
1594 err = numa_parse_mdesc();
1595 else
1596 err = numa_parse_sun4u();
1597 }
1598 return err;
1599}
1600
1601#else
1602
1603static int bootmem_init_numa(void)
1604{
1605 return -1;
1606}
1607
1608#endif
1609
1610static void __init bootmem_init_nonnuma(void)
1611{
1612 unsigned long top_of_ram = memblock_end_of_DRAM();
1613 unsigned long total_ram = memblock_phys_mem_size();
1614
1615 numadbg("bootmem_init_nonnuma()\n");
1616
1617 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1618 top_of_ram, total_ram);
1619 printk(KERN_INFO "Memory hole size: %ldMB\n",
1620 (top_of_ram - total_ram) >> 20);
1621
1622 init_node_masks_nonnuma();
1623 memblock_set_node(0, (phys_addr_t)ULLONG_MAX, &memblock.memory, 0);
1624 allocate_node_data(0);
1625 node_set_online(0);
1626}
1627
1628static unsigned long __init bootmem_init(unsigned long phys_base)
1629{
1630 unsigned long end_pfn;
1631
1632 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1633 max_pfn = max_low_pfn = end_pfn;
1634 min_low_pfn = (phys_base >> PAGE_SHIFT);
1635
1636 if (bootmem_init_numa() < 0)
1637 bootmem_init_nonnuma();
1638
1639 /* Dump memblock with node info. */
1640 memblock_dump_all();
1641
1642 /* XXX cpu notifier XXX */
1643
1644 sparse_memory_present_with_active_regions(MAX_NUMNODES);
1645 sparse_init();
1646
1647 return end_pfn;
1648}
1649
1650static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1651static int pall_ents __initdata;
1652
1653static unsigned long max_phys_bits = 40;
1654
1655bool kern_addr_valid(unsigned long addr)
1656{
1657 pgd_t *pgd;
1658 pud_t *pud;
1659 pmd_t *pmd;
1660 pte_t *pte;
1661
1662 if ((long)addr < 0L) {
1663 unsigned long pa = __pa(addr);
1664
1665 if ((pa >> max_phys_bits) != 0UL)
1666 return false;
1667
1668 return pfn_valid(pa >> PAGE_SHIFT);
1669 }
1670
1671 if (addr >= (unsigned long) KERNBASE &&
1672 addr < (unsigned long)&_end)
1673 return true;
1674
1675 pgd = pgd_offset_k(addr);
1676 if (pgd_none(*pgd))
1677 return 0;
1678
1679 pud = pud_offset(pgd, addr);
1680 if (pud_none(*pud))
1681 return 0;
1682
1683 if (pud_large(*pud))
1684 return pfn_valid(pud_pfn(*pud));
1685
1686 pmd = pmd_offset(pud, addr);
1687 if (pmd_none(*pmd))
1688 return 0;
1689
1690 if (pmd_large(*pmd))
1691 return pfn_valid(pmd_pfn(*pmd));
1692
1693 pte = pte_offset_kernel(pmd, addr);
1694 if (pte_none(*pte))
1695 return 0;
1696
1697 return pfn_valid(pte_pfn(*pte));
1698}
1699EXPORT_SYMBOL(kern_addr_valid);
1700
1701static unsigned long __ref kernel_map_hugepud(unsigned long vstart,
1702 unsigned long vend,
1703 pud_t *pud)
1704{
1705 const unsigned long mask16gb = (1UL << 34) - 1UL;
1706 u64 pte_val = vstart;
1707
1708 /* Each PUD is 8GB */
1709 if ((vstart & mask16gb) ||
1710 (vend - vstart <= mask16gb)) {
1711 pte_val ^= kern_linear_pte_xor[2];
1712 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE;
1713
1714 return vstart + PUD_SIZE;
1715 }
1716
1717 pte_val ^= kern_linear_pte_xor[3];
1718 pte_val |= _PAGE_PUD_HUGE;
1719
1720 vend = vstart + mask16gb + 1UL;
1721 while (vstart < vend) {
1722 pud_val(*pud) = pte_val;
1723
1724 pte_val += PUD_SIZE;
1725 vstart += PUD_SIZE;
1726 pud++;
1727 }
1728 return vstart;
1729}
1730
1731static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend,
1732 bool guard)
1733{
1734 if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE)
1735 return true;
1736
1737 return false;
1738}
1739
1740static unsigned long __ref kernel_map_hugepmd(unsigned long vstart,
1741 unsigned long vend,
1742 pmd_t *pmd)
1743{
1744 const unsigned long mask256mb = (1UL << 28) - 1UL;
1745 const unsigned long mask2gb = (1UL << 31) - 1UL;
1746 u64 pte_val = vstart;
1747
1748 /* Each PMD is 8MB */
1749 if ((vstart & mask256mb) ||
1750 (vend - vstart <= mask256mb)) {
1751 pte_val ^= kern_linear_pte_xor[0];
1752 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE;
1753
1754 return vstart + PMD_SIZE;
1755 }
1756
1757 if ((vstart & mask2gb) ||
1758 (vend - vstart <= mask2gb)) {
1759 pte_val ^= kern_linear_pte_xor[1];
1760 pte_val |= _PAGE_PMD_HUGE;
1761 vend = vstart + mask256mb + 1UL;
1762 } else {
1763 pte_val ^= kern_linear_pte_xor[2];
1764 pte_val |= _PAGE_PMD_HUGE;
1765 vend = vstart + mask2gb + 1UL;
1766 }
1767
1768 while (vstart < vend) {
1769 pmd_val(*pmd) = pte_val;
1770
1771 pte_val += PMD_SIZE;
1772 vstart += PMD_SIZE;
1773 pmd++;
1774 }
1775
1776 return vstart;
1777}
1778
1779static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend,
1780 bool guard)
1781{
1782 if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE)
1783 return true;
1784
1785 return false;
1786}
1787
1788static unsigned long __ref kernel_map_range(unsigned long pstart,
1789 unsigned long pend, pgprot_t prot,
1790 bool use_huge)
1791{
1792 unsigned long vstart = PAGE_OFFSET + pstart;
1793 unsigned long vend = PAGE_OFFSET + pend;
1794 unsigned long alloc_bytes = 0UL;
1795
1796 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1797 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1798 vstart, vend);
1799 prom_halt();
1800 }
1801
1802 while (vstart < vend) {
1803 unsigned long this_end, paddr = __pa(vstart);
1804 pgd_t *pgd = pgd_offset_k(vstart);
1805 pud_t *pud;
1806 pmd_t *pmd;
1807 pte_t *pte;
1808
1809 if (pgd_none(*pgd)) {
1810 pud_t *new;
1811
1812 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1813 alloc_bytes += PAGE_SIZE;
1814 pgd_populate(&init_mm, pgd, new);
1815 }
1816 pud = pud_offset(pgd, vstart);
1817 if (pud_none(*pud)) {
1818 pmd_t *new;
1819
1820 if (kernel_can_map_hugepud(vstart, vend, use_huge)) {
1821 vstart = kernel_map_hugepud(vstart, vend, pud);
1822 continue;
1823 }
1824 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1825 alloc_bytes += PAGE_SIZE;
1826 pud_populate(&init_mm, pud, new);
1827 }
1828
1829 pmd = pmd_offset(pud, vstart);
1830 if (pmd_none(*pmd)) {
1831 pte_t *new;
1832
1833 if (kernel_can_map_hugepmd(vstart, vend, use_huge)) {
1834 vstart = kernel_map_hugepmd(vstart, vend, pmd);
1835 continue;
1836 }
1837 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1838 alloc_bytes += PAGE_SIZE;
1839 pmd_populate_kernel(&init_mm, pmd, new);
1840 }
1841
1842 pte = pte_offset_kernel(pmd, vstart);
1843 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1844 if (this_end > vend)
1845 this_end = vend;
1846
1847 while (vstart < this_end) {
1848 pte_val(*pte) = (paddr | pgprot_val(prot));
1849
1850 vstart += PAGE_SIZE;
1851 paddr += PAGE_SIZE;
1852 pte++;
1853 }
1854 }
1855
1856 return alloc_bytes;
1857}
1858
1859static void __init flush_all_kernel_tsbs(void)
1860{
1861 int i;
1862
1863 for (i = 0; i < KERNEL_TSB_NENTRIES; i++) {
1864 struct tsb *ent = &swapper_tsb[i];
1865
1866 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1867 }
1868#ifndef CONFIG_DEBUG_PAGEALLOC
1869 for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) {
1870 struct tsb *ent = &swapper_4m_tsb[i];
1871
1872 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1873 }
1874#endif
1875}
1876
1877extern unsigned int kvmap_linear_patch[1];
1878
1879static void __init kernel_physical_mapping_init(void)
1880{
1881 unsigned long i, mem_alloced = 0UL;
1882 bool use_huge = true;
1883
1884#ifdef CONFIG_DEBUG_PAGEALLOC
1885 use_huge = false;
1886#endif
1887 for (i = 0; i < pall_ents; i++) {
1888 unsigned long phys_start, phys_end;
1889
1890 phys_start = pall[i].phys_addr;
1891 phys_end = phys_start + pall[i].reg_size;
1892
1893 mem_alloced += kernel_map_range(phys_start, phys_end,
1894 PAGE_KERNEL, use_huge);
1895 }
1896
1897 printk("Allocated %ld bytes for kernel page tables.\n",
1898 mem_alloced);
1899
1900 kvmap_linear_patch[0] = 0x01000000; /* nop */
1901 flushi(&kvmap_linear_patch[0]);
1902
1903 flush_all_kernel_tsbs();
1904
1905 __flush_tlb_all();
1906}
1907
1908#ifdef CONFIG_DEBUG_PAGEALLOC
1909void __kernel_map_pages(struct page *page, int numpages, int enable)
1910{
1911 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1912 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1913
1914 kernel_map_range(phys_start, phys_end,
1915 (enable ? PAGE_KERNEL : __pgprot(0)), false);
1916
1917 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1918 PAGE_OFFSET + phys_end);
1919
1920 /* we should perform an IPI and flush all tlbs,
1921 * but that can deadlock->flush only current cpu.
1922 */
1923 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1924 PAGE_OFFSET + phys_end);
1925}
1926#endif
1927
1928unsigned long __init find_ecache_flush_span(unsigned long size)
1929{
1930 int i;
1931
1932 for (i = 0; i < pavail_ents; i++) {
1933 if (pavail[i].reg_size >= size)
1934 return pavail[i].phys_addr;
1935 }
1936
1937 return ~0UL;
1938}
1939
1940unsigned long PAGE_OFFSET;
1941EXPORT_SYMBOL(PAGE_OFFSET);
1942
1943unsigned long VMALLOC_END = 0x0000010000000000UL;
1944EXPORT_SYMBOL(VMALLOC_END);
1945
1946unsigned long sparc64_va_hole_top = 0xfffff80000000000UL;
1947unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;
1948
1949static void __init setup_page_offset(void)
1950{
1951 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1952 /* Cheetah/Panther support a full 64-bit virtual
1953 * address, so we can use all that our page tables
1954 * support.
1955 */
1956 sparc64_va_hole_top = 0xfff0000000000000UL;
1957 sparc64_va_hole_bottom = 0x0010000000000000UL;
1958
1959 max_phys_bits = 42;
1960 } else if (tlb_type == hypervisor) {
1961 switch (sun4v_chip_type) {
1962 case SUN4V_CHIP_NIAGARA1:
1963 case SUN4V_CHIP_NIAGARA2:
1964 /* T1 and T2 support 48-bit virtual addresses. */
1965 sparc64_va_hole_top = 0xffff800000000000UL;
1966 sparc64_va_hole_bottom = 0x0000800000000000UL;
1967
1968 max_phys_bits = 39;
1969 break;
1970 case SUN4V_CHIP_NIAGARA3:
1971 /* T3 supports 48-bit virtual addresses. */
1972 sparc64_va_hole_top = 0xffff800000000000UL;
1973 sparc64_va_hole_bottom = 0x0000800000000000UL;
1974
1975 max_phys_bits = 43;
1976 break;
1977 case SUN4V_CHIP_NIAGARA4:
1978 case SUN4V_CHIP_NIAGARA5:
1979 case SUN4V_CHIP_SPARC64X:
1980 case SUN4V_CHIP_SPARC_M6:
1981 /* T4 and later support 52-bit virtual addresses. */
1982 sparc64_va_hole_top = 0xfff8000000000000UL;
1983 sparc64_va_hole_bottom = 0x0008000000000000UL;
1984 max_phys_bits = 47;
1985 break;
1986 case SUN4V_CHIP_SPARC_M7:
1987 case SUN4V_CHIP_SPARC_SN:
1988 /* M7 and later support 52-bit virtual addresses. */
1989 sparc64_va_hole_top = 0xfff8000000000000UL;
1990 sparc64_va_hole_bottom = 0x0008000000000000UL;
1991 max_phys_bits = 49;
1992 break;
1993 case SUN4V_CHIP_SPARC_M8:
1994 default:
1995 /* M8 and later support 54-bit virtual addresses.
1996 * However, restricting M8 and above VA bits to 53
1997 * as 4-level page table cannot support more than
1998 * 53 VA bits.
1999 */
2000 sparc64_va_hole_top = 0xfff0000000000000UL;
2001 sparc64_va_hole_bottom = 0x0010000000000000UL;
2002 max_phys_bits = 51;
2003 break;
2004 }
2005 }
2006
2007 if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
2008 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
2009 max_phys_bits);
2010 prom_halt();
2011 }
2012
2013 PAGE_OFFSET = sparc64_va_hole_top;
2014 VMALLOC_END = ((sparc64_va_hole_bottom >> 1) +
2015 (sparc64_va_hole_bottom >> 2));
2016
2017 pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
2018 PAGE_OFFSET, max_phys_bits);
2019 pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
2020 VMALLOC_START, VMALLOC_END);
2021 pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
2022 VMEMMAP_BASE, VMEMMAP_BASE << 1);
2023}
2024
2025static void __init tsb_phys_patch(void)
2026{
2027 struct tsb_ldquad_phys_patch_entry *pquad;
2028 struct tsb_phys_patch_entry *p;
2029
2030 pquad = &__tsb_ldquad_phys_patch;
2031 while (pquad < &__tsb_ldquad_phys_patch_end) {
2032 unsigned long addr = pquad->addr;
2033
2034 if (tlb_type == hypervisor)
2035 *(unsigned int *) addr = pquad->sun4v_insn;
2036 else
2037 *(unsigned int *) addr = pquad->sun4u_insn;
2038 wmb();
2039 __asm__ __volatile__("flush %0"
2040 : /* no outputs */
2041 : "r" (addr));
2042
2043 pquad++;
2044 }
2045
2046 p = &__tsb_phys_patch;
2047 while (p < &__tsb_phys_patch_end) {
2048 unsigned long addr = p->addr;
2049
2050 *(unsigned int *) addr = p->insn;
2051 wmb();
2052 __asm__ __volatile__("flush %0"
2053 : /* no outputs */
2054 : "r" (addr));
2055
2056 p++;
2057 }
2058}
2059
2060/* Don't mark as init, we give this to the Hypervisor. */
2061#ifndef CONFIG_DEBUG_PAGEALLOC
2062#define NUM_KTSB_DESCR 2
2063#else
2064#define NUM_KTSB_DESCR 1
2065#endif
2066static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
2067
2068/* The swapper TSBs are loaded with a base sequence of:
2069 *
2070 * sethi %uhi(SYMBOL), REG1
2071 * sethi %hi(SYMBOL), REG2
2072 * or REG1, %ulo(SYMBOL), REG1
2073 * or REG2, %lo(SYMBOL), REG2
2074 * sllx REG1, 32, REG1
2075 * or REG1, REG2, REG1
2076 *
2077 * When we use physical addressing for the TSB accesses, we patch the
2078 * first four instructions in the above sequence.
2079 */
2080
2081static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
2082{
2083 unsigned long high_bits, low_bits;
2084
2085 high_bits = (pa >> 32) & 0xffffffff;
2086 low_bits = (pa >> 0) & 0xffffffff;
2087
2088 while (start < end) {
2089 unsigned int *ia = (unsigned int *)(unsigned long)*start;
2090
2091 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10);
2092 __asm__ __volatile__("flush %0" : : "r" (ia));
2093
2094 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10);
2095 __asm__ __volatile__("flush %0" : : "r" (ia + 1));
2096
2097 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff);
2098 __asm__ __volatile__("flush %0" : : "r" (ia + 2));
2099
2100 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff);
2101 __asm__ __volatile__("flush %0" : : "r" (ia + 3));
2102
2103 start++;
2104 }
2105}
2106
2107static void ktsb_phys_patch(void)
2108{
2109 extern unsigned int __swapper_tsb_phys_patch;
2110 extern unsigned int __swapper_tsb_phys_patch_end;
2111 unsigned long ktsb_pa;
2112
2113 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
2114 patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
2115 &__swapper_tsb_phys_patch_end, ktsb_pa);
2116#ifndef CONFIG_DEBUG_PAGEALLOC
2117 {
2118 extern unsigned int __swapper_4m_tsb_phys_patch;
2119 extern unsigned int __swapper_4m_tsb_phys_patch_end;
2120 ktsb_pa = (kern_base +
2121 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
2122 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
2123 &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
2124 }
2125#endif
2126}
2127
2128static void __init sun4v_ktsb_init(void)
2129{
2130 unsigned long ktsb_pa;
2131
2132 /* First KTSB for PAGE_SIZE mappings. */
2133 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
2134
2135 switch (PAGE_SIZE) {
2136 case 8 * 1024:
2137 default:
2138 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
2139 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
2140 break;
2141
2142 case 64 * 1024:
2143 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
2144 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
2145 break;
2146
2147 case 512 * 1024:
2148 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
2149 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
2150 break;
2151
2152 case 4 * 1024 * 1024:
2153 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
2154 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
2155 break;
2156 }
2157
2158 ktsb_descr[0].assoc = 1;
2159 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
2160 ktsb_descr[0].ctx_idx = 0;
2161 ktsb_descr[0].tsb_base = ktsb_pa;
2162 ktsb_descr[0].resv = 0;
2163
2164#ifndef CONFIG_DEBUG_PAGEALLOC
2165 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */
2166 ktsb_pa = (kern_base +
2167 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
2168
2169 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
2170 ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
2171 HV_PGSZ_MASK_256MB |
2172 HV_PGSZ_MASK_2GB |
2173 HV_PGSZ_MASK_16GB) &
2174 cpu_pgsz_mask);
2175 ktsb_descr[1].assoc = 1;
2176 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
2177 ktsb_descr[1].ctx_idx = 0;
2178 ktsb_descr[1].tsb_base = ktsb_pa;
2179 ktsb_descr[1].resv = 0;
2180#endif
2181}
2182
2183void sun4v_ktsb_register(void)
2184{
2185 unsigned long pa, ret;
2186
2187 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
2188
2189 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
2190 if (ret != 0) {
2191 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
2192 "errors with %lx\n", pa, ret);
2193 prom_halt();
2194 }
2195}
2196
2197static void __init sun4u_linear_pte_xor_finalize(void)
2198{
2199#ifndef CONFIG_DEBUG_PAGEALLOC
2200 /* This is where we would add Panther support for
2201 * 32MB and 256MB pages.
2202 */
2203#endif
2204}
2205
2206static void __init sun4v_linear_pte_xor_finalize(void)
2207{
2208 unsigned long pagecv_flag;
2209
2210 /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
2211 * enables MCD error. Do not set bit 9 on M7 processor.
2212 */
2213 switch (sun4v_chip_type) {
2214 case SUN4V_CHIP_SPARC_M7:
2215 case SUN4V_CHIP_SPARC_M8:
2216 case SUN4V_CHIP_SPARC_SN:
2217 pagecv_flag = 0x00;
2218 break;
2219 default:
2220 pagecv_flag = _PAGE_CV_4V;
2221 break;
2222 }
2223#ifndef CONFIG_DEBUG_PAGEALLOC
2224 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
2225 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2226 PAGE_OFFSET;
2227 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag |
2228 _PAGE_P_4V | _PAGE_W_4V);
2229 } else {
2230 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2231 }
2232
2233 if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
2234 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
2235 PAGE_OFFSET;
2236 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag |
2237 _PAGE_P_4V | _PAGE_W_4V);
2238 } else {
2239 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
2240 }
2241
2242 if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
2243 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
2244 PAGE_OFFSET;
2245 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag |
2246 _PAGE_P_4V | _PAGE_W_4V);
2247 } else {
2248 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
2249 }
2250#endif
2251}
2252
2253/* paging_init() sets up the page tables */
2254
2255static unsigned long last_valid_pfn;
2256
2257static void sun4u_pgprot_init(void);
2258static void sun4v_pgprot_init(void);
2259
2260static phys_addr_t __init available_memory(void)
2261{
2262 phys_addr_t available = 0ULL;
2263 phys_addr_t pa_start, pa_end;
2264 u64 i;
2265
2266 for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start,
2267 &pa_end, NULL)
2268 available = available + (pa_end - pa_start);
2269
2270 return available;
2271}
2272
2273#define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2274#define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2275#define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2276#define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2277#define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2278#define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2279
2280/* We need to exclude reserved regions. This exclusion will include
2281 * vmlinux and initrd. To be more precise the initrd size could be used to
2282 * compute a new lower limit because it is freed later during initialization.
2283 */
2284static void __init reduce_memory(phys_addr_t limit_ram)
2285{
2286 phys_addr_t avail_ram = available_memory();
2287 phys_addr_t pa_start, pa_end;
2288 u64 i;
2289
2290 if (limit_ram >= avail_ram)
2291 return;
2292
2293 for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start,
2294 &pa_end, NULL) {
2295 phys_addr_t region_size = pa_end - pa_start;
2296 phys_addr_t clip_start = pa_start;
2297
2298 avail_ram = avail_ram - region_size;
2299 /* Are we consuming too much? */
2300 if (avail_ram < limit_ram) {
2301 phys_addr_t give_back = limit_ram - avail_ram;
2302
2303 region_size = region_size - give_back;
2304 clip_start = clip_start + give_back;
2305 }
2306
2307 memblock_remove(clip_start, region_size);
2308
2309 if (avail_ram <= limit_ram)
2310 break;
2311 i = 0UL;
2312 }
2313}
2314
2315void __init paging_init(void)
2316{
2317 unsigned long end_pfn, shift, phys_base;
2318 unsigned long real_end, i;
2319
2320 setup_page_offset();
2321
2322 /* These build time checkes make sure that the dcache_dirty_cpu()
2323 * page->flags usage will work.
2324 *
2325 * When a page gets marked as dcache-dirty, we store the
2326 * cpu number starting at bit 32 in the page->flags. Also,
2327 * functions like clear_dcache_dirty_cpu use the cpu mask
2328 * in 13-bit signed-immediate instruction fields.
2329 */
2330
2331 /*
2332 * Page flags must not reach into upper 32 bits that are used
2333 * for the cpu number
2334 */
2335 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
2336
2337 /*
2338 * The bit fields placed in the high range must not reach below
2339 * the 32 bit boundary. Otherwise we cannot place the cpu field
2340 * at the 32 bit boundary.
2341 */
2342 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
2343 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
2344
2345 BUILD_BUG_ON(NR_CPUS > 4096);
2346
2347 kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
2348 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
2349
2350 /* Invalidate both kernel TSBs. */
2351 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
2352#ifndef CONFIG_DEBUG_PAGEALLOC
2353 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2354#endif
2355
2356 /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde
2357 * bit on M7 processor. This is a conflicting usage of the same
2358 * bit. Enabling TTE.cv on M7 would turn on Memory Corruption
2359 * Detection error on all pages and this will lead to problems
2360 * later. Kernel does not run with MCD enabled and hence rest
2361 * of the required steps to fully configure memory corruption
2362 * detection are not taken. We need to ensure TTE.mcde is not
2363 * set on M7 processor. Compute the value of cacheability
2364 * flag for use later taking this into consideration.
2365 */
2366 switch (sun4v_chip_type) {
2367 case SUN4V_CHIP_SPARC_M7:
2368 case SUN4V_CHIP_SPARC_M8:
2369 case SUN4V_CHIP_SPARC_SN:
2370 page_cache4v_flag = _PAGE_CP_4V;
2371 break;
2372 default:
2373 page_cache4v_flag = _PAGE_CACHE_4V;
2374 break;
2375 }
2376
2377 if (tlb_type == hypervisor)
2378 sun4v_pgprot_init();
2379 else
2380 sun4u_pgprot_init();
2381
2382 if (tlb_type == cheetah_plus ||
2383 tlb_type == hypervisor) {
2384 tsb_phys_patch();
2385 ktsb_phys_patch();
2386 }
2387
2388 if (tlb_type == hypervisor)
2389 sun4v_patch_tlb_handlers();
2390
2391 /* Find available physical memory...
2392 *
2393 * Read it twice in order to work around a bug in openfirmware.
2394 * The call to grab this table itself can cause openfirmware to
2395 * allocate memory, which in turn can take away some space from
2396 * the list of available memory. Reading it twice makes sure
2397 * we really do get the final value.
2398 */
2399 read_obp_translations();
2400 read_obp_memory("reg", &pall[0], &pall_ents);
2401 read_obp_memory("available", &pavail[0], &pavail_ents);
2402 read_obp_memory("available", &pavail[0], &pavail_ents);
2403
2404 phys_base = 0xffffffffffffffffUL;
2405 for (i = 0; i < pavail_ents; i++) {
2406 phys_base = min(phys_base, pavail[i].phys_addr);
2407 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
2408 }
2409
2410 memblock_reserve(kern_base, kern_size);
2411
2412 find_ramdisk(phys_base);
2413
2414 if (cmdline_memory_size)
2415 reduce_memory(cmdline_memory_size);
2416
2417 memblock_allow_resize();
2418 memblock_dump_all();
2419
2420 set_bit(0, mmu_context_bmap);
2421
2422 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
2423
2424 real_end = (unsigned long)_end;
2425 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
2426 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
2427 num_kernel_image_mappings);
2428
2429 /* Set kernel pgd to upper alias so physical page computations
2430 * work.
2431 */
2432 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
2433
2434 memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
2435
2436 inherit_prom_mappings();
2437
2438 /* Ok, we can use our TLB miss and window trap handlers safely. */
2439 setup_tba();
2440
2441 __flush_tlb_all();
2442
2443 prom_build_devicetree();
2444 of_populate_present_mask();
2445#ifndef CONFIG_SMP
2446 of_fill_in_cpu_data();
2447#endif
2448
2449 if (tlb_type == hypervisor) {
2450 sun4v_mdesc_init();
2451 mdesc_populate_present_mask(cpu_all_mask);
2452#ifndef CONFIG_SMP
2453 mdesc_fill_in_cpu_data(cpu_all_mask);
2454#endif
2455 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
2456
2457 sun4v_linear_pte_xor_finalize();
2458
2459 sun4v_ktsb_init();
2460 sun4v_ktsb_register();
2461 } else {
2462 unsigned long impl, ver;
2463
2464 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
2465 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
2466
2467 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
2468 impl = ((ver >> 32) & 0xffff);
2469 if (impl == PANTHER_IMPL)
2470 cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
2471 HV_PGSZ_MASK_256MB);
2472
2473 sun4u_linear_pte_xor_finalize();
2474 }
2475
2476 /* Flush the TLBs and the 4M TSB so that the updated linear
2477 * pte XOR settings are realized for all mappings.
2478 */
2479 __flush_tlb_all();
2480#ifndef CONFIG_DEBUG_PAGEALLOC
2481 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2482#endif
2483 __flush_tlb_all();
2484
2485 /* Setup bootmem... */
2486 last_valid_pfn = end_pfn = bootmem_init(phys_base);
2487
2488 kernel_physical_mapping_init();
2489
2490 {
2491 unsigned long max_zone_pfns[MAX_NR_ZONES];
2492
2493 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
2494
2495 max_zone_pfns[ZONE_NORMAL] = end_pfn;
2496
2497 free_area_init_nodes(max_zone_pfns);
2498 }
2499
2500 printk("Booting Linux...\n");
2501}
2502
2503int page_in_phys_avail(unsigned long paddr)
2504{
2505 int i;
2506
2507 paddr &= PAGE_MASK;
2508
2509 for (i = 0; i < pavail_ents; i++) {
2510 unsigned long start, end;
2511
2512 start = pavail[i].phys_addr;
2513 end = start + pavail[i].reg_size;
2514
2515 if (paddr >= start && paddr < end)
2516 return 1;
2517 }
2518 if (paddr >= kern_base && paddr < (kern_base + kern_size))
2519 return 1;
2520#ifdef CONFIG_BLK_DEV_INITRD
2521 if (paddr >= __pa(initrd_start) &&
2522 paddr < __pa(PAGE_ALIGN(initrd_end)))
2523 return 1;
2524#endif
2525
2526 return 0;
2527}
2528
2529static void __init register_page_bootmem_info(void)
2530{
2531#ifdef CONFIG_NEED_MULTIPLE_NODES
2532 int i;
2533
2534 for_each_online_node(i)
2535 if (NODE_DATA(i)->node_spanned_pages)
2536 register_page_bootmem_info_node(NODE_DATA(i));
2537#endif
2538}
2539void __init mem_init(void)
2540{
2541 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2542
2543 free_all_bootmem();
2544
2545 /*
2546 * Must be done after boot memory is put on freelist, because here we
2547 * might set fields in deferred struct pages that have not yet been
2548 * initialized, and free_all_bootmem() initializes all the reserved
2549 * deferred pages for us.
2550 */
2551 register_page_bootmem_info();
2552
2553 /*
2554 * Set up the zero page, mark it reserved, so that page count
2555 * is not manipulated when freeing the page from user ptes.
2556 */
2557 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2558 if (mem_map_zero == NULL) {
2559 prom_printf("paging_init: Cannot alloc zero page.\n");
2560 prom_halt();
2561 }
2562 mark_page_reserved(mem_map_zero);
2563
2564 mem_init_print_info(NULL);
2565
2566 if (tlb_type == cheetah || tlb_type == cheetah_plus)
2567 cheetah_ecache_flush_init();
2568}
2569
2570void free_initmem(void)
2571{
2572 unsigned long addr, initend;
2573 int do_free = 1;
2574
2575 /* If the physical memory maps were trimmed by kernel command
2576 * line options, don't even try freeing this initmem stuff up.
2577 * The kernel image could have been in the trimmed out region
2578 * and if so the freeing below will free invalid page structs.
2579 */
2580 if (cmdline_memory_size)
2581 do_free = 0;
2582
2583 /*
2584 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2585 */
2586 addr = PAGE_ALIGN((unsigned long)(__init_begin));
2587 initend = (unsigned long)(__init_end) & PAGE_MASK;
2588 for (; addr < initend; addr += PAGE_SIZE) {
2589 unsigned long page;
2590
2591 page = (addr +
2592 ((unsigned long) __va(kern_base)) -
2593 ((unsigned long) KERNBASE));
2594 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2595
2596 if (do_free)
2597 free_reserved_page(virt_to_page(page));
2598 }
2599}
2600
2601#ifdef CONFIG_BLK_DEV_INITRD
2602void free_initrd_mem(unsigned long start, unsigned long end)
2603{
2604 free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM,
2605 "initrd");
2606}
2607#endif
2608
2609pgprot_t PAGE_KERNEL __read_mostly;
2610EXPORT_SYMBOL(PAGE_KERNEL);
2611
2612pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2613pgprot_t PAGE_COPY __read_mostly;
2614
2615pgprot_t PAGE_SHARED __read_mostly;
2616EXPORT_SYMBOL(PAGE_SHARED);
2617
2618unsigned long pg_iobits __read_mostly;
2619
2620unsigned long _PAGE_IE __read_mostly;
2621EXPORT_SYMBOL(_PAGE_IE);
2622
2623unsigned long _PAGE_E __read_mostly;
2624EXPORT_SYMBOL(_PAGE_E);
2625
2626unsigned long _PAGE_CACHE __read_mostly;
2627EXPORT_SYMBOL(_PAGE_CACHE);
2628
2629#ifdef CONFIG_SPARSEMEM_VMEMMAP
2630int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2631 int node, struct vmem_altmap *altmap)
2632{
2633 unsigned long pte_base;
2634
2635 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2636 _PAGE_CP_4U | _PAGE_CV_4U |
2637 _PAGE_P_4U | _PAGE_W_4U);
2638 if (tlb_type == hypervisor)
2639 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2640 page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V);
2641
2642 pte_base |= _PAGE_PMD_HUGE;
2643
2644 vstart = vstart & PMD_MASK;
2645 vend = ALIGN(vend, PMD_SIZE);
2646 for (; vstart < vend; vstart += PMD_SIZE) {
2647 pgd_t *pgd = vmemmap_pgd_populate(vstart, node);
2648 unsigned long pte;
2649 pud_t *pud;
2650 pmd_t *pmd;
2651
2652 if (!pgd)
2653 return -ENOMEM;
2654
2655 pud = vmemmap_pud_populate(pgd, vstart, node);
2656 if (!pud)
2657 return -ENOMEM;
2658
2659 pmd = pmd_offset(pud, vstart);
2660 pte = pmd_val(*pmd);
2661 if (!(pte & _PAGE_VALID)) {
2662 void *block = vmemmap_alloc_block(PMD_SIZE, node);
2663
2664 if (!block)
2665 return -ENOMEM;
2666
2667 pmd_val(*pmd) = pte_base | __pa(block);
2668 }
2669 }
2670
2671 return 0;
2672}
2673
2674void vmemmap_free(unsigned long start, unsigned long end,
2675 struct vmem_altmap *altmap)
2676{
2677}
2678#endif /* CONFIG_SPARSEMEM_VMEMMAP */
2679
2680static void prot_init_common(unsigned long page_none,
2681 unsigned long page_shared,
2682 unsigned long page_copy,
2683 unsigned long page_readonly,
2684 unsigned long page_exec_bit)
2685{
2686 PAGE_COPY = __pgprot(page_copy);
2687 PAGE_SHARED = __pgprot(page_shared);
2688
2689 protection_map[0x0] = __pgprot(page_none);
2690 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2691 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2692 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2693 protection_map[0x4] = __pgprot(page_readonly);
2694 protection_map[0x5] = __pgprot(page_readonly);
2695 protection_map[0x6] = __pgprot(page_copy);
2696 protection_map[0x7] = __pgprot(page_copy);
2697 protection_map[0x8] = __pgprot(page_none);
2698 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2699 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2700 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2701 protection_map[0xc] = __pgprot(page_readonly);
2702 protection_map[0xd] = __pgprot(page_readonly);
2703 protection_map[0xe] = __pgprot(page_shared);
2704 protection_map[0xf] = __pgprot(page_shared);
2705}
2706
2707static void __init sun4u_pgprot_init(void)
2708{
2709 unsigned long page_none, page_shared, page_copy, page_readonly;
2710 unsigned long page_exec_bit;
2711 int i;
2712
2713 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2714 _PAGE_CACHE_4U | _PAGE_P_4U |
2715 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2716 _PAGE_EXEC_4U);
2717 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2718 _PAGE_CACHE_4U | _PAGE_P_4U |
2719 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2720 _PAGE_EXEC_4U | _PAGE_L_4U);
2721
2722 _PAGE_IE = _PAGE_IE_4U;
2723 _PAGE_E = _PAGE_E_4U;
2724 _PAGE_CACHE = _PAGE_CACHE_4U;
2725
2726 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2727 __ACCESS_BITS_4U | _PAGE_E_4U);
2728
2729#ifdef CONFIG_DEBUG_PAGEALLOC
2730 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2731#else
2732 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2733 PAGE_OFFSET;
2734#endif
2735 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2736 _PAGE_P_4U | _PAGE_W_4U);
2737
2738 for (i = 1; i < 4; i++)
2739 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2740
2741 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2742 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2743 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2744
2745
2746 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2747 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2748 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2749 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2750 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2751 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2752 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2753
2754 page_exec_bit = _PAGE_EXEC_4U;
2755
2756 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2757 page_exec_bit);
2758}
2759
2760static void __init sun4v_pgprot_init(void)
2761{
2762 unsigned long page_none, page_shared, page_copy, page_readonly;
2763 unsigned long page_exec_bit;
2764 int i;
2765
2766 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2767 page_cache4v_flag | _PAGE_P_4V |
2768 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2769 _PAGE_EXEC_4V);
2770 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2771
2772 _PAGE_IE = _PAGE_IE_4V;
2773 _PAGE_E = _PAGE_E_4V;
2774 _PAGE_CACHE = page_cache4v_flag;
2775
2776#ifdef CONFIG_DEBUG_PAGEALLOC
2777 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2778#else
2779 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2780 PAGE_OFFSET;
2781#endif
2782 kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V |
2783 _PAGE_W_4V);
2784
2785 for (i = 1; i < 4; i++)
2786 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2787
2788 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2789 __ACCESS_BITS_4V | _PAGE_E_4V);
2790
2791 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2792 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2793 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2794 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2795
2796 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag;
2797 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2798 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2799 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2800 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2801 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2802 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2803
2804 page_exec_bit = _PAGE_EXEC_4V;
2805
2806 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2807 page_exec_bit);
2808}
2809
2810unsigned long pte_sz_bits(unsigned long sz)
2811{
2812 if (tlb_type == hypervisor) {
2813 switch (sz) {
2814 case 8 * 1024:
2815 default:
2816 return _PAGE_SZ8K_4V;
2817 case 64 * 1024:
2818 return _PAGE_SZ64K_4V;
2819 case 512 * 1024:
2820 return _PAGE_SZ512K_4V;
2821 case 4 * 1024 * 1024:
2822 return _PAGE_SZ4MB_4V;
2823 }
2824 } else {
2825 switch (sz) {
2826 case 8 * 1024:
2827 default:
2828 return _PAGE_SZ8K_4U;
2829 case 64 * 1024:
2830 return _PAGE_SZ64K_4U;
2831 case 512 * 1024:
2832 return _PAGE_SZ512K_4U;
2833 case 4 * 1024 * 1024:
2834 return _PAGE_SZ4MB_4U;
2835 }
2836 }
2837}
2838
2839pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2840{
2841 pte_t pte;
2842
2843 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
2844 pte_val(pte) |= (((unsigned long)space) << 32);
2845 pte_val(pte) |= pte_sz_bits(page_size);
2846
2847 return pte;
2848}
2849
2850static unsigned long kern_large_tte(unsigned long paddr)
2851{
2852 unsigned long val;
2853
2854 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2855 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2856 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2857 if (tlb_type == hypervisor)
2858 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2859 page_cache4v_flag | _PAGE_P_4V |
2860 _PAGE_EXEC_4V | _PAGE_W_4V);
2861
2862 return val | paddr;
2863}
2864
2865/* If not locked, zap it. */
2866void __flush_tlb_all(void)
2867{
2868 unsigned long pstate;
2869 int i;
2870
2871 __asm__ __volatile__("flushw\n\t"
2872 "rdpr %%pstate, %0\n\t"
2873 "wrpr %0, %1, %%pstate"
2874 : "=r" (pstate)
2875 : "i" (PSTATE_IE));
2876 if (tlb_type == hypervisor) {
2877 sun4v_mmu_demap_all();
2878 } else if (tlb_type == spitfire) {
2879 for (i = 0; i < 64; i++) {
2880 /* Spitfire Errata #32 workaround */
2881 /* NOTE: Always runs on spitfire, so no
2882 * cheetah+ page size encodings.
2883 */
2884 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2885 "flush %%g6"
2886 : /* No outputs */
2887 : "r" (0),
2888 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2889
2890 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2891 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2892 "membar #Sync"
2893 : /* no outputs */
2894 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2895 spitfire_put_dtlb_data(i, 0x0UL);
2896 }
2897
2898 /* Spitfire Errata #32 workaround */
2899 /* NOTE: Always runs on spitfire, so no
2900 * cheetah+ page size encodings.
2901 */
2902 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2903 "flush %%g6"
2904 : /* No outputs */
2905 : "r" (0),
2906 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2907
2908 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2909 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2910 "membar #Sync"
2911 : /* no outputs */
2912 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2913 spitfire_put_itlb_data(i, 0x0UL);
2914 }
2915 }
2916 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2917 cheetah_flush_dtlb_all();
2918 cheetah_flush_itlb_all();
2919 }
2920 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2921 : : "r" (pstate));
2922}
2923
2924pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
2925 unsigned long address)
2926{
2927 struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
2928 pte_t *pte = NULL;
2929
2930 if (page)
2931 pte = (pte_t *) page_address(page);
2932
2933 return pte;
2934}
2935
2936pgtable_t pte_alloc_one(struct mm_struct *mm,
2937 unsigned long address)
2938{
2939 struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
2940 if (!page)
2941 return NULL;
2942 if (!pgtable_page_ctor(page)) {
2943 free_unref_page(page);
2944 return NULL;
2945 }
2946 return (pte_t *) page_address(page);
2947}
2948
2949void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2950{
2951 free_page((unsigned long)pte);
2952}
2953
2954static void __pte_free(pgtable_t pte)
2955{
2956 struct page *page = virt_to_page(pte);
2957
2958 pgtable_page_dtor(page);
2959 __free_page(page);
2960}
2961
2962void pte_free(struct mm_struct *mm, pgtable_t pte)
2963{
2964 __pte_free(pte);
2965}
2966
2967void pgtable_free(void *table, bool is_page)
2968{
2969 if (is_page)
2970 __pte_free(table);
2971 else
2972 kmem_cache_free(pgtable_cache, table);
2973}
2974
2975#ifdef CONFIG_TRANSPARENT_HUGEPAGE
2976void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2977 pmd_t *pmd)
2978{
2979 unsigned long pte, flags;
2980 struct mm_struct *mm;
2981 pmd_t entry = *pmd;
2982
2983 if (!pmd_large(entry) || !pmd_young(entry))
2984 return;
2985
2986 pte = pmd_val(entry);
2987
2988 /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */
2989 if (!(pte & _PAGE_VALID))
2990 return;
2991
2992 /* We are fabricating 8MB pages using 4MB real hw pages. */
2993 pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
2994
2995 mm = vma->vm_mm;
2996
2997 spin_lock_irqsave(&mm->context.lock, flags);
2998
2999 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
3000 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
3001 addr, pte);
3002
3003 spin_unlock_irqrestore(&mm->context.lock, flags);
3004}
3005#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
3006
3007#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
3008static void context_reload(void *__data)
3009{
3010 struct mm_struct *mm = __data;
3011
3012 if (mm == current->mm)
3013 load_secondary_context(mm);
3014}
3015
3016void hugetlb_setup(struct pt_regs *regs)
3017{
3018 struct mm_struct *mm = current->mm;
3019 struct tsb_config *tp;
3020
3021 if (faulthandler_disabled() || !mm) {
3022 const struct exception_table_entry *entry;
3023
3024 entry = search_exception_tables(regs->tpc);
3025 if (entry) {
3026 regs->tpc = entry->fixup;
3027 regs->tnpc = regs->tpc + 4;
3028 return;
3029 }
3030 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
3031 die_if_kernel("HugeTSB in atomic", regs);
3032 }
3033
3034 tp = &mm->context.tsb_block[MM_TSB_HUGE];
3035 if (likely(tp->tsb == NULL))
3036 tsb_grow(mm, MM_TSB_HUGE, 0);
3037
3038 tsb_context_switch(mm);
3039 smp_tsb_sync(mm);
3040
3041 /* On UltraSPARC-III+ and later, configure the second half of
3042 * the Data-TLB for huge pages.
3043 */
3044 if (tlb_type == cheetah_plus) {
3045 bool need_context_reload = false;
3046 unsigned long ctx;
3047
3048 spin_lock_irq(&ctx_alloc_lock);
3049 ctx = mm->context.sparc64_ctx_val;
3050 ctx &= ~CTX_PGSZ_MASK;
3051 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
3052 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
3053
3054 if (ctx != mm->context.sparc64_ctx_val) {
3055 /* When changing the page size fields, we
3056 * must perform a context flush so that no
3057 * stale entries match. This flush must
3058 * occur with the original context register
3059 * settings.
3060 */
3061 do_flush_tlb_mm(mm);
3062
3063 /* Reload the context register of all processors
3064 * also executing in this address space.
3065 */
3066 mm->context.sparc64_ctx_val = ctx;
3067 need_context_reload = true;
3068 }
3069 spin_unlock_irq(&ctx_alloc_lock);
3070
3071 if (need_context_reload)
3072 on_each_cpu(context_reload, mm, 0);
3073 }
3074}
3075#endif
3076
3077static struct resource code_resource = {
3078 .name = "Kernel code",
3079 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3080};
3081
3082static struct resource data_resource = {
3083 .name = "Kernel data",
3084 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3085};
3086
3087static struct resource bss_resource = {
3088 .name = "Kernel bss",
3089 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3090};
3091
3092static inline resource_size_t compute_kern_paddr(void *addr)
3093{
3094 return (resource_size_t) (addr - KERNBASE + kern_base);
3095}
3096
3097static void __init kernel_lds_init(void)
3098{
3099 code_resource.start = compute_kern_paddr(_text);
3100 code_resource.end = compute_kern_paddr(_etext - 1);
3101 data_resource.start = compute_kern_paddr(_etext);
3102 data_resource.end = compute_kern_paddr(_edata - 1);
3103 bss_resource.start = compute_kern_paddr(__bss_start);
3104 bss_resource.end = compute_kern_paddr(_end - 1);
3105}
3106
3107static int __init report_memory(void)
3108{
3109 int i;
3110 struct resource *res;
3111
3112 kernel_lds_init();
3113
3114 for (i = 0; i < pavail_ents; i++) {
3115 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
3116
3117 if (!res) {
3118 pr_warn("Failed to allocate source.\n");
3119 break;
3120 }
3121
3122 res->name = "System RAM";
3123 res->start = pavail[i].phys_addr;
3124 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1;
3125 res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM;
3126
3127 if (insert_resource(&iomem_resource, res) < 0) {
3128 pr_warn("Resource insertion failed.\n");
3129 break;
3130 }
3131
3132 insert_resource(res, &code_resource);
3133 insert_resource(res, &data_resource);
3134 insert_resource(res, &bss_resource);
3135 }
3136
3137 return 0;
3138}
3139arch_initcall(report_memory);
3140
3141#ifdef CONFIG_SMP
3142#define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range
3143#else
3144#define do_flush_tlb_kernel_range __flush_tlb_kernel_range
3145#endif
3146
3147void flush_tlb_kernel_range(unsigned long start, unsigned long end)
3148{
3149 if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
3150 if (start < LOW_OBP_ADDRESS) {
3151 flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
3152 do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
3153 }
3154 if (end > HI_OBP_ADDRESS) {
3155 flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
3156 do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
3157 }
3158 } else {
3159 flush_tsb_kernel_range(start, end);
3160 do_flush_tlb_kernel_range(start, end);
3161 }
3162}
3163
3164void copy_user_highpage(struct page *to, struct page *from,
3165 unsigned long vaddr, struct vm_area_struct *vma)
3166{
3167 char *vfrom, *vto;
3168
3169 vfrom = kmap_atomic(from);
3170 vto = kmap_atomic(to);
3171 copy_user_page(vto, vfrom, vaddr, to);
3172 kunmap_atomic(vto);
3173 kunmap_atomic(vfrom);
3174
3175 /* If this page has ADI enabled, copy over any ADI tags
3176 * as well
3177 */
3178 if (vma->vm_flags & VM_SPARC_ADI) {
3179 unsigned long pfrom, pto, i, adi_tag;
3180
3181 pfrom = page_to_phys(from);
3182 pto = page_to_phys(to);
3183
3184 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
3185 asm volatile("ldxa [%1] %2, %0\n\t"
3186 : "=r" (adi_tag)
3187 : "r" (i), "i" (ASI_MCD_REAL));
3188 asm volatile("stxa %0, [%1] %2\n\t"
3189 :
3190 : "r" (adi_tag), "r" (pto),
3191 "i" (ASI_MCD_REAL));
3192 pto += adi_blksize();
3193 }
3194 asm volatile("membar #Sync\n\t");
3195 }
3196}
3197EXPORT_SYMBOL(copy_user_highpage);
3198
3199void copy_highpage(struct page *to, struct page *from)
3200{
3201 char *vfrom, *vto;
3202
3203 vfrom = kmap_atomic(from);
3204 vto = kmap_atomic(to);
3205 copy_page(vto, vfrom);
3206 kunmap_atomic(vto);
3207 kunmap_atomic(vfrom);
3208
3209 /* If this platform is ADI enabled, copy any ADI tags
3210 * as well
3211 */
3212 if (adi_capable()) {
3213 unsigned long pfrom, pto, i, adi_tag;
3214
3215 pfrom = page_to_phys(from);
3216 pto = page_to_phys(to);
3217
3218 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
3219 asm volatile("ldxa [%1] %2, %0\n\t"
3220 : "=r" (adi_tag)
3221 : "r" (i), "i" (ASI_MCD_REAL));
3222 asm volatile("stxa %0, [%1] %2\n\t"
3223 :
3224 : "r" (adi_tag), "r" (pto),
3225 "i" (ASI_MCD_REAL));
3226 pto += adi_blksize();
3227 }
3228 asm volatile("membar #Sync\n\t");
3229 }
3230}
3231EXPORT_SYMBOL(copy_highpage);
1/*
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8#include <linux/module.h>
9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/string.h>
12#include <linux/init.h>
13#include <linux/bootmem.h>
14#include <linux/mm.h>
15#include <linux/hugetlb.h>
16#include <linux/initrd.h>
17#include <linux/swap.h>
18#include <linux/pagemap.h>
19#include <linux/poison.h>
20#include <linux/fs.h>
21#include <linux/seq_file.h>
22#include <linux/kprobes.h>
23#include <linux/cache.h>
24#include <linux/sort.h>
25#include <linux/percpu.h>
26#include <linux/memblock.h>
27#include <linux/mmzone.h>
28#include <linux/gfp.h>
29
30#include <asm/head.h>
31#include <asm/page.h>
32#include <asm/pgalloc.h>
33#include <asm/pgtable.h>
34#include <asm/oplib.h>
35#include <asm/iommu.h>
36#include <asm/io.h>
37#include <asm/uaccess.h>
38#include <asm/mmu_context.h>
39#include <asm/tlbflush.h>
40#include <asm/dma.h>
41#include <asm/starfire.h>
42#include <asm/tlb.h>
43#include <asm/spitfire.h>
44#include <asm/sections.h>
45#include <asm/tsb.h>
46#include <asm/hypervisor.h>
47#include <asm/prom.h>
48#include <asm/mdesc.h>
49#include <asm/cpudata.h>
50#include <asm/irq.h>
51
52#include "init_64.h"
53
54unsigned long kern_linear_pte_xor[2] __read_mostly;
55
56/* A bitmap, one bit for every 256MB of physical memory. If the bit
57 * is clear, we should use a 4MB page (via kern_linear_pte_xor[0]) else
58 * if set we should use a 256MB page (via kern_linear_pte_xor[1]).
59 */
60unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
61
62#ifndef CONFIG_DEBUG_PAGEALLOC
63/* A special kernel TSB for 4MB and 256MB linear mappings.
64 * Space is allocated for this right after the trap table
65 * in arch/sparc64/kernel/head.S
66 */
67extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
68#endif
69
70#define MAX_BANKS 32
71
72static struct linux_prom64_registers pavail[MAX_BANKS] __devinitdata;
73static int pavail_ents __devinitdata;
74
75static int cmp_p64(const void *a, const void *b)
76{
77 const struct linux_prom64_registers *x = a, *y = b;
78
79 if (x->phys_addr > y->phys_addr)
80 return 1;
81 if (x->phys_addr < y->phys_addr)
82 return -1;
83 return 0;
84}
85
86static void __init read_obp_memory(const char *property,
87 struct linux_prom64_registers *regs,
88 int *num_ents)
89{
90 phandle node = prom_finddevice("/memory");
91 int prop_size = prom_getproplen(node, property);
92 int ents, ret, i;
93
94 ents = prop_size / sizeof(struct linux_prom64_registers);
95 if (ents > MAX_BANKS) {
96 prom_printf("The machine has more %s property entries than "
97 "this kernel can support (%d).\n",
98 property, MAX_BANKS);
99 prom_halt();
100 }
101
102 ret = prom_getproperty(node, property, (char *) regs, prop_size);
103 if (ret == -1) {
104 prom_printf("Couldn't get %s property from /memory.\n");
105 prom_halt();
106 }
107
108 /* Sanitize what we got from the firmware, by page aligning
109 * everything.
110 */
111 for (i = 0; i < ents; i++) {
112 unsigned long base, size;
113
114 base = regs[i].phys_addr;
115 size = regs[i].reg_size;
116
117 size &= PAGE_MASK;
118 if (base & ~PAGE_MASK) {
119 unsigned long new_base = PAGE_ALIGN(base);
120
121 size -= new_base - base;
122 if ((long) size < 0L)
123 size = 0UL;
124 base = new_base;
125 }
126 if (size == 0UL) {
127 /* If it is empty, simply get rid of it.
128 * This simplifies the logic of the other
129 * functions that process these arrays.
130 */
131 memmove(®s[i], ®s[i + 1],
132 (ents - i - 1) * sizeof(regs[0]));
133 i--;
134 ents--;
135 continue;
136 }
137 regs[i].phys_addr = base;
138 regs[i].reg_size = size;
139 }
140
141 *num_ents = ents;
142
143 sort(regs, ents, sizeof(struct linux_prom64_registers),
144 cmp_p64, NULL);
145}
146
147unsigned long sparc64_valid_addr_bitmap[VALID_ADDR_BITMAP_BYTES /
148 sizeof(unsigned long)];
149EXPORT_SYMBOL(sparc64_valid_addr_bitmap);
150
151/* Kernel physical address base and size in bytes. */
152unsigned long kern_base __read_mostly;
153unsigned long kern_size __read_mostly;
154
155/* Initial ramdisk setup */
156extern unsigned long sparc_ramdisk_image64;
157extern unsigned int sparc_ramdisk_image;
158extern unsigned int sparc_ramdisk_size;
159
160struct page *mem_map_zero __read_mostly;
161EXPORT_SYMBOL(mem_map_zero);
162
163unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
164
165unsigned long sparc64_kern_pri_context __read_mostly;
166unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
167unsigned long sparc64_kern_sec_context __read_mostly;
168
169int num_kernel_image_mappings;
170
171#ifdef CONFIG_DEBUG_DCFLUSH
172atomic_t dcpage_flushes = ATOMIC_INIT(0);
173#ifdef CONFIG_SMP
174atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
175#endif
176#endif
177
178inline void flush_dcache_page_impl(struct page *page)
179{
180 BUG_ON(tlb_type == hypervisor);
181#ifdef CONFIG_DEBUG_DCFLUSH
182 atomic_inc(&dcpage_flushes);
183#endif
184
185#ifdef DCACHE_ALIASING_POSSIBLE
186 __flush_dcache_page(page_address(page),
187 ((tlb_type == spitfire) &&
188 page_mapping(page) != NULL));
189#else
190 if (page_mapping(page) != NULL &&
191 tlb_type == spitfire)
192 __flush_icache_page(__pa(page_address(page)));
193#endif
194}
195
196#define PG_dcache_dirty PG_arch_1
197#define PG_dcache_cpu_shift 32UL
198#define PG_dcache_cpu_mask \
199 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
200
201#define dcache_dirty_cpu(page) \
202 (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
203
204static inline void set_dcache_dirty(struct page *page, int this_cpu)
205{
206 unsigned long mask = this_cpu;
207 unsigned long non_cpu_bits;
208
209 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
210 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
211
212 __asm__ __volatile__("1:\n\t"
213 "ldx [%2], %%g7\n\t"
214 "and %%g7, %1, %%g1\n\t"
215 "or %%g1, %0, %%g1\n\t"
216 "casx [%2], %%g7, %%g1\n\t"
217 "cmp %%g7, %%g1\n\t"
218 "bne,pn %%xcc, 1b\n\t"
219 " nop"
220 : /* no outputs */
221 : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags)
222 : "g1", "g7");
223}
224
225static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu)
226{
227 unsigned long mask = (1UL << PG_dcache_dirty);
228
229 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
230 "1:\n\t"
231 "ldx [%2], %%g7\n\t"
232 "srlx %%g7, %4, %%g1\n\t"
233 "and %%g1, %3, %%g1\n\t"
234 "cmp %%g1, %0\n\t"
235 "bne,pn %%icc, 2f\n\t"
236 " andn %%g7, %1, %%g1\n\t"
237 "casx [%2], %%g7, %%g1\n\t"
238 "cmp %%g7, %%g1\n\t"
239 "bne,pn %%xcc, 1b\n\t"
240 " nop\n"
241 "2:"
242 : /* no outputs */
243 : "r" (cpu), "r" (mask), "r" (&page->flags),
244 "i" (PG_dcache_cpu_mask),
245 "i" (PG_dcache_cpu_shift)
246 : "g1", "g7");
247}
248
249static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
250{
251 unsigned long tsb_addr = (unsigned long) ent;
252
253 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
254 tsb_addr = __pa(tsb_addr);
255
256 __tsb_insert(tsb_addr, tag, pte);
257}
258
259unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
260unsigned long _PAGE_SZBITS __read_mostly;
261
262static void flush_dcache(unsigned long pfn)
263{
264 struct page *page;
265
266 page = pfn_to_page(pfn);
267 if (page) {
268 unsigned long pg_flags;
269
270 pg_flags = page->flags;
271 if (pg_flags & (1UL << PG_dcache_dirty)) {
272 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
273 PG_dcache_cpu_mask);
274 int this_cpu = get_cpu();
275
276 /* This is just to optimize away some function calls
277 * in the SMP case.
278 */
279 if (cpu == this_cpu)
280 flush_dcache_page_impl(page);
281 else
282 smp_flush_dcache_page_impl(page, cpu);
283
284 clear_dcache_dirty_cpu(page, cpu);
285
286 put_cpu();
287 }
288 }
289}
290
291void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep)
292{
293 struct mm_struct *mm;
294 struct tsb *tsb;
295 unsigned long tag, flags;
296 unsigned long tsb_index, tsb_hash_shift;
297 pte_t pte = *ptep;
298
299 if (tlb_type != hypervisor) {
300 unsigned long pfn = pte_pfn(pte);
301
302 if (pfn_valid(pfn))
303 flush_dcache(pfn);
304 }
305
306 mm = vma->vm_mm;
307
308 tsb_index = MM_TSB_BASE;
309 tsb_hash_shift = PAGE_SHIFT;
310
311 spin_lock_irqsave(&mm->context.lock, flags);
312
313#ifdef CONFIG_HUGETLB_PAGE
314 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) {
315 if ((tlb_type == hypervisor &&
316 (pte_val(pte) & _PAGE_SZALL_4V) == _PAGE_SZHUGE_4V) ||
317 (tlb_type != hypervisor &&
318 (pte_val(pte) & _PAGE_SZALL_4U) == _PAGE_SZHUGE_4U)) {
319 tsb_index = MM_TSB_HUGE;
320 tsb_hash_shift = HPAGE_SHIFT;
321 }
322 }
323#endif
324
325 tsb = mm->context.tsb_block[tsb_index].tsb;
326 tsb += ((address >> tsb_hash_shift) &
327 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
328 tag = (address >> 22UL);
329 tsb_insert(tsb, tag, pte_val(pte));
330
331 spin_unlock_irqrestore(&mm->context.lock, flags);
332}
333
334void flush_dcache_page(struct page *page)
335{
336 struct address_space *mapping;
337 int this_cpu;
338
339 if (tlb_type == hypervisor)
340 return;
341
342 /* Do not bother with the expensive D-cache flush if it
343 * is merely the zero page. The 'bigcore' testcase in GDB
344 * causes this case to run millions of times.
345 */
346 if (page == ZERO_PAGE(0))
347 return;
348
349 this_cpu = get_cpu();
350
351 mapping = page_mapping(page);
352 if (mapping && !mapping_mapped(mapping)) {
353 int dirty = test_bit(PG_dcache_dirty, &page->flags);
354 if (dirty) {
355 int dirty_cpu = dcache_dirty_cpu(page);
356
357 if (dirty_cpu == this_cpu)
358 goto out;
359 smp_flush_dcache_page_impl(page, dirty_cpu);
360 }
361 set_dcache_dirty(page, this_cpu);
362 } else {
363 /* We could delay the flush for the !page_mapping
364 * case too. But that case is for exec env/arg
365 * pages and those are %99 certainly going to get
366 * faulted into the tlb (and thus flushed) anyways.
367 */
368 flush_dcache_page_impl(page);
369 }
370
371out:
372 put_cpu();
373}
374EXPORT_SYMBOL(flush_dcache_page);
375
376void __kprobes flush_icache_range(unsigned long start, unsigned long end)
377{
378 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
379 if (tlb_type == spitfire) {
380 unsigned long kaddr;
381
382 /* This code only runs on Spitfire cpus so this is
383 * why we can assume _PAGE_PADDR_4U.
384 */
385 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
386 unsigned long paddr, mask = _PAGE_PADDR_4U;
387
388 if (kaddr >= PAGE_OFFSET)
389 paddr = kaddr & mask;
390 else {
391 pgd_t *pgdp = pgd_offset_k(kaddr);
392 pud_t *pudp = pud_offset(pgdp, kaddr);
393 pmd_t *pmdp = pmd_offset(pudp, kaddr);
394 pte_t *ptep = pte_offset_kernel(pmdp, kaddr);
395
396 paddr = pte_val(*ptep) & mask;
397 }
398 __flush_icache_page(paddr);
399 }
400 }
401}
402EXPORT_SYMBOL(flush_icache_range);
403
404void mmu_info(struct seq_file *m)
405{
406 if (tlb_type == cheetah)
407 seq_printf(m, "MMU Type\t: Cheetah\n");
408 else if (tlb_type == cheetah_plus)
409 seq_printf(m, "MMU Type\t: Cheetah+\n");
410 else if (tlb_type == spitfire)
411 seq_printf(m, "MMU Type\t: Spitfire\n");
412 else if (tlb_type == hypervisor)
413 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
414 else
415 seq_printf(m, "MMU Type\t: ???\n");
416
417#ifdef CONFIG_DEBUG_DCFLUSH
418 seq_printf(m, "DCPageFlushes\t: %d\n",
419 atomic_read(&dcpage_flushes));
420#ifdef CONFIG_SMP
421 seq_printf(m, "DCPageFlushesXC\t: %d\n",
422 atomic_read(&dcpage_flushes_xcall));
423#endif /* CONFIG_SMP */
424#endif /* CONFIG_DEBUG_DCFLUSH */
425}
426
427struct linux_prom_translation prom_trans[512] __read_mostly;
428unsigned int prom_trans_ents __read_mostly;
429
430unsigned long kern_locked_tte_data;
431
432/* The obp translations are saved based on 8k pagesize, since obp can
433 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
434 * HI_OBP_ADDRESS range are handled in ktlb.S.
435 */
436static inline int in_obp_range(unsigned long vaddr)
437{
438 return (vaddr >= LOW_OBP_ADDRESS &&
439 vaddr < HI_OBP_ADDRESS);
440}
441
442static int cmp_ptrans(const void *a, const void *b)
443{
444 const struct linux_prom_translation *x = a, *y = b;
445
446 if (x->virt > y->virt)
447 return 1;
448 if (x->virt < y->virt)
449 return -1;
450 return 0;
451}
452
453/* Read OBP translations property into 'prom_trans[]'. */
454static void __init read_obp_translations(void)
455{
456 int n, node, ents, first, last, i;
457
458 node = prom_finddevice("/virtual-memory");
459 n = prom_getproplen(node, "translations");
460 if (unlikely(n == 0 || n == -1)) {
461 prom_printf("prom_mappings: Couldn't get size.\n");
462 prom_halt();
463 }
464 if (unlikely(n > sizeof(prom_trans))) {
465 prom_printf("prom_mappings: Size %Zd is too big.\n", n);
466 prom_halt();
467 }
468
469 if ((n = prom_getproperty(node, "translations",
470 (char *)&prom_trans[0],
471 sizeof(prom_trans))) == -1) {
472 prom_printf("prom_mappings: Couldn't get property.\n");
473 prom_halt();
474 }
475
476 n = n / sizeof(struct linux_prom_translation);
477
478 ents = n;
479
480 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
481 cmp_ptrans, NULL);
482
483 /* Now kick out all the non-OBP entries. */
484 for (i = 0; i < ents; i++) {
485 if (in_obp_range(prom_trans[i].virt))
486 break;
487 }
488 first = i;
489 for (; i < ents; i++) {
490 if (!in_obp_range(prom_trans[i].virt))
491 break;
492 }
493 last = i;
494
495 for (i = 0; i < (last - first); i++) {
496 struct linux_prom_translation *src = &prom_trans[i + first];
497 struct linux_prom_translation *dest = &prom_trans[i];
498
499 *dest = *src;
500 }
501 for (; i < ents; i++) {
502 struct linux_prom_translation *dest = &prom_trans[i];
503 dest->virt = dest->size = dest->data = 0x0UL;
504 }
505
506 prom_trans_ents = last - first;
507
508 if (tlb_type == spitfire) {
509 /* Clear diag TTE bits. */
510 for (i = 0; i < prom_trans_ents; i++)
511 prom_trans[i].data &= ~0x0003fe0000000000UL;
512 }
513
514 /* Force execute bit on. */
515 for (i = 0; i < prom_trans_ents; i++)
516 prom_trans[i].data |= (tlb_type == hypervisor ?
517 _PAGE_EXEC_4V : _PAGE_EXEC_4U);
518}
519
520static void __init hypervisor_tlb_lock(unsigned long vaddr,
521 unsigned long pte,
522 unsigned long mmu)
523{
524 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
525
526 if (ret != 0) {
527 prom_printf("hypervisor_tlb_lock[%lx:%lx:%lx:%lx]: "
528 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
529 prom_halt();
530 }
531}
532
533static unsigned long kern_large_tte(unsigned long paddr);
534
535static void __init remap_kernel(void)
536{
537 unsigned long phys_page, tte_vaddr, tte_data;
538 int i, tlb_ent = sparc64_highest_locked_tlbent();
539
540 tte_vaddr = (unsigned long) KERNBASE;
541 phys_page = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
542 tte_data = kern_large_tte(phys_page);
543
544 kern_locked_tte_data = tte_data;
545
546 /* Now lock us into the TLBs via Hypervisor or OBP. */
547 if (tlb_type == hypervisor) {
548 for (i = 0; i < num_kernel_image_mappings; i++) {
549 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
550 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
551 tte_vaddr += 0x400000;
552 tte_data += 0x400000;
553 }
554 } else {
555 for (i = 0; i < num_kernel_image_mappings; i++) {
556 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
557 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
558 tte_vaddr += 0x400000;
559 tte_data += 0x400000;
560 }
561 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
562 }
563 if (tlb_type == cheetah_plus) {
564 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
565 CTX_CHEETAH_PLUS_NUC);
566 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
567 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
568 }
569}
570
571
572static void __init inherit_prom_mappings(void)
573{
574 /* Now fixup OBP's idea about where we really are mapped. */
575 printk("Remapping the kernel... ");
576 remap_kernel();
577 printk("done.\n");
578}
579
580void prom_world(int enter)
581{
582 if (!enter)
583 set_fs((mm_segment_t) { get_thread_current_ds() });
584
585 __asm__ __volatile__("flushw");
586}
587
588void __flush_dcache_range(unsigned long start, unsigned long end)
589{
590 unsigned long va;
591
592 if (tlb_type == spitfire) {
593 int n = 0;
594
595 for (va = start; va < end; va += 32) {
596 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
597 if (++n >= 512)
598 break;
599 }
600 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
601 start = __pa(start);
602 end = __pa(end);
603 for (va = start; va < end; va += 32)
604 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
605 "membar #Sync"
606 : /* no outputs */
607 : "r" (va),
608 "i" (ASI_DCACHE_INVALIDATE));
609 }
610}
611EXPORT_SYMBOL(__flush_dcache_range);
612
613/* get_new_mmu_context() uses "cache + 1". */
614DEFINE_SPINLOCK(ctx_alloc_lock);
615unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
616#define MAX_CTX_NR (1UL << CTX_NR_BITS)
617#define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
618DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
619
620/* Caller does TLB context flushing on local CPU if necessary.
621 * The caller also ensures that CTX_VALID(mm->context) is false.
622 *
623 * We must be careful about boundary cases so that we never
624 * let the user have CTX 0 (nucleus) or we ever use a CTX
625 * version of zero (and thus NO_CONTEXT would not be caught
626 * by version mis-match tests in mmu_context.h).
627 *
628 * Always invoked with interrupts disabled.
629 */
630void get_new_mmu_context(struct mm_struct *mm)
631{
632 unsigned long ctx, new_ctx;
633 unsigned long orig_pgsz_bits;
634 unsigned long flags;
635 int new_version;
636
637 spin_lock_irqsave(&ctx_alloc_lock, flags);
638 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
639 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
640 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
641 new_version = 0;
642 if (new_ctx >= (1 << CTX_NR_BITS)) {
643 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
644 if (new_ctx >= ctx) {
645 int i;
646 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
647 CTX_FIRST_VERSION;
648 if (new_ctx == 1)
649 new_ctx = CTX_FIRST_VERSION;
650
651 /* Don't call memset, for 16 entries that's just
652 * plain silly...
653 */
654 mmu_context_bmap[0] = 3;
655 mmu_context_bmap[1] = 0;
656 mmu_context_bmap[2] = 0;
657 mmu_context_bmap[3] = 0;
658 for (i = 4; i < CTX_BMAP_SLOTS; i += 4) {
659 mmu_context_bmap[i + 0] = 0;
660 mmu_context_bmap[i + 1] = 0;
661 mmu_context_bmap[i + 2] = 0;
662 mmu_context_bmap[i + 3] = 0;
663 }
664 new_version = 1;
665 goto out;
666 }
667 }
668 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
669 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
670out:
671 tlb_context_cache = new_ctx;
672 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
673 spin_unlock_irqrestore(&ctx_alloc_lock, flags);
674
675 if (unlikely(new_version))
676 smp_new_mmu_context_version();
677}
678
679static int numa_enabled = 1;
680static int numa_debug;
681
682static int __init early_numa(char *p)
683{
684 if (!p)
685 return 0;
686
687 if (strstr(p, "off"))
688 numa_enabled = 0;
689
690 if (strstr(p, "debug"))
691 numa_debug = 1;
692
693 return 0;
694}
695early_param("numa", early_numa);
696
697#define numadbg(f, a...) \
698do { if (numa_debug) \
699 printk(KERN_INFO f, ## a); \
700} while (0)
701
702static void __init find_ramdisk(unsigned long phys_base)
703{
704#ifdef CONFIG_BLK_DEV_INITRD
705 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
706 unsigned long ramdisk_image;
707
708 /* Older versions of the bootloader only supported a
709 * 32-bit physical address for the ramdisk image
710 * location, stored at sparc_ramdisk_image. Newer
711 * SILO versions set sparc_ramdisk_image to zero and
712 * provide a full 64-bit physical address at
713 * sparc_ramdisk_image64.
714 */
715 ramdisk_image = sparc_ramdisk_image;
716 if (!ramdisk_image)
717 ramdisk_image = sparc_ramdisk_image64;
718
719 /* Another bootloader quirk. The bootloader normalizes
720 * the physical address to KERNBASE, so we have to
721 * factor that back out and add in the lowest valid
722 * physical page address to get the true physical address.
723 */
724 ramdisk_image -= KERNBASE;
725 ramdisk_image += phys_base;
726
727 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
728 ramdisk_image, sparc_ramdisk_size);
729
730 initrd_start = ramdisk_image;
731 initrd_end = ramdisk_image + sparc_ramdisk_size;
732
733 memblock_reserve(initrd_start, sparc_ramdisk_size);
734
735 initrd_start += PAGE_OFFSET;
736 initrd_end += PAGE_OFFSET;
737 }
738#endif
739}
740
741struct node_mem_mask {
742 unsigned long mask;
743 unsigned long val;
744};
745static struct node_mem_mask node_masks[MAX_NUMNODES];
746static int num_node_masks;
747
748int numa_cpu_lookup_table[NR_CPUS];
749cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
750
751#ifdef CONFIG_NEED_MULTIPLE_NODES
752
753struct mdesc_mblock {
754 u64 base;
755 u64 size;
756 u64 offset; /* RA-to-PA */
757};
758static struct mdesc_mblock *mblocks;
759static int num_mblocks;
760
761static unsigned long ra_to_pa(unsigned long addr)
762{
763 int i;
764
765 for (i = 0; i < num_mblocks; i++) {
766 struct mdesc_mblock *m = &mblocks[i];
767
768 if (addr >= m->base &&
769 addr < (m->base + m->size)) {
770 addr += m->offset;
771 break;
772 }
773 }
774 return addr;
775}
776
777static int find_node(unsigned long addr)
778{
779 int i;
780
781 addr = ra_to_pa(addr);
782 for (i = 0; i < num_node_masks; i++) {
783 struct node_mem_mask *p = &node_masks[i];
784
785 if ((addr & p->mask) == p->val)
786 return i;
787 }
788 return -1;
789}
790
791static u64 memblock_nid_range(u64 start, u64 end, int *nid)
792{
793 *nid = find_node(start);
794 start += PAGE_SIZE;
795 while (start < end) {
796 int n = find_node(start);
797
798 if (n != *nid)
799 break;
800 start += PAGE_SIZE;
801 }
802
803 if (start > end)
804 start = end;
805
806 return start;
807}
808#endif
809
810/* This must be invoked after performing all of the necessary
811 * memblock_set_node() calls for 'nid'. We need to be able to get
812 * correct data from get_pfn_range_for_nid().
813 */
814static void __init allocate_node_data(int nid)
815{
816 struct pglist_data *p;
817 unsigned long start_pfn, end_pfn;
818#ifdef CONFIG_NEED_MULTIPLE_NODES
819 unsigned long paddr;
820
821 paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid);
822 if (!paddr) {
823 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
824 prom_halt();
825 }
826 NODE_DATA(nid) = __va(paddr);
827 memset(NODE_DATA(nid), 0, sizeof(struct pglist_data));
828
829 NODE_DATA(nid)->node_id = nid;
830#endif
831
832 p = NODE_DATA(nid);
833
834 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
835 p->node_start_pfn = start_pfn;
836 p->node_spanned_pages = end_pfn - start_pfn;
837}
838
839static void init_node_masks_nonnuma(void)
840{
841 int i;
842
843 numadbg("Initializing tables for non-numa.\n");
844
845 node_masks[0].mask = node_masks[0].val = 0;
846 num_node_masks = 1;
847
848 for (i = 0; i < NR_CPUS; i++)
849 numa_cpu_lookup_table[i] = 0;
850
851 cpumask_setall(&numa_cpumask_lookup_table[0]);
852}
853
854#ifdef CONFIG_NEED_MULTIPLE_NODES
855struct pglist_data *node_data[MAX_NUMNODES];
856
857EXPORT_SYMBOL(numa_cpu_lookup_table);
858EXPORT_SYMBOL(numa_cpumask_lookup_table);
859EXPORT_SYMBOL(node_data);
860
861struct mdesc_mlgroup {
862 u64 node;
863 u64 latency;
864 u64 match;
865 u64 mask;
866};
867static struct mdesc_mlgroup *mlgroups;
868static int num_mlgroups;
869
870static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
871 u32 cfg_handle)
872{
873 u64 arc;
874
875 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
876 u64 target = mdesc_arc_target(md, arc);
877 const u64 *val;
878
879 val = mdesc_get_property(md, target,
880 "cfg-handle", NULL);
881 if (val && *val == cfg_handle)
882 return 0;
883 }
884 return -ENODEV;
885}
886
887static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
888 u32 cfg_handle)
889{
890 u64 arc, candidate, best_latency = ~(u64)0;
891
892 candidate = MDESC_NODE_NULL;
893 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
894 u64 target = mdesc_arc_target(md, arc);
895 const char *name = mdesc_node_name(md, target);
896 const u64 *val;
897
898 if (strcmp(name, "pio-latency-group"))
899 continue;
900
901 val = mdesc_get_property(md, target, "latency", NULL);
902 if (!val)
903 continue;
904
905 if (*val < best_latency) {
906 candidate = target;
907 best_latency = *val;
908 }
909 }
910
911 if (candidate == MDESC_NODE_NULL)
912 return -ENODEV;
913
914 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
915}
916
917int of_node_to_nid(struct device_node *dp)
918{
919 const struct linux_prom64_registers *regs;
920 struct mdesc_handle *md;
921 u32 cfg_handle;
922 int count, nid;
923 u64 grp;
924
925 /* This is the right thing to do on currently supported
926 * SUN4U NUMA platforms as well, as the PCI controller does
927 * not sit behind any particular memory controller.
928 */
929 if (!mlgroups)
930 return -1;
931
932 regs = of_get_property(dp, "reg", NULL);
933 if (!regs)
934 return -1;
935
936 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
937
938 md = mdesc_grab();
939
940 count = 0;
941 nid = -1;
942 mdesc_for_each_node_by_name(md, grp, "group") {
943 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
944 nid = count;
945 break;
946 }
947 count++;
948 }
949
950 mdesc_release(md);
951
952 return nid;
953}
954
955static void __init add_node_ranges(void)
956{
957 struct memblock_region *reg;
958
959 for_each_memblock(memory, reg) {
960 unsigned long size = reg->size;
961 unsigned long start, end;
962
963 start = reg->base;
964 end = start + size;
965 while (start < end) {
966 unsigned long this_end;
967 int nid;
968
969 this_end = memblock_nid_range(start, end, &nid);
970
971 numadbg("Setting memblock NUMA node nid[%d] "
972 "start[%lx] end[%lx]\n",
973 nid, start, this_end);
974
975 memblock_set_node(start, this_end - start, nid);
976 start = this_end;
977 }
978 }
979}
980
981static int __init grab_mlgroups(struct mdesc_handle *md)
982{
983 unsigned long paddr;
984 int count = 0;
985 u64 node;
986
987 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
988 count++;
989 if (!count)
990 return -ENOENT;
991
992 paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup),
993 SMP_CACHE_BYTES);
994 if (!paddr)
995 return -ENOMEM;
996
997 mlgroups = __va(paddr);
998 num_mlgroups = count;
999
1000 count = 0;
1001 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1002 struct mdesc_mlgroup *m = &mlgroups[count++];
1003 const u64 *val;
1004
1005 m->node = node;
1006
1007 val = mdesc_get_property(md, node, "latency", NULL);
1008 m->latency = *val;
1009 val = mdesc_get_property(md, node, "address-match", NULL);
1010 m->match = *val;
1011 val = mdesc_get_property(md, node, "address-mask", NULL);
1012 m->mask = *val;
1013
1014 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1015 "match[%llx] mask[%llx]\n",
1016 count - 1, m->node, m->latency, m->match, m->mask);
1017 }
1018
1019 return 0;
1020}
1021
1022static int __init grab_mblocks(struct mdesc_handle *md)
1023{
1024 unsigned long paddr;
1025 int count = 0;
1026 u64 node;
1027
1028 mdesc_for_each_node_by_name(md, node, "mblock")
1029 count++;
1030 if (!count)
1031 return -ENOENT;
1032
1033 paddr = memblock_alloc(count * sizeof(struct mdesc_mblock),
1034 SMP_CACHE_BYTES);
1035 if (!paddr)
1036 return -ENOMEM;
1037
1038 mblocks = __va(paddr);
1039 num_mblocks = count;
1040
1041 count = 0;
1042 mdesc_for_each_node_by_name(md, node, "mblock") {
1043 struct mdesc_mblock *m = &mblocks[count++];
1044 const u64 *val;
1045
1046 val = mdesc_get_property(md, node, "base", NULL);
1047 m->base = *val;
1048 val = mdesc_get_property(md, node, "size", NULL);
1049 m->size = *val;
1050 val = mdesc_get_property(md, node,
1051 "address-congruence-offset", NULL);
1052 m->offset = *val;
1053
1054 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1055 count - 1, m->base, m->size, m->offset);
1056 }
1057
1058 return 0;
1059}
1060
1061static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1062 u64 grp, cpumask_t *mask)
1063{
1064 u64 arc;
1065
1066 cpumask_clear(mask);
1067
1068 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1069 u64 target = mdesc_arc_target(md, arc);
1070 const char *name = mdesc_node_name(md, target);
1071 const u64 *id;
1072
1073 if (strcmp(name, "cpu"))
1074 continue;
1075 id = mdesc_get_property(md, target, "id", NULL);
1076 if (*id < nr_cpu_ids)
1077 cpumask_set_cpu(*id, mask);
1078 }
1079}
1080
1081static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1082{
1083 int i;
1084
1085 for (i = 0; i < num_mlgroups; i++) {
1086 struct mdesc_mlgroup *m = &mlgroups[i];
1087 if (m->node == node)
1088 return m;
1089 }
1090 return NULL;
1091}
1092
1093static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1094 int index)
1095{
1096 struct mdesc_mlgroup *candidate = NULL;
1097 u64 arc, best_latency = ~(u64)0;
1098 struct node_mem_mask *n;
1099
1100 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1101 u64 target = mdesc_arc_target(md, arc);
1102 struct mdesc_mlgroup *m = find_mlgroup(target);
1103 if (!m)
1104 continue;
1105 if (m->latency < best_latency) {
1106 candidate = m;
1107 best_latency = m->latency;
1108 }
1109 }
1110 if (!candidate)
1111 return -ENOENT;
1112
1113 if (num_node_masks != index) {
1114 printk(KERN_ERR "Inconsistent NUMA state, "
1115 "index[%d] != num_node_masks[%d]\n",
1116 index, num_node_masks);
1117 return -EINVAL;
1118 }
1119
1120 n = &node_masks[num_node_masks++];
1121
1122 n->mask = candidate->mask;
1123 n->val = candidate->match;
1124
1125 numadbg("NUMA NODE[%d]: mask[%lx] val[%lx] (latency[%llx])\n",
1126 index, n->mask, n->val, candidate->latency);
1127
1128 return 0;
1129}
1130
1131static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1132 int index)
1133{
1134 cpumask_t mask;
1135 int cpu;
1136
1137 numa_parse_mdesc_group_cpus(md, grp, &mask);
1138
1139 for_each_cpu(cpu, &mask)
1140 numa_cpu_lookup_table[cpu] = index;
1141 cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1142
1143 if (numa_debug) {
1144 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1145 for_each_cpu(cpu, &mask)
1146 printk("%d ", cpu);
1147 printk("]\n");
1148 }
1149
1150 return numa_attach_mlgroup(md, grp, index);
1151}
1152
1153static int __init numa_parse_mdesc(void)
1154{
1155 struct mdesc_handle *md = mdesc_grab();
1156 int i, err, count;
1157 u64 node;
1158
1159 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1160 if (node == MDESC_NODE_NULL) {
1161 mdesc_release(md);
1162 return -ENOENT;
1163 }
1164
1165 err = grab_mblocks(md);
1166 if (err < 0)
1167 goto out;
1168
1169 err = grab_mlgroups(md);
1170 if (err < 0)
1171 goto out;
1172
1173 count = 0;
1174 mdesc_for_each_node_by_name(md, node, "group") {
1175 err = numa_parse_mdesc_group(md, node, count);
1176 if (err < 0)
1177 break;
1178 count++;
1179 }
1180
1181 add_node_ranges();
1182
1183 for (i = 0; i < num_node_masks; i++) {
1184 allocate_node_data(i);
1185 node_set_online(i);
1186 }
1187
1188 err = 0;
1189out:
1190 mdesc_release(md);
1191 return err;
1192}
1193
1194static int __init numa_parse_jbus(void)
1195{
1196 unsigned long cpu, index;
1197
1198 /* NUMA node id is encoded in bits 36 and higher, and there is
1199 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1200 */
1201 index = 0;
1202 for_each_present_cpu(cpu) {
1203 numa_cpu_lookup_table[cpu] = index;
1204 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1205 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1206 node_masks[index].val = cpu << 36UL;
1207
1208 index++;
1209 }
1210 num_node_masks = index;
1211
1212 add_node_ranges();
1213
1214 for (index = 0; index < num_node_masks; index++) {
1215 allocate_node_data(index);
1216 node_set_online(index);
1217 }
1218
1219 return 0;
1220}
1221
1222static int __init numa_parse_sun4u(void)
1223{
1224 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1225 unsigned long ver;
1226
1227 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1228 if ((ver >> 32UL) == __JALAPENO_ID ||
1229 (ver >> 32UL) == __SERRANO_ID)
1230 return numa_parse_jbus();
1231 }
1232 return -1;
1233}
1234
1235static int __init bootmem_init_numa(void)
1236{
1237 int err = -1;
1238
1239 numadbg("bootmem_init_numa()\n");
1240
1241 if (numa_enabled) {
1242 if (tlb_type == hypervisor)
1243 err = numa_parse_mdesc();
1244 else
1245 err = numa_parse_sun4u();
1246 }
1247 return err;
1248}
1249
1250#else
1251
1252static int bootmem_init_numa(void)
1253{
1254 return -1;
1255}
1256
1257#endif
1258
1259static void __init bootmem_init_nonnuma(void)
1260{
1261 unsigned long top_of_ram = memblock_end_of_DRAM();
1262 unsigned long total_ram = memblock_phys_mem_size();
1263
1264 numadbg("bootmem_init_nonnuma()\n");
1265
1266 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1267 top_of_ram, total_ram);
1268 printk(KERN_INFO "Memory hole size: %ldMB\n",
1269 (top_of_ram - total_ram) >> 20);
1270
1271 init_node_masks_nonnuma();
1272 memblock_set_node(0, (phys_addr_t)ULLONG_MAX, 0);
1273 allocate_node_data(0);
1274 node_set_online(0);
1275}
1276
1277static unsigned long __init bootmem_init(unsigned long phys_base)
1278{
1279 unsigned long end_pfn;
1280
1281 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1282 max_pfn = max_low_pfn = end_pfn;
1283 min_low_pfn = (phys_base >> PAGE_SHIFT);
1284
1285 if (bootmem_init_numa() < 0)
1286 bootmem_init_nonnuma();
1287
1288 /* Dump memblock with node info. */
1289 memblock_dump_all();
1290
1291 /* XXX cpu notifier XXX */
1292
1293 sparse_memory_present_with_active_regions(MAX_NUMNODES);
1294 sparse_init();
1295
1296 return end_pfn;
1297}
1298
1299static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1300static int pall_ents __initdata;
1301
1302#ifdef CONFIG_DEBUG_PAGEALLOC
1303static unsigned long __ref kernel_map_range(unsigned long pstart,
1304 unsigned long pend, pgprot_t prot)
1305{
1306 unsigned long vstart = PAGE_OFFSET + pstart;
1307 unsigned long vend = PAGE_OFFSET + pend;
1308 unsigned long alloc_bytes = 0UL;
1309
1310 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1311 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1312 vstart, vend);
1313 prom_halt();
1314 }
1315
1316 while (vstart < vend) {
1317 unsigned long this_end, paddr = __pa(vstart);
1318 pgd_t *pgd = pgd_offset_k(vstart);
1319 pud_t *pud;
1320 pmd_t *pmd;
1321 pte_t *pte;
1322
1323 pud = pud_offset(pgd, vstart);
1324 if (pud_none(*pud)) {
1325 pmd_t *new;
1326
1327 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1328 alloc_bytes += PAGE_SIZE;
1329 pud_populate(&init_mm, pud, new);
1330 }
1331
1332 pmd = pmd_offset(pud, vstart);
1333 if (!pmd_present(*pmd)) {
1334 pte_t *new;
1335
1336 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1337 alloc_bytes += PAGE_SIZE;
1338 pmd_populate_kernel(&init_mm, pmd, new);
1339 }
1340
1341 pte = pte_offset_kernel(pmd, vstart);
1342 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1343 if (this_end > vend)
1344 this_end = vend;
1345
1346 while (vstart < this_end) {
1347 pte_val(*pte) = (paddr | pgprot_val(prot));
1348
1349 vstart += PAGE_SIZE;
1350 paddr += PAGE_SIZE;
1351 pte++;
1352 }
1353 }
1354
1355 return alloc_bytes;
1356}
1357
1358extern unsigned int kvmap_linear_patch[1];
1359#endif /* CONFIG_DEBUG_PAGEALLOC */
1360
1361static void __init mark_kpte_bitmap(unsigned long start, unsigned long end)
1362{
1363 const unsigned long shift_256MB = 28;
1364 const unsigned long mask_256MB = ((1UL << shift_256MB) - 1UL);
1365 const unsigned long size_256MB = (1UL << shift_256MB);
1366
1367 while (start < end) {
1368 long remains;
1369
1370 remains = end - start;
1371 if (remains < size_256MB)
1372 break;
1373
1374 if (start & mask_256MB) {
1375 start = (start + size_256MB) & ~mask_256MB;
1376 continue;
1377 }
1378
1379 while (remains >= size_256MB) {
1380 unsigned long index = start >> shift_256MB;
1381
1382 __set_bit(index, kpte_linear_bitmap);
1383
1384 start += size_256MB;
1385 remains -= size_256MB;
1386 }
1387 }
1388}
1389
1390static void __init init_kpte_bitmap(void)
1391{
1392 unsigned long i;
1393
1394 for (i = 0; i < pall_ents; i++) {
1395 unsigned long phys_start, phys_end;
1396
1397 phys_start = pall[i].phys_addr;
1398 phys_end = phys_start + pall[i].reg_size;
1399
1400 mark_kpte_bitmap(phys_start, phys_end);
1401 }
1402}
1403
1404static void __init kernel_physical_mapping_init(void)
1405{
1406#ifdef CONFIG_DEBUG_PAGEALLOC
1407 unsigned long i, mem_alloced = 0UL;
1408
1409 for (i = 0; i < pall_ents; i++) {
1410 unsigned long phys_start, phys_end;
1411
1412 phys_start = pall[i].phys_addr;
1413 phys_end = phys_start + pall[i].reg_size;
1414
1415 mem_alloced += kernel_map_range(phys_start, phys_end,
1416 PAGE_KERNEL);
1417 }
1418
1419 printk("Allocated %ld bytes for kernel page tables.\n",
1420 mem_alloced);
1421
1422 kvmap_linear_patch[0] = 0x01000000; /* nop */
1423 flushi(&kvmap_linear_patch[0]);
1424
1425 __flush_tlb_all();
1426#endif
1427}
1428
1429#ifdef CONFIG_DEBUG_PAGEALLOC
1430void kernel_map_pages(struct page *page, int numpages, int enable)
1431{
1432 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1433 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1434
1435 kernel_map_range(phys_start, phys_end,
1436 (enable ? PAGE_KERNEL : __pgprot(0)));
1437
1438 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1439 PAGE_OFFSET + phys_end);
1440
1441 /* we should perform an IPI and flush all tlbs,
1442 * but that can deadlock->flush only current cpu.
1443 */
1444 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1445 PAGE_OFFSET + phys_end);
1446}
1447#endif
1448
1449unsigned long __init find_ecache_flush_span(unsigned long size)
1450{
1451 int i;
1452
1453 for (i = 0; i < pavail_ents; i++) {
1454 if (pavail[i].reg_size >= size)
1455 return pavail[i].phys_addr;
1456 }
1457
1458 return ~0UL;
1459}
1460
1461static void __init tsb_phys_patch(void)
1462{
1463 struct tsb_ldquad_phys_patch_entry *pquad;
1464 struct tsb_phys_patch_entry *p;
1465
1466 pquad = &__tsb_ldquad_phys_patch;
1467 while (pquad < &__tsb_ldquad_phys_patch_end) {
1468 unsigned long addr = pquad->addr;
1469
1470 if (tlb_type == hypervisor)
1471 *(unsigned int *) addr = pquad->sun4v_insn;
1472 else
1473 *(unsigned int *) addr = pquad->sun4u_insn;
1474 wmb();
1475 __asm__ __volatile__("flush %0"
1476 : /* no outputs */
1477 : "r" (addr));
1478
1479 pquad++;
1480 }
1481
1482 p = &__tsb_phys_patch;
1483 while (p < &__tsb_phys_patch_end) {
1484 unsigned long addr = p->addr;
1485
1486 *(unsigned int *) addr = p->insn;
1487 wmb();
1488 __asm__ __volatile__("flush %0"
1489 : /* no outputs */
1490 : "r" (addr));
1491
1492 p++;
1493 }
1494}
1495
1496/* Don't mark as init, we give this to the Hypervisor. */
1497#ifndef CONFIG_DEBUG_PAGEALLOC
1498#define NUM_KTSB_DESCR 2
1499#else
1500#define NUM_KTSB_DESCR 1
1501#endif
1502static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
1503extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
1504
1505static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
1506{
1507 pa >>= KTSB_PHYS_SHIFT;
1508
1509 while (start < end) {
1510 unsigned int *ia = (unsigned int *)(unsigned long)*start;
1511
1512 ia[0] = (ia[0] & ~0x3fffff) | (pa >> 10);
1513 __asm__ __volatile__("flush %0" : : "r" (ia));
1514
1515 ia[1] = (ia[1] & ~0x3ff) | (pa & 0x3ff);
1516 __asm__ __volatile__("flush %0" : : "r" (ia + 1));
1517
1518 start++;
1519 }
1520}
1521
1522static void ktsb_phys_patch(void)
1523{
1524 extern unsigned int __swapper_tsb_phys_patch;
1525 extern unsigned int __swapper_tsb_phys_patch_end;
1526 unsigned long ktsb_pa;
1527
1528 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1529 patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
1530 &__swapper_tsb_phys_patch_end, ktsb_pa);
1531#ifndef CONFIG_DEBUG_PAGEALLOC
1532 {
1533 extern unsigned int __swapper_4m_tsb_phys_patch;
1534 extern unsigned int __swapper_4m_tsb_phys_patch_end;
1535 ktsb_pa = (kern_base +
1536 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1537 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
1538 &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
1539 }
1540#endif
1541}
1542
1543static void __init sun4v_ktsb_init(void)
1544{
1545 unsigned long ktsb_pa;
1546
1547 /* First KTSB for PAGE_SIZE mappings. */
1548 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
1549
1550 switch (PAGE_SIZE) {
1551 case 8 * 1024:
1552 default:
1553 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
1554 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
1555 break;
1556
1557 case 64 * 1024:
1558 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
1559 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
1560 break;
1561
1562 case 512 * 1024:
1563 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
1564 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
1565 break;
1566
1567 case 4 * 1024 * 1024:
1568 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
1569 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
1570 break;
1571 }
1572
1573 ktsb_descr[0].assoc = 1;
1574 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
1575 ktsb_descr[0].ctx_idx = 0;
1576 ktsb_descr[0].tsb_base = ktsb_pa;
1577 ktsb_descr[0].resv = 0;
1578
1579#ifndef CONFIG_DEBUG_PAGEALLOC
1580 /* Second KTSB for 4MB/256MB mappings. */
1581 ktsb_pa = (kern_base +
1582 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
1583
1584 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
1585 ktsb_descr[1].pgsz_mask = (HV_PGSZ_MASK_4MB |
1586 HV_PGSZ_MASK_256MB);
1587 ktsb_descr[1].assoc = 1;
1588 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
1589 ktsb_descr[1].ctx_idx = 0;
1590 ktsb_descr[1].tsb_base = ktsb_pa;
1591 ktsb_descr[1].resv = 0;
1592#endif
1593}
1594
1595void __cpuinit sun4v_ktsb_register(void)
1596{
1597 unsigned long pa, ret;
1598
1599 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
1600
1601 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
1602 if (ret != 0) {
1603 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
1604 "errors with %lx\n", pa, ret);
1605 prom_halt();
1606 }
1607}
1608
1609/* paging_init() sets up the page tables */
1610
1611static unsigned long last_valid_pfn;
1612pgd_t swapper_pg_dir[2048];
1613
1614static void sun4u_pgprot_init(void);
1615static void sun4v_pgprot_init(void);
1616
1617void __init paging_init(void)
1618{
1619 unsigned long end_pfn, shift, phys_base;
1620 unsigned long real_end, i;
1621 int node;
1622
1623 /* These build time checkes make sure that the dcache_dirty_cpu()
1624 * page->flags usage will work.
1625 *
1626 * When a page gets marked as dcache-dirty, we store the
1627 * cpu number starting at bit 32 in the page->flags. Also,
1628 * functions like clear_dcache_dirty_cpu use the cpu mask
1629 * in 13-bit signed-immediate instruction fields.
1630 */
1631
1632 /*
1633 * Page flags must not reach into upper 32 bits that are used
1634 * for the cpu number
1635 */
1636 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
1637
1638 /*
1639 * The bit fields placed in the high range must not reach below
1640 * the 32 bit boundary. Otherwise we cannot place the cpu field
1641 * at the 32 bit boundary.
1642 */
1643 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
1644 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
1645
1646 BUILD_BUG_ON(NR_CPUS > 4096);
1647
1648 kern_base = (prom_boot_mapping_phys_low >> 22UL) << 22UL;
1649 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
1650
1651 /* Invalidate both kernel TSBs. */
1652 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
1653#ifndef CONFIG_DEBUG_PAGEALLOC
1654 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
1655#endif
1656
1657 if (tlb_type == hypervisor)
1658 sun4v_pgprot_init();
1659 else
1660 sun4u_pgprot_init();
1661
1662 if (tlb_type == cheetah_plus ||
1663 tlb_type == hypervisor) {
1664 tsb_phys_patch();
1665 ktsb_phys_patch();
1666 }
1667
1668 if (tlb_type == hypervisor) {
1669 sun4v_patch_tlb_handlers();
1670 sun4v_ktsb_init();
1671 }
1672
1673 /* Find available physical memory...
1674 *
1675 * Read it twice in order to work around a bug in openfirmware.
1676 * The call to grab this table itself can cause openfirmware to
1677 * allocate memory, which in turn can take away some space from
1678 * the list of available memory. Reading it twice makes sure
1679 * we really do get the final value.
1680 */
1681 read_obp_translations();
1682 read_obp_memory("reg", &pall[0], &pall_ents);
1683 read_obp_memory("available", &pavail[0], &pavail_ents);
1684 read_obp_memory("available", &pavail[0], &pavail_ents);
1685
1686 phys_base = 0xffffffffffffffffUL;
1687 for (i = 0; i < pavail_ents; i++) {
1688 phys_base = min(phys_base, pavail[i].phys_addr);
1689 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
1690 }
1691
1692 memblock_reserve(kern_base, kern_size);
1693
1694 find_ramdisk(phys_base);
1695
1696 memblock_enforce_memory_limit(cmdline_memory_size);
1697
1698 memblock_allow_resize();
1699 memblock_dump_all();
1700
1701 set_bit(0, mmu_context_bmap);
1702
1703 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
1704
1705 real_end = (unsigned long)_end;
1706 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << 22);
1707 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
1708 num_kernel_image_mappings);
1709
1710 /* Set kernel pgd to upper alias so physical page computations
1711 * work.
1712 */
1713 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1714
1715 memset(swapper_low_pmd_dir, 0, sizeof(swapper_low_pmd_dir));
1716
1717 /* Now can init the kernel/bad page tables. */
1718 pud_set(pud_offset(&swapper_pg_dir[0], 0),
1719 swapper_low_pmd_dir + (shift / sizeof(pgd_t)));
1720
1721 inherit_prom_mappings();
1722
1723 init_kpte_bitmap();
1724
1725 /* Ok, we can use our TLB miss and window trap handlers safely. */
1726 setup_tba();
1727
1728 __flush_tlb_all();
1729
1730 if (tlb_type == hypervisor)
1731 sun4v_ktsb_register();
1732
1733 prom_build_devicetree();
1734 of_populate_present_mask();
1735#ifndef CONFIG_SMP
1736 of_fill_in_cpu_data();
1737#endif
1738
1739 if (tlb_type == hypervisor) {
1740 sun4v_mdesc_init();
1741 mdesc_populate_present_mask(cpu_all_mask);
1742#ifndef CONFIG_SMP
1743 mdesc_fill_in_cpu_data(cpu_all_mask);
1744#endif
1745 }
1746
1747 /* Setup bootmem... */
1748 last_valid_pfn = end_pfn = bootmem_init(phys_base);
1749
1750 /* Once the OF device tree and MDESC have been setup, we know
1751 * the list of possible cpus. Therefore we can allocate the
1752 * IRQ stacks.
1753 */
1754 for_each_possible_cpu(i) {
1755 node = cpu_to_node(i);
1756
1757 softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
1758 THREAD_SIZE,
1759 THREAD_SIZE, 0);
1760 hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
1761 THREAD_SIZE,
1762 THREAD_SIZE, 0);
1763 }
1764
1765 kernel_physical_mapping_init();
1766
1767 {
1768 unsigned long max_zone_pfns[MAX_NR_ZONES];
1769
1770 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
1771
1772 max_zone_pfns[ZONE_NORMAL] = end_pfn;
1773
1774 free_area_init_nodes(max_zone_pfns);
1775 }
1776
1777 printk("Booting Linux...\n");
1778}
1779
1780int __devinit page_in_phys_avail(unsigned long paddr)
1781{
1782 int i;
1783
1784 paddr &= PAGE_MASK;
1785
1786 for (i = 0; i < pavail_ents; i++) {
1787 unsigned long start, end;
1788
1789 start = pavail[i].phys_addr;
1790 end = start + pavail[i].reg_size;
1791
1792 if (paddr >= start && paddr < end)
1793 return 1;
1794 }
1795 if (paddr >= kern_base && paddr < (kern_base + kern_size))
1796 return 1;
1797#ifdef CONFIG_BLK_DEV_INITRD
1798 if (paddr >= __pa(initrd_start) &&
1799 paddr < __pa(PAGE_ALIGN(initrd_end)))
1800 return 1;
1801#endif
1802
1803 return 0;
1804}
1805
1806static struct linux_prom64_registers pavail_rescan[MAX_BANKS] __initdata;
1807static int pavail_rescan_ents __initdata;
1808
1809/* Certain OBP calls, such as fetching "available" properties, can
1810 * claim physical memory. So, along with initializing the valid
1811 * address bitmap, what we do here is refetch the physical available
1812 * memory list again, and make sure it provides at least as much
1813 * memory as 'pavail' does.
1814 */
1815static void __init setup_valid_addr_bitmap_from_pavail(unsigned long *bitmap)
1816{
1817 int i;
1818
1819 read_obp_memory("available", &pavail_rescan[0], &pavail_rescan_ents);
1820
1821 for (i = 0; i < pavail_ents; i++) {
1822 unsigned long old_start, old_end;
1823
1824 old_start = pavail[i].phys_addr;
1825 old_end = old_start + pavail[i].reg_size;
1826 while (old_start < old_end) {
1827 int n;
1828
1829 for (n = 0; n < pavail_rescan_ents; n++) {
1830 unsigned long new_start, new_end;
1831
1832 new_start = pavail_rescan[n].phys_addr;
1833 new_end = new_start +
1834 pavail_rescan[n].reg_size;
1835
1836 if (new_start <= old_start &&
1837 new_end >= (old_start + PAGE_SIZE)) {
1838 set_bit(old_start >> 22, bitmap);
1839 goto do_next_page;
1840 }
1841 }
1842
1843 prom_printf("mem_init: Lost memory in pavail\n");
1844 prom_printf("mem_init: OLD start[%lx] size[%lx]\n",
1845 pavail[i].phys_addr,
1846 pavail[i].reg_size);
1847 prom_printf("mem_init: NEW start[%lx] size[%lx]\n",
1848 pavail_rescan[i].phys_addr,
1849 pavail_rescan[i].reg_size);
1850 prom_printf("mem_init: Cannot continue, aborting.\n");
1851 prom_halt();
1852
1853 do_next_page:
1854 old_start += PAGE_SIZE;
1855 }
1856 }
1857}
1858
1859static void __init patch_tlb_miss_handler_bitmap(void)
1860{
1861 extern unsigned int valid_addr_bitmap_insn[];
1862 extern unsigned int valid_addr_bitmap_patch[];
1863
1864 valid_addr_bitmap_insn[1] = valid_addr_bitmap_patch[1];
1865 mb();
1866 valid_addr_bitmap_insn[0] = valid_addr_bitmap_patch[0];
1867 flushi(&valid_addr_bitmap_insn[0]);
1868}
1869
1870void __init mem_init(void)
1871{
1872 unsigned long codepages, datapages, initpages;
1873 unsigned long addr, last;
1874
1875 addr = PAGE_OFFSET + kern_base;
1876 last = PAGE_ALIGN(kern_size) + addr;
1877 while (addr < last) {
1878 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1879 addr += PAGE_SIZE;
1880 }
1881
1882 setup_valid_addr_bitmap_from_pavail(sparc64_valid_addr_bitmap);
1883 patch_tlb_miss_handler_bitmap();
1884
1885 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
1886
1887#ifdef CONFIG_NEED_MULTIPLE_NODES
1888 {
1889 int i;
1890 for_each_online_node(i) {
1891 if (NODE_DATA(i)->node_spanned_pages != 0) {
1892 totalram_pages +=
1893 free_all_bootmem_node(NODE_DATA(i));
1894 }
1895 }
1896 totalram_pages += free_low_memory_core_early(MAX_NUMNODES);
1897 }
1898#else
1899 totalram_pages = free_all_bootmem();
1900#endif
1901
1902 /* We subtract one to account for the mem_map_zero page
1903 * allocated below.
1904 */
1905 totalram_pages -= 1;
1906 num_physpages = totalram_pages;
1907
1908 /*
1909 * Set up the zero page, mark it reserved, so that page count
1910 * is not manipulated when freeing the page from user ptes.
1911 */
1912 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
1913 if (mem_map_zero == NULL) {
1914 prom_printf("paging_init: Cannot alloc zero page.\n");
1915 prom_halt();
1916 }
1917 SetPageReserved(mem_map_zero);
1918
1919 codepages = (((unsigned long) _etext) - ((unsigned long) _start));
1920 codepages = PAGE_ALIGN(codepages) >> PAGE_SHIFT;
1921 datapages = (((unsigned long) _edata) - ((unsigned long) _etext));
1922 datapages = PAGE_ALIGN(datapages) >> PAGE_SHIFT;
1923 initpages = (((unsigned long) __init_end) - ((unsigned long) __init_begin));
1924 initpages = PAGE_ALIGN(initpages) >> PAGE_SHIFT;
1925
1926 printk("Memory: %luk available (%ldk kernel code, %ldk data, %ldk init) [%016lx,%016lx]\n",
1927 nr_free_pages() << (PAGE_SHIFT-10),
1928 codepages << (PAGE_SHIFT-10),
1929 datapages << (PAGE_SHIFT-10),
1930 initpages << (PAGE_SHIFT-10),
1931 PAGE_OFFSET, (last_valid_pfn << PAGE_SHIFT));
1932
1933 if (tlb_type == cheetah || tlb_type == cheetah_plus)
1934 cheetah_ecache_flush_init();
1935}
1936
1937void free_initmem(void)
1938{
1939 unsigned long addr, initend;
1940 int do_free = 1;
1941
1942 /* If the physical memory maps were trimmed by kernel command
1943 * line options, don't even try freeing this initmem stuff up.
1944 * The kernel image could have been in the trimmed out region
1945 * and if so the freeing below will free invalid page structs.
1946 */
1947 if (cmdline_memory_size)
1948 do_free = 0;
1949
1950 /*
1951 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
1952 */
1953 addr = PAGE_ALIGN((unsigned long)(__init_begin));
1954 initend = (unsigned long)(__init_end) & PAGE_MASK;
1955 for (; addr < initend; addr += PAGE_SIZE) {
1956 unsigned long page;
1957 struct page *p;
1958
1959 page = (addr +
1960 ((unsigned long) __va(kern_base)) -
1961 ((unsigned long) KERNBASE));
1962 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
1963
1964 if (do_free) {
1965 p = virt_to_page(page);
1966
1967 ClearPageReserved(p);
1968 init_page_count(p);
1969 __free_page(p);
1970 num_physpages++;
1971 totalram_pages++;
1972 }
1973 }
1974}
1975
1976#ifdef CONFIG_BLK_DEV_INITRD
1977void free_initrd_mem(unsigned long start, unsigned long end)
1978{
1979 if (start < end)
1980 printk ("Freeing initrd memory: %ldk freed\n", (end - start) >> 10);
1981 for (; start < end; start += PAGE_SIZE) {
1982 struct page *p = virt_to_page(start);
1983
1984 ClearPageReserved(p);
1985 init_page_count(p);
1986 __free_page(p);
1987 num_physpages++;
1988 totalram_pages++;
1989 }
1990}
1991#endif
1992
1993#define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
1994#define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
1995#define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
1996#define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
1997#define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
1998#define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
1999
2000pgprot_t PAGE_KERNEL __read_mostly;
2001EXPORT_SYMBOL(PAGE_KERNEL);
2002
2003pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2004pgprot_t PAGE_COPY __read_mostly;
2005
2006pgprot_t PAGE_SHARED __read_mostly;
2007EXPORT_SYMBOL(PAGE_SHARED);
2008
2009unsigned long pg_iobits __read_mostly;
2010
2011unsigned long _PAGE_IE __read_mostly;
2012EXPORT_SYMBOL(_PAGE_IE);
2013
2014unsigned long _PAGE_E __read_mostly;
2015EXPORT_SYMBOL(_PAGE_E);
2016
2017unsigned long _PAGE_CACHE __read_mostly;
2018EXPORT_SYMBOL(_PAGE_CACHE);
2019
2020#ifdef CONFIG_SPARSEMEM_VMEMMAP
2021unsigned long vmemmap_table[VMEMMAP_SIZE];
2022
2023int __meminit vmemmap_populate(struct page *start, unsigned long nr, int node)
2024{
2025 unsigned long vstart = (unsigned long) start;
2026 unsigned long vend = (unsigned long) (start + nr);
2027 unsigned long phys_start = (vstart - VMEMMAP_BASE);
2028 unsigned long phys_end = (vend - VMEMMAP_BASE);
2029 unsigned long addr = phys_start & VMEMMAP_CHUNK_MASK;
2030 unsigned long end = VMEMMAP_ALIGN(phys_end);
2031 unsigned long pte_base;
2032
2033 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2034 _PAGE_CP_4U | _PAGE_CV_4U |
2035 _PAGE_P_4U | _PAGE_W_4U);
2036 if (tlb_type == hypervisor)
2037 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2038 _PAGE_CP_4V | _PAGE_CV_4V |
2039 _PAGE_P_4V | _PAGE_W_4V);
2040
2041 for (; addr < end; addr += VMEMMAP_CHUNK) {
2042 unsigned long *vmem_pp =
2043 vmemmap_table + (addr >> VMEMMAP_CHUNK_SHIFT);
2044 void *block;
2045
2046 if (!(*vmem_pp & _PAGE_VALID)) {
2047 block = vmemmap_alloc_block(1UL << 22, node);
2048 if (!block)
2049 return -ENOMEM;
2050
2051 *vmem_pp = pte_base | __pa(block);
2052
2053 printk(KERN_INFO "[%p-%p] page_structs=%lu "
2054 "node=%d entry=%lu/%lu\n", start, block, nr,
2055 node,
2056 addr >> VMEMMAP_CHUNK_SHIFT,
2057 VMEMMAP_SIZE);
2058 }
2059 }
2060 return 0;
2061}
2062#endif /* CONFIG_SPARSEMEM_VMEMMAP */
2063
2064static void prot_init_common(unsigned long page_none,
2065 unsigned long page_shared,
2066 unsigned long page_copy,
2067 unsigned long page_readonly,
2068 unsigned long page_exec_bit)
2069{
2070 PAGE_COPY = __pgprot(page_copy);
2071 PAGE_SHARED = __pgprot(page_shared);
2072
2073 protection_map[0x0] = __pgprot(page_none);
2074 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2075 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2076 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2077 protection_map[0x4] = __pgprot(page_readonly);
2078 protection_map[0x5] = __pgprot(page_readonly);
2079 protection_map[0x6] = __pgprot(page_copy);
2080 protection_map[0x7] = __pgprot(page_copy);
2081 protection_map[0x8] = __pgprot(page_none);
2082 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2083 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2084 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2085 protection_map[0xc] = __pgprot(page_readonly);
2086 protection_map[0xd] = __pgprot(page_readonly);
2087 protection_map[0xe] = __pgprot(page_shared);
2088 protection_map[0xf] = __pgprot(page_shared);
2089}
2090
2091static void __init sun4u_pgprot_init(void)
2092{
2093 unsigned long page_none, page_shared, page_copy, page_readonly;
2094 unsigned long page_exec_bit;
2095
2096 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2097 _PAGE_CACHE_4U | _PAGE_P_4U |
2098 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2099 _PAGE_EXEC_4U);
2100 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2101 _PAGE_CACHE_4U | _PAGE_P_4U |
2102 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2103 _PAGE_EXEC_4U | _PAGE_L_4U);
2104
2105 _PAGE_IE = _PAGE_IE_4U;
2106 _PAGE_E = _PAGE_E_4U;
2107 _PAGE_CACHE = _PAGE_CACHE_4U;
2108
2109 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2110 __ACCESS_BITS_4U | _PAGE_E_4U);
2111
2112#ifdef CONFIG_DEBUG_PAGEALLOC
2113 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4U) ^
2114 0xfffff80000000000UL;
2115#else
2116 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2117 0xfffff80000000000UL;
2118#endif
2119 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2120 _PAGE_P_4U | _PAGE_W_4U);
2121
2122 /* XXX Should use 256MB on Panther. XXX */
2123 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2124
2125 _PAGE_SZBITS = _PAGE_SZBITS_4U;
2126 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2127 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2128 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2129
2130
2131 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2132 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2133 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2134 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2135 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2136 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2137 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2138
2139 page_exec_bit = _PAGE_EXEC_4U;
2140
2141 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2142 page_exec_bit);
2143}
2144
2145static void __init sun4v_pgprot_init(void)
2146{
2147 unsigned long page_none, page_shared, page_copy, page_readonly;
2148 unsigned long page_exec_bit;
2149
2150 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2151 _PAGE_CACHE_4V | _PAGE_P_4V |
2152 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2153 _PAGE_EXEC_4V);
2154 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2155
2156 _PAGE_IE = _PAGE_IE_4V;
2157 _PAGE_E = _PAGE_E_4V;
2158 _PAGE_CACHE = _PAGE_CACHE_4V;
2159
2160#ifdef CONFIG_DEBUG_PAGEALLOC
2161 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2162 0xfffff80000000000UL;
2163#else
2164 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2165 0xfffff80000000000UL;
2166#endif
2167 kern_linear_pte_xor[0] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2168 _PAGE_P_4V | _PAGE_W_4V);
2169
2170#ifdef CONFIG_DEBUG_PAGEALLOC
2171 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZBITS_4V) ^
2172 0xfffff80000000000UL;
2173#else
2174 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2175 0xfffff80000000000UL;
2176#endif
2177 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | _PAGE_CV_4V |
2178 _PAGE_P_4V | _PAGE_W_4V);
2179
2180 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2181 __ACCESS_BITS_4V | _PAGE_E_4V);
2182
2183 _PAGE_SZBITS = _PAGE_SZBITS_4V;
2184 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2185 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2186 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2187 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2188
2189 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | _PAGE_CACHE_4V;
2190 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2191 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2192 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2193 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2194 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | _PAGE_CACHE_4V |
2195 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2196
2197 page_exec_bit = _PAGE_EXEC_4V;
2198
2199 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2200 page_exec_bit);
2201}
2202
2203unsigned long pte_sz_bits(unsigned long sz)
2204{
2205 if (tlb_type == hypervisor) {
2206 switch (sz) {
2207 case 8 * 1024:
2208 default:
2209 return _PAGE_SZ8K_4V;
2210 case 64 * 1024:
2211 return _PAGE_SZ64K_4V;
2212 case 512 * 1024:
2213 return _PAGE_SZ512K_4V;
2214 case 4 * 1024 * 1024:
2215 return _PAGE_SZ4MB_4V;
2216 }
2217 } else {
2218 switch (sz) {
2219 case 8 * 1024:
2220 default:
2221 return _PAGE_SZ8K_4U;
2222 case 64 * 1024:
2223 return _PAGE_SZ64K_4U;
2224 case 512 * 1024:
2225 return _PAGE_SZ512K_4U;
2226 case 4 * 1024 * 1024:
2227 return _PAGE_SZ4MB_4U;
2228 }
2229 }
2230}
2231
2232pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2233{
2234 pte_t pte;
2235
2236 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
2237 pte_val(pte) |= (((unsigned long)space) << 32);
2238 pte_val(pte) |= pte_sz_bits(page_size);
2239
2240 return pte;
2241}
2242
2243static unsigned long kern_large_tte(unsigned long paddr)
2244{
2245 unsigned long val;
2246
2247 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2248 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2249 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2250 if (tlb_type == hypervisor)
2251 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2252 _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_P_4V |
2253 _PAGE_EXEC_4V | _PAGE_W_4V);
2254
2255 return val | paddr;
2256}
2257
2258/* If not locked, zap it. */
2259void __flush_tlb_all(void)
2260{
2261 unsigned long pstate;
2262 int i;
2263
2264 __asm__ __volatile__("flushw\n\t"
2265 "rdpr %%pstate, %0\n\t"
2266 "wrpr %0, %1, %%pstate"
2267 : "=r" (pstate)
2268 : "i" (PSTATE_IE));
2269 if (tlb_type == hypervisor) {
2270 sun4v_mmu_demap_all();
2271 } else if (tlb_type == spitfire) {
2272 for (i = 0; i < 64; i++) {
2273 /* Spitfire Errata #32 workaround */
2274 /* NOTE: Always runs on spitfire, so no
2275 * cheetah+ page size encodings.
2276 */
2277 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2278 "flush %%g6"
2279 : /* No outputs */
2280 : "r" (0),
2281 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2282
2283 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2284 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2285 "membar #Sync"
2286 : /* no outputs */
2287 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2288 spitfire_put_dtlb_data(i, 0x0UL);
2289 }
2290
2291 /* Spitfire Errata #32 workaround */
2292 /* NOTE: Always runs on spitfire, so no
2293 * cheetah+ page size encodings.
2294 */
2295 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2296 "flush %%g6"
2297 : /* No outputs */
2298 : "r" (0),
2299 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2300
2301 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2302 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2303 "membar #Sync"
2304 : /* no outputs */
2305 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2306 spitfire_put_itlb_data(i, 0x0UL);
2307 }
2308 }
2309 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2310 cheetah_flush_dtlb_all();
2311 cheetah_flush_itlb_all();
2312 }
2313 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2314 : : "r" (pstate));
2315}