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1// SPDX-License-Identifier: GPL-2.0
2#include "tegra30.dtsi"
3
4/*
5 * Toradex Apalis T30 Module Device Tree
6 * Compatible for Revisions 1GB: V1.0A, V1.1A; 1GB IT: V1.1A;
7 * 2GB: V1.0B, V1.0C, V1.0E, V1.1A
8 */
9/ {
10 model = "Toradex Apalis T30";
11 compatible = "toradex,apalis_t30", "nvidia,tegra30";
12
13 pcie@3000 {
14 avdd-pexa-supply = <&vdd2_reg>;
15 vdd-pexa-supply = <&vdd2_reg>;
16 avdd-pexb-supply = <&vdd2_reg>;
17 vdd-pexb-supply = <&vdd2_reg>;
18 avdd-pex-pll-supply = <&vdd2_reg>;
19 avdd-plle-supply = <&ldo6_reg>;
20 vddio-pex-ctl-supply = <&sys_3v3_reg>;
21 hvdd-pex-supply = <&sys_3v3_reg>;
22
23 pci@1,0 {
24 nvidia,num-lanes = <4>;
25 };
26
27 pci@2,0 {
28 nvidia,num-lanes = <1>;
29 };
30
31 pci@3,0 {
32 nvidia,num-lanes = <1>;
33 };
34 };
35
36 host1x@50000000 {
37 hdmi@54280000 {
38 vdd-supply = <&avdd_hdmi_3v3_reg>;
39 pll-supply = <&avdd_hdmi_pll_1v8_reg>;
40
41 nvidia,hpd-gpio =
42 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
43 nvidia,ddc-i2c-bus = <&hdmiddc>;
44 };
45 };
46
47 pinmux@70000868 {
48 pinctrl-names = "default";
49 pinctrl-0 = <&state_default>;
50
51 state_default: pinmux {
52 /* Analogue Audio (On-module) */
53 clk1_out_pw4 {
54 nvidia,pins = "clk1_out_pw4";
55 nvidia,function = "extperiph1";
56 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
57 nvidia,tristate = <TEGRA_PIN_DISABLE>;
58 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
59 };
60 dap3_fs_pp0 {
61 nvidia,pins = "dap3_fs_pp0",
62 "dap3_sclk_pp3",
63 "dap3_din_pp1",
64 "dap3_dout_pp2";
65 nvidia,function = "i2s2";
66 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
67 nvidia,tristate = <TEGRA_PIN_DISABLE>;
68 };
69
70 /* Apalis BKL1_ON */
71 pv2 {
72 nvidia,pins = "pv2";
73 nvidia,function = "rsvd4";
74 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
75 nvidia,tristate = <TEGRA_PIN_DISABLE>;
76 };
77
78 /* Apalis BKL1_PWM */
79 uart3_rts_n_pc0 {
80 nvidia,pins = "uart3_rts_n_pc0";
81 nvidia,function = "pwm0";
82 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
83 nvidia,tristate = <TEGRA_PIN_DISABLE>;
84 };
85 /* BKL1_PWM_EN#, disable TPS65911 PMIC PWM backlight */
86 uart3_cts_n_pa1 {
87 nvidia,pins = "uart3_cts_n_pa1";
88 nvidia,function = "rsvd2";
89 nvidia,pull = <TEGRA_PIN_PULL_UP>;
90 nvidia,tristate = <TEGRA_PIN_DISABLE>;
91 };
92
93 /* Apalis CAN1 on SPI6 */
94 spi2_cs0_n_px3 {
95 nvidia,pins = "spi2_cs0_n_px3",
96 "spi2_miso_px1",
97 "spi2_mosi_px0",
98 "spi2_sck_px2";
99 nvidia,function = "spi6";
100 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
101 nvidia,tristate = <TEGRA_PIN_DISABLE>;
102 };
103 /* CAN_INT1 */
104 spi2_cs1_n_pw2 {
105 nvidia,pins = "spi2_cs1_n_pw2";
106 nvidia,function = "spi3";
107 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
108 nvidia,tristate = <TEGRA_PIN_DISABLE>;
109 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
110 };
111
112 /* Apalis CAN2 on SPI4 */
113 gmi_a16_pj7 {
114 nvidia,pins = "gmi_a16_pj7",
115 "gmi_a17_pb0",
116 "gmi_a18_pb1",
117 "gmi_a19_pk7";
118 nvidia,function = "spi4";
119 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
120 nvidia,tristate = <TEGRA_PIN_DISABLE>;
121 };
122 /* CAN_INT2 */
123 spi2_cs2_n_pw3 {
124 nvidia,pins = "spi2_cs2_n_pw3";
125 nvidia,function = "spi3";
126 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
127 nvidia,tristate = <TEGRA_PIN_DISABLE>;
128 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
129 };
130
131 /* Apalis Digital Audio */
132 clk1_req_pee2 {
133 nvidia,pins = "clk1_req_pee2";
134 nvidia,function = "hda";
135 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
136 nvidia,tristate = <TEGRA_PIN_DISABLE>;
137 };
138 clk2_out_pw5 {
139 nvidia,pins = "clk2_out_pw5";
140 nvidia,function = "extperiph2";
141 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
142 nvidia,tristate = <TEGRA_PIN_DISABLE>;
143 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
144 };
145 dap1_fs_pn0 {
146 nvidia,pins = "dap1_fs_pn0",
147 "dap1_din_pn1",
148 "dap1_dout_pn2",
149 "dap1_sclk_pn3";
150 nvidia,function = "hda";
151 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
152 nvidia,tristate = <TEGRA_PIN_DISABLE>;
153 };
154
155 /* Apalis I2C3 */
156 cam_i2c_scl_pbb1 {
157 nvidia,pins = "cam_i2c_scl_pbb1",
158 "cam_i2c_sda_pbb2";
159 nvidia,function = "i2c3";
160 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
161 nvidia,tristate = <TEGRA_PIN_DISABLE>;
162 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
163 nvidia,lock = <TEGRA_PIN_DISABLE>;
164 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
165 };
166
167 /* Apalis MMC1 */
168 sdmmc3_clk_pa6 {
169 nvidia,pins = "sdmmc3_clk_pa6",
170 "sdmmc3_cmd_pa7";
171 nvidia,function = "sdmmc3";
172 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
173 nvidia,tristate = <TEGRA_PIN_DISABLE>;
174 };
175 sdmmc3_dat0_pb7 {
176 nvidia,pins = "sdmmc3_dat0_pb7",
177 "sdmmc3_dat1_pb6",
178 "sdmmc3_dat2_pb5",
179 "sdmmc3_dat3_pb4",
180 "sdmmc3_dat4_pd1",
181 "sdmmc3_dat5_pd0",
182 "sdmmc3_dat6_pd3",
183 "sdmmc3_dat7_pd4";
184 nvidia,function = "sdmmc3";
185 nvidia,pull = <TEGRA_PIN_PULL_UP>;
186 nvidia,tristate = <TEGRA_PIN_DISABLE>;
187 };
188 /* Apalis MMC1_CD# */
189 pv3 {
190 nvidia,pins = "pv3";
191 nvidia,function = "rsvd2";
192 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
193 nvidia,tristate = <TEGRA_PIN_DISABLE>;
194 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
195 };
196
197 /* Apalis PWM1 */
198 pu6 {
199 nvidia,pins = "pu6";
200 nvidia,function = "pwm3";
201 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
202 nvidia,tristate = <TEGRA_PIN_DISABLE>;
203 };
204
205 /* Apalis PWM2 */
206 pu5 {
207 nvidia,pins = "pu5";
208 nvidia,function = "pwm2";
209 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
210 nvidia,tristate = <TEGRA_PIN_DISABLE>;
211 };
212
213 /* Apalis PWM3 */
214 pu4 {
215 nvidia,pins = "pu4";
216 nvidia,function = "pwm1";
217 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
218 nvidia,tristate = <TEGRA_PIN_DISABLE>;
219 };
220
221 /* Apalis PWM4 */
222 pu3 {
223 nvidia,pins = "pu3";
224 nvidia,function = "pwm0";
225 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
226 nvidia,tristate = <TEGRA_PIN_DISABLE>;
227 };
228
229 /* Apalis RESET_MOCI# */
230 gmi_rst_n_pi4 {
231 nvidia,pins = "gmi_rst_n_pi4";
232 nvidia,function = "gmi";
233 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
234 nvidia,tristate = <TEGRA_PIN_DISABLE>;
235 };
236
237 /* Apalis SD1 */
238 sdmmc1_clk_pz0 {
239 nvidia,pins = "sdmmc1_clk_pz0";
240 nvidia,function = "sdmmc1";
241 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
242 nvidia,tristate = <TEGRA_PIN_DISABLE>;
243 };
244 sdmmc1_cmd_pz1 {
245 nvidia,pins = "sdmmc1_cmd_pz1",
246 "sdmmc1_dat0_py7",
247 "sdmmc1_dat1_py6",
248 "sdmmc1_dat2_py5",
249 "sdmmc1_dat3_py4";
250 nvidia,function = "sdmmc1";
251 nvidia,pull = <TEGRA_PIN_PULL_UP>;
252 nvidia,tristate = <TEGRA_PIN_DISABLE>;
253 };
254 /* Apalis SD1_CD# */
255 clk2_req_pcc5 {
256 nvidia,pins = "clk2_req_pcc5";
257 nvidia,function = "rsvd2";
258 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
259 nvidia,tristate = <TEGRA_PIN_DISABLE>;
260 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
261 };
262
263 /* Apalis SPI1 */
264 spi1_sck_px5 {
265 nvidia,pins = "spi1_sck_px5",
266 "spi1_mosi_px4",
267 "spi1_miso_px7",
268 "spi1_cs0_n_px6";
269 nvidia,function = "spi1";
270 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
271 nvidia,tristate = <TEGRA_PIN_DISABLE>;
272 };
273
274 /* Apalis SPI2 */
275 lcd_sck_pz4 {
276 nvidia,pins = "lcd_sck_pz4",
277 "lcd_sdout_pn5",
278 "lcd_sdin_pz2",
279 "lcd_cs0_n_pn4";
280 nvidia,function = "spi5";
281 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
282 nvidia,tristate = <TEGRA_PIN_DISABLE>;
283 };
284
285 /* Apalis UART1 */
286 ulpi_data0 {
287 nvidia,pins = "ulpi_data0_po1",
288 "ulpi_data1_po2",
289 "ulpi_data2_po3",
290 "ulpi_data3_po4",
291 "ulpi_data4_po5",
292 "ulpi_data5_po6",
293 "ulpi_data6_po7",
294 "ulpi_data7_po0";
295 nvidia,function = "uarta";
296 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
297 nvidia,tristate = <TEGRA_PIN_DISABLE>;
298 };
299
300 /* Apalis UART2 */
301 ulpi_clk_py0 {
302 nvidia,pins = "ulpi_clk_py0",
303 "ulpi_dir_py1",
304 "ulpi_nxt_py2",
305 "ulpi_stp_py3";
306 nvidia,function = "uartd";
307 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
308 nvidia,tristate = <TEGRA_PIN_DISABLE>;
309 };
310
311 /* Apalis UART3 */
312 uart2_rxd_pc3 {
313 nvidia,pins = "uart2_rxd_pc3",
314 "uart2_txd_pc2";
315 nvidia,function = "uartb";
316 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
317 nvidia,tristate = <TEGRA_PIN_DISABLE>;
318 };
319
320 /* Apalis UART4 */
321 uart3_rxd_pw7 {
322 nvidia,pins = "uart3_rxd_pw7",
323 "uart3_txd_pw6";
324 nvidia,function = "uartc";
325 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
326 nvidia,tristate = <TEGRA_PIN_DISABLE>;
327 };
328
329 /* Apalis USBO1_EN */
330 gen2_i2c_scl_pt5 {
331 nvidia,pins = "gen2_i2c_scl_pt5";
332 nvidia,function = "rsvd4";
333 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
334 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
335 nvidia,tristate = <TEGRA_PIN_DISABLE>;
336 };
337
338 /* Apalis USBO1_OC# */
339 gen2_i2c_sda_pt6 {
340 nvidia,pins = "gen2_i2c_sda_pt6";
341 nvidia,function = "rsvd4";
342 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
343 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
344 nvidia,tristate = <TEGRA_PIN_DISABLE>;
345 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
346 };
347
348 /* Apalis WAKE1_MICO */
349 pv1 {
350 nvidia,pins = "pv1";
351 nvidia,function = "rsvd1";
352 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
353 nvidia,tristate = <TEGRA_PIN_DISABLE>;
354 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
355 };
356
357 /* eMMC (On-module) */
358 sdmmc4_clk_pcc4 {
359 nvidia,pins = "sdmmc4_clk_pcc4",
360 "sdmmc4_rst_n_pcc3";
361 nvidia,function = "sdmmc4";
362 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
363 nvidia,tristate = <TEGRA_PIN_DISABLE>;
364 };
365 sdmmc4_dat0_paa0 {
366 nvidia,pins = "sdmmc4_dat0_paa0",
367 "sdmmc4_dat1_paa1",
368 "sdmmc4_dat2_paa2",
369 "sdmmc4_dat3_paa3",
370 "sdmmc4_dat4_paa4",
371 "sdmmc4_dat5_paa5",
372 "sdmmc4_dat6_paa6",
373 "sdmmc4_dat7_paa7";
374 nvidia,function = "sdmmc4";
375 nvidia,pull = <TEGRA_PIN_PULL_UP>;
376 nvidia,tristate = <TEGRA_PIN_DISABLE>;
377 };
378
379 /* LVDS Transceiver Configuration */
380 pbb0 {
381 nvidia,pins = "pbb0",
382 "pbb7",
383 "pcc1",
384 "pcc2";
385 nvidia,function = "rsvd2";
386 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
387 nvidia,tristate = <TEGRA_PIN_DISABLE>;
388 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
389 nvidia,lock = <TEGRA_PIN_DISABLE>;
390 };
391 pbb3 {
392 nvidia,pins = "pbb3",
393 "pbb4",
394 "pbb5",
395 "pbb6";
396 nvidia,function = "displayb";
397 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
398 nvidia,tristate = <TEGRA_PIN_DISABLE>;
399 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
400 nvidia,lock = <TEGRA_PIN_DISABLE>;
401 };
402
403 /* Power I2C (On-module) */
404 pwr_i2c_scl_pz6 {
405 nvidia,pins = "pwr_i2c_scl_pz6",
406 "pwr_i2c_sda_pz7";
407 nvidia,function = "i2cpwr";
408 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
409 nvidia,tristate = <TEGRA_PIN_DISABLE>;
410 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
411 nvidia,lock = <TEGRA_PIN_DISABLE>;
412 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
413 };
414
415 /*
416 * THERMD_ALERT#, unlatched I2C address pin of LM95245
417 * temperature sensor therefore requires disabling for
418 * now
419 */
420 lcd_dc1_pd2 {
421 nvidia,pins = "lcd_dc1_pd2";
422 nvidia,function = "rsvd3";
423 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
424 nvidia,tristate = <TEGRA_PIN_DISABLE>;
425 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
426 };
427
428 /* TOUCH_PEN_INT# */
429 pv0 {
430 nvidia,pins = "pv0";
431 nvidia,function = "rsvd1";
432 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
433 nvidia,tristate = <TEGRA_PIN_DISABLE>;
434 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
435 };
436 };
437 };
438
439 hdmiddc: i2c@7000c700 {
440 clock-frequency = <10000>;
441 };
442
443 /*
444 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
445 * touch screen controller
446 */
447 i2c@7000d000 {
448 status = "okay";
449 clock-frequency = <100000>;
450
451 /* SGTL5000 audio codec */
452 sgtl5000: codec@a {
453 compatible = "fsl,sgtl5000";
454 reg = <0x0a>;
455 VDDA-supply = <&sys_3v3_reg>;
456 VDDIO-supply = <&sys_3v3_reg>;
457 clocks = <&tegra_car TEGRA30_CLK_EXTERN1>;
458 };
459
460 pmic: tps65911@2d {
461 compatible = "ti,tps65911";
462 reg = <0x2d>;
463
464 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
465 #interrupt-cells = <2>;
466 interrupt-controller;
467
468 ti,system-power-controller;
469
470 #gpio-cells = <2>;
471 gpio-controller;
472
473 vcc1-supply = <&sys_3v3_reg>;
474 vcc2-supply = <&sys_3v3_reg>;
475 vcc3-supply = <&vio_reg>;
476 vcc4-supply = <&sys_3v3_reg>;
477 vcc5-supply = <&sys_3v3_reg>;
478 vcc6-supply = <&vio_reg>;
479 vcc7-supply = <&charge_pump_5v0_reg>;
480 vccio-supply = <&sys_3v3_reg>;
481
482 regulators {
483 /* SW1: +V1.35_VDDIO_DDR */
484 vdd1_reg: vdd1 {
485 regulator-name = "vddio_ddr_1v35";
486 regulator-min-microvolt = <1350000>;
487 regulator-max-microvolt = <1350000>;
488 regulator-always-on;
489 };
490
491 /* SW2: +V1.05 */
492 vdd2_reg: vdd2 {
493 regulator-name =
494 "vdd_pexa,vdd_pexb,vdd_sata";
495 regulator-min-microvolt = <1050000>;
496 regulator-max-microvolt = <1050000>;
497 };
498
499 /* SW CTRL: +V1.0_VDD_CPU */
500 vddctrl_reg: vddctrl {
501 regulator-name = "vdd_cpu,vdd_sys";
502 regulator-min-microvolt = <1150000>;
503 regulator-max-microvolt = <1150000>;
504 regulator-always-on;
505 };
506
507 /* SWIO: +V1.8 */
508 vio_reg: vio {
509 regulator-name = "vdd_1v8_gen";
510 regulator-min-microvolt = <1800000>;
511 regulator-max-microvolt = <1800000>;
512 regulator-always-on;
513 };
514
515 /* LDO1: unused */
516
517 /*
518 * EN_+V3.3 switching via FET:
519 * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
520 * see also v3_3 fixed supply
521 */
522 ldo2_reg: ldo2 {
523 regulator-name = "en_3v3";
524 regulator-min-microvolt = <3300000>;
525 regulator-max-microvolt = <3300000>;
526 regulator-always-on;
527 };
528
529 /* +V1.2_CSI */
530 ldo3_reg: ldo3 {
531 regulator-name =
532 "avdd_dsi_csi,pwrdet_mipi";
533 regulator-min-microvolt = <1200000>;
534 regulator-max-microvolt = <1200000>;
535 };
536
537 /* +V1.2_VDD_RTC */
538 ldo4_reg: ldo4 {
539 regulator-name = "vdd_rtc";
540 regulator-min-microvolt = <1200000>;
541 regulator-max-microvolt = <1200000>;
542 regulator-always-on;
543 };
544
545 /*
546 * +V2.8_AVDD_VDAC:
547 * only required for analog RGB
548 */
549 ldo5_reg: ldo5 {
550 regulator-name = "avdd_vdac";
551 regulator-min-microvolt = <2800000>;
552 regulator-max-microvolt = <2800000>;
553 regulator-always-on;
554 };
555
556 /*
557 * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
558 * but LDO6 can't set voltage in 50mV
559 * granularity
560 */
561 ldo6_reg: ldo6 {
562 regulator-name = "avdd_plle";
563 regulator-min-microvolt = <1100000>;
564 regulator-max-microvolt = <1100000>;
565 };
566
567 /* +V1.2_AVDD_PLL */
568 ldo7_reg: ldo7 {
569 regulator-name = "avdd_pll";
570 regulator-min-microvolt = <1200000>;
571 regulator-max-microvolt = <1200000>;
572 regulator-always-on;
573 };
574
575 /* +V1.0_VDD_DDR_HS */
576 ldo8_reg: ldo8 {
577 regulator-name = "vdd_ddr_hs";
578 regulator-min-microvolt = <1000000>;
579 regulator-max-microvolt = <1000000>;
580 regulator-always-on;
581 };
582 };
583 };
584
585 /* STMPE811 touch screen controller */
586 stmpe811@41 {
587 compatible = "st,stmpe811";
588 #address-cells = <1>;
589 #size-cells = <0>;
590 reg = <0x41>;
591 interrupts = <TEGRA_GPIO(V, 0) IRQ_TYPE_LEVEL_LOW>;
592 interrupt-parent = <&gpio>;
593 interrupt-controller;
594 id = <0>;
595 blocks = <0x5>;
596 irq-trigger = <0x1>;
597
598 stmpe_touchscreen@0 {
599 compatible = "st,stmpe-ts";
600 /* 3.25 MHz ADC clock speed */
601 st,adc-freq = <1>;
602 /* 8 sample average control */
603 st,ave-ctrl = <3>;
604 /* 7 length fractional part in z */
605 st,fraction-z = <7>;
606 /*
607 * 50 mA typical 80 mA max touchscreen drivers
608 * current limit value
609 */
610 st,i-drive = <1>;
611 /* 12-bit ADC */
612 st,mod-12b = <1>;
613 /* internal ADC reference */
614 st,ref-sel = <0>;
615 /* ADC converstion time: 80 clocks */
616 st,sample-time = <4>;
617 /* 1 ms panel driver settling time */
618 st,settling = <3>;
619 /* 5 ms touch detect interrupt delay */
620 st,touch-det-delay = <5>;
621 };
622 };
623
624 /*
625 * LM95245 temperature sensor
626 * Note: OVERT_N directly connected to PMIC PWRDN
627 */
628 temp-sensor@4c {
629 compatible = "national,lm95245";
630 reg = <0x4c>;
631 };
632
633 /* SW: +V1.2_VDD_CORE */
634 tps62362@60 {
635 compatible = "ti,tps62362";
636 reg = <0x60>;
637
638 regulator-name = "tps62362-vout";
639 regulator-min-microvolt = <900000>;
640 regulator-max-microvolt = <1400000>;
641 regulator-boot-on;
642 regulator-always-on;
643 ti,vsel0-state-low;
644 /* VSEL1: EN_CORE_DVFS_N low for DVFS */
645 ti,vsel1-state-low;
646 };
647 };
648
649 /* SPI4: CAN2 */
650 spi@7000da00 {
651 status = "okay";
652 spi-max-frequency = <10000000>;
653
654 can@1 {
655 compatible = "microchip,mcp2515";
656 reg = <1>;
657 clocks = <&clk16m>;
658 interrupt-parent = <&gpio>;
659 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_EDGE_RISING>;
660 spi-max-frequency = <10000000>;
661 };
662 };
663
664 /* SPI6: CAN1 */
665 spi@7000de00 {
666 status = "okay";
667 spi-max-frequency = <10000000>;
668
669 can@0 {
670 compatible = "microchip,mcp2515";
671 reg = <0>;
672 clocks = <&clk16m>;
673 interrupt-parent = <&gpio>;
674 interrupts = <TEGRA_GPIO(W, 2) IRQ_TYPE_EDGE_RISING>;
675 spi-max-frequency = <10000000>;
676 };
677 };
678
679 pmc@7000e400 {
680 nvidia,invert-interrupt;
681 nvidia,suspend-mode = <1>;
682 nvidia,cpu-pwr-good-time = <5000>;
683 nvidia,cpu-pwr-off-time = <5000>;
684 nvidia,core-pwr-good-time = <3845 3845>;
685 nvidia,core-pwr-off-time = <0>;
686 nvidia,core-power-req-active-high;
687 nvidia,sys-clock-req-active-high;
688 };
689
690 ahub@70080000 {
691 i2s@70080500 {
692 status = "okay";
693 };
694 };
695
696 /* eMMC */
697 sdhci@78000600 {
698 status = "okay";
699 bus-width = <8>;
700 non-removable;
701 };
702
703 clocks {
704 compatible = "simple-bus";
705 #address-cells = <1>;
706 #size-cells = <0>;
707
708 clk32k_in: clk@0 {
709 compatible = "fixed-clock";
710 reg = <0>;
711 #clock-cells = <0>;
712 clock-frequency = <32768>;
713 };
714
715 clk16m: clk@1 {
716 compatible = "fixed-clock";
717 reg = <1>;
718 #clock-cells = <0>;
719 clock-frequency = <16000000>;
720 clock-output-names = "clk16m";
721 };
722 };
723
724 regulators {
725 compatible = "simple-bus";
726 #address-cells = <1>;
727 #size-cells = <0>;
728
729 avdd_hdmi_pll_1v8_reg: regulator@100 {
730 compatible = "regulator-fixed";
731 reg = <100>;
732 regulator-name = "+V1.8_AVDD_HDMI_PLL";
733 regulator-min-microvolt = <1800000>;
734 regulator-max-microvolt = <1800000>;
735 enable-active-high;
736 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
737 vin-supply = <&vio_reg>;
738 };
739
740 sys_3v3_reg: regulator@101 {
741 compatible = "regulator-fixed";
742 reg = <101>;
743 regulator-name = "3v3";
744 regulator-min-microvolt = <3300000>;
745 regulator-max-microvolt = <3300000>;
746 regulator-always-on;
747 };
748
749 avdd_hdmi_3v3_reg: regulator@102 {
750 compatible = "regulator-fixed";
751 reg = <102>;
752 regulator-name = "+V3.3_AVDD_HDMI";
753 regulator-min-microvolt = <3300000>;
754 regulator-max-microvolt = <3300000>;
755 enable-active-high;
756 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
757 vin-supply = <&sys_3v3_reg>;
758 };
759
760 charge_pump_5v0_reg: regulator@103 {
761 compatible = "regulator-fixed";
762 reg = <103>;
763 regulator-name = "5v0";
764 regulator-min-microvolt = <5000000>;
765 regulator-max-microvolt = <5000000>;
766 regulator-always-on;
767 };
768 };
769
770 sound {
771 compatible = "toradex,tegra-audio-sgtl5000-apalis_t30",
772 "nvidia,tegra-audio-sgtl5000";
773 nvidia,model = "Toradex Apalis T30";
774 nvidia,audio-routing =
775 "Headphone Jack", "HP_OUT",
776 "LINE_IN", "Line In Jack",
777 "MIC_IN", "Mic Jack";
778 nvidia,i2s-controller = <&tegra_i2s2>;
779 nvidia,audio-codec = <&sgtl5000>;
780 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
781 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
782 <&tegra_car TEGRA30_CLK_EXTERN1>;
783 clock-names = "pll_a", "pll_a_out0", "mclk";
784 };
785};