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1/*
2 * simple driver for PWM (Pulse Width Modulator) controller
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/platform_device.h>
14#include <linux/slab.h>
15#include <linux/err.h>
16#include <linux/clk.h>
17#include <linux/delay.h>
18#include <linux/io.h>
19#include <linux/pwm.h>
20#include <linux/of.h>
21#include <linux/of_device.h>
22
23/* i.MX1 and i.MX21 share the same PWM function block: */
24
25#define MX1_PWMC 0x00 /* PWM Control Register */
26#define MX1_PWMS 0x04 /* PWM Sample Register */
27#define MX1_PWMP 0x08 /* PWM Period Register */
28
29#define MX1_PWMC_EN (1 << 4)
30
31/* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
32
33#define MX3_PWMCR 0x00 /* PWM Control Register */
34#define MX3_PWMSR 0x04 /* PWM Status Register */
35#define MX3_PWMSAR 0x0C /* PWM Sample Register */
36#define MX3_PWMPR 0x10 /* PWM Period Register */
37#define MX3_PWMCR_PRESCALER(x) ((((x) - 1) & 0xFFF) << 4)
38#define MX3_PWMCR_STOPEN (1 << 25)
39#define MX3_PWMCR_DOZEEN (1 << 24)
40#define MX3_PWMCR_WAITEN (1 << 23)
41#define MX3_PWMCR_DBGEN (1 << 22)
42#define MX3_PWMCR_POUTC (1 << 18)
43#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
44#define MX3_PWMCR_CLKSRC_IPG (1 << 16)
45#define MX3_PWMCR_SWR (1 << 3)
46#define MX3_PWMCR_EN (1 << 0)
47#define MX3_PWMSR_FIFOAV_4WORDS 0x4
48#define MX3_PWMSR_FIFOAV_MASK 0x7
49
50#define MX3_PWM_SWR_LOOP 5
51
52struct imx_chip {
53 struct clk *clk_per;
54
55 void __iomem *mmio_base;
56
57 struct pwm_chip chip;
58};
59
60#define to_imx_chip(chip) container_of(chip, struct imx_chip, chip)
61
62static int imx_pwm_config_v1(struct pwm_chip *chip,
63 struct pwm_device *pwm, int duty_ns, int period_ns)
64{
65 struct imx_chip *imx = to_imx_chip(chip);
66
67 /*
68 * The PWM subsystem allows for exact frequencies. However,
69 * I cannot connect a scope on my device to the PWM line and
70 * thus cannot provide the program the PWM controller
71 * exactly. Instead, I'm relying on the fact that the
72 * Bootloader (u-boot or WinCE+haret) has programmed the PWM
73 * function group already. So I'll just modify the PWM sample
74 * register to follow the ratio of duty_ns vs. period_ns
75 * accordingly.
76 *
77 * This is good enough for programming the brightness of
78 * the LCD backlight.
79 *
80 * The real implementation would divide PERCLK[0] first by
81 * both the prescaler (/1 .. /128) and then by CLKSEL
82 * (/2 .. /16).
83 */
84 u32 max = readl(imx->mmio_base + MX1_PWMP);
85 u32 p = max * duty_ns / period_ns;
86 writel(max - p, imx->mmio_base + MX1_PWMS);
87
88 return 0;
89}
90
91static int imx_pwm_enable_v1(struct pwm_chip *chip, struct pwm_device *pwm)
92{
93 struct imx_chip *imx = to_imx_chip(chip);
94 u32 val;
95 int ret;
96
97 ret = clk_prepare_enable(imx->clk_per);
98 if (ret < 0)
99 return ret;
100
101 val = readl(imx->mmio_base + MX1_PWMC);
102 val |= MX1_PWMC_EN;
103 writel(val, imx->mmio_base + MX1_PWMC);
104
105 return 0;
106}
107
108static void imx_pwm_disable_v1(struct pwm_chip *chip, struct pwm_device *pwm)
109{
110 struct imx_chip *imx = to_imx_chip(chip);
111 u32 val;
112
113 val = readl(imx->mmio_base + MX1_PWMC);
114 val &= ~MX1_PWMC_EN;
115 writel(val, imx->mmio_base + MX1_PWMC);
116
117 clk_disable_unprepare(imx->clk_per);
118}
119
120static void imx_pwm_sw_reset(struct pwm_chip *chip)
121{
122 struct imx_chip *imx = to_imx_chip(chip);
123 struct device *dev = chip->dev;
124 int wait_count = 0;
125 u32 cr;
126
127 writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
128 do {
129 usleep_range(200, 1000);
130 cr = readl(imx->mmio_base + MX3_PWMCR);
131 } while ((cr & MX3_PWMCR_SWR) &&
132 (wait_count++ < MX3_PWM_SWR_LOOP));
133
134 if (cr & MX3_PWMCR_SWR)
135 dev_warn(dev, "software reset timeout\n");
136}
137
138static void imx_pwm_wait_fifo_slot(struct pwm_chip *chip,
139 struct pwm_device *pwm)
140{
141 struct imx_chip *imx = to_imx_chip(chip);
142 struct device *dev = chip->dev;
143 unsigned int period_ms;
144 int fifoav;
145 u32 sr;
146
147 sr = readl(imx->mmio_base + MX3_PWMSR);
148 fifoav = sr & MX3_PWMSR_FIFOAV_MASK;
149 if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
150 period_ms = DIV_ROUND_UP(pwm_get_period(pwm),
151 NSEC_PER_MSEC);
152 msleep(period_ms);
153
154 sr = readl(imx->mmio_base + MX3_PWMSR);
155 if (fifoav == (sr & MX3_PWMSR_FIFOAV_MASK))
156 dev_warn(dev, "there is no free FIFO slot\n");
157 }
158}
159
160static int imx_pwm_apply_v2(struct pwm_chip *chip, struct pwm_device *pwm,
161 struct pwm_state *state)
162{
163 unsigned long period_cycles, duty_cycles, prescale;
164 struct imx_chip *imx = to_imx_chip(chip);
165 struct pwm_state cstate;
166 unsigned long long c;
167 int ret;
168 u32 cr;
169
170 pwm_get_state(pwm, &cstate);
171
172 if (state->enabled) {
173 c = clk_get_rate(imx->clk_per);
174 c *= state->period;
175
176 do_div(c, 1000000000);
177 period_cycles = c;
178
179 prescale = period_cycles / 0x10000 + 1;
180
181 period_cycles /= prescale;
182 c = (unsigned long long)period_cycles * state->duty_cycle;
183 do_div(c, state->period);
184 duty_cycles = c;
185
186 /*
187 * according to imx pwm RM, the real period value should be
188 * PERIOD value in PWMPR plus 2.
189 */
190 if (period_cycles > 2)
191 period_cycles -= 2;
192 else
193 period_cycles = 0;
194
195 /*
196 * Wait for a free FIFO slot if the PWM is already enabled, and
197 * flush the FIFO if the PWM was disabled and is about to be
198 * enabled.
199 */
200 if (cstate.enabled) {
201 imx_pwm_wait_fifo_slot(chip, pwm);
202 } else {
203 ret = clk_prepare_enable(imx->clk_per);
204 if (ret)
205 return ret;
206
207 imx_pwm_sw_reset(chip);
208 }
209
210 writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
211 writel(period_cycles, imx->mmio_base + MX3_PWMPR);
212
213 cr = MX3_PWMCR_PRESCALER(prescale) |
214 MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
215 MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH |
216 MX3_PWMCR_EN;
217
218 if (state->polarity == PWM_POLARITY_INVERSED)
219 cr |= MX3_PWMCR_POUTC;
220
221 writel(cr, imx->mmio_base + MX3_PWMCR);
222 } else if (cstate.enabled) {
223 writel(0, imx->mmio_base + MX3_PWMCR);
224
225 clk_disable_unprepare(imx->clk_per);
226 }
227
228 return 0;
229}
230
231static const struct pwm_ops imx_pwm_ops_v1 = {
232 .enable = imx_pwm_enable_v1,
233 .disable = imx_pwm_disable_v1,
234 .config = imx_pwm_config_v1,
235 .owner = THIS_MODULE,
236};
237
238static const struct pwm_ops imx_pwm_ops_v2 = {
239 .apply = imx_pwm_apply_v2,
240 .owner = THIS_MODULE,
241};
242
243struct imx_pwm_data {
244 bool polarity_supported;
245 const struct pwm_ops *ops;
246};
247
248static struct imx_pwm_data imx_pwm_data_v1 = {
249 .ops = &imx_pwm_ops_v1,
250};
251
252static struct imx_pwm_data imx_pwm_data_v2 = {
253 .polarity_supported = true,
254 .ops = &imx_pwm_ops_v2,
255};
256
257static const struct of_device_id imx_pwm_dt_ids[] = {
258 { .compatible = "fsl,imx1-pwm", .data = &imx_pwm_data_v1, },
259 { .compatible = "fsl,imx27-pwm", .data = &imx_pwm_data_v2, },
260 { /* sentinel */ }
261};
262MODULE_DEVICE_TABLE(of, imx_pwm_dt_ids);
263
264static int imx_pwm_probe(struct platform_device *pdev)
265{
266 const struct of_device_id *of_id =
267 of_match_device(imx_pwm_dt_ids, &pdev->dev);
268 const struct imx_pwm_data *data;
269 struct imx_chip *imx;
270 struct resource *r;
271 int ret = 0;
272
273 if (!of_id)
274 return -ENODEV;
275
276 data = of_id->data;
277
278 imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
279 if (imx == NULL)
280 return -ENOMEM;
281
282 imx->clk_per = devm_clk_get(&pdev->dev, "per");
283 if (IS_ERR(imx->clk_per)) {
284 dev_err(&pdev->dev, "getting per clock failed with %ld\n",
285 PTR_ERR(imx->clk_per));
286 return PTR_ERR(imx->clk_per);
287 }
288
289 imx->chip.ops = data->ops;
290 imx->chip.dev = &pdev->dev;
291 imx->chip.base = -1;
292 imx->chip.npwm = 1;
293
294 if (data->polarity_supported) {
295 dev_dbg(&pdev->dev, "PWM supports output inversion\n");
296 imx->chip.of_xlate = of_pwm_xlate_with_flags;
297 imx->chip.of_pwm_n_cells = 3;
298 }
299
300 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
301 imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
302 if (IS_ERR(imx->mmio_base))
303 return PTR_ERR(imx->mmio_base);
304
305 ret = pwmchip_add(&imx->chip);
306 if (ret < 0)
307 return ret;
308
309 platform_set_drvdata(pdev, imx);
310 return 0;
311}
312
313static int imx_pwm_remove(struct platform_device *pdev)
314{
315 struct imx_chip *imx;
316
317 imx = platform_get_drvdata(pdev);
318 if (imx == NULL)
319 return -ENODEV;
320
321 return pwmchip_remove(&imx->chip);
322}
323
324static struct platform_driver imx_pwm_driver = {
325 .driver = {
326 .name = "imx-pwm",
327 .of_match_table = imx_pwm_dt_ids,
328 },
329 .probe = imx_pwm_probe,
330 .remove = imx_pwm_remove,
331};
332
333module_platform_driver(imx_pwm_driver);
334
335MODULE_LICENSE("GPL v2");
336MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1/*
2 * simple driver for PWM (Pulse Width Modulator) controller
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/platform_device.h>
14#include <linux/slab.h>
15#include <linux/err.h>
16#include <linux/clk.h>
17#include <linux/io.h>
18#include <linux/pwm.h>
19#include <linux/of.h>
20#include <linux/of_device.h>
21
22/* i.MX1 and i.MX21 share the same PWM function block: */
23
24#define MX1_PWMC 0x00 /* PWM Control Register */
25#define MX1_PWMS 0x04 /* PWM Sample Register */
26#define MX1_PWMP 0x08 /* PWM Period Register */
27
28#define MX1_PWMC_EN (1 << 4)
29
30/* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
31
32#define MX3_PWMCR 0x00 /* PWM Control Register */
33#define MX3_PWMSAR 0x0C /* PWM Sample Register */
34#define MX3_PWMPR 0x10 /* PWM Period Register */
35#define MX3_PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
36#define MX3_PWMCR_DOZEEN (1 << 24)
37#define MX3_PWMCR_WAITEN (1 << 23)
38#define MX3_PWMCR_DBGEN (1 << 22)
39#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
40#define MX3_PWMCR_CLKSRC_IPG (1 << 16)
41#define MX3_PWMCR_EN (1 << 0)
42
43struct imx_chip {
44 struct clk *clk_per;
45 struct clk *clk_ipg;
46
47 void __iomem *mmio_base;
48
49 struct pwm_chip chip;
50
51 int (*config)(struct pwm_chip *chip,
52 struct pwm_device *pwm, int duty_ns, int period_ns);
53 void (*set_enable)(struct pwm_chip *chip, bool enable);
54};
55
56#define to_imx_chip(chip) container_of(chip, struct imx_chip, chip)
57
58static int imx_pwm_config_v1(struct pwm_chip *chip,
59 struct pwm_device *pwm, int duty_ns, int period_ns)
60{
61 struct imx_chip *imx = to_imx_chip(chip);
62
63 /*
64 * The PWM subsystem allows for exact frequencies. However,
65 * I cannot connect a scope on my device to the PWM line and
66 * thus cannot provide the program the PWM controller
67 * exactly. Instead, I'm relying on the fact that the
68 * Bootloader (u-boot or WinCE+haret) has programmed the PWM
69 * function group already. So I'll just modify the PWM sample
70 * register to follow the ratio of duty_ns vs. period_ns
71 * accordingly.
72 *
73 * This is good enough for programming the brightness of
74 * the LCD backlight.
75 *
76 * The real implementation would divide PERCLK[0] first by
77 * both the prescaler (/1 .. /128) and then by CLKSEL
78 * (/2 .. /16).
79 */
80 u32 max = readl(imx->mmio_base + MX1_PWMP);
81 u32 p = max * duty_ns / period_ns;
82 writel(max - p, imx->mmio_base + MX1_PWMS);
83
84 return 0;
85}
86
87static void imx_pwm_set_enable_v1(struct pwm_chip *chip, bool enable)
88{
89 struct imx_chip *imx = to_imx_chip(chip);
90 u32 val;
91
92 val = readl(imx->mmio_base + MX1_PWMC);
93
94 if (enable)
95 val |= MX1_PWMC_EN;
96 else
97 val &= ~MX1_PWMC_EN;
98
99 writel(val, imx->mmio_base + MX1_PWMC);
100}
101
102static int imx_pwm_config_v2(struct pwm_chip *chip,
103 struct pwm_device *pwm, int duty_ns, int period_ns)
104{
105 struct imx_chip *imx = to_imx_chip(chip);
106 unsigned long long c;
107 unsigned long period_cycles, duty_cycles, prescale;
108 u32 cr;
109
110 c = clk_get_rate(imx->clk_per);
111 c = c * period_ns;
112 do_div(c, 1000000000);
113 period_cycles = c;
114
115 prescale = period_cycles / 0x10000 + 1;
116
117 period_cycles /= prescale;
118 c = (unsigned long long)period_cycles * duty_ns;
119 do_div(c, period_ns);
120 duty_cycles = c;
121
122 /*
123 * according to imx pwm RM, the real period value should be
124 * PERIOD value in PWMPR plus 2.
125 */
126 if (period_cycles > 2)
127 period_cycles -= 2;
128 else
129 period_cycles = 0;
130
131 writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
132 writel(period_cycles, imx->mmio_base + MX3_PWMPR);
133
134 cr = MX3_PWMCR_PRESCALER(prescale) |
135 MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
136 MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH;
137
138 if (test_bit(PWMF_ENABLED, &pwm->flags))
139 cr |= MX3_PWMCR_EN;
140
141 writel(cr, imx->mmio_base + MX3_PWMCR);
142
143 return 0;
144}
145
146static void imx_pwm_set_enable_v2(struct pwm_chip *chip, bool enable)
147{
148 struct imx_chip *imx = to_imx_chip(chip);
149 u32 val;
150
151 val = readl(imx->mmio_base + MX3_PWMCR);
152
153 if (enable)
154 val |= MX3_PWMCR_EN;
155 else
156 val &= ~MX3_PWMCR_EN;
157
158 writel(val, imx->mmio_base + MX3_PWMCR);
159}
160
161static int imx_pwm_config(struct pwm_chip *chip,
162 struct pwm_device *pwm, int duty_ns, int period_ns)
163{
164 struct imx_chip *imx = to_imx_chip(chip);
165 int ret;
166
167 ret = clk_prepare_enable(imx->clk_ipg);
168 if (ret)
169 return ret;
170
171 ret = imx->config(chip, pwm, duty_ns, period_ns);
172
173 clk_disable_unprepare(imx->clk_ipg);
174
175 return ret;
176}
177
178static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
179{
180 struct imx_chip *imx = to_imx_chip(chip);
181 int ret;
182
183 ret = clk_prepare_enable(imx->clk_per);
184 if (ret)
185 return ret;
186
187 imx->set_enable(chip, true);
188
189 return 0;
190}
191
192static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
193{
194 struct imx_chip *imx = to_imx_chip(chip);
195
196 imx->set_enable(chip, false);
197
198 clk_disable_unprepare(imx->clk_per);
199}
200
201static struct pwm_ops imx_pwm_ops = {
202 .enable = imx_pwm_enable,
203 .disable = imx_pwm_disable,
204 .config = imx_pwm_config,
205 .owner = THIS_MODULE,
206};
207
208struct imx_pwm_data {
209 int (*config)(struct pwm_chip *chip,
210 struct pwm_device *pwm, int duty_ns, int period_ns);
211 void (*set_enable)(struct pwm_chip *chip, bool enable);
212};
213
214static struct imx_pwm_data imx_pwm_data_v1 = {
215 .config = imx_pwm_config_v1,
216 .set_enable = imx_pwm_set_enable_v1,
217};
218
219static struct imx_pwm_data imx_pwm_data_v2 = {
220 .config = imx_pwm_config_v2,
221 .set_enable = imx_pwm_set_enable_v2,
222};
223
224static const struct of_device_id imx_pwm_dt_ids[] = {
225 { .compatible = "fsl,imx1-pwm", .data = &imx_pwm_data_v1, },
226 { .compatible = "fsl,imx27-pwm", .data = &imx_pwm_data_v2, },
227 { /* sentinel */ }
228};
229MODULE_DEVICE_TABLE(of, imx_pwm_dt_ids);
230
231static int imx_pwm_probe(struct platform_device *pdev)
232{
233 const struct of_device_id *of_id =
234 of_match_device(imx_pwm_dt_ids, &pdev->dev);
235 const struct imx_pwm_data *data;
236 struct imx_chip *imx;
237 struct resource *r;
238 int ret = 0;
239
240 if (!of_id)
241 return -ENODEV;
242
243 imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
244 if (imx == NULL) {
245 dev_err(&pdev->dev, "failed to allocate memory\n");
246 return -ENOMEM;
247 }
248
249 imx->clk_per = devm_clk_get(&pdev->dev, "per");
250 if (IS_ERR(imx->clk_per)) {
251 dev_err(&pdev->dev, "getting per clock failed with %ld\n",
252 PTR_ERR(imx->clk_per));
253 return PTR_ERR(imx->clk_per);
254 }
255
256 imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
257 if (IS_ERR(imx->clk_ipg)) {
258 dev_err(&pdev->dev, "getting ipg clock failed with %ld\n",
259 PTR_ERR(imx->clk_ipg));
260 return PTR_ERR(imx->clk_ipg);
261 }
262
263 imx->chip.ops = &imx_pwm_ops;
264 imx->chip.dev = &pdev->dev;
265 imx->chip.base = -1;
266 imx->chip.npwm = 1;
267
268 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
269 imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
270 if (IS_ERR(imx->mmio_base))
271 return PTR_ERR(imx->mmio_base);
272
273 data = of_id->data;
274 imx->config = data->config;
275 imx->set_enable = data->set_enable;
276
277 ret = pwmchip_add(&imx->chip);
278 if (ret < 0)
279 return ret;
280
281 platform_set_drvdata(pdev, imx);
282 return 0;
283}
284
285static int imx_pwm_remove(struct platform_device *pdev)
286{
287 struct imx_chip *imx;
288
289 imx = platform_get_drvdata(pdev);
290 if (imx == NULL)
291 return -ENODEV;
292
293 return pwmchip_remove(&imx->chip);
294}
295
296static struct platform_driver imx_pwm_driver = {
297 .driver = {
298 .name = "imx-pwm",
299 .owner = THIS_MODULE,
300 .of_match_table = imx_pwm_dt_ids,
301 },
302 .probe = imx_pwm_probe,
303 .remove = imx_pwm_remove,
304};
305
306module_platform_driver(imx_pwm_driver);
307
308MODULE_LICENSE("GPL v2");
309MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");