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  1/*
  2 * simple driver for PWM (Pulse Width Modulator) controller
  3 *
  4 * This program is free software; you can redistribute it and/or modify
  5 * it under the terms of the GNU General Public License version 2 as
  6 * published by the Free Software Foundation.
  7 *
  8 * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
  9 */
 10
 11#include <linux/module.h>
 12#include <linux/kernel.h>
 13#include <linux/platform_device.h>
 14#include <linux/slab.h>
 15#include <linux/err.h>
 16#include <linux/clk.h>
 17#include <linux/delay.h>
 18#include <linux/io.h>
 19#include <linux/pwm.h>
 20#include <linux/of.h>
 21#include <linux/of_device.h>
 22
 23/* i.MX1 and i.MX21 share the same PWM function block: */
 24
 25#define MX1_PWMC			0x00   /* PWM Control Register */
 26#define MX1_PWMS			0x04   /* PWM Sample Register */
 27#define MX1_PWMP			0x08   /* PWM Period Register */
 28
 29#define MX1_PWMC_EN			(1 << 4)
 30
 31/* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
 32
 33#define MX3_PWMCR			0x00    /* PWM Control Register */
 34#define MX3_PWMSR			0x04    /* PWM Status Register */
 35#define MX3_PWMSAR			0x0C    /* PWM Sample Register */
 36#define MX3_PWMPR			0x10    /* PWM Period Register */
 37#define MX3_PWMCR_PRESCALER(x)		((((x) - 1) & 0xFFF) << 4)
 38#define MX3_PWMCR_STOPEN		(1 << 25)
 39#define MX3_PWMCR_DOZEEN		(1 << 24)
 40#define MX3_PWMCR_WAITEN		(1 << 23)
 41#define MX3_PWMCR_DBGEN			(1 << 22)
 42#define MX3_PWMCR_POUTC			(1 << 18)
 43#define MX3_PWMCR_CLKSRC_IPG_HIGH	(2 << 16)
 44#define MX3_PWMCR_CLKSRC_IPG		(1 << 16)
 45#define MX3_PWMCR_SWR			(1 << 3)
 46#define MX3_PWMCR_EN			(1 << 0)
 47#define MX3_PWMSR_FIFOAV_4WORDS		0x4
 48#define MX3_PWMSR_FIFOAV_MASK		0x7
 49
 50#define MX3_PWM_SWR_LOOP		5
 51
 52struct imx_chip {
 53	struct clk	*clk_per;
 54
 55	void __iomem	*mmio_base;
 56
 57	struct pwm_chip	chip;
 58};
 59
 60#define to_imx_chip(chip)	container_of(chip, struct imx_chip, chip)
 61
 62static int imx_pwm_config_v1(struct pwm_chip *chip,
 63		struct pwm_device *pwm, int duty_ns, int period_ns)
 64{
 65	struct imx_chip *imx = to_imx_chip(chip);
 66
 67	/*
 68	 * The PWM subsystem allows for exact frequencies. However,
 69	 * I cannot connect a scope on my device to the PWM line and
 70	 * thus cannot provide the program the PWM controller
 71	 * exactly. Instead, I'm relying on the fact that the
 72	 * Bootloader (u-boot or WinCE+haret) has programmed the PWM
 73	 * function group already. So I'll just modify the PWM sample
 74	 * register to follow the ratio of duty_ns vs. period_ns
 75	 * accordingly.
 76	 *
 77	 * This is good enough for programming the brightness of
 78	 * the LCD backlight.
 79	 *
 80	 * The real implementation would divide PERCLK[0] first by
 81	 * both the prescaler (/1 .. /128) and then by CLKSEL
 82	 * (/2 .. /16).
 83	 */
 84	u32 max = readl(imx->mmio_base + MX1_PWMP);
 85	u32 p = max * duty_ns / period_ns;
 86	writel(max - p, imx->mmio_base + MX1_PWMS);
 87
 88	return 0;
 89}
 90
 91static int imx_pwm_enable_v1(struct pwm_chip *chip, struct pwm_device *pwm)
 92{
 93	struct imx_chip *imx = to_imx_chip(chip);
 94	u32 val;
 95	int ret;
 96
 97	ret = clk_prepare_enable(imx->clk_per);
 98	if (ret < 0)
 99		return ret;
100
101	val = readl(imx->mmio_base + MX1_PWMC);
102	val |= MX1_PWMC_EN;
103	writel(val, imx->mmio_base + MX1_PWMC);
104
105	return 0;
106}
107
108static void imx_pwm_disable_v1(struct pwm_chip *chip, struct pwm_device *pwm)
109{
110	struct imx_chip *imx = to_imx_chip(chip);
111	u32 val;
112
113	val = readl(imx->mmio_base + MX1_PWMC);
114	val &= ~MX1_PWMC_EN;
115	writel(val, imx->mmio_base + MX1_PWMC);
116
117	clk_disable_unprepare(imx->clk_per);
118}
119
120static void imx_pwm_sw_reset(struct pwm_chip *chip)
121{
122	struct imx_chip *imx = to_imx_chip(chip);
123	struct device *dev = chip->dev;
124	int wait_count = 0;
125	u32 cr;
126
127	writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
128	do {
129		usleep_range(200, 1000);
130		cr = readl(imx->mmio_base + MX3_PWMCR);
131	} while ((cr & MX3_PWMCR_SWR) &&
132		 (wait_count++ < MX3_PWM_SWR_LOOP));
133
134	if (cr & MX3_PWMCR_SWR)
135		dev_warn(dev, "software reset timeout\n");
136}
137
138static void imx_pwm_wait_fifo_slot(struct pwm_chip *chip,
139				   struct pwm_device *pwm)
140{
141	struct imx_chip *imx = to_imx_chip(chip);
142	struct device *dev = chip->dev;
143	unsigned int period_ms;
144	int fifoav;
145	u32 sr;
146
147	sr = readl(imx->mmio_base + MX3_PWMSR);
148	fifoav = sr & MX3_PWMSR_FIFOAV_MASK;
149	if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
150		period_ms = DIV_ROUND_UP(pwm_get_period(pwm),
151					 NSEC_PER_MSEC);
152		msleep(period_ms);
153
154		sr = readl(imx->mmio_base + MX3_PWMSR);
155		if (fifoav == (sr & MX3_PWMSR_FIFOAV_MASK))
156			dev_warn(dev, "there is no free FIFO slot\n");
157	}
158}
159
160static int imx_pwm_apply_v2(struct pwm_chip *chip, struct pwm_device *pwm,
161			    struct pwm_state *state)
162{
163	unsigned long period_cycles, duty_cycles, prescale;
164	struct imx_chip *imx = to_imx_chip(chip);
165	struct pwm_state cstate;
166	unsigned long long c;
167	int ret;
168	u32 cr;
169
170	pwm_get_state(pwm, &cstate);
171
172	if (state->enabled) {
173		c = clk_get_rate(imx->clk_per);
174		c *= state->period;
175
176		do_div(c, 1000000000);
177		period_cycles = c;
178
179		prescale = period_cycles / 0x10000 + 1;
180
181		period_cycles /= prescale;
182		c = (unsigned long long)period_cycles * state->duty_cycle;
183		do_div(c, state->period);
184		duty_cycles = c;
185
186		/*
187		 * according to imx pwm RM, the real period value should be
188		 * PERIOD value in PWMPR plus 2.
189		 */
190		if (period_cycles > 2)
191			period_cycles -= 2;
192		else
193			period_cycles = 0;
194
195		/*
196		 * Wait for a free FIFO slot if the PWM is already enabled, and
197		 * flush the FIFO if the PWM was disabled and is about to be
198		 * enabled.
199		 */
200		if (cstate.enabled) {
201			imx_pwm_wait_fifo_slot(chip, pwm);
202		} else {
203			ret = clk_prepare_enable(imx->clk_per);
204			if (ret)
205				return ret;
206
207			imx_pwm_sw_reset(chip);
208		}
209
210		writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
211		writel(period_cycles, imx->mmio_base + MX3_PWMPR);
212
213		cr = MX3_PWMCR_PRESCALER(prescale) |
214		     MX3_PWMCR_STOPEN | MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
215		     MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH |
216		     MX3_PWMCR_EN;
217
218		if (state->polarity == PWM_POLARITY_INVERSED)
219			cr |= MX3_PWMCR_POUTC;
220
221		writel(cr, imx->mmio_base + MX3_PWMCR);
222	} else if (cstate.enabled) {
223		writel(0, imx->mmio_base + MX3_PWMCR);
224
225		clk_disable_unprepare(imx->clk_per);
226	}
227
228	return 0;
229}
230
231static const struct pwm_ops imx_pwm_ops_v1 = {
232	.enable = imx_pwm_enable_v1,
233	.disable = imx_pwm_disable_v1,
234	.config = imx_pwm_config_v1,
235	.owner = THIS_MODULE,
236};
237
238static const struct pwm_ops imx_pwm_ops_v2 = {
239	.apply = imx_pwm_apply_v2,
240	.owner = THIS_MODULE,
241};
242
243struct imx_pwm_data {
244	bool polarity_supported;
245	const struct pwm_ops *ops;
246};
247
248static struct imx_pwm_data imx_pwm_data_v1 = {
249	.ops = &imx_pwm_ops_v1,
250};
251
252static struct imx_pwm_data imx_pwm_data_v2 = {
253	.polarity_supported = true,
254	.ops = &imx_pwm_ops_v2,
255};
256
257static const struct of_device_id imx_pwm_dt_ids[] = {
258	{ .compatible = "fsl,imx1-pwm", .data = &imx_pwm_data_v1, },
259	{ .compatible = "fsl,imx27-pwm", .data = &imx_pwm_data_v2, },
260	{ /* sentinel */ }
261};
262MODULE_DEVICE_TABLE(of, imx_pwm_dt_ids);
263
264static int imx_pwm_probe(struct platform_device *pdev)
265{
266	const struct of_device_id *of_id =
267			of_match_device(imx_pwm_dt_ids, &pdev->dev);
268	const struct imx_pwm_data *data;
269	struct imx_chip *imx;
270	struct resource *r;
271	int ret = 0;
272
273	if (!of_id)
274		return -ENODEV;
275
276	data = of_id->data;
277
278	imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
279	if (imx == NULL)
280		return -ENOMEM;
281
282	imx->clk_per = devm_clk_get(&pdev->dev, "per");
283	if (IS_ERR(imx->clk_per)) {
284		dev_err(&pdev->dev, "getting per clock failed with %ld\n",
285				PTR_ERR(imx->clk_per));
286		return PTR_ERR(imx->clk_per);
287	}
288
289	imx->chip.ops = data->ops;
290	imx->chip.dev = &pdev->dev;
291	imx->chip.base = -1;
292	imx->chip.npwm = 1;
293
294	if (data->polarity_supported) {
295		dev_dbg(&pdev->dev, "PWM supports output inversion\n");
296		imx->chip.of_xlate = of_pwm_xlate_with_flags;
297		imx->chip.of_pwm_n_cells = 3;
298	}
299
300	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
301	imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
302	if (IS_ERR(imx->mmio_base))
303		return PTR_ERR(imx->mmio_base);
304
305	ret = pwmchip_add(&imx->chip);
306	if (ret < 0)
307		return ret;
308
309	platform_set_drvdata(pdev, imx);
310	return 0;
311}
312
313static int imx_pwm_remove(struct platform_device *pdev)
314{
315	struct imx_chip *imx;
316
317	imx = platform_get_drvdata(pdev);
318	if (imx == NULL)
319		return -ENODEV;
320
321	return pwmchip_remove(&imx->chip);
322}
323
324static struct platform_driver imx_pwm_driver = {
325	.driver		= {
326		.name	= "imx-pwm",
327		.of_match_table = imx_pwm_dt_ids,
328	},
329	.probe		= imx_pwm_probe,
330	.remove		= imx_pwm_remove,
331};
332
333module_platform_driver(imx_pwm_driver);
334
335MODULE_LICENSE("GPL v2");
336MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");