Loading...
Note: File does not exist in v3.15.
1/****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2013 Solarflare Communications Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
9 */
10
11#ifndef EF4_IO_H
12#define EF4_IO_H
13
14#include <linux/io.h>
15#include <linux/spinlock.h>
16
17/**************************************************************************
18 *
19 * NIC register I/O
20 *
21 **************************************************************************
22 *
23 * Notes on locking strategy for the Falcon architecture:
24 *
25 * Many CSRs are very wide and cannot be read or written atomically.
26 * Writes from the host are buffered by the Bus Interface Unit (BIU)
27 * up to 128 bits. Whenever the host writes part of such a register,
28 * the BIU collects the written value and does not write to the
29 * underlying register until all 4 dwords have been written. A
30 * similar buffering scheme applies to host access to the NIC's 64-bit
31 * SRAM.
32 *
33 * Writes to different CSRs and 64-bit SRAM words must be serialised,
34 * since interleaved access can result in lost writes. We use
35 * ef4_nic::biu_lock for this.
36 *
37 * We also serialise reads from 128-bit CSRs and SRAM with the same
38 * spinlock. This may not be necessary, but it doesn't really matter
39 * as there are no such reads on the fast path.
40 *
41 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
42 * 128-bit but are special-cased in the BIU to avoid the need for
43 * locking in the host:
44 *
45 * - They are write-only.
46 * - The semantics of writing to these registers are such that
47 * replacing the low 96 bits with zero does not affect functionality.
48 * - If the host writes to the last dword address of such a register
49 * (i.e. the high 32 bits) the underlying register will always be
50 * written. If the collector and the current write together do not
51 * provide values for all 128 bits of the register, the low 96 bits
52 * will be written as zero.
53 * - If the host writes to the address of any other part of such a
54 * register while the collector already holds values for some other
55 * register, the write is discarded and the collector maintains its
56 * current state.
57 *
58 * The EF10 architecture exposes very few registers to the host and
59 * most of them are only 32 bits wide. The only exceptions are the MC
60 * doorbell register pair, which has its own latching, and
61 * TX_DESC_UPD, which works in a similar way to the Falcon
62 * architecture.
63 */
64
65#if BITS_PER_LONG == 64
66#define EF4_USE_QWORD_IO 1
67#endif
68
69#ifdef EF4_USE_QWORD_IO
70static inline void _ef4_writeq(struct ef4_nic *efx, __le64 value,
71 unsigned int reg)
72{
73 __raw_writeq((__force u64)value, efx->membase + reg);
74}
75static inline __le64 _ef4_readq(struct ef4_nic *efx, unsigned int reg)
76{
77 return (__force __le64)__raw_readq(efx->membase + reg);
78}
79#endif
80
81static inline void _ef4_writed(struct ef4_nic *efx, __le32 value,
82 unsigned int reg)
83{
84 __raw_writel((__force u32)value, efx->membase + reg);
85}
86static inline __le32 _ef4_readd(struct ef4_nic *efx, unsigned int reg)
87{
88 return (__force __le32)__raw_readl(efx->membase + reg);
89}
90
91/* Write a normal 128-bit CSR, locking as appropriate. */
92static inline void ef4_writeo(struct ef4_nic *efx, const ef4_oword_t *value,
93 unsigned int reg)
94{
95 unsigned long flags __attribute__ ((unused));
96
97 netif_vdbg(efx, hw, efx->net_dev,
98 "writing register %x with " EF4_OWORD_FMT "\n", reg,
99 EF4_OWORD_VAL(*value));
100
101 spin_lock_irqsave(&efx->biu_lock, flags);
102#ifdef EF4_USE_QWORD_IO
103 _ef4_writeq(efx, value->u64[0], reg + 0);
104 _ef4_writeq(efx, value->u64[1], reg + 8);
105#else
106 _ef4_writed(efx, value->u32[0], reg + 0);
107 _ef4_writed(efx, value->u32[1], reg + 4);
108 _ef4_writed(efx, value->u32[2], reg + 8);
109 _ef4_writed(efx, value->u32[3], reg + 12);
110#endif
111 mmiowb();
112 spin_unlock_irqrestore(&efx->biu_lock, flags);
113}
114
115/* Write 64-bit SRAM through the supplied mapping, locking as appropriate. */
116static inline void ef4_sram_writeq(struct ef4_nic *efx, void __iomem *membase,
117 const ef4_qword_t *value, unsigned int index)
118{
119 unsigned int addr = index * sizeof(*value);
120 unsigned long flags __attribute__ ((unused));
121
122 netif_vdbg(efx, hw, efx->net_dev,
123 "writing SRAM address %x with " EF4_QWORD_FMT "\n",
124 addr, EF4_QWORD_VAL(*value));
125
126 spin_lock_irqsave(&efx->biu_lock, flags);
127#ifdef EF4_USE_QWORD_IO
128 __raw_writeq((__force u64)value->u64[0], membase + addr);
129#else
130 __raw_writel((__force u32)value->u32[0], membase + addr);
131 __raw_writel((__force u32)value->u32[1], membase + addr + 4);
132#endif
133 mmiowb();
134 spin_unlock_irqrestore(&efx->biu_lock, flags);
135}
136
137/* Write a 32-bit CSR or the last dword of a special 128-bit CSR */
138static inline void ef4_writed(struct ef4_nic *efx, const ef4_dword_t *value,
139 unsigned int reg)
140{
141 netif_vdbg(efx, hw, efx->net_dev,
142 "writing register %x with "EF4_DWORD_FMT"\n",
143 reg, EF4_DWORD_VAL(*value));
144
145 /* No lock required */
146 _ef4_writed(efx, value->u32[0], reg);
147}
148
149/* Read a 128-bit CSR, locking as appropriate. */
150static inline void ef4_reado(struct ef4_nic *efx, ef4_oword_t *value,
151 unsigned int reg)
152{
153 unsigned long flags __attribute__ ((unused));
154
155 spin_lock_irqsave(&efx->biu_lock, flags);
156 value->u32[0] = _ef4_readd(efx, reg + 0);
157 value->u32[1] = _ef4_readd(efx, reg + 4);
158 value->u32[2] = _ef4_readd(efx, reg + 8);
159 value->u32[3] = _ef4_readd(efx, reg + 12);
160 spin_unlock_irqrestore(&efx->biu_lock, flags);
161
162 netif_vdbg(efx, hw, efx->net_dev,
163 "read from register %x, got " EF4_OWORD_FMT "\n", reg,
164 EF4_OWORD_VAL(*value));
165}
166
167/* Read 64-bit SRAM through the supplied mapping, locking as appropriate. */
168static inline void ef4_sram_readq(struct ef4_nic *efx, void __iomem *membase,
169 ef4_qword_t *value, unsigned int index)
170{
171 unsigned int addr = index * sizeof(*value);
172 unsigned long flags __attribute__ ((unused));
173
174 spin_lock_irqsave(&efx->biu_lock, flags);
175#ifdef EF4_USE_QWORD_IO
176 value->u64[0] = (__force __le64)__raw_readq(membase + addr);
177#else
178 value->u32[0] = (__force __le32)__raw_readl(membase + addr);
179 value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4);
180#endif
181 spin_unlock_irqrestore(&efx->biu_lock, flags);
182
183 netif_vdbg(efx, hw, efx->net_dev,
184 "read from SRAM address %x, got "EF4_QWORD_FMT"\n",
185 addr, EF4_QWORD_VAL(*value));
186}
187
188/* Read a 32-bit CSR or SRAM */
189static inline void ef4_readd(struct ef4_nic *efx, ef4_dword_t *value,
190 unsigned int reg)
191{
192 value->u32[0] = _ef4_readd(efx, reg);
193 netif_vdbg(efx, hw, efx->net_dev,
194 "read from register %x, got "EF4_DWORD_FMT"\n",
195 reg, EF4_DWORD_VAL(*value));
196}
197
198/* Write a 128-bit CSR forming part of a table */
199static inline void
200ef4_writeo_table(struct ef4_nic *efx, const ef4_oword_t *value,
201 unsigned int reg, unsigned int index)
202{
203 ef4_writeo(efx, value, reg + index * sizeof(ef4_oword_t));
204}
205
206/* Read a 128-bit CSR forming part of a table */
207static inline void ef4_reado_table(struct ef4_nic *efx, ef4_oword_t *value,
208 unsigned int reg, unsigned int index)
209{
210 ef4_reado(efx, value, reg + index * sizeof(ef4_oword_t));
211}
212
213/* Page size used as step between per-VI registers */
214#define EF4_VI_PAGE_SIZE 0x2000
215
216/* Calculate offset to page-mapped register */
217#define EF4_PAGED_REG(page, reg) \
218 ((page) * EF4_VI_PAGE_SIZE + (reg))
219
220/* Write the whole of RX_DESC_UPD or TX_DESC_UPD */
221static inline void _ef4_writeo_page(struct ef4_nic *efx, ef4_oword_t *value,
222 unsigned int reg, unsigned int page)
223{
224 reg = EF4_PAGED_REG(page, reg);
225
226 netif_vdbg(efx, hw, efx->net_dev,
227 "writing register %x with " EF4_OWORD_FMT "\n", reg,
228 EF4_OWORD_VAL(*value));
229
230#ifdef EF4_USE_QWORD_IO
231 _ef4_writeq(efx, value->u64[0], reg + 0);
232 _ef4_writeq(efx, value->u64[1], reg + 8);
233#else
234 _ef4_writed(efx, value->u32[0], reg + 0);
235 _ef4_writed(efx, value->u32[1], reg + 4);
236 _ef4_writed(efx, value->u32[2], reg + 8);
237 _ef4_writed(efx, value->u32[3], reg + 12);
238#endif
239}
240#define ef4_writeo_page(efx, value, reg, page) \
241 _ef4_writeo_page(efx, value, \
242 reg + \
243 BUILD_BUG_ON_ZERO((reg) != 0x830 && (reg) != 0xa10), \
244 page)
245
246/* Write a page-mapped 32-bit CSR (EVQ_RPTR, EVQ_TMR (EF10), or the
247 * high bits of RX_DESC_UPD or TX_DESC_UPD)
248 */
249static inline void
250_ef4_writed_page(struct ef4_nic *efx, const ef4_dword_t *value,
251 unsigned int reg, unsigned int page)
252{
253 ef4_writed(efx, value, EF4_PAGED_REG(page, reg));
254}
255#define ef4_writed_page(efx, value, reg, page) \
256 _ef4_writed_page(efx, value, \
257 reg + \
258 BUILD_BUG_ON_ZERO((reg) != 0x400 && \
259 (reg) != 0x420 && \
260 (reg) != 0x830 && \
261 (reg) != 0x83c && \
262 (reg) != 0xa18 && \
263 (reg) != 0xa1c), \
264 page)
265
266/* Write TIMER_COMMAND. This is a page-mapped 32-bit CSR, but a bug
267 * in the BIU means that writes to TIMER_COMMAND[0] invalidate the
268 * collector register.
269 */
270static inline void _ef4_writed_page_locked(struct ef4_nic *efx,
271 const ef4_dword_t *value,
272 unsigned int reg,
273 unsigned int page)
274{
275 unsigned long flags __attribute__ ((unused));
276
277 if (page == 0) {
278 spin_lock_irqsave(&efx->biu_lock, flags);
279 ef4_writed(efx, value, EF4_PAGED_REG(page, reg));
280 spin_unlock_irqrestore(&efx->biu_lock, flags);
281 } else {
282 ef4_writed(efx, value, EF4_PAGED_REG(page, reg));
283 }
284}
285#define ef4_writed_page_locked(efx, value, reg, page) \
286 _ef4_writed_page_locked(efx, value, \
287 reg + BUILD_BUG_ON_ZERO((reg) != 0x420), \
288 page)
289
290#endif /* EF4_IO_H */