Loading...
1/* SPDX-License-Identifier: GPL-2.0-only */
2/****************************************************************************
3 * Driver for Solarflare network controllers and boards
4 * Copyright 2005-2006 Fen Systems Ltd.
5 * Copyright 2006-2013 Solarflare Communications Inc.
6 */
7
8#ifndef EF4_IO_H
9#define EF4_IO_H
10
11#include <linux/io.h>
12#include <linux/spinlock.h>
13
14/**************************************************************************
15 *
16 * NIC register I/O
17 *
18 **************************************************************************
19 *
20 * Notes on locking strategy for the Falcon architecture:
21 *
22 * Many CSRs are very wide and cannot be read or written atomically.
23 * Writes from the host are buffered by the Bus Interface Unit (BIU)
24 * up to 128 bits. Whenever the host writes part of such a register,
25 * the BIU collects the written value and does not write to the
26 * underlying register until all 4 dwords have been written. A
27 * similar buffering scheme applies to host access to the NIC's 64-bit
28 * SRAM.
29 *
30 * Writes to different CSRs and 64-bit SRAM words must be serialised,
31 * since interleaved access can result in lost writes. We use
32 * ef4_nic::biu_lock for this.
33 *
34 * We also serialise reads from 128-bit CSRs and SRAM with the same
35 * spinlock. This may not be necessary, but it doesn't really matter
36 * as there are no such reads on the fast path.
37 *
38 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
39 * 128-bit but are special-cased in the BIU to avoid the need for
40 * locking in the host:
41 *
42 * - They are write-only.
43 * - The semantics of writing to these registers are such that
44 * replacing the low 96 bits with zero does not affect functionality.
45 * - If the host writes to the last dword address of such a register
46 * (i.e. the high 32 bits) the underlying register will always be
47 * written. If the collector and the current write together do not
48 * provide values for all 128 bits of the register, the low 96 bits
49 * will be written as zero.
50 * - If the host writes to the address of any other part of such a
51 * register while the collector already holds values for some other
52 * register, the write is discarded and the collector maintains its
53 * current state.
54 *
55 * The EF10 architecture exposes very few registers to the host and
56 * most of them are only 32 bits wide. The only exceptions are the MC
57 * doorbell register pair, which has its own latching, and
58 * TX_DESC_UPD, which works in a similar way to the Falcon
59 * architecture.
60 */
61
62#if BITS_PER_LONG == 64
63#define EF4_USE_QWORD_IO 1
64#endif
65
66#ifdef EF4_USE_QWORD_IO
67static inline void _ef4_writeq(struct ef4_nic *efx, __le64 value,
68 unsigned int reg)
69{
70 __raw_writeq((__force u64)value, efx->membase + reg);
71}
72static inline __le64 _ef4_readq(struct ef4_nic *efx, unsigned int reg)
73{
74 return (__force __le64)__raw_readq(efx->membase + reg);
75}
76#endif
77
78static inline void _ef4_writed(struct ef4_nic *efx, __le32 value,
79 unsigned int reg)
80{
81 __raw_writel((__force u32)value, efx->membase + reg);
82}
83static inline __le32 _ef4_readd(struct ef4_nic *efx, unsigned int reg)
84{
85 return (__force __le32)__raw_readl(efx->membase + reg);
86}
87
88/* Write a normal 128-bit CSR, locking as appropriate. */
89static inline void ef4_writeo(struct ef4_nic *efx, const ef4_oword_t *value,
90 unsigned int reg)
91{
92 unsigned long flags __attribute__ ((unused));
93
94 netif_vdbg(efx, hw, efx->net_dev,
95 "writing register %x with " EF4_OWORD_FMT "\n", reg,
96 EF4_OWORD_VAL(*value));
97
98 spin_lock_irqsave(&efx->biu_lock, flags);
99#ifdef EF4_USE_QWORD_IO
100 _ef4_writeq(efx, value->u64[0], reg + 0);
101 _ef4_writeq(efx, value->u64[1], reg + 8);
102#else
103 _ef4_writed(efx, value->u32[0], reg + 0);
104 _ef4_writed(efx, value->u32[1], reg + 4);
105 _ef4_writed(efx, value->u32[2], reg + 8);
106 _ef4_writed(efx, value->u32[3], reg + 12);
107#endif
108 spin_unlock_irqrestore(&efx->biu_lock, flags);
109}
110
111/* Write 64-bit SRAM through the supplied mapping, locking as appropriate. */
112static inline void ef4_sram_writeq(struct ef4_nic *efx, void __iomem *membase,
113 const ef4_qword_t *value, unsigned int index)
114{
115 unsigned int addr = index * sizeof(*value);
116 unsigned long flags __attribute__ ((unused));
117
118 netif_vdbg(efx, hw, efx->net_dev,
119 "writing SRAM address %x with " EF4_QWORD_FMT "\n",
120 addr, EF4_QWORD_VAL(*value));
121
122 spin_lock_irqsave(&efx->biu_lock, flags);
123#ifdef EF4_USE_QWORD_IO
124 __raw_writeq((__force u64)value->u64[0], membase + addr);
125#else
126 __raw_writel((__force u32)value->u32[0], membase + addr);
127 __raw_writel((__force u32)value->u32[1], membase + addr + 4);
128#endif
129 spin_unlock_irqrestore(&efx->biu_lock, flags);
130}
131
132/* Write a 32-bit CSR or the last dword of a special 128-bit CSR */
133static inline void ef4_writed(struct ef4_nic *efx, const ef4_dword_t *value,
134 unsigned int reg)
135{
136 netif_vdbg(efx, hw, efx->net_dev,
137 "writing register %x with "EF4_DWORD_FMT"\n",
138 reg, EF4_DWORD_VAL(*value));
139
140 /* No lock required */
141 _ef4_writed(efx, value->u32[0], reg);
142}
143
144/* Read a 128-bit CSR, locking as appropriate. */
145static inline void ef4_reado(struct ef4_nic *efx, ef4_oword_t *value,
146 unsigned int reg)
147{
148 unsigned long flags __attribute__ ((unused));
149
150 spin_lock_irqsave(&efx->biu_lock, flags);
151 value->u32[0] = _ef4_readd(efx, reg + 0);
152 value->u32[1] = _ef4_readd(efx, reg + 4);
153 value->u32[2] = _ef4_readd(efx, reg + 8);
154 value->u32[3] = _ef4_readd(efx, reg + 12);
155 spin_unlock_irqrestore(&efx->biu_lock, flags);
156
157 netif_vdbg(efx, hw, efx->net_dev,
158 "read from register %x, got " EF4_OWORD_FMT "\n", reg,
159 EF4_OWORD_VAL(*value));
160}
161
162/* Read 64-bit SRAM through the supplied mapping, locking as appropriate. */
163static inline void ef4_sram_readq(struct ef4_nic *efx, void __iomem *membase,
164 ef4_qword_t *value, unsigned int index)
165{
166 unsigned int addr = index * sizeof(*value);
167 unsigned long flags __attribute__ ((unused));
168
169 spin_lock_irqsave(&efx->biu_lock, flags);
170#ifdef EF4_USE_QWORD_IO
171 value->u64[0] = (__force __le64)__raw_readq(membase + addr);
172#else
173 value->u32[0] = (__force __le32)__raw_readl(membase + addr);
174 value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4);
175#endif
176 spin_unlock_irqrestore(&efx->biu_lock, flags);
177
178 netif_vdbg(efx, hw, efx->net_dev,
179 "read from SRAM address %x, got "EF4_QWORD_FMT"\n",
180 addr, EF4_QWORD_VAL(*value));
181}
182
183/* Read a 32-bit CSR or SRAM */
184static inline void ef4_readd(struct ef4_nic *efx, ef4_dword_t *value,
185 unsigned int reg)
186{
187 value->u32[0] = _ef4_readd(efx, reg);
188 netif_vdbg(efx, hw, efx->net_dev,
189 "read from register %x, got "EF4_DWORD_FMT"\n",
190 reg, EF4_DWORD_VAL(*value));
191}
192
193/* Write a 128-bit CSR forming part of a table */
194static inline void
195ef4_writeo_table(struct ef4_nic *efx, const ef4_oword_t *value,
196 unsigned int reg, unsigned int index)
197{
198 ef4_writeo(efx, value, reg + index * sizeof(ef4_oword_t));
199}
200
201/* Read a 128-bit CSR forming part of a table */
202static inline void ef4_reado_table(struct ef4_nic *efx, ef4_oword_t *value,
203 unsigned int reg, unsigned int index)
204{
205 ef4_reado(efx, value, reg + index * sizeof(ef4_oword_t));
206}
207
208/* Page size used as step between per-VI registers */
209#define EF4_VI_PAGE_SIZE 0x2000
210
211/* Calculate offset to page-mapped register */
212#define EF4_PAGED_REG(page, reg) \
213 ((page) * EF4_VI_PAGE_SIZE + (reg))
214
215/* Write the whole of RX_DESC_UPD or TX_DESC_UPD */
216static inline void _ef4_writeo_page(struct ef4_nic *efx, ef4_oword_t *value,
217 unsigned int reg, unsigned int page)
218{
219 reg = EF4_PAGED_REG(page, reg);
220
221 netif_vdbg(efx, hw, efx->net_dev,
222 "writing register %x with " EF4_OWORD_FMT "\n", reg,
223 EF4_OWORD_VAL(*value));
224
225#ifdef EF4_USE_QWORD_IO
226 _ef4_writeq(efx, value->u64[0], reg + 0);
227 _ef4_writeq(efx, value->u64[1], reg + 8);
228#else
229 _ef4_writed(efx, value->u32[0], reg + 0);
230 _ef4_writed(efx, value->u32[1], reg + 4);
231 _ef4_writed(efx, value->u32[2], reg + 8);
232 _ef4_writed(efx, value->u32[3], reg + 12);
233#endif
234}
235#define ef4_writeo_page(efx, value, reg, page) \
236 _ef4_writeo_page(efx, value, \
237 reg + \
238 BUILD_BUG_ON_ZERO((reg) != 0x830 && (reg) != 0xa10), \
239 page)
240
241/* Write a page-mapped 32-bit CSR (EVQ_RPTR, EVQ_TMR (EF10), or the
242 * high bits of RX_DESC_UPD or TX_DESC_UPD)
243 */
244static inline void
245_ef4_writed_page(struct ef4_nic *efx, const ef4_dword_t *value,
246 unsigned int reg, unsigned int page)
247{
248 ef4_writed(efx, value, EF4_PAGED_REG(page, reg));
249}
250#define ef4_writed_page(efx, value, reg, page) \
251 _ef4_writed_page(efx, value, \
252 reg + \
253 BUILD_BUG_ON_ZERO((reg) != 0x400 && \
254 (reg) != 0x420 && \
255 (reg) != 0x830 && \
256 (reg) != 0x83c && \
257 (reg) != 0xa18 && \
258 (reg) != 0xa1c), \
259 page)
260
261/* Write TIMER_COMMAND. This is a page-mapped 32-bit CSR, but a bug
262 * in the BIU means that writes to TIMER_COMMAND[0] invalidate the
263 * collector register.
264 */
265static inline void _ef4_writed_page_locked(struct ef4_nic *efx,
266 const ef4_dword_t *value,
267 unsigned int reg,
268 unsigned int page)
269{
270 unsigned long flags __attribute__ ((unused));
271
272 if (page == 0) {
273 spin_lock_irqsave(&efx->biu_lock, flags);
274 ef4_writed(efx, value, EF4_PAGED_REG(page, reg));
275 spin_unlock_irqrestore(&efx->biu_lock, flags);
276 } else {
277 ef4_writed(efx, value, EF4_PAGED_REG(page, reg));
278 }
279}
280#define ef4_writed_page_locked(efx, value, reg, page) \
281 _ef4_writed_page_locked(efx, value, \
282 reg + BUILD_BUG_ON_ZERO((reg) != 0x420), \
283 page)
284
285#endif /* EF4_IO_H */