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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit
4 *
5 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
6 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
7 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
8 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
9 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
10 */
11
12
13#include <linux/linkage.h>
14#include <linux/threads.h>
15#include <linux/init.h>
16#include <asm/segment.h>
17#include <asm/pgtable.h>
18#include <asm/page.h>
19#include <asm/msr.h>
20#include <asm/cache.h>
21#include <asm/processor-flags.h>
22#include <asm/percpu.h>
23#include <asm/nops.h>
24#include "../entry/calling.h"
25#include <asm/export.h>
26#include <asm/nospec-branch.h>
27
28#ifdef CONFIG_PARAVIRT
29#include <asm/asm-offsets.h>
30#include <asm/paravirt.h>
31#define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg
32#else
33#define GET_CR2_INTO(reg) movq %cr2, reg
34#define INTERRUPT_RETURN iretq
35#endif
36
37/* we are not able to switch in one step to the final KERNEL ADDRESS SPACE
38 * because we need identity-mapped pages.
39 *
40 */
41
42#define l4_index(x) (((x) >> 39) & 511)
43#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
44
45L4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE_L4)
46L4_START_KERNEL = l4_index(__START_KERNEL_map)
47
48L3_START_KERNEL = pud_index(__START_KERNEL_map)
49
50 .text
51 __HEAD
52 .code64
53 .globl startup_64
54startup_64:
55 UNWIND_HINT_EMPTY
56 /*
57 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
58 * and someone has loaded an identity mapped page table
59 * for us. These identity mapped page tables map all of the
60 * kernel pages and possibly all of memory.
61 *
62 * %rsi holds a physical pointer to real_mode_data.
63 *
64 * We come here either directly from a 64bit bootloader, or from
65 * arch/x86/boot/compressed/head_64.S.
66 *
67 * We only come here initially at boot nothing else comes here.
68 *
69 * Since we may be loaded at an address different from what we were
70 * compiled to run at we first fixup the physical addresses in our page
71 * tables and then reload them.
72 */
73
74 /* Set up the stack for verify_cpu(), similar to initial_stack below */
75 leaq (__end_init_task - SIZEOF_PTREGS)(%rip), %rsp
76
77 /* Sanitize CPU configuration */
78 call verify_cpu
79
80 /*
81 * Perform pagetable fixups. Additionally, if SME is active, encrypt
82 * the kernel and retrieve the modifier (SME encryption mask if SME
83 * is active) to be added to the initial pgdir entry that will be
84 * programmed into CR3.
85 */
86 leaq _text(%rip), %rdi
87 pushq %rsi
88 call __startup_64
89 popq %rsi
90
91 /* Form the CR3 value being sure to include the CR3 modifier */
92 addq $(early_top_pgt - __START_KERNEL_map), %rax
93 jmp 1f
94ENTRY(secondary_startup_64)
95 UNWIND_HINT_EMPTY
96 /*
97 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
98 * and someone has loaded a mapped page table.
99 *
100 * %rsi holds a physical pointer to real_mode_data.
101 *
102 * We come here either from startup_64 (using physical addresses)
103 * or from trampoline.S (using virtual addresses).
104 *
105 * Using virtual addresses from trampoline.S removes the need
106 * to have any identity mapped pages in the kernel page table
107 * after the boot processor executes this code.
108 */
109
110 /* Sanitize CPU configuration */
111 call verify_cpu
112
113 /*
114 * Retrieve the modifier (SME encryption mask if SME is active) to be
115 * added to the initial pgdir entry that will be programmed into CR3.
116 */
117 pushq %rsi
118 call __startup_secondary_64
119 popq %rsi
120
121 /* Form the CR3 value being sure to include the CR3 modifier */
122 addq $(init_top_pgt - __START_KERNEL_map), %rax
1231:
124
125 /* Enable PAE mode, PGE and LA57 */
126 movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx
127#ifdef CONFIG_X86_5LEVEL
128 testl $1, __pgtable_l5_enabled(%rip)
129 jz 1f
130 orl $X86_CR4_LA57, %ecx
1311:
132#endif
133 movq %rcx, %cr4
134
135 /* Setup early boot stage 4-/5-level pagetables. */
136 addq phys_base(%rip), %rax
137 movq %rax, %cr3
138
139 /* Ensure I am executing from virtual addresses */
140 movq $1f, %rax
141 ANNOTATE_RETPOLINE_SAFE
142 jmp *%rax
1431:
144 UNWIND_HINT_EMPTY
145
146 /* Check if nx is implemented */
147 movl $0x80000001, %eax
148 cpuid
149 movl %edx,%edi
150
151 /* Setup EFER (Extended Feature Enable Register) */
152 movl $MSR_EFER, %ecx
153 rdmsr
154 btsl $_EFER_SCE, %eax /* Enable System Call */
155 btl $20,%edi /* No Execute supported? */
156 jnc 1f
157 btsl $_EFER_NX, %eax
158 btsq $_PAGE_BIT_NX,early_pmd_flags(%rip)
1591: wrmsr /* Make changes effective */
160
161 /* Setup cr0 */
162 movl $CR0_STATE, %eax
163 /* Make changes effective */
164 movq %rax, %cr0
165
166 /* Setup a boot time stack */
167 movq initial_stack(%rip), %rsp
168
169 /* zero EFLAGS after setting rsp */
170 pushq $0
171 popfq
172
173 /*
174 * We must switch to a new descriptor in kernel space for the GDT
175 * because soon the kernel won't have access anymore to the userspace
176 * addresses where we're currently running on. We have to do that here
177 * because in 32bit we couldn't load a 64bit linear address.
178 */
179 lgdt early_gdt_descr(%rip)
180
181 /* set up data segments */
182 xorl %eax,%eax
183 movl %eax,%ds
184 movl %eax,%ss
185 movl %eax,%es
186
187 /*
188 * We don't really need to load %fs or %gs, but load them anyway
189 * to kill any stale realmode selectors. This allows execution
190 * under VT hardware.
191 */
192 movl %eax,%fs
193 movl %eax,%gs
194
195 /* Set up %gs.
196 *
197 * The base of %gs always points to the bottom of the irqstack
198 * union. If the stack protector canary is enabled, it is
199 * located at %gs:40. Note that, on SMP, the boot cpu uses
200 * init data section till per cpu areas are set up.
201 */
202 movl $MSR_GS_BASE,%ecx
203 movl initial_gs(%rip),%eax
204 movl initial_gs+4(%rip),%edx
205 wrmsr
206
207 /* rsi is pointer to real mode structure with interesting info.
208 pass it to C */
209 movq %rsi, %rdi
210
211.Ljump_to_C_code:
212 /*
213 * Jump to run C code and to be on a real kernel address.
214 * Since we are running on identity-mapped space we have to jump
215 * to the full 64bit address, this is only possible as indirect
216 * jump. In addition we need to ensure %cs is set so we make this
217 * a far return.
218 *
219 * Note: do not change to far jump indirect with 64bit offset.
220 *
221 * AMD does not support far jump indirect with 64bit offset.
222 * AMD64 Architecture Programmer's Manual, Volume 3: states only
223 * JMP FAR mem16:16 FF /5 Far jump indirect,
224 * with the target specified by a far pointer in memory.
225 * JMP FAR mem16:32 FF /5 Far jump indirect,
226 * with the target specified by a far pointer in memory.
227 *
228 * Intel64 does support 64bit offset.
229 * Software Developer Manual Vol 2: states:
230 * FF /5 JMP m16:16 Jump far, absolute indirect,
231 * address given in m16:16
232 * FF /5 JMP m16:32 Jump far, absolute indirect,
233 * address given in m16:32.
234 * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect,
235 * address given in m16:64.
236 */
237 pushq $.Lafter_lret # put return address on stack for unwinder
238 xorq %rbp, %rbp # clear frame pointer
239 movq initial_code(%rip), %rax
240 pushq $__KERNEL_CS # set correct cs
241 pushq %rax # target address in negative space
242 lretq
243.Lafter_lret:
244END(secondary_startup_64)
245
246#include "verify_cpu.S"
247
248#ifdef CONFIG_HOTPLUG_CPU
249/*
250 * Boot CPU0 entry point. It's called from play_dead(). Everything has been set
251 * up already except stack. We just set up stack here. Then call
252 * start_secondary() via .Ljump_to_C_code.
253 */
254ENTRY(start_cpu0)
255 movq initial_stack(%rip), %rsp
256 UNWIND_HINT_EMPTY
257 jmp .Ljump_to_C_code
258ENDPROC(start_cpu0)
259#endif
260
261 /* Both SMP bootup and ACPI suspend change these variables */
262 __REFDATA
263 .balign 8
264 GLOBAL(initial_code)
265 .quad x86_64_start_kernel
266 GLOBAL(initial_gs)
267 .quad INIT_PER_CPU_VAR(irq_stack_union)
268 GLOBAL(initial_stack)
269 /*
270 * The SIZEOF_PTREGS gap is a convention which helps the in-kernel
271 * unwinder reliably detect the end of the stack.
272 */
273 .quad init_thread_union + THREAD_SIZE - SIZEOF_PTREGS
274 __FINITDATA
275
276 __INIT
277ENTRY(early_idt_handler_array)
278 i = 0
279 .rept NUM_EXCEPTION_VECTORS
280 .if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0
281 UNWIND_HINT_IRET_REGS
282 pushq $0 # Dummy error code, to make stack frame uniform
283 .else
284 UNWIND_HINT_IRET_REGS offset=8
285 .endif
286 pushq $i # 72(%rsp) Vector number
287 jmp early_idt_handler_common
288 UNWIND_HINT_IRET_REGS
289 i = i + 1
290 .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc
291 .endr
292 UNWIND_HINT_IRET_REGS offset=16
293END(early_idt_handler_array)
294
295early_idt_handler_common:
296 /*
297 * The stack is the hardware frame, an error code or zero, and the
298 * vector number.
299 */
300 cld
301
302 incl early_recursion_flag(%rip)
303
304 /* The vector number is currently in the pt_regs->di slot. */
305 pushq %rsi /* pt_regs->si */
306 movq 8(%rsp), %rsi /* RSI = vector number */
307 movq %rdi, 8(%rsp) /* pt_regs->di = RDI */
308 pushq %rdx /* pt_regs->dx */
309 pushq %rcx /* pt_regs->cx */
310 pushq %rax /* pt_regs->ax */
311 pushq %r8 /* pt_regs->r8 */
312 pushq %r9 /* pt_regs->r9 */
313 pushq %r10 /* pt_regs->r10 */
314 pushq %r11 /* pt_regs->r11 */
315 pushq %rbx /* pt_regs->bx */
316 pushq %rbp /* pt_regs->bp */
317 pushq %r12 /* pt_regs->r12 */
318 pushq %r13 /* pt_regs->r13 */
319 pushq %r14 /* pt_regs->r14 */
320 pushq %r15 /* pt_regs->r15 */
321 UNWIND_HINT_REGS
322
323 cmpq $14,%rsi /* Page fault? */
324 jnz 10f
325 GET_CR2_INTO(%rdi) /* Can clobber any volatile register if pv */
326 call early_make_pgtable
327 andl %eax,%eax
328 jz 20f /* All good */
329
33010:
331 movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */
332 call early_fixup_exception
333
33420:
335 decl early_recursion_flag(%rip)
336 jmp restore_regs_and_return_to_kernel
337END(early_idt_handler_common)
338
339 __INITDATA
340
341 .balign 4
342GLOBAL(early_recursion_flag)
343 .long 0
344
345#define NEXT_PAGE(name) \
346 .balign PAGE_SIZE; \
347GLOBAL(name)
348
349#ifdef CONFIG_PAGE_TABLE_ISOLATION
350/*
351 * Each PGD needs to be 8k long and 8k aligned. We do not
352 * ever go out to userspace with these, so we do not
353 * strictly *need* the second page, but this allows us to
354 * have a single set_pgd() implementation that does not
355 * need to worry about whether it has 4k or 8k to work
356 * with.
357 *
358 * This ensures PGDs are 8k long:
359 */
360#define PTI_USER_PGD_FILL 512
361/* This ensures they are 8k-aligned: */
362#define NEXT_PGD_PAGE(name) \
363 .balign 2 * PAGE_SIZE; \
364GLOBAL(name)
365#else
366#define NEXT_PGD_PAGE(name) NEXT_PAGE(name)
367#define PTI_USER_PGD_FILL 0
368#endif
369
370/* Automate the creation of 1 to 1 mapping pmd entries */
371#define PMDS(START, PERM, COUNT) \
372 i = 0 ; \
373 .rept (COUNT) ; \
374 .quad (START) + (i << PMD_SHIFT) + (PERM) ; \
375 i = i + 1 ; \
376 .endr
377
378 __INITDATA
379NEXT_PGD_PAGE(early_top_pgt)
380 .fill 512,8,0
381 .fill PTI_USER_PGD_FILL,8,0
382
383NEXT_PAGE(early_dynamic_pgts)
384 .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0
385
386 .data
387
388#if defined(CONFIG_XEN_PV) || defined(CONFIG_XEN_PVH)
389NEXT_PGD_PAGE(init_top_pgt)
390 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
391 .org init_top_pgt + L4_PAGE_OFFSET*8, 0
392 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
393 .org init_top_pgt + L4_START_KERNEL*8, 0
394 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
395 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
396 .fill PTI_USER_PGD_FILL,8,0
397
398NEXT_PAGE(level3_ident_pgt)
399 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
400 .fill 511, 8, 0
401NEXT_PAGE(level2_ident_pgt)
402 /*
403 * Since I easily can, map the first 1G.
404 * Don't set NX because code runs from these pages.
405 *
406 * Note: This sets _PAGE_GLOBAL despite whether
407 * the CPU supports it or it is enabled. But,
408 * the CPU should ignore the bit.
409 */
410 PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
411#else
412NEXT_PGD_PAGE(init_top_pgt)
413 .fill 512,8,0
414 .fill PTI_USER_PGD_FILL,8,0
415#endif
416
417#ifdef CONFIG_X86_5LEVEL
418NEXT_PAGE(level4_kernel_pgt)
419 .fill 511,8,0
420 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
421#endif
422
423NEXT_PAGE(level3_kernel_pgt)
424 .fill L3_START_KERNEL,8,0
425 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
426 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
427 .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
428
429NEXT_PAGE(level2_kernel_pgt)
430 /*
431 * 512 MB kernel mapping. We spend a full page on this pagetable
432 * anyway.
433 *
434 * The kernel code+data+bss must not be bigger than that.
435 *
436 * (NOTE: at +512MB starts the module area, see MODULES_VADDR.
437 * If you want to increase this then increase MODULES_VADDR
438 * too.)
439 *
440 * This table is eventually used by the kernel during normal
441 * runtime. Care must be taken to clear out undesired bits
442 * later, like _PAGE_RW or _PAGE_GLOBAL in some cases.
443 */
444 PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
445 KERNEL_IMAGE_SIZE/PMD_SIZE)
446
447NEXT_PAGE(level2_fixmap_pgt)
448 .fill 506,8,0
449 .quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
450 /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */
451 .fill 5,8,0
452
453NEXT_PAGE(level1_fixmap_pgt)
454 .fill 512,8,0
455
456#undef PMDS
457
458 .data
459 .align 16
460 .globl early_gdt_descr
461early_gdt_descr:
462 .word GDT_ENTRIES*8-1
463early_gdt_descr_base:
464 .quad INIT_PER_CPU_VAR(gdt_page)
465
466ENTRY(phys_base)
467 /* This must match the first entry in level2_kernel_pgt */
468 .quad 0x0000000000000000
469EXPORT_SYMBOL(phys_base)
470
471#include "../../x86/xen/xen-head.S"
472
473 __PAGE_ALIGNED_BSS
474NEXT_PAGE(empty_zero_page)
475 .skip PAGE_SIZE
476EXPORT_SYMBOL(empty_zero_page)
477
1/*
2 * linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
3 *
4 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
5 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
6 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
7 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
8 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
9 */
10
11
12#include <linux/linkage.h>
13#include <linux/threads.h>
14#include <linux/init.h>
15#include <asm/segment.h>
16#include <asm/pgtable.h>
17#include <asm/page.h>
18#include <asm/msr.h>
19#include <asm/cache.h>
20#include <asm/processor-flags.h>
21#include <asm/percpu.h>
22#include <asm/nops.h>
23
24#ifdef CONFIG_PARAVIRT
25#include <asm/asm-offsets.h>
26#include <asm/paravirt.h>
27#define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg
28#else
29#define GET_CR2_INTO(reg) movq %cr2, reg
30#define INTERRUPT_RETURN iretq
31#endif
32
33/* we are not able to switch in one step to the final KERNEL ADDRESS SPACE
34 * because we need identity-mapped pages.
35 *
36 */
37
38#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
39
40L4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET)
41L3_PAGE_OFFSET = pud_index(__PAGE_OFFSET)
42L4_START_KERNEL = pgd_index(__START_KERNEL_map)
43L3_START_KERNEL = pud_index(__START_KERNEL_map)
44
45 .text
46 __HEAD
47 .code64
48 .globl startup_64
49startup_64:
50 /*
51 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
52 * and someone has loaded an identity mapped page table
53 * for us. These identity mapped page tables map all of the
54 * kernel pages and possibly all of memory.
55 *
56 * %rsi holds a physical pointer to real_mode_data.
57 *
58 * We come here either directly from a 64bit bootloader, or from
59 * arch/x86_64/boot/compressed/head.S.
60 *
61 * We only come here initially at boot nothing else comes here.
62 *
63 * Since we may be loaded at an address different from what we were
64 * compiled to run at we first fixup the physical addresses in our page
65 * tables and then reload them.
66 */
67
68 /*
69 * Compute the delta between the address I am compiled to run at and the
70 * address I am actually running at.
71 */
72 leaq _text(%rip), %rbp
73 subq $_text - __START_KERNEL_map, %rbp
74
75 /* Is the address not 2M aligned? */
76 movq %rbp, %rax
77 andl $~PMD_PAGE_MASK, %eax
78 testl %eax, %eax
79 jnz bad_address
80
81 /*
82 * Is the address too large?
83 */
84 leaq _text(%rip), %rax
85 shrq $MAX_PHYSMEM_BITS, %rax
86 jnz bad_address
87
88 /*
89 * Fixup the physical addresses in the page table
90 */
91 addq %rbp, early_level4_pgt + (L4_START_KERNEL*8)(%rip)
92
93 addq %rbp, level3_kernel_pgt + (510*8)(%rip)
94 addq %rbp, level3_kernel_pgt + (511*8)(%rip)
95
96 addq %rbp, level2_fixmap_pgt + (506*8)(%rip)
97
98 /*
99 * Set up the identity mapping for the switchover. These
100 * entries should *NOT* have the global bit set! This also
101 * creates a bunch of nonsense entries but that is fine --
102 * it avoids problems around wraparound.
103 */
104 leaq _text(%rip), %rdi
105 leaq early_level4_pgt(%rip), %rbx
106
107 movq %rdi, %rax
108 shrq $PGDIR_SHIFT, %rax
109
110 leaq (4096 + _KERNPG_TABLE)(%rbx), %rdx
111 movq %rdx, 0(%rbx,%rax,8)
112 movq %rdx, 8(%rbx,%rax,8)
113
114 addq $4096, %rdx
115 movq %rdi, %rax
116 shrq $PUD_SHIFT, %rax
117 andl $(PTRS_PER_PUD-1), %eax
118 movq %rdx, 4096(%rbx,%rax,8)
119 incl %eax
120 andl $(PTRS_PER_PUD-1), %eax
121 movq %rdx, 4096(%rbx,%rax,8)
122
123 addq $8192, %rbx
124 movq %rdi, %rax
125 shrq $PMD_SHIFT, %rdi
126 addq $(__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL), %rax
127 leaq (_end - 1)(%rip), %rcx
128 shrq $PMD_SHIFT, %rcx
129 subq %rdi, %rcx
130 incl %ecx
131
1321:
133 andq $(PTRS_PER_PMD - 1), %rdi
134 movq %rax, (%rbx,%rdi,8)
135 incq %rdi
136 addq $PMD_SIZE, %rax
137 decl %ecx
138 jnz 1b
139
140 /*
141 * Fixup the kernel text+data virtual addresses. Note that
142 * we might write invalid pmds, when the kernel is relocated
143 * cleanup_highmap() fixes this up along with the mappings
144 * beyond _end.
145 */
146 leaq level2_kernel_pgt(%rip), %rdi
147 leaq 4096(%rdi), %r8
148 /* See if it is a valid page table entry */
1491: testq $1, 0(%rdi)
150 jz 2f
151 addq %rbp, 0(%rdi)
152 /* Go to the next page */
1532: addq $8, %rdi
154 cmp %r8, %rdi
155 jne 1b
156
157 /* Fixup phys_base */
158 addq %rbp, phys_base(%rip)
159
160 movq $(early_level4_pgt - __START_KERNEL_map), %rax
161 jmp 1f
162ENTRY(secondary_startup_64)
163 /*
164 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
165 * and someone has loaded a mapped page table.
166 *
167 * %rsi holds a physical pointer to real_mode_data.
168 *
169 * We come here either from startup_64 (using physical addresses)
170 * or from trampoline.S (using virtual addresses).
171 *
172 * Using virtual addresses from trampoline.S removes the need
173 * to have any identity mapped pages in the kernel page table
174 * after the boot processor executes this code.
175 */
176
177 movq $(init_level4_pgt - __START_KERNEL_map), %rax
1781:
179
180 /* Enable PAE mode and PGE */
181 movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx
182 movq %rcx, %cr4
183
184 /* Setup early boot stage 4 level pagetables. */
185 addq phys_base(%rip), %rax
186 movq %rax, %cr3
187
188 /* Ensure I am executing from virtual addresses */
189 movq $1f, %rax
190 jmp *%rax
1911:
192
193 /* Check if nx is implemented */
194 movl $0x80000001, %eax
195 cpuid
196 movl %edx,%edi
197
198 /* Setup EFER (Extended Feature Enable Register) */
199 movl $MSR_EFER, %ecx
200 rdmsr
201 btsl $_EFER_SCE, %eax /* Enable System Call */
202 btl $20,%edi /* No Execute supported? */
203 jnc 1f
204 btsl $_EFER_NX, %eax
205 btsq $_PAGE_BIT_NX,early_pmd_flags(%rip)
2061: wrmsr /* Make changes effective */
207
208 /* Setup cr0 */
209#define CR0_STATE (X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \
210 X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \
211 X86_CR0_PG)
212 movl $CR0_STATE, %eax
213 /* Make changes effective */
214 movq %rax, %cr0
215
216 /* Setup a boot time stack */
217 movq stack_start(%rip), %rsp
218
219 /* zero EFLAGS after setting rsp */
220 pushq $0
221 popfq
222
223 /*
224 * We must switch to a new descriptor in kernel space for the GDT
225 * because soon the kernel won't have access anymore to the userspace
226 * addresses where we're currently running on. We have to do that here
227 * because in 32bit we couldn't load a 64bit linear address.
228 */
229 lgdt early_gdt_descr(%rip)
230
231 /* set up data segments */
232 xorl %eax,%eax
233 movl %eax,%ds
234 movl %eax,%ss
235 movl %eax,%es
236
237 /*
238 * We don't really need to load %fs or %gs, but load them anyway
239 * to kill any stale realmode selectors. This allows execution
240 * under VT hardware.
241 */
242 movl %eax,%fs
243 movl %eax,%gs
244
245 /* Set up %gs.
246 *
247 * The base of %gs always points to the bottom of the irqstack
248 * union. If the stack protector canary is enabled, it is
249 * located at %gs:40. Note that, on SMP, the boot cpu uses
250 * init data section till per cpu areas are set up.
251 */
252 movl $MSR_GS_BASE,%ecx
253 movl initial_gs(%rip),%eax
254 movl initial_gs+4(%rip),%edx
255 wrmsr
256
257 /* rsi is pointer to real mode structure with interesting info.
258 pass it to C */
259 movq %rsi, %rdi
260
261 /* Finally jump to run C code and to be on real kernel address
262 * Since we are running on identity-mapped space we have to jump
263 * to the full 64bit address, this is only possible as indirect
264 * jump. In addition we need to ensure %cs is set so we make this
265 * a far return.
266 *
267 * Note: do not change to far jump indirect with 64bit offset.
268 *
269 * AMD does not support far jump indirect with 64bit offset.
270 * AMD64 Architecture Programmer's Manual, Volume 3: states only
271 * JMP FAR mem16:16 FF /5 Far jump indirect,
272 * with the target specified by a far pointer in memory.
273 * JMP FAR mem16:32 FF /5 Far jump indirect,
274 * with the target specified by a far pointer in memory.
275 *
276 * Intel64 does support 64bit offset.
277 * Software Developer Manual Vol 2: states:
278 * FF /5 JMP m16:16 Jump far, absolute indirect,
279 * address given in m16:16
280 * FF /5 JMP m16:32 Jump far, absolute indirect,
281 * address given in m16:32.
282 * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect,
283 * address given in m16:64.
284 */
285 movq initial_code(%rip),%rax
286 pushq $0 # fake return address to stop unwinder
287 pushq $__KERNEL_CS # set correct cs
288 pushq %rax # target address in negative space
289 lretq
290
291#ifdef CONFIG_HOTPLUG_CPU
292/*
293 * Boot CPU0 entry point. It's called from play_dead(). Everything has been set
294 * up already except stack. We just set up stack here. Then call
295 * start_secondary().
296 */
297ENTRY(start_cpu0)
298 movq stack_start(%rip),%rsp
299 movq initial_code(%rip),%rax
300 pushq $0 # fake return address to stop unwinder
301 pushq $__KERNEL_CS # set correct cs
302 pushq %rax # target address in negative space
303 lretq
304ENDPROC(start_cpu0)
305#endif
306
307 /* SMP bootup changes these two */
308 __REFDATA
309 .balign 8
310 GLOBAL(initial_code)
311 .quad x86_64_start_kernel
312 GLOBAL(initial_gs)
313 .quad INIT_PER_CPU_VAR(irq_stack_union)
314
315 GLOBAL(stack_start)
316 .quad init_thread_union+THREAD_SIZE-8
317 .word 0
318 __FINITDATA
319
320bad_address:
321 jmp bad_address
322
323 __INIT
324 .globl early_idt_handlers
325early_idt_handlers:
326 # 104(%rsp) %rflags
327 # 96(%rsp) %cs
328 # 88(%rsp) %rip
329 # 80(%rsp) error code
330 i = 0
331 .rept NUM_EXCEPTION_VECTORS
332 .if (EXCEPTION_ERRCODE_MASK >> i) & 1
333 ASM_NOP2
334 .else
335 pushq $0 # Dummy error code, to make stack frame uniform
336 .endif
337 pushq $i # 72(%rsp) Vector number
338 jmp early_idt_handler
339 i = i + 1
340 .endr
341
342/* This is global to keep gas from relaxing the jumps */
343ENTRY(early_idt_handler)
344 cld
345
346 cmpl $2,(%rsp) # X86_TRAP_NMI
347 je is_nmi # Ignore NMI
348
349 cmpl $2,early_recursion_flag(%rip)
350 jz 1f
351 incl early_recursion_flag(%rip)
352
353 pushq %rax # 64(%rsp)
354 pushq %rcx # 56(%rsp)
355 pushq %rdx # 48(%rsp)
356 pushq %rsi # 40(%rsp)
357 pushq %rdi # 32(%rsp)
358 pushq %r8 # 24(%rsp)
359 pushq %r9 # 16(%rsp)
360 pushq %r10 # 8(%rsp)
361 pushq %r11 # 0(%rsp)
362
363 cmpl $__KERNEL_CS,96(%rsp)
364 jne 11f
365
366 cmpl $14,72(%rsp) # Page fault?
367 jnz 10f
368 GET_CR2_INTO(%rdi) # can clobber any volatile register if pv
369 call early_make_pgtable
370 andl %eax,%eax
371 jz 20f # All good
372
37310:
374 leaq 88(%rsp),%rdi # Pointer to %rip
375 call early_fixup_exception
376 andl %eax,%eax
377 jnz 20f # Found an exception entry
378
37911:
380#ifdef CONFIG_EARLY_PRINTK
381 GET_CR2_INTO(%r9) # can clobber any volatile register if pv
382 movl 80(%rsp),%r8d # error code
383 movl 72(%rsp),%esi # vector number
384 movl 96(%rsp),%edx # %cs
385 movq 88(%rsp),%rcx # %rip
386 xorl %eax,%eax
387 leaq early_idt_msg(%rip),%rdi
388 call early_printk
389 cmpl $2,early_recursion_flag(%rip)
390 jz 1f
391 call dump_stack
392#ifdef CONFIG_KALLSYMS
393 leaq early_idt_ripmsg(%rip),%rdi
394 movq 40(%rsp),%rsi # %rip again
395 call __print_symbol
396#endif
397#endif /* EARLY_PRINTK */
3981: hlt
399 jmp 1b
400
40120: # Exception table entry found or page table generated
402 popq %r11
403 popq %r10
404 popq %r9
405 popq %r8
406 popq %rdi
407 popq %rsi
408 popq %rdx
409 popq %rcx
410 popq %rax
411 decl early_recursion_flag(%rip)
412is_nmi:
413 addq $16,%rsp # drop vector number and error code
414 INTERRUPT_RETURN
415ENDPROC(early_idt_handler)
416
417 __INITDATA
418
419 .balign 4
420early_recursion_flag:
421 .long 0
422
423#ifdef CONFIG_EARLY_PRINTK
424early_idt_msg:
425 .asciz "PANIC: early exception %02lx rip %lx:%lx error %lx cr2 %lx\n"
426early_idt_ripmsg:
427 .asciz "RIP %s\n"
428#endif /* CONFIG_EARLY_PRINTK */
429
430#define NEXT_PAGE(name) \
431 .balign PAGE_SIZE; \
432GLOBAL(name)
433
434/* Automate the creation of 1 to 1 mapping pmd entries */
435#define PMDS(START, PERM, COUNT) \
436 i = 0 ; \
437 .rept (COUNT) ; \
438 .quad (START) + (i << PMD_SHIFT) + (PERM) ; \
439 i = i + 1 ; \
440 .endr
441
442 __INITDATA
443NEXT_PAGE(early_level4_pgt)
444 .fill 511,8,0
445 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
446
447NEXT_PAGE(early_dynamic_pgts)
448 .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0
449
450 .data
451
452#ifndef CONFIG_XEN
453NEXT_PAGE(init_level4_pgt)
454 .fill 512,8,0
455#else
456NEXT_PAGE(init_level4_pgt)
457 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
458 .org init_level4_pgt + L4_PAGE_OFFSET*8, 0
459 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
460 .org init_level4_pgt + L4_START_KERNEL*8, 0
461 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
462 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
463
464NEXT_PAGE(level3_ident_pgt)
465 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
466 .fill 511, 8, 0
467NEXT_PAGE(level2_ident_pgt)
468 /* Since I easily can, map the first 1G.
469 * Don't set NX because code runs from these pages.
470 */
471 PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
472#endif
473
474NEXT_PAGE(level3_kernel_pgt)
475 .fill L3_START_KERNEL,8,0
476 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
477 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
478 .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
479
480NEXT_PAGE(level2_kernel_pgt)
481 /*
482 * 512 MB kernel mapping. We spend a full page on this pagetable
483 * anyway.
484 *
485 * The kernel code+data+bss must not be bigger than that.
486 *
487 * (NOTE: at +512MB starts the module area, see MODULES_VADDR.
488 * If you want to increase this then increase MODULES_VADDR
489 * too.)
490 */
491 PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
492 KERNEL_IMAGE_SIZE/PMD_SIZE)
493
494NEXT_PAGE(level2_fixmap_pgt)
495 .fill 506,8,0
496 .quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
497 /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */
498 .fill 5,8,0
499
500NEXT_PAGE(level1_fixmap_pgt)
501 .fill 512,8,0
502
503#undef PMDS
504
505 .data
506 .align 16
507 .globl early_gdt_descr
508early_gdt_descr:
509 .word GDT_ENTRIES*8-1
510early_gdt_descr_base:
511 .quad INIT_PER_CPU_VAR(gdt_page)
512
513ENTRY(phys_base)
514 /* This must match the first entry in level2_kernel_pgt */
515 .quad 0x0000000000000000
516
517#include "../../x86/xen/xen-head.S"
518
519 __PAGE_ALIGNED_BSS
520NEXT_PAGE(empty_zero_page)
521 .skip PAGE_SIZE