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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit
4 *
5 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
6 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
7 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
8 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
9 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
10 */
11
12
13#include <linux/linkage.h>
14#include <linux/threads.h>
15#include <linux/init.h>
16#include <asm/segment.h>
17#include <asm/pgtable.h>
18#include <asm/page.h>
19#include <asm/msr.h>
20#include <asm/cache.h>
21#include <asm/processor-flags.h>
22#include <asm/percpu.h>
23#include <asm/nops.h>
24#include "../entry/calling.h"
25#include <asm/export.h>
26#include <asm/nospec-branch.h>
27
28#ifdef CONFIG_PARAVIRT
29#include <asm/asm-offsets.h>
30#include <asm/paravirt.h>
31#define GET_CR2_INTO(reg) GET_CR2_INTO_RAX ; movq %rax, reg
32#else
33#define GET_CR2_INTO(reg) movq %cr2, reg
34#define INTERRUPT_RETURN iretq
35#endif
36
37/* we are not able to switch in one step to the final KERNEL ADDRESS SPACE
38 * because we need identity-mapped pages.
39 *
40 */
41
42#define l4_index(x) (((x) >> 39) & 511)
43#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
44
45L4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE_L4)
46L4_START_KERNEL = l4_index(__START_KERNEL_map)
47
48L3_START_KERNEL = pud_index(__START_KERNEL_map)
49
50 .text
51 __HEAD
52 .code64
53 .globl startup_64
54startup_64:
55 UNWIND_HINT_EMPTY
56 /*
57 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
58 * and someone has loaded an identity mapped page table
59 * for us. These identity mapped page tables map all of the
60 * kernel pages and possibly all of memory.
61 *
62 * %rsi holds a physical pointer to real_mode_data.
63 *
64 * We come here either directly from a 64bit bootloader, or from
65 * arch/x86/boot/compressed/head_64.S.
66 *
67 * We only come here initially at boot nothing else comes here.
68 *
69 * Since we may be loaded at an address different from what we were
70 * compiled to run at we first fixup the physical addresses in our page
71 * tables and then reload them.
72 */
73
74 /* Set up the stack for verify_cpu(), similar to initial_stack below */
75 leaq (__end_init_task - SIZEOF_PTREGS)(%rip), %rsp
76
77 /* Sanitize CPU configuration */
78 call verify_cpu
79
80 /*
81 * Perform pagetable fixups. Additionally, if SME is active, encrypt
82 * the kernel and retrieve the modifier (SME encryption mask if SME
83 * is active) to be added to the initial pgdir entry that will be
84 * programmed into CR3.
85 */
86 leaq _text(%rip), %rdi
87 pushq %rsi
88 call __startup_64
89 popq %rsi
90
91 /* Form the CR3 value being sure to include the CR3 modifier */
92 addq $(early_top_pgt - __START_KERNEL_map), %rax
93 jmp 1f
94ENTRY(secondary_startup_64)
95 UNWIND_HINT_EMPTY
96 /*
97 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
98 * and someone has loaded a mapped page table.
99 *
100 * %rsi holds a physical pointer to real_mode_data.
101 *
102 * We come here either from startup_64 (using physical addresses)
103 * or from trampoline.S (using virtual addresses).
104 *
105 * Using virtual addresses from trampoline.S removes the need
106 * to have any identity mapped pages in the kernel page table
107 * after the boot processor executes this code.
108 */
109
110 /* Sanitize CPU configuration */
111 call verify_cpu
112
113 /*
114 * Retrieve the modifier (SME encryption mask if SME is active) to be
115 * added to the initial pgdir entry that will be programmed into CR3.
116 */
117 pushq %rsi
118 call __startup_secondary_64
119 popq %rsi
120
121 /* Form the CR3 value being sure to include the CR3 modifier */
122 addq $(init_top_pgt - __START_KERNEL_map), %rax
1231:
124
125 /* Enable PAE mode, PGE and LA57 */
126 movl $(X86_CR4_PAE | X86_CR4_PGE), %ecx
127#ifdef CONFIG_X86_5LEVEL
128 testl $1, __pgtable_l5_enabled(%rip)
129 jz 1f
130 orl $X86_CR4_LA57, %ecx
1311:
132#endif
133 movq %rcx, %cr4
134
135 /* Setup early boot stage 4-/5-level pagetables. */
136 addq phys_base(%rip), %rax
137 movq %rax, %cr3
138
139 /* Ensure I am executing from virtual addresses */
140 movq $1f, %rax
141 ANNOTATE_RETPOLINE_SAFE
142 jmp *%rax
1431:
144 UNWIND_HINT_EMPTY
145
146 /* Check if nx is implemented */
147 movl $0x80000001, %eax
148 cpuid
149 movl %edx,%edi
150
151 /* Setup EFER (Extended Feature Enable Register) */
152 movl $MSR_EFER, %ecx
153 rdmsr
154 btsl $_EFER_SCE, %eax /* Enable System Call */
155 btl $20,%edi /* No Execute supported? */
156 jnc 1f
157 btsl $_EFER_NX, %eax
158 btsq $_PAGE_BIT_NX,early_pmd_flags(%rip)
1591: wrmsr /* Make changes effective */
160
161 /* Setup cr0 */
162 movl $CR0_STATE, %eax
163 /* Make changes effective */
164 movq %rax, %cr0
165
166 /* Setup a boot time stack */
167 movq initial_stack(%rip), %rsp
168
169 /* zero EFLAGS after setting rsp */
170 pushq $0
171 popfq
172
173 /*
174 * We must switch to a new descriptor in kernel space for the GDT
175 * because soon the kernel won't have access anymore to the userspace
176 * addresses where we're currently running on. We have to do that here
177 * because in 32bit we couldn't load a 64bit linear address.
178 */
179 lgdt early_gdt_descr(%rip)
180
181 /* set up data segments */
182 xorl %eax,%eax
183 movl %eax,%ds
184 movl %eax,%ss
185 movl %eax,%es
186
187 /*
188 * We don't really need to load %fs or %gs, but load them anyway
189 * to kill any stale realmode selectors. This allows execution
190 * under VT hardware.
191 */
192 movl %eax,%fs
193 movl %eax,%gs
194
195 /* Set up %gs.
196 *
197 * The base of %gs always points to the bottom of the irqstack
198 * union. If the stack protector canary is enabled, it is
199 * located at %gs:40. Note that, on SMP, the boot cpu uses
200 * init data section till per cpu areas are set up.
201 */
202 movl $MSR_GS_BASE,%ecx
203 movl initial_gs(%rip),%eax
204 movl initial_gs+4(%rip),%edx
205 wrmsr
206
207 /* rsi is pointer to real mode structure with interesting info.
208 pass it to C */
209 movq %rsi, %rdi
210
211.Ljump_to_C_code:
212 /*
213 * Jump to run C code and to be on a real kernel address.
214 * Since we are running on identity-mapped space we have to jump
215 * to the full 64bit address, this is only possible as indirect
216 * jump. In addition we need to ensure %cs is set so we make this
217 * a far return.
218 *
219 * Note: do not change to far jump indirect with 64bit offset.
220 *
221 * AMD does not support far jump indirect with 64bit offset.
222 * AMD64 Architecture Programmer's Manual, Volume 3: states only
223 * JMP FAR mem16:16 FF /5 Far jump indirect,
224 * with the target specified by a far pointer in memory.
225 * JMP FAR mem16:32 FF /5 Far jump indirect,
226 * with the target specified by a far pointer in memory.
227 *
228 * Intel64 does support 64bit offset.
229 * Software Developer Manual Vol 2: states:
230 * FF /5 JMP m16:16 Jump far, absolute indirect,
231 * address given in m16:16
232 * FF /5 JMP m16:32 Jump far, absolute indirect,
233 * address given in m16:32.
234 * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect,
235 * address given in m16:64.
236 */
237 pushq $.Lafter_lret # put return address on stack for unwinder
238 xorq %rbp, %rbp # clear frame pointer
239 movq initial_code(%rip), %rax
240 pushq $__KERNEL_CS # set correct cs
241 pushq %rax # target address in negative space
242 lretq
243.Lafter_lret:
244END(secondary_startup_64)
245
246#include "verify_cpu.S"
247
248#ifdef CONFIG_HOTPLUG_CPU
249/*
250 * Boot CPU0 entry point. It's called from play_dead(). Everything has been set
251 * up already except stack. We just set up stack here. Then call
252 * start_secondary() via .Ljump_to_C_code.
253 */
254ENTRY(start_cpu0)
255 movq initial_stack(%rip), %rsp
256 UNWIND_HINT_EMPTY
257 jmp .Ljump_to_C_code
258ENDPROC(start_cpu0)
259#endif
260
261 /* Both SMP bootup and ACPI suspend change these variables */
262 __REFDATA
263 .balign 8
264 GLOBAL(initial_code)
265 .quad x86_64_start_kernel
266 GLOBAL(initial_gs)
267 .quad INIT_PER_CPU_VAR(irq_stack_union)
268 GLOBAL(initial_stack)
269 /*
270 * The SIZEOF_PTREGS gap is a convention which helps the in-kernel
271 * unwinder reliably detect the end of the stack.
272 */
273 .quad init_thread_union + THREAD_SIZE - SIZEOF_PTREGS
274 __FINITDATA
275
276 __INIT
277ENTRY(early_idt_handler_array)
278 i = 0
279 .rept NUM_EXCEPTION_VECTORS
280 .if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0
281 UNWIND_HINT_IRET_REGS
282 pushq $0 # Dummy error code, to make stack frame uniform
283 .else
284 UNWIND_HINT_IRET_REGS offset=8
285 .endif
286 pushq $i # 72(%rsp) Vector number
287 jmp early_idt_handler_common
288 UNWIND_HINT_IRET_REGS
289 i = i + 1
290 .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc
291 .endr
292 UNWIND_HINT_IRET_REGS offset=16
293END(early_idt_handler_array)
294
295early_idt_handler_common:
296 /*
297 * The stack is the hardware frame, an error code or zero, and the
298 * vector number.
299 */
300 cld
301
302 incl early_recursion_flag(%rip)
303
304 /* The vector number is currently in the pt_regs->di slot. */
305 pushq %rsi /* pt_regs->si */
306 movq 8(%rsp), %rsi /* RSI = vector number */
307 movq %rdi, 8(%rsp) /* pt_regs->di = RDI */
308 pushq %rdx /* pt_regs->dx */
309 pushq %rcx /* pt_regs->cx */
310 pushq %rax /* pt_regs->ax */
311 pushq %r8 /* pt_regs->r8 */
312 pushq %r9 /* pt_regs->r9 */
313 pushq %r10 /* pt_regs->r10 */
314 pushq %r11 /* pt_regs->r11 */
315 pushq %rbx /* pt_regs->bx */
316 pushq %rbp /* pt_regs->bp */
317 pushq %r12 /* pt_regs->r12 */
318 pushq %r13 /* pt_regs->r13 */
319 pushq %r14 /* pt_regs->r14 */
320 pushq %r15 /* pt_regs->r15 */
321 UNWIND_HINT_REGS
322
323 cmpq $14,%rsi /* Page fault? */
324 jnz 10f
325 GET_CR2_INTO(%rdi) /* Can clobber any volatile register if pv */
326 call early_make_pgtable
327 andl %eax,%eax
328 jz 20f /* All good */
329
33010:
331 movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */
332 call early_fixup_exception
333
33420:
335 decl early_recursion_flag(%rip)
336 jmp restore_regs_and_return_to_kernel
337END(early_idt_handler_common)
338
339 __INITDATA
340
341 .balign 4
342GLOBAL(early_recursion_flag)
343 .long 0
344
345#define NEXT_PAGE(name) \
346 .balign PAGE_SIZE; \
347GLOBAL(name)
348
349#ifdef CONFIG_PAGE_TABLE_ISOLATION
350/*
351 * Each PGD needs to be 8k long and 8k aligned. We do not
352 * ever go out to userspace with these, so we do not
353 * strictly *need* the second page, but this allows us to
354 * have a single set_pgd() implementation that does not
355 * need to worry about whether it has 4k or 8k to work
356 * with.
357 *
358 * This ensures PGDs are 8k long:
359 */
360#define PTI_USER_PGD_FILL 512
361/* This ensures they are 8k-aligned: */
362#define NEXT_PGD_PAGE(name) \
363 .balign 2 * PAGE_SIZE; \
364GLOBAL(name)
365#else
366#define NEXT_PGD_PAGE(name) NEXT_PAGE(name)
367#define PTI_USER_PGD_FILL 0
368#endif
369
370/* Automate the creation of 1 to 1 mapping pmd entries */
371#define PMDS(START, PERM, COUNT) \
372 i = 0 ; \
373 .rept (COUNT) ; \
374 .quad (START) + (i << PMD_SHIFT) + (PERM) ; \
375 i = i + 1 ; \
376 .endr
377
378 __INITDATA
379NEXT_PGD_PAGE(early_top_pgt)
380 .fill 512,8,0
381 .fill PTI_USER_PGD_FILL,8,0
382
383NEXT_PAGE(early_dynamic_pgts)
384 .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0
385
386 .data
387
388#if defined(CONFIG_XEN_PV) || defined(CONFIG_XEN_PVH)
389NEXT_PGD_PAGE(init_top_pgt)
390 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
391 .org init_top_pgt + L4_PAGE_OFFSET*8, 0
392 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
393 .org init_top_pgt + L4_START_KERNEL*8, 0
394 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
395 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
396 .fill PTI_USER_PGD_FILL,8,0
397
398NEXT_PAGE(level3_ident_pgt)
399 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
400 .fill 511, 8, 0
401NEXT_PAGE(level2_ident_pgt)
402 /*
403 * Since I easily can, map the first 1G.
404 * Don't set NX because code runs from these pages.
405 *
406 * Note: This sets _PAGE_GLOBAL despite whether
407 * the CPU supports it or it is enabled. But,
408 * the CPU should ignore the bit.
409 */
410 PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
411#else
412NEXT_PGD_PAGE(init_top_pgt)
413 .fill 512,8,0
414 .fill PTI_USER_PGD_FILL,8,0
415#endif
416
417#ifdef CONFIG_X86_5LEVEL
418NEXT_PAGE(level4_kernel_pgt)
419 .fill 511,8,0
420 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
421#endif
422
423NEXT_PAGE(level3_kernel_pgt)
424 .fill L3_START_KERNEL,8,0
425 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
426 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
427 .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
428
429NEXT_PAGE(level2_kernel_pgt)
430 /*
431 * 512 MB kernel mapping. We spend a full page on this pagetable
432 * anyway.
433 *
434 * The kernel code+data+bss must not be bigger than that.
435 *
436 * (NOTE: at +512MB starts the module area, see MODULES_VADDR.
437 * If you want to increase this then increase MODULES_VADDR
438 * too.)
439 *
440 * This table is eventually used by the kernel during normal
441 * runtime. Care must be taken to clear out undesired bits
442 * later, like _PAGE_RW or _PAGE_GLOBAL in some cases.
443 */
444 PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
445 KERNEL_IMAGE_SIZE/PMD_SIZE)
446
447NEXT_PAGE(level2_fixmap_pgt)
448 .fill 506,8,0
449 .quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
450 /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */
451 .fill 5,8,0
452
453NEXT_PAGE(level1_fixmap_pgt)
454 .fill 512,8,0
455
456#undef PMDS
457
458 .data
459 .align 16
460 .globl early_gdt_descr
461early_gdt_descr:
462 .word GDT_ENTRIES*8-1
463early_gdt_descr_base:
464 .quad INIT_PER_CPU_VAR(gdt_page)
465
466ENTRY(phys_base)
467 /* This must match the first entry in level2_kernel_pgt */
468 .quad 0x0000000000000000
469EXPORT_SYMBOL(phys_base)
470
471#include "../../x86/xen/xen-head.S"
472
473 __PAGE_ALIGNED_BSS
474NEXT_PAGE(empty_zero_page)
475 .skip PAGE_SIZE
476EXPORT_SYMBOL(empty_zero_page)
477
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit
4 *
5 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
6 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
7 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
8 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
9 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
10 */
11
12#include <linux/export.h>
13#include <linux/linkage.h>
14#include <linux/threads.h>
15#include <linux/init.h>
16#include <linux/pgtable.h>
17#include <asm/segment.h>
18#include <asm/page.h>
19#include <asm/msr.h>
20#include <asm/cache.h>
21#include <asm/processor-flags.h>
22#include <asm/percpu.h>
23#include <asm/nops.h>
24#include "../entry/calling.h"
25#include <asm/nospec-branch.h>
26#include <asm/apicdef.h>
27#include <asm/fixmap.h>
28#include <asm/smp.h>
29
30/*
31 * We are not able to switch in one step to the final KERNEL ADDRESS SPACE
32 * because we need identity-mapped pages.
33 */
34#define l4_index(x) (((x) >> 39) & 511)
35#define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
36
37L4_PAGE_OFFSET = l4_index(__PAGE_OFFSET_BASE_L4)
38L4_START_KERNEL = l4_index(__START_KERNEL_map)
39
40L3_START_KERNEL = pud_index(__START_KERNEL_map)
41
42 .text
43 __HEAD
44 .code64
45SYM_CODE_START_NOALIGN(startup_64)
46 UNWIND_HINT_END_OF_STACK
47 /*
48 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
49 * and someone has loaded an identity mapped page table
50 * for us. These identity mapped page tables map all of the
51 * kernel pages and possibly all of memory.
52 *
53 * %RSI holds the physical address of the boot_params structure
54 * provided by the bootloader. Preserve it in %R15 so C function calls
55 * will not clobber it.
56 *
57 * We come here either directly from a 64bit bootloader, or from
58 * arch/x86/boot/compressed/head_64.S.
59 *
60 * We only come here initially at boot nothing else comes here.
61 *
62 * Since we may be loaded at an address different from what we were
63 * compiled to run at we first fixup the physical addresses in our page
64 * tables and then reload them.
65 */
66 mov %rsi, %r15
67
68 /* Set up the stack for verify_cpu() */
69 leaq (__end_init_task - PTREGS_SIZE)(%rip), %rsp
70
71 leaq _text(%rip), %rdi
72
73 /* Setup GSBASE to allow stack canary access for C code */
74 movl $MSR_GS_BASE, %ecx
75 leaq INIT_PER_CPU_VAR(fixed_percpu_data)(%rip), %rdx
76 movl %edx, %eax
77 shrq $32, %rdx
78 wrmsr
79
80 call startup_64_setup_env
81
82 /* Now switch to __KERNEL_CS so IRET works reliably */
83 pushq $__KERNEL_CS
84 leaq .Lon_kernel_cs(%rip), %rax
85 pushq %rax
86 lretq
87
88.Lon_kernel_cs:
89 UNWIND_HINT_END_OF_STACK
90
91#ifdef CONFIG_AMD_MEM_ENCRYPT
92 /*
93 * Activate SEV/SME memory encryption if supported/enabled. This needs to
94 * be done now, since this also includes setup of the SEV-SNP CPUID table,
95 * which needs to be done before any CPUID instructions are executed in
96 * subsequent code. Pass the boot_params pointer as the first argument.
97 */
98 movq %r15, %rdi
99 call sme_enable
100#endif
101
102 /* Sanitize CPU configuration */
103 call verify_cpu
104
105 /*
106 * Perform pagetable fixups. Additionally, if SME is active, encrypt
107 * the kernel and retrieve the modifier (SME encryption mask if SME
108 * is active) to be added to the initial pgdir entry that will be
109 * programmed into CR3.
110 */
111 leaq _text(%rip), %rdi
112 movq %r15, %rsi
113 call __startup_64
114
115 /* Form the CR3 value being sure to include the CR3 modifier */
116 addq $(early_top_pgt - __START_KERNEL_map), %rax
117
118#ifdef CONFIG_AMD_MEM_ENCRYPT
119 mov %rax, %rdi
120 mov %rax, %r14
121
122 addq phys_base(%rip), %rdi
123
124 /*
125 * For SEV guests: Verify that the C-bit is correct. A malicious
126 * hypervisor could lie about the C-bit position to perform a ROP
127 * attack on the guest by writing to the unencrypted stack and wait for
128 * the next RET instruction.
129 */
130 call sev_verify_cbit
131
132 /*
133 * Restore CR3 value without the phys_base which will be added
134 * below, before writing %cr3.
135 */
136 mov %r14, %rax
137#endif
138
139 jmp 1f
140SYM_CODE_END(startup_64)
141
142SYM_CODE_START(secondary_startup_64)
143 UNWIND_HINT_END_OF_STACK
144 ANNOTATE_NOENDBR
145 /*
146 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
147 * and someone has loaded a mapped page table.
148 *
149 * We come here either from startup_64 (using physical addresses)
150 * or from trampoline.S (using virtual addresses).
151 *
152 * Using virtual addresses from trampoline.S removes the need
153 * to have any identity mapped pages in the kernel page table
154 * after the boot processor executes this code.
155 */
156
157 /* Sanitize CPU configuration */
158 call verify_cpu
159
160 /*
161 * The secondary_startup_64_no_verify entry point is only used by
162 * SEV-ES guests. In those guests the call to verify_cpu() would cause
163 * #VC exceptions which can not be handled at this stage of secondary
164 * CPU bringup.
165 *
166 * All non SEV-ES systems, especially Intel systems, need to execute
167 * verify_cpu() above to make sure NX is enabled.
168 */
169SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL)
170 UNWIND_HINT_END_OF_STACK
171 ANNOTATE_NOENDBR
172
173 /* Clear %R15 which holds the boot_params pointer on the boot CPU */
174 xorq %r15, %r15
175
176 /*
177 * Retrieve the modifier (SME encryption mask if SME is active) to be
178 * added to the initial pgdir entry that will be programmed into CR3.
179 */
180#ifdef CONFIG_AMD_MEM_ENCRYPT
181 movq sme_me_mask, %rax
182#else
183 xorq %rax, %rax
184#endif
185
186 /* Form the CR3 value being sure to include the CR3 modifier */
187 addq $(init_top_pgt - __START_KERNEL_map), %rax
1881:
189
190#ifdef CONFIG_X86_MCE
191 /*
192 * Preserve CR4.MCE if the kernel will enable #MC support.
193 * Clearing MCE may fault in some environments (that also force #MC
194 * support). Any machine check that occurs before #MC support is fully
195 * configured will crash the system regardless of the CR4.MCE value set
196 * here.
197 */
198 movq %cr4, %rcx
199 andl $X86_CR4_MCE, %ecx
200#else
201 movl $0, %ecx
202#endif
203
204 /* Enable PAE mode, PSE, PGE and LA57 */
205 orl $(X86_CR4_PAE | X86_CR4_PSE | X86_CR4_PGE), %ecx
206#ifdef CONFIG_X86_5LEVEL
207 testb $1, __pgtable_l5_enabled(%rip)
208 jz 1f
209 orl $X86_CR4_LA57, %ecx
2101:
211#endif
212 movq %rcx, %cr4
213
214 /* Setup early boot stage 4-/5-level pagetables. */
215 addq phys_base(%rip), %rax
216
217 /*
218 * Switch to new page-table
219 *
220 * For the boot CPU this switches to early_top_pgt which still has the
221 * identity mappings present. The secondary CPUs will switch to the
222 * init_top_pgt here, away from the trampoline_pgd and unmap the
223 * identity mapped ranges.
224 */
225 movq %rax, %cr3
226
227 /*
228 * Do a global TLB flush after the CR3 switch to make sure the TLB
229 * entries from the identity mapping are flushed.
230 */
231 movq %cr4, %rcx
232 movq %rcx, %rax
233 xorq $X86_CR4_PGE, %rcx
234 movq %rcx, %cr4
235 movq %rax, %cr4
236
237 /* Ensure I am executing from virtual addresses */
238 movq $1f, %rax
239 ANNOTATE_RETPOLINE_SAFE
240 jmp *%rax
2411:
242 UNWIND_HINT_END_OF_STACK
243 ANNOTATE_NOENDBR // above
244
245#ifdef CONFIG_SMP
246 /*
247 * For parallel boot, the APIC ID is read from the APIC, and then
248 * used to look up the CPU number. For booting a single CPU, the
249 * CPU number is encoded in smpboot_control.
250 *
251 * Bit 31 STARTUP_READ_APICID (Read APICID from APIC)
252 * Bit 0-23 CPU# if STARTUP_xx flags are not set
253 */
254 movl smpboot_control(%rip), %ecx
255 testl $STARTUP_READ_APICID, %ecx
256 jnz .Lread_apicid
257 /*
258 * No control bit set, single CPU bringup. CPU number is provided
259 * in bit 0-23. This is also the boot CPU case (CPU number 0).
260 */
261 andl $(~STARTUP_PARALLEL_MASK), %ecx
262 jmp .Lsetup_cpu
263
264.Lread_apicid:
265 /* Check whether X2APIC mode is already enabled */
266 mov $MSR_IA32_APICBASE, %ecx
267 rdmsr
268 testl $X2APIC_ENABLE, %eax
269 jnz .Lread_apicid_msr
270
271#ifdef CONFIG_X86_X2APIC
272 /*
273 * If system is in X2APIC mode then MMIO base might not be
274 * mapped causing the MMIO read below to fault. Faults can't
275 * be handled at that point.
276 */
277 cmpl $0, x2apic_mode(%rip)
278 jz .Lread_apicid_mmio
279
280 /* Force the AP into X2APIC mode. */
281 orl $X2APIC_ENABLE, %eax
282 wrmsr
283 jmp .Lread_apicid_msr
284#endif
285
286.Lread_apicid_mmio:
287 /* Read the APIC ID from the fix-mapped MMIO space. */
288 movq apic_mmio_base(%rip), %rcx
289 addq $APIC_ID, %rcx
290 movl (%rcx), %eax
291 shr $24, %eax
292 jmp .Llookup_AP
293
294.Lread_apicid_msr:
295 mov $APIC_X2APIC_ID_MSR, %ecx
296 rdmsr
297
298.Llookup_AP:
299 /* EAX contains the APIC ID of the current CPU */
300 xorq %rcx, %rcx
301 leaq cpuid_to_apicid(%rip), %rbx
302
303.Lfind_cpunr:
304 cmpl (%rbx,%rcx,4), %eax
305 jz .Lsetup_cpu
306 inc %ecx
307#ifdef CONFIG_FORCE_NR_CPUS
308 cmpl $NR_CPUS, %ecx
309#else
310 cmpl nr_cpu_ids(%rip), %ecx
311#endif
312 jb .Lfind_cpunr
313
314 /* APIC ID not found in the table. Drop the trampoline lock and bail. */
315 movq trampoline_lock(%rip), %rax
316 movl $0, (%rax)
317
3181: cli
319 hlt
320 jmp 1b
321
322.Lsetup_cpu:
323 /* Get the per cpu offset for the given CPU# which is in ECX */
324 movq __per_cpu_offset(,%rcx,8), %rdx
325#else
326 xorl %edx, %edx /* zero-extended to clear all of RDX */
327#endif /* CONFIG_SMP */
328
329 /*
330 * Setup a boot time stack - Any secondary CPU will have lost its stack
331 * by now because the cr3-switch above unmaps the real-mode stack.
332 *
333 * RDX contains the per-cpu offset
334 */
335 movq pcpu_hot + X86_current_task(%rdx), %rax
336 movq TASK_threadsp(%rax), %rsp
337
338 /*
339 * Now that this CPU is running on its own stack, drop the realmode
340 * protection. For the boot CPU the pointer is NULL!
341 */
342 movq trampoline_lock(%rip), %rax
343 testq %rax, %rax
344 jz .Lsetup_gdt
345 movl $0, (%rax)
346
347.Lsetup_gdt:
348 /*
349 * We must switch to a new descriptor in kernel space for the GDT
350 * because soon the kernel won't have access anymore to the userspace
351 * addresses where we're currently running on. We have to do that here
352 * because in 32bit we couldn't load a 64bit linear address.
353 */
354 subq $16, %rsp
355 movw $(GDT_SIZE-1), (%rsp)
356 leaq gdt_page(%rdx), %rax
357 movq %rax, 2(%rsp)
358 lgdt (%rsp)
359 addq $16, %rsp
360
361 /* set up data segments */
362 xorl %eax,%eax
363 movl %eax,%ds
364 movl %eax,%ss
365 movl %eax,%es
366
367 /*
368 * We don't really need to load %fs or %gs, but load them anyway
369 * to kill any stale realmode selectors. This allows execution
370 * under VT hardware.
371 */
372 movl %eax,%fs
373 movl %eax,%gs
374
375 /* Set up %gs.
376 *
377 * The base of %gs always points to fixed_percpu_data. If the
378 * stack protector canary is enabled, it is located at %gs:40.
379 * Note that, on SMP, the boot cpu uses init data section until
380 * the per cpu areas are set up.
381 */
382 movl $MSR_GS_BASE,%ecx
383#ifndef CONFIG_SMP
384 leaq INIT_PER_CPU_VAR(fixed_percpu_data)(%rip), %rdx
385#endif
386 movl %edx, %eax
387 shrq $32, %rdx
388 wrmsr
389
390 /* Setup and Load IDT */
391 call early_setup_idt
392
393 /* Check if nx is implemented */
394 movl $0x80000001, %eax
395 cpuid
396 movl %edx,%edi
397
398 /* Setup EFER (Extended Feature Enable Register) */
399 movl $MSR_EFER, %ecx
400 rdmsr
401 /*
402 * Preserve current value of EFER for comparison and to skip
403 * EFER writes if no change was made (for TDX guest)
404 */
405 movl %eax, %edx
406 btsl $_EFER_SCE, %eax /* Enable System Call */
407 btl $20,%edi /* No Execute supported? */
408 jnc 1f
409 btsl $_EFER_NX, %eax
410 btsq $_PAGE_BIT_NX,early_pmd_flags(%rip)
411
412 /* Avoid writing EFER if no change was made (for TDX guest) */
4131: cmpl %edx, %eax
414 je 1f
415 xor %edx, %edx
416 wrmsr /* Make changes effective */
4171:
418 /* Setup cr0 */
419 movl $CR0_STATE, %eax
420 /* Make changes effective */
421 movq %rax, %cr0
422
423 /* zero EFLAGS after setting rsp */
424 pushq $0
425 popfq
426
427 /* Pass the boot_params pointer as first argument */
428 movq %r15, %rdi
429
430.Ljump_to_C_code:
431 /*
432 * Jump to run C code and to be on a real kernel address.
433 * Since we are running on identity-mapped space we have to jump
434 * to the full 64bit address, this is only possible as indirect
435 * jump. In addition we need to ensure %cs is set so we make this
436 * a far return.
437 *
438 * Note: do not change to far jump indirect with 64bit offset.
439 *
440 * AMD does not support far jump indirect with 64bit offset.
441 * AMD64 Architecture Programmer's Manual, Volume 3: states only
442 * JMP FAR mem16:16 FF /5 Far jump indirect,
443 * with the target specified by a far pointer in memory.
444 * JMP FAR mem16:32 FF /5 Far jump indirect,
445 * with the target specified by a far pointer in memory.
446 *
447 * Intel64 does support 64bit offset.
448 * Software Developer Manual Vol 2: states:
449 * FF /5 JMP m16:16 Jump far, absolute indirect,
450 * address given in m16:16
451 * FF /5 JMP m16:32 Jump far, absolute indirect,
452 * address given in m16:32.
453 * REX.W + FF /5 JMP m16:64 Jump far, absolute indirect,
454 * address given in m16:64.
455 */
456 pushq $.Lafter_lret # put return address on stack for unwinder
457 xorl %ebp, %ebp # clear frame pointer
458 movq initial_code(%rip), %rax
459 pushq $__KERNEL_CS # set correct cs
460 pushq %rax # target address in negative space
461 lretq
462.Lafter_lret:
463 ANNOTATE_NOENDBR
464SYM_CODE_END(secondary_startup_64)
465
466#include "verify_cpu.S"
467#include "sev_verify_cbit.S"
468
469#if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_AMD_MEM_ENCRYPT)
470/*
471 * Entry point for soft restart of a CPU. Invoked from xxx_play_dead() for
472 * restarting the boot CPU or for restarting SEV guest CPUs after CPU hot
473 * unplug. Everything is set up already except the stack.
474 */
475SYM_CODE_START(soft_restart_cpu)
476 ANNOTATE_NOENDBR
477 UNWIND_HINT_END_OF_STACK
478
479 /* Find the idle task stack */
480 movq PER_CPU_VAR(pcpu_hot) + X86_current_task, %rcx
481 movq TASK_threadsp(%rcx), %rsp
482
483 jmp .Ljump_to_C_code
484SYM_CODE_END(soft_restart_cpu)
485#endif
486
487#ifdef CONFIG_AMD_MEM_ENCRYPT
488/*
489 * VC Exception handler used during early boot when running on kernel
490 * addresses, but before the switch to the idt_table can be made.
491 * The early_idt_handler_array can't be used here because it calls into a lot
492 * of __init code and this handler is also used during CPU offlining/onlining.
493 * Therefore this handler ends up in the .text section so that it stays around
494 * when .init.text is freed.
495 */
496SYM_CODE_START_NOALIGN(vc_boot_ghcb)
497 UNWIND_HINT_IRET_REGS offset=8
498 ENDBR
499
500 /* Build pt_regs */
501 PUSH_AND_CLEAR_REGS
502
503 /* Call C handler */
504 movq %rsp, %rdi
505 movq ORIG_RAX(%rsp), %rsi
506 movq initial_vc_handler(%rip), %rax
507 ANNOTATE_RETPOLINE_SAFE
508 call *%rax
509
510 /* Unwind pt_regs */
511 POP_REGS
512
513 /* Remove Error Code */
514 addq $8, %rsp
515
516 iretq
517SYM_CODE_END(vc_boot_ghcb)
518#endif
519
520 /* Both SMP bootup and ACPI suspend change these variables */
521 __REFDATA
522 .balign 8
523SYM_DATA(initial_code, .quad x86_64_start_kernel)
524#ifdef CONFIG_AMD_MEM_ENCRYPT
525SYM_DATA(initial_vc_handler, .quad handle_vc_boot_ghcb)
526#endif
527
528SYM_DATA(trampoline_lock, .quad 0);
529 __FINITDATA
530
531 __INIT
532SYM_CODE_START(early_idt_handler_array)
533 i = 0
534 .rept NUM_EXCEPTION_VECTORS
535 .if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0
536 UNWIND_HINT_IRET_REGS
537 ENDBR
538 pushq $0 # Dummy error code, to make stack frame uniform
539 .else
540 UNWIND_HINT_IRET_REGS offset=8
541 ENDBR
542 .endif
543 pushq $i # 72(%rsp) Vector number
544 jmp early_idt_handler_common
545 UNWIND_HINT_IRET_REGS
546 i = i + 1
547 .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc
548 .endr
549SYM_CODE_END(early_idt_handler_array)
550 ANNOTATE_NOENDBR // early_idt_handler_array[NUM_EXCEPTION_VECTORS]
551
552SYM_CODE_START_LOCAL(early_idt_handler_common)
553 UNWIND_HINT_IRET_REGS offset=16
554 /*
555 * The stack is the hardware frame, an error code or zero, and the
556 * vector number.
557 */
558 cld
559
560 incl early_recursion_flag(%rip)
561
562 /* The vector number is currently in the pt_regs->di slot. */
563 pushq %rsi /* pt_regs->si */
564 movq 8(%rsp), %rsi /* RSI = vector number */
565 movq %rdi, 8(%rsp) /* pt_regs->di = RDI */
566 pushq %rdx /* pt_regs->dx */
567 pushq %rcx /* pt_regs->cx */
568 pushq %rax /* pt_regs->ax */
569 pushq %r8 /* pt_regs->r8 */
570 pushq %r9 /* pt_regs->r9 */
571 pushq %r10 /* pt_regs->r10 */
572 pushq %r11 /* pt_regs->r11 */
573 pushq %rbx /* pt_regs->bx */
574 pushq %rbp /* pt_regs->bp */
575 pushq %r12 /* pt_regs->r12 */
576 pushq %r13 /* pt_regs->r13 */
577 pushq %r14 /* pt_regs->r14 */
578 pushq %r15 /* pt_regs->r15 */
579 UNWIND_HINT_REGS
580
581 movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */
582 call do_early_exception
583
584 decl early_recursion_flag(%rip)
585 jmp restore_regs_and_return_to_kernel
586SYM_CODE_END(early_idt_handler_common)
587
588#ifdef CONFIG_AMD_MEM_ENCRYPT
589/*
590 * VC Exception handler used during very early boot. The
591 * early_idt_handler_array can't be used because it returns via the
592 * paravirtualized INTERRUPT_RETURN and pv-ops don't work that early.
593 *
594 * XXX it does, fix this.
595 *
596 * This handler will end up in the .init.text section and not be
597 * available to boot secondary CPUs.
598 */
599SYM_CODE_START_NOALIGN(vc_no_ghcb)
600 UNWIND_HINT_IRET_REGS offset=8
601 ENDBR
602
603 /* Build pt_regs */
604 PUSH_AND_CLEAR_REGS
605
606 /* Call C handler */
607 movq %rsp, %rdi
608 movq ORIG_RAX(%rsp), %rsi
609 call do_vc_no_ghcb
610
611 /* Unwind pt_regs */
612 POP_REGS
613
614 /* Remove Error Code */
615 addq $8, %rsp
616
617 /* Pure iret required here - don't use INTERRUPT_RETURN */
618 iretq
619SYM_CODE_END(vc_no_ghcb)
620#endif
621
622#define SYM_DATA_START_PAGE_ALIGNED(name) \
623 SYM_START(name, SYM_L_GLOBAL, .balign PAGE_SIZE)
624
625#ifdef CONFIG_PAGE_TABLE_ISOLATION
626/*
627 * Each PGD needs to be 8k long and 8k aligned. We do not
628 * ever go out to userspace with these, so we do not
629 * strictly *need* the second page, but this allows us to
630 * have a single set_pgd() implementation that does not
631 * need to worry about whether it has 4k or 8k to work
632 * with.
633 *
634 * This ensures PGDs are 8k long:
635 */
636#define PTI_USER_PGD_FILL 512
637/* This ensures they are 8k-aligned: */
638#define SYM_DATA_START_PTI_ALIGNED(name) \
639 SYM_START(name, SYM_L_GLOBAL, .balign 2 * PAGE_SIZE)
640#else
641#define SYM_DATA_START_PTI_ALIGNED(name) \
642 SYM_DATA_START_PAGE_ALIGNED(name)
643#define PTI_USER_PGD_FILL 0
644#endif
645
646/* Automate the creation of 1 to 1 mapping pmd entries */
647#define PMDS(START, PERM, COUNT) \
648 i = 0 ; \
649 .rept (COUNT) ; \
650 .quad (START) + (i << PMD_SHIFT) + (PERM) ; \
651 i = i + 1 ; \
652 .endr
653
654 __INITDATA
655 .balign 4
656
657SYM_DATA_START_PTI_ALIGNED(early_top_pgt)
658 .fill 512,8,0
659 .fill PTI_USER_PGD_FILL,8,0
660SYM_DATA_END(early_top_pgt)
661
662SYM_DATA_START_PAGE_ALIGNED(early_dynamic_pgts)
663 .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0
664SYM_DATA_END(early_dynamic_pgts)
665
666SYM_DATA(early_recursion_flag, .long 0)
667
668 .data
669
670#if defined(CONFIG_XEN_PV) || defined(CONFIG_PVH)
671SYM_DATA_START_PTI_ALIGNED(init_top_pgt)
672 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
673 .org init_top_pgt + L4_PAGE_OFFSET*8, 0
674 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
675 .org init_top_pgt + L4_START_KERNEL*8, 0
676 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
677 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
678 .fill PTI_USER_PGD_FILL,8,0
679SYM_DATA_END(init_top_pgt)
680
681SYM_DATA_START_PAGE_ALIGNED(level3_ident_pgt)
682 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
683 .fill 511, 8, 0
684SYM_DATA_END(level3_ident_pgt)
685SYM_DATA_START_PAGE_ALIGNED(level2_ident_pgt)
686 /*
687 * Since I easily can, map the first 1G.
688 * Don't set NX because code runs from these pages.
689 *
690 * Note: This sets _PAGE_GLOBAL despite whether
691 * the CPU supports it or it is enabled. But,
692 * the CPU should ignore the bit.
693 */
694 PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
695SYM_DATA_END(level2_ident_pgt)
696#else
697SYM_DATA_START_PTI_ALIGNED(init_top_pgt)
698 .fill 512,8,0
699 .fill PTI_USER_PGD_FILL,8,0
700SYM_DATA_END(init_top_pgt)
701#endif
702
703#ifdef CONFIG_X86_5LEVEL
704SYM_DATA_START_PAGE_ALIGNED(level4_kernel_pgt)
705 .fill 511,8,0
706 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
707SYM_DATA_END(level4_kernel_pgt)
708#endif
709
710SYM_DATA_START_PAGE_ALIGNED(level3_kernel_pgt)
711 .fill L3_START_KERNEL,8,0
712 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
713 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC
714 .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC
715SYM_DATA_END(level3_kernel_pgt)
716
717SYM_DATA_START_PAGE_ALIGNED(level2_kernel_pgt)
718 /*
719 * Kernel high mapping.
720 *
721 * The kernel code+data+bss must be located below KERNEL_IMAGE_SIZE in
722 * virtual address space, which is 1 GiB if RANDOMIZE_BASE is enabled,
723 * 512 MiB otherwise.
724 *
725 * (NOTE: after that starts the module area, see MODULES_VADDR.)
726 *
727 * This table is eventually used by the kernel during normal runtime.
728 * Care must be taken to clear out undesired bits later, like _PAGE_RW
729 * or _PAGE_GLOBAL in some cases.
730 */
731 PMDS(0, __PAGE_KERNEL_LARGE_EXEC, KERNEL_IMAGE_SIZE/PMD_SIZE)
732SYM_DATA_END(level2_kernel_pgt)
733
734SYM_DATA_START_PAGE_ALIGNED(level2_fixmap_pgt)
735 .fill (512 - 4 - FIXMAP_PMD_NUM),8,0
736 pgtno = 0
737 .rept (FIXMAP_PMD_NUM)
738 .quad level1_fixmap_pgt + (pgtno << PAGE_SHIFT) - __START_KERNEL_map \
739 + _PAGE_TABLE_NOENC;
740 pgtno = pgtno + 1
741 .endr
742 /* 6 MB reserved space + a 2MB hole */
743 .fill 4,8,0
744SYM_DATA_END(level2_fixmap_pgt)
745
746SYM_DATA_START_PAGE_ALIGNED(level1_fixmap_pgt)
747 .rept (FIXMAP_PMD_NUM)
748 .fill 512,8,0
749 .endr
750SYM_DATA_END(level1_fixmap_pgt)
751
752#undef PMDS
753
754 .data
755 .align 16
756
757SYM_DATA(smpboot_control, .long 0)
758
759 .align 16
760/* This must match the first entry in level2_kernel_pgt */
761SYM_DATA(phys_base, .quad 0x0)
762EXPORT_SYMBOL(phys_base)
763
764#include "../../x86/xen/xen-head.S"
765
766 __PAGE_ALIGNED_BSS
767SYM_DATA_START_PAGE_ALIGNED(empty_zero_page)
768 .skip PAGE_SIZE
769SYM_DATA_END(empty_zero_page)
770EXPORT_SYMBOL(empty_zero_page)
771