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1// SPDX-License-Identifier: GPL-2.0
2#include <linux/kernel.h>
3
4#include <linux/string.h>
5#include <linux/bitops.h>
6#include <linux/smp.h>
7#include <linux/sched.h>
8#include <linux/sched/clock.h>
9#include <linux/thread_info.h>
10#include <linux/init.h>
11#include <linux/uaccess.h>
12
13#include <asm/cpufeature.h>
14#include <asm/pgtable.h>
15#include <asm/msr.h>
16#include <asm/bugs.h>
17#include <asm/cpu.h>
18#include <asm/intel-family.h>
19#include <asm/microcode_intel.h>
20#include <asm/hwcap2.h>
21#include <asm/elf.h>
22
23#ifdef CONFIG_X86_64
24#include <linux/topology.h>
25#endif
26
27#include "cpu.h"
28
29#ifdef CONFIG_X86_LOCAL_APIC
30#include <asm/mpspec.h>
31#include <asm/apic.h>
32#endif
33
34/*
35 * Just in case our CPU detection goes bad, or you have a weird system,
36 * allow a way to override the automatic disabling of MPX.
37 */
38static int forcempx;
39
40static int __init forcempx_setup(char *__unused)
41{
42 forcempx = 1;
43
44 return 1;
45}
46__setup("intel-skd-046-workaround=disable", forcempx_setup);
47
48void check_mpx_erratum(struct cpuinfo_x86 *c)
49{
50 if (forcempx)
51 return;
52 /*
53 * Turn off the MPX feature on CPUs where SMEP is not
54 * available or disabled.
55 *
56 * Works around Intel Erratum SKD046: "Branch Instructions
57 * May Initialize MPX Bound Registers Incorrectly".
58 *
59 * This might falsely disable MPX on systems without
60 * SMEP, like Atom processors without SMEP. But there
61 * is no such hardware known at the moment.
62 */
63 if (cpu_has(c, X86_FEATURE_MPX) && !cpu_has(c, X86_FEATURE_SMEP)) {
64 setup_clear_cpu_cap(X86_FEATURE_MPX);
65 pr_warn("x86/mpx: Disabling MPX since SMEP not present\n");
66 }
67}
68
69static bool ring3mwait_disabled __read_mostly;
70
71static int __init ring3mwait_disable(char *__unused)
72{
73 ring3mwait_disabled = true;
74 return 0;
75}
76__setup("ring3mwait=disable", ring3mwait_disable);
77
78static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
79{
80 /*
81 * Ring 3 MONITOR/MWAIT feature cannot be detected without
82 * cpu model and family comparison.
83 */
84 if (c->x86 != 6)
85 return;
86 switch (c->x86_model) {
87 case INTEL_FAM6_XEON_PHI_KNL:
88 case INTEL_FAM6_XEON_PHI_KNM:
89 break;
90 default:
91 return;
92 }
93
94 if (ring3mwait_disabled)
95 return;
96
97 set_cpu_cap(c, X86_FEATURE_RING3MWAIT);
98 this_cpu_or(msr_misc_features_shadow,
99 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT);
100
101 if (c == &boot_cpu_data)
102 ELF_HWCAP2 |= HWCAP2_RING3MWAIT;
103}
104
105/*
106 * Early microcode releases for the Spectre v2 mitigation were broken.
107 * Information taken from;
108 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
109 * - https://kb.vmware.com/s/article/52345
110 * - Microcode revisions observed in the wild
111 * - Release note from 20180108 microcode release
112 */
113struct sku_microcode {
114 u8 model;
115 u8 stepping;
116 u32 microcode;
117};
118static const struct sku_microcode spectre_bad_microcodes[] = {
119 { INTEL_FAM6_KABYLAKE_DESKTOP, 0x0B, 0x80 },
120 { INTEL_FAM6_KABYLAKE_DESKTOP, 0x0A, 0x80 },
121 { INTEL_FAM6_KABYLAKE_DESKTOP, 0x09, 0x80 },
122 { INTEL_FAM6_KABYLAKE_MOBILE, 0x0A, 0x80 },
123 { INTEL_FAM6_KABYLAKE_MOBILE, 0x09, 0x80 },
124 { INTEL_FAM6_SKYLAKE_X, 0x03, 0x0100013e },
125 { INTEL_FAM6_SKYLAKE_X, 0x04, 0x0200003c },
126 { INTEL_FAM6_BROADWELL_CORE, 0x04, 0x28 },
127 { INTEL_FAM6_BROADWELL_GT3E, 0x01, 0x1b },
128 { INTEL_FAM6_BROADWELL_XEON_D, 0x02, 0x14 },
129 { INTEL_FAM6_BROADWELL_XEON_D, 0x03, 0x07000011 },
130 { INTEL_FAM6_BROADWELL_X, 0x01, 0x0b000025 },
131 { INTEL_FAM6_HASWELL_ULT, 0x01, 0x21 },
132 { INTEL_FAM6_HASWELL_GT3E, 0x01, 0x18 },
133 { INTEL_FAM6_HASWELL_CORE, 0x03, 0x23 },
134 { INTEL_FAM6_HASWELL_X, 0x02, 0x3b },
135 { INTEL_FAM6_HASWELL_X, 0x04, 0x10 },
136 { INTEL_FAM6_IVYBRIDGE_X, 0x04, 0x42a },
137 /* Observed in the wild */
138 { INTEL_FAM6_SANDYBRIDGE_X, 0x06, 0x61b },
139 { INTEL_FAM6_SANDYBRIDGE_X, 0x07, 0x712 },
140};
141
142static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
143{
144 int i;
145
146 /*
147 * We know that the hypervisor lie to us on the microcode version so
148 * we may as well hope that it is running the correct version.
149 */
150 if (cpu_has(c, X86_FEATURE_HYPERVISOR))
151 return false;
152
153 for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {
154 if (c->x86_model == spectre_bad_microcodes[i].model &&
155 c->x86_stepping == spectre_bad_microcodes[i].stepping)
156 return (c->microcode <= spectre_bad_microcodes[i].microcode);
157 }
158 return false;
159}
160
161static void early_init_intel(struct cpuinfo_x86 *c)
162{
163 u64 misc_enable;
164
165 /* Unmask CPUID levels if masked: */
166 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
167 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
168 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
169 c->cpuid_level = cpuid_eax(0);
170 get_cpu_cap(c);
171 }
172 }
173
174 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
175 (c->x86 == 0x6 && c->x86_model >= 0x0e))
176 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
177
178 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
179 c->microcode = intel_get_microcode_revision();
180
181 /* Now if any of them are set, check the blacklist and clear the lot */
182 if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) ||
183 cpu_has(c, X86_FEATURE_INTEL_STIBP) ||
184 cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) ||
185 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) {
186 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n");
187 setup_clear_cpu_cap(X86_FEATURE_IBRS);
188 setup_clear_cpu_cap(X86_FEATURE_IBPB);
189 setup_clear_cpu_cap(X86_FEATURE_STIBP);
190 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL);
191 setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL);
192 setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP);
193 setup_clear_cpu_cap(X86_FEATURE_SSBD);
194 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL_SSBD);
195 }
196
197 /*
198 * Atom erratum AAE44/AAF40/AAG38/AAH41:
199 *
200 * A race condition between speculative fetches and invalidating
201 * a large page. This is worked around in microcode, but we
202 * need the microcode to have already been loaded... so if it is
203 * not, recommend a BIOS update and disable large pages.
204 */
205 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_stepping <= 2 &&
206 c->microcode < 0x20e) {
207 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
208 clear_cpu_cap(c, X86_FEATURE_PSE);
209 }
210
211#ifdef CONFIG_X86_64
212 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
213#else
214 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
215 if (c->x86 == 15 && c->x86_cache_alignment == 64)
216 c->x86_cache_alignment = 128;
217#endif
218
219 /* CPUID workaround for 0F33/0F34 CPU */
220 if (c->x86 == 0xF && c->x86_model == 0x3
221 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))
222 c->x86_phys_bits = 36;
223
224 /*
225 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
226 * with P/T states and does not stop in deep C-states.
227 *
228 * It is also reliable across cores and sockets. (but not across
229 * cabinets - we turn it off in that case explicitly.)
230 */
231 if (c->x86_power & (1 << 8)) {
232 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
233 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
234 }
235
236 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
237 if (c->x86 == 6) {
238 switch (c->x86_model) {
239 case 0x27: /* Penwell */
240 case 0x35: /* Cloverview */
241 case 0x4a: /* Merrifield */
242 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
243 break;
244 default:
245 break;
246 }
247 }
248
249 /*
250 * There is a known erratum on Pentium III and Core Solo
251 * and Core Duo CPUs.
252 * " Page with PAT set to WC while associated MTRR is UC
253 * may consolidate to UC "
254 * Because of this erratum, it is better to stick with
255 * setting WC in MTRR rather than using PAT on these CPUs.
256 *
257 * Enable PAT WC only on P4, Core 2 or later CPUs.
258 */
259 if (c->x86 == 6 && c->x86_model < 15)
260 clear_cpu_cap(c, X86_FEATURE_PAT);
261
262 /*
263 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
264 * clear the fast string and enhanced fast string CPU capabilities.
265 */
266 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
267 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
268 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
269 pr_info("Disabled fast string operations\n");
270 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
271 setup_clear_cpu_cap(X86_FEATURE_ERMS);
272 }
273 }
274
275 /*
276 * Intel Quark Core DevMan_001.pdf section 6.4.11
277 * "The operating system also is required to invalidate (i.e., flush)
278 * the TLB when any changes are made to any of the page table entries.
279 * The operating system must reload CR3 to cause the TLB to be flushed"
280 *
281 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h
282 * should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE
283 * to be modified.
284 */
285 if (c->x86 == 5 && c->x86_model == 9) {
286 pr_info("Disabling PGE capability bit\n");
287 setup_clear_cpu_cap(X86_FEATURE_PGE);
288 }
289
290 if (c->cpuid_level >= 0x00000001) {
291 u32 eax, ebx, ecx, edx;
292
293 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
294 /*
295 * If HTT (EDX[28]) is set EBX[16:23] contain the number of
296 * apicids which are reserved per package. Store the resulting
297 * shift value for the package management code.
298 */
299 if (edx & (1U << 28))
300 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
301 }
302
303 check_mpx_erratum(c);
304}
305
306#ifdef CONFIG_X86_32
307/*
308 * Early probe support logic for ppro memory erratum #50
309 *
310 * This is called before we do cpu ident work
311 */
312
313int ppro_with_ram_bug(void)
314{
315 /* Uses data from early_cpu_detect now */
316 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
317 boot_cpu_data.x86 == 6 &&
318 boot_cpu_data.x86_model == 1 &&
319 boot_cpu_data.x86_stepping < 8) {
320 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
321 return 1;
322 }
323 return 0;
324}
325
326static void intel_smp_check(struct cpuinfo_x86 *c)
327{
328 /* calling is from identify_secondary_cpu() ? */
329 if (!c->cpu_index)
330 return;
331
332 /*
333 * Mask B, Pentium, but not Pentium MMX
334 */
335 if (c->x86 == 5 &&
336 c->x86_stepping >= 1 && c->x86_stepping <= 4 &&
337 c->x86_model <= 3) {
338 /*
339 * Remember we have B step Pentia with bugs
340 */
341 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
342 "with B stepping processors.\n");
343 }
344}
345
346static int forcepae;
347static int __init forcepae_setup(char *__unused)
348{
349 forcepae = 1;
350 return 1;
351}
352__setup("forcepae", forcepae_setup);
353
354static void intel_workarounds(struct cpuinfo_x86 *c)
355{
356#ifdef CONFIG_X86_F00F_BUG
357 /*
358 * All models of Pentium and Pentium with MMX technology CPUs
359 * have the F0 0F bug, which lets nonprivileged users lock up the
360 * system. Announce that the fault handler will be checking for it.
361 * The Quark is also family 5, but does not have the same bug.
362 */
363 clear_cpu_bug(c, X86_BUG_F00F);
364 if (c->x86 == 5 && c->x86_model < 9) {
365 static int f00f_workaround_enabled;
366
367 set_cpu_bug(c, X86_BUG_F00F);
368 if (!f00f_workaround_enabled) {
369 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");
370 f00f_workaround_enabled = 1;
371 }
372 }
373#endif
374
375 /*
376 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
377 * model 3 mask 3
378 */
379 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)
380 clear_cpu_cap(c, X86_FEATURE_SEP);
381
382 /*
383 * PAE CPUID issue: many Pentium M report no PAE but may have a
384 * functionally usable PAE implementation.
385 * Forcefully enable PAE if kernel parameter "forcepae" is present.
386 */
387 if (forcepae) {
388 pr_warn("PAE forced!\n");
389 set_cpu_cap(c, X86_FEATURE_PAE);
390 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
391 }
392
393 /*
394 * P4 Xeon erratum 037 workaround.
395 * Hardware prefetcher may cause stale data to be loaded into the cache.
396 */
397 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {
398 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
399 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
400 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
401 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
402 }
403 }
404
405 /*
406 * See if we have a good local APIC by checking for buggy Pentia,
407 * i.e. all B steppings and the C2 stepping of P54C when using their
408 * integrated APIC (see 11AP erratum in "Pentium Processor
409 * Specification Update").
410 */
411 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
412 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))
413 set_cpu_bug(c, X86_BUG_11AP);
414
415
416#ifdef CONFIG_X86_INTEL_USERCOPY
417 /*
418 * Set up the preferred alignment for movsl bulk memory moves
419 */
420 switch (c->x86) {
421 case 4: /* 486: untested */
422 break;
423 case 5: /* Old Pentia: untested */
424 break;
425 case 6: /* PII/PIII only like movsl with 8-byte alignment */
426 movsl_mask.mask = 7;
427 break;
428 case 15: /* P4 is OK down to 8-byte alignment */
429 movsl_mask.mask = 7;
430 break;
431 }
432#endif
433
434 intel_smp_check(c);
435}
436#else
437static void intel_workarounds(struct cpuinfo_x86 *c)
438{
439}
440#endif
441
442static void srat_detect_node(struct cpuinfo_x86 *c)
443{
444#ifdef CONFIG_NUMA
445 unsigned node;
446 int cpu = smp_processor_id();
447
448 /* Don't do the funky fallback heuristics the AMD version employs
449 for now. */
450 node = numa_cpu_node(cpu);
451 if (node == NUMA_NO_NODE || !node_online(node)) {
452 /* reuse the value from init_cpu_to_node() */
453 node = cpu_to_node(cpu);
454 }
455 numa_set_node(cpu, node);
456#endif
457}
458
459/*
460 * find out the number of processor cores on the die
461 */
462static int intel_num_cpu_cores(struct cpuinfo_x86 *c)
463{
464 unsigned int eax, ebx, ecx, edx;
465
466 if (!IS_ENABLED(CONFIG_SMP) || c->cpuid_level < 4)
467 return 1;
468
469 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
470 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
471 if (eax & 0x1f)
472 return (eax >> 26) + 1;
473 else
474 return 1;
475}
476
477static void detect_vmx_virtcap(struct cpuinfo_x86 *c)
478{
479 /* Intel VMX MSR indicated features */
480#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
481#define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
482#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
483#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
484#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
485#define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
486
487 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
488
489 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
490 clear_cpu_cap(c, X86_FEATURE_VNMI);
491 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
492 clear_cpu_cap(c, X86_FEATURE_EPT);
493 clear_cpu_cap(c, X86_FEATURE_VPID);
494
495 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
496 msr_ctl = vmx_msr_high | vmx_msr_low;
497 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
498 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
499 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
500 set_cpu_cap(c, X86_FEATURE_VNMI);
501 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
502 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
503 vmx_msr_low, vmx_msr_high);
504 msr_ctl2 = vmx_msr_high | vmx_msr_low;
505 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
506 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
507 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
508 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
509 set_cpu_cap(c, X86_FEATURE_EPT);
510 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
511 set_cpu_cap(c, X86_FEATURE_VPID);
512 }
513}
514
515#define MSR_IA32_TME_ACTIVATE 0x982
516
517/* Helpers to access TME_ACTIVATE MSR */
518#define TME_ACTIVATE_LOCKED(x) (x & 0x1)
519#define TME_ACTIVATE_ENABLED(x) (x & 0x2)
520
521#define TME_ACTIVATE_POLICY(x) ((x >> 4) & 0xf) /* Bits 7:4 */
522#define TME_ACTIVATE_POLICY_AES_XTS_128 0
523
524#define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */
525
526#define TME_ACTIVATE_CRYPTO_ALGS(x) ((x >> 48) & 0xffff) /* Bits 63:48 */
527#define TME_ACTIVATE_CRYPTO_AES_XTS_128 1
528
529/* Values for mktme_status (SW only construct) */
530#define MKTME_ENABLED 0
531#define MKTME_DISABLED 1
532#define MKTME_UNINITIALIZED 2
533static int mktme_status = MKTME_UNINITIALIZED;
534
535static void detect_tme(struct cpuinfo_x86 *c)
536{
537 u64 tme_activate, tme_policy, tme_crypto_algs;
538 int keyid_bits = 0, nr_keyids = 0;
539 static u64 tme_activate_cpu0 = 0;
540
541 rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate);
542
543 if (mktme_status != MKTME_UNINITIALIZED) {
544 if (tme_activate != tme_activate_cpu0) {
545 /* Broken BIOS? */
546 pr_err_once("x86/tme: configuration is inconsistent between CPUs\n");
547 pr_err_once("x86/tme: MKTME is not usable\n");
548 mktme_status = MKTME_DISABLED;
549
550 /* Proceed. We may need to exclude bits from x86_phys_bits. */
551 }
552 } else {
553 tme_activate_cpu0 = tme_activate;
554 }
555
556 if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) {
557 pr_info_once("x86/tme: not enabled by BIOS\n");
558 mktme_status = MKTME_DISABLED;
559 return;
560 }
561
562 if (mktme_status != MKTME_UNINITIALIZED)
563 goto detect_keyid_bits;
564
565 pr_info("x86/tme: enabled by BIOS\n");
566
567 tme_policy = TME_ACTIVATE_POLICY(tme_activate);
568 if (tme_policy != TME_ACTIVATE_POLICY_AES_XTS_128)
569 pr_warn("x86/tme: Unknown policy is active: %#llx\n", tme_policy);
570
571 tme_crypto_algs = TME_ACTIVATE_CRYPTO_ALGS(tme_activate);
572 if (!(tme_crypto_algs & TME_ACTIVATE_CRYPTO_AES_XTS_128)) {
573 pr_err("x86/mktme: No known encryption algorithm is supported: %#llx\n",
574 tme_crypto_algs);
575 mktme_status = MKTME_DISABLED;
576 }
577detect_keyid_bits:
578 keyid_bits = TME_ACTIVATE_KEYID_BITS(tme_activate);
579 nr_keyids = (1UL << keyid_bits) - 1;
580 if (nr_keyids) {
581 pr_info_once("x86/mktme: enabled by BIOS\n");
582 pr_info_once("x86/mktme: %d KeyIDs available\n", nr_keyids);
583 } else {
584 pr_info_once("x86/mktme: disabled by BIOS\n");
585 }
586
587 if (mktme_status == MKTME_UNINITIALIZED) {
588 /* MKTME is usable */
589 mktme_status = MKTME_ENABLED;
590 }
591
592 /*
593 * KeyID bits effectively lower the number of physical address
594 * bits. Update cpuinfo_x86::x86_phys_bits accordingly.
595 */
596 c->x86_phys_bits -= keyid_bits;
597}
598
599static void init_intel_energy_perf(struct cpuinfo_x86 *c)
600{
601 u64 epb;
602
603 /*
604 * Initialize MSR_IA32_ENERGY_PERF_BIAS if not already initialized.
605 * (x86_energy_perf_policy(8) is available to change it at run-time.)
606 */
607 if (!cpu_has(c, X86_FEATURE_EPB))
608 return;
609
610 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
611 if ((epb & 0xF) != ENERGY_PERF_BIAS_PERFORMANCE)
612 return;
613
614 pr_warn_once("ENERGY_PERF_BIAS: Set to 'normal', was 'performance'\n");
615 pr_warn_once("ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)\n");
616 epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
617 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
618}
619
620static void intel_bsp_resume(struct cpuinfo_x86 *c)
621{
622 /*
623 * MSR_IA32_ENERGY_PERF_BIAS is lost across suspend/resume,
624 * so reinitialize it properly like during bootup:
625 */
626 init_intel_energy_perf(c);
627}
628
629static void init_cpuid_fault(struct cpuinfo_x86 *c)
630{
631 u64 msr;
632
633 if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) {
634 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT)
635 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT);
636 }
637}
638
639static void init_intel_misc_features(struct cpuinfo_x86 *c)
640{
641 u64 msr;
642
643 if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr))
644 return;
645
646 /* Clear all MISC features */
647 this_cpu_write(msr_misc_features_shadow, 0);
648
649 /* Check features and update capabilities and shadow control bits */
650 init_cpuid_fault(c);
651 probe_xeon_phi_r3mwait(c);
652
653 msr = this_cpu_read(msr_misc_features_shadow);
654 wrmsrl(MSR_MISC_FEATURES_ENABLES, msr);
655}
656
657static void init_intel(struct cpuinfo_x86 *c)
658{
659 unsigned int l2 = 0;
660
661 early_init_intel(c);
662
663 intel_workarounds(c);
664
665 /*
666 * Detect the extended topology information if available. This
667 * will reinitialise the initial_apicid which will be used
668 * in init_intel_cacheinfo()
669 */
670 detect_extended_topology(c);
671
672 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
673 /*
674 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
675 * detection.
676 */
677 c->x86_max_cores = intel_num_cpu_cores(c);
678#ifdef CONFIG_X86_32
679 detect_ht(c);
680#endif
681 }
682
683 l2 = init_intel_cacheinfo(c);
684
685 /* Detect legacy cache sizes if init_intel_cacheinfo did not */
686 if (l2 == 0) {
687 cpu_detect_cache_sizes(c);
688 l2 = c->x86_cache_size;
689 }
690
691 if (c->cpuid_level > 9) {
692 unsigned eax = cpuid_eax(10);
693 /* Check for version and the number of counters */
694 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
695 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
696 }
697
698 if (cpu_has(c, X86_FEATURE_XMM2))
699 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
700
701 if (boot_cpu_has(X86_FEATURE_DS)) {
702 unsigned int l1;
703 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
704 if (!(l1 & (1<<11)))
705 set_cpu_cap(c, X86_FEATURE_BTS);
706 if (!(l1 & (1<<12)))
707 set_cpu_cap(c, X86_FEATURE_PEBS);
708 }
709
710 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&
711 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
712 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
713
714 if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_MWAIT) &&
715 ((c->x86_model == INTEL_FAM6_ATOM_GOLDMONT)))
716 set_cpu_bug(c, X86_BUG_MONITOR);
717
718#ifdef CONFIG_X86_64
719 if (c->x86 == 15)
720 c->x86_cache_alignment = c->x86_clflush_size * 2;
721 if (c->x86 == 6)
722 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
723#else
724 /*
725 * Names for the Pentium II/Celeron processors
726 * detectable only by also checking the cache size.
727 * Dixon is NOT a Celeron.
728 */
729 if (c->x86 == 6) {
730 char *p = NULL;
731
732 switch (c->x86_model) {
733 case 5:
734 if (l2 == 0)
735 p = "Celeron (Covington)";
736 else if (l2 == 256)
737 p = "Mobile Pentium II (Dixon)";
738 break;
739
740 case 6:
741 if (l2 == 128)
742 p = "Celeron (Mendocino)";
743 else if (c->x86_stepping == 0 || c->x86_stepping == 5)
744 p = "Celeron-A";
745 break;
746
747 case 8:
748 if (l2 == 128)
749 p = "Celeron (Coppermine)";
750 break;
751 }
752
753 if (p)
754 strcpy(c->x86_model_id, p);
755 }
756
757 if (c->x86 == 15)
758 set_cpu_cap(c, X86_FEATURE_P4);
759 if (c->x86 == 6)
760 set_cpu_cap(c, X86_FEATURE_P3);
761#endif
762
763 /* Work around errata */
764 srat_detect_node(c);
765
766 if (cpu_has(c, X86_FEATURE_VMX))
767 detect_vmx_virtcap(c);
768
769 if (cpu_has(c, X86_FEATURE_TME))
770 detect_tme(c);
771
772 init_intel_energy_perf(c);
773
774 init_intel_misc_features(c);
775}
776
777#ifdef CONFIG_X86_32
778static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
779{
780 /*
781 * Intel PIII Tualatin. This comes in two flavours.
782 * One has 256kb of cache, the other 512. We have no way
783 * to determine which, so we use a boottime override
784 * for the 512kb model, and assume 256 otherwise.
785 */
786 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
787 size = 256;
788
789 /*
790 * Intel Quark SoC X1000 contains a 4-way set associative
791 * 16K cache with a 16 byte cache line and 256 lines per tag
792 */
793 if ((c->x86 == 5) && (c->x86_model == 9))
794 size = 16;
795 return size;
796}
797#endif
798
799#define TLB_INST_4K 0x01
800#define TLB_INST_4M 0x02
801#define TLB_INST_2M_4M 0x03
802
803#define TLB_INST_ALL 0x05
804#define TLB_INST_1G 0x06
805
806#define TLB_DATA_4K 0x11
807#define TLB_DATA_4M 0x12
808#define TLB_DATA_2M_4M 0x13
809#define TLB_DATA_4K_4M 0x14
810
811#define TLB_DATA_1G 0x16
812
813#define TLB_DATA0_4K 0x21
814#define TLB_DATA0_4M 0x22
815#define TLB_DATA0_2M_4M 0x23
816
817#define STLB_4K 0x41
818#define STLB_4K_2M 0x42
819
820static const struct _tlb_table intel_tlb_table[] = {
821 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
822 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
823 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
824 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
825 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
826 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
827 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" },
828 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
829 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
830 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
831 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
832 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
833 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
834 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
835 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
836 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
837 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
838 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
839 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
840 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
841 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" },
842 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
843 { 0x6d, TLB_DATA_1G, 16, " TLB_DATA 1 GByte pages, fully associative" },
844 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
845 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
846 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
847 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
848 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
849 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
850 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
851 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
852 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
853 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
854 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
855 { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" },
856 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
857 { 0x00, 0, 0 }
858};
859
860static void intel_tlb_lookup(const unsigned char desc)
861{
862 unsigned char k;
863 if (desc == 0)
864 return;
865
866 /* look up this descriptor in the table */
867 for (k = 0; intel_tlb_table[k].descriptor != desc && \
868 intel_tlb_table[k].descriptor != 0; k++)
869 ;
870
871 if (intel_tlb_table[k].tlb_type == 0)
872 return;
873
874 switch (intel_tlb_table[k].tlb_type) {
875 case STLB_4K:
876 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
877 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
878 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
879 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
880 break;
881 case STLB_4K_2M:
882 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
883 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
884 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
885 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
886 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
887 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
888 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
889 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
890 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
891 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
892 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
893 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
894 break;
895 case TLB_INST_ALL:
896 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
897 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
898 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
899 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
900 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
901 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
902 break;
903 case TLB_INST_4K:
904 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
905 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
906 break;
907 case TLB_INST_4M:
908 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
909 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
910 break;
911 case TLB_INST_2M_4M:
912 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
913 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
914 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
915 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
916 break;
917 case TLB_DATA_4K:
918 case TLB_DATA0_4K:
919 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
920 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
921 break;
922 case TLB_DATA_4M:
923 case TLB_DATA0_4M:
924 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
925 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
926 break;
927 case TLB_DATA_2M_4M:
928 case TLB_DATA0_2M_4M:
929 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
930 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
931 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
932 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
933 break;
934 case TLB_DATA_4K_4M:
935 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
936 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
937 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
938 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
939 break;
940 case TLB_DATA_1G:
941 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
942 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
943 break;
944 }
945}
946
947static void intel_detect_tlb(struct cpuinfo_x86 *c)
948{
949 int i, j, n;
950 unsigned int regs[4];
951 unsigned char *desc = (unsigned char *)regs;
952
953 if (c->cpuid_level < 2)
954 return;
955
956 /* Number of times to iterate */
957 n = cpuid_eax(2) & 0xFF;
958
959 for (i = 0 ; i < n ; i++) {
960 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]);
961
962 /* If bit 31 is set, this is an unknown format */
963 for (j = 0 ; j < 3 ; j++)
964 if (regs[j] & (1 << 31))
965 regs[j] = 0;
966
967 /* Byte 0 is level count, not a descriptor */
968 for (j = 1 ; j < 16 ; j++)
969 intel_tlb_lookup(desc[j]);
970 }
971}
972
973static const struct cpu_dev intel_cpu_dev = {
974 .c_vendor = "Intel",
975 .c_ident = { "GenuineIntel" },
976#ifdef CONFIG_X86_32
977 .legacy_models = {
978 { .family = 4, .model_names =
979 {
980 [0] = "486 DX-25/33",
981 [1] = "486 DX-50",
982 [2] = "486 SX",
983 [3] = "486 DX/2",
984 [4] = "486 SL",
985 [5] = "486 SX/2",
986 [7] = "486 DX/2-WB",
987 [8] = "486 DX/4",
988 [9] = "486 DX/4-WB"
989 }
990 },
991 { .family = 5, .model_names =
992 {
993 [0] = "Pentium 60/66 A-step",
994 [1] = "Pentium 60/66",
995 [2] = "Pentium 75 - 200",
996 [3] = "OverDrive PODP5V83",
997 [4] = "Pentium MMX",
998 [7] = "Mobile Pentium 75 - 200",
999 [8] = "Mobile Pentium MMX",
1000 [9] = "Quark SoC X1000",
1001 }
1002 },
1003 { .family = 6, .model_names =
1004 {
1005 [0] = "Pentium Pro A-step",
1006 [1] = "Pentium Pro",
1007 [3] = "Pentium II (Klamath)",
1008 [4] = "Pentium II (Deschutes)",
1009 [5] = "Pentium II (Deschutes)",
1010 [6] = "Mobile Pentium II",
1011 [7] = "Pentium III (Katmai)",
1012 [8] = "Pentium III (Coppermine)",
1013 [10] = "Pentium III (Cascades)",
1014 [11] = "Pentium III (Tualatin)",
1015 }
1016 },
1017 { .family = 15, .model_names =
1018 {
1019 [0] = "Pentium 4 (Unknown)",
1020 [1] = "Pentium 4 (Willamette)",
1021 [2] = "Pentium 4 (Northwood)",
1022 [4] = "Pentium 4 (Foster)",
1023 [5] = "Pentium 4 (Foster)",
1024 }
1025 },
1026 },
1027 .legacy_cache_size = intel_size_cache,
1028#endif
1029 .c_detect_tlb = intel_detect_tlb,
1030 .c_early_init = early_init_intel,
1031 .c_init = init_intel,
1032 .c_bsp_resume = intel_bsp_resume,
1033 .c_x86_vendor = X86_VENDOR_INTEL,
1034};
1035
1036cpu_dev_register(intel_cpu_dev);
1037
1#include <linux/kernel.h>
2
3#include <linux/string.h>
4#include <linux/bitops.h>
5#include <linux/smp.h>
6#include <linux/sched.h>
7#include <linux/thread_info.h>
8#include <linux/module.h>
9#include <linux/uaccess.h>
10
11#include <asm/processor.h>
12#include <asm/pgtable.h>
13#include <asm/msr.h>
14#include <asm/bugs.h>
15#include <asm/cpu.h>
16
17#ifdef CONFIG_X86_64
18#include <linux/topology.h>
19#endif
20
21#include "cpu.h"
22
23#ifdef CONFIG_X86_LOCAL_APIC
24#include <asm/mpspec.h>
25#include <asm/apic.h>
26#endif
27
28static void early_init_intel(struct cpuinfo_x86 *c)
29{
30 u64 misc_enable;
31
32 /* Unmask CPUID levels if masked: */
33 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
34 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
35 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
36 c->cpuid_level = cpuid_eax(0);
37 get_cpu_cap(c);
38 }
39 }
40
41 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
42 (c->x86 == 0x6 && c->x86_model >= 0x0e))
43 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
44
45 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) {
46 unsigned lower_word;
47
48 wrmsr(MSR_IA32_UCODE_REV, 0, 0);
49 /* Required by the SDM */
50 sync_core();
51 rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode);
52 }
53
54 /*
55 * Atom erratum AAE44/AAF40/AAG38/AAH41:
56 *
57 * A race condition between speculative fetches and invalidating
58 * a large page. This is worked around in microcode, but we
59 * need the microcode to have already been loaded... so if it is
60 * not, recommend a BIOS update and disable large pages.
61 */
62 if (c->x86 == 6 && c->x86_model == 0x1c && c->x86_mask <= 2 &&
63 c->microcode < 0x20e) {
64 printk(KERN_WARNING "Atom PSE erratum detected, BIOS microcode update recommended\n");
65 clear_cpu_cap(c, X86_FEATURE_PSE);
66 }
67
68#ifdef CONFIG_X86_64
69 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
70#else
71 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
72 if (c->x86 == 15 && c->x86_cache_alignment == 64)
73 c->x86_cache_alignment = 128;
74#endif
75
76 /* CPUID workaround for 0F33/0F34 CPU */
77 if (c->x86 == 0xF && c->x86_model == 0x3
78 && (c->x86_mask == 0x3 || c->x86_mask == 0x4))
79 c->x86_phys_bits = 36;
80
81 /*
82 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
83 * with P/T states and does not stop in deep C-states.
84 *
85 * It is also reliable across cores and sockets. (but not across
86 * cabinets - we turn it off in that case explicitly.)
87 */
88 if (c->x86_power & (1 << 8)) {
89 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
90 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
91 if (!check_tsc_unstable())
92 set_sched_clock_stable();
93 }
94
95 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
96 if (c->x86 == 6) {
97 switch (c->x86_model) {
98 case 0x27: /* Penwell */
99 case 0x35: /* Cloverview */
100 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
101 break;
102 default:
103 break;
104 }
105 }
106
107 /*
108 * There is a known erratum on Pentium III and Core Solo
109 * and Core Duo CPUs.
110 * " Page with PAT set to WC while associated MTRR is UC
111 * may consolidate to UC "
112 * Because of this erratum, it is better to stick with
113 * setting WC in MTRR rather than using PAT on these CPUs.
114 *
115 * Enable PAT WC only on P4, Core 2 or later CPUs.
116 */
117 if (c->x86 == 6 && c->x86_model < 15)
118 clear_cpu_cap(c, X86_FEATURE_PAT);
119
120#ifdef CONFIG_KMEMCHECK
121 /*
122 * P4s have a "fast strings" feature which causes single-
123 * stepping REP instructions to only generate a #DB on
124 * cache-line boundaries.
125 *
126 * Ingo Molnar reported a Pentium D (model 6) and a Xeon
127 * (model 2) with the same problem.
128 */
129 if (c->x86 == 15)
130 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
131 MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) > 0)
132 pr_info("kmemcheck: Disabling fast string operations\n");
133#endif
134
135 /*
136 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
137 * clear the fast string and enhanced fast string CPU capabilities.
138 */
139 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
140 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
141 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
142 printk(KERN_INFO "Disabled fast string operations\n");
143 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
144 setup_clear_cpu_cap(X86_FEATURE_ERMS);
145 }
146 }
147}
148
149#ifdef CONFIG_X86_32
150/*
151 * Early probe support logic for ppro memory erratum #50
152 *
153 * This is called before we do cpu ident work
154 */
155
156int ppro_with_ram_bug(void)
157{
158 /* Uses data from early_cpu_detect now */
159 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
160 boot_cpu_data.x86 == 6 &&
161 boot_cpu_data.x86_model == 1 &&
162 boot_cpu_data.x86_mask < 8) {
163 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
164 return 1;
165 }
166 return 0;
167}
168
169static void intel_smp_check(struct cpuinfo_x86 *c)
170{
171 /* calling is from identify_secondary_cpu() ? */
172 if (!c->cpu_index)
173 return;
174
175 /*
176 * Mask B, Pentium, but not Pentium MMX
177 */
178 if (c->x86 == 5 &&
179 c->x86_mask >= 1 && c->x86_mask <= 4 &&
180 c->x86_model <= 3) {
181 /*
182 * Remember we have B step Pentia with bugs
183 */
184 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
185 "with B stepping processors.\n");
186 }
187}
188
189static int forcepae;
190static int __init forcepae_setup(char *__unused)
191{
192 forcepae = 1;
193 return 1;
194}
195__setup("forcepae", forcepae_setup);
196
197static void intel_workarounds(struct cpuinfo_x86 *c)
198{
199#ifdef CONFIG_X86_F00F_BUG
200 /*
201 * All current models of Pentium and Pentium with MMX technology CPUs
202 * have the F0 0F bug, which lets nonprivileged users lock up the
203 * system. Announce that the fault handler will be checking for it.
204 */
205 clear_cpu_bug(c, X86_BUG_F00F);
206 if (!paravirt_enabled() && c->x86 == 5) {
207 static int f00f_workaround_enabled;
208
209 set_cpu_bug(c, X86_BUG_F00F);
210 if (!f00f_workaround_enabled) {
211 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
212 f00f_workaround_enabled = 1;
213 }
214 }
215#endif
216
217 /*
218 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
219 * model 3 mask 3
220 */
221 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
222 clear_cpu_cap(c, X86_FEATURE_SEP);
223
224 /*
225 * PAE CPUID issue: many Pentium M report no PAE but may have a
226 * functionally usable PAE implementation.
227 * Forcefully enable PAE if kernel parameter "forcepae" is present.
228 */
229 if (forcepae) {
230 printk(KERN_WARNING "PAE forced!\n");
231 set_cpu_cap(c, X86_FEATURE_PAE);
232 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
233 }
234
235 /*
236 * P4 Xeon errata 037 workaround.
237 * Hardware prefetcher may cause stale data to be loaded into the cache.
238 */
239 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
240 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
241 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
242 > 0) {
243 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
244 pr_info("CPU: Disabling hardware prefetching (Errata 037)\n");
245 }
246 }
247
248 /*
249 * See if we have a good local APIC by checking for buggy Pentia,
250 * i.e. all B steppings and the C2 stepping of P54C when using their
251 * integrated APIC (see 11AP erratum in "Pentium Processor
252 * Specification Update").
253 */
254 if (cpu_has_apic && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
255 (c->x86_mask < 0x6 || c->x86_mask == 0xb))
256 set_cpu_cap(c, X86_FEATURE_11AP);
257
258
259#ifdef CONFIG_X86_INTEL_USERCOPY
260 /*
261 * Set up the preferred alignment for movsl bulk memory moves
262 */
263 switch (c->x86) {
264 case 4: /* 486: untested */
265 break;
266 case 5: /* Old Pentia: untested */
267 break;
268 case 6: /* PII/PIII only like movsl with 8-byte alignment */
269 movsl_mask.mask = 7;
270 break;
271 case 15: /* P4 is OK down to 8-byte alignment */
272 movsl_mask.mask = 7;
273 break;
274 }
275#endif
276
277 intel_smp_check(c);
278}
279#else
280static void intel_workarounds(struct cpuinfo_x86 *c)
281{
282}
283#endif
284
285static void srat_detect_node(struct cpuinfo_x86 *c)
286{
287#ifdef CONFIG_NUMA
288 unsigned node;
289 int cpu = smp_processor_id();
290
291 /* Don't do the funky fallback heuristics the AMD version employs
292 for now. */
293 node = numa_cpu_node(cpu);
294 if (node == NUMA_NO_NODE || !node_online(node)) {
295 /* reuse the value from init_cpu_to_node() */
296 node = cpu_to_node(cpu);
297 }
298 numa_set_node(cpu, node);
299#endif
300}
301
302/*
303 * find out the number of processor cores on the die
304 */
305static int intel_num_cpu_cores(struct cpuinfo_x86 *c)
306{
307 unsigned int eax, ebx, ecx, edx;
308
309 if (c->cpuid_level < 4)
310 return 1;
311
312 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
313 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
314 if (eax & 0x1f)
315 return (eax >> 26) + 1;
316 else
317 return 1;
318}
319
320static void detect_vmx_virtcap(struct cpuinfo_x86 *c)
321{
322 /* Intel VMX MSR indicated features */
323#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
324#define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
325#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
326#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
327#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
328#define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
329
330 u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
331
332 clear_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
333 clear_cpu_cap(c, X86_FEATURE_VNMI);
334 clear_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
335 clear_cpu_cap(c, X86_FEATURE_EPT);
336 clear_cpu_cap(c, X86_FEATURE_VPID);
337
338 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
339 msr_ctl = vmx_msr_high | vmx_msr_low;
340 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
341 set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
342 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
343 set_cpu_cap(c, X86_FEATURE_VNMI);
344 if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
345 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
346 vmx_msr_low, vmx_msr_high);
347 msr_ctl2 = vmx_msr_high | vmx_msr_low;
348 if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
349 (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
350 set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
351 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
352 set_cpu_cap(c, X86_FEATURE_EPT);
353 if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
354 set_cpu_cap(c, X86_FEATURE_VPID);
355 }
356}
357
358static void init_intel(struct cpuinfo_x86 *c)
359{
360 unsigned int l2 = 0;
361
362 early_init_intel(c);
363
364 intel_workarounds(c);
365
366 /*
367 * Detect the extended topology information if available. This
368 * will reinitialise the initial_apicid which will be used
369 * in init_intel_cacheinfo()
370 */
371 detect_extended_topology(c);
372
373 l2 = init_intel_cacheinfo(c);
374 if (c->cpuid_level > 9) {
375 unsigned eax = cpuid_eax(10);
376 /* Check for version and the number of counters */
377 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
378 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
379 }
380
381 if (cpu_has_xmm2)
382 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
383 if (cpu_has_ds) {
384 unsigned int l1;
385 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
386 if (!(l1 & (1<<11)))
387 set_cpu_cap(c, X86_FEATURE_BTS);
388 if (!(l1 & (1<<12)))
389 set_cpu_cap(c, X86_FEATURE_PEBS);
390 }
391
392 if (c->x86 == 6 && cpu_has_clflush &&
393 (c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
394 set_cpu_cap(c, X86_FEATURE_CLFLUSH_MONITOR);
395
396#ifdef CONFIG_X86_64
397 if (c->x86 == 15)
398 c->x86_cache_alignment = c->x86_clflush_size * 2;
399 if (c->x86 == 6)
400 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
401#else
402 /*
403 * Names for the Pentium II/Celeron processors
404 * detectable only by also checking the cache size.
405 * Dixon is NOT a Celeron.
406 */
407 if (c->x86 == 6) {
408 char *p = NULL;
409
410 switch (c->x86_model) {
411 case 5:
412 if (l2 == 0)
413 p = "Celeron (Covington)";
414 else if (l2 == 256)
415 p = "Mobile Pentium II (Dixon)";
416 break;
417
418 case 6:
419 if (l2 == 128)
420 p = "Celeron (Mendocino)";
421 else if (c->x86_mask == 0 || c->x86_mask == 5)
422 p = "Celeron-A";
423 break;
424
425 case 8:
426 if (l2 == 128)
427 p = "Celeron (Coppermine)";
428 break;
429 }
430
431 if (p)
432 strcpy(c->x86_model_id, p);
433 }
434
435 if (c->x86 == 15)
436 set_cpu_cap(c, X86_FEATURE_P4);
437 if (c->x86 == 6)
438 set_cpu_cap(c, X86_FEATURE_P3);
439#endif
440
441 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
442 /*
443 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
444 * detection.
445 */
446 c->x86_max_cores = intel_num_cpu_cores(c);
447#ifdef CONFIG_X86_32
448 detect_ht(c);
449#endif
450 }
451
452 /* Work around errata */
453 srat_detect_node(c);
454
455 if (cpu_has(c, X86_FEATURE_VMX))
456 detect_vmx_virtcap(c);
457
458 /*
459 * Initialize MSR_IA32_ENERGY_PERF_BIAS if BIOS did not.
460 * x86_energy_perf_policy(8) is available to change it at run-time
461 */
462 if (cpu_has(c, X86_FEATURE_EPB)) {
463 u64 epb;
464
465 rdmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
466 if ((epb & 0xF) == ENERGY_PERF_BIAS_PERFORMANCE) {
467 printk_once(KERN_WARNING "ENERGY_PERF_BIAS:"
468 " Set to 'normal', was 'performance'\n"
469 "ENERGY_PERF_BIAS: View and update with"
470 " x86_energy_perf_policy(8)\n");
471 epb = (epb & ~0xF) | ENERGY_PERF_BIAS_NORMAL;
472 wrmsrl(MSR_IA32_ENERGY_PERF_BIAS, epb);
473 }
474 }
475}
476
477#ifdef CONFIG_X86_32
478static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
479{
480 /*
481 * Intel PIII Tualatin. This comes in two flavours.
482 * One has 256kb of cache, the other 512. We have no way
483 * to determine which, so we use a boottime override
484 * for the 512kb model, and assume 256 otherwise.
485 */
486 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
487 size = 256;
488 return size;
489}
490#endif
491
492#define TLB_INST_4K 0x01
493#define TLB_INST_4M 0x02
494#define TLB_INST_2M_4M 0x03
495
496#define TLB_INST_ALL 0x05
497#define TLB_INST_1G 0x06
498
499#define TLB_DATA_4K 0x11
500#define TLB_DATA_4M 0x12
501#define TLB_DATA_2M_4M 0x13
502#define TLB_DATA_4K_4M 0x14
503
504#define TLB_DATA_1G 0x16
505
506#define TLB_DATA0_4K 0x21
507#define TLB_DATA0_4M 0x22
508#define TLB_DATA0_2M_4M 0x23
509
510#define STLB_4K 0x41
511#define STLB_4K_2M 0x42
512
513static const struct _tlb_table intel_tlb_table[] = {
514 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
515 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
516 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
517 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
518 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
519 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
520 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages */" },
521 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
522 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
523 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
524 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
525 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
526 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
527 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
528 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
529 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
530 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
531 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
532 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
533 { 0x63, TLB_DATA_1G, 4, " TLB_DATA 1 GByte pages, 4-way set associative" },
534 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
535 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
536 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
537 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
538 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
539 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
540 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set ssociative" },
541 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set ssociative" },
542 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
543 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
544 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
545 { 0xc2, TLB_DATA_2M_4M, 16, " DTLB 2 MByte/4MByte pages, 4-way associative" },
546 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
547 { 0x00, 0, 0 }
548};
549
550static void intel_tlb_lookup(const unsigned char desc)
551{
552 unsigned char k;
553 if (desc == 0)
554 return;
555
556 /* look up this descriptor in the table */
557 for (k = 0; intel_tlb_table[k].descriptor != desc && \
558 intel_tlb_table[k].descriptor != 0; k++)
559 ;
560
561 if (intel_tlb_table[k].tlb_type == 0)
562 return;
563
564 switch (intel_tlb_table[k].tlb_type) {
565 case STLB_4K:
566 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
567 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
568 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
569 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
570 break;
571 case STLB_4K_2M:
572 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
573 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
574 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
575 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
576 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
577 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
578 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
579 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
580 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
581 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
582 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
583 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
584 break;
585 case TLB_INST_ALL:
586 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
587 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
588 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
589 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
590 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
591 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
592 break;
593 case TLB_INST_4K:
594 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
595 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
596 break;
597 case TLB_INST_4M:
598 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
599 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
600 break;
601 case TLB_INST_2M_4M:
602 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
603 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
604 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
605 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
606 break;
607 case TLB_DATA_4K:
608 case TLB_DATA0_4K:
609 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
610 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
611 break;
612 case TLB_DATA_4M:
613 case TLB_DATA0_4M:
614 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
615 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
616 break;
617 case TLB_DATA_2M_4M:
618 case TLB_DATA0_2M_4M:
619 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
620 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
621 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
622 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
623 break;
624 case TLB_DATA_4K_4M:
625 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
626 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
627 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
628 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
629 break;
630 case TLB_DATA_1G:
631 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
632 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
633 break;
634 }
635}
636
637static void intel_tlb_flushall_shift_set(struct cpuinfo_x86 *c)
638{
639 switch ((c->x86 << 8) + c->x86_model) {
640 case 0x60f: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
641 case 0x616: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
642 case 0x617: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
643 case 0x61d: /* six-core 45 nm xeon "Dunnington" */
644 tlb_flushall_shift = -1;
645 break;
646 case 0x63a: /* Ivybridge */
647 tlb_flushall_shift = 2;
648 break;
649 case 0x61a: /* 45 nm nehalem, "Bloomfield" */
650 case 0x61e: /* 45 nm nehalem, "Lynnfield" */
651 case 0x625: /* 32 nm nehalem, "Clarkdale" */
652 case 0x62c: /* 32 nm nehalem, "Gulftown" */
653 case 0x62e: /* 45 nm nehalem-ex, "Beckton" */
654 case 0x62f: /* 32 nm Xeon E7 */
655 case 0x62a: /* SandyBridge */
656 case 0x62d: /* SandyBridge, "Romely-EP" */
657 default:
658 tlb_flushall_shift = 6;
659 }
660}
661
662static void intel_detect_tlb(struct cpuinfo_x86 *c)
663{
664 int i, j, n;
665 unsigned int regs[4];
666 unsigned char *desc = (unsigned char *)regs;
667
668 if (c->cpuid_level < 2)
669 return;
670
671 /* Number of times to iterate */
672 n = cpuid_eax(2) & 0xFF;
673
674 for (i = 0 ; i < n ; i++) {
675 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]);
676
677 /* If bit 31 is set, this is an unknown format */
678 for (j = 0 ; j < 3 ; j++)
679 if (regs[j] & (1 << 31))
680 regs[j] = 0;
681
682 /* Byte 0 is level count, not a descriptor */
683 for (j = 1 ; j < 16 ; j++)
684 intel_tlb_lookup(desc[j]);
685 }
686 intel_tlb_flushall_shift_set(c);
687}
688
689static const struct cpu_dev intel_cpu_dev = {
690 .c_vendor = "Intel",
691 .c_ident = { "GenuineIntel" },
692#ifdef CONFIG_X86_32
693 .legacy_models = {
694 { .family = 4, .model_names =
695 {
696 [0] = "486 DX-25/33",
697 [1] = "486 DX-50",
698 [2] = "486 SX",
699 [3] = "486 DX/2",
700 [4] = "486 SL",
701 [5] = "486 SX/2",
702 [7] = "486 DX/2-WB",
703 [8] = "486 DX/4",
704 [9] = "486 DX/4-WB"
705 }
706 },
707 { .family = 5, .model_names =
708 {
709 [0] = "Pentium 60/66 A-step",
710 [1] = "Pentium 60/66",
711 [2] = "Pentium 75 - 200",
712 [3] = "OverDrive PODP5V83",
713 [4] = "Pentium MMX",
714 [7] = "Mobile Pentium 75 - 200",
715 [8] = "Mobile Pentium MMX"
716 }
717 },
718 { .family = 6, .model_names =
719 {
720 [0] = "Pentium Pro A-step",
721 [1] = "Pentium Pro",
722 [3] = "Pentium II (Klamath)",
723 [4] = "Pentium II (Deschutes)",
724 [5] = "Pentium II (Deschutes)",
725 [6] = "Mobile Pentium II",
726 [7] = "Pentium III (Katmai)",
727 [8] = "Pentium III (Coppermine)",
728 [10] = "Pentium III (Cascades)",
729 [11] = "Pentium III (Tualatin)",
730 }
731 },
732 { .family = 15, .model_names =
733 {
734 [0] = "Pentium 4 (Unknown)",
735 [1] = "Pentium 4 (Willamette)",
736 [2] = "Pentium 4 (Northwood)",
737 [4] = "Pentium 4 (Foster)",
738 [5] = "Pentium 4 (Foster)",
739 }
740 },
741 },
742 .legacy_cache_size = intel_size_cache,
743#endif
744 .c_detect_tlb = intel_detect_tlb,
745 .c_early_init = early_init_intel,
746 .c_init = init_intel,
747 .c_x86_vendor = X86_VENDOR_INTEL,
748};
749
750cpu_dev_register(intel_cpu_dev);
751