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1/*
2 * Driver for the National Semiconductor DP83640 PHYTER
3 *
4 * Copyright (C) 2010 OMICRON electronics GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22
23#include <linux/crc32.h>
24#include <linux/ethtool.h>
25#include <linux/kernel.h>
26#include <linux/list.h>
27#include <linux/mii.h>
28#include <linux/module.h>
29#include <linux/net_tstamp.h>
30#include <linux/netdevice.h>
31#include <linux/if_vlan.h>
32#include <linux/phy.h>
33#include <linux/ptp_classify.h>
34#include <linux/ptp_clock_kernel.h>
35
36#include "dp83640_reg.h"
37
38#define DP83640_PHY_ID 0x20005ce1
39#define PAGESEL 0x13
40#define MAX_RXTS 64
41#define N_EXT_TS 6
42#define N_PER_OUT 7
43#define PSF_PTPVER 2
44#define PSF_EVNT 0x4000
45#define PSF_RX 0x2000
46#define PSF_TX 0x1000
47#define EXT_EVENT 1
48#define CAL_EVENT 7
49#define CAL_TRIGGER 1
50#define DP83640_N_PINS 12
51
52#define MII_DP83640_MICR 0x11
53#define MII_DP83640_MISR 0x12
54
55#define MII_DP83640_MICR_OE 0x1
56#define MII_DP83640_MICR_IE 0x2
57
58#define MII_DP83640_MISR_RHF_INT_EN 0x01
59#define MII_DP83640_MISR_FHF_INT_EN 0x02
60#define MII_DP83640_MISR_ANC_INT_EN 0x04
61#define MII_DP83640_MISR_DUP_INT_EN 0x08
62#define MII_DP83640_MISR_SPD_INT_EN 0x10
63#define MII_DP83640_MISR_LINK_INT_EN 0x20
64#define MII_DP83640_MISR_ED_INT_EN 0x40
65#define MII_DP83640_MISR_LQ_INT_EN 0x80
66
67/* phyter seems to miss the mark by 16 ns */
68#define ADJTIME_FIX 16
69
70#define SKB_TIMESTAMP_TIMEOUT 2 /* jiffies */
71
72#if defined(__BIG_ENDIAN)
73#define ENDIAN_FLAG 0
74#elif defined(__LITTLE_ENDIAN)
75#define ENDIAN_FLAG PSF_ENDIAN
76#endif
77
78struct dp83640_skb_info {
79 int ptp_type;
80 unsigned long tmo;
81};
82
83struct phy_rxts {
84 u16 ns_lo; /* ns[15:0] */
85 u16 ns_hi; /* overflow[1:0], ns[29:16] */
86 u16 sec_lo; /* sec[15:0] */
87 u16 sec_hi; /* sec[31:16] */
88 u16 seqid; /* sequenceId[15:0] */
89 u16 msgtype; /* messageType[3:0], hash[11:0] */
90};
91
92struct phy_txts {
93 u16 ns_lo; /* ns[15:0] */
94 u16 ns_hi; /* overflow[1:0], ns[29:16] */
95 u16 sec_lo; /* sec[15:0] */
96 u16 sec_hi; /* sec[31:16] */
97};
98
99struct rxts {
100 struct list_head list;
101 unsigned long tmo;
102 u64 ns;
103 u16 seqid;
104 u8 msgtype;
105 u16 hash;
106};
107
108struct dp83640_clock;
109
110struct dp83640_private {
111 struct list_head list;
112 struct dp83640_clock *clock;
113 struct phy_device *phydev;
114 struct delayed_work ts_work;
115 int hwts_tx_en;
116 int hwts_rx_en;
117 int layer;
118 int version;
119 /* remember state of cfg0 during calibration */
120 int cfg0;
121 /* remember the last event time stamp */
122 struct phy_txts edata;
123 /* list of rx timestamps */
124 struct list_head rxts;
125 struct list_head rxpool;
126 struct rxts rx_pool_data[MAX_RXTS];
127 /* protects above three fields from concurrent access */
128 spinlock_t rx_lock;
129 /* queues of incoming and outgoing packets */
130 struct sk_buff_head rx_queue;
131 struct sk_buff_head tx_queue;
132};
133
134struct dp83640_clock {
135 /* keeps the instance in the 'phyter_clocks' list */
136 struct list_head list;
137 /* we create one clock instance per MII bus */
138 struct mii_bus *bus;
139 /* protects extended registers from concurrent access */
140 struct mutex extreg_lock;
141 /* remembers which page was last selected */
142 int page;
143 /* our advertised capabilities */
144 struct ptp_clock_info caps;
145 /* protects the three fields below from concurrent access */
146 struct mutex clock_lock;
147 /* the one phyter from which we shall read */
148 struct dp83640_private *chosen;
149 /* list of the other attached phyters, not chosen */
150 struct list_head phylist;
151 /* reference to our PTP hardware clock */
152 struct ptp_clock *ptp_clock;
153};
154
155/* globals */
156
157enum {
158 CALIBRATE_GPIO,
159 PEROUT_GPIO,
160 EXTTS0_GPIO,
161 EXTTS1_GPIO,
162 EXTTS2_GPIO,
163 EXTTS3_GPIO,
164 EXTTS4_GPIO,
165 EXTTS5_GPIO,
166 GPIO_TABLE_SIZE
167};
168
169static int chosen_phy = -1;
170static ushort gpio_tab[GPIO_TABLE_SIZE] = {
171 1, 2, 3, 4, 8, 9, 10, 11
172};
173
174module_param(chosen_phy, int, 0444);
175module_param_array(gpio_tab, ushort, NULL, 0444);
176
177MODULE_PARM_DESC(chosen_phy, \
178 "The address of the PHY to use for the ancillary clock features");
179MODULE_PARM_DESC(gpio_tab, \
180 "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6");
181
182static void dp83640_gpio_defaults(struct ptp_pin_desc *pd)
183{
184 int i, index;
185
186 for (i = 0; i < DP83640_N_PINS; i++) {
187 snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i);
188 pd[i].index = i;
189 }
190
191 for (i = 0; i < GPIO_TABLE_SIZE; i++) {
192 if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) {
193 pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]);
194 return;
195 }
196 }
197
198 index = gpio_tab[CALIBRATE_GPIO] - 1;
199 pd[index].func = PTP_PF_PHYSYNC;
200 pd[index].chan = 0;
201
202 index = gpio_tab[PEROUT_GPIO] - 1;
203 pd[index].func = PTP_PF_PEROUT;
204 pd[index].chan = 0;
205
206 for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) {
207 index = gpio_tab[i] - 1;
208 pd[index].func = PTP_PF_EXTTS;
209 pd[index].chan = i - EXTTS0_GPIO;
210 }
211}
212
213/* a list of clocks and a mutex to protect it */
214static LIST_HEAD(phyter_clocks);
215static DEFINE_MUTEX(phyter_clocks_lock);
216
217static void rx_timestamp_work(struct work_struct *work);
218
219/* extended register access functions */
220
221#define BROADCAST_ADDR 31
222
223static inline int broadcast_write(struct phy_device *phydev, u32 regnum,
224 u16 val)
225{
226 return mdiobus_write(phydev->mdio.bus, BROADCAST_ADDR, regnum, val);
227}
228
229/* Caller must hold extreg_lock. */
230static int ext_read(struct phy_device *phydev, int page, u32 regnum)
231{
232 struct dp83640_private *dp83640 = phydev->priv;
233 int val;
234
235 if (dp83640->clock->page != page) {
236 broadcast_write(phydev, PAGESEL, page);
237 dp83640->clock->page = page;
238 }
239 val = phy_read(phydev, regnum);
240
241 return val;
242}
243
244/* Caller must hold extreg_lock. */
245static void ext_write(int broadcast, struct phy_device *phydev,
246 int page, u32 regnum, u16 val)
247{
248 struct dp83640_private *dp83640 = phydev->priv;
249
250 if (dp83640->clock->page != page) {
251 broadcast_write(phydev, PAGESEL, page);
252 dp83640->clock->page = page;
253 }
254 if (broadcast)
255 broadcast_write(phydev, regnum, val);
256 else
257 phy_write(phydev, regnum, val);
258}
259
260/* Caller must hold extreg_lock. */
261static int tdr_write(int bc, struct phy_device *dev,
262 const struct timespec64 *ts, u16 cmd)
263{
264 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */
265 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */
266 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */
267 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/
268
269 ext_write(bc, dev, PAGE4, PTP_CTL, cmd);
270
271 return 0;
272}
273
274/* convert phy timestamps into driver timestamps */
275
276static void phy2rxts(struct phy_rxts *p, struct rxts *rxts)
277{
278 u32 sec;
279
280 sec = p->sec_lo;
281 sec |= p->sec_hi << 16;
282
283 rxts->ns = p->ns_lo;
284 rxts->ns |= (p->ns_hi & 0x3fff) << 16;
285 rxts->ns += ((u64)sec) * 1000000000ULL;
286 rxts->seqid = p->seqid;
287 rxts->msgtype = (p->msgtype >> 12) & 0xf;
288 rxts->hash = p->msgtype & 0x0fff;
289 rxts->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
290}
291
292static u64 phy2txts(struct phy_txts *p)
293{
294 u64 ns;
295 u32 sec;
296
297 sec = p->sec_lo;
298 sec |= p->sec_hi << 16;
299
300 ns = p->ns_lo;
301 ns |= (p->ns_hi & 0x3fff) << 16;
302 ns += ((u64)sec) * 1000000000ULL;
303
304 return ns;
305}
306
307static int periodic_output(struct dp83640_clock *clock,
308 struct ptp_clock_request *clkreq, bool on,
309 int trigger)
310{
311 struct dp83640_private *dp83640 = clock->chosen;
312 struct phy_device *phydev = dp83640->phydev;
313 u32 sec, nsec, pwidth;
314 u16 gpio, ptp_trig, val;
315
316 if (on) {
317 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT,
318 trigger);
319 if (gpio < 1)
320 return -EINVAL;
321 } else {
322 gpio = 0;
323 }
324
325 ptp_trig = TRIG_WR |
326 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT |
327 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT |
328 TRIG_PER |
329 TRIG_PULSE;
330
331 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
332
333 if (!on) {
334 val |= TRIG_DIS;
335 mutex_lock(&clock->extreg_lock);
336 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
337 ext_write(0, phydev, PAGE4, PTP_CTL, val);
338 mutex_unlock(&clock->extreg_lock);
339 return 0;
340 }
341
342 sec = clkreq->perout.start.sec;
343 nsec = clkreq->perout.start.nsec;
344 pwidth = clkreq->perout.period.sec * 1000000000UL;
345 pwidth += clkreq->perout.period.nsec;
346 pwidth /= 2;
347
348 mutex_lock(&clock->extreg_lock);
349
350 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
351
352 /*load trigger*/
353 val |= TRIG_LOAD;
354 ext_write(0, phydev, PAGE4, PTP_CTL, val);
355 ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff); /* ns[15:0] */
356 ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */
357 ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */
358 ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */
359 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */
360 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); /* ns[31:16] */
361 /* Triggers 0 and 1 has programmable pulsewidth2 */
362 if (trigger < 2) {
363 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff);
364 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16);
365 }
366
367 /*enable trigger*/
368 val &= ~TRIG_LOAD;
369 val |= TRIG_EN;
370 ext_write(0, phydev, PAGE4, PTP_CTL, val);
371
372 mutex_unlock(&clock->extreg_lock);
373 return 0;
374}
375
376/* ptp clock methods */
377
378static int ptp_dp83640_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
379{
380 struct dp83640_clock *clock =
381 container_of(ptp, struct dp83640_clock, caps);
382 struct phy_device *phydev = clock->chosen->phydev;
383 u64 rate;
384 int neg_adj = 0;
385 u16 hi, lo;
386
387 if (scaled_ppm < 0) {
388 neg_adj = 1;
389 scaled_ppm = -scaled_ppm;
390 }
391 rate = scaled_ppm;
392 rate <<= 13;
393 rate = div_u64(rate, 15625);
394
395 hi = (rate >> 16) & PTP_RATE_HI_MASK;
396 if (neg_adj)
397 hi |= PTP_RATE_DIR;
398
399 lo = rate & 0xffff;
400
401 mutex_lock(&clock->extreg_lock);
402
403 ext_write(1, phydev, PAGE4, PTP_RATEH, hi);
404 ext_write(1, phydev, PAGE4, PTP_RATEL, lo);
405
406 mutex_unlock(&clock->extreg_lock);
407
408 return 0;
409}
410
411static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta)
412{
413 struct dp83640_clock *clock =
414 container_of(ptp, struct dp83640_clock, caps);
415 struct phy_device *phydev = clock->chosen->phydev;
416 struct timespec64 ts;
417 int err;
418
419 delta += ADJTIME_FIX;
420
421 ts = ns_to_timespec64(delta);
422
423 mutex_lock(&clock->extreg_lock);
424
425 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);
426
427 mutex_unlock(&clock->extreg_lock);
428
429 return err;
430}
431
432static int ptp_dp83640_gettime(struct ptp_clock_info *ptp,
433 struct timespec64 *ts)
434{
435 struct dp83640_clock *clock =
436 container_of(ptp, struct dp83640_clock, caps);
437 struct phy_device *phydev = clock->chosen->phydev;
438 unsigned int val[4];
439
440 mutex_lock(&clock->extreg_lock);
441
442 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
443
444 val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */
445 val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */
446 val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */
447 val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */
448
449 mutex_unlock(&clock->extreg_lock);
450
451 ts->tv_nsec = val[0] | (val[1] << 16);
452 ts->tv_sec = val[2] | (val[3] << 16);
453
454 return 0;
455}
456
457static int ptp_dp83640_settime(struct ptp_clock_info *ptp,
458 const struct timespec64 *ts)
459{
460 struct dp83640_clock *clock =
461 container_of(ptp, struct dp83640_clock, caps);
462 struct phy_device *phydev = clock->chosen->phydev;
463 int err;
464
465 mutex_lock(&clock->extreg_lock);
466
467 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);
468
469 mutex_unlock(&clock->extreg_lock);
470
471 return err;
472}
473
474static int ptp_dp83640_enable(struct ptp_clock_info *ptp,
475 struct ptp_clock_request *rq, int on)
476{
477 struct dp83640_clock *clock =
478 container_of(ptp, struct dp83640_clock, caps);
479 struct phy_device *phydev = clock->chosen->phydev;
480 unsigned int index;
481 u16 evnt, event_num, gpio_num;
482
483 switch (rq->type) {
484 case PTP_CLK_REQ_EXTTS:
485 index = rq->extts.index;
486 if (index >= N_EXT_TS)
487 return -EINVAL;
488 event_num = EXT_EVENT + index;
489 evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
490 if (on) {
491 gpio_num = 1 + ptp_find_pin(clock->ptp_clock,
492 PTP_PF_EXTTS, index);
493 if (gpio_num < 1)
494 return -EINVAL;
495 evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
496 if (rq->extts.flags & PTP_FALLING_EDGE)
497 evnt |= EVNT_FALL;
498 else
499 evnt |= EVNT_RISE;
500 }
501 mutex_lock(&clock->extreg_lock);
502 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt);
503 mutex_unlock(&clock->extreg_lock);
504 return 0;
505
506 case PTP_CLK_REQ_PEROUT:
507 if (rq->perout.index >= N_PER_OUT)
508 return -EINVAL;
509 return periodic_output(clock, rq, on, rq->perout.index);
510
511 default:
512 break;
513 }
514
515 return -EOPNOTSUPP;
516}
517
518static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin,
519 enum ptp_pin_function func, unsigned int chan)
520{
521 struct dp83640_clock *clock =
522 container_of(ptp, struct dp83640_clock, caps);
523
524 if (clock->caps.pin_config[pin].func == PTP_PF_PHYSYNC &&
525 !list_empty(&clock->phylist))
526 return 1;
527
528 if (func == PTP_PF_PHYSYNC)
529 return 1;
530
531 return 0;
532}
533
534static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 };
535static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F };
536
537static void enable_status_frames(struct phy_device *phydev, bool on)
538{
539 struct dp83640_private *dp83640 = phydev->priv;
540 struct dp83640_clock *clock = dp83640->clock;
541 u16 cfg0 = 0, ver;
542
543 if (on)
544 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG;
545
546 ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT;
547
548 mutex_lock(&clock->extreg_lock);
549
550 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0);
551 ext_write(0, phydev, PAGE6, PSF_CFG1, ver);
552
553 mutex_unlock(&clock->extreg_lock);
554
555 if (!phydev->attached_dev) {
556 pr_warn("expected to find an attached netdevice\n");
557 return;
558 }
559
560 if (on) {
561 if (dev_mc_add(phydev->attached_dev, status_frame_dst))
562 pr_warn("failed to add mc address\n");
563 } else {
564 if (dev_mc_del(phydev->attached_dev, status_frame_dst))
565 pr_warn("failed to delete mc address\n");
566 }
567}
568
569static bool is_status_frame(struct sk_buff *skb, int type)
570{
571 struct ethhdr *h = eth_hdr(skb);
572
573 if (PTP_CLASS_V2_L2 == type &&
574 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src)))
575 return true;
576 else
577 return false;
578}
579
580static int expired(struct rxts *rxts)
581{
582 return time_after(jiffies, rxts->tmo);
583}
584
585/* Caller must hold rx_lock. */
586static void prune_rx_ts(struct dp83640_private *dp83640)
587{
588 struct list_head *this, *next;
589 struct rxts *rxts;
590
591 list_for_each_safe(this, next, &dp83640->rxts) {
592 rxts = list_entry(this, struct rxts, list);
593 if (expired(rxts)) {
594 list_del_init(&rxts->list);
595 list_add(&rxts->list, &dp83640->rxpool);
596 }
597 }
598}
599
600/* synchronize the phyters so they act as one clock */
601
602static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
603{
604 int val;
605 phy_write(phydev, PAGESEL, 0);
606 val = phy_read(phydev, PHYCR2);
607 if (on)
608 val |= BC_WRITE;
609 else
610 val &= ~BC_WRITE;
611 phy_write(phydev, PHYCR2, val);
612 phy_write(phydev, PAGESEL, init_page);
613}
614
615static void recalibrate(struct dp83640_clock *clock)
616{
617 s64 now, diff;
618 struct phy_txts event_ts;
619 struct timespec64 ts;
620 struct list_head *this;
621 struct dp83640_private *tmp;
622 struct phy_device *master = clock->chosen->phydev;
623 u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val;
624
625 trigger = CAL_TRIGGER;
626 cal_gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PHYSYNC, 0);
627 if (cal_gpio < 1) {
628 pr_err("PHY calibration pin not available - PHY is not calibrated.");
629 return;
630 }
631
632 mutex_lock(&clock->extreg_lock);
633
634 /*
635 * enable broadcast, disable status frames, enable ptp clock
636 */
637 list_for_each(this, &clock->phylist) {
638 tmp = list_entry(this, struct dp83640_private, list);
639 enable_broadcast(tmp->phydev, clock->page, 1);
640 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);
641 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);
642 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);
643 }
644 enable_broadcast(master, clock->page, 1);
645 cfg0 = ext_read(master, PAGE5, PSF_CFG0);
646 ext_write(0, master, PAGE5, PSF_CFG0, 0);
647 ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE);
648
649 /*
650 * enable an event timestamp
651 */
652 evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE;
653 evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
654 evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
655
656 list_for_each(this, &clock->phylist) {
657 tmp = list_entry(this, struct dp83640_private, list);
658 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
659 }
660 ext_write(0, master, PAGE5, PTP_EVNT, evnt);
661
662 /*
663 * configure a trigger
664 */
665 ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE;
666 ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT;
667 ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT;
668 ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig);
669
670 /* load trigger */
671 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
672 val |= TRIG_LOAD;
673 ext_write(0, master, PAGE4, PTP_CTL, val);
674
675 /* enable trigger */
676 val &= ~TRIG_LOAD;
677 val |= TRIG_EN;
678 ext_write(0, master, PAGE4, PTP_CTL, val);
679
680 /* disable trigger */
681 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
682 val |= TRIG_DIS;
683 ext_write(0, master, PAGE4, PTP_CTL, val);
684
685 /*
686 * read out and correct offsets
687 */
688 val = ext_read(master, PAGE4, PTP_STS);
689 pr_info("master PTP_STS 0x%04hx\n", val);
690 val = ext_read(master, PAGE4, PTP_ESTS);
691 pr_info("master PTP_ESTS 0x%04hx\n", val);
692 event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA);
693 event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA);
694 event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA);
695 event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA);
696 now = phy2txts(&event_ts);
697
698 list_for_each(this, &clock->phylist) {
699 tmp = list_entry(this, struct dp83640_private, list);
700 val = ext_read(tmp->phydev, PAGE4, PTP_STS);
701 pr_info("slave PTP_STS 0x%04hx\n", val);
702 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);
703 pr_info("slave PTP_ESTS 0x%04hx\n", val);
704 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
705 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
706 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
707 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
708 diff = now - (s64) phy2txts(&event_ts);
709 pr_info("slave offset %lld nanoseconds\n", diff);
710 diff += ADJTIME_FIX;
711 ts = ns_to_timespec64(diff);
712 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);
713 }
714
715 /*
716 * restore status frames
717 */
718 list_for_each(this, &clock->phylist) {
719 tmp = list_entry(this, struct dp83640_private, list);
720 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);
721 }
722 ext_write(0, master, PAGE5, PSF_CFG0, cfg0);
723
724 mutex_unlock(&clock->extreg_lock);
725}
726
727/* time stamping methods */
728
729static inline u16 exts_chan_to_edata(int ch)
730{
731 return 1 << ((ch + EXT_EVENT) * 2);
732}
733
734static int decode_evnt(struct dp83640_private *dp83640,
735 void *data, int len, u16 ests)
736{
737 struct phy_txts *phy_txts;
738 struct ptp_clock_event event;
739 int i, parsed;
740 int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK;
741 u16 ext_status = 0;
742
743 /* calculate length of the event timestamp status message */
744 if (ests & MULT_EVNT)
745 parsed = (words + 2) * sizeof(u16);
746 else
747 parsed = (words + 1) * sizeof(u16);
748
749 /* check if enough data is available */
750 if (len < parsed)
751 return len;
752
753 if (ests & MULT_EVNT) {
754 ext_status = *(u16 *) data;
755 data += sizeof(ext_status);
756 }
757
758 phy_txts = data;
759
760 switch (words) { /* fall through in every case */
761 case 3:
762 dp83640->edata.sec_hi = phy_txts->sec_hi;
763 case 2:
764 dp83640->edata.sec_lo = phy_txts->sec_lo;
765 case 1:
766 dp83640->edata.ns_hi = phy_txts->ns_hi;
767 case 0:
768 dp83640->edata.ns_lo = phy_txts->ns_lo;
769 }
770
771 if (!ext_status) {
772 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT;
773 ext_status = exts_chan_to_edata(i);
774 }
775
776 event.type = PTP_CLOCK_EXTTS;
777 event.timestamp = phy2txts(&dp83640->edata);
778
779 /* Compensate for input path and synchronization delays */
780 event.timestamp -= 35;
781
782 for (i = 0; i < N_EXT_TS; i++) {
783 if (ext_status & exts_chan_to_edata(i)) {
784 event.index = i;
785 ptp_clock_event(dp83640->clock->ptp_clock, &event);
786 }
787 }
788
789 return parsed;
790}
791
792#define DP83640_PACKET_HASH_OFFSET 20
793#define DP83640_PACKET_HASH_LEN 10
794
795static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
796{
797 u16 *seqid, hash;
798 unsigned int offset = 0;
799 u8 *msgtype, *data = skb_mac_header(skb);
800
801 /* check sequenceID, messageType, 12 bit hash of offset 20-29 */
802
803 if (type & PTP_CLASS_VLAN)
804 offset += VLAN_HLEN;
805
806 switch (type & PTP_CLASS_PMASK) {
807 case PTP_CLASS_IPV4:
808 offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN;
809 break;
810 case PTP_CLASS_IPV6:
811 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN;
812 break;
813 case PTP_CLASS_L2:
814 offset += ETH_HLEN;
815 break;
816 default:
817 return 0;
818 }
819
820 if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid))
821 return 0;
822
823 if (unlikely(type & PTP_CLASS_V1))
824 msgtype = data + offset + OFF_PTP_CONTROL;
825 else
826 msgtype = data + offset;
827 if (rxts->msgtype != (*msgtype & 0xf))
828 return 0;
829
830 seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
831 if (rxts->seqid != ntohs(*seqid))
832 return 0;
833
834 hash = ether_crc(DP83640_PACKET_HASH_LEN,
835 data + offset + DP83640_PACKET_HASH_OFFSET) >> 20;
836 if (rxts->hash != hash)
837 return 0;
838
839 return 1;
840}
841
842static void decode_rxts(struct dp83640_private *dp83640,
843 struct phy_rxts *phy_rxts)
844{
845 struct rxts *rxts;
846 struct skb_shared_hwtstamps *shhwtstamps = NULL;
847 struct sk_buff *skb;
848 unsigned long flags;
849 u8 overflow;
850
851 overflow = (phy_rxts->ns_hi >> 14) & 0x3;
852 if (overflow)
853 pr_debug("rx timestamp queue overflow, count %d\n", overflow);
854
855 spin_lock_irqsave(&dp83640->rx_lock, flags);
856
857 prune_rx_ts(dp83640);
858
859 if (list_empty(&dp83640->rxpool)) {
860 pr_debug("rx timestamp pool is empty\n");
861 goto out;
862 }
863 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);
864 list_del_init(&rxts->list);
865 phy2rxts(phy_rxts, rxts);
866
867 spin_lock(&dp83640->rx_queue.lock);
868 skb_queue_walk(&dp83640->rx_queue, skb) {
869 struct dp83640_skb_info *skb_info;
870
871 skb_info = (struct dp83640_skb_info *)skb->cb;
872 if (match(skb, skb_info->ptp_type, rxts)) {
873 __skb_unlink(skb, &dp83640->rx_queue);
874 shhwtstamps = skb_hwtstamps(skb);
875 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
876 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
877 list_add(&rxts->list, &dp83640->rxpool);
878 break;
879 }
880 }
881 spin_unlock(&dp83640->rx_queue.lock);
882
883 if (!shhwtstamps)
884 list_add_tail(&rxts->list, &dp83640->rxts);
885out:
886 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
887
888 if (shhwtstamps)
889 netif_rx_ni(skb);
890}
891
892static void decode_txts(struct dp83640_private *dp83640,
893 struct phy_txts *phy_txts)
894{
895 struct skb_shared_hwtstamps shhwtstamps;
896 struct sk_buff *skb;
897 u64 ns;
898 u8 overflow;
899
900 /* We must already have the skb that triggered this. */
901
902 skb = skb_dequeue(&dp83640->tx_queue);
903
904 if (!skb) {
905 pr_debug("have timestamp but tx_queue empty\n");
906 return;
907 }
908
909 overflow = (phy_txts->ns_hi >> 14) & 0x3;
910 if (overflow) {
911 pr_debug("tx timestamp queue overflow, count %d\n", overflow);
912 while (skb) {
913 kfree_skb(skb);
914 skb = skb_dequeue(&dp83640->tx_queue);
915 }
916 return;
917 }
918
919 ns = phy2txts(phy_txts);
920 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
921 shhwtstamps.hwtstamp = ns_to_ktime(ns);
922 skb_complete_tx_timestamp(skb, &shhwtstamps);
923}
924
925static void decode_status_frame(struct dp83640_private *dp83640,
926 struct sk_buff *skb)
927{
928 struct phy_rxts *phy_rxts;
929 struct phy_txts *phy_txts;
930 u8 *ptr;
931 int len, size;
932 u16 ests, type;
933
934 ptr = skb->data + 2;
935
936 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) {
937
938 type = *(u16 *)ptr;
939 ests = type & 0x0fff;
940 type = type & 0xf000;
941 len -= sizeof(type);
942 ptr += sizeof(type);
943
944 if (PSF_RX == type && len >= sizeof(*phy_rxts)) {
945
946 phy_rxts = (struct phy_rxts *) ptr;
947 decode_rxts(dp83640, phy_rxts);
948 size = sizeof(*phy_rxts);
949
950 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) {
951
952 phy_txts = (struct phy_txts *) ptr;
953 decode_txts(dp83640, phy_txts);
954 size = sizeof(*phy_txts);
955
956 } else if (PSF_EVNT == type) {
957
958 size = decode_evnt(dp83640, ptr, len, ests);
959
960 } else {
961 size = 0;
962 break;
963 }
964 ptr += size;
965 }
966}
967
968static int is_sync(struct sk_buff *skb, int type)
969{
970 u8 *data = skb->data, *msgtype;
971 unsigned int offset = 0;
972
973 if (type & PTP_CLASS_VLAN)
974 offset += VLAN_HLEN;
975
976 switch (type & PTP_CLASS_PMASK) {
977 case PTP_CLASS_IPV4:
978 offset += ETH_HLEN + IPV4_HLEN(data + offset) + UDP_HLEN;
979 break;
980 case PTP_CLASS_IPV6:
981 offset += ETH_HLEN + IP6_HLEN + UDP_HLEN;
982 break;
983 case PTP_CLASS_L2:
984 offset += ETH_HLEN;
985 break;
986 default:
987 return 0;
988 }
989
990 if (type & PTP_CLASS_V1)
991 offset += OFF_PTP_CONTROL;
992
993 if (skb->len < offset + 1)
994 return 0;
995
996 msgtype = data + offset;
997
998 return (*msgtype & 0xf) == 0;
999}
1000
1001static void dp83640_free_clocks(void)
1002{
1003 struct dp83640_clock *clock;
1004 struct list_head *this, *next;
1005
1006 mutex_lock(&phyter_clocks_lock);
1007
1008 list_for_each_safe(this, next, &phyter_clocks) {
1009 clock = list_entry(this, struct dp83640_clock, list);
1010 if (!list_empty(&clock->phylist)) {
1011 pr_warn("phy list non-empty while unloading\n");
1012 BUG();
1013 }
1014 list_del(&clock->list);
1015 mutex_destroy(&clock->extreg_lock);
1016 mutex_destroy(&clock->clock_lock);
1017 put_device(&clock->bus->dev);
1018 kfree(clock->caps.pin_config);
1019 kfree(clock);
1020 }
1021
1022 mutex_unlock(&phyter_clocks_lock);
1023}
1024
1025static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus)
1026{
1027 INIT_LIST_HEAD(&clock->list);
1028 clock->bus = bus;
1029 mutex_init(&clock->extreg_lock);
1030 mutex_init(&clock->clock_lock);
1031 INIT_LIST_HEAD(&clock->phylist);
1032 clock->caps.owner = THIS_MODULE;
1033 sprintf(clock->caps.name, "dp83640 timer");
1034 clock->caps.max_adj = 1953124;
1035 clock->caps.n_alarm = 0;
1036 clock->caps.n_ext_ts = N_EXT_TS;
1037 clock->caps.n_per_out = N_PER_OUT;
1038 clock->caps.n_pins = DP83640_N_PINS;
1039 clock->caps.pps = 0;
1040 clock->caps.adjfine = ptp_dp83640_adjfine;
1041 clock->caps.adjtime = ptp_dp83640_adjtime;
1042 clock->caps.gettime64 = ptp_dp83640_gettime;
1043 clock->caps.settime64 = ptp_dp83640_settime;
1044 clock->caps.enable = ptp_dp83640_enable;
1045 clock->caps.verify = ptp_dp83640_verify;
1046 /*
1047 * Convert the module param defaults into a dynamic pin configuration.
1048 */
1049 dp83640_gpio_defaults(clock->caps.pin_config);
1050 /*
1051 * Get a reference to this bus instance.
1052 */
1053 get_device(&bus->dev);
1054}
1055
1056static int choose_this_phy(struct dp83640_clock *clock,
1057 struct phy_device *phydev)
1058{
1059 if (chosen_phy == -1 && !clock->chosen)
1060 return 1;
1061
1062 if (chosen_phy == phydev->mdio.addr)
1063 return 1;
1064
1065 return 0;
1066}
1067
1068static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock)
1069{
1070 if (clock)
1071 mutex_lock(&clock->clock_lock);
1072 return clock;
1073}
1074
1075/*
1076 * Look up and lock a clock by bus instance.
1077 * If there is no clock for this bus, then create it first.
1078 */
1079static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus)
1080{
1081 struct dp83640_clock *clock = NULL, *tmp;
1082 struct list_head *this;
1083
1084 mutex_lock(&phyter_clocks_lock);
1085
1086 list_for_each(this, &phyter_clocks) {
1087 tmp = list_entry(this, struct dp83640_clock, list);
1088 if (tmp->bus == bus) {
1089 clock = tmp;
1090 break;
1091 }
1092 }
1093 if (clock)
1094 goto out;
1095
1096 clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL);
1097 if (!clock)
1098 goto out;
1099
1100 clock->caps.pin_config = kzalloc(sizeof(struct ptp_pin_desc) *
1101 DP83640_N_PINS, GFP_KERNEL);
1102 if (!clock->caps.pin_config) {
1103 kfree(clock);
1104 clock = NULL;
1105 goto out;
1106 }
1107 dp83640_clock_init(clock, bus);
1108 list_add_tail(&phyter_clocks, &clock->list);
1109out:
1110 mutex_unlock(&phyter_clocks_lock);
1111
1112 return dp83640_clock_get(clock);
1113}
1114
1115static void dp83640_clock_put(struct dp83640_clock *clock)
1116{
1117 mutex_unlock(&clock->clock_lock);
1118}
1119
1120static int dp83640_probe(struct phy_device *phydev)
1121{
1122 struct dp83640_clock *clock;
1123 struct dp83640_private *dp83640;
1124 int err = -ENOMEM, i;
1125
1126 if (phydev->mdio.addr == BROADCAST_ADDR)
1127 return 0;
1128
1129 clock = dp83640_clock_get_bus(phydev->mdio.bus);
1130 if (!clock)
1131 goto no_clock;
1132
1133 dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL);
1134 if (!dp83640)
1135 goto no_memory;
1136
1137 dp83640->phydev = phydev;
1138 INIT_DELAYED_WORK(&dp83640->ts_work, rx_timestamp_work);
1139
1140 INIT_LIST_HEAD(&dp83640->rxts);
1141 INIT_LIST_HEAD(&dp83640->rxpool);
1142 for (i = 0; i < MAX_RXTS; i++)
1143 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool);
1144
1145 phydev->priv = dp83640;
1146
1147 spin_lock_init(&dp83640->rx_lock);
1148 skb_queue_head_init(&dp83640->rx_queue);
1149 skb_queue_head_init(&dp83640->tx_queue);
1150
1151 dp83640->clock = clock;
1152
1153 if (choose_this_phy(clock, phydev)) {
1154 clock->chosen = dp83640;
1155 clock->ptp_clock = ptp_clock_register(&clock->caps,
1156 &phydev->mdio.dev);
1157 if (IS_ERR(clock->ptp_clock)) {
1158 err = PTR_ERR(clock->ptp_clock);
1159 goto no_register;
1160 }
1161 } else
1162 list_add_tail(&dp83640->list, &clock->phylist);
1163
1164 dp83640_clock_put(clock);
1165 return 0;
1166
1167no_register:
1168 clock->chosen = NULL;
1169 kfree(dp83640);
1170no_memory:
1171 dp83640_clock_put(clock);
1172no_clock:
1173 return err;
1174}
1175
1176static void dp83640_remove(struct phy_device *phydev)
1177{
1178 struct dp83640_clock *clock;
1179 struct list_head *this, *next;
1180 struct dp83640_private *tmp, *dp83640 = phydev->priv;
1181
1182 if (phydev->mdio.addr == BROADCAST_ADDR)
1183 return;
1184
1185 enable_status_frames(phydev, false);
1186 cancel_delayed_work_sync(&dp83640->ts_work);
1187
1188 skb_queue_purge(&dp83640->rx_queue);
1189 skb_queue_purge(&dp83640->tx_queue);
1190
1191 clock = dp83640_clock_get(dp83640->clock);
1192
1193 if (dp83640 == clock->chosen) {
1194 ptp_clock_unregister(clock->ptp_clock);
1195 clock->chosen = NULL;
1196 } else {
1197 list_for_each_safe(this, next, &clock->phylist) {
1198 tmp = list_entry(this, struct dp83640_private, list);
1199 if (tmp == dp83640) {
1200 list_del_init(&tmp->list);
1201 break;
1202 }
1203 }
1204 }
1205
1206 dp83640_clock_put(clock);
1207 kfree(dp83640);
1208}
1209
1210static int dp83640_soft_reset(struct phy_device *phydev)
1211{
1212 int ret;
1213
1214 ret = genphy_soft_reset(phydev);
1215 if (ret < 0)
1216 return ret;
1217
1218 /* From DP83640 datasheet: "Software driver code must wait 3 us
1219 * following a software reset before allowing further serial MII
1220 * operations with the DP83640."
1221 */
1222 udelay(10); /* Taking udelay inaccuracy into account */
1223
1224 return 0;
1225}
1226
1227static int dp83640_config_init(struct phy_device *phydev)
1228{
1229 struct dp83640_private *dp83640 = phydev->priv;
1230 struct dp83640_clock *clock = dp83640->clock;
1231
1232 if (clock->chosen && !list_empty(&clock->phylist))
1233 recalibrate(clock);
1234 else {
1235 mutex_lock(&clock->extreg_lock);
1236 enable_broadcast(phydev, clock->page, 1);
1237 mutex_unlock(&clock->extreg_lock);
1238 }
1239
1240 enable_status_frames(phydev, true);
1241
1242 mutex_lock(&clock->extreg_lock);
1243 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);
1244 mutex_unlock(&clock->extreg_lock);
1245
1246 return 0;
1247}
1248
1249static int dp83640_ack_interrupt(struct phy_device *phydev)
1250{
1251 int err = phy_read(phydev, MII_DP83640_MISR);
1252
1253 if (err < 0)
1254 return err;
1255
1256 return 0;
1257}
1258
1259static int dp83640_config_intr(struct phy_device *phydev)
1260{
1261 int micr;
1262 int misr;
1263 int err;
1264
1265 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1266 misr = phy_read(phydev, MII_DP83640_MISR);
1267 if (misr < 0)
1268 return misr;
1269 misr |=
1270 (MII_DP83640_MISR_ANC_INT_EN |
1271 MII_DP83640_MISR_DUP_INT_EN |
1272 MII_DP83640_MISR_SPD_INT_EN |
1273 MII_DP83640_MISR_LINK_INT_EN);
1274 err = phy_write(phydev, MII_DP83640_MISR, misr);
1275 if (err < 0)
1276 return err;
1277
1278 micr = phy_read(phydev, MII_DP83640_MICR);
1279 if (micr < 0)
1280 return micr;
1281 micr |=
1282 (MII_DP83640_MICR_OE |
1283 MII_DP83640_MICR_IE);
1284 return phy_write(phydev, MII_DP83640_MICR, micr);
1285 } else {
1286 micr = phy_read(phydev, MII_DP83640_MICR);
1287 if (micr < 0)
1288 return micr;
1289 micr &=
1290 ~(MII_DP83640_MICR_OE |
1291 MII_DP83640_MICR_IE);
1292 err = phy_write(phydev, MII_DP83640_MICR, micr);
1293 if (err < 0)
1294 return err;
1295
1296 misr = phy_read(phydev, MII_DP83640_MISR);
1297 if (misr < 0)
1298 return misr;
1299 misr &=
1300 ~(MII_DP83640_MISR_ANC_INT_EN |
1301 MII_DP83640_MISR_DUP_INT_EN |
1302 MII_DP83640_MISR_SPD_INT_EN |
1303 MII_DP83640_MISR_LINK_INT_EN);
1304 return phy_write(phydev, MII_DP83640_MISR, misr);
1305 }
1306}
1307
1308static int dp83640_hwtstamp(struct phy_device *phydev, struct ifreq *ifr)
1309{
1310 struct dp83640_private *dp83640 = phydev->priv;
1311 struct hwtstamp_config cfg;
1312 u16 txcfg0, rxcfg0;
1313
1314 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1315 return -EFAULT;
1316
1317 if (cfg.flags) /* reserved for future extensions */
1318 return -EINVAL;
1319
1320 if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC)
1321 return -ERANGE;
1322
1323 dp83640->hwts_tx_en = cfg.tx_type;
1324
1325 switch (cfg.rx_filter) {
1326 case HWTSTAMP_FILTER_NONE:
1327 dp83640->hwts_rx_en = 0;
1328 dp83640->layer = 0;
1329 dp83640->version = 0;
1330 break;
1331 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1332 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1333 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1334 dp83640->hwts_rx_en = 1;
1335 dp83640->layer = PTP_CLASS_L4;
1336 dp83640->version = PTP_CLASS_V1;
1337 break;
1338 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1339 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1340 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1341 dp83640->hwts_rx_en = 1;
1342 dp83640->layer = PTP_CLASS_L4;
1343 dp83640->version = PTP_CLASS_V2;
1344 break;
1345 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1346 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1347 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1348 dp83640->hwts_rx_en = 1;
1349 dp83640->layer = PTP_CLASS_L2;
1350 dp83640->version = PTP_CLASS_V2;
1351 break;
1352 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1353 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1354 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1355 dp83640->hwts_rx_en = 1;
1356 dp83640->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
1357 dp83640->version = PTP_CLASS_V2;
1358 break;
1359 default:
1360 return -ERANGE;
1361 }
1362
1363 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1364 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1365
1366 if (dp83640->layer & PTP_CLASS_L2) {
1367 txcfg0 |= TX_L2_EN;
1368 rxcfg0 |= RX_L2_EN;
1369 }
1370 if (dp83640->layer & PTP_CLASS_L4) {
1371 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN;
1372 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN;
1373 }
1374
1375 if (dp83640->hwts_tx_en)
1376 txcfg0 |= TX_TS_EN;
1377
1378 if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC)
1379 txcfg0 |= SYNC_1STEP | CHK_1STEP;
1380
1381 if (dp83640->hwts_rx_en)
1382 rxcfg0 |= RX_TS_EN;
1383
1384 mutex_lock(&dp83640->clock->extreg_lock);
1385
1386 ext_write(0, phydev, PAGE5, PTP_TXCFG0, txcfg0);
1387 ext_write(0, phydev, PAGE5, PTP_RXCFG0, rxcfg0);
1388
1389 mutex_unlock(&dp83640->clock->extreg_lock);
1390
1391 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1392}
1393
1394static void rx_timestamp_work(struct work_struct *work)
1395{
1396 struct dp83640_private *dp83640 =
1397 container_of(work, struct dp83640_private, ts_work.work);
1398 struct sk_buff *skb;
1399
1400 /* Deliver expired packets. */
1401 while ((skb = skb_dequeue(&dp83640->rx_queue))) {
1402 struct dp83640_skb_info *skb_info;
1403
1404 skb_info = (struct dp83640_skb_info *)skb->cb;
1405 if (!time_after(jiffies, skb_info->tmo)) {
1406 skb_queue_head(&dp83640->rx_queue, skb);
1407 break;
1408 }
1409
1410 netif_rx_ni(skb);
1411 }
1412
1413 if (!skb_queue_empty(&dp83640->rx_queue))
1414 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
1415}
1416
1417static bool dp83640_rxtstamp(struct phy_device *phydev,
1418 struct sk_buff *skb, int type)
1419{
1420 struct dp83640_private *dp83640 = phydev->priv;
1421 struct dp83640_skb_info *skb_info = (struct dp83640_skb_info *)skb->cb;
1422 struct list_head *this, *next;
1423 struct rxts *rxts;
1424 struct skb_shared_hwtstamps *shhwtstamps = NULL;
1425 unsigned long flags;
1426
1427 if (is_status_frame(skb, type)) {
1428 decode_status_frame(dp83640, skb);
1429 kfree_skb(skb);
1430 return true;
1431 }
1432
1433 if (!dp83640->hwts_rx_en)
1434 return false;
1435
1436 if ((type & dp83640->version) == 0 || (type & dp83640->layer) == 0)
1437 return false;
1438
1439 spin_lock_irqsave(&dp83640->rx_lock, flags);
1440 prune_rx_ts(dp83640);
1441 list_for_each_safe(this, next, &dp83640->rxts) {
1442 rxts = list_entry(this, struct rxts, list);
1443 if (match(skb, type, rxts)) {
1444 shhwtstamps = skb_hwtstamps(skb);
1445 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
1446 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
1447 list_del_init(&rxts->list);
1448 list_add(&rxts->list, &dp83640->rxpool);
1449 break;
1450 }
1451 }
1452 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
1453
1454 if (!shhwtstamps) {
1455 skb_info->ptp_type = type;
1456 skb_info->tmo = jiffies + SKB_TIMESTAMP_TIMEOUT;
1457 skb_queue_tail(&dp83640->rx_queue, skb);
1458 schedule_delayed_work(&dp83640->ts_work, SKB_TIMESTAMP_TIMEOUT);
1459 } else {
1460 netif_rx_ni(skb);
1461 }
1462
1463 return true;
1464}
1465
1466static void dp83640_txtstamp(struct phy_device *phydev,
1467 struct sk_buff *skb, int type)
1468{
1469 struct dp83640_private *dp83640 = phydev->priv;
1470
1471 switch (dp83640->hwts_tx_en) {
1472
1473 case HWTSTAMP_TX_ONESTEP_SYNC:
1474 if (is_sync(skb, type)) {
1475 kfree_skb(skb);
1476 return;
1477 }
1478 /* fall through */
1479 case HWTSTAMP_TX_ON:
1480 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1481 skb_queue_tail(&dp83640->tx_queue, skb);
1482 break;
1483
1484 case HWTSTAMP_TX_OFF:
1485 default:
1486 kfree_skb(skb);
1487 break;
1488 }
1489}
1490
1491static int dp83640_ts_info(struct phy_device *dev, struct ethtool_ts_info *info)
1492{
1493 struct dp83640_private *dp83640 = dev->priv;
1494
1495 info->so_timestamping =
1496 SOF_TIMESTAMPING_TX_HARDWARE |
1497 SOF_TIMESTAMPING_RX_HARDWARE |
1498 SOF_TIMESTAMPING_RAW_HARDWARE;
1499 info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock);
1500 info->tx_types =
1501 (1 << HWTSTAMP_TX_OFF) |
1502 (1 << HWTSTAMP_TX_ON) |
1503 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
1504 info->rx_filters =
1505 (1 << HWTSTAMP_FILTER_NONE) |
1506 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
1507 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
1508 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1509 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
1510 return 0;
1511}
1512
1513static struct phy_driver dp83640_driver = {
1514 .phy_id = DP83640_PHY_ID,
1515 .phy_id_mask = 0xfffffff0,
1516 .name = "NatSemi DP83640",
1517 .features = PHY_BASIC_FEATURES,
1518 .flags = PHY_HAS_INTERRUPT,
1519 .probe = dp83640_probe,
1520 .remove = dp83640_remove,
1521 .soft_reset = dp83640_soft_reset,
1522 .config_init = dp83640_config_init,
1523 .ack_interrupt = dp83640_ack_interrupt,
1524 .config_intr = dp83640_config_intr,
1525 .ts_info = dp83640_ts_info,
1526 .hwtstamp = dp83640_hwtstamp,
1527 .rxtstamp = dp83640_rxtstamp,
1528 .txtstamp = dp83640_txtstamp,
1529};
1530
1531static int __init dp83640_init(void)
1532{
1533 return phy_driver_register(&dp83640_driver, THIS_MODULE);
1534}
1535
1536static void __exit dp83640_exit(void)
1537{
1538 dp83640_free_clocks();
1539 phy_driver_unregister(&dp83640_driver);
1540}
1541
1542MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver");
1543MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
1544MODULE_LICENSE("GPL");
1545
1546module_init(dp83640_init);
1547module_exit(dp83640_exit);
1548
1549static struct mdio_device_id __maybe_unused dp83640_tbl[] = {
1550 { DP83640_PHY_ID, 0xfffffff0 },
1551 { }
1552};
1553
1554MODULE_DEVICE_TABLE(mdio, dp83640_tbl);
1/*
2 * Driver for the National Semiconductor DP83640 PHYTER
3 *
4 * Copyright (C) 2010 OMICRON electronics GmbH
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22
23#include <linux/ethtool.h>
24#include <linux/kernel.h>
25#include <linux/list.h>
26#include <linux/mii.h>
27#include <linux/module.h>
28#include <linux/net_tstamp.h>
29#include <linux/netdevice.h>
30#include <linux/if_vlan.h>
31#include <linux/phy.h>
32#include <linux/ptp_classify.h>
33#include <linux/ptp_clock_kernel.h>
34
35#include "dp83640_reg.h"
36
37#define DP83640_PHY_ID 0x20005ce1
38#define PAGESEL 0x13
39#define LAYER4 0x02
40#define LAYER2 0x01
41#define MAX_RXTS 64
42#define N_EXT_TS 6
43#define PSF_PTPVER 2
44#define PSF_EVNT 0x4000
45#define PSF_RX 0x2000
46#define PSF_TX 0x1000
47#define EXT_EVENT 1
48#define CAL_EVENT 7
49#define CAL_TRIGGER 7
50#define PER_TRIGGER 6
51#define DP83640_N_PINS 12
52
53#define MII_DP83640_MICR 0x11
54#define MII_DP83640_MISR 0x12
55
56#define MII_DP83640_MICR_OE 0x1
57#define MII_DP83640_MICR_IE 0x2
58
59#define MII_DP83640_MISR_RHF_INT_EN 0x01
60#define MII_DP83640_MISR_FHF_INT_EN 0x02
61#define MII_DP83640_MISR_ANC_INT_EN 0x04
62#define MII_DP83640_MISR_DUP_INT_EN 0x08
63#define MII_DP83640_MISR_SPD_INT_EN 0x10
64#define MII_DP83640_MISR_LINK_INT_EN 0x20
65#define MII_DP83640_MISR_ED_INT_EN 0x40
66#define MII_DP83640_MISR_LQ_INT_EN 0x80
67
68/* phyter seems to miss the mark by 16 ns */
69#define ADJTIME_FIX 16
70
71#if defined(__BIG_ENDIAN)
72#define ENDIAN_FLAG 0
73#elif defined(__LITTLE_ENDIAN)
74#define ENDIAN_FLAG PSF_ENDIAN
75#endif
76
77#define SKB_PTP_TYPE(__skb) (*(unsigned int *)((__skb)->cb))
78
79struct phy_rxts {
80 u16 ns_lo; /* ns[15:0] */
81 u16 ns_hi; /* overflow[1:0], ns[29:16] */
82 u16 sec_lo; /* sec[15:0] */
83 u16 sec_hi; /* sec[31:16] */
84 u16 seqid; /* sequenceId[15:0] */
85 u16 msgtype; /* messageType[3:0], hash[11:0] */
86};
87
88struct phy_txts {
89 u16 ns_lo; /* ns[15:0] */
90 u16 ns_hi; /* overflow[1:0], ns[29:16] */
91 u16 sec_lo; /* sec[15:0] */
92 u16 sec_hi; /* sec[31:16] */
93};
94
95struct rxts {
96 struct list_head list;
97 unsigned long tmo;
98 u64 ns;
99 u16 seqid;
100 u8 msgtype;
101 u16 hash;
102};
103
104struct dp83640_clock;
105
106struct dp83640_private {
107 struct list_head list;
108 struct dp83640_clock *clock;
109 struct phy_device *phydev;
110 struct work_struct ts_work;
111 int hwts_tx_en;
112 int hwts_rx_en;
113 int layer;
114 int version;
115 /* remember state of cfg0 during calibration */
116 int cfg0;
117 /* remember the last event time stamp */
118 struct phy_txts edata;
119 /* list of rx timestamps */
120 struct list_head rxts;
121 struct list_head rxpool;
122 struct rxts rx_pool_data[MAX_RXTS];
123 /* protects above three fields from concurrent access */
124 spinlock_t rx_lock;
125 /* queues of incoming and outgoing packets */
126 struct sk_buff_head rx_queue;
127 struct sk_buff_head tx_queue;
128};
129
130struct dp83640_clock {
131 /* keeps the instance in the 'phyter_clocks' list */
132 struct list_head list;
133 /* we create one clock instance per MII bus */
134 struct mii_bus *bus;
135 /* protects extended registers from concurrent access */
136 struct mutex extreg_lock;
137 /* remembers which page was last selected */
138 int page;
139 /* our advertised capabilities */
140 struct ptp_clock_info caps;
141 /* protects the three fields below from concurrent access */
142 struct mutex clock_lock;
143 /* the one phyter from which we shall read */
144 struct dp83640_private *chosen;
145 /* list of the other attached phyters, not chosen */
146 struct list_head phylist;
147 /* reference to our PTP hardware clock */
148 struct ptp_clock *ptp_clock;
149};
150
151/* globals */
152
153enum {
154 CALIBRATE_GPIO,
155 PEROUT_GPIO,
156 EXTTS0_GPIO,
157 EXTTS1_GPIO,
158 EXTTS2_GPIO,
159 EXTTS3_GPIO,
160 EXTTS4_GPIO,
161 EXTTS5_GPIO,
162 GPIO_TABLE_SIZE
163};
164
165static int chosen_phy = -1;
166static ushort gpio_tab[GPIO_TABLE_SIZE] = {
167 1, 2, 3, 4, 8, 9, 10, 11
168};
169
170module_param(chosen_phy, int, 0444);
171module_param_array(gpio_tab, ushort, NULL, 0444);
172
173MODULE_PARM_DESC(chosen_phy, \
174 "The address of the PHY to use for the ancillary clock features");
175MODULE_PARM_DESC(gpio_tab, \
176 "Which GPIO line to use for which purpose: cal,perout,extts1,...,extts6");
177
178static void dp83640_gpio_defaults(struct ptp_pin_desc *pd)
179{
180 int i, index;
181
182 for (i = 0; i < DP83640_N_PINS; i++) {
183 snprintf(pd[i].name, sizeof(pd[i].name), "GPIO%d", 1 + i);
184 pd[i].index = i;
185 }
186
187 for (i = 0; i < GPIO_TABLE_SIZE; i++) {
188 if (gpio_tab[i] < 1 || gpio_tab[i] > DP83640_N_PINS) {
189 pr_err("gpio_tab[%d]=%hu out of range", i, gpio_tab[i]);
190 return;
191 }
192 }
193
194 index = gpio_tab[CALIBRATE_GPIO] - 1;
195 pd[index].func = PTP_PF_PHYSYNC;
196 pd[index].chan = 0;
197
198 index = gpio_tab[PEROUT_GPIO] - 1;
199 pd[index].func = PTP_PF_PEROUT;
200 pd[index].chan = 0;
201
202 for (i = EXTTS0_GPIO; i < GPIO_TABLE_SIZE; i++) {
203 index = gpio_tab[i] - 1;
204 pd[index].func = PTP_PF_EXTTS;
205 pd[index].chan = i - EXTTS0_GPIO;
206 }
207}
208
209/* a list of clocks and a mutex to protect it */
210static LIST_HEAD(phyter_clocks);
211static DEFINE_MUTEX(phyter_clocks_lock);
212
213static void rx_timestamp_work(struct work_struct *work);
214
215/* extended register access functions */
216
217#define BROADCAST_ADDR 31
218
219static inline int broadcast_write(struct mii_bus *bus, u32 regnum, u16 val)
220{
221 return mdiobus_write(bus, BROADCAST_ADDR, regnum, val);
222}
223
224/* Caller must hold extreg_lock. */
225static int ext_read(struct phy_device *phydev, int page, u32 regnum)
226{
227 struct dp83640_private *dp83640 = phydev->priv;
228 int val;
229
230 if (dp83640->clock->page != page) {
231 broadcast_write(phydev->bus, PAGESEL, page);
232 dp83640->clock->page = page;
233 }
234 val = phy_read(phydev, regnum);
235
236 return val;
237}
238
239/* Caller must hold extreg_lock. */
240static void ext_write(int broadcast, struct phy_device *phydev,
241 int page, u32 regnum, u16 val)
242{
243 struct dp83640_private *dp83640 = phydev->priv;
244
245 if (dp83640->clock->page != page) {
246 broadcast_write(phydev->bus, PAGESEL, page);
247 dp83640->clock->page = page;
248 }
249 if (broadcast)
250 broadcast_write(phydev->bus, regnum, val);
251 else
252 phy_write(phydev, regnum, val);
253}
254
255/* Caller must hold extreg_lock. */
256static int tdr_write(int bc, struct phy_device *dev,
257 const struct timespec *ts, u16 cmd)
258{
259 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */
260 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */
261 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */
262 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/
263
264 ext_write(bc, dev, PAGE4, PTP_CTL, cmd);
265
266 return 0;
267}
268
269/* convert phy timestamps into driver timestamps */
270
271static void phy2rxts(struct phy_rxts *p, struct rxts *rxts)
272{
273 u32 sec;
274
275 sec = p->sec_lo;
276 sec |= p->sec_hi << 16;
277
278 rxts->ns = p->ns_lo;
279 rxts->ns |= (p->ns_hi & 0x3fff) << 16;
280 rxts->ns += ((u64)sec) * 1000000000ULL;
281 rxts->seqid = p->seqid;
282 rxts->msgtype = (p->msgtype >> 12) & 0xf;
283 rxts->hash = p->msgtype & 0x0fff;
284 rxts->tmo = jiffies + 2;
285}
286
287static u64 phy2txts(struct phy_txts *p)
288{
289 u64 ns;
290 u32 sec;
291
292 sec = p->sec_lo;
293 sec |= p->sec_hi << 16;
294
295 ns = p->ns_lo;
296 ns |= (p->ns_hi & 0x3fff) << 16;
297 ns += ((u64)sec) * 1000000000ULL;
298
299 return ns;
300}
301
302static int periodic_output(struct dp83640_clock *clock,
303 struct ptp_clock_request *clkreq, bool on)
304{
305 struct dp83640_private *dp83640 = clock->chosen;
306 struct phy_device *phydev = dp83640->phydev;
307 u32 sec, nsec, pwidth;
308 u16 gpio, ptp_trig, trigger, val;
309
310 if (on) {
311 gpio = 1 + ptp_find_pin(clock->ptp_clock, PTP_PF_PEROUT, 0);
312 if (gpio < 1)
313 return -EINVAL;
314 } else {
315 gpio = 0;
316 }
317
318 trigger = PER_TRIGGER;
319
320 ptp_trig = TRIG_WR |
321 (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT |
322 (gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT |
323 TRIG_PER |
324 TRIG_PULSE;
325
326 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
327
328 if (!on) {
329 val |= TRIG_DIS;
330 mutex_lock(&clock->extreg_lock);
331 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
332 ext_write(0, phydev, PAGE4, PTP_CTL, val);
333 mutex_unlock(&clock->extreg_lock);
334 return 0;
335 }
336
337 sec = clkreq->perout.start.sec;
338 nsec = clkreq->perout.start.nsec;
339 pwidth = clkreq->perout.period.sec * 1000000000UL;
340 pwidth += clkreq->perout.period.nsec;
341 pwidth /= 2;
342
343 mutex_lock(&clock->extreg_lock);
344
345 ext_write(0, phydev, PAGE5, PTP_TRIG, ptp_trig);
346
347 /*load trigger*/
348 val |= TRIG_LOAD;
349 ext_write(0, phydev, PAGE4, PTP_CTL, val);
350 ext_write(0, phydev, PAGE4, PTP_TDR, nsec & 0xffff); /* ns[15:0] */
351 ext_write(0, phydev, PAGE4, PTP_TDR, nsec >> 16); /* ns[31:16] */
352 ext_write(0, phydev, PAGE4, PTP_TDR, sec & 0xffff); /* sec[15:0] */
353 ext_write(0, phydev, PAGE4, PTP_TDR, sec >> 16); /* sec[31:16] */
354 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth & 0xffff); /* ns[15:0] */
355 ext_write(0, phydev, PAGE4, PTP_TDR, pwidth >> 16); /* ns[31:16] */
356
357 /*enable trigger*/
358 val &= ~TRIG_LOAD;
359 val |= TRIG_EN;
360 ext_write(0, phydev, PAGE4, PTP_CTL, val);
361
362 mutex_unlock(&clock->extreg_lock);
363 return 0;
364}
365
366/* ptp clock methods */
367
368static int ptp_dp83640_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
369{
370 struct dp83640_clock *clock =
371 container_of(ptp, struct dp83640_clock, caps);
372 struct phy_device *phydev = clock->chosen->phydev;
373 u64 rate;
374 int neg_adj = 0;
375 u16 hi, lo;
376
377 if (ppb < 0) {
378 neg_adj = 1;
379 ppb = -ppb;
380 }
381 rate = ppb;
382 rate <<= 26;
383 rate = div_u64(rate, 1953125);
384
385 hi = (rate >> 16) & PTP_RATE_HI_MASK;
386 if (neg_adj)
387 hi |= PTP_RATE_DIR;
388
389 lo = rate & 0xffff;
390
391 mutex_lock(&clock->extreg_lock);
392
393 ext_write(1, phydev, PAGE4, PTP_RATEH, hi);
394 ext_write(1, phydev, PAGE4, PTP_RATEL, lo);
395
396 mutex_unlock(&clock->extreg_lock);
397
398 return 0;
399}
400
401static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta)
402{
403 struct dp83640_clock *clock =
404 container_of(ptp, struct dp83640_clock, caps);
405 struct phy_device *phydev = clock->chosen->phydev;
406 struct timespec ts;
407 int err;
408
409 delta += ADJTIME_FIX;
410
411 ts = ns_to_timespec(delta);
412
413 mutex_lock(&clock->extreg_lock);
414
415 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);
416
417 mutex_unlock(&clock->extreg_lock);
418
419 return err;
420}
421
422static int ptp_dp83640_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
423{
424 struct dp83640_clock *clock =
425 container_of(ptp, struct dp83640_clock, caps);
426 struct phy_device *phydev = clock->chosen->phydev;
427 unsigned int val[4];
428
429 mutex_lock(&clock->extreg_lock);
430
431 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
432
433 val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */
434 val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */
435 val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */
436 val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */
437
438 mutex_unlock(&clock->extreg_lock);
439
440 ts->tv_nsec = val[0] | (val[1] << 16);
441 ts->tv_sec = val[2] | (val[3] << 16);
442
443 return 0;
444}
445
446static int ptp_dp83640_settime(struct ptp_clock_info *ptp,
447 const struct timespec *ts)
448{
449 struct dp83640_clock *clock =
450 container_of(ptp, struct dp83640_clock, caps);
451 struct phy_device *phydev = clock->chosen->phydev;
452 int err;
453
454 mutex_lock(&clock->extreg_lock);
455
456 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);
457
458 mutex_unlock(&clock->extreg_lock);
459
460 return err;
461}
462
463static int ptp_dp83640_enable(struct ptp_clock_info *ptp,
464 struct ptp_clock_request *rq, int on)
465{
466 struct dp83640_clock *clock =
467 container_of(ptp, struct dp83640_clock, caps);
468 struct phy_device *phydev = clock->chosen->phydev;
469 unsigned int index;
470 u16 evnt, event_num, gpio_num;
471
472 switch (rq->type) {
473 case PTP_CLK_REQ_EXTTS:
474 index = rq->extts.index;
475 if (index >= N_EXT_TS)
476 return -EINVAL;
477 event_num = EXT_EVENT + index;
478 evnt = EVNT_WR | (event_num & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
479 if (on) {
480 gpio_num = 1 + ptp_find_pin(clock->ptp_clock,
481 PTP_PF_EXTTS, index);
482 if (gpio_num < 1)
483 return -EINVAL;
484 evnt |= (gpio_num & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
485 if (rq->extts.flags & PTP_FALLING_EDGE)
486 evnt |= EVNT_FALL;
487 else
488 evnt |= EVNT_RISE;
489 }
490 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt);
491 return 0;
492
493 case PTP_CLK_REQ_PEROUT:
494 if (rq->perout.index != 0)
495 return -EINVAL;
496 return periodic_output(clock, rq, on);
497
498 default:
499 break;
500 }
501
502 return -EOPNOTSUPP;
503}
504
505static int ptp_dp83640_verify(struct ptp_clock_info *ptp, unsigned int pin,
506 enum ptp_pin_function func, unsigned int chan)
507{
508 return 0;
509}
510
511static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 };
512static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F };
513
514static void enable_status_frames(struct phy_device *phydev, bool on)
515{
516 u16 cfg0 = 0, ver;
517
518 if (on)
519 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG;
520
521 ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT;
522
523 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0);
524 ext_write(0, phydev, PAGE6, PSF_CFG1, ver);
525
526 if (!phydev->attached_dev) {
527 pr_warn("expected to find an attached netdevice\n");
528 return;
529 }
530
531 if (on) {
532 if (dev_mc_add(phydev->attached_dev, status_frame_dst))
533 pr_warn("failed to add mc address\n");
534 } else {
535 if (dev_mc_del(phydev->attached_dev, status_frame_dst))
536 pr_warn("failed to delete mc address\n");
537 }
538}
539
540static bool is_status_frame(struct sk_buff *skb, int type)
541{
542 struct ethhdr *h = eth_hdr(skb);
543
544 if (PTP_CLASS_V2_L2 == type &&
545 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src)))
546 return true;
547 else
548 return false;
549}
550
551static int expired(struct rxts *rxts)
552{
553 return time_after(jiffies, rxts->tmo);
554}
555
556/* Caller must hold rx_lock. */
557static void prune_rx_ts(struct dp83640_private *dp83640)
558{
559 struct list_head *this, *next;
560 struct rxts *rxts;
561
562 list_for_each_safe(this, next, &dp83640->rxts) {
563 rxts = list_entry(this, struct rxts, list);
564 if (expired(rxts)) {
565 list_del_init(&rxts->list);
566 list_add(&rxts->list, &dp83640->rxpool);
567 }
568 }
569}
570
571/* synchronize the phyters so they act as one clock */
572
573static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
574{
575 int val;
576 phy_write(phydev, PAGESEL, 0);
577 val = phy_read(phydev, PHYCR2);
578 if (on)
579 val |= BC_WRITE;
580 else
581 val &= ~BC_WRITE;
582 phy_write(phydev, PHYCR2, val);
583 phy_write(phydev, PAGESEL, init_page);
584}
585
586static void recalibrate(struct dp83640_clock *clock)
587{
588 s64 now, diff;
589 struct phy_txts event_ts;
590 struct timespec ts;
591 struct list_head *this;
592 struct dp83640_private *tmp;
593 struct phy_device *master = clock->chosen->phydev;
594 u16 cal_gpio, cfg0, evnt, ptp_trig, trigger, val;
595
596 trigger = CAL_TRIGGER;
597 cal_gpio = gpio_tab[CALIBRATE_GPIO];
598
599 mutex_lock(&clock->extreg_lock);
600
601 /*
602 * enable broadcast, disable status frames, enable ptp clock
603 */
604 list_for_each(this, &clock->phylist) {
605 tmp = list_entry(this, struct dp83640_private, list);
606 enable_broadcast(tmp->phydev, clock->page, 1);
607 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);
608 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);
609 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);
610 }
611 enable_broadcast(master, clock->page, 1);
612 cfg0 = ext_read(master, PAGE5, PSF_CFG0);
613 ext_write(0, master, PAGE5, PSF_CFG0, 0);
614 ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE);
615
616 /*
617 * enable an event timestamp
618 */
619 evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE;
620 evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
621 evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
622
623 list_for_each(this, &clock->phylist) {
624 tmp = list_entry(this, struct dp83640_private, list);
625 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
626 }
627 ext_write(0, master, PAGE5, PTP_EVNT, evnt);
628
629 /*
630 * configure a trigger
631 */
632 ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE;
633 ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT;
634 ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT;
635 ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig);
636
637 /* load trigger */
638 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
639 val |= TRIG_LOAD;
640 ext_write(0, master, PAGE4, PTP_CTL, val);
641
642 /* enable trigger */
643 val &= ~TRIG_LOAD;
644 val |= TRIG_EN;
645 ext_write(0, master, PAGE4, PTP_CTL, val);
646
647 /* disable trigger */
648 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
649 val |= TRIG_DIS;
650 ext_write(0, master, PAGE4, PTP_CTL, val);
651
652 /*
653 * read out and correct offsets
654 */
655 val = ext_read(master, PAGE4, PTP_STS);
656 pr_info("master PTP_STS 0x%04hx\n", val);
657 val = ext_read(master, PAGE4, PTP_ESTS);
658 pr_info("master PTP_ESTS 0x%04hx\n", val);
659 event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA);
660 event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA);
661 event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA);
662 event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA);
663 now = phy2txts(&event_ts);
664
665 list_for_each(this, &clock->phylist) {
666 tmp = list_entry(this, struct dp83640_private, list);
667 val = ext_read(tmp->phydev, PAGE4, PTP_STS);
668 pr_info("slave PTP_STS 0x%04hx\n", val);
669 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);
670 pr_info("slave PTP_ESTS 0x%04hx\n", val);
671 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
672 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
673 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
674 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
675 diff = now - (s64) phy2txts(&event_ts);
676 pr_info("slave offset %lld nanoseconds\n", diff);
677 diff += ADJTIME_FIX;
678 ts = ns_to_timespec(diff);
679 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);
680 }
681
682 /*
683 * restore status frames
684 */
685 list_for_each(this, &clock->phylist) {
686 tmp = list_entry(this, struct dp83640_private, list);
687 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);
688 }
689 ext_write(0, master, PAGE5, PSF_CFG0, cfg0);
690
691 mutex_unlock(&clock->extreg_lock);
692}
693
694/* time stamping methods */
695
696static inline u16 exts_chan_to_edata(int ch)
697{
698 return 1 << ((ch + EXT_EVENT) * 2);
699}
700
701static int decode_evnt(struct dp83640_private *dp83640,
702 void *data, u16 ests)
703{
704 struct phy_txts *phy_txts;
705 struct ptp_clock_event event;
706 int i, parsed;
707 int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK;
708 u16 ext_status = 0;
709
710 if (ests & MULT_EVNT) {
711 ext_status = *(u16 *) data;
712 data += sizeof(ext_status);
713 }
714
715 phy_txts = data;
716
717 switch (words) { /* fall through in every case */
718 case 3:
719 dp83640->edata.sec_hi = phy_txts->sec_hi;
720 case 2:
721 dp83640->edata.sec_lo = phy_txts->sec_lo;
722 case 1:
723 dp83640->edata.ns_hi = phy_txts->ns_hi;
724 case 0:
725 dp83640->edata.ns_lo = phy_txts->ns_lo;
726 }
727
728 if (ext_status) {
729 parsed = words + 2;
730 } else {
731 parsed = words + 1;
732 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT;
733 ext_status = exts_chan_to_edata(i);
734 }
735
736 event.type = PTP_CLOCK_EXTTS;
737 event.timestamp = phy2txts(&dp83640->edata);
738
739 for (i = 0; i < N_EXT_TS; i++) {
740 if (ext_status & exts_chan_to_edata(i)) {
741 event.index = i;
742 ptp_clock_event(dp83640->clock->ptp_clock, &event);
743 }
744 }
745
746 return parsed * sizeof(u16);
747}
748
749static void decode_rxts(struct dp83640_private *dp83640,
750 struct phy_rxts *phy_rxts)
751{
752 struct rxts *rxts;
753 unsigned long flags;
754
755 spin_lock_irqsave(&dp83640->rx_lock, flags);
756
757 prune_rx_ts(dp83640);
758
759 if (list_empty(&dp83640->rxpool)) {
760 pr_debug("rx timestamp pool is empty\n");
761 goto out;
762 }
763 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);
764 list_del_init(&rxts->list);
765 phy2rxts(phy_rxts, rxts);
766 list_add_tail(&rxts->list, &dp83640->rxts);
767out:
768 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
769}
770
771static void decode_txts(struct dp83640_private *dp83640,
772 struct phy_txts *phy_txts)
773{
774 struct skb_shared_hwtstamps shhwtstamps;
775 struct sk_buff *skb;
776 u64 ns;
777
778 /* We must already have the skb that triggered this. */
779
780 skb = skb_dequeue(&dp83640->tx_queue);
781
782 if (!skb) {
783 pr_debug("have timestamp but tx_queue empty\n");
784 return;
785 }
786 ns = phy2txts(phy_txts);
787 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
788 shhwtstamps.hwtstamp = ns_to_ktime(ns);
789 skb_complete_tx_timestamp(skb, &shhwtstamps);
790}
791
792static void decode_status_frame(struct dp83640_private *dp83640,
793 struct sk_buff *skb)
794{
795 struct phy_rxts *phy_rxts;
796 struct phy_txts *phy_txts;
797 u8 *ptr;
798 int len, size;
799 u16 ests, type;
800
801 ptr = skb->data + 2;
802
803 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) {
804
805 type = *(u16 *)ptr;
806 ests = type & 0x0fff;
807 type = type & 0xf000;
808 len -= sizeof(type);
809 ptr += sizeof(type);
810
811 if (PSF_RX == type && len >= sizeof(*phy_rxts)) {
812
813 phy_rxts = (struct phy_rxts *) ptr;
814 decode_rxts(dp83640, phy_rxts);
815 size = sizeof(*phy_rxts);
816
817 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) {
818
819 phy_txts = (struct phy_txts *) ptr;
820 decode_txts(dp83640, phy_txts);
821 size = sizeof(*phy_txts);
822
823 } else if (PSF_EVNT == type && len >= sizeof(*phy_txts)) {
824
825 size = decode_evnt(dp83640, ptr, ests);
826
827 } else {
828 size = 0;
829 break;
830 }
831 ptr += size;
832 }
833}
834
835static int is_sync(struct sk_buff *skb, int type)
836{
837 u8 *data = skb->data, *msgtype;
838 unsigned int offset = 0;
839
840 switch (type) {
841 case PTP_CLASS_V1_IPV4:
842 case PTP_CLASS_V2_IPV4:
843 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
844 break;
845 case PTP_CLASS_V1_IPV6:
846 case PTP_CLASS_V2_IPV6:
847 offset = OFF_PTP6;
848 break;
849 case PTP_CLASS_V2_L2:
850 offset = ETH_HLEN;
851 break;
852 case PTP_CLASS_V2_VLAN:
853 offset = ETH_HLEN + VLAN_HLEN;
854 break;
855 default:
856 return 0;
857 }
858
859 if (type & PTP_CLASS_V1)
860 offset += OFF_PTP_CONTROL;
861
862 if (skb->len < offset + 1)
863 return 0;
864
865 msgtype = data + offset;
866
867 return (*msgtype & 0xf) == 0;
868}
869
870static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
871{
872 u16 *seqid;
873 unsigned int offset;
874 u8 *msgtype, *data = skb_mac_header(skb);
875
876 /* check sequenceID, messageType, 12 bit hash of offset 20-29 */
877
878 switch (type) {
879 case PTP_CLASS_V1_IPV4:
880 case PTP_CLASS_V2_IPV4:
881 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
882 break;
883 case PTP_CLASS_V1_IPV6:
884 case PTP_CLASS_V2_IPV6:
885 offset = OFF_PTP6;
886 break;
887 case PTP_CLASS_V2_L2:
888 offset = ETH_HLEN;
889 break;
890 case PTP_CLASS_V2_VLAN:
891 offset = ETH_HLEN + VLAN_HLEN;
892 break;
893 default:
894 return 0;
895 }
896
897 if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid))
898 return 0;
899
900 if (unlikely(type & PTP_CLASS_V1))
901 msgtype = data + offset + OFF_PTP_CONTROL;
902 else
903 msgtype = data + offset;
904
905 seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
906
907 return rxts->msgtype == (*msgtype & 0xf) &&
908 rxts->seqid == ntohs(*seqid);
909}
910
911static void dp83640_free_clocks(void)
912{
913 struct dp83640_clock *clock;
914 struct list_head *this, *next;
915
916 mutex_lock(&phyter_clocks_lock);
917
918 list_for_each_safe(this, next, &phyter_clocks) {
919 clock = list_entry(this, struct dp83640_clock, list);
920 if (!list_empty(&clock->phylist)) {
921 pr_warn("phy list non-empty while unloading\n");
922 BUG();
923 }
924 list_del(&clock->list);
925 mutex_destroy(&clock->extreg_lock);
926 mutex_destroy(&clock->clock_lock);
927 put_device(&clock->bus->dev);
928 kfree(clock->caps.pin_config);
929 kfree(clock);
930 }
931
932 mutex_unlock(&phyter_clocks_lock);
933}
934
935static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus)
936{
937 INIT_LIST_HEAD(&clock->list);
938 clock->bus = bus;
939 mutex_init(&clock->extreg_lock);
940 mutex_init(&clock->clock_lock);
941 INIT_LIST_HEAD(&clock->phylist);
942 clock->caps.owner = THIS_MODULE;
943 sprintf(clock->caps.name, "dp83640 timer");
944 clock->caps.max_adj = 1953124;
945 clock->caps.n_alarm = 0;
946 clock->caps.n_ext_ts = N_EXT_TS;
947 clock->caps.n_per_out = 1;
948 clock->caps.n_pins = DP83640_N_PINS;
949 clock->caps.pps = 0;
950 clock->caps.adjfreq = ptp_dp83640_adjfreq;
951 clock->caps.adjtime = ptp_dp83640_adjtime;
952 clock->caps.gettime = ptp_dp83640_gettime;
953 clock->caps.settime = ptp_dp83640_settime;
954 clock->caps.enable = ptp_dp83640_enable;
955 clock->caps.verify = ptp_dp83640_verify;
956 /*
957 * Convert the module param defaults into a dynamic pin configuration.
958 */
959 dp83640_gpio_defaults(clock->caps.pin_config);
960 /*
961 * Get a reference to this bus instance.
962 */
963 get_device(&bus->dev);
964}
965
966static int choose_this_phy(struct dp83640_clock *clock,
967 struct phy_device *phydev)
968{
969 if (chosen_phy == -1 && !clock->chosen)
970 return 1;
971
972 if (chosen_phy == phydev->addr)
973 return 1;
974
975 return 0;
976}
977
978static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock)
979{
980 if (clock)
981 mutex_lock(&clock->clock_lock);
982 return clock;
983}
984
985/*
986 * Look up and lock a clock by bus instance.
987 * If there is no clock for this bus, then create it first.
988 */
989static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus)
990{
991 struct dp83640_clock *clock = NULL, *tmp;
992 struct list_head *this;
993
994 mutex_lock(&phyter_clocks_lock);
995
996 list_for_each(this, &phyter_clocks) {
997 tmp = list_entry(this, struct dp83640_clock, list);
998 if (tmp->bus == bus) {
999 clock = tmp;
1000 break;
1001 }
1002 }
1003 if (clock)
1004 goto out;
1005
1006 clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL);
1007 if (!clock)
1008 goto out;
1009
1010 clock->caps.pin_config = kzalloc(sizeof(struct ptp_pin_desc) *
1011 DP83640_N_PINS, GFP_KERNEL);
1012 if (!clock->caps.pin_config) {
1013 kfree(clock);
1014 clock = NULL;
1015 goto out;
1016 }
1017 dp83640_clock_init(clock, bus);
1018 list_add_tail(&phyter_clocks, &clock->list);
1019out:
1020 mutex_unlock(&phyter_clocks_lock);
1021
1022 return dp83640_clock_get(clock);
1023}
1024
1025static void dp83640_clock_put(struct dp83640_clock *clock)
1026{
1027 mutex_unlock(&clock->clock_lock);
1028}
1029
1030static int dp83640_probe(struct phy_device *phydev)
1031{
1032 struct dp83640_clock *clock;
1033 struct dp83640_private *dp83640;
1034 int err = -ENOMEM, i;
1035
1036 if (phydev->addr == BROADCAST_ADDR)
1037 return 0;
1038
1039 clock = dp83640_clock_get_bus(phydev->bus);
1040 if (!clock)
1041 goto no_clock;
1042
1043 dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL);
1044 if (!dp83640)
1045 goto no_memory;
1046
1047 dp83640->phydev = phydev;
1048 INIT_WORK(&dp83640->ts_work, rx_timestamp_work);
1049
1050 INIT_LIST_HEAD(&dp83640->rxts);
1051 INIT_LIST_HEAD(&dp83640->rxpool);
1052 for (i = 0; i < MAX_RXTS; i++)
1053 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool);
1054
1055 phydev->priv = dp83640;
1056
1057 spin_lock_init(&dp83640->rx_lock);
1058 skb_queue_head_init(&dp83640->rx_queue);
1059 skb_queue_head_init(&dp83640->tx_queue);
1060
1061 dp83640->clock = clock;
1062
1063 if (choose_this_phy(clock, phydev)) {
1064 clock->chosen = dp83640;
1065 clock->ptp_clock = ptp_clock_register(&clock->caps, &phydev->dev);
1066 if (IS_ERR(clock->ptp_clock)) {
1067 err = PTR_ERR(clock->ptp_clock);
1068 goto no_register;
1069 }
1070 } else
1071 list_add_tail(&dp83640->list, &clock->phylist);
1072
1073 dp83640_clock_put(clock);
1074 return 0;
1075
1076no_register:
1077 clock->chosen = NULL;
1078 kfree(dp83640);
1079no_memory:
1080 dp83640_clock_put(clock);
1081no_clock:
1082 return err;
1083}
1084
1085static void dp83640_remove(struct phy_device *phydev)
1086{
1087 struct dp83640_clock *clock;
1088 struct list_head *this, *next;
1089 struct dp83640_private *tmp, *dp83640 = phydev->priv;
1090 struct sk_buff *skb;
1091
1092 if (phydev->addr == BROADCAST_ADDR)
1093 return;
1094
1095 enable_status_frames(phydev, false);
1096 cancel_work_sync(&dp83640->ts_work);
1097
1098 while ((skb = skb_dequeue(&dp83640->rx_queue)) != NULL)
1099 kfree_skb(skb);
1100
1101 while ((skb = skb_dequeue(&dp83640->tx_queue)) != NULL)
1102 skb_complete_tx_timestamp(skb, NULL);
1103
1104 clock = dp83640_clock_get(dp83640->clock);
1105
1106 if (dp83640 == clock->chosen) {
1107 ptp_clock_unregister(clock->ptp_clock);
1108 clock->chosen = NULL;
1109 } else {
1110 list_for_each_safe(this, next, &clock->phylist) {
1111 tmp = list_entry(this, struct dp83640_private, list);
1112 if (tmp == dp83640) {
1113 list_del_init(&tmp->list);
1114 break;
1115 }
1116 }
1117 }
1118
1119 dp83640_clock_put(clock);
1120 kfree(dp83640);
1121}
1122
1123static int dp83640_config_init(struct phy_device *phydev)
1124{
1125 struct dp83640_private *dp83640 = phydev->priv;
1126 struct dp83640_clock *clock = dp83640->clock;
1127
1128 if (clock->chosen && !list_empty(&clock->phylist))
1129 recalibrate(clock);
1130 else
1131 enable_broadcast(phydev, clock->page, 1);
1132
1133 enable_status_frames(phydev, true);
1134 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);
1135 return 0;
1136}
1137
1138static int dp83640_ack_interrupt(struct phy_device *phydev)
1139{
1140 int err = phy_read(phydev, MII_DP83640_MISR);
1141
1142 if (err < 0)
1143 return err;
1144
1145 return 0;
1146}
1147
1148static int dp83640_config_intr(struct phy_device *phydev)
1149{
1150 int micr;
1151 int misr;
1152 int err;
1153
1154 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1155 misr = phy_read(phydev, MII_DP83640_MISR);
1156 if (misr < 0)
1157 return misr;
1158 misr |=
1159 (MII_DP83640_MISR_ANC_INT_EN |
1160 MII_DP83640_MISR_DUP_INT_EN |
1161 MII_DP83640_MISR_SPD_INT_EN |
1162 MII_DP83640_MISR_LINK_INT_EN);
1163 err = phy_write(phydev, MII_DP83640_MISR, misr);
1164 if (err < 0)
1165 return err;
1166
1167 micr = phy_read(phydev, MII_DP83640_MICR);
1168 if (micr < 0)
1169 return micr;
1170 micr |=
1171 (MII_DP83640_MICR_OE |
1172 MII_DP83640_MICR_IE);
1173 return phy_write(phydev, MII_DP83640_MICR, micr);
1174 } else {
1175 micr = phy_read(phydev, MII_DP83640_MICR);
1176 if (micr < 0)
1177 return micr;
1178 micr &=
1179 ~(MII_DP83640_MICR_OE |
1180 MII_DP83640_MICR_IE);
1181 err = phy_write(phydev, MII_DP83640_MICR, micr);
1182 if (err < 0)
1183 return err;
1184
1185 misr = phy_read(phydev, MII_DP83640_MISR);
1186 if (misr < 0)
1187 return misr;
1188 misr &=
1189 ~(MII_DP83640_MISR_ANC_INT_EN |
1190 MII_DP83640_MISR_DUP_INT_EN |
1191 MII_DP83640_MISR_SPD_INT_EN |
1192 MII_DP83640_MISR_LINK_INT_EN);
1193 return phy_write(phydev, MII_DP83640_MISR, misr);
1194 }
1195}
1196
1197static int dp83640_hwtstamp(struct phy_device *phydev, struct ifreq *ifr)
1198{
1199 struct dp83640_private *dp83640 = phydev->priv;
1200 struct hwtstamp_config cfg;
1201 u16 txcfg0, rxcfg0;
1202
1203 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1204 return -EFAULT;
1205
1206 if (cfg.flags) /* reserved for future extensions */
1207 return -EINVAL;
1208
1209 if (cfg.tx_type < 0 || cfg.tx_type > HWTSTAMP_TX_ONESTEP_SYNC)
1210 return -ERANGE;
1211
1212 dp83640->hwts_tx_en = cfg.tx_type;
1213
1214 switch (cfg.rx_filter) {
1215 case HWTSTAMP_FILTER_NONE:
1216 dp83640->hwts_rx_en = 0;
1217 dp83640->layer = 0;
1218 dp83640->version = 0;
1219 break;
1220 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1221 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1222 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1223 dp83640->hwts_rx_en = 1;
1224 dp83640->layer = LAYER4;
1225 dp83640->version = 1;
1226 break;
1227 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1228 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1229 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1230 dp83640->hwts_rx_en = 1;
1231 dp83640->layer = LAYER4;
1232 dp83640->version = 2;
1233 break;
1234 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1235 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1236 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1237 dp83640->hwts_rx_en = 1;
1238 dp83640->layer = LAYER2;
1239 dp83640->version = 2;
1240 break;
1241 case HWTSTAMP_FILTER_PTP_V2_EVENT:
1242 case HWTSTAMP_FILTER_PTP_V2_SYNC:
1243 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1244 dp83640->hwts_rx_en = 1;
1245 dp83640->layer = LAYER4|LAYER2;
1246 dp83640->version = 2;
1247 break;
1248 default:
1249 return -ERANGE;
1250 }
1251
1252 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1253 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
1254
1255 if (dp83640->layer & LAYER2) {
1256 txcfg0 |= TX_L2_EN;
1257 rxcfg0 |= RX_L2_EN;
1258 }
1259 if (dp83640->layer & LAYER4) {
1260 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN;
1261 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN;
1262 }
1263
1264 if (dp83640->hwts_tx_en)
1265 txcfg0 |= TX_TS_EN;
1266
1267 if (dp83640->hwts_tx_en == HWTSTAMP_TX_ONESTEP_SYNC)
1268 txcfg0 |= SYNC_1STEP | CHK_1STEP;
1269
1270 if (dp83640->hwts_rx_en)
1271 rxcfg0 |= RX_TS_EN;
1272
1273 mutex_lock(&dp83640->clock->extreg_lock);
1274
1275 ext_write(0, phydev, PAGE5, PTP_TXCFG0, txcfg0);
1276 ext_write(0, phydev, PAGE5, PTP_RXCFG0, rxcfg0);
1277
1278 mutex_unlock(&dp83640->clock->extreg_lock);
1279
1280 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1281}
1282
1283static void rx_timestamp_work(struct work_struct *work)
1284{
1285 struct dp83640_private *dp83640 =
1286 container_of(work, struct dp83640_private, ts_work);
1287 struct list_head *this, *next;
1288 struct rxts *rxts;
1289 struct skb_shared_hwtstamps *shhwtstamps;
1290 struct sk_buff *skb;
1291 unsigned int type;
1292 unsigned long flags;
1293
1294 /* Deliver each deferred packet, with or without a time stamp. */
1295
1296 while ((skb = skb_dequeue(&dp83640->rx_queue)) != NULL) {
1297 type = SKB_PTP_TYPE(skb);
1298 spin_lock_irqsave(&dp83640->rx_lock, flags);
1299 list_for_each_safe(this, next, &dp83640->rxts) {
1300 rxts = list_entry(this, struct rxts, list);
1301 if (match(skb, type, rxts)) {
1302 shhwtstamps = skb_hwtstamps(skb);
1303 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
1304 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
1305 list_del_init(&rxts->list);
1306 list_add(&rxts->list, &dp83640->rxpool);
1307 break;
1308 }
1309 }
1310 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
1311 netif_rx_ni(skb);
1312 }
1313
1314 /* Clear out expired time stamps. */
1315
1316 spin_lock_irqsave(&dp83640->rx_lock, flags);
1317 prune_rx_ts(dp83640);
1318 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
1319}
1320
1321static bool dp83640_rxtstamp(struct phy_device *phydev,
1322 struct sk_buff *skb, int type)
1323{
1324 struct dp83640_private *dp83640 = phydev->priv;
1325
1326 if (!dp83640->hwts_rx_en)
1327 return false;
1328
1329 if (is_status_frame(skb, type)) {
1330 decode_status_frame(dp83640, skb);
1331 kfree_skb(skb);
1332 return true;
1333 }
1334
1335 SKB_PTP_TYPE(skb) = type;
1336 skb_queue_tail(&dp83640->rx_queue, skb);
1337 schedule_work(&dp83640->ts_work);
1338
1339 return true;
1340}
1341
1342static void dp83640_txtstamp(struct phy_device *phydev,
1343 struct sk_buff *skb, int type)
1344{
1345 struct dp83640_private *dp83640 = phydev->priv;
1346
1347 switch (dp83640->hwts_tx_en) {
1348
1349 case HWTSTAMP_TX_ONESTEP_SYNC:
1350 if (is_sync(skb, type)) {
1351 skb_complete_tx_timestamp(skb, NULL);
1352 return;
1353 }
1354 /* fall through */
1355 case HWTSTAMP_TX_ON:
1356 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1357 skb_queue_tail(&dp83640->tx_queue, skb);
1358 schedule_work(&dp83640->ts_work);
1359 break;
1360
1361 case HWTSTAMP_TX_OFF:
1362 default:
1363 skb_complete_tx_timestamp(skb, NULL);
1364 break;
1365 }
1366}
1367
1368static int dp83640_ts_info(struct phy_device *dev, struct ethtool_ts_info *info)
1369{
1370 struct dp83640_private *dp83640 = dev->priv;
1371
1372 info->so_timestamping =
1373 SOF_TIMESTAMPING_TX_HARDWARE |
1374 SOF_TIMESTAMPING_RX_HARDWARE |
1375 SOF_TIMESTAMPING_RAW_HARDWARE;
1376 info->phc_index = ptp_clock_index(dp83640->clock->ptp_clock);
1377 info->tx_types =
1378 (1 << HWTSTAMP_TX_OFF) |
1379 (1 << HWTSTAMP_TX_ON) |
1380 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
1381 info->rx_filters =
1382 (1 << HWTSTAMP_FILTER_NONE) |
1383 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
1384 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
1385 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
1386 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
1387 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
1388 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
1389 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1390 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
1391 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
1392 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
1393 (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
1394 (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ);
1395 return 0;
1396}
1397
1398static struct phy_driver dp83640_driver = {
1399 .phy_id = DP83640_PHY_ID,
1400 .phy_id_mask = 0xfffffff0,
1401 .name = "NatSemi DP83640",
1402 .features = PHY_BASIC_FEATURES,
1403 .flags = PHY_HAS_INTERRUPT,
1404 .probe = dp83640_probe,
1405 .remove = dp83640_remove,
1406 .config_init = dp83640_config_init,
1407 .config_aneg = genphy_config_aneg,
1408 .read_status = genphy_read_status,
1409 .ack_interrupt = dp83640_ack_interrupt,
1410 .config_intr = dp83640_config_intr,
1411 .ts_info = dp83640_ts_info,
1412 .hwtstamp = dp83640_hwtstamp,
1413 .rxtstamp = dp83640_rxtstamp,
1414 .txtstamp = dp83640_txtstamp,
1415 .driver = {.owner = THIS_MODULE,}
1416};
1417
1418static int __init dp83640_init(void)
1419{
1420 return phy_driver_register(&dp83640_driver);
1421}
1422
1423static void __exit dp83640_exit(void)
1424{
1425 dp83640_free_clocks();
1426 phy_driver_unregister(&dp83640_driver);
1427}
1428
1429MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver");
1430MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
1431MODULE_LICENSE("GPL");
1432
1433module_init(dp83640_init);
1434module_exit(dp83640_exit);
1435
1436static struct mdio_device_id __maybe_unused dp83640_tbl[] = {
1437 { DP83640_PHY_ID, 0xfffffff0 },
1438 { }
1439};
1440
1441MODULE_DEVICE_TABLE(mdio, dp83640_tbl);