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1/*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Derived from "arch/m68k/kernel/ptrace.c"
6 * Copyright (C) 1994 by Hamish Macdonald
7 * Taken from linux/kernel/ptrace.c and modified for M680x0.
8 * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
9 *
10 * Modified by Cort Dougan (cort@hq.fsmlabs.com)
11 * and Paul Mackerras (paulus@samba.org).
12 *
13 * This file is subject to the terms and conditions of the GNU General
14 * Public License. See the file README.legal in the main directory of
15 * this archive for more details.
16 */
17
18#include <linux/kernel.h>
19#include <linux/sched.h>
20#include <linux/mm.h>
21#include <linux/smp.h>
22#include <linux/errno.h>
23#include <linux/ptrace.h>
24#include <linux/regset.h>
25#include <linux/tracehook.h>
26#include <linux/elf.h>
27#include <linux/user.h>
28#include <linux/security.h>
29#include <linux/signal.h>
30#include <linux/seccomp.h>
31#include <linux/audit.h>
32#include <trace/syscall.h>
33#include <linux/hw_breakpoint.h>
34#include <linux/perf_event.h>
35#include <linux/context_tracking.h>
36
37#include <linux/uaccess.h>
38#include <linux/pkeys.h>
39#include <asm/page.h>
40#include <asm/pgtable.h>
41#include <asm/switch_to.h>
42#include <asm/tm.h>
43#include <asm/asm-prototypes.h>
44#include <asm/debug.h>
45
46#define CREATE_TRACE_POINTS
47#include <trace/events/syscalls.h>
48
49/*
50 * The parameter save area on the stack is used to store arguments being passed
51 * to callee function and is located at fixed offset from stack pointer.
52 */
53#ifdef CONFIG_PPC32
54#define PARAMETER_SAVE_AREA_OFFSET 24 /* bytes */
55#else /* CONFIG_PPC32 */
56#define PARAMETER_SAVE_AREA_OFFSET 48 /* bytes */
57#endif
58
59struct pt_regs_offset {
60 const char *name;
61 int offset;
62};
63
64#define STR(s) #s /* convert to string */
65#define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)}
66#define GPR_OFFSET_NAME(num) \
67 {.name = STR(r##num), .offset = offsetof(struct pt_regs, gpr[num])}, \
68 {.name = STR(gpr##num), .offset = offsetof(struct pt_regs, gpr[num])}
69#define REG_OFFSET_END {.name = NULL, .offset = 0}
70
71#define TVSO(f) (offsetof(struct thread_vr_state, f))
72#define TFSO(f) (offsetof(struct thread_fp_state, f))
73#define TSO(f) (offsetof(struct thread_struct, f))
74
75static const struct pt_regs_offset regoffset_table[] = {
76 GPR_OFFSET_NAME(0),
77 GPR_OFFSET_NAME(1),
78 GPR_OFFSET_NAME(2),
79 GPR_OFFSET_NAME(3),
80 GPR_OFFSET_NAME(4),
81 GPR_OFFSET_NAME(5),
82 GPR_OFFSET_NAME(6),
83 GPR_OFFSET_NAME(7),
84 GPR_OFFSET_NAME(8),
85 GPR_OFFSET_NAME(9),
86 GPR_OFFSET_NAME(10),
87 GPR_OFFSET_NAME(11),
88 GPR_OFFSET_NAME(12),
89 GPR_OFFSET_NAME(13),
90 GPR_OFFSET_NAME(14),
91 GPR_OFFSET_NAME(15),
92 GPR_OFFSET_NAME(16),
93 GPR_OFFSET_NAME(17),
94 GPR_OFFSET_NAME(18),
95 GPR_OFFSET_NAME(19),
96 GPR_OFFSET_NAME(20),
97 GPR_OFFSET_NAME(21),
98 GPR_OFFSET_NAME(22),
99 GPR_OFFSET_NAME(23),
100 GPR_OFFSET_NAME(24),
101 GPR_OFFSET_NAME(25),
102 GPR_OFFSET_NAME(26),
103 GPR_OFFSET_NAME(27),
104 GPR_OFFSET_NAME(28),
105 GPR_OFFSET_NAME(29),
106 GPR_OFFSET_NAME(30),
107 GPR_OFFSET_NAME(31),
108 REG_OFFSET_NAME(nip),
109 REG_OFFSET_NAME(msr),
110 REG_OFFSET_NAME(ctr),
111 REG_OFFSET_NAME(link),
112 REG_OFFSET_NAME(xer),
113 REG_OFFSET_NAME(ccr),
114#ifdef CONFIG_PPC64
115 REG_OFFSET_NAME(softe),
116#else
117 REG_OFFSET_NAME(mq),
118#endif
119 REG_OFFSET_NAME(trap),
120 REG_OFFSET_NAME(dar),
121 REG_OFFSET_NAME(dsisr),
122 REG_OFFSET_END,
123};
124
125#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
126static void flush_tmregs_to_thread(struct task_struct *tsk)
127{
128 /*
129 * If task is not current, it will have been flushed already to
130 * it's thread_struct during __switch_to().
131 *
132 * A reclaim flushes ALL the state or if not in TM save TM SPRs
133 * in the appropriate thread structures from live.
134 */
135
136 if ((!cpu_has_feature(CPU_FTR_TM)) || (tsk != current))
137 return;
138
139 if (MSR_TM_SUSPENDED(mfmsr())) {
140 tm_reclaim_current(TM_CAUSE_SIGNAL);
141 } else {
142 tm_enable();
143 tm_save_sprs(&(tsk->thread));
144 }
145}
146#else
147static inline void flush_tmregs_to_thread(struct task_struct *tsk) { }
148#endif
149
150/**
151 * regs_query_register_offset() - query register offset from its name
152 * @name: the name of a register
153 *
154 * regs_query_register_offset() returns the offset of a register in struct
155 * pt_regs from its name. If the name is invalid, this returns -EINVAL;
156 */
157int regs_query_register_offset(const char *name)
158{
159 const struct pt_regs_offset *roff;
160 for (roff = regoffset_table; roff->name != NULL; roff++)
161 if (!strcmp(roff->name, name))
162 return roff->offset;
163 return -EINVAL;
164}
165
166/**
167 * regs_query_register_name() - query register name from its offset
168 * @offset: the offset of a register in struct pt_regs.
169 *
170 * regs_query_register_name() returns the name of a register from its
171 * offset in struct pt_regs. If the @offset is invalid, this returns NULL;
172 */
173const char *regs_query_register_name(unsigned int offset)
174{
175 const struct pt_regs_offset *roff;
176 for (roff = regoffset_table; roff->name != NULL; roff++)
177 if (roff->offset == offset)
178 return roff->name;
179 return NULL;
180}
181
182/*
183 * does not yet catch signals sent when the child dies.
184 * in exit.c or in signal.c.
185 */
186
187/*
188 * Set of msr bits that gdb can change on behalf of a process.
189 */
190#ifdef CONFIG_PPC_ADV_DEBUG_REGS
191#define MSR_DEBUGCHANGE 0
192#else
193#define MSR_DEBUGCHANGE (MSR_SE | MSR_BE)
194#endif
195
196/*
197 * Max register writeable via put_reg
198 */
199#ifdef CONFIG_PPC32
200#define PT_MAX_PUT_REG PT_MQ
201#else
202#define PT_MAX_PUT_REG PT_CCR
203#endif
204
205static unsigned long get_user_msr(struct task_struct *task)
206{
207 return task->thread.regs->msr | task->thread.fpexc_mode;
208}
209
210static int set_user_msr(struct task_struct *task, unsigned long msr)
211{
212 task->thread.regs->msr &= ~MSR_DEBUGCHANGE;
213 task->thread.regs->msr |= msr & MSR_DEBUGCHANGE;
214 return 0;
215}
216
217#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
218static unsigned long get_user_ckpt_msr(struct task_struct *task)
219{
220 return task->thread.ckpt_regs.msr | task->thread.fpexc_mode;
221}
222
223static int set_user_ckpt_msr(struct task_struct *task, unsigned long msr)
224{
225 task->thread.ckpt_regs.msr &= ~MSR_DEBUGCHANGE;
226 task->thread.ckpt_regs.msr |= msr & MSR_DEBUGCHANGE;
227 return 0;
228}
229
230static int set_user_ckpt_trap(struct task_struct *task, unsigned long trap)
231{
232 task->thread.ckpt_regs.trap = trap & 0xfff0;
233 return 0;
234}
235#endif
236
237#ifdef CONFIG_PPC64
238static int get_user_dscr(struct task_struct *task, unsigned long *data)
239{
240 *data = task->thread.dscr;
241 return 0;
242}
243
244static int set_user_dscr(struct task_struct *task, unsigned long dscr)
245{
246 task->thread.dscr = dscr;
247 task->thread.dscr_inherit = 1;
248 return 0;
249}
250#else
251static int get_user_dscr(struct task_struct *task, unsigned long *data)
252{
253 return -EIO;
254}
255
256static int set_user_dscr(struct task_struct *task, unsigned long dscr)
257{
258 return -EIO;
259}
260#endif
261
262/*
263 * We prevent mucking around with the reserved area of trap
264 * which are used internally by the kernel.
265 */
266static int set_user_trap(struct task_struct *task, unsigned long trap)
267{
268 task->thread.regs->trap = trap & 0xfff0;
269 return 0;
270}
271
272/*
273 * Get contents of register REGNO in task TASK.
274 */
275int ptrace_get_reg(struct task_struct *task, int regno, unsigned long *data)
276{
277 if ((task->thread.regs == NULL) || !data)
278 return -EIO;
279
280 if (regno == PT_MSR) {
281 *data = get_user_msr(task);
282 return 0;
283 }
284
285 if (regno == PT_DSCR)
286 return get_user_dscr(task, data);
287
288#ifdef CONFIG_PPC64
289 /*
290 * softe copies paca->irq_soft_mask variable state. Since irq_soft_mask is
291 * no more used as a flag, lets force usr to alway see the softe value as 1
292 * which means interrupts are not soft disabled.
293 */
294 if (regno == PT_SOFTE) {
295 *data = 1;
296 return 0;
297 }
298#endif
299
300 if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long))) {
301 *data = ((unsigned long *)task->thread.regs)[regno];
302 return 0;
303 }
304
305 return -EIO;
306}
307
308/*
309 * Write contents of register REGNO in task TASK.
310 */
311int ptrace_put_reg(struct task_struct *task, int regno, unsigned long data)
312{
313 if (task->thread.regs == NULL)
314 return -EIO;
315
316 if (regno == PT_MSR)
317 return set_user_msr(task, data);
318 if (regno == PT_TRAP)
319 return set_user_trap(task, data);
320 if (regno == PT_DSCR)
321 return set_user_dscr(task, data);
322
323 if (regno <= PT_MAX_PUT_REG) {
324 ((unsigned long *)task->thread.regs)[regno] = data;
325 return 0;
326 }
327 return -EIO;
328}
329
330static int gpr_get(struct task_struct *target, const struct user_regset *regset,
331 unsigned int pos, unsigned int count,
332 void *kbuf, void __user *ubuf)
333{
334 int i, ret;
335
336 if (target->thread.regs == NULL)
337 return -EIO;
338
339 if (!FULL_REGS(target->thread.regs)) {
340 /* We have a partial register set. Fill 14-31 with bogus values */
341 for (i = 14; i < 32; i++)
342 target->thread.regs->gpr[i] = NV_REG_POISON;
343 }
344
345 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
346 target->thread.regs,
347 0, offsetof(struct pt_regs, msr));
348 if (!ret) {
349 unsigned long msr = get_user_msr(target);
350 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr,
351 offsetof(struct pt_regs, msr),
352 offsetof(struct pt_regs, msr) +
353 sizeof(msr));
354 }
355
356 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
357 offsetof(struct pt_regs, msr) + sizeof(long));
358
359 if (!ret)
360 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
361 &target->thread.regs->orig_gpr3,
362 offsetof(struct pt_regs, orig_gpr3),
363 sizeof(struct pt_regs));
364 if (!ret)
365 ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
366 sizeof(struct pt_regs), -1);
367
368 return ret;
369}
370
371static int gpr_set(struct task_struct *target, const struct user_regset *regset,
372 unsigned int pos, unsigned int count,
373 const void *kbuf, const void __user *ubuf)
374{
375 unsigned long reg;
376 int ret;
377
378 if (target->thread.regs == NULL)
379 return -EIO;
380
381 CHECK_FULL_REGS(target->thread.regs);
382
383 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
384 target->thread.regs,
385 0, PT_MSR * sizeof(reg));
386
387 if (!ret && count > 0) {
388 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®,
389 PT_MSR * sizeof(reg),
390 (PT_MSR + 1) * sizeof(reg));
391 if (!ret)
392 ret = set_user_msr(target, reg);
393 }
394
395 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
396 offsetof(struct pt_regs, msr) + sizeof(long));
397
398 if (!ret)
399 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
400 &target->thread.regs->orig_gpr3,
401 PT_ORIG_R3 * sizeof(reg),
402 (PT_MAX_PUT_REG + 1) * sizeof(reg));
403
404 if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret)
405 ret = user_regset_copyin_ignore(
406 &pos, &count, &kbuf, &ubuf,
407 (PT_MAX_PUT_REG + 1) * sizeof(reg),
408 PT_TRAP * sizeof(reg));
409
410 if (!ret && count > 0) {
411 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®,
412 PT_TRAP * sizeof(reg),
413 (PT_TRAP + 1) * sizeof(reg));
414 if (!ret)
415 ret = set_user_trap(target, reg);
416 }
417
418 if (!ret)
419 ret = user_regset_copyin_ignore(
420 &pos, &count, &kbuf, &ubuf,
421 (PT_TRAP + 1) * sizeof(reg), -1);
422
423 return ret;
424}
425
426/*
427 * Regardless of transactions, 'fp_state' holds the current running
428 * value of all FPR registers and 'ckfp_state' holds the last checkpointed
429 * value of all FPR registers for the current transaction.
430 *
431 * Userspace interface buffer layout:
432 *
433 * struct data {
434 * u64 fpr[32];
435 * u64 fpscr;
436 * };
437 */
438static int fpr_get(struct task_struct *target, const struct user_regset *regset,
439 unsigned int pos, unsigned int count,
440 void *kbuf, void __user *ubuf)
441{
442#ifdef CONFIG_VSX
443 u64 buf[33];
444 int i;
445
446 flush_fp_to_thread(target);
447
448 /* copy to local buffer then write that out */
449 for (i = 0; i < 32 ; i++)
450 buf[i] = target->thread.TS_FPR(i);
451 buf[32] = target->thread.fp_state.fpscr;
452 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
453#else
454 BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) !=
455 offsetof(struct thread_fp_state, fpr[32]));
456
457 flush_fp_to_thread(target);
458
459 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
460 &target->thread.fp_state, 0, -1);
461#endif
462}
463
464/*
465 * Regardless of transactions, 'fp_state' holds the current running
466 * value of all FPR registers and 'ckfp_state' holds the last checkpointed
467 * value of all FPR registers for the current transaction.
468 *
469 * Userspace interface buffer layout:
470 *
471 * struct data {
472 * u64 fpr[32];
473 * u64 fpscr;
474 * };
475 *
476 */
477static int fpr_set(struct task_struct *target, const struct user_regset *regset,
478 unsigned int pos, unsigned int count,
479 const void *kbuf, const void __user *ubuf)
480{
481#ifdef CONFIG_VSX
482 u64 buf[33];
483 int i;
484
485 flush_fp_to_thread(target);
486
487 for (i = 0; i < 32 ; i++)
488 buf[i] = target->thread.TS_FPR(i);
489 buf[32] = target->thread.fp_state.fpscr;
490
491 /* copy to local buffer then write that out */
492 i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
493 if (i)
494 return i;
495
496 for (i = 0; i < 32 ; i++)
497 target->thread.TS_FPR(i) = buf[i];
498 target->thread.fp_state.fpscr = buf[32];
499 return 0;
500#else
501 BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) !=
502 offsetof(struct thread_fp_state, fpr[32]));
503
504 flush_fp_to_thread(target);
505
506 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
507 &target->thread.fp_state, 0, -1);
508#endif
509}
510
511#ifdef CONFIG_ALTIVEC
512/*
513 * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
514 * The transfer totals 34 quadword. Quadwords 0-31 contain the
515 * corresponding vector registers. Quadword 32 contains the vscr as the
516 * last word (offset 12) within that quadword. Quadword 33 contains the
517 * vrsave as the first word (offset 0) within the quadword.
518 *
519 * This definition of the VMX state is compatible with the current PPC32
520 * ptrace interface. This allows signal handling and ptrace to use the
521 * same structures. This also simplifies the implementation of a bi-arch
522 * (combined (32- and 64-bit) gdb.
523 */
524
525static int vr_active(struct task_struct *target,
526 const struct user_regset *regset)
527{
528 flush_altivec_to_thread(target);
529 return target->thread.used_vr ? regset->n : 0;
530}
531
532/*
533 * Regardless of transactions, 'vr_state' holds the current running
534 * value of all the VMX registers and 'ckvr_state' holds the last
535 * checkpointed value of all the VMX registers for the current
536 * transaction to fall back on in case it aborts.
537 *
538 * Userspace interface buffer layout:
539 *
540 * struct data {
541 * vector128 vr[32];
542 * vector128 vscr;
543 * vector128 vrsave;
544 * };
545 */
546static int vr_get(struct task_struct *target, const struct user_regset *regset,
547 unsigned int pos, unsigned int count,
548 void *kbuf, void __user *ubuf)
549{
550 int ret;
551
552 flush_altivec_to_thread(target);
553
554 BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) !=
555 offsetof(struct thread_vr_state, vr[32]));
556
557 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
558 &target->thread.vr_state, 0,
559 33 * sizeof(vector128));
560 if (!ret) {
561 /*
562 * Copy out only the low-order word of vrsave.
563 */
564 union {
565 elf_vrreg_t reg;
566 u32 word;
567 } vrsave;
568 memset(&vrsave, 0, sizeof(vrsave));
569
570 vrsave.word = target->thread.vrsave;
571
572 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave,
573 33 * sizeof(vector128), -1);
574 }
575
576 return ret;
577}
578
579/*
580 * Regardless of transactions, 'vr_state' holds the current running
581 * value of all the VMX registers and 'ckvr_state' holds the last
582 * checkpointed value of all the VMX registers for the current
583 * transaction to fall back on in case it aborts.
584 *
585 * Userspace interface buffer layout:
586 *
587 * struct data {
588 * vector128 vr[32];
589 * vector128 vscr;
590 * vector128 vrsave;
591 * };
592 */
593static int vr_set(struct task_struct *target, const struct user_regset *regset,
594 unsigned int pos, unsigned int count,
595 const void *kbuf, const void __user *ubuf)
596{
597 int ret;
598
599 flush_altivec_to_thread(target);
600
601 BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) !=
602 offsetof(struct thread_vr_state, vr[32]));
603
604 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
605 &target->thread.vr_state, 0,
606 33 * sizeof(vector128));
607 if (!ret && count > 0) {
608 /*
609 * We use only the first word of vrsave.
610 */
611 union {
612 elf_vrreg_t reg;
613 u32 word;
614 } vrsave;
615 memset(&vrsave, 0, sizeof(vrsave));
616
617 vrsave.word = target->thread.vrsave;
618
619 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave,
620 33 * sizeof(vector128), -1);
621 if (!ret)
622 target->thread.vrsave = vrsave.word;
623 }
624
625 return ret;
626}
627#endif /* CONFIG_ALTIVEC */
628
629#ifdef CONFIG_VSX
630/*
631 * Currently to set and and get all the vsx state, you need to call
632 * the fp and VMX calls as well. This only get/sets the lower 32
633 * 128bit VSX registers.
634 */
635
636static int vsr_active(struct task_struct *target,
637 const struct user_regset *regset)
638{
639 flush_vsx_to_thread(target);
640 return target->thread.used_vsr ? regset->n : 0;
641}
642
643/*
644 * Regardless of transactions, 'fp_state' holds the current running
645 * value of all FPR registers and 'ckfp_state' holds the last
646 * checkpointed value of all FPR registers for the current
647 * transaction.
648 *
649 * Userspace interface buffer layout:
650 *
651 * struct data {
652 * u64 vsx[32];
653 * };
654 */
655static int vsr_get(struct task_struct *target, const struct user_regset *regset,
656 unsigned int pos, unsigned int count,
657 void *kbuf, void __user *ubuf)
658{
659 u64 buf[32];
660 int ret, i;
661
662 flush_tmregs_to_thread(target);
663 flush_fp_to_thread(target);
664 flush_altivec_to_thread(target);
665 flush_vsx_to_thread(target);
666
667 for (i = 0; i < 32 ; i++)
668 buf[i] = target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET];
669
670 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
671 buf, 0, 32 * sizeof(double));
672
673 return ret;
674}
675
676/*
677 * Regardless of transactions, 'fp_state' holds the current running
678 * value of all FPR registers and 'ckfp_state' holds the last
679 * checkpointed value of all FPR registers for the current
680 * transaction.
681 *
682 * Userspace interface buffer layout:
683 *
684 * struct data {
685 * u64 vsx[32];
686 * };
687 */
688static int vsr_set(struct task_struct *target, const struct user_regset *regset,
689 unsigned int pos, unsigned int count,
690 const void *kbuf, const void __user *ubuf)
691{
692 u64 buf[32];
693 int ret,i;
694
695 flush_tmregs_to_thread(target);
696 flush_fp_to_thread(target);
697 flush_altivec_to_thread(target);
698 flush_vsx_to_thread(target);
699
700 for (i = 0; i < 32 ; i++)
701 buf[i] = target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET];
702
703 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
704 buf, 0, 32 * sizeof(double));
705 if (!ret)
706 for (i = 0; i < 32 ; i++)
707 target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET] = buf[i];
708
709 return ret;
710}
711#endif /* CONFIG_VSX */
712
713#ifdef CONFIG_SPE
714
715/*
716 * For get_evrregs/set_evrregs functions 'data' has the following layout:
717 *
718 * struct {
719 * u32 evr[32];
720 * u64 acc;
721 * u32 spefscr;
722 * }
723 */
724
725static int evr_active(struct task_struct *target,
726 const struct user_regset *regset)
727{
728 flush_spe_to_thread(target);
729 return target->thread.used_spe ? regset->n : 0;
730}
731
732static int evr_get(struct task_struct *target, const struct user_regset *regset,
733 unsigned int pos, unsigned int count,
734 void *kbuf, void __user *ubuf)
735{
736 int ret;
737
738 flush_spe_to_thread(target);
739
740 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
741 &target->thread.evr,
742 0, sizeof(target->thread.evr));
743
744 BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) !=
745 offsetof(struct thread_struct, spefscr));
746
747 if (!ret)
748 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
749 &target->thread.acc,
750 sizeof(target->thread.evr), -1);
751
752 return ret;
753}
754
755static int evr_set(struct task_struct *target, const struct user_regset *regset,
756 unsigned int pos, unsigned int count,
757 const void *kbuf, const void __user *ubuf)
758{
759 int ret;
760
761 flush_spe_to_thread(target);
762
763 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
764 &target->thread.evr,
765 0, sizeof(target->thread.evr));
766
767 BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) !=
768 offsetof(struct thread_struct, spefscr));
769
770 if (!ret)
771 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
772 &target->thread.acc,
773 sizeof(target->thread.evr), -1);
774
775 return ret;
776}
777#endif /* CONFIG_SPE */
778
779#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
780/**
781 * tm_cgpr_active - get active number of registers in CGPR
782 * @target: The target task.
783 * @regset: The user regset structure.
784 *
785 * This function checks for the active number of available
786 * regisers in transaction checkpointed GPR category.
787 */
788static int tm_cgpr_active(struct task_struct *target,
789 const struct user_regset *regset)
790{
791 if (!cpu_has_feature(CPU_FTR_TM))
792 return -ENODEV;
793
794 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
795 return 0;
796
797 return regset->n;
798}
799
800/**
801 * tm_cgpr_get - get CGPR registers
802 * @target: The target task.
803 * @regset: The user regset structure.
804 * @pos: The buffer position.
805 * @count: Number of bytes to copy.
806 * @kbuf: Kernel buffer to copy from.
807 * @ubuf: User buffer to copy into.
808 *
809 * This function gets transaction checkpointed GPR registers.
810 *
811 * When the transaction is active, 'ckpt_regs' holds all the checkpointed
812 * GPR register values for the current transaction to fall back on if it
813 * aborts in between. This function gets those checkpointed GPR registers.
814 * The userspace interface buffer layout is as follows.
815 *
816 * struct data {
817 * struct pt_regs ckpt_regs;
818 * };
819 */
820static int tm_cgpr_get(struct task_struct *target,
821 const struct user_regset *regset,
822 unsigned int pos, unsigned int count,
823 void *kbuf, void __user *ubuf)
824{
825 int ret;
826
827 if (!cpu_has_feature(CPU_FTR_TM))
828 return -ENODEV;
829
830 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
831 return -ENODATA;
832
833 flush_tmregs_to_thread(target);
834 flush_fp_to_thread(target);
835 flush_altivec_to_thread(target);
836
837 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
838 &target->thread.ckpt_regs,
839 0, offsetof(struct pt_regs, msr));
840 if (!ret) {
841 unsigned long msr = get_user_ckpt_msr(target);
842
843 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr,
844 offsetof(struct pt_regs, msr),
845 offsetof(struct pt_regs, msr) +
846 sizeof(msr));
847 }
848
849 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
850 offsetof(struct pt_regs, msr) + sizeof(long));
851
852 if (!ret)
853 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
854 &target->thread.ckpt_regs.orig_gpr3,
855 offsetof(struct pt_regs, orig_gpr3),
856 sizeof(struct pt_regs));
857 if (!ret)
858 ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
859 sizeof(struct pt_regs), -1);
860
861 return ret;
862}
863
864/*
865 * tm_cgpr_set - set the CGPR registers
866 * @target: The target task.
867 * @regset: The user regset structure.
868 * @pos: The buffer position.
869 * @count: Number of bytes to copy.
870 * @kbuf: Kernel buffer to copy into.
871 * @ubuf: User buffer to copy from.
872 *
873 * This function sets in transaction checkpointed GPR registers.
874 *
875 * When the transaction is active, 'ckpt_regs' holds the checkpointed
876 * GPR register values for the current transaction to fall back on if it
877 * aborts in between. This function sets those checkpointed GPR registers.
878 * The userspace interface buffer layout is as follows.
879 *
880 * struct data {
881 * struct pt_regs ckpt_regs;
882 * };
883 */
884static int tm_cgpr_set(struct task_struct *target,
885 const struct user_regset *regset,
886 unsigned int pos, unsigned int count,
887 const void *kbuf, const void __user *ubuf)
888{
889 unsigned long reg;
890 int ret;
891
892 if (!cpu_has_feature(CPU_FTR_TM))
893 return -ENODEV;
894
895 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
896 return -ENODATA;
897
898 flush_tmregs_to_thread(target);
899 flush_fp_to_thread(target);
900 flush_altivec_to_thread(target);
901
902 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
903 &target->thread.ckpt_regs,
904 0, PT_MSR * sizeof(reg));
905
906 if (!ret && count > 0) {
907 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®,
908 PT_MSR * sizeof(reg),
909 (PT_MSR + 1) * sizeof(reg));
910 if (!ret)
911 ret = set_user_ckpt_msr(target, reg);
912 }
913
914 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
915 offsetof(struct pt_regs, msr) + sizeof(long));
916
917 if (!ret)
918 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
919 &target->thread.ckpt_regs.orig_gpr3,
920 PT_ORIG_R3 * sizeof(reg),
921 (PT_MAX_PUT_REG + 1) * sizeof(reg));
922
923 if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret)
924 ret = user_regset_copyin_ignore(
925 &pos, &count, &kbuf, &ubuf,
926 (PT_MAX_PUT_REG + 1) * sizeof(reg),
927 PT_TRAP * sizeof(reg));
928
929 if (!ret && count > 0) {
930 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®,
931 PT_TRAP * sizeof(reg),
932 (PT_TRAP + 1) * sizeof(reg));
933 if (!ret)
934 ret = set_user_ckpt_trap(target, reg);
935 }
936
937 if (!ret)
938 ret = user_regset_copyin_ignore(
939 &pos, &count, &kbuf, &ubuf,
940 (PT_TRAP + 1) * sizeof(reg), -1);
941
942 return ret;
943}
944
945/**
946 * tm_cfpr_active - get active number of registers in CFPR
947 * @target: The target task.
948 * @regset: The user regset structure.
949 *
950 * This function checks for the active number of available
951 * regisers in transaction checkpointed FPR category.
952 */
953static int tm_cfpr_active(struct task_struct *target,
954 const struct user_regset *regset)
955{
956 if (!cpu_has_feature(CPU_FTR_TM))
957 return -ENODEV;
958
959 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
960 return 0;
961
962 return regset->n;
963}
964
965/**
966 * tm_cfpr_get - get CFPR registers
967 * @target: The target task.
968 * @regset: The user regset structure.
969 * @pos: The buffer position.
970 * @count: Number of bytes to copy.
971 * @kbuf: Kernel buffer to copy from.
972 * @ubuf: User buffer to copy into.
973 *
974 * This function gets in transaction checkpointed FPR registers.
975 *
976 * When the transaction is active 'ckfp_state' holds the checkpointed
977 * values for the current transaction to fall back on if it aborts
978 * in between. This function gets those checkpointed FPR registers.
979 * The userspace interface buffer layout is as follows.
980 *
981 * struct data {
982 * u64 fpr[32];
983 * u64 fpscr;
984 *};
985 */
986static int tm_cfpr_get(struct task_struct *target,
987 const struct user_regset *regset,
988 unsigned int pos, unsigned int count,
989 void *kbuf, void __user *ubuf)
990{
991 u64 buf[33];
992 int i;
993
994 if (!cpu_has_feature(CPU_FTR_TM))
995 return -ENODEV;
996
997 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
998 return -ENODATA;
999
1000 flush_tmregs_to_thread(target);
1001 flush_fp_to_thread(target);
1002 flush_altivec_to_thread(target);
1003
1004 /* copy to local buffer then write that out */
1005 for (i = 0; i < 32 ; i++)
1006 buf[i] = target->thread.TS_CKFPR(i);
1007 buf[32] = target->thread.ckfp_state.fpscr;
1008 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
1009}
1010
1011/**
1012 * tm_cfpr_set - set CFPR registers
1013 * @target: The target task.
1014 * @regset: The user regset structure.
1015 * @pos: The buffer position.
1016 * @count: Number of bytes to copy.
1017 * @kbuf: Kernel buffer to copy into.
1018 * @ubuf: User buffer to copy from.
1019 *
1020 * This function sets in transaction checkpointed FPR registers.
1021 *
1022 * When the transaction is active 'ckfp_state' holds the checkpointed
1023 * FPR register values for the current transaction to fall back on
1024 * if it aborts in between. This function sets these checkpointed
1025 * FPR registers. The userspace interface buffer layout is as follows.
1026 *
1027 * struct data {
1028 * u64 fpr[32];
1029 * u64 fpscr;
1030 *};
1031 */
1032static int tm_cfpr_set(struct task_struct *target,
1033 const struct user_regset *regset,
1034 unsigned int pos, unsigned int count,
1035 const void *kbuf, const void __user *ubuf)
1036{
1037 u64 buf[33];
1038 int i;
1039
1040 if (!cpu_has_feature(CPU_FTR_TM))
1041 return -ENODEV;
1042
1043 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1044 return -ENODATA;
1045
1046 flush_tmregs_to_thread(target);
1047 flush_fp_to_thread(target);
1048 flush_altivec_to_thread(target);
1049
1050 for (i = 0; i < 32; i++)
1051 buf[i] = target->thread.TS_CKFPR(i);
1052 buf[32] = target->thread.ckfp_state.fpscr;
1053
1054 /* copy to local buffer then write that out */
1055 i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
1056 if (i)
1057 return i;
1058 for (i = 0; i < 32 ; i++)
1059 target->thread.TS_CKFPR(i) = buf[i];
1060 target->thread.ckfp_state.fpscr = buf[32];
1061 return 0;
1062}
1063
1064/**
1065 * tm_cvmx_active - get active number of registers in CVMX
1066 * @target: The target task.
1067 * @regset: The user regset structure.
1068 *
1069 * This function checks for the active number of available
1070 * regisers in checkpointed VMX category.
1071 */
1072static int tm_cvmx_active(struct task_struct *target,
1073 const struct user_regset *regset)
1074{
1075 if (!cpu_has_feature(CPU_FTR_TM))
1076 return -ENODEV;
1077
1078 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1079 return 0;
1080
1081 return regset->n;
1082}
1083
1084/**
1085 * tm_cvmx_get - get CMVX registers
1086 * @target: The target task.
1087 * @regset: The user regset structure.
1088 * @pos: The buffer position.
1089 * @count: Number of bytes to copy.
1090 * @kbuf: Kernel buffer to copy from.
1091 * @ubuf: User buffer to copy into.
1092 *
1093 * This function gets in transaction checkpointed VMX registers.
1094 *
1095 * When the transaction is active 'ckvr_state' and 'ckvrsave' hold
1096 * the checkpointed values for the current transaction to fall
1097 * back on if it aborts in between. The userspace interface buffer
1098 * layout is as follows.
1099 *
1100 * struct data {
1101 * vector128 vr[32];
1102 * vector128 vscr;
1103 * vector128 vrsave;
1104 *};
1105 */
1106static int tm_cvmx_get(struct task_struct *target,
1107 const struct user_regset *regset,
1108 unsigned int pos, unsigned int count,
1109 void *kbuf, void __user *ubuf)
1110{
1111 int ret;
1112
1113 BUILD_BUG_ON(TVSO(vscr) != TVSO(vr[32]));
1114
1115 if (!cpu_has_feature(CPU_FTR_TM))
1116 return -ENODEV;
1117
1118 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1119 return -ENODATA;
1120
1121 /* Flush the state */
1122 flush_tmregs_to_thread(target);
1123 flush_fp_to_thread(target);
1124 flush_altivec_to_thread(target);
1125
1126 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1127 &target->thread.ckvr_state, 0,
1128 33 * sizeof(vector128));
1129 if (!ret) {
1130 /*
1131 * Copy out only the low-order word of vrsave.
1132 */
1133 union {
1134 elf_vrreg_t reg;
1135 u32 word;
1136 } vrsave;
1137 memset(&vrsave, 0, sizeof(vrsave));
1138 vrsave.word = target->thread.ckvrsave;
1139 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave,
1140 33 * sizeof(vector128), -1);
1141 }
1142
1143 return ret;
1144}
1145
1146/**
1147 * tm_cvmx_set - set CMVX registers
1148 * @target: The target task.
1149 * @regset: The user regset structure.
1150 * @pos: The buffer position.
1151 * @count: Number of bytes to copy.
1152 * @kbuf: Kernel buffer to copy into.
1153 * @ubuf: User buffer to copy from.
1154 *
1155 * This function sets in transaction checkpointed VMX registers.
1156 *
1157 * When the transaction is active 'ckvr_state' and 'ckvrsave' hold
1158 * the checkpointed values for the current transaction to fall
1159 * back on if it aborts in between. The userspace interface buffer
1160 * layout is as follows.
1161 *
1162 * struct data {
1163 * vector128 vr[32];
1164 * vector128 vscr;
1165 * vector128 vrsave;
1166 *};
1167 */
1168static int tm_cvmx_set(struct task_struct *target,
1169 const struct user_regset *regset,
1170 unsigned int pos, unsigned int count,
1171 const void *kbuf, const void __user *ubuf)
1172{
1173 int ret;
1174
1175 BUILD_BUG_ON(TVSO(vscr) != TVSO(vr[32]));
1176
1177 if (!cpu_has_feature(CPU_FTR_TM))
1178 return -ENODEV;
1179
1180 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1181 return -ENODATA;
1182
1183 flush_tmregs_to_thread(target);
1184 flush_fp_to_thread(target);
1185 flush_altivec_to_thread(target);
1186
1187 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1188 &target->thread.ckvr_state, 0,
1189 33 * sizeof(vector128));
1190 if (!ret && count > 0) {
1191 /*
1192 * We use only the low-order word of vrsave.
1193 */
1194 union {
1195 elf_vrreg_t reg;
1196 u32 word;
1197 } vrsave;
1198 memset(&vrsave, 0, sizeof(vrsave));
1199 vrsave.word = target->thread.ckvrsave;
1200 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave,
1201 33 * sizeof(vector128), -1);
1202 if (!ret)
1203 target->thread.ckvrsave = vrsave.word;
1204 }
1205
1206 return ret;
1207}
1208
1209/**
1210 * tm_cvsx_active - get active number of registers in CVSX
1211 * @target: The target task.
1212 * @regset: The user regset structure.
1213 *
1214 * This function checks for the active number of available
1215 * regisers in transaction checkpointed VSX category.
1216 */
1217static int tm_cvsx_active(struct task_struct *target,
1218 const struct user_regset *regset)
1219{
1220 if (!cpu_has_feature(CPU_FTR_TM))
1221 return -ENODEV;
1222
1223 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1224 return 0;
1225
1226 flush_vsx_to_thread(target);
1227 return target->thread.used_vsr ? regset->n : 0;
1228}
1229
1230/**
1231 * tm_cvsx_get - get CVSX registers
1232 * @target: The target task.
1233 * @regset: The user regset structure.
1234 * @pos: The buffer position.
1235 * @count: Number of bytes to copy.
1236 * @kbuf: Kernel buffer to copy from.
1237 * @ubuf: User buffer to copy into.
1238 *
1239 * This function gets in transaction checkpointed VSX registers.
1240 *
1241 * When the transaction is active 'ckfp_state' holds the checkpointed
1242 * values for the current transaction to fall back on if it aborts
1243 * in between. This function gets those checkpointed VSX registers.
1244 * The userspace interface buffer layout is as follows.
1245 *
1246 * struct data {
1247 * u64 vsx[32];
1248 *};
1249 */
1250static int tm_cvsx_get(struct task_struct *target,
1251 const struct user_regset *regset,
1252 unsigned int pos, unsigned int count,
1253 void *kbuf, void __user *ubuf)
1254{
1255 u64 buf[32];
1256 int ret, i;
1257
1258 if (!cpu_has_feature(CPU_FTR_TM))
1259 return -ENODEV;
1260
1261 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1262 return -ENODATA;
1263
1264 /* Flush the state */
1265 flush_tmregs_to_thread(target);
1266 flush_fp_to_thread(target);
1267 flush_altivec_to_thread(target);
1268 flush_vsx_to_thread(target);
1269
1270 for (i = 0; i < 32 ; i++)
1271 buf[i] = target->thread.ckfp_state.fpr[i][TS_VSRLOWOFFSET];
1272 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1273 buf, 0, 32 * sizeof(double));
1274
1275 return ret;
1276}
1277
1278/**
1279 * tm_cvsx_set - set CFPR registers
1280 * @target: The target task.
1281 * @regset: The user regset structure.
1282 * @pos: The buffer position.
1283 * @count: Number of bytes to copy.
1284 * @kbuf: Kernel buffer to copy into.
1285 * @ubuf: User buffer to copy from.
1286 *
1287 * This function sets in transaction checkpointed VSX registers.
1288 *
1289 * When the transaction is active 'ckfp_state' holds the checkpointed
1290 * VSX register values for the current transaction to fall back on
1291 * if it aborts in between. This function sets these checkpointed
1292 * FPR registers. The userspace interface buffer layout is as follows.
1293 *
1294 * struct data {
1295 * u64 vsx[32];
1296 *};
1297 */
1298static int tm_cvsx_set(struct task_struct *target,
1299 const struct user_regset *regset,
1300 unsigned int pos, unsigned int count,
1301 const void *kbuf, const void __user *ubuf)
1302{
1303 u64 buf[32];
1304 int ret, i;
1305
1306 if (!cpu_has_feature(CPU_FTR_TM))
1307 return -ENODEV;
1308
1309 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1310 return -ENODATA;
1311
1312 /* Flush the state */
1313 flush_tmregs_to_thread(target);
1314 flush_fp_to_thread(target);
1315 flush_altivec_to_thread(target);
1316 flush_vsx_to_thread(target);
1317
1318 for (i = 0; i < 32 ; i++)
1319 buf[i] = target->thread.ckfp_state.fpr[i][TS_VSRLOWOFFSET];
1320
1321 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1322 buf, 0, 32 * sizeof(double));
1323 if (!ret)
1324 for (i = 0; i < 32 ; i++)
1325 target->thread.ckfp_state.fpr[i][TS_VSRLOWOFFSET] = buf[i];
1326
1327 return ret;
1328}
1329
1330/**
1331 * tm_spr_active - get active number of registers in TM SPR
1332 * @target: The target task.
1333 * @regset: The user regset structure.
1334 *
1335 * This function checks the active number of available
1336 * regisers in the transactional memory SPR category.
1337 */
1338static int tm_spr_active(struct task_struct *target,
1339 const struct user_regset *regset)
1340{
1341 if (!cpu_has_feature(CPU_FTR_TM))
1342 return -ENODEV;
1343
1344 return regset->n;
1345}
1346
1347/**
1348 * tm_spr_get - get the TM related SPR registers
1349 * @target: The target task.
1350 * @regset: The user regset structure.
1351 * @pos: The buffer position.
1352 * @count: Number of bytes to copy.
1353 * @kbuf: Kernel buffer to copy from.
1354 * @ubuf: User buffer to copy into.
1355 *
1356 * This function gets transactional memory related SPR registers.
1357 * The userspace interface buffer layout is as follows.
1358 *
1359 * struct {
1360 * u64 tm_tfhar;
1361 * u64 tm_texasr;
1362 * u64 tm_tfiar;
1363 * };
1364 */
1365static int tm_spr_get(struct task_struct *target,
1366 const struct user_regset *regset,
1367 unsigned int pos, unsigned int count,
1368 void *kbuf, void __user *ubuf)
1369{
1370 int ret;
1371
1372 /* Build tests */
1373 BUILD_BUG_ON(TSO(tm_tfhar) + sizeof(u64) != TSO(tm_texasr));
1374 BUILD_BUG_ON(TSO(tm_texasr) + sizeof(u64) != TSO(tm_tfiar));
1375 BUILD_BUG_ON(TSO(tm_tfiar) + sizeof(u64) != TSO(ckpt_regs));
1376
1377 if (!cpu_has_feature(CPU_FTR_TM))
1378 return -ENODEV;
1379
1380 /* Flush the states */
1381 flush_tmregs_to_thread(target);
1382 flush_fp_to_thread(target);
1383 flush_altivec_to_thread(target);
1384
1385 /* TFHAR register */
1386 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1387 &target->thread.tm_tfhar, 0, sizeof(u64));
1388
1389 /* TEXASR register */
1390 if (!ret)
1391 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1392 &target->thread.tm_texasr, sizeof(u64),
1393 2 * sizeof(u64));
1394
1395 /* TFIAR register */
1396 if (!ret)
1397 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1398 &target->thread.tm_tfiar,
1399 2 * sizeof(u64), 3 * sizeof(u64));
1400 return ret;
1401}
1402
1403/**
1404 * tm_spr_set - set the TM related SPR registers
1405 * @target: The target task.
1406 * @regset: The user regset structure.
1407 * @pos: The buffer position.
1408 * @count: Number of bytes to copy.
1409 * @kbuf: Kernel buffer to copy into.
1410 * @ubuf: User buffer to copy from.
1411 *
1412 * This function sets transactional memory related SPR registers.
1413 * The userspace interface buffer layout is as follows.
1414 *
1415 * struct {
1416 * u64 tm_tfhar;
1417 * u64 tm_texasr;
1418 * u64 tm_tfiar;
1419 * };
1420 */
1421static int tm_spr_set(struct task_struct *target,
1422 const struct user_regset *regset,
1423 unsigned int pos, unsigned int count,
1424 const void *kbuf, const void __user *ubuf)
1425{
1426 int ret;
1427
1428 /* Build tests */
1429 BUILD_BUG_ON(TSO(tm_tfhar) + sizeof(u64) != TSO(tm_texasr));
1430 BUILD_BUG_ON(TSO(tm_texasr) + sizeof(u64) != TSO(tm_tfiar));
1431 BUILD_BUG_ON(TSO(tm_tfiar) + sizeof(u64) != TSO(ckpt_regs));
1432
1433 if (!cpu_has_feature(CPU_FTR_TM))
1434 return -ENODEV;
1435
1436 /* Flush the states */
1437 flush_tmregs_to_thread(target);
1438 flush_fp_to_thread(target);
1439 flush_altivec_to_thread(target);
1440
1441 /* TFHAR register */
1442 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1443 &target->thread.tm_tfhar, 0, sizeof(u64));
1444
1445 /* TEXASR register */
1446 if (!ret)
1447 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1448 &target->thread.tm_texasr, sizeof(u64),
1449 2 * sizeof(u64));
1450
1451 /* TFIAR register */
1452 if (!ret)
1453 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1454 &target->thread.tm_tfiar,
1455 2 * sizeof(u64), 3 * sizeof(u64));
1456 return ret;
1457}
1458
1459static int tm_tar_active(struct task_struct *target,
1460 const struct user_regset *regset)
1461{
1462 if (!cpu_has_feature(CPU_FTR_TM))
1463 return -ENODEV;
1464
1465 if (MSR_TM_ACTIVE(target->thread.regs->msr))
1466 return regset->n;
1467
1468 return 0;
1469}
1470
1471static int tm_tar_get(struct task_struct *target,
1472 const struct user_regset *regset,
1473 unsigned int pos, unsigned int count,
1474 void *kbuf, void __user *ubuf)
1475{
1476 int ret;
1477
1478 if (!cpu_has_feature(CPU_FTR_TM))
1479 return -ENODEV;
1480
1481 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1482 return -ENODATA;
1483
1484 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1485 &target->thread.tm_tar, 0, sizeof(u64));
1486 return ret;
1487}
1488
1489static int tm_tar_set(struct task_struct *target,
1490 const struct user_regset *regset,
1491 unsigned int pos, unsigned int count,
1492 const void *kbuf, const void __user *ubuf)
1493{
1494 int ret;
1495
1496 if (!cpu_has_feature(CPU_FTR_TM))
1497 return -ENODEV;
1498
1499 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1500 return -ENODATA;
1501
1502 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1503 &target->thread.tm_tar, 0, sizeof(u64));
1504 return ret;
1505}
1506
1507static int tm_ppr_active(struct task_struct *target,
1508 const struct user_regset *regset)
1509{
1510 if (!cpu_has_feature(CPU_FTR_TM))
1511 return -ENODEV;
1512
1513 if (MSR_TM_ACTIVE(target->thread.regs->msr))
1514 return regset->n;
1515
1516 return 0;
1517}
1518
1519
1520static int tm_ppr_get(struct task_struct *target,
1521 const struct user_regset *regset,
1522 unsigned int pos, unsigned int count,
1523 void *kbuf, void __user *ubuf)
1524{
1525 int ret;
1526
1527 if (!cpu_has_feature(CPU_FTR_TM))
1528 return -ENODEV;
1529
1530 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1531 return -ENODATA;
1532
1533 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1534 &target->thread.tm_ppr, 0, sizeof(u64));
1535 return ret;
1536}
1537
1538static int tm_ppr_set(struct task_struct *target,
1539 const struct user_regset *regset,
1540 unsigned int pos, unsigned int count,
1541 const void *kbuf, const void __user *ubuf)
1542{
1543 int ret;
1544
1545 if (!cpu_has_feature(CPU_FTR_TM))
1546 return -ENODEV;
1547
1548 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1549 return -ENODATA;
1550
1551 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1552 &target->thread.tm_ppr, 0, sizeof(u64));
1553 return ret;
1554}
1555
1556static int tm_dscr_active(struct task_struct *target,
1557 const struct user_regset *regset)
1558{
1559 if (!cpu_has_feature(CPU_FTR_TM))
1560 return -ENODEV;
1561
1562 if (MSR_TM_ACTIVE(target->thread.regs->msr))
1563 return regset->n;
1564
1565 return 0;
1566}
1567
1568static int tm_dscr_get(struct task_struct *target,
1569 const struct user_regset *regset,
1570 unsigned int pos, unsigned int count,
1571 void *kbuf, void __user *ubuf)
1572{
1573 int ret;
1574
1575 if (!cpu_has_feature(CPU_FTR_TM))
1576 return -ENODEV;
1577
1578 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1579 return -ENODATA;
1580
1581 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1582 &target->thread.tm_dscr, 0, sizeof(u64));
1583 return ret;
1584}
1585
1586static int tm_dscr_set(struct task_struct *target,
1587 const struct user_regset *regset,
1588 unsigned int pos, unsigned int count,
1589 const void *kbuf, const void __user *ubuf)
1590{
1591 int ret;
1592
1593 if (!cpu_has_feature(CPU_FTR_TM))
1594 return -ENODEV;
1595
1596 if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1597 return -ENODATA;
1598
1599 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1600 &target->thread.tm_dscr, 0, sizeof(u64));
1601 return ret;
1602}
1603#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1604
1605#ifdef CONFIG_PPC64
1606static int ppr_get(struct task_struct *target,
1607 const struct user_regset *regset,
1608 unsigned int pos, unsigned int count,
1609 void *kbuf, void __user *ubuf)
1610{
1611 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1612 &target->thread.ppr, 0, sizeof(u64));
1613}
1614
1615static int ppr_set(struct task_struct *target,
1616 const struct user_regset *regset,
1617 unsigned int pos, unsigned int count,
1618 const void *kbuf, const void __user *ubuf)
1619{
1620 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1621 &target->thread.ppr, 0, sizeof(u64));
1622}
1623
1624static int dscr_get(struct task_struct *target,
1625 const struct user_regset *regset,
1626 unsigned int pos, unsigned int count,
1627 void *kbuf, void __user *ubuf)
1628{
1629 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1630 &target->thread.dscr, 0, sizeof(u64));
1631}
1632static int dscr_set(struct task_struct *target,
1633 const struct user_regset *regset,
1634 unsigned int pos, unsigned int count,
1635 const void *kbuf, const void __user *ubuf)
1636{
1637 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1638 &target->thread.dscr, 0, sizeof(u64));
1639}
1640#endif
1641#ifdef CONFIG_PPC_BOOK3S_64
1642static int tar_get(struct task_struct *target,
1643 const struct user_regset *regset,
1644 unsigned int pos, unsigned int count,
1645 void *kbuf, void __user *ubuf)
1646{
1647 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1648 &target->thread.tar, 0, sizeof(u64));
1649}
1650static int tar_set(struct task_struct *target,
1651 const struct user_regset *regset,
1652 unsigned int pos, unsigned int count,
1653 const void *kbuf, const void __user *ubuf)
1654{
1655 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1656 &target->thread.tar, 0, sizeof(u64));
1657}
1658
1659static int ebb_active(struct task_struct *target,
1660 const struct user_regset *regset)
1661{
1662 if (!cpu_has_feature(CPU_FTR_ARCH_207S))
1663 return -ENODEV;
1664
1665 if (target->thread.used_ebb)
1666 return regset->n;
1667
1668 return 0;
1669}
1670
1671static int ebb_get(struct task_struct *target,
1672 const struct user_regset *regset,
1673 unsigned int pos, unsigned int count,
1674 void *kbuf, void __user *ubuf)
1675{
1676 /* Build tests */
1677 BUILD_BUG_ON(TSO(ebbrr) + sizeof(unsigned long) != TSO(ebbhr));
1678 BUILD_BUG_ON(TSO(ebbhr) + sizeof(unsigned long) != TSO(bescr));
1679
1680 if (!cpu_has_feature(CPU_FTR_ARCH_207S))
1681 return -ENODEV;
1682
1683 if (!target->thread.used_ebb)
1684 return -ENODATA;
1685
1686 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1687 &target->thread.ebbrr, 0, 3 * sizeof(unsigned long));
1688}
1689
1690static int ebb_set(struct task_struct *target,
1691 const struct user_regset *regset,
1692 unsigned int pos, unsigned int count,
1693 const void *kbuf, const void __user *ubuf)
1694{
1695 int ret = 0;
1696
1697 /* Build tests */
1698 BUILD_BUG_ON(TSO(ebbrr) + sizeof(unsigned long) != TSO(ebbhr));
1699 BUILD_BUG_ON(TSO(ebbhr) + sizeof(unsigned long) != TSO(bescr));
1700
1701 if (!cpu_has_feature(CPU_FTR_ARCH_207S))
1702 return -ENODEV;
1703
1704 if (target->thread.used_ebb)
1705 return -ENODATA;
1706
1707 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1708 &target->thread.ebbrr, 0, sizeof(unsigned long));
1709
1710 if (!ret)
1711 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1712 &target->thread.ebbhr, sizeof(unsigned long),
1713 2 * sizeof(unsigned long));
1714
1715 if (!ret)
1716 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1717 &target->thread.bescr,
1718 2 * sizeof(unsigned long), 3 * sizeof(unsigned long));
1719
1720 return ret;
1721}
1722static int pmu_active(struct task_struct *target,
1723 const struct user_regset *regset)
1724{
1725 if (!cpu_has_feature(CPU_FTR_ARCH_207S))
1726 return -ENODEV;
1727
1728 return regset->n;
1729}
1730
1731static int pmu_get(struct task_struct *target,
1732 const struct user_regset *regset,
1733 unsigned int pos, unsigned int count,
1734 void *kbuf, void __user *ubuf)
1735{
1736 /* Build tests */
1737 BUILD_BUG_ON(TSO(siar) + sizeof(unsigned long) != TSO(sdar));
1738 BUILD_BUG_ON(TSO(sdar) + sizeof(unsigned long) != TSO(sier));
1739 BUILD_BUG_ON(TSO(sier) + sizeof(unsigned long) != TSO(mmcr2));
1740 BUILD_BUG_ON(TSO(mmcr2) + sizeof(unsigned long) != TSO(mmcr0));
1741
1742 if (!cpu_has_feature(CPU_FTR_ARCH_207S))
1743 return -ENODEV;
1744
1745 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1746 &target->thread.siar, 0,
1747 5 * sizeof(unsigned long));
1748}
1749
1750static int pmu_set(struct task_struct *target,
1751 const struct user_regset *regset,
1752 unsigned int pos, unsigned int count,
1753 const void *kbuf, const void __user *ubuf)
1754{
1755 int ret = 0;
1756
1757 /* Build tests */
1758 BUILD_BUG_ON(TSO(siar) + sizeof(unsigned long) != TSO(sdar));
1759 BUILD_BUG_ON(TSO(sdar) + sizeof(unsigned long) != TSO(sier));
1760 BUILD_BUG_ON(TSO(sier) + sizeof(unsigned long) != TSO(mmcr2));
1761 BUILD_BUG_ON(TSO(mmcr2) + sizeof(unsigned long) != TSO(mmcr0));
1762
1763 if (!cpu_has_feature(CPU_FTR_ARCH_207S))
1764 return -ENODEV;
1765
1766 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1767 &target->thread.siar, 0,
1768 sizeof(unsigned long));
1769
1770 if (!ret)
1771 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1772 &target->thread.sdar, sizeof(unsigned long),
1773 2 * sizeof(unsigned long));
1774
1775 if (!ret)
1776 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1777 &target->thread.sier, 2 * sizeof(unsigned long),
1778 3 * sizeof(unsigned long));
1779
1780 if (!ret)
1781 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1782 &target->thread.mmcr2, 3 * sizeof(unsigned long),
1783 4 * sizeof(unsigned long));
1784
1785 if (!ret)
1786 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1787 &target->thread.mmcr0, 4 * sizeof(unsigned long),
1788 5 * sizeof(unsigned long));
1789 return ret;
1790}
1791#endif
1792
1793#ifdef CONFIG_PPC_MEM_KEYS
1794static int pkey_active(struct task_struct *target,
1795 const struct user_regset *regset)
1796{
1797 if (!arch_pkeys_enabled())
1798 return -ENODEV;
1799
1800 return regset->n;
1801}
1802
1803static int pkey_get(struct task_struct *target,
1804 const struct user_regset *regset,
1805 unsigned int pos, unsigned int count,
1806 void *kbuf, void __user *ubuf)
1807{
1808 BUILD_BUG_ON(TSO(amr) + sizeof(unsigned long) != TSO(iamr));
1809 BUILD_BUG_ON(TSO(iamr) + sizeof(unsigned long) != TSO(uamor));
1810
1811 if (!arch_pkeys_enabled())
1812 return -ENODEV;
1813
1814 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1815 &target->thread.amr, 0,
1816 ELF_NPKEY * sizeof(unsigned long));
1817}
1818
1819static int pkey_set(struct task_struct *target,
1820 const struct user_regset *regset,
1821 unsigned int pos, unsigned int count,
1822 const void *kbuf, const void __user *ubuf)
1823{
1824 u64 new_amr;
1825 int ret;
1826
1827 if (!arch_pkeys_enabled())
1828 return -ENODEV;
1829
1830 /* Only the AMR can be set from userspace */
1831 if (pos != 0 || count != sizeof(new_amr))
1832 return -EINVAL;
1833
1834 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1835 &new_amr, 0, sizeof(new_amr));
1836 if (ret)
1837 return ret;
1838
1839 /* UAMOR determines which bits of the AMR can be set from userspace. */
1840 target->thread.amr = (new_amr & target->thread.uamor) |
1841 (target->thread.amr & ~target->thread.uamor);
1842
1843 return 0;
1844}
1845#endif /* CONFIG_PPC_MEM_KEYS */
1846
1847/*
1848 * These are our native regset flavors.
1849 */
1850enum powerpc_regset {
1851 REGSET_GPR,
1852 REGSET_FPR,
1853#ifdef CONFIG_ALTIVEC
1854 REGSET_VMX,
1855#endif
1856#ifdef CONFIG_VSX
1857 REGSET_VSX,
1858#endif
1859#ifdef CONFIG_SPE
1860 REGSET_SPE,
1861#endif
1862#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1863 REGSET_TM_CGPR, /* TM checkpointed GPR registers */
1864 REGSET_TM_CFPR, /* TM checkpointed FPR registers */
1865 REGSET_TM_CVMX, /* TM checkpointed VMX registers */
1866 REGSET_TM_CVSX, /* TM checkpointed VSX registers */
1867 REGSET_TM_SPR, /* TM specific SPR registers */
1868 REGSET_TM_CTAR, /* TM checkpointed TAR register */
1869 REGSET_TM_CPPR, /* TM checkpointed PPR register */
1870 REGSET_TM_CDSCR, /* TM checkpointed DSCR register */
1871#endif
1872#ifdef CONFIG_PPC64
1873 REGSET_PPR, /* PPR register */
1874 REGSET_DSCR, /* DSCR register */
1875#endif
1876#ifdef CONFIG_PPC_BOOK3S_64
1877 REGSET_TAR, /* TAR register */
1878 REGSET_EBB, /* EBB registers */
1879 REGSET_PMR, /* Performance Monitor Registers */
1880#endif
1881#ifdef CONFIG_PPC_MEM_KEYS
1882 REGSET_PKEY, /* AMR register */
1883#endif
1884};
1885
1886static const struct user_regset native_regsets[] = {
1887 [REGSET_GPR] = {
1888 .core_note_type = NT_PRSTATUS, .n = ELF_NGREG,
1889 .size = sizeof(long), .align = sizeof(long),
1890 .get = gpr_get, .set = gpr_set
1891 },
1892 [REGSET_FPR] = {
1893 .core_note_type = NT_PRFPREG, .n = ELF_NFPREG,
1894 .size = sizeof(double), .align = sizeof(double),
1895 .get = fpr_get, .set = fpr_set
1896 },
1897#ifdef CONFIG_ALTIVEC
1898 [REGSET_VMX] = {
1899 .core_note_type = NT_PPC_VMX, .n = 34,
1900 .size = sizeof(vector128), .align = sizeof(vector128),
1901 .active = vr_active, .get = vr_get, .set = vr_set
1902 },
1903#endif
1904#ifdef CONFIG_VSX
1905 [REGSET_VSX] = {
1906 .core_note_type = NT_PPC_VSX, .n = 32,
1907 .size = sizeof(double), .align = sizeof(double),
1908 .active = vsr_active, .get = vsr_get, .set = vsr_set
1909 },
1910#endif
1911#ifdef CONFIG_SPE
1912 [REGSET_SPE] = {
1913 .core_note_type = NT_PPC_SPE, .n = 35,
1914 .size = sizeof(u32), .align = sizeof(u32),
1915 .active = evr_active, .get = evr_get, .set = evr_set
1916 },
1917#endif
1918#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1919 [REGSET_TM_CGPR] = {
1920 .core_note_type = NT_PPC_TM_CGPR, .n = ELF_NGREG,
1921 .size = sizeof(long), .align = sizeof(long),
1922 .active = tm_cgpr_active, .get = tm_cgpr_get, .set = tm_cgpr_set
1923 },
1924 [REGSET_TM_CFPR] = {
1925 .core_note_type = NT_PPC_TM_CFPR, .n = ELF_NFPREG,
1926 .size = sizeof(double), .align = sizeof(double),
1927 .active = tm_cfpr_active, .get = tm_cfpr_get, .set = tm_cfpr_set
1928 },
1929 [REGSET_TM_CVMX] = {
1930 .core_note_type = NT_PPC_TM_CVMX, .n = ELF_NVMX,
1931 .size = sizeof(vector128), .align = sizeof(vector128),
1932 .active = tm_cvmx_active, .get = tm_cvmx_get, .set = tm_cvmx_set
1933 },
1934 [REGSET_TM_CVSX] = {
1935 .core_note_type = NT_PPC_TM_CVSX, .n = ELF_NVSX,
1936 .size = sizeof(double), .align = sizeof(double),
1937 .active = tm_cvsx_active, .get = tm_cvsx_get, .set = tm_cvsx_set
1938 },
1939 [REGSET_TM_SPR] = {
1940 .core_note_type = NT_PPC_TM_SPR, .n = ELF_NTMSPRREG,
1941 .size = sizeof(u64), .align = sizeof(u64),
1942 .active = tm_spr_active, .get = tm_spr_get, .set = tm_spr_set
1943 },
1944 [REGSET_TM_CTAR] = {
1945 .core_note_type = NT_PPC_TM_CTAR, .n = 1,
1946 .size = sizeof(u64), .align = sizeof(u64),
1947 .active = tm_tar_active, .get = tm_tar_get, .set = tm_tar_set
1948 },
1949 [REGSET_TM_CPPR] = {
1950 .core_note_type = NT_PPC_TM_CPPR, .n = 1,
1951 .size = sizeof(u64), .align = sizeof(u64),
1952 .active = tm_ppr_active, .get = tm_ppr_get, .set = tm_ppr_set
1953 },
1954 [REGSET_TM_CDSCR] = {
1955 .core_note_type = NT_PPC_TM_CDSCR, .n = 1,
1956 .size = sizeof(u64), .align = sizeof(u64),
1957 .active = tm_dscr_active, .get = tm_dscr_get, .set = tm_dscr_set
1958 },
1959#endif
1960#ifdef CONFIG_PPC64
1961 [REGSET_PPR] = {
1962 .core_note_type = NT_PPC_PPR, .n = 1,
1963 .size = sizeof(u64), .align = sizeof(u64),
1964 .get = ppr_get, .set = ppr_set
1965 },
1966 [REGSET_DSCR] = {
1967 .core_note_type = NT_PPC_DSCR, .n = 1,
1968 .size = sizeof(u64), .align = sizeof(u64),
1969 .get = dscr_get, .set = dscr_set
1970 },
1971#endif
1972#ifdef CONFIG_PPC_BOOK3S_64
1973 [REGSET_TAR] = {
1974 .core_note_type = NT_PPC_TAR, .n = 1,
1975 .size = sizeof(u64), .align = sizeof(u64),
1976 .get = tar_get, .set = tar_set
1977 },
1978 [REGSET_EBB] = {
1979 .core_note_type = NT_PPC_EBB, .n = ELF_NEBB,
1980 .size = sizeof(u64), .align = sizeof(u64),
1981 .active = ebb_active, .get = ebb_get, .set = ebb_set
1982 },
1983 [REGSET_PMR] = {
1984 .core_note_type = NT_PPC_PMU, .n = ELF_NPMU,
1985 .size = sizeof(u64), .align = sizeof(u64),
1986 .active = pmu_active, .get = pmu_get, .set = pmu_set
1987 },
1988#endif
1989#ifdef CONFIG_PPC_MEM_KEYS
1990 [REGSET_PKEY] = {
1991 .core_note_type = NT_PPC_PKEY, .n = ELF_NPKEY,
1992 .size = sizeof(u64), .align = sizeof(u64),
1993 .active = pkey_active, .get = pkey_get, .set = pkey_set
1994 },
1995#endif
1996};
1997
1998static const struct user_regset_view user_ppc_native_view = {
1999 .name = UTS_MACHINE, .e_machine = ELF_ARCH, .ei_osabi = ELF_OSABI,
2000 .regsets = native_regsets, .n = ARRAY_SIZE(native_regsets)
2001};
2002
2003#ifdef CONFIG_PPC64
2004#include <linux/compat.h>
2005
2006static int gpr32_get_common(struct task_struct *target,
2007 const struct user_regset *regset,
2008 unsigned int pos, unsigned int count,
2009 void *kbuf, void __user *ubuf,
2010 unsigned long *regs)
2011{
2012 compat_ulong_t *k = kbuf;
2013 compat_ulong_t __user *u = ubuf;
2014 compat_ulong_t reg;
2015
2016 pos /= sizeof(reg);
2017 count /= sizeof(reg);
2018
2019 if (kbuf)
2020 for (; count > 0 && pos < PT_MSR; --count)
2021 *k++ = regs[pos++];
2022 else
2023 for (; count > 0 && pos < PT_MSR; --count)
2024 if (__put_user((compat_ulong_t) regs[pos++], u++))
2025 return -EFAULT;
2026
2027 if (count > 0 && pos == PT_MSR) {
2028 reg = get_user_msr(target);
2029 if (kbuf)
2030 *k++ = reg;
2031 else if (__put_user(reg, u++))
2032 return -EFAULT;
2033 ++pos;
2034 --count;
2035 }
2036
2037 if (kbuf)
2038 for (; count > 0 && pos < PT_REGS_COUNT; --count)
2039 *k++ = regs[pos++];
2040 else
2041 for (; count > 0 && pos < PT_REGS_COUNT; --count)
2042 if (__put_user((compat_ulong_t) regs[pos++], u++))
2043 return -EFAULT;
2044
2045 kbuf = k;
2046 ubuf = u;
2047 pos *= sizeof(reg);
2048 count *= sizeof(reg);
2049 return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
2050 PT_REGS_COUNT * sizeof(reg), -1);
2051}
2052
2053static int gpr32_set_common(struct task_struct *target,
2054 const struct user_regset *regset,
2055 unsigned int pos, unsigned int count,
2056 const void *kbuf, const void __user *ubuf,
2057 unsigned long *regs)
2058{
2059 const compat_ulong_t *k = kbuf;
2060 const compat_ulong_t __user *u = ubuf;
2061 compat_ulong_t reg;
2062
2063 pos /= sizeof(reg);
2064 count /= sizeof(reg);
2065
2066 if (kbuf)
2067 for (; count > 0 && pos < PT_MSR; --count)
2068 regs[pos++] = *k++;
2069 else
2070 for (; count > 0 && pos < PT_MSR; --count) {
2071 if (__get_user(reg, u++))
2072 return -EFAULT;
2073 regs[pos++] = reg;
2074 }
2075
2076
2077 if (count > 0 && pos == PT_MSR) {
2078 if (kbuf)
2079 reg = *k++;
2080 else if (__get_user(reg, u++))
2081 return -EFAULT;
2082 set_user_msr(target, reg);
2083 ++pos;
2084 --count;
2085 }
2086
2087 if (kbuf) {
2088 for (; count > 0 && pos <= PT_MAX_PUT_REG; --count)
2089 regs[pos++] = *k++;
2090 for (; count > 0 && pos < PT_TRAP; --count, ++pos)
2091 ++k;
2092 } else {
2093 for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) {
2094 if (__get_user(reg, u++))
2095 return -EFAULT;
2096 regs[pos++] = reg;
2097 }
2098 for (; count > 0 && pos < PT_TRAP; --count, ++pos)
2099 if (__get_user(reg, u++))
2100 return -EFAULT;
2101 }
2102
2103 if (count > 0 && pos == PT_TRAP) {
2104 if (kbuf)
2105 reg = *k++;
2106 else if (__get_user(reg, u++))
2107 return -EFAULT;
2108 set_user_trap(target, reg);
2109 ++pos;
2110 --count;
2111 }
2112
2113 kbuf = k;
2114 ubuf = u;
2115 pos *= sizeof(reg);
2116 count *= sizeof(reg);
2117 return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
2118 (PT_TRAP + 1) * sizeof(reg), -1);
2119}
2120
2121#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2122static int tm_cgpr32_get(struct task_struct *target,
2123 const struct user_regset *regset,
2124 unsigned int pos, unsigned int count,
2125 void *kbuf, void __user *ubuf)
2126{
2127 return gpr32_get_common(target, regset, pos, count, kbuf, ubuf,
2128 &target->thread.ckpt_regs.gpr[0]);
2129}
2130
2131static int tm_cgpr32_set(struct task_struct *target,
2132 const struct user_regset *regset,
2133 unsigned int pos, unsigned int count,
2134 const void *kbuf, const void __user *ubuf)
2135{
2136 return gpr32_set_common(target, regset, pos, count, kbuf, ubuf,
2137 &target->thread.ckpt_regs.gpr[0]);
2138}
2139#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
2140
2141static int gpr32_get(struct task_struct *target,
2142 const struct user_regset *regset,
2143 unsigned int pos, unsigned int count,
2144 void *kbuf, void __user *ubuf)
2145{
2146 int i;
2147
2148 if (target->thread.regs == NULL)
2149 return -EIO;
2150
2151 if (!FULL_REGS(target->thread.regs)) {
2152 /*
2153 * We have a partial register set.
2154 * Fill 14-31 with bogus values.
2155 */
2156 for (i = 14; i < 32; i++)
2157 target->thread.regs->gpr[i] = NV_REG_POISON;
2158 }
2159 return gpr32_get_common(target, regset, pos, count, kbuf, ubuf,
2160 &target->thread.regs->gpr[0]);
2161}
2162
2163static int gpr32_set(struct task_struct *target,
2164 const struct user_regset *regset,
2165 unsigned int pos, unsigned int count,
2166 const void *kbuf, const void __user *ubuf)
2167{
2168 if (target->thread.regs == NULL)
2169 return -EIO;
2170
2171 CHECK_FULL_REGS(target->thread.regs);
2172 return gpr32_set_common(target, regset, pos, count, kbuf, ubuf,
2173 &target->thread.regs->gpr[0]);
2174}
2175
2176/*
2177 * These are the regset flavors matching the CONFIG_PPC32 native set.
2178 */
2179static const struct user_regset compat_regsets[] = {
2180 [REGSET_GPR] = {
2181 .core_note_type = NT_PRSTATUS, .n = ELF_NGREG,
2182 .size = sizeof(compat_long_t), .align = sizeof(compat_long_t),
2183 .get = gpr32_get, .set = gpr32_set
2184 },
2185 [REGSET_FPR] = {
2186 .core_note_type = NT_PRFPREG, .n = ELF_NFPREG,
2187 .size = sizeof(double), .align = sizeof(double),
2188 .get = fpr_get, .set = fpr_set
2189 },
2190#ifdef CONFIG_ALTIVEC
2191 [REGSET_VMX] = {
2192 .core_note_type = NT_PPC_VMX, .n = 34,
2193 .size = sizeof(vector128), .align = sizeof(vector128),
2194 .active = vr_active, .get = vr_get, .set = vr_set
2195 },
2196#endif
2197#ifdef CONFIG_SPE
2198 [REGSET_SPE] = {
2199 .core_note_type = NT_PPC_SPE, .n = 35,
2200 .size = sizeof(u32), .align = sizeof(u32),
2201 .active = evr_active, .get = evr_get, .set = evr_set
2202 },
2203#endif
2204#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2205 [REGSET_TM_CGPR] = {
2206 .core_note_type = NT_PPC_TM_CGPR, .n = ELF_NGREG,
2207 .size = sizeof(long), .align = sizeof(long),
2208 .active = tm_cgpr_active,
2209 .get = tm_cgpr32_get, .set = tm_cgpr32_set
2210 },
2211 [REGSET_TM_CFPR] = {
2212 .core_note_type = NT_PPC_TM_CFPR, .n = ELF_NFPREG,
2213 .size = sizeof(double), .align = sizeof(double),
2214 .active = tm_cfpr_active, .get = tm_cfpr_get, .set = tm_cfpr_set
2215 },
2216 [REGSET_TM_CVMX] = {
2217 .core_note_type = NT_PPC_TM_CVMX, .n = ELF_NVMX,
2218 .size = sizeof(vector128), .align = sizeof(vector128),
2219 .active = tm_cvmx_active, .get = tm_cvmx_get, .set = tm_cvmx_set
2220 },
2221 [REGSET_TM_CVSX] = {
2222 .core_note_type = NT_PPC_TM_CVSX, .n = ELF_NVSX,
2223 .size = sizeof(double), .align = sizeof(double),
2224 .active = tm_cvsx_active, .get = tm_cvsx_get, .set = tm_cvsx_set
2225 },
2226 [REGSET_TM_SPR] = {
2227 .core_note_type = NT_PPC_TM_SPR, .n = ELF_NTMSPRREG,
2228 .size = sizeof(u64), .align = sizeof(u64),
2229 .active = tm_spr_active, .get = tm_spr_get, .set = tm_spr_set
2230 },
2231 [REGSET_TM_CTAR] = {
2232 .core_note_type = NT_PPC_TM_CTAR, .n = 1,
2233 .size = sizeof(u64), .align = sizeof(u64),
2234 .active = tm_tar_active, .get = tm_tar_get, .set = tm_tar_set
2235 },
2236 [REGSET_TM_CPPR] = {
2237 .core_note_type = NT_PPC_TM_CPPR, .n = 1,
2238 .size = sizeof(u64), .align = sizeof(u64),
2239 .active = tm_ppr_active, .get = tm_ppr_get, .set = tm_ppr_set
2240 },
2241 [REGSET_TM_CDSCR] = {
2242 .core_note_type = NT_PPC_TM_CDSCR, .n = 1,
2243 .size = sizeof(u64), .align = sizeof(u64),
2244 .active = tm_dscr_active, .get = tm_dscr_get, .set = tm_dscr_set
2245 },
2246#endif
2247#ifdef CONFIG_PPC64
2248 [REGSET_PPR] = {
2249 .core_note_type = NT_PPC_PPR, .n = 1,
2250 .size = sizeof(u64), .align = sizeof(u64),
2251 .get = ppr_get, .set = ppr_set
2252 },
2253 [REGSET_DSCR] = {
2254 .core_note_type = NT_PPC_DSCR, .n = 1,
2255 .size = sizeof(u64), .align = sizeof(u64),
2256 .get = dscr_get, .set = dscr_set
2257 },
2258#endif
2259#ifdef CONFIG_PPC_BOOK3S_64
2260 [REGSET_TAR] = {
2261 .core_note_type = NT_PPC_TAR, .n = 1,
2262 .size = sizeof(u64), .align = sizeof(u64),
2263 .get = tar_get, .set = tar_set
2264 },
2265 [REGSET_EBB] = {
2266 .core_note_type = NT_PPC_EBB, .n = ELF_NEBB,
2267 .size = sizeof(u64), .align = sizeof(u64),
2268 .active = ebb_active, .get = ebb_get, .set = ebb_set
2269 },
2270#endif
2271};
2272
2273static const struct user_regset_view user_ppc_compat_view = {
2274 .name = "ppc", .e_machine = EM_PPC, .ei_osabi = ELF_OSABI,
2275 .regsets = compat_regsets, .n = ARRAY_SIZE(compat_regsets)
2276};
2277#endif /* CONFIG_PPC64 */
2278
2279const struct user_regset_view *task_user_regset_view(struct task_struct *task)
2280{
2281#ifdef CONFIG_PPC64
2282 if (test_tsk_thread_flag(task, TIF_32BIT))
2283 return &user_ppc_compat_view;
2284#endif
2285 return &user_ppc_native_view;
2286}
2287
2288
2289void user_enable_single_step(struct task_struct *task)
2290{
2291 struct pt_regs *regs = task->thread.regs;
2292
2293 if (regs != NULL) {
2294#ifdef CONFIG_PPC_ADV_DEBUG_REGS
2295 task->thread.debug.dbcr0 &= ~DBCR0_BT;
2296 task->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
2297 regs->msr |= MSR_DE;
2298#else
2299 regs->msr &= ~MSR_BE;
2300 regs->msr |= MSR_SE;
2301#endif
2302 }
2303 set_tsk_thread_flag(task, TIF_SINGLESTEP);
2304}
2305
2306void user_enable_block_step(struct task_struct *task)
2307{
2308 struct pt_regs *regs = task->thread.regs;
2309
2310 if (regs != NULL) {
2311#ifdef CONFIG_PPC_ADV_DEBUG_REGS
2312 task->thread.debug.dbcr0 &= ~DBCR0_IC;
2313 task->thread.debug.dbcr0 = DBCR0_IDM | DBCR0_BT;
2314 regs->msr |= MSR_DE;
2315#else
2316 regs->msr &= ~MSR_SE;
2317 regs->msr |= MSR_BE;
2318#endif
2319 }
2320 set_tsk_thread_flag(task, TIF_SINGLESTEP);
2321}
2322
2323void user_disable_single_step(struct task_struct *task)
2324{
2325 struct pt_regs *regs = task->thread.regs;
2326
2327 if (regs != NULL) {
2328#ifdef CONFIG_PPC_ADV_DEBUG_REGS
2329 /*
2330 * The logic to disable single stepping should be as
2331 * simple as turning off the Instruction Complete flag.
2332 * And, after doing so, if all debug flags are off, turn
2333 * off DBCR0(IDM) and MSR(DE) .... Torez
2334 */
2335 task->thread.debug.dbcr0 &= ~(DBCR0_IC|DBCR0_BT);
2336 /*
2337 * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set.
2338 */
2339 if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0,
2340 task->thread.debug.dbcr1)) {
2341 /*
2342 * All debug events were off.....
2343 */
2344 task->thread.debug.dbcr0 &= ~DBCR0_IDM;
2345 regs->msr &= ~MSR_DE;
2346 }
2347#else
2348 regs->msr &= ~(MSR_SE | MSR_BE);
2349#endif
2350 }
2351 clear_tsk_thread_flag(task, TIF_SINGLESTEP);
2352}
2353
2354#ifdef CONFIG_HAVE_HW_BREAKPOINT
2355void ptrace_triggered(struct perf_event *bp,
2356 struct perf_sample_data *data, struct pt_regs *regs)
2357{
2358 struct perf_event_attr attr;
2359
2360 /*
2361 * Disable the breakpoint request here since ptrace has defined a
2362 * one-shot behaviour for breakpoint exceptions in PPC64.
2363 * The SIGTRAP signal is generated automatically for us in do_dabr().
2364 * We don't have to do anything about that here
2365 */
2366 attr = bp->attr;
2367 attr.disabled = true;
2368 modify_user_hw_breakpoint(bp, &attr);
2369}
2370#endif /* CONFIG_HAVE_HW_BREAKPOINT */
2371
2372static int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
2373 unsigned long data)
2374{
2375#ifdef CONFIG_HAVE_HW_BREAKPOINT
2376 int ret;
2377 struct thread_struct *thread = &(task->thread);
2378 struct perf_event *bp;
2379 struct perf_event_attr attr;
2380#endif /* CONFIG_HAVE_HW_BREAKPOINT */
2381#ifndef CONFIG_PPC_ADV_DEBUG_REGS
2382 bool set_bp = true;
2383 struct arch_hw_breakpoint hw_brk;
2384#endif
2385
2386 /* For ppc64 we support one DABR and no IABR's at the moment (ppc64).
2387 * For embedded processors we support one DAC and no IAC's at the
2388 * moment.
2389 */
2390 if (addr > 0)
2391 return -EINVAL;
2392
2393 /* The bottom 3 bits in dabr are flags */
2394 if ((data & ~0x7UL) >= TASK_SIZE)
2395 return -EIO;
2396
2397#ifndef CONFIG_PPC_ADV_DEBUG_REGS
2398 /* For processors using DABR (i.e. 970), the bottom 3 bits are flags.
2399 * It was assumed, on previous implementations, that 3 bits were
2400 * passed together with the data address, fitting the design of the
2401 * DABR register, as follows:
2402 *
2403 * bit 0: Read flag
2404 * bit 1: Write flag
2405 * bit 2: Breakpoint translation
2406 *
2407 * Thus, we use them here as so.
2408 */
2409
2410 /* Ensure breakpoint translation bit is set */
2411 if (data && !(data & HW_BRK_TYPE_TRANSLATE))
2412 return -EIO;
2413 hw_brk.address = data & (~HW_BRK_TYPE_DABR);
2414 hw_brk.type = (data & HW_BRK_TYPE_DABR) | HW_BRK_TYPE_PRIV_ALL;
2415 hw_brk.len = 8;
2416 set_bp = (data) && (hw_brk.type & HW_BRK_TYPE_RDWR);
2417#ifdef CONFIG_HAVE_HW_BREAKPOINT
2418 bp = thread->ptrace_bps[0];
2419 if (!set_bp) {
2420 if (bp) {
2421 unregister_hw_breakpoint(bp);
2422 thread->ptrace_bps[0] = NULL;
2423 }
2424 return 0;
2425 }
2426 if (bp) {
2427 attr = bp->attr;
2428 attr.bp_addr = hw_brk.address;
2429 arch_bp_generic_fields(hw_brk.type, &attr.bp_type);
2430
2431 /* Enable breakpoint */
2432 attr.disabled = false;
2433
2434 ret = modify_user_hw_breakpoint(bp, &attr);
2435 if (ret) {
2436 return ret;
2437 }
2438 thread->ptrace_bps[0] = bp;
2439 thread->hw_brk = hw_brk;
2440 return 0;
2441 }
2442
2443 /* Create a new breakpoint request if one doesn't exist already */
2444 hw_breakpoint_init(&attr);
2445 attr.bp_addr = hw_brk.address;
2446 arch_bp_generic_fields(hw_brk.type,
2447 &attr.bp_type);
2448
2449 thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
2450 ptrace_triggered, NULL, task);
2451 if (IS_ERR(bp)) {
2452 thread->ptrace_bps[0] = NULL;
2453 return PTR_ERR(bp);
2454 }
2455
2456#else /* !CONFIG_HAVE_HW_BREAKPOINT */
2457 if (set_bp && (!ppc_breakpoint_available()))
2458 return -ENODEV;
2459#endif /* CONFIG_HAVE_HW_BREAKPOINT */
2460 task->thread.hw_brk = hw_brk;
2461#else /* CONFIG_PPC_ADV_DEBUG_REGS */
2462 /* As described above, it was assumed 3 bits were passed with the data
2463 * address, but we will assume only the mode bits will be passed
2464 * as to not cause alignment restrictions for DAC-based processors.
2465 */
2466
2467 /* DAC's hold the whole address without any mode flags */
2468 task->thread.debug.dac1 = data & ~0x3UL;
2469
2470 if (task->thread.debug.dac1 == 0) {
2471 dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W);
2472 if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0,
2473 task->thread.debug.dbcr1)) {
2474 task->thread.regs->msr &= ~MSR_DE;
2475 task->thread.debug.dbcr0 &= ~DBCR0_IDM;
2476 }
2477 return 0;
2478 }
2479
2480 /* Read or Write bits must be set */
2481
2482 if (!(data & 0x3UL))
2483 return -EINVAL;
2484
2485 /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0
2486 register */
2487 task->thread.debug.dbcr0 |= DBCR0_IDM;
2488
2489 /* Check for write and read flags and set DBCR0
2490 accordingly */
2491 dbcr_dac(task) &= ~(DBCR_DAC1R|DBCR_DAC1W);
2492 if (data & 0x1UL)
2493 dbcr_dac(task) |= DBCR_DAC1R;
2494 if (data & 0x2UL)
2495 dbcr_dac(task) |= DBCR_DAC1W;
2496 task->thread.regs->msr |= MSR_DE;
2497#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
2498 return 0;
2499}
2500
2501/*
2502 * Called by kernel/ptrace.c when detaching..
2503 *
2504 * Make sure single step bits etc are not set.
2505 */
2506void ptrace_disable(struct task_struct *child)
2507{
2508 /* make sure the single step bit is not set. */
2509 user_disable_single_step(child);
2510}
2511
2512#ifdef CONFIG_PPC_ADV_DEBUG_REGS
2513static long set_instruction_bp(struct task_struct *child,
2514 struct ppc_hw_breakpoint *bp_info)
2515{
2516 int slot;
2517 int slot1_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC1) != 0);
2518 int slot2_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC2) != 0);
2519 int slot3_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC3) != 0);
2520 int slot4_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC4) != 0);
2521
2522 if (dbcr_iac_range(child) & DBCR_IAC12MODE)
2523 slot2_in_use = 1;
2524 if (dbcr_iac_range(child) & DBCR_IAC34MODE)
2525 slot4_in_use = 1;
2526
2527 if (bp_info->addr >= TASK_SIZE)
2528 return -EIO;
2529
2530 if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) {
2531
2532 /* Make sure range is valid. */
2533 if (bp_info->addr2 >= TASK_SIZE)
2534 return -EIO;
2535
2536 /* We need a pair of IAC regsisters */
2537 if ((!slot1_in_use) && (!slot2_in_use)) {
2538 slot = 1;
2539 child->thread.debug.iac1 = bp_info->addr;
2540 child->thread.debug.iac2 = bp_info->addr2;
2541 child->thread.debug.dbcr0 |= DBCR0_IAC1;
2542 if (bp_info->addr_mode ==
2543 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
2544 dbcr_iac_range(child) |= DBCR_IAC12X;
2545 else
2546 dbcr_iac_range(child) |= DBCR_IAC12I;
2547#if CONFIG_PPC_ADV_DEBUG_IACS > 2
2548 } else if ((!slot3_in_use) && (!slot4_in_use)) {
2549 slot = 3;
2550 child->thread.debug.iac3 = bp_info->addr;
2551 child->thread.debug.iac4 = bp_info->addr2;
2552 child->thread.debug.dbcr0 |= DBCR0_IAC3;
2553 if (bp_info->addr_mode ==
2554 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
2555 dbcr_iac_range(child) |= DBCR_IAC34X;
2556 else
2557 dbcr_iac_range(child) |= DBCR_IAC34I;
2558#endif
2559 } else
2560 return -ENOSPC;
2561 } else {
2562 /* We only need one. If possible leave a pair free in
2563 * case a range is needed later
2564 */
2565 if (!slot1_in_use) {
2566 /*
2567 * Don't use iac1 if iac1-iac2 are free and either
2568 * iac3 or iac4 (but not both) are free
2569 */
2570 if (slot2_in_use || (slot3_in_use == slot4_in_use)) {
2571 slot = 1;
2572 child->thread.debug.iac1 = bp_info->addr;
2573 child->thread.debug.dbcr0 |= DBCR0_IAC1;
2574 goto out;
2575 }
2576 }
2577 if (!slot2_in_use) {
2578 slot = 2;
2579 child->thread.debug.iac2 = bp_info->addr;
2580 child->thread.debug.dbcr0 |= DBCR0_IAC2;
2581#if CONFIG_PPC_ADV_DEBUG_IACS > 2
2582 } else if (!slot3_in_use) {
2583 slot = 3;
2584 child->thread.debug.iac3 = bp_info->addr;
2585 child->thread.debug.dbcr0 |= DBCR0_IAC3;
2586 } else if (!slot4_in_use) {
2587 slot = 4;
2588 child->thread.debug.iac4 = bp_info->addr;
2589 child->thread.debug.dbcr0 |= DBCR0_IAC4;
2590#endif
2591 } else
2592 return -ENOSPC;
2593 }
2594out:
2595 child->thread.debug.dbcr0 |= DBCR0_IDM;
2596 child->thread.regs->msr |= MSR_DE;
2597
2598 return slot;
2599}
2600
2601static int del_instruction_bp(struct task_struct *child, int slot)
2602{
2603 switch (slot) {
2604 case 1:
2605 if ((child->thread.debug.dbcr0 & DBCR0_IAC1) == 0)
2606 return -ENOENT;
2607
2608 if (dbcr_iac_range(child) & DBCR_IAC12MODE) {
2609 /* address range - clear slots 1 & 2 */
2610 child->thread.debug.iac2 = 0;
2611 dbcr_iac_range(child) &= ~DBCR_IAC12MODE;
2612 }
2613 child->thread.debug.iac1 = 0;
2614 child->thread.debug.dbcr0 &= ~DBCR0_IAC1;
2615 break;
2616 case 2:
2617 if ((child->thread.debug.dbcr0 & DBCR0_IAC2) == 0)
2618 return -ENOENT;
2619
2620 if (dbcr_iac_range(child) & DBCR_IAC12MODE)
2621 /* used in a range */
2622 return -EINVAL;
2623 child->thread.debug.iac2 = 0;
2624 child->thread.debug.dbcr0 &= ~DBCR0_IAC2;
2625 break;
2626#if CONFIG_PPC_ADV_DEBUG_IACS > 2
2627 case 3:
2628 if ((child->thread.debug.dbcr0 & DBCR0_IAC3) == 0)
2629 return -ENOENT;
2630
2631 if (dbcr_iac_range(child) & DBCR_IAC34MODE) {
2632 /* address range - clear slots 3 & 4 */
2633 child->thread.debug.iac4 = 0;
2634 dbcr_iac_range(child) &= ~DBCR_IAC34MODE;
2635 }
2636 child->thread.debug.iac3 = 0;
2637 child->thread.debug.dbcr0 &= ~DBCR0_IAC3;
2638 break;
2639 case 4:
2640 if ((child->thread.debug.dbcr0 & DBCR0_IAC4) == 0)
2641 return -ENOENT;
2642
2643 if (dbcr_iac_range(child) & DBCR_IAC34MODE)
2644 /* Used in a range */
2645 return -EINVAL;
2646 child->thread.debug.iac4 = 0;
2647 child->thread.debug.dbcr0 &= ~DBCR0_IAC4;
2648 break;
2649#endif
2650 default:
2651 return -EINVAL;
2652 }
2653 return 0;
2654}
2655
2656static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info)
2657{
2658 int byte_enable =
2659 (bp_info->condition_mode >> PPC_BREAKPOINT_CONDITION_BE_SHIFT)
2660 & 0xf;
2661 int condition_mode =
2662 bp_info->condition_mode & PPC_BREAKPOINT_CONDITION_MODE;
2663 int slot;
2664
2665 if (byte_enable && (condition_mode == 0))
2666 return -EINVAL;
2667
2668 if (bp_info->addr >= TASK_SIZE)
2669 return -EIO;
2670
2671 if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) {
2672 slot = 1;
2673 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
2674 dbcr_dac(child) |= DBCR_DAC1R;
2675 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
2676 dbcr_dac(child) |= DBCR_DAC1W;
2677 child->thread.debug.dac1 = (unsigned long)bp_info->addr;
2678#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
2679 if (byte_enable) {
2680 child->thread.debug.dvc1 =
2681 (unsigned long)bp_info->condition_value;
2682 child->thread.debug.dbcr2 |=
2683 ((byte_enable << DBCR2_DVC1BE_SHIFT) |
2684 (condition_mode << DBCR2_DVC1M_SHIFT));
2685 }
2686#endif
2687#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2688 } else if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) {
2689 /* Both dac1 and dac2 are part of a range */
2690 return -ENOSPC;
2691#endif
2692 } else if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) {
2693 slot = 2;
2694 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
2695 dbcr_dac(child) |= DBCR_DAC2R;
2696 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
2697 dbcr_dac(child) |= DBCR_DAC2W;
2698 child->thread.debug.dac2 = (unsigned long)bp_info->addr;
2699#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
2700 if (byte_enable) {
2701 child->thread.debug.dvc2 =
2702 (unsigned long)bp_info->condition_value;
2703 child->thread.debug.dbcr2 |=
2704 ((byte_enable << DBCR2_DVC2BE_SHIFT) |
2705 (condition_mode << DBCR2_DVC2M_SHIFT));
2706 }
2707#endif
2708 } else
2709 return -ENOSPC;
2710 child->thread.debug.dbcr0 |= DBCR0_IDM;
2711 child->thread.regs->msr |= MSR_DE;
2712
2713 return slot + 4;
2714}
2715
2716static int del_dac(struct task_struct *child, int slot)
2717{
2718 if (slot == 1) {
2719 if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0)
2720 return -ENOENT;
2721
2722 child->thread.debug.dac1 = 0;
2723 dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W);
2724#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2725 if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) {
2726 child->thread.debug.dac2 = 0;
2727 child->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
2728 }
2729 child->thread.debug.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE);
2730#endif
2731#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
2732 child->thread.debug.dvc1 = 0;
2733#endif
2734 } else if (slot == 2) {
2735 if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0)
2736 return -ENOENT;
2737
2738#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2739 if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE)
2740 /* Part of a range */
2741 return -EINVAL;
2742 child->thread.debug.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE);
2743#endif
2744#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
2745 child->thread.debug.dvc2 = 0;
2746#endif
2747 child->thread.debug.dac2 = 0;
2748 dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W);
2749 } else
2750 return -EINVAL;
2751
2752 return 0;
2753}
2754#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
2755
2756#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2757static int set_dac_range(struct task_struct *child,
2758 struct ppc_hw_breakpoint *bp_info)
2759{
2760 int mode = bp_info->addr_mode & PPC_BREAKPOINT_MODE_MASK;
2761
2762 /* We don't allow range watchpoints to be used with DVC */
2763 if (bp_info->condition_mode)
2764 return -EINVAL;
2765
2766 /*
2767 * Best effort to verify the address range. The user/supervisor bits
2768 * prevent trapping in kernel space, but let's fail on an obvious bad
2769 * range. The simple test on the mask is not fool-proof, and any
2770 * exclusive range will spill over into kernel space.
2771 */
2772 if (bp_info->addr >= TASK_SIZE)
2773 return -EIO;
2774 if (mode == PPC_BREAKPOINT_MODE_MASK) {
2775 /*
2776 * dac2 is a bitmask. Don't allow a mask that makes a
2777 * kernel space address from a valid dac1 value
2778 */
2779 if (~((unsigned long)bp_info->addr2) >= TASK_SIZE)
2780 return -EIO;
2781 } else {
2782 /*
2783 * For range breakpoints, addr2 must also be a valid address
2784 */
2785 if (bp_info->addr2 >= TASK_SIZE)
2786 return -EIO;
2787 }
2788
2789 if (child->thread.debug.dbcr0 &
2790 (DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W))
2791 return -ENOSPC;
2792
2793 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
2794 child->thread.debug.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM);
2795 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
2796 child->thread.debug.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM);
2797 child->thread.debug.dac1 = bp_info->addr;
2798 child->thread.debug.dac2 = bp_info->addr2;
2799 if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE)
2800 child->thread.debug.dbcr2 |= DBCR2_DAC12M;
2801 else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
2802 child->thread.debug.dbcr2 |= DBCR2_DAC12MX;
2803 else /* PPC_BREAKPOINT_MODE_MASK */
2804 child->thread.debug.dbcr2 |= DBCR2_DAC12MM;
2805 child->thread.regs->msr |= MSR_DE;
2806
2807 return 5;
2808}
2809#endif /* CONFIG_PPC_ADV_DEBUG_DAC_RANGE */
2810
2811static long ppc_set_hwdebug(struct task_struct *child,
2812 struct ppc_hw_breakpoint *bp_info)
2813{
2814#ifdef CONFIG_HAVE_HW_BREAKPOINT
2815 int len = 0;
2816 struct thread_struct *thread = &(child->thread);
2817 struct perf_event *bp;
2818 struct perf_event_attr attr;
2819#endif /* CONFIG_HAVE_HW_BREAKPOINT */
2820#ifndef CONFIG_PPC_ADV_DEBUG_REGS
2821 struct arch_hw_breakpoint brk;
2822#endif
2823
2824 if (bp_info->version != 1)
2825 return -ENOTSUPP;
2826#ifdef CONFIG_PPC_ADV_DEBUG_REGS
2827 /*
2828 * Check for invalid flags and combinations
2829 */
2830 if ((bp_info->trigger_type == 0) ||
2831 (bp_info->trigger_type & ~(PPC_BREAKPOINT_TRIGGER_EXECUTE |
2832 PPC_BREAKPOINT_TRIGGER_RW)) ||
2833 (bp_info->addr_mode & ~PPC_BREAKPOINT_MODE_MASK) ||
2834 (bp_info->condition_mode &
2835 ~(PPC_BREAKPOINT_CONDITION_MODE |
2836 PPC_BREAKPOINT_CONDITION_BE_ALL)))
2837 return -EINVAL;
2838#if CONFIG_PPC_ADV_DEBUG_DVCS == 0
2839 if (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
2840 return -EINVAL;
2841#endif
2842
2843 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_EXECUTE) {
2844 if ((bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_EXECUTE) ||
2845 (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE))
2846 return -EINVAL;
2847 return set_instruction_bp(child, bp_info);
2848 }
2849 if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT)
2850 return set_dac(child, bp_info);
2851
2852#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2853 return set_dac_range(child, bp_info);
2854#else
2855 return -EINVAL;
2856#endif
2857#else /* !CONFIG_PPC_ADV_DEBUG_DVCS */
2858 /*
2859 * We only support one data breakpoint
2860 */
2861 if ((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0 ||
2862 (bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0 ||
2863 bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
2864 return -EINVAL;
2865
2866 if ((unsigned long)bp_info->addr >= TASK_SIZE)
2867 return -EIO;
2868
2869 brk.address = bp_info->addr & ~7UL;
2870 brk.type = HW_BRK_TYPE_TRANSLATE;
2871 brk.len = 8;
2872 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
2873 brk.type |= HW_BRK_TYPE_READ;
2874 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
2875 brk.type |= HW_BRK_TYPE_WRITE;
2876#ifdef CONFIG_HAVE_HW_BREAKPOINT
2877 /*
2878 * Check if the request is for 'range' breakpoints. We can
2879 * support it if range < 8 bytes.
2880 */
2881 if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE)
2882 len = bp_info->addr2 - bp_info->addr;
2883 else if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT)
2884 len = 1;
2885 else
2886 return -EINVAL;
2887 bp = thread->ptrace_bps[0];
2888 if (bp)
2889 return -ENOSPC;
2890
2891 /* Create a new breakpoint request if one doesn't exist already */
2892 hw_breakpoint_init(&attr);
2893 attr.bp_addr = (unsigned long)bp_info->addr & ~HW_BREAKPOINT_ALIGN;
2894 attr.bp_len = len;
2895 arch_bp_generic_fields(brk.type, &attr.bp_type);
2896
2897 thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
2898 ptrace_triggered, NULL, child);
2899 if (IS_ERR(bp)) {
2900 thread->ptrace_bps[0] = NULL;
2901 return PTR_ERR(bp);
2902 }
2903
2904 return 1;
2905#endif /* CONFIG_HAVE_HW_BREAKPOINT */
2906
2907 if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT)
2908 return -EINVAL;
2909
2910 if (child->thread.hw_brk.address)
2911 return -ENOSPC;
2912
2913 if (!ppc_breakpoint_available())
2914 return -ENODEV;
2915
2916 child->thread.hw_brk = brk;
2917
2918 return 1;
2919#endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */
2920}
2921
2922static long ppc_del_hwdebug(struct task_struct *child, long data)
2923{
2924#ifdef CONFIG_HAVE_HW_BREAKPOINT
2925 int ret = 0;
2926 struct thread_struct *thread = &(child->thread);
2927 struct perf_event *bp;
2928#endif /* CONFIG_HAVE_HW_BREAKPOINT */
2929#ifdef CONFIG_PPC_ADV_DEBUG_REGS
2930 int rc;
2931
2932 if (data <= 4)
2933 rc = del_instruction_bp(child, (int)data);
2934 else
2935 rc = del_dac(child, (int)data - 4);
2936
2937 if (!rc) {
2938 if (!DBCR_ACTIVE_EVENTS(child->thread.debug.dbcr0,
2939 child->thread.debug.dbcr1)) {
2940 child->thread.debug.dbcr0 &= ~DBCR0_IDM;
2941 child->thread.regs->msr &= ~MSR_DE;
2942 }
2943 }
2944 return rc;
2945#else
2946 if (data != 1)
2947 return -EINVAL;
2948
2949#ifdef CONFIG_HAVE_HW_BREAKPOINT
2950 bp = thread->ptrace_bps[0];
2951 if (bp) {
2952 unregister_hw_breakpoint(bp);
2953 thread->ptrace_bps[0] = NULL;
2954 } else
2955 ret = -ENOENT;
2956 return ret;
2957#else /* CONFIG_HAVE_HW_BREAKPOINT */
2958 if (child->thread.hw_brk.address == 0)
2959 return -ENOENT;
2960
2961 child->thread.hw_brk.address = 0;
2962 child->thread.hw_brk.type = 0;
2963#endif /* CONFIG_HAVE_HW_BREAKPOINT */
2964
2965 return 0;
2966#endif
2967}
2968
2969long arch_ptrace(struct task_struct *child, long request,
2970 unsigned long addr, unsigned long data)
2971{
2972 int ret = -EPERM;
2973 void __user *datavp = (void __user *) data;
2974 unsigned long __user *datalp = datavp;
2975
2976 switch (request) {
2977 /* read the word at location addr in the USER area. */
2978 case PTRACE_PEEKUSR: {
2979 unsigned long index, tmp;
2980
2981 ret = -EIO;
2982 /* convert to index and check */
2983#ifdef CONFIG_PPC32
2984 index = addr >> 2;
2985 if ((addr & 3) || (index > PT_FPSCR)
2986 || (child->thread.regs == NULL))
2987#else
2988 index = addr >> 3;
2989 if ((addr & 7) || (index > PT_FPSCR))
2990#endif
2991 break;
2992
2993 CHECK_FULL_REGS(child->thread.regs);
2994 if (index < PT_FPR0) {
2995 ret = ptrace_get_reg(child, (int) index, &tmp);
2996 if (ret)
2997 break;
2998 } else {
2999 unsigned int fpidx = index - PT_FPR0;
3000
3001 flush_fp_to_thread(child);
3002 if (fpidx < (PT_FPSCR - PT_FPR0))
3003 memcpy(&tmp, &child->thread.TS_FPR(fpidx),
3004 sizeof(long));
3005 else
3006 tmp = child->thread.fp_state.fpscr;
3007 }
3008 ret = put_user(tmp, datalp);
3009 break;
3010 }
3011
3012 /* write the word at location addr in the USER area */
3013 case PTRACE_POKEUSR: {
3014 unsigned long index;
3015
3016 ret = -EIO;
3017 /* convert to index and check */
3018#ifdef CONFIG_PPC32
3019 index = addr >> 2;
3020 if ((addr & 3) || (index > PT_FPSCR)
3021 || (child->thread.regs == NULL))
3022#else
3023 index = addr >> 3;
3024 if ((addr & 7) || (index > PT_FPSCR))
3025#endif
3026 break;
3027
3028 CHECK_FULL_REGS(child->thread.regs);
3029 if (index < PT_FPR0) {
3030 ret = ptrace_put_reg(child, index, data);
3031 } else {
3032 unsigned int fpidx = index - PT_FPR0;
3033
3034 flush_fp_to_thread(child);
3035 if (fpidx < (PT_FPSCR - PT_FPR0))
3036 memcpy(&child->thread.TS_FPR(fpidx), &data,
3037 sizeof(long));
3038 else
3039 child->thread.fp_state.fpscr = data;
3040 ret = 0;
3041 }
3042 break;
3043 }
3044
3045 case PPC_PTRACE_GETHWDBGINFO: {
3046 struct ppc_debug_info dbginfo;
3047
3048 dbginfo.version = 1;
3049#ifdef CONFIG_PPC_ADV_DEBUG_REGS
3050 dbginfo.num_instruction_bps = CONFIG_PPC_ADV_DEBUG_IACS;
3051 dbginfo.num_data_bps = CONFIG_PPC_ADV_DEBUG_DACS;
3052 dbginfo.num_condition_regs = CONFIG_PPC_ADV_DEBUG_DVCS;
3053 dbginfo.data_bp_alignment = 4;
3054 dbginfo.sizeof_condition = 4;
3055 dbginfo.features = PPC_DEBUG_FEATURE_INSN_BP_RANGE |
3056 PPC_DEBUG_FEATURE_INSN_BP_MASK;
3057#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
3058 dbginfo.features |=
3059 PPC_DEBUG_FEATURE_DATA_BP_RANGE |
3060 PPC_DEBUG_FEATURE_DATA_BP_MASK;
3061#endif
3062#else /* !CONFIG_PPC_ADV_DEBUG_REGS */
3063 dbginfo.num_instruction_bps = 0;
3064 if (ppc_breakpoint_available())
3065 dbginfo.num_data_bps = 1;
3066 else
3067 dbginfo.num_data_bps = 0;
3068 dbginfo.num_condition_regs = 0;
3069#ifdef CONFIG_PPC64
3070 dbginfo.data_bp_alignment = 8;
3071#else
3072 dbginfo.data_bp_alignment = 4;
3073#endif
3074 dbginfo.sizeof_condition = 0;
3075#ifdef CONFIG_HAVE_HW_BREAKPOINT
3076 dbginfo.features = PPC_DEBUG_FEATURE_DATA_BP_RANGE;
3077 if (cpu_has_feature(CPU_FTR_DAWR))
3078 dbginfo.features |= PPC_DEBUG_FEATURE_DATA_BP_DAWR;
3079#else
3080 dbginfo.features = 0;
3081#endif /* CONFIG_HAVE_HW_BREAKPOINT */
3082#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
3083
3084 if (!access_ok(VERIFY_WRITE, datavp,
3085 sizeof(struct ppc_debug_info)))
3086 return -EFAULT;
3087 ret = __copy_to_user(datavp, &dbginfo,
3088 sizeof(struct ppc_debug_info)) ?
3089 -EFAULT : 0;
3090 break;
3091 }
3092
3093 case PPC_PTRACE_SETHWDEBUG: {
3094 struct ppc_hw_breakpoint bp_info;
3095
3096 if (!access_ok(VERIFY_READ, datavp,
3097 sizeof(struct ppc_hw_breakpoint)))
3098 return -EFAULT;
3099 ret = __copy_from_user(&bp_info, datavp,
3100 sizeof(struct ppc_hw_breakpoint)) ?
3101 -EFAULT : 0;
3102 if (!ret)
3103 ret = ppc_set_hwdebug(child, &bp_info);
3104 break;
3105 }
3106
3107 case PPC_PTRACE_DELHWDEBUG: {
3108 ret = ppc_del_hwdebug(child, data);
3109 break;
3110 }
3111
3112 case PTRACE_GET_DEBUGREG: {
3113#ifndef CONFIG_PPC_ADV_DEBUG_REGS
3114 unsigned long dabr_fake;
3115#endif
3116 ret = -EINVAL;
3117 /* We only support one DABR and no IABRS at the moment */
3118 if (addr > 0)
3119 break;
3120#ifdef CONFIG_PPC_ADV_DEBUG_REGS
3121 ret = put_user(child->thread.debug.dac1, datalp);
3122#else
3123 dabr_fake = ((child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) |
3124 (child->thread.hw_brk.type & HW_BRK_TYPE_DABR));
3125 ret = put_user(dabr_fake, datalp);
3126#endif
3127 break;
3128 }
3129
3130 case PTRACE_SET_DEBUGREG:
3131 ret = ptrace_set_debugreg(child, addr, data);
3132 break;
3133
3134#ifdef CONFIG_PPC64
3135 case PTRACE_GETREGS64:
3136#endif
3137 case PTRACE_GETREGS: /* Get all pt_regs from the child. */
3138 return copy_regset_to_user(child, &user_ppc_native_view,
3139 REGSET_GPR,
3140 0, sizeof(struct pt_regs),
3141 datavp);
3142
3143#ifdef CONFIG_PPC64
3144 case PTRACE_SETREGS64:
3145#endif
3146 case PTRACE_SETREGS: /* Set all gp regs in the child. */
3147 return copy_regset_from_user(child, &user_ppc_native_view,
3148 REGSET_GPR,
3149 0, sizeof(struct pt_regs),
3150 datavp);
3151
3152 case PTRACE_GETFPREGS: /* Get the child FPU state (FPR0...31 + FPSCR) */
3153 return copy_regset_to_user(child, &user_ppc_native_view,
3154 REGSET_FPR,
3155 0, sizeof(elf_fpregset_t),
3156 datavp);
3157
3158 case PTRACE_SETFPREGS: /* Set the child FPU state (FPR0...31 + FPSCR) */
3159 return copy_regset_from_user(child, &user_ppc_native_view,
3160 REGSET_FPR,
3161 0, sizeof(elf_fpregset_t),
3162 datavp);
3163
3164#ifdef CONFIG_ALTIVEC
3165 case PTRACE_GETVRREGS:
3166 return copy_regset_to_user(child, &user_ppc_native_view,
3167 REGSET_VMX,
3168 0, (33 * sizeof(vector128) +
3169 sizeof(u32)),
3170 datavp);
3171
3172 case PTRACE_SETVRREGS:
3173 return copy_regset_from_user(child, &user_ppc_native_view,
3174 REGSET_VMX,
3175 0, (33 * sizeof(vector128) +
3176 sizeof(u32)),
3177 datavp);
3178#endif
3179#ifdef CONFIG_VSX
3180 case PTRACE_GETVSRREGS:
3181 return copy_regset_to_user(child, &user_ppc_native_view,
3182 REGSET_VSX,
3183 0, 32 * sizeof(double),
3184 datavp);
3185
3186 case PTRACE_SETVSRREGS:
3187 return copy_regset_from_user(child, &user_ppc_native_view,
3188 REGSET_VSX,
3189 0, 32 * sizeof(double),
3190 datavp);
3191#endif
3192#ifdef CONFIG_SPE
3193 case PTRACE_GETEVRREGS:
3194 /* Get the child spe register state. */
3195 return copy_regset_to_user(child, &user_ppc_native_view,
3196 REGSET_SPE, 0, 35 * sizeof(u32),
3197 datavp);
3198
3199 case PTRACE_SETEVRREGS:
3200 /* Set the child spe register state. */
3201 return copy_regset_from_user(child, &user_ppc_native_view,
3202 REGSET_SPE, 0, 35 * sizeof(u32),
3203 datavp);
3204#endif
3205
3206 default:
3207 ret = ptrace_request(child, request, addr, data);
3208 break;
3209 }
3210 return ret;
3211}
3212
3213#ifdef CONFIG_SECCOMP
3214static int do_seccomp(struct pt_regs *regs)
3215{
3216 if (!test_thread_flag(TIF_SECCOMP))
3217 return 0;
3218
3219 /*
3220 * The ABI we present to seccomp tracers is that r3 contains
3221 * the syscall return value and orig_gpr3 contains the first
3222 * syscall parameter. This is different to the ptrace ABI where
3223 * both r3 and orig_gpr3 contain the first syscall parameter.
3224 */
3225 regs->gpr[3] = -ENOSYS;
3226
3227 /*
3228 * We use the __ version here because we have already checked
3229 * TIF_SECCOMP. If this fails, there is nothing left to do, we
3230 * have already loaded -ENOSYS into r3, or seccomp has put
3231 * something else in r3 (via SECCOMP_RET_ERRNO/TRACE).
3232 */
3233 if (__secure_computing(NULL))
3234 return -1;
3235
3236 /*
3237 * The syscall was allowed by seccomp, restore the register
3238 * state to what audit expects.
3239 * Note that we use orig_gpr3, which means a seccomp tracer can
3240 * modify the first syscall parameter (in orig_gpr3) and also
3241 * allow the syscall to proceed.
3242 */
3243 regs->gpr[3] = regs->orig_gpr3;
3244
3245 return 0;
3246}
3247#else
3248static inline int do_seccomp(struct pt_regs *regs) { return 0; }
3249#endif /* CONFIG_SECCOMP */
3250
3251/**
3252 * do_syscall_trace_enter() - Do syscall tracing on kernel entry.
3253 * @regs: the pt_regs of the task to trace (current)
3254 *
3255 * Performs various types of tracing on syscall entry. This includes seccomp,
3256 * ptrace, syscall tracepoints and audit.
3257 *
3258 * The pt_regs are potentially visible to userspace via ptrace, so their
3259 * contents is ABI.
3260 *
3261 * One or more of the tracers may modify the contents of pt_regs, in particular
3262 * to modify arguments or even the syscall number itself.
3263 *
3264 * It's also possible that a tracer can choose to reject the system call. In
3265 * that case this function will return an illegal syscall number, and will put
3266 * an appropriate return value in regs->r3.
3267 *
3268 * Return: the (possibly changed) syscall number.
3269 */
3270long do_syscall_trace_enter(struct pt_regs *regs)
3271{
3272 user_exit();
3273
3274 /*
3275 * The tracer may decide to abort the syscall, if so tracehook
3276 * will return !0. Note that the tracer may also just change
3277 * regs->gpr[0] to an invalid syscall number, that is handled
3278 * below on the exit path.
3279 */
3280 if (test_thread_flag(TIF_SYSCALL_TRACE) &&
3281 tracehook_report_syscall_entry(regs))
3282 goto skip;
3283
3284 /* Run seccomp after ptrace; allow it to set gpr[3]. */
3285 if (do_seccomp(regs))
3286 return -1;
3287
3288 /* Avoid trace and audit when syscall is invalid. */
3289 if (regs->gpr[0] >= NR_syscalls)
3290 goto skip;
3291
3292 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
3293 trace_sys_enter(regs, regs->gpr[0]);
3294
3295#ifdef CONFIG_PPC64
3296 if (!is_32bit_task())
3297 audit_syscall_entry(regs->gpr[0], regs->gpr[3], regs->gpr[4],
3298 regs->gpr[5], regs->gpr[6]);
3299 else
3300#endif
3301 audit_syscall_entry(regs->gpr[0],
3302 regs->gpr[3] & 0xffffffff,
3303 regs->gpr[4] & 0xffffffff,
3304 regs->gpr[5] & 0xffffffff,
3305 regs->gpr[6] & 0xffffffff);
3306
3307 /* Return the possibly modified but valid syscall number */
3308 return regs->gpr[0];
3309
3310skip:
3311 /*
3312 * If we are aborting explicitly, or if the syscall number is
3313 * now invalid, set the return value to -ENOSYS.
3314 */
3315 regs->gpr[3] = -ENOSYS;
3316 return -1;
3317}
3318
3319void do_syscall_trace_leave(struct pt_regs *regs)
3320{
3321 int step;
3322
3323 audit_syscall_exit(regs);
3324
3325 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
3326 trace_sys_exit(regs, regs->result);
3327
3328 step = test_thread_flag(TIF_SINGLESTEP);
3329 if (step || test_thread_flag(TIF_SYSCALL_TRACE))
3330 tracehook_report_syscall_exit(regs, step);
3331
3332 user_enter();
3333}
1/*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 *
5 * Derived from "arch/m68k/kernel/ptrace.c"
6 * Copyright (C) 1994 by Hamish Macdonald
7 * Taken from linux/kernel/ptrace.c and modified for M680x0.
8 * linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
9 *
10 * Modified by Cort Dougan (cort@hq.fsmlabs.com)
11 * and Paul Mackerras (paulus@samba.org).
12 *
13 * This file is subject to the terms and conditions of the GNU General
14 * Public License. See the file README.legal in the main directory of
15 * this archive for more details.
16 */
17
18#include <linux/kernel.h>
19#include <linux/sched.h>
20#include <linux/mm.h>
21#include <linux/smp.h>
22#include <linux/errno.h>
23#include <linux/ptrace.h>
24#include <linux/regset.h>
25#include <linux/tracehook.h>
26#include <linux/elf.h>
27#include <linux/user.h>
28#include <linux/security.h>
29#include <linux/signal.h>
30#include <linux/seccomp.h>
31#include <linux/audit.h>
32#include <trace/syscall.h>
33#include <linux/hw_breakpoint.h>
34#include <linux/perf_event.h>
35#include <linux/context_tracking.h>
36
37#include <asm/uaccess.h>
38#include <asm/page.h>
39#include <asm/pgtable.h>
40#include <asm/switch_to.h>
41
42#define CREATE_TRACE_POINTS
43#include <trace/events/syscalls.h>
44
45/*
46 * The parameter save area on the stack is used to store arguments being passed
47 * to callee function and is located at fixed offset from stack pointer.
48 */
49#ifdef CONFIG_PPC32
50#define PARAMETER_SAVE_AREA_OFFSET 24 /* bytes */
51#else /* CONFIG_PPC32 */
52#define PARAMETER_SAVE_AREA_OFFSET 48 /* bytes */
53#endif
54
55struct pt_regs_offset {
56 const char *name;
57 int offset;
58};
59
60#define STR(s) #s /* convert to string */
61#define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)}
62#define GPR_OFFSET_NAME(num) \
63 {.name = STR(gpr##num), .offset = offsetof(struct pt_regs, gpr[num])}
64#define REG_OFFSET_END {.name = NULL, .offset = 0}
65
66static const struct pt_regs_offset regoffset_table[] = {
67 GPR_OFFSET_NAME(0),
68 GPR_OFFSET_NAME(1),
69 GPR_OFFSET_NAME(2),
70 GPR_OFFSET_NAME(3),
71 GPR_OFFSET_NAME(4),
72 GPR_OFFSET_NAME(5),
73 GPR_OFFSET_NAME(6),
74 GPR_OFFSET_NAME(7),
75 GPR_OFFSET_NAME(8),
76 GPR_OFFSET_NAME(9),
77 GPR_OFFSET_NAME(10),
78 GPR_OFFSET_NAME(11),
79 GPR_OFFSET_NAME(12),
80 GPR_OFFSET_NAME(13),
81 GPR_OFFSET_NAME(14),
82 GPR_OFFSET_NAME(15),
83 GPR_OFFSET_NAME(16),
84 GPR_OFFSET_NAME(17),
85 GPR_OFFSET_NAME(18),
86 GPR_OFFSET_NAME(19),
87 GPR_OFFSET_NAME(20),
88 GPR_OFFSET_NAME(21),
89 GPR_OFFSET_NAME(22),
90 GPR_OFFSET_NAME(23),
91 GPR_OFFSET_NAME(24),
92 GPR_OFFSET_NAME(25),
93 GPR_OFFSET_NAME(26),
94 GPR_OFFSET_NAME(27),
95 GPR_OFFSET_NAME(28),
96 GPR_OFFSET_NAME(29),
97 GPR_OFFSET_NAME(30),
98 GPR_OFFSET_NAME(31),
99 REG_OFFSET_NAME(nip),
100 REG_OFFSET_NAME(msr),
101 REG_OFFSET_NAME(ctr),
102 REG_OFFSET_NAME(link),
103 REG_OFFSET_NAME(xer),
104 REG_OFFSET_NAME(ccr),
105#ifdef CONFIG_PPC64
106 REG_OFFSET_NAME(softe),
107#else
108 REG_OFFSET_NAME(mq),
109#endif
110 REG_OFFSET_NAME(trap),
111 REG_OFFSET_NAME(dar),
112 REG_OFFSET_NAME(dsisr),
113 REG_OFFSET_END,
114};
115
116/**
117 * regs_query_register_offset() - query register offset from its name
118 * @name: the name of a register
119 *
120 * regs_query_register_offset() returns the offset of a register in struct
121 * pt_regs from its name. If the name is invalid, this returns -EINVAL;
122 */
123int regs_query_register_offset(const char *name)
124{
125 const struct pt_regs_offset *roff;
126 for (roff = regoffset_table; roff->name != NULL; roff++)
127 if (!strcmp(roff->name, name))
128 return roff->offset;
129 return -EINVAL;
130}
131
132/**
133 * regs_query_register_name() - query register name from its offset
134 * @offset: the offset of a register in struct pt_regs.
135 *
136 * regs_query_register_name() returns the name of a register from its
137 * offset in struct pt_regs. If the @offset is invalid, this returns NULL;
138 */
139const char *regs_query_register_name(unsigned int offset)
140{
141 const struct pt_regs_offset *roff;
142 for (roff = regoffset_table; roff->name != NULL; roff++)
143 if (roff->offset == offset)
144 return roff->name;
145 return NULL;
146}
147
148/*
149 * does not yet catch signals sent when the child dies.
150 * in exit.c or in signal.c.
151 */
152
153/*
154 * Set of msr bits that gdb can change on behalf of a process.
155 */
156#ifdef CONFIG_PPC_ADV_DEBUG_REGS
157#define MSR_DEBUGCHANGE 0
158#else
159#define MSR_DEBUGCHANGE (MSR_SE | MSR_BE)
160#endif
161
162/*
163 * Max register writeable via put_reg
164 */
165#ifdef CONFIG_PPC32
166#define PT_MAX_PUT_REG PT_MQ
167#else
168#define PT_MAX_PUT_REG PT_CCR
169#endif
170
171static unsigned long get_user_msr(struct task_struct *task)
172{
173 return task->thread.regs->msr | task->thread.fpexc_mode;
174}
175
176static int set_user_msr(struct task_struct *task, unsigned long msr)
177{
178 task->thread.regs->msr &= ~MSR_DEBUGCHANGE;
179 task->thread.regs->msr |= msr & MSR_DEBUGCHANGE;
180 return 0;
181}
182
183#ifdef CONFIG_PPC64
184static int get_user_dscr(struct task_struct *task, unsigned long *data)
185{
186 *data = task->thread.dscr;
187 return 0;
188}
189
190static int set_user_dscr(struct task_struct *task, unsigned long dscr)
191{
192 task->thread.dscr = dscr;
193 task->thread.dscr_inherit = 1;
194 return 0;
195}
196#else
197static int get_user_dscr(struct task_struct *task, unsigned long *data)
198{
199 return -EIO;
200}
201
202static int set_user_dscr(struct task_struct *task, unsigned long dscr)
203{
204 return -EIO;
205}
206#endif
207
208/*
209 * We prevent mucking around with the reserved area of trap
210 * which are used internally by the kernel.
211 */
212static int set_user_trap(struct task_struct *task, unsigned long trap)
213{
214 task->thread.regs->trap = trap & 0xfff0;
215 return 0;
216}
217
218/*
219 * Get contents of register REGNO in task TASK.
220 */
221int ptrace_get_reg(struct task_struct *task, int regno, unsigned long *data)
222{
223 if ((task->thread.regs == NULL) || !data)
224 return -EIO;
225
226 if (regno == PT_MSR) {
227 *data = get_user_msr(task);
228 return 0;
229 }
230
231 if (regno == PT_DSCR)
232 return get_user_dscr(task, data);
233
234 if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long))) {
235 *data = ((unsigned long *)task->thread.regs)[regno];
236 return 0;
237 }
238
239 return -EIO;
240}
241
242/*
243 * Write contents of register REGNO in task TASK.
244 */
245int ptrace_put_reg(struct task_struct *task, int regno, unsigned long data)
246{
247 if (task->thread.regs == NULL)
248 return -EIO;
249
250 if (regno == PT_MSR)
251 return set_user_msr(task, data);
252 if (regno == PT_TRAP)
253 return set_user_trap(task, data);
254 if (regno == PT_DSCR)
255 return set_user_dscr(task, data);
256
257 if (regno <= PT_MAX_PUT_REG) {
258 ((unsigned long *)task->thread.regs)[regno] = data;
259 return 0;
260 }
261 return -EIO;
262}
263
264static int gpr_get(struct task_struct *target, const struct user_regset *regset,
265 unsigned int pos, unsigned int count,
266 void *kbuf, void __user *ubuf)
267{
268 int i, ret;
269
270 if (target->thread.regs == NULL)
271 return -EIO;
272
273 if (!FULL_REGS(target->thread.regs)) {
274 /* We have a partial register set. Fill 14-31 with bogus values */
275 for (i = 14; i < 32; i++)
276 target->thread.regs->gpr[i] = NV_REG_POISON;
277 }
278
279 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
280 target->thread.regs,
281 0, offsetof(struct pt_regs, msr));
282 if (!ret) {
283 unsigned long msr = get_user_msr(target);
284 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr,
285 offsetof(struct pt_regs, msr),
286 offsetof(struct pt_regs, msr) +
287 sizeof(msr));
288 }
289
290 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
291 offsetof(struct pt_regs, msr) + sizeof(long));
292
293 if (!ret)
294 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
295 &target->thread.regs->orig_gpr3,
296 offsetof(struct pt_regs, orig_gpr3),
297 sizeof(struct pt_regs));
298 if (!ret)
299 ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
300 sizeof(struct pt_regs), -1);
301
302 return ret;
303}
304
305static int gpr_set(struct task_struct *target, const struct user_regset *regset,
306 unsigned int pos, unsigned int count,
307 const void *kbuf, const void __user *ubuf)
308{
309 unsigned long reg;
310 int ret;
311
312 if (target->thread.regs == NULL)
313 return -EIO;
314
315 CHECK_FULL_REGS(target->thread.regs);
316
317 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
318 target->thread.regs,
319 0, PT_MSR * sizeof(reg));
320
321 if (!ret && count > 0) {
322 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®,
323 PT_MSR * sizeof(reg),
324 (PT_MSR + 1) * sizeof(reg));
325 if (!ret)
326 ret = set_user_msr(target, reg);
327 }
328
329 BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
330 offsetof(struct pt_regs, msr) + sizeof(long));
331
332 if (!ret)
333 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
334 &target->thread.regs->orig_gpr3,
335 PT_ORIG_R3 * sizeof(reg),
336 (PT_MAX_PUT_REG + 1) * sizeof(reg));
337
338 if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret)
339 ret = user_regset_copyin_ignore(
340 &pos, &count, &kbuf, &ubuf,
341 (PT_MAX_PUT_REG + 1) * sizeof(reg),
342 PT_TRAP * sizeof(reg));
343
344 if (!ret && count > 0) {
345 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, ®,
346 PT_TRAP * sizeof(reg),
347 (PT_TRAP + 1) * sizeof(reg));
348 if (!ret)
349 ret = set_user_trap(target, reg);
350 }
351
352 if (!ret)
353 ret = user_regset_copyin_ignore(
354 &pos, &count, &kbuf, &ubuf,
355 (PT_TRAP + 1) * sizeof(reg), -1);
356
357 return ret;
358}
359
360static int fpr_get(struct task_struct *target, const struct user_regset *regset,
361 unsigned int pos, unsigned int count,
362 void *kbuf, void __user *ubuf)
363{
364#ifdef CONFIG_VSX
365 u64 buf[33];
366 int i;
367#endif
368 flush_fp_to_thread(target);
369
370#ifdef CONFIG_VSX
371 /* copy to local buffer then write that out */
372 for (i = 0; i < 32 ; i++)
373 buf[i] = target->thread.TS_FPR(i);
374 buf[32] = target->thread.fp_state.fpscr;
375 return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
376
377#else
378 BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) !=
379 offsetof(struct thread_fp_state, fpr[32][0]));
380
381 return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
382 &target->thread.fp_state, 0, -1);
383#endif
384}
385
386static int fpr_set(struct task_struct *target, const struct user_regset *regset,
387 unsigned int pos, unsigned int count,
388 const void *kbuf, const void __user *ubuf)
389{
390#ifdef CONFIG_VSX
391 u64 buf[33];
392 int i;
393#endif
394 flush_fp_to_thread(target);
395
396#ifdef CONFIG_VSX
397 /* copy to local buffer then write that out */
398 i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
399 if (i)
400 return i;
401 for (i = 0; i < 32 ; i++)
402 target->thread.TS_FPR(i) = buf[i];
403 target->thread.fp_state.fpscr = buf[32];
404 return 0;
405#else
406 BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) !=
407 offsetof(struct thread_fp_state, fpr[32][0]));
408
409 return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
410 &target->thread.fp_state, 0, -1);
411#endif
412}
413
414#ifdef CONFIG_ALTIVEC
415/*
416 * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
417 * The transfer totals 34 quadword. Quadwords 0-31 contain the
418 * corresponding vector registers. Quadword 32 contains the vscr as the
419 * last word (offset 12) within that quadword. Quadword 33 contains the
420 * vrsave as the first word (offset 0) within the quadword.
421 *
422 * This definition of the VMX state is compatible with the current PPC32
423 * ptrace interface. This allows signal handling and ptrace to use the
424 * same structures. This also simplifies the implementation of a bi-arch
425 * (combined (32- and 64-bit) gdb.
426 */
427
428static int vr_active(struct task_struct *target,
429 const struct user_regset *regset)
430{
431 flush_altivec_to_thread(target);
432 return target->thread.used_vr ? regset->n : 0;
433}
434
435static int vr_get(struct task_struct *target, const struct user_regset *regset,
436 unsigned int pos, unsigned int count,
437 void *kbuf, void __user *ubuf)
438{
439 int ret;
440
441 flush_altivec_to_thread(target);
442
443 BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) !=
444 offsetof(struct thread_vr_state, vr[32]));
445
446 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
447 &target->thread.vr_state, 0,
448 33 * sizeof(vector128));
449 if (!ret) {
450 /*
451 * Copy out only the low-order word of vrsave.
452 */
453 union {
454 elf_vrreg_t reg;
455 u32 word;
456 } vrsave;
457 memset(&vrsave, 0, sizeof(vrsave));
458 vrsave.word = target->thread.vrsave;
459 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave,
460 33 * sizeof(vector128), -1);
461 }
462
463 return ret;
464}
465
466static int vr_set(struct task_struct *target, const struct user_regset *regset,
467 unsigned int pos, unsigned int count,
468 const void *kbuf, const void __user *ubuf)
469{
470 int ret;
471
472 flush_altivec_to_thread(target);
473
474 BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) !=
475 offsetof(struct thread_vr_state, vr[32]));
476
477 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
478 &target->thread.vr_state, 0,
479 33 * sizeof(vector128));
480 if (!ret && count > 0) {
481 /*
482 * We use only the first word of vrsave.
483 */
484 union {
485 elf_vrreg_t reg;
486 u32 word;
487 } vrsave;
488 memset(&vrsave, 0, sizeof(vrsave));
489 vrsave.word = target->thread.vrsave;
490 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave,
491 33 * sizeof(vector128), -1);
492 if (!ret)
493 target->thread.vrsave = vrsave.word;
494 }
495
496 return ret;
497}
498#endif /* CONFIG_ALTIVEC */
499
500#ifdef CONFIG_VSX
501/*
502 * Currently to set and and get all the vsx state, you need to call
503 * the fp and VMX calls as well. This only get/sets the lower 32
504 * 128bit VSX registers.
505 */
506
507static int vsr_active(struct task_struct *target,
508 const struct user_regset *regset)
509{
510 flush_vsx_to_thread(target);
511 return target->thread.used_vsr ? regset->n : 0;
512}
513
514static int vsr_get(struct task_struct *target, const struct user_regset *regset,
515 unsigned int pos, unsigned int count,
516 void *kbuf, void __user *ubuf)
517{
518 u64 buf[32];
519 int ret, i;
520
521 flush_vsx_to_thread(target);
522
523 for (i = 0; i < 32 ; i++)
524 buf[i] = target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET];
525 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
526 buf, 0, 32 * sizeof(double));
527
528 return ret;
529}
530
531static int vsr_set(struct task_struct *target, const struct user_regset *regset,
532 unsigned int pos, unsigned int count,
533 const void *kbuf, const void __user *ubuf)
534{
535 u64 buf[32];
536 int ret,i;
537
538 flush_vsx_to_thread(target);
539
540 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
541 buf, 0, 32 * sizeof(double));
542 for (i = 0; i < 32 ; i++)
543 target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET] = buf[i];
544
545
546 return ret;
547}
548#endif /* CONFIG_VSX */
549
550#ifdef CONFIG_SPE
551
552/*
553 * For get_evrregs/set_evrregs functions 'data' has the following layout:
554 *
555 * struct {
556 * u32 evr[32];
557 * u64 acc;
558 * u32 spefscr;
559 * }
560 */
561
562static int evr_active(struct task_struct *target,
563 const struct user_regset *regset)
564{
565 flush_spe_to_thread(target);
566 return target->thread.used_spe ? regset->n : 0;
567}
568
569static int evr_get(struct task_struct *target, const struct user_regset *regset,
570 unsigned int pos, unsigned int count,
571 void *kbuf, void __user *ubuf)
572{
573 int ret;
574
575 flush_spe_to_thread(target);
576
577 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
578 &target->thread.evr,
579 0, sizeof(target->thread.evr));
580
581 BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) !=
582 offsetof(struct thread_struct, spefscr));
583
584 if (!ret)
585 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
586 &target->thread.acc,
587 sizeof(target->thread.evr), -1);
588
589 return ret;
590}
591
592static int evr_set(struct task_struct *target, const struct user_regset *regset,
593 unsigned int pos, unsigned int count,
594 const void *kbuf, const void __user *ubuf)
595{
596 int ret;
597
598 flush_spe_to_thread(target);
599
600 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
601 &target->thread.evr,
602 0, sizeof(target->thread.evr));
603
604 BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) !=
605 offsetof(struct thread_struct, spefscr));
606
607 if (!ret)
608 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
609 &target->thread.acc,
610 sizeof(target->thread.evr), -1);
611
612 return ret;
613}
614#endif /* CONFIG_SPE */
615
616
617/*
618 * These are our native regset flavors.
619 */
620enum powerpc_regset {
621 REGSET_GPR,
622 REGSET_FPR,
623#ifdef CONFIG_ALTIVEC
624 REGSET_VMX,
625#endif
626#ifdef CONFIG_VSX
627 REGSET_VSX,
628#endif
629#ifdef CONFIG_SPE
630 REGSET_SPE,
631#endif
632};
633
634static const struct user_regset native_regsets[] = {
635 [REGSET_GPR] = {
636 .core_note_type = NT_PRSTATUS, .n = ELF_NGREG,
637 .size = sizeof(long), .align = sizeof(long),
638 .get = gpr_get, .set = gpr_set
639 },
640 [REGSET_FPR] = {
641 .core_note_type = NT_PRFPREG, .n = ELF_NFPREG,
642 .size = sizeof(double), .align = sizeof(double),
643 .get = fpr_get, .set = fpr_set
644 },
645#ifdef CONFIG_ALTIVEC
646 [REGSET_VMX] = {
647 .core_note_type = NT_PPC_VMX, .n = 34,
648 .size = sizeof(vector128), .align = sizeof(vector128),
649 .active = vr_active, .get = vr_get, .set = vr_set
650 },
651#endif
652#ifdef CONFIG_VSX
653 [REGSET_VSX] = {
654 .core_note_type = NT_PPC_VSX, .n = 32,
655 .size = sizeof(double), .align = sizeof(double),
656 .active = vsr_active, .get = vsr_get, .set = vsr_set
657 },
658#endif
659#ifdef CONFIG_SPE
660 [REGSET_SPE] = {
661 .core_note_type = NT_PPC_SPE, .n = 35,
662 .size = sizeof(u32), .align = sizeof(u32),
663 .active = evr_active, .get = evr_get, .set = evr_set
664 },
665#endif
666};
667
668static const struct user_regset_view user_ppc_native_view = {
669 .name = UTS_MACHINE, .e_machine = ELF_ARCH, .ei_osabi = ELF_OSABI,
670 .regsets = native_regsets, .n = ARRAY_SIZE(native_regsets)
671};
672
673#ifdef CONFIG_PPC64
674#include <linux/compat.h>
675
676static int gpr32_get(struct task_struct *target,
677 const struct user_regset *regset,
678 unsigned int pos, unsigned int count,
679 void *kbuf, void __user *ubuf)
680{
681 const unsigned long *regs = &target->thread.regs->gpr[0];
682 compat_ulong_t *k = kbuf;
683 compat_ulong_t __user *u = ubuf;
684 compat_ulong_t reg;
685 int i;
686
687 if (target->thread.regs == NULL)
688 return -EIO;
689
690 if (!FULL_REGS(target->thread.regs)) {
691 /* We have a partial register set. Fill 14-31 with bogus values */
692 for (i = 14; i < 32; i++)
693 target->thread.regs->gpr[i] = NV_REG_POISON;
694 }
695
696 pos /= sizeof(reg);
697 count /= sizeof(reg);
698
699 if (kbuf)
700 for (; count > 0 && pos < PT_MSR; --count)
701 *k++ = regs[pos++];
702 else
703 for (; count > 0 && pos < PT_MSR; --count)
704 if (__put_user((compat_ulong_t) regs[pos++], u++))
705 return -EFAULT;
706
707 if (count > 0 && pos == PT_MSR) {
708 reg = get_user_msr(target);
709 if (kbuf)
710 *k++ = reg;
711 else if (__put_user(reg, u++))
712 return -EFAULT;
713 ++pos;
714 --count;
715 }
716
717 if (kbuf)
718 for (; count > 0 && pos < PT_REGS_COUNT; --count)
719 *k++ = regs[pos++];
720 else
721 for (; count > 0 && pos < PT_REGS_COUNT; --count)
722 if (__put_user((compat_ulong_t) regs[pos++], u++))
723 return -EFAULT;
724
725 kbuf = k;
726 ubuf = u;
727 pos *= sizeof(reg);
728 count *= sizeof(reg);
729 return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
730 PT_REGS_COUNT * sizeof(reg), -1);
731}
732
733static int gpr32_set(struct task_struct *target,
734 const struct user_regset *regset,
735 unsigned int pos, unsigned int count,
736 const void *kbuf, const void __user *ubuf)
737{
738 unsigned long *regs = &target->thread.regs->gpr[0];
739 const compat_ulong_t *k = kbuf;
740 const compat_ulong_t __user *u = ubuf;
741 compat_ulong_t reg;
742
743 if (target->thread.regs == NULL)
744 return -EIO;
745
746 CHECK_FULL_REGS(target->thread.regs);
747
748 pos /= sizeof(reg);
749 count /= sizeof(reg);
750
751 if (kbuf)
752 for (; count > 0 && pos < PT_MSR; --count)
753 regs[pos++] = *k++;
754 else
755 for (; count > 0 && pos < PT_MSR; --count) {
756 if (__get_user(reg, u++))
757 return -EFAULT;
758 regs[pos++] = reg;
759 }
760
761
762 if (count > 0 && pos == PT_MSR) {
763 if (kbuf)
764 reg = *k++;
765 else if (__get_user(reg, u++))
766 return -EFAULT;
767 set_user_msr(target, reg);
768 ++pos;
769 --count;
770 }
771
772 if (kbuf) {
773 for (; count > 0 && pos <= PT_MAX_PUT_REG; --count)
774 regs[pos++] = *k++;
775 for (; count > 0 && pos < PT_TRAP; --count, ++pos)
776 ++k;
777 } else {
778 for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) {
779 if (__get_user(reg, u++))
780 return -EFAULT;
781 regs[pos++] = reg;
782 }
783 for (; count > 0 && pos < PT_TRAP; --count, ++pos)
784 if (__get_user(reg, u++))
785 return -EFAULT;
786 }
787
788 if (count > 0 && pos == PT_TRAP) {
789 if (kbuf)
790 reg = *k++;
791 else if (__get_user(reg, u++))
792 return -EFAULT;
793 set_user_trap(target, reg);
794 ++pos;
795 --count;
796 }
797
798 kbuf = k;
799 ubuf = u;
800 pos *= sizeof(reg);
801 count *= sizeof(reg);
802 return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
803 (PT_TRAP + 1) * sizeof(reg), -1);
804}
805
806/*
807 * These are the regset flavors matching the CONFIG_PPC32 native set.
808 */
809static const struct user_regset compat_regsets[] = {
810 [REGSET_GPR] = {
811 .core_note_type = NT_PRSTATUS, .n = ELF_NGREG,
812 .size = sizeof(compat_long_t), .align = sizeof(compat_long_t),
813 .get = gpr32_get, .set = gpr32_set
814 },
815 [REGSET_FPR] = {
816 .core_note_type = NT_PRFPREG, .n = ELF_NFPREG,
817 .size = sizeof(double), .align = sizeof(double),
818 .get = fpr_get, .set = fpr_set
819 },
820#ifdef CONFIG_ALTIVEC
821 [REGSET_VMX] = {
822 .core_note_type = NT_PPC_VMX, .n = 34,
823 .size = sizeof(vector128), .align = sizeof(vector128),
824 .active = vr_active, .get = vr_get, .set = vr_set
825 },
826#endif
827#ifdef CONFIG_SPE
828 [REGSET_SPE] = {
829 .core_note_type = NT_PPC_SPE, .n = 35,
830 .size = sizeof(u32), .align = sizeof(u32),
831 .active = evr_active, .get = evr_get, .set = evr_set
832 },
833#endif
834};
835
836static const struct user_regset_view user_ppc_compat_view = {
837 .name = "ppc", .e_machine = EM_PPC, .ei_osabi = ELF_OSABI,
838 .regsets = compat_regsets, .n = ARRAY_SIZE(compat_regsets)
839};
840#endif /* CONFIG_PPC64 */
841
842const struct user_regset_view *task_user_regset_view(struct task_struct *task)
843{
844#ifdef CONFIG_PPC64
845 if (test_tsk_thread_flag(task, TIF_32BIT))
846 return &user_ppc_compat_view;
847#endif
848 return &user_ppc_native_view;
849}
850
851
852void user_enable_single_step(struct task_struct *task)
853{
854 struct pt_regs *regs = task->thread.regs;
855
856 if (regs != NULL) {
857#ifdef CONFIG_PPC_ADV_DEBUG_REGS
858 task->thread.debug.dbcr0 &= ~DBCR0_BT;
859 task->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
860 regs->msr |= MSR_DE;
861#else
862 regs->msr &= ~MSR_BE;
863 regs->msr |= MSR_SE;
864#endif
865 }
866 set_tsk_thread_flag(task, TIF_SINGLESTEP);
867}
868
869void user_enable_block_step(struct task_struct *task)
870{
871 struct pt_regs *regs = task->thread.regs;
872
873 if (regs != NULL) {
874#ifdef CONFIG_PPC_ADV_DEBUG_REGS
875 task->thread.debug.dbcr0 &= ~DBCR0_IC;
876 task->thread.debug.dbcr0 = DBCR0_IDM | DBCR0_BT;
877 regs->msr |= MSR_DE;
878#else
879 regs->msr &= ~MSR_SE;
880 regs->msr |= MSR_BE;
881#endif
882 }
883 set_tsk_thread_flag(task, TIF_SINGLESTEP);
884}
885
886void user_disable_single_step(struct task_struct *task)
887{
888 struct pt_regs *regs = task->thread.regs;
889
890 if (regs != NULL) {
891#ifdef CONFIG_PPC_ADV_DEBUG_REGS
892 /*
893 * The logic to disable single stepping should be as
894 * simple as turning off the Instruction Complete flag.
895 * And, after doing so, if all debug flags are off, turn
896 * off DBCR0(IDM) and MSR(DE) .... Torez
897 */
898 task->thread.debug.dbcr0 &= ~(DBCR0_IC|DBCR0_BT);
899 /*
900 * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set.
901 */
902 if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0,
903 task->thread.debug.dbcr1)) {
904 /*
905 * All debug events were off.....
906 */
907 task->thread.debug.dbcr0 &= ~DBCR0_IDM;
908 regs->msr &= ~MSR_DE;
909 }
910#else
911 regs->msr &= ~(MSR_SE | MSR_BE);
912#endif
913 }
914 clear_tsk_thread_flag(task, TIF_SINGLESTEP);
915}
916
917#ifdef CONFIG_HAVE_HW_BREAKPOINT
918void ptrace_triggered(struct perf_event *bp,
919 struct perf_sample_data *data, struct pt_regs *regs)
920{
921 struct perf_event_attr attr;
922
923 /*
924 * Disable the breakpoint request here since ptrace has defined a
925 * one-shot behaviour for breakpoint exceptions in PPC64.
926 * The SIGTRAP signal is generated automatically for us in do_dabr().
927 * We don't have to do anything about that here
928 */
929 attr = bp->attr;
930 attr.disabled = true;
931 modify_user_hw_breakpoint(bp, &attr);
932}
933#endif /* CONFIG_HAVE_HW_BREAKPOINT */
934
935int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
936 unsigned long data)
937{
938#ifdef CONFIG_HAVE_HW_BREAKPOINT
939 int ret;
940 struct thread_struct *thread = &(task->thread);
941 struct perf_event *bp;
942 struct perf_event_attr attr;
943#endif /* CONFIG_HAVE_HW_BREAKPOINT */
944#ifndef CONFIG_PPC_ADV_DEBUG_REGS
945 struct arch_hw_breakpoint hw_brk;
946#endif
947
948 /* For ppc64 we support one DABR and no IABR's at the moment (ppc64).
949 * For embedded processors we support one DAC and no IAC's at the
950 * moment.
951 */
952 if (addr > 0)
953 return -EINVAL;
954
955 /* The bottom 3 bits in dabr are flags */
956 if ((data & ~0x7UL) >= TASK_SIZE)
957 return -EIO;
958
959#ifndef CONFIG_PPC_ADV_DEBUG_REGS
960 /* For processors using DABR (i.e. 970), the bottom 3 bits are flags.
961 * It was assumed, on previous implementations, that 3 bits were
962 * passed together with the data address, fitting the design of the
963 * DABR register, as follows:
964 *
965 * bit 0: Read flag
966 * bit 1: Write flag
967 * bit 2: Breakpoint translation
968 *
969 * Thus, we use them here as so.
970 */
971
972 /* Ensure breakpoint translation bit is set */
973 if (data && !(data & HW_BRK_TYPE_TRANSLATE))
974 return -EIO;
975 hw_brk.address = data & (~HW_BRK_TYPE_DABR);
976 hw_brk.type = (data & HW_BRK_TYPE_DABR) | HW_BRK_TYPE_PRIV_ALL;
977 hw_brk.len = 8;
978#ifdef CONFIG_HAVE_HW_BREAKPOINT
979 bp = thread->ptrace_bps[0];
980 if ((!data) || !(hw_brk.type & HW_BRK_TYPE_RDWR)) {
981 if (bp) {
982 unregister_hw_breakpoint(bp);
983 thread->ptrace_bps[0] = NULL;
984 }
985 return 0;
986 }
987 if (bp) {
988 attr = bp->attr;
989 attr.bp_addr = hw_brk.address;
990 arch_bp_generic_fields(hw_brk.type, &attr.bp_type);
991
992 /* Enable breakpoint */
993 attr.disabled = false;
994
995 ret = modify_user_hw_breakpoint(bp, &attr);
996 if (ret) {
997 return ret;
998 }
999 thread->ptrace_bps[0] = bp;
1000 thread->hw_brk = hw_brk;
1001 return 0;
1002 }
1003
1004 /* Create a new breakpoint request if one doesn't exist already */
1005 hw_breakpoint_init(&attr);
1006 attr.bp_addr = hw_brk.address;
1007 arch_bp_generic_fields(hw_brk.type,
1008 &attr.bp_type);
1009
1010 thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
1011 ptrace_triggered, NULL, task);
1012 if (IS_ERR(bp)) {
1013 thread->ptrace_bps[0] = NULL;
1014 return PTR_ERR(bp);
1015 }
1016
1017#endif /* CONFIG_HAVE_HW_BREAKPOINT */
1018 task->thread.hw_brk = hw_brk;
1019#else /* CONFIG_PPC_ADV_DEBUG_REGS */
1020 /* As described above, it was assumed 3 bits were passed with the data
1021 * address, but we will assume only the mode bits will be passed
1022 * as to not cause alignment restrictions for DAC-based processors.
1023 */
1024
1025 /* DAC's hold the whole address without any mode flags */
1026 task->thread.debug.dac1 = data & ~0x3UL;
1027
1028 if (task->thread.debug.dac1 == 0) {
1029 dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1030 if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0,
1031 task->thread.debug.dbcr1)) {
1032 task->thread.regs->msr &= ~MSR_DE;
1033 task->thread.debug.dbcr0 &= ~DBCR0_IDM;
1034 }
1035 return 0;
1036 }
1037
1038 /* Read or Write bits must be set */
1039
1040 if (!(data & 0x3UL))
1041 return -EINVAL;
1042
1043 /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0
1044 register */
1045 task->thread.debug.dbcr0 |= DBCR0_IDM;
1046
1047 /* Check for write and read flags and set DBCR0
1048 accordingly */
1049 dbcr_dac(task) &= ~(DBCR_DAC1R|DBCR_DAC1W);
1050 if (data & 0x1UL)
1051 dbcr_dac(task) |= DBCR_DAC1R;
1052 if (data & 0x2UL)
1053 dbcr_dac(task) |= DBCR_DAC1W;
1054 task->thread.regs->msr |= MSR_DE;
1055#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1056 return 0;
1057}
1058
1059/*
1060 * Called by kernel/ptrace.c when detaching..
1061 *
1062 * Make sure single step bits etc are not set.
1063 */
1064void ptrace_disable(struct task_struct *child)
1065{
1066 /* make sure the single step bit is not set. */
1067 user_disable_single_step(child);
1068}
1069
1070#ifdef CONFIG_PPC_ADV_DEBUG_REGS
1071static long set_instruction_bp(struct task_struct *child,
1072 struct ppc_hw_breakpoint *bp_info)
1073{
1074 int slot;
1075 int slot1_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC1) != 0);
1076 int slot2_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC2) != 0);
1077 int slot3_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC3) != 0);
1078 int slot4_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC4) != 0);
1079
1080 if (dbcr_iac_range(child) & DBCR_IAC12MODE)
1081 slot2_in_use = 1;
1082 if (dbcr_iac_range(child) & DBCR_IAC34MODE)
1083 slot4_in_use = 1;
1084
1085 if (bp_info->addr >= TASK_SIZE)
1086 return -EIO;
1087
1088 if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) {
1089
1090 /* Make sure range is valid. */
1091 if (bp_info->addr2 >= TASK_SIZE)
1092 return -EIO;
1093
1094 /* We need a pair of IAC regsisters */
1095 if ((!slot1_in_use) && (!slot2_in_use)) {
1096 slot = 1;
1097 child->thread.debug.iac1 = bp_info->addr;
1098 child->thread.debug.iac2 = bp_info->addr2;
1099 child->thread.debug.dbcr0 |= DBCR0_IAC1;
1100 if (bp_info->addr_mode ==
1101 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
1102 dbcr_iac_range(child) |= DBCR_IAC12X;
1103 else
1104 dbcr_iac_range(child) |= DBCR_IAC12I;
1105#if CONFIG_PPC_ADV_DEBUG_IACS > 2
1106 } else if ((!slot3_in_use) && (!slot4_in_use)) {
1107 slot = 3;
1108 child->thread.debug.iac3 = bp_info->addr;
1109 child->thread.debug.iac4 = bp_info->addr2;
1110 child->thread.debug.dbcr0 |= DBCR0_IAC3;
1111 if (bp_info->addr_mode ==
1112 PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
1113 dbcr_iac_range(child) |= DBCR_IAC34X;
1114 else
1115 dbcr_iac_range(child) |= DBCR_IAC34I;
1116#endif
1117 } else
1118 return -ENOSPC;
1119 } else {
1120 /* We only need one. If possible leave a pair free in
1121 * case a range is needed later
1122 */
1123 if (!slot1_in_use) {
1124 /*
1125 * Don't use iac1 if iac1-iac2 are free and either
1126 * iac3 or iac4 (but not both) are free
1127 */
1128 if (slot2_in_use || (slot3_in_use == slot4_in_use)) {
1129 slot = 1;
1130 child->thread.debug.iac1 = bp_info->addr;
1131 child->thread.debug.dbcr0 |= DBCR0_IAC1;
1132 goto out;
1133 }
1134 }
1135 if (!slot2_in_use) {
1136 slot = 2;
1137 child->thread.debug.iac2 = bp_info->addr;
1138 child->thread.debug.dbcr0 |= DBCR0_IAC2;
1139#if CONFIG_PPC_ADV_DEBUG_IACS > 2
1140 } else if (!slot3_in_use) {
1141 slot = 3;
1142 child->thread.debug.iac3 = bp_info->addr;
1143 child->thread.debug.dbcr0 |= DBCR0_IAC3;
1144 } else if (!slot4_in_use) {
1145 slot = 4;
1146 child->thread.debug.iac4 = bp_info->addr;
1147 child->thread.debug.dbcr0 |= DBCR0_IAC4;
1148#endif
1149 } else
1150 return -ENOSPC;
1151 }
1152out:
1153 child->thread.debug.dbcr0 |= DBCR0_IDM;
1154 child->thread.regs->msr |= MSR_DE;
1155
1156 return slot;
1157}
1158
1159static int del_instruction_bp(struct task_struct *child, int slot)
1160{
1161 switch (slot) {
1162 case 1:
1163 if ((child->thread.debug.dbcr0 & DBCR0_IAC1) == 0)
1164 return -ENOENT;
1165
1166 if (dbcr_iac_range(child) & DBCR_IAC12MODE) {
1167 /* address range - clear slots 1 & 2 */
1168 child->thread.debug.iac2 = 0;
1169 dbcr_iac_range(child) &= ~DBCR_IAC12MODE;
1170 }
1171 child->thread.debug.iac1 = 0;
1172 child->thread.debug.dbcr0 &= ~DBCR0_IAC1;
1173 break;
1174 case 2:
1175 if ((child->thread.debug.dbcr0 & DBCR0_IAC2) == 0)
1176 return -ENOENT;
1177
1178 if (dbcr_iac_range(child) & DBCR_IAC12MODE)
1179 /* used in a range */
1180 return -EINVAL;
1181 child->thread.debug.iac2 = 0;
1182 child->thread.debug.dbcr0 &= ~DBCR0_IAC2;
1183 break;
1184#if CONFIG_PPC_ADV_DEBUG_IACS > 2
1185 case 3:
1186 if ((child->thread.debug.dbcr0 & DBCR0_IAC3) == 0)
1187 return -ENOENT;
1188
1189 if (dbcr_iac_range(child) & DBCR_IAC34MODE) {
1190 /* address range - clear slots 3 & 4 */
1191 child->thread.debug.iac4 = 0;
1192 dbcr_iac_range(child) &= ~DBCR_IAC34MODE;
1193 }
1194 child->thread.debug.iac3 = 0;
1195 child->thread.debug.dbcr0 &= ~DBCR0_IAC3;
1196 break;
1197 case 4:
1198 if ((child->thread.debug.dbcr0 & DBCR0_IAC4) == 0)
1199 return -ENOENT;
1200
1201 if (dbcr_iac_range(child) & DBCR_IAC34MODE)
1202 /* Used in a range */
1203 return -EINVAL;
1204 child->thread.debug.iac4 = 0;
1205 child->thread.debug.dbcr0 &= ~DBCR0_IAC4;
1206 break;
1207#endif
1208 default:
1209 return -EINVAL;
1210 }
1211 return 0;
1212}
1213
1214static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info)
1215{
1216 int byte_enable =
1217 (bp_info->condition_mode >> PPC_BREAKPOINT_CONDITION_BE_SHIFT)
1218 & 0xf;
1219 int condition_mode =
1220 bp_info->condition_mode & PPC_BREAKPOINT_CONDITION_MODE;
1221 int slot;
1222
1223 if (byte_enable && (condition_mode == 0))
1224 return -EINVAL;
1225
1226 if (bp_info->addr >= TASK_SIZE)
1227 return -EIO;
1228
1229 if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) {
1230 slot = 1;
1231 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
1232 dbcr_dac(child) |= DBCR_DAC1R;
1233 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1234 dbcr_dac(child) |= DBCR_DAC1W;
1235 child->thread.debug.dac1 = (unsigned long)bp_info->addr;
1236#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1237 if (byte_enable) {
1238 child->thread.debug.dvc1 =
1239 (unsigned long)bp_info->condition_value;
1240 child->thread.debug.dbcr2 |=
1241 ((byte_enable << DBCR2_DVC1BE_SHIFT) |
1242 (condition_mode << DBCR2_DVC1M_SHIFT));
1243 }
1244#endif
1245#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1246 } else if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) {
1247 /* Both dac1 and dac2 are part of a range */
1248 return -ENOSPC;
1249#endif
1250 } else if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) {
1251 slot = 2;
1252 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
1253 dbcr_dac(child) |= DBCR_DAC2R;
1254 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1255 dbcr_dac(child) |= DBCR_DAC2W;
1256 child->thread.debug.dac2 = (unsigned long)bp_info->addr;
1257#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1258 if (byte_enable) {
1259 child->thread.debug.dvc2 =
1260 (unsigned long)bp_info->condition_value;
1261 child->thread.debug.dbcr2 |=
1262 ((byte_enable << DBCR2_DVC2BE_SHIFT) |
1263 (condition_mode << DBCR2_DVC2M_SHIFT));
1264 }
1265#endif
1266 } else
1267 return -ENOSPC;
1268 child->thread.debug.dbcr0 |= DBCR0_IDM;
1269 child->thread.regs->msr |= MSR_DE;
1270
1271 return slot + 4;
1272}
1273
1274static int del_dac(struct task_struct *child, int slot)
1275{
1276 if (slot == 1) {
1277 if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0)
1278 return -ENOENT;
1279
1280 child->thread.debug.dac1 = 0;
1281 dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1282#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1283 if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) {
1284 child->thread.debug.dac2 = 0;
1285 child->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
1286 }
1287 child->thread.debug.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE);
1288#endif
1289#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1290 child->thread.debug.dvc1 = 0;
1291#endif
1292 } else if (slot == 2) {
1293 if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0)
1294 return -ENOENT;
1295
1296#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1297 if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE)
1298 /* Part of a range */
1299 return -EINVAL;
1300 child->thread.debug.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE);
1301#endif
1302#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
1303 child->thread.debug.dvc2 = 0;
1304#endif
1305 child->thread.debug.dac2 = 0;
1306 dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1307 } else
1308 return -EINVAL;
1309
1310 return 0;
1311}
1312#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1313
1314#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1315static int set_dac_range(struct task_struct *child,
1316 struct ppc_hw_breakpoint *bp_info)
1317{
1318 int mode = bp_info->addr_mode & PPC_BREAKPOINT_MODE_MASK;
1319
1320 /* We don't allow range watchpoints to be used with DVC */
1321 if (bp_info->condition_mode)
1322 return -EINVAL;
1323
1324 /*
1325 * Best effort to verify the address range. The user/supervisor bits
1326 * prevent trapping in kernel space, but let's fail on an obvious bad
1327 * range. The simple test on the mask is not fool-proof, and any
1328 * exclusive range will spill over into kernel space.
1329 */
1330 if (bp_info->addr >= TASK_SIZE)
1331 return -EIO;
1332 if (mode == PPC_BREAKPOINT_MODE_MASK) {
1333 /*
1334 * dac2 is a bitmask. Don't allow a mask that makes a
1335 * kernel space address from a valid dac1 value
1336 */
1337 if (~((unsigned long)bp_info->addr2) >= TASK_SIZE)
1338 return -EIO;
1339 } else {
1340 /*
1341 * For range breakpoints, addr2 must also be a valid address
1342 */
1343 if (bp_info->addr2 >= TASK_SIZE)
1344 return -EIO;
1345 }
1346
1347 if (child->thread.debug.dbcr0 &
1348 (DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W))
1349 return -ENOSPC;
1350
1351 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
1352 child->thread.debug.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM);
1353 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1354 child->thread.debug.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM);
1355 child->thread.debug.dac1 = bp_info->addr;
1356 child->thread.debug.dac2 = bp_info->addr2;
1357 if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE)
1358 child->thread.debug.dbcr2 |= DBCR2_DAC12M;
1359 else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
1360 child->thread.debug.dbcr2 |= DBCR2_DAC12MX;
1361 else /* PPC_BREAKPOINT_MODE_MASK */
1362 child->thread.debug.dbcr2 |= DBCR2_DAC12MM;
1363 child->thread.regs->msr |= MSR_DE;
1364
1365 return 5;
1366}
1367#endif /* CONFIG_PPC_ADV_DEBUG_DAC_RANGE */
1368
1369static long ppc_set_hwdebug(struct task_struct *child,
1370 struct ppc_hw_breakpoint *bp_info)
1371{
1372#ifdef CONFIG_HAVE_HW_BREAKPOINT
1373 int len = 0;
1374 struct thread_struct *thread = &(child->thread);
1375 struct perf_event *bp;
1376 struct perf_event_attr attr;
1377#endif /* CONFIG_HAVE_HW_BREAKPOINT */
1378#ifndef CONFIG_PPC_ADV_DEBUG_REGS
1379 struct arch_hw_breakpoint brk;
1380#endif
1381
1382 if (bp_info->version != 1)
1383 return -ENOTSUPP;
1384#ifdef CONFIG_PPC_ADV_DEBUG_REGS
1385 /*
1386 * Check for invalid flags and combinations
1387 */
1388 if ((bp_info->trigger_type == 0) ||
1389 (bp_info->trigger_type & ~(PPC_BREAKPOINT_TRIGGER_EXECUTE |
1390 PPC_BREAKPOINT_TRIGGER_RW)) ||
1391 (bp_info->addr_mode & ~PPC_BREAKPOINT_MODE_MASK) ||
1392 (bp_info->condition_mode &
1393 ~(PPC_BREAKPOINT_CONDITION_MODE |
1394 PPC_BREAKPOINT_CONDITION_BE_ALL)))
1395 return -EINVAL;
1396#if CONFIG_PPC_ADV_DEBUG_DVCS == 0
1397 if (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
1398 return -EINVAL;
1399#endif
1400
1401 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_EXECUTE) {
1402 if ((bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_EXECUTE) ||
1403 (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE))
1404 return -EINVAL;
1405 return set_instruction_bp(child, bp_info);
1406 }
1407 if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT)
1408 return set_dac(child, bp_info);
1409
1410#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1411 return set_dac_range(child, bp_info);
1412#else
1413 return -EINVAL;
1414#endif
1415#else /* !CONFIG_PPC_ADV_DEBUG_DVCS */
1416 /*
1417 * We only support one data breakpoint
1418 */
1419 if ((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0 ||
1420 (bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0 ||
1421 bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
1422 return -EINVAL;
1423
1424 if ((unsigned long)bp_info->addr >= TASK_SIZE)
1425 return -EIO;
1426
1427 brk.address = bp_info->addr & ~7UL;
1428 brk.type = HW_BRK_TYPE_TRANSLATE;
1429 brk.len = 8;
1430 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
1431 brk.type |= HW_BRK_TYPE_READ;
1432 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
1433 brk.type |= HW_BRK_TYPE_WRITE;
1434#ifdef CONFIG_HAVE_HW_BREAKPOINT
1435 /*
1436 * Check if the request is for 'range' breakpoints. We can
1437 * support it if range < 8 bytes.
1438 */
1439 if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE)
1440 len = bp_info->addr2 - bp_info->addr;
1441 else if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT)
1442 len = 1;
1443 else
1444 return -EINVAL;
1445 bp = thread->ptrace_bps[0];
1446 if (bp)
1447 return -ENOSPC;
1448
1449 /* Create a new breakpoint request if one doesn't exist already */
1450 hw_breakpoint_init(&attr);
1451 attr.bp_addr = (unsigned long)bp_info->addr & ~HW_BREAKPOINT_ALIGN;
1452 attr.bp_len = len;
1453 arch_bp_generic_fields(brk.type, &attr.bp_type);
1454
1455 thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
1456 ptrace_triggered, NULL, child);
1457 if (IS_ERR(bp)) {
1458 thread->ptrace_bps[0] = NULL;
1459 return PTR_ERR(bp);
1460 }
1461
1462 return 1;
1463#endif /* CONFIG_HAVE_HW_BREAKPOINT */
1464
1465 if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT)
1466 return -EINVAL;
1467
1468 if (child->thread.hw_brk.address)
1469 return -ENOSPC;
1470
1471 child->thread.hw_brk = brk;
1472
1473 return 1;
1474#endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */
1475}
1476
1477static long ppc_del_hwdebug(struct task_struct *child, long data)
1478{
1479#ifdef CONFIG_HAVE_HW_BREAKPOINT
1480 int ret = 0;
1481 struct thread_struct *thread = &(child->thread);
1482 struct perf_event *bp;
1483#endif /* CONFIG_HAVE_HW_BREAKPOINT */
1484#ifdef CONFIG_PPC_ADV_DEBUG_REGS
1485 int rc;
1486
1487 if (data <= 4)
1488 rc = del_instruction_bp(child, (int)data);
1489 else
1490 rc = del_dac(child, (int)data - 4);
1491
1492 if (!rc) {
1493 if (!DBCR_ACTIVE_EVENTS(child->thread.debug.dbcr0,
1494 child->thread.debug.dbcr1)) {
1495 child->thread.debug.dbcr0 &= ~DBCR0_IDM;
1496 child->thread.regs->msr &= ~MSR_DE;
1497 }
1498 }
1499 return rc;
1500#else
1501 if (data != 1)
1502 return -EINVAL;
1503
1504#ifdef CONFIG_HAVE_HW_BREAKPOINT
1505 bp = thread->ptrace_bps[0];
1506 if (bp) {
1507 unregister_hw_breakpoint(bp);
1508 thread->ptrace_bps[0] = NULL;
1509 } else
1510 ret = -ENOENT;
1511 return ret;
1512#else /* CONFIG_HAVE_HW_BREAKPOINT */
1513 if (child->thread.hw_brk.address == 0)
1514 return -ENOENT;
1515
1516 child->thread.hw_brk.address = 0;
1517 child->thread.hw_brk.type = 0;
1518#endif /* CONFIG_HAVE_HW_BREAKPOINT */
1519
1520 return 0;
1521#endif
1522}
1523
1524long arch_ptrace(struct task_struct *child, long request,
1525 unsigned long addr, unsigned long data)
1526{
1527 int ret = -EPERM;
1528 void __user *datavp = (void __user *) data;
1529 unsigned long __user *datalp = datavp;
1530
1531 switch (request) {
1532 /* read the word at location addr in the USER area. */
1533 case PTRACE_PEEKUSR: {
1534 unsigned long index, tmp;
1535
1536 ret = -EIO;
1537 /* convert to index and check */
1538#ifdef CONFIG_PPC32
1539 index = addr >> 2;
1540 if ((addr & 3) || (index > PT_FPSCR)
1541 || (child->thread.regs == NULL))
1542#else
1543 index = addr >> 3;
1544 if ((addr & 7) || (index > PT_FPSCR))
1545#endif
1546 break;
1547
1548 CHECK_FULL_REGS(child->thread.regs);
1549 if (index < PT_FPR0) {
1550 ret = ptrace_get_reg(child, (int) index, &tmp);
1551 if (ret)
1552 break;
1553 } else {
1554 unsigned int fpidx = index - PT_FPR0;
1555
1556 flush_fp_to_thread(child);
1557 if (fpidx < (PT_FPSCR - PT_FPR0))
1558 memcpy(&tmp, &child->thread.TS_FPR(fpidx),
1559 sizeof(long));
1560 else
1561 tmp = child->thread.fp_state.fpscr;
1562 }
1563 ret = put_user(tmp, datalp);
1564 break;
1565 }
1566
1567 /* write the word at location addr in the USER area */
1568 case PTRACE_POKEUSR: {
1569 unsigned long index;
1570
1571 ret = -EIO;
1572 /* convert to index and check */
1573#ifdef CONFIG_PPC32
1574 index = addr >> 2;
1575 if ((addr & 3) || (index > PT_FPSCR)
1576 || (child->thread.regs == NULL))
1577#else
1578 index = addr >> 3;
1579 if ((addr & 7) || (index > PT_FPSCR))
1580#endif
1581 break;
1582
1583 CHECK_FULL_REGS(child->thread.regs);
1584 if (index < PT_FPR0) {
1585 ret = ptrace_put_reg(child, index, data);
1586 } else {
1587 unsigned int fpidx = index - PT_FPR0;
1588
1589 flush_fp_to_thread(child);
1590 if (fpidx < (PT_FPSCR - PT_FPR0))
1591 memcpy(&child->thread.TS_FPR(fpidx), &data,
1592 sizeof(long));
1593 else
1594 child->thread.fp_state.fpscr = data;
1595 ret = 0;
1596 }
1597 break;
1598 }
1599
1600 case PPC_PTRACE_GETHWDBGINFO: {
1601 struct ppc_debug_info dbginfo;
1602
1603 dbginfo.version = 1;
1604#ifdef CONFIG_PPC_ADV_DEBUG_REGS
1605 dbginfo.num_instruction_bps = CONFIG_PPC_ADV_DEBUG_IACS;
1606 dbginfo.num_data_bps = CONFIG_PPC_ADV_DEBUG_DACS;
1607 dbginfo.num_condition_regs = CONFIG_PPC_ADV_DEBUG_DVCS;
1608 dbginfo.data_bp_alignment = 4;
1609 dbginfo.sizeof_condition = 4;
1610 dbginfo.features = PPC_DEBUG_FEATURE_INSN_BP_RANGE |
1611 PPC_DEBUG_FEATURE_INSN_BP_MASK;
1612#ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1613 dbginfo.features |=
1614 PPC_DEBUG_FEATURE_DATA_BP_RANGE |
1615 PPC_DEBUG_FEATURE_DATA_BP_MASK;
1616#endif
1617#else /* !CONFIG_PPC_ADV_DEBUG_REGS */
1618 dbginfo.num_instruction_bps = 0;
1619 dbginfo.num_data_bps = 1;
1620 dbginfo.num_condition_regs = 0;
1621#ifdef CONFIG_PPC64
1622 dbginfo.data_bp_alignment = 8;
1623#else
1624 dbginfo.data_bp_alignment = 4;
1625#endif
1626 dbginfo.sizeof_condition = 0;
1627#ifdef CONFIG_HAVE_HW_BREAKPOINT
1628 dbginfo.features = PPC_DEBUG_FEATURE_DATA_BP_RANGE;
1629 if (cpu_has_feature(CPU_FTR_DAWR))
1630 dbginfo.features |= PPC_DEBUG_FEATURE_DATA_BP_DAWR;
1631#else
1632 dbginfo.features = 0;
1633#endif /* CONFIG_HAVE_HW_BREAKPOINT */
1634#endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1635
1636 if (!access_ok(VERIFY_WRITE, datavp,
1637 sizeof(struct ppc_debug_info)))
1638 return -EFAULT;
1639 ret = __copy_to_user(datavp, &dbginfo,
1640 sizeof(struct ppc_debug_info)) ?
1641 -EFAULT : 0;
1642 break;
1643 }
1644
1645 case PPC_PTRACE_SETHWDEBUG: {
1646 struct ppc_hw_breakpoint bp_info;
1647
1648 if (!access_ok(VERIFY_READ, datavp,
1649 sizeof(struct ppc_hw_breakpoint)))
1650 return -EFAULT;
1651 ret = __copy_from_user(&bp_info, datavp,
1652 sizeof(struct ppc_hw_breakpoint)) ?
1653 -EFAULT : 0;
1654 if (!ret)
1655 ret = ppc_set_hwdebug(child, &bp_info);
1656 break;
1657 }
1658
1659 case PPC_PTRACE_DELHWDEBUG: {
1660 ret = ppc_del_hwdebug(child, data);
1661 break;
1662 }
1663
1664 case PTRACE_GET_DEBUGREG: {
1665#ifndef CONFIG_PPC_ADV_DEBUG_REGS
1666 unsigned long dabr_fake;
1667#endif
1668 ret = -EINVAL;
1669 /* We only support one DABR and no IABRS at the moment */
1670 if (addr > 0)
1671 break;
1672#ifdef CONFIG_PPC_ADV_DEBUG_REGS
1673 ret = put_user(child->thread.debug.dac1, datalp);
1674#else
1675 dabr_fake = ((child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) |
1676 (child->thread.hw_brk.type & HW_BRK_TYPE_DABR));
1677 ret = put_user(dabr_fake, datalp);
1678#endif
1679 break;
1680 }
1681
1682 case PTRACE_SET_DEBUGREG:
1683 ret = ptrace_set_debugreg(child, addr, data);
1684 break;
1685
1686#ifdef CONFIG_PPC64
1687 case PTRACE_GETREGS64:
1688#endif
1689 case PTRACE_GETREGS: /* Get all pt_regs from the child. */
1690 return copy_regset_to_user(child, &user_ppc_native_view,
1691 REGSET_GPR,
1692 0, sizeof(struct pt_regs),
1693 datavp);
1694
1695#ifdef CONFIG_PPC64
1696 case PTRACE_SETREGS64:
1697#endif
1698 case PTRACE_SETREGS: /* Set all gp regs in the child. */
1699 return copy_regset_from_user(child, &user_ppc_native_view,
1700 REGSET_GPR,
1701 0, sizeof(struct pt_regs),
1702 datavp);
1703
1704 case PTRACE_GETFPREGS: /* Get the child FPU state (FPR0...31 + FPSCR) */
1705 return copy_regset_to_user(child, &user_ppc_native_view,
1706 REGSET_FPR,
1707 0, sizeof(elf_fpregset_t),
1708 datavp);
1709
1710 case PTRACE_SETFPREGS: /* Set the child FPU state (FPR0...31 + FPSCR) */
1711 return copy_regset_from_user(child, &user_ppc_native_view,
1712 REGSET_FPR,
1713 0, sizeof(elf_fpregset_t),
1714 datavp);
1715
1716#ifdef CONFIG_ALTIVEC
1717 case PTRACE_GETVRREGS:
1718 return copy_regset_to_user(child, &user_ppc_native_view,
1719 REGSET_VMX,
1720 0, (33 * sizeof(vector128) +
1721 sizeof(u32)),
1722 datavp);
1723
1724 case PTRACE_SETVRREGS:
1725 return copy_regset_from_user(child, &user_ppc_native_view,
1726 REGSET_VMX,
1727 0, (33 * sizeof(vector128) +
1728 sizeof(u32)),
1729 datavp);
1730#endif
1731#ifdef CONFIG_VSX
1732 case PTRACE_GETVSRREGS:
1733 return copy_regset_to_user(child, &user_ppc_native_view,
1734 REGSET_VSX,
1735 0, 32 * sizeof(double),
1736 datavp);
1737
1738 case PTRACE_SETVSRREGS:
1739 return copy_regset_from_user(child, &user_ppc_native_view,
1740 REGSET_VSX,
1741 0, 32 * sizeof(double),
1742 datavp);
1743#endif
1744#ifdef CONFIG_SPE
1745 case PTRACE_GETEVRREGS:
1746 /* Get the child spe register state. */
1747 return copy_regset_to_user(child, &user_ppc_native_view,
1748 REGSET_SPE, 0, 35 * sizeof(u32),
1749 datavp);
1750
1751 case PTRACE_SETEVRREGS:
1752 /* Set the child spe register state. */
1753 return copy_regset_from_user(child, &user_ppc_native_view,
1754 REGSET_SPE, 0, 35 * sizeof(u32),
1755 datavp);
1756#endif
1757
1758 default:
1759 ret = ptrace_request(child, request, addr, data);
1760 break;
1761 }
1762 return ret;
1763}
1764
1765/*
1766 * We must return the syscall number to actually look up in the table.
1767 * This can be -1L to skip running any syscall at all.
1768 */
1769long do_syscall_trace_enter(struct pt_regs *regs)
1770{
1771 long ret = 0;
1772
1773 user_exit();
1774
1775 secure_computing_strict(regs->gpr[0]);
1776
1777 if (test_thread_flag(TIF_SYSCALL_TRACE) &&
1778 tracehook_report_syscall_entry(regs))
1779 /*
1780 * Tracing decided this syscall should not happen.
1781 * We'll return a bogus call number to get an ENOSYS
1782 * error, but leave the original number in regs->gpr[0].
1783 */
1784 ret = -1L;
1785
1786 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
1787 trace_sys_enter(regs, regs->gpr[0]);
1788
1789#ifdef CONFIG_PPC64
1790 if (!is_32bit_task())
1791 audit_syscall_entry(AUDIT_ARCH_PPC64,
1792 regs->gpr[0],
1793 regs->gpr[3], regs->gpr[4],
1794 regs->gpr[5], regs->gpr[6]);
1795 else
1796#endif
1797 audit_syscall_entry(AUDIT_ARCH_PPC,
1798 regs->gpr[0],
1799 regs->gpr[3] & 0xffffffff,
1800 regs->gpr[4] & 0xffffffff,
1801 regs->gpr[5] & 0xffffffff,
1802 regs->gpr[6] & 0xffffffff);
1803
1804 return ret ?: regs->gpr[0];
1805}
1806
1807void do_syscall_trace_leave(struct pt_regs *regs)
1808{
1809 int step;
1810
1811 audit_syscall_exit(regs);
1812
1813 if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
1814 trace_sys_exit(regs, regs->result);
1815
1816 step = test_thread_flag(TIF_SINGLESTEP);
1817 if (step || test_thread_flag(TIF_SYSCALL_TRACE))
1818 tracehook_report_syscall_exit(regs, step);
1819
1820 user_enter();
1821}