1/*
  2 * Copyright (c) 2015-2016 MediaTek Inc.
  3 * Author: Yong Wu <yong.wu@mediatek.com>
  4 *
  5 * This program is free software; you can redistribute it and/or modify
  6 * it under the terms of the GNU General Public License version 2 as
  7 * published by the Free Software Foundation.
  8 *
  9 * This program is distributed in the hope that it will be useful,
 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 12 * GNU General Public License for more details.
 13 */
 14#ifndef __DTS_IOMMU_PORT_MT8173_H
 15#define __DTS_IOMMU_PORT_MT8173_H
 16
 17#define MTK_M4U_ID(larb, port)		(((larb) << 5) | (port))
 18
 19#define M4U_LARB0_ID			0
 20#define M4U_LARB1_ID			1
 21#define M4U_LARB2_ID			2
 22#define M4U_LARB3_ID			3
 23#define M4U_LARB4_ID			4
 24#define M4U_LARB5_ID			5
 25
 26/* larb0 */
 27#define M4U_PORT_DISP_OVL0		MTK_M4U_ID(M4U_LARB0_ID, 0)
 28#define M4U_PORT_DISP_RDMA0		MTK_M4U_ID(M4U_LARB0_ID, 1)
 29#define M4U_PORT_DISP_WDMA0		MTK_M4U_ID(M4U_LARB0_ID, 2)
 30#define M4U_PORT_DISP_OD_R		MTK_M4U_ID(M4U_LARB0_ID, 3)
 31#define M4U_PORT_DISP_OD_W		MTK_M4U_ID(M4U_LARB0_ID, 4)
 32#define M4U_PORT_MDP_RDMA0		MTK_M4U_ID(M4U_LARB0_ID, 5)
 33#define M4U_PORT_MDP_WDMA		MTK_M4U_ID(M4U_LARB0_ID, 6)
 34#define M4U_PORT_MDP_WROT0		MTK_M4U_ID(M4U_LARB0_ID, 7)
 35
 36/* larb1 */
 37#define M4U_PORT_HW_VDEC_MC_EXT		MTK_M4U_ID(M4U_LARB1_ID, 0)
 38#define M4U_PORT_HW_VDEC_PP_EXT		MTK_M4U_ID(M4U_LARB1_ID, 1)
 39#define M4U_PORT_HW_VDEC_UFO_EXT	MTK_M4U_ID(M4U_LARB1_ID, 2)
 40#define M4U_PORT_HW_VDEC_VLD_EXT	MTK_M4U_ID(M4U_LARB1_ID, 3)
 41#define M4U_PORT_HW_VDEC_VLD2_EXT	MTK_M4U_ID(M4U_LARB1_ID, 4)
 42#define M4U_PORT_HW_VDEC_AVC_MV_EXT	MTK_M4U_ID(M4U_LARB1_ID, 5)
 43#define M4U_PORT_HW_VDEC_PRED_RD_EXT	MTK_M4U_ID(M4U_LARB1_ID, 6)
 44#define M4U_PORT_HW_VDEC_PRED_WR_EXT	MTK_M4U_ID(M4U_LARB1_ID, 7)
 45#define M4U_PORT_HW_VDEC_PPWRAP_EXT	MTK_M4U_ID(M4U_LARB1_ID, 8)
 46#define M4U_PORT_HW_VDEC_TILE		MTK_M4U_ID(M4U_LARB1_ID, 9)
 47
 48/* larb2 */
 49#define M4U_PORT_IMGO			MTK_M4U_ID(M4U_LARB2_ID, 0)
 50#define M4U_PORT_RRZO			MTK_M4U_ID(M4U_LARB2_ID, 1)
 51#define M4U_PORT_AAO			MTK_M4U_ID(M4U_LARB2_ID, 2)
 52#define M4U_PORT_LCSO			MTK_M4U_ID(M4U_LARB2_ID, 3)
 53#define M4U_PORT_ESFKO			MTK_M4U_ID(M4U_LARB2_ID, 4)
 54#define M4U_PORT_IMGO_D			MTK_M4U_ID(M4U_LARB2_ID, 5)
 55#define M4U_PORT_LSCI			MTK_M4U_ID(M4U_LARB2_ID, 6)
 56#define M4U_PORT_LSCI_D			MTK_M4U_ID(M4U_LARB2_ID, 7)
 57#define M4U_PORT_BPCI			MTK_M4U_ID(M4U_LARB2_ID, 8)
 58#define M4U_PORT_BPCI_D			MTK_M4U_ID(M4U_LARB2_ID, 9)
 59#define M4U_PORT_UFDI			MTK_M4U_ID(M4U_LARB2_ID, 10)
 60#define M4U_PORT_IMGI			MTK_M4U_ID(M4U_LARB2_ID, 11)
 61#define M4U_PORT_IMG2O			MTK_M4U_ID(M4U_LARB2_ID, 12)
 62#define M4U_PORT_IMG3O			MTK_M4U_ID(M4U_LARB2_ID, 13)
 63#define M4U_PORT_VIPI			MTK_M4U_ID(M4U_LARB2_ID, 14)
 64#define M4U_PORT_VIP2I			MTK_M4U_ID(M4U_LARB2_ID, 15)
 65#define M4U_PORT_VIP3I			MTK_M4U_ID(M4U_LARB2_ID, 16)
 66#define M4U_PORT_LCEI			MTK_M4U_ID(M4U_LARB2_ID, 17)
 67#define M4U_PORT_RB			MTK_M4U_ID(M4U_LARB2_ID, 18)
 68#define M4U_PORT_RP			MTK_M4U_ID(M4U_LARB2_ID, 19)
 69#define M4U_PORT_WR			MTK_M4U_ID(M4U_LARB2_ID, 20)
 70
 71/* larb3 */
 72#define M4U_PORT_VENC_RCPU		MTK_M4U_ID(M4U_LARB3_ID, 0)
 73#define M4U_PORT_VENC_REC		MTK_M4U_ID(M4U_LARB3_ID, 1)
 74#define M4U_PORT_VENC_BSDMA		MTK_M4U_ID(M4U_LARB3_ID, 2)
 75#define M4U_PORT_VENC_SV_COMV		MTK_M4U_ID(M4U_LARB3_ID, 3)
 76#define M4U_PORT_VENC_RD_COMV		MTK_M4U_ID(M4U_LARB3_ID, 4)
 77#define M4U_PORT_JPGENC_RDMA		MTK_M4U_ID(M4U_LARB3_ID, 5)
 78#define M4U_PORT_JPGENC_BSDMA		MTK_M4U_ID(M4U_LARB3_ID, 6)
 79#define M4U_PORT_JPGDEC_WDMA		MTK_M4U_ID(M4U_LARB3_ID, 7)
 80#define M4U_PORT_JPGDEC_BSDMA		MTK_M4U_ID(M4U_LARB3_ID, 8)
 81#define M4U_PORT_VENC_CUR_LUMA		MTK_M4U_ID(M4U_LARB3_ID, 9)
 82#define M4U_PORT_VENC_CUR_CHROMA	MTK_M4U_ID(M4U_LARB3_ID, 10)
 83#define M4U_PORT_VENC_REF_LUMA		MTK_M4U_ID(M4U_LARB3_ID, 11)
 84#define M4U_PORT_VENC_REF_CHROMA	MTK_M4U_ID(M4U_LARB3_ID, 12)
 85#define M4U_PORT_VENC_NBM_RDMA		MTK_M4U_ID(M4U_LARB3_ID, 13)
 86#define M4U_PORT_VENC_NBM_WDMA		MTK_M4U_ID(M4U_LARB3_ID, 14)
 87
 88/* larb4 */
 89#define M4U_PORT_DISP_OVL1		MTK_M4U_ID(M4U_LARB4_ID, 0)
 90#define M4U_PORT_DISP_RDMA1		MTK_M4U_ID(M4U_LARB4_ID, 1)
 91#define M4U_PORT_DISP_RDMA2		MTK_M4U_ID(M4U_LARB4_ID, 2)
 92#define M4U_PORT_DISP_WDMA1		MTK_M4U_ID(M4U_LARB4_ID, 3)
 93#define M4U_PORT_MDP_RDMA1		MTK_M4U_ID(M4U_LARB4_ID, 4)
 94#define M4U_PORT_MDP_WROT1		MTK_M4U_ID(M4U_LARB4_ID, 5)
 95
 96/* larb5 */
 97#define M4U_PORT_VENC_RCPU_SET2		MTK_M4U_ID(M4U_LARB5_ID, 0)
 98#define M4U_PORT_VENC_REC_FRM_SET2	MTK_M4U_ID(M4U_LARB5_ID, 1)
 99#define M4U_PORT_VENC_REF_LUMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 2)
100#define M4U_PORT_VENC_REC_CHROMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 3)
101#define M4U_PORT_VENC_BSDMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 4)
102#define M4U_PORT_VENC_CUR_LUMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 5)
103#define M4U_PORT_VENC_CUR_CHROMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 6)
104#define M4U_PORT_VENC_RD_COMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 7)
105#define M4U_PORT_VENC_SV_COMA_SET2	MTK_M4U_ID(M4U_LARB5_ID, 8)
106
107#endif