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1/*
2 * Copyright (c) 2015-2016 MediaTek Inc.
3 * Author: Yong Wu <yong.wu@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14#ifndef __DTS_IOMMU_PORT_MT8173_H
15#define __DTS_IOMMU_PORT_MT8173_H
16
17#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
18/* Local arbiter ID */
19#define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0x7)
20/* PortID within the local arbiter */
21#define MTK_M4U_TO_PORT(id) ((id) & 0x1f)
22
23#define M4U_LARB0_ID 0
24#define M4U_LARB1_ID 1
25#define M4U_LARB2_ID 2
26#define M4U_LARB3_ID 3
27#define M4U_LARB4_ID 4
28#define M4U_LARB5_ID 5
29
30/* larb0 */
31#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
32#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1)
33#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2)
34#define M4U_PORT_DISP_OD_R MTK_M4U_ID(M4U_LARB0_ID, 3)
35#define M4U_PORT_DISP_OD_W MTK_M4U_ID(M4U_LARB0_ID, 4)
36#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5)
37#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 6)
38#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7)
39
40/* larb1 */
41#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0)
42#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1)
43#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB1_ID, 2)
44#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 3)
45#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB1_ID, 4)
46#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 5)
47#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 6)
48#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 7)
49#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 8)
50#define M4U_PORT_HW_VDEC_TILE MTK_M4U_ID(M4U_LARB1_ID, 9)
51
52/* larb2 */
53#define M4U_PORT_IMGO MTK_M4U_ID(M4U_LARB2_ID, 0)
54#define M4U_PORT_RRZO MTK_M4U_ID(M4U_LARB2_ID, 1)
55#define M4U_PORT_AAO MTK_M4U_ID(M4U_LARB2_ID, 2)
56#define M4U_PORT_LCSO MTK_M4U_ID(M4U_LARB2_ID, 3)
57#define M4U_PORT_ESFKO MTK_M4U_ID(M4U_LARB2_ID, 4)
58#define M4U_PORT_IMGO_D MTK_M4U_ID(M4U_LARB2_ID, 5)
59#define M4U_PORT_LSCI MTK_M4U_ID(M4U_LARB2_ID, 6)
60#define M4U_PORT_LSCI_D MTK_M4U_ID(M4U_LARB2_ID, 7)
61#define M4U_PORT_BPCI MTK_M4U_ID(M4U_LARB2_ID, 8)
62#define M4U_PORT_BPCI_D MTK_M4U_ID(M4U_LARB2_ID, 9)
63#define M4U_PORT_UFDI MTK_M4U_ID(M4U_LARB2_ID, 10)
64#define M4U_PORT_IMGI MTK_M4U_ID(M4U_LARB2_ID, 11)
65#define M4U_PORT_IMG2O MTK_M4U_ID(M4U_LARB2_ID, 12)
66#define M4U_PORT_IMG3O MTK_M4U_ID(M4U_LARB2_ID, 13)
67#define M4U_PORT_VIPI MTK_M4U_ID(M4U_LARB2_ID, 14)
68#define M4U_PORT_VIP2I MTK_M4U_ID(M4U_LARB2_ID, 15)
69#define M4U_PORT_VIP3I MTK_M4U_ID(M4U_LARB2_ID, 16)
70#define M4U_PORT_LCEI MTK_M4U_ID(M4U_LARB2_ID, 17)
71#define M4U_PORT_RB MTK_M4U_ID(M4U_LARB2_ID, 18)
72#define M4U_PORT_RP MTK_M4U_ID(M4U_LARB2_ID, 19)
73#define M4U_PORT_WR MTK_M4U_ID(M4U_LARB2_ID, 20)
74
75/* larb3 */
76#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB3_ID, 0)
77#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB3_ID, 1)
78#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 2)
79#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB3_ID, 3)
80#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB3_ID, 4)
81#define M4U_PORT_JPGENC_RDMA MTK_M4U_ID(M4U_LARB3_ID, 5)
82#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 6)
83#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB3_ID, 7)
84#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB3_ID, 8)
85#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB3_ID, 9)
86#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 10)
87#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB3_ID, 11)
88#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB3_ID, 12)
89#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB3_ID, 13)
90#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB3_ID, 14)
91
92/* larb4 */
93#define M4U_PORT_DISP_OVL1 MTK_M4U_ID(M4U_LARB4_ID, 0)
94#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 1)
95#define M4U_PORT_DISP_RDMA2 MTK_M4U_ID(M4U_LARB4_ID, 2)
96#define M4U_PORT_DISP_WDMA1 MTK_M4U_ID(M4U_LARB4_ID, 3)
97#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB4_ID, 4)
98#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB4_ID, 5)
99
100/* larb5 */
101#define M4U_PORT_VENC_RCPU_SET2 MTK_M4U_ID(M4U_LARB5_ID, 0)
102#define M4U_PORT_VENC_REC_FRM_SET2 MTK_M4U_ID(M4U_LARB5_ID, 1)
103#define M4U_PORT_VENC_REF_LUMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 2)
104#define M4U_PORT_VENC_REC_CHROMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 3)
105#define M4U_PORT_VENC_BSDMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 4)
106#define M4U_PORT_VENC_CUR_LUMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 5)
107#define M4U_PORT_VENC_CUR_CHROMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 6)
108#define M4U_PORT_VENC_RD_COMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 7)
109#define M4U_PORT_VENC_SV_COMA_SET2 MTK_M4U_ID(M4U_LARB5_ID, 8)
110
111#endif