Loading...
1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
17#include <linux/smp.h>
18#include <linux/stddef.h>
19#include <linux/export.h>
20
21#include <asm/bugs.h>
22#include <asm/cpu.h>
23#include <asm/cpu-features.h>
24#include <asm/cpu-type.h>
25#include <asm/fpu.h>
26#include <asm/mipsregs.h>
27#include <asm/mipsmtregs.h>
28#include <asm/msa.h>
29#include <asm/watch.h>
30#include <asm/elf.h>
31#include <asm/pgtable-bits.h>
32#include <asm/spram.h>
33#include <linux/uaccess.h>
34
35/* Hardware capabilities */
36unsigned int elf_hwcap __read_mostly;
37EXPORT_SYMBOL_GPL(elf_hwcap);
38
39/*
40 * Get the FPU Implementation/Revision.
41 */
42static inline unsigned long cpu_get_fpu_id(void)
43{
44 unsigned long tmp, fpu_id;
45
46 tmp = read_c0_status();
47 __enable_fpu(FPU_AS_IS);
48 fpu_id = read_32bit_cp1_register(CP1_REVISION);
49 write_c0_status(tmp);
50 return fpu_id;
51}
52
53/*
54 * Check if the CPU has an external FPU.
55 */
56static inline int __cpu_has_fpu(void)
57{
58 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
59}
60
61static inline unsigned long cpu_get_msa_id(void)
62{
63 unsigned long status, msa_id;
64
65 status = read_c0_status();
66 __enable_fpu(FPU_64BIT);
67 enable_msa();
68 msa_id = read_msa_ir();
69 disable_msa();
70 write_c0_status(status);
71 return msa_id;
72}
73
74/*
75 * Determine the FCSR mask for FPU hardware.
76 */
77static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
78{
79 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
80
81 fcsr = c->fpu_csr31;
82 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
83
84 sr = read_c0_status();
85 __enable_fpu(FPU_AS_IS);
86
87 fcsr0 = fcsr & mask;
88 write_32bit_cp1_register(CP1_STATUS, fcsr0);
89 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
90
91 fcsr1 = fcsr | ~mask;
92 write_32bit_cp1_register(CP1_STATUS, fcsr1);
93 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
94
95 write_32bit_cp1_register(CP1_STATUS, fcsr);
96
97 write_c0_status(sr);
98
99 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
100}
101
102/*
103 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
104 * supported by FPU hardware.
105 */
106static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
107{
108 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
109 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
110 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
111 unsigned long sr, fir, fcsr, fcsr0, fcsr1;
112
113 sr = read_c0_status();
114 __enable_fpu(FPU_AS_IS);
115
116 fir = read_32bit_cp1_register(CP1_REVISION);
117 if (fir & MIPS_FPIR_HAS2008) {
118 fcsr = read_32bit_cp1_register(CP1_STATUS);
119
120 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
121 write_32bit_cp1_register(CP1_STATUS, fcsr0);
122 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
123
124 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
125 write_32bit_cp1_register(CP1_STATUS, fcsr1);
126 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
127
128 write_32bit_cp1_register(CP1_STATUS, fcsr);
129
130 if (!(fcsr0 & FPU_CSR_NAN2008))
131 c->options |= MIPS_CPU_NAN_LEGACY;
132 if (fcsr1 & FPU_CSR_NAN2008)
133 c->options |= MIPS_CPU_NAN_2008;
134
135 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
136 c->fpu_msk31 &= ~FPU_CSR_ABS2008;
137 else
138 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
139
140 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
141 c->fpu_msk31 &= ~FPU_CSR_NAN2008;
142 else
143 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
144 } else {
145 c->options |= MIPS_CPU_NAN_LEGACY;
146 }
147
148 write_c0_status(sr);
149 } else {
150 c->options |= MIPS_CPU_NAN_LEGACY;
151 }
152}
153
154/*
155 * IEEE 754 conformance mode to use. Affects the NaN encoding and the
156 * ABS.fmt/NEG.fmt execution mode.
157 */
158static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
159
160/*
161 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
162 * to support by the FPU emulator according to the IEEE 754 conformance
163 * mode selected. Note that "relaxed" straps the emulator so that it
164 * allows 2008-NaN binaries even for legacy processors.
165 */
166static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
167{
168 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
169 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
170 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
171
172 switch (ieee754) {
173 case STRICT:
174 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
175 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
176 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
177 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
178 } else {
179 c->options |= MIPS_CPU_NAN_LEGACY;
180 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
181 }
182 break;
183 case LEGACY:
184 c->options |= MIPS_CPU_NAN_LEGACY;
185 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
186 break;
187 case STD2008:
188 c->options |= MIPS_CPU_NAN_2008;
189 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
190 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
191 break;
192 case RELAXED:
193 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
194 break;
195 }
196}
197
198/*
199 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
200 * according to the "ieee754=" parameter.
201 */
202static void cpu_set_nan_2008(struct cpuinfo_mips *c)
203{
204 switch (ieee754) {
205 case STRICT:
206 mips_use_nan_legacy = !!cpu_has_nan_legacy;
207 mips_use_nan_2008 = !!cpu_has_nan_2008;
208 break;
209 case LEGACY:
210 mips_use_nan_legacy = !!cpu_has_nan_legacy;
211 mips_use_nan_2008 = !cpu_has_nan_legacy;
212 break;
213 case STD2008:
214 mips_use_nan_legacy = !cpu_has_nan_2008;
215 mips_use_nan_2008 = !!cpu_has_nan_2008;
216 break;
217 case RELAXED:
218 mips_use_nan_legacy = true;
219 mips_use_nan_2008 = true;
220 break;
221 }
222}
223
224/*
225 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
226 * settings:
227 *
228 * strict: accept binaries that request a NaN encoding supported by the FPU
229 * legacy: only accept legacy-NaN binaries
230 * 2008: only accept 2008-NaN binaries
231 * relaxed: accept any binaries regardless of whether supported by the FPU
232 */
233static int __init ieee754_setup(char *s)
234{
235 if (!s)
236 return -1;
237 else if (!strcmp(s, "strict"))
238 ieee754 = STRICT;
239 else if (!strcmp(s, "legacy"))
240 ieee754 = LEGACY;
241 else if (!strcmp(s, "2008"))
242 ieee754 = STD2008;
243 else if (!strcmp(s, "relaxed"))
244 ieee754 = RELAXED;
245 else
246 return -1;
247
248 if (!(boot_cpu_data.options & MIPS_CPU_FPU))
249 cpu_set_nofpu_2008(&boot_cpu_data);
250 cpu_set_nan_2008(&boot_cpu_data);
251
252 return 0;
253}
254
255early_param("ieee754", ieee754_setup);
256
257/*
258 * Set the FIR feature flags for the FPU emulator.
259 */
260static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
261{
262 u32 value;
263
264 value = 0;
265 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
266 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
267 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
268 value |= MIPS_FPIR_D | MIPS_FPIR_S;
269 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
270 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
271 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
272 if (c->options & MIPS_CPU_NAN_2008)
273 value |= MIPS_FPIR_HAS2008;
274 c->fpu_id = value;
275}
276
277/* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
278static unsigned int mips_nofpu_msk31;
279
280/*
281 * Set options for FPU hardware.
282 */
283static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
284{
285 c->fpu_id = cpu_get_fpu_id();
286 mips_nofpu_msk31 = c->fpu_msk31;
287
288 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
289 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
290 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
291 if (c->fpu_id & MIPS_FPIR_3D)
292 c->ases |= MIPS_ASE_MIPS3D;
293 if (c->fpu_id & MIPS_FPIR_UFRP)
294 c->options |= MIPS_CPU_UFR;
295 if (c->fpu_id & MIPS_FPIR_FREP)
296 c->options |= MIPS_CPU_FRE;
297 }
298
299 cpu_set_fpu_fcsr_mask(c);
300 cpu_set_fpu_2008(c);
301 cpu_set_nan_2008(c);
302}
303
304/*
305 * Set options for the FPU emulator.
306 */
307static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
308{
309 c->options &= ~MIPS_CPU_FPU;
310 c->fpu_msk31 = mips_nofpu_msk31;
311
312 cpu_set_nofpu_2008(c);
313 cpu_set_nan_2008(c);
314 cpu_set_nofpu_id(c);
315}
316
317static int mips_fpu_disabled;
318
319static int __init fpu_disable(char *s)
320{
321 cpu_set_nofpu_opts(&boot_cpu_data);
322 mips_fpu_disabled = 1;
323
324 return 1;
325}
326
327__setup("nofpu", fpu_disable);
328
329static int mips_dsp_disabled;
330
331static int __init dsp_disable(char *s)
332{
333 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
334 mips_dsp_disabled = 1;
335
336 return 1;
337}
338
339__setup("nodsp", dsp_disable);
340
341static int mips_htw_disabled;
342
343static int __init htw_disable(char *s)
344{
345 mips_htw_disabled = 1;
346 cpu_data[0].options &= ~MIPS_CPU_HTW;
347 write_c0_pwctl(read_c0_pwctl() &
348 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
349
350 return 1;
351}
352
353__setup("nohtw", htw_disable);
354
355static int mips_ftlb_disabled;
356static int mips_has_ftlb_configured;
357
358enum ftlb_flags {
359 FTLB_EN = 1 << 0,
360 FTLB_SET_PROB = 1 << 1,
361};
362
363static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags);
364
365static int __init ftlb_disable(char *s)
366{
367 unsigned int config4, mmuextdef;
368
369 /*
370 * If the core hasn't done any FTLB configuration, there is nothing
371 * for us to do here.
372 */
373 if (!mips_has_ftlb_configured)
374 return 1;
375
376 /* Disable it in the boot cpu */
377 if (set_ftlb_enable(&cpu_data[0], 0)) {
378 pr_warn("Can't turn FTLB off\n");
379 return 1;
380 }
381
382 config4 = read_c0_config4();
383
384 /* Check that FTLB has been disabled */
385 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
386 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
387 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
388 /* This should never happen */
389 pr_warn("FTLB could not be disabled!\n");
390 return 1;
391 }
392
393 mips_ftlb_disabled = 1;
394 mips_has_ftlb_configured = 0;
395
396 /*
397 * noftlb is mainly used for debug purposes so print
398 * an informative message instead of using pr_debug()
399 */
400 pr_info("FTLB has been disabled\n");
401
402 /*
403 * Some of these bits are duplicated in the decode_config4.
404 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
405 * once FTLB has been disabled so undo what decode_config4 did.
406 */
407 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
408 cpu_data[0].tlbsizeftlbsets;
409 cpu_data[0].tlbsizeftlbsets = 0;
410 cpu_data[0].tlbsizeftlbways = 0;
411
412 return 1;
413}
414
415__setup("noftlb", ftlb_disable);
416
417
418static inline void check_errata(void)
419{
420 struct cpuinfo_mips *c = ¤t_cpu_data;
421
422 switch (current_cpu_type()) {
423 case CPU_34K:
424 /*
425 * Erratum "RPS May Cause Incorrect Instruction Execution"
426 * This code only handles VPE0, any SMP/RTOS code
427 * making use of VPE1 will be responsable for that VPE.
428 */
429 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
430 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
431 break;
432 default:
433 break;
434 }
435}
436
437void __init check_bugs32(void)
438{
439 check_errata();
440}
441
442/*
443 * Probe whether cpu has config register by trying to play with
444 * alternate cache bit and see whether it matters.
445 * It's used by cpu_probe to distinguish between R3000A and R3081.
446 */
447static inline int cpu_has_confreg(void)
448{
449#ifdef CONFIG_CPU_R3000
450 extern unsigned long r3k_cache_size(unsigned long);
451 unsigned long size1, size2;
452 unsigned long cfg = read_c0_conf();
453
454 size1 = r3k_cache_size(ST0_ISC);
455 write_c0_conf(cfg ^ R30XX_CONF_AC);
456 size2 = r3k_cache_size(ST0_ISC);
457 write_c0_conf(cfg);
458 return size1 != size2;
459#else
460 return 0;
461#endif
462}
463
464static inline void set_elf_platform(int cpu, const char *plat)
465{
466 if (cpu == 0)
467 __elf_platform = plat;
468}
469
470static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
471{
472#ifdef __NEED_VMBITS_PROBE
473 write_c0_entryhi(0x3fffffffffffe000ULL);
474 back_to_back_c0_hazard();
475 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
476#endif
477}
478
479static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
480{
481 switch (isa) {
482 case MIPS_CPU_ISA_M64R2:
483 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
484 case MIPS_CPU_ISA_M64R1:
485 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
486 case MIPS_CPU_ISA_V:
487 c->isa_level |= MIPS_CPU_ISA_V;
488 case MIPS_CPU_ISA_IV:
489 c->isa_level |= MIPS_CPU_ISA_IV;
490 case MIPS_CPU_ISA_III:
491 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
492 break;
493
494 /* R6 incompatible with everything else */
495 case MIPS_CPU_ISA_M64R6:
496 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
497 case MIPS_CPU_ISA_M32R6:
498 c->isa_level |= MIPS_CPU_ISA_M32R6;
499 /* Break here so we don't add incompatible ISAs */
500 break;
501 case MIPS_CPU_ISA_M32R2:
502 c->isa_level |= MIPS_CPU_ISA_M32R2;
503 case MIPS_CPU_ISA_M32R1:
504 c->isa_level |= MIPS_CPU_ISA_M32R1;
505 case MIPS_CPU_ISA_II:
506 c->isa_level |= MIPS_CPU_ISA_II;
507 break;
508 }
509}
510
511static char unknown_isa[] = KERN_ERR \
512 "Unsupported ISA type, c0.config0: %d.";
513
514static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
515{
516
517 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
518
519 /*
520 * 0 = All TLBWR instructions go to FTLB
521 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
522 * FTLB and 1 goes to the VTLB.
523 * 2 = 7:1: As above with 7:1 ratio.
524 * 3 = 3:1: As above with 3:1 ratio.
525 *
526 * Use the linear midpoint as the probability threshold.
527 */
528 if (probability >= 12)
529 return 1;
530 else if (probability >= 6)
531 return 2;
532 else
533 /*
534 * So FTLB is less than 4 times bigger than VTLB.
535 * A 3:1 ratio can still be useful though.
536 */
537 return 3;
538}
539
540static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
541{
542 unsigned int config;
543
544 /* It's implementation dependent how the FTLB can be enabled */
545 switch (c->cputype) {
546 case CPU_PROAPTIV:
547 case CPU_P5600:
548 case CPU_P6600:
549 /* proAptiv & related cores use Config6 to enable the FTLB */
550 config = read_c0_config6();
551
552 if (flags & FTLB_EN)
553 config |= MIPS_CONF6_FTLBEN;
554 else
555 config &= ~MIPS_CONF6_FTLBEN;
556
557 if (flags & FTLB_SET_PROB) {
558 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
559 config |= calculate_ftlb_probability(c)
560 << MIPS_CONF6_FTLBP_SHIFT;
561 }
562
563 write_c0_config6(config);
564 back_to_back_c0_hazard();
565 break;
566 case CPU_I6400:
567 case CPU_I6500:
568 /* There's no way to disable the FTLB */
569 if (!(flags & FTLB_EN))
570 return 1;
571 return 0;
572 case CPU_LOONGSON3:
573 /* Flush ITLB, DTLB, VTLB and FTLB */
574 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
575 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
576 /* Loongson-3 cores use Config6 to enable the FTLB */
577 config = read_c0_config6();
578 if (flags & FTLB_EN)
579 /* Enable FTLB */
580 write_c0_config6(config & ~MIPS_CONF6_FTLBDIS);
581 else
582 /* Disable FTLB */
583 write_c0_config6(config | MIPS_CONF6_FTLBDIS);
584 break;
585 default:
586 return 1;
587 }
588
589 return 0;
590}
591
592static inline unsigned int decode_config0(struct cpuinfo_mips *c)
593{
594 unsigned int config0;
595 int isa, mt;
596
597 config0 = read_c0_config();
598
599 /*
600 * Look for Standard TLB or Dual VTLB and FTLB
601 */
602 mt = config0 & MIPS_CONF_MT;
603 if (mt == MIPS_CONF_MT_TLB)
604 c->options |= MIPS_CPU_TLB;
605 else if (mt == MIPS_CONF_MT_FTLB)
606 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
607
608 isa = (config0 & MIPS_CONF_AT) >> 13;
609 switch (isa) {
610 case 0:
611 switch ((config0 & MIPS_CONF_AR) >> 10) {
612 case 0:
613 set_isa(c, MIPS_CPU_ISA_M32R1);
614 break;
615 case 1:
616 set_isa(c, MIPS_CPU_ISA_M32R2);
617 break;
618 case 2:
619 set_isa(c, MIPS_CPU_ISA_M32R6);
620 break;
621 default:
622 goto unknown;
623 }
624 break;
625 case 2:
626 switch ((config0 & MIPS_CONF_AR) >> 10) {
627 case 0:
628 set_isa(c, MIPS_CPU_ISA_M64R1);
629 break;
630 case 1:
631 set_isa(c, MIPS_CPU_ISA_M64R2);
632 break;
633 case 2:
634 set_isa(c, MIPS_CPU_ISA_M64R6);
635 break;
636 default:
637 goto unknown;
638 }
639 break;
640 default:
641 goto unknown;
642 }
643
644 return config0 & MIPS_CONF_M;
645
646unknown:
647 panic(unknown_isa, config0);
648}
649
650static inline unsigned int decode_config1(struct cpuinfo_mips *c)
651{
652 unsigned int config1;
653
654 config1 = read_c0_config1();
655
656 if (config1 & MIPS_CONF1_MD)
657 c->ases |= MIPS_ASE_MDMX;
658 if (config1 & MIPS_CONF1_PC)
659 c->options |= MIPS_CPU_PERF;
660 if (config1 & MIPS_CONF1_WR)
661 c->options |= MIPS_CPU_WATCH;
662 if (config1 & MIPS_CONF1_CA)
663 c->ases |= MIPS_ASE_MIPS16;
664 if (config1 & MIPS_CONF1_EP)
665 c->options |= MIPS_CPU_EJTAG;
666 if (config1 & MIPS_CONF1_FP) {
667 c->options |= MIPS_CPU_FPU;
668 c->options |= MIPS_CPU_32FPR;
669 }
670 if (cpu_has_tlb) {
671 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
672 c->tlbsizevtlb = c->tlbsize;
673 c->tlbsizeftlbsets = 0;
674 }
675
676 return config1 & MIPS_CONF_M;
677}
678
679static inline unsigned int decode_config2(struct cpuinfo_mips *c)
680{
681 unsigned int config2;
682
683 config2 = read_c0_config2();
684
685 if (config2 & MIPS_CONF2_SL)
686 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
687
688 return config2 & MIPS_CONF_M;
689}
690
691static inline unsigned int decode_config3(struct cpuinfo_mips *c)
692{
693 unsigned int config3;
694
695 config3 = read_c0_config3();
696
697 if (config3 & MIPS_CONF3_SM) {
698 c->ases |= MIPS_ASE_SMARTMIPS;
699 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;
700 }
701 if (config3 & MIPS_CONF3_RXI)
702 c->options |= MIPS_CPU_RIXI;
703 if (config3 & MIPS_CONF3_CTXTC)
704 c->options |= MIPS_CPU_CTXTC;
705 if (config3 & MIPS_CONF3_DSP)
706 c->ases |= MIPS_ASE_DSP;
707 if (config3 & MIPS_CONF3_DSP2P) {
708 c->ases |= MIPS_ASE_DSP2P;
709 if (cpu_has_mips_r6)
710 c->ases |= MIPS_ASE_DSP3;
711 }
712 if (config3 & MIPS_CONF3_VINT)
713 c->options |= MIPS_CPU_VINT;
714 if (config3 & MIPS_CONF3_VEIC)
715 c->options |= MIPS_CPU_VEIC;
716 if (config3 & MIPS_CONF3_LPA)
717 c->options |= MIPS_CPU_LPA;
718 if (config3 & MIPS_CONF3_MT)
719 c->ases |= MIPS_ASE_MIPSMT;
720 if (config3 & MIPS_CONF3_ULRI)
721 c->options |= MIPS_CPU_ULRI;
722 if (config3 & MIPS_CONF3_ISA)
723 c->options |= MIPS_CPU_MICROMIPS;
724 if (config3 & MIPS_CONF3_VZ)
725 c->ases |= MIPS_ASE_VZ;
726 if (config3 & MIPS_CONF3_SC)
727 c->options |= MIPS_CPU_SEGMENTS;
728 if (config3 & MIPS_CONF3_BI)
729 c->options |= MIPS_CPU_BADINSTR;
730 if (config3 & MIPS_CONF3_BP)
731 c->options |= MIPS_CPU_BADINSTRP;
732 if (config3 & MIPS_CONF3_MSA)
733 c->ases |= MIPS_ASE_MSA;
734 if (config3 & MIPS_CONF3_PW) {
735 c->htw_seq = 0;
736 c->options |= MIPS_CPU_HTW;
737 }
738 if (config3 & MIPS_CONF3_CDMM)
739 c->options |= MIPS_CPU_CDMM;
740 if (config3 & MIPS_CONF3_SP)
741 c->options |= MIPS_CPU_SP;
742
743 return config3 & MIPS_CONF_M;
744}
745
746static inline unsigned int decode_config4(struct cpuinfo_mips *c)
747{
748 unsigned int config4;
749 unsigned int newcf4;
750 unsigned int mmuextdef;
751 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
752 unsigned long asid_mask;
753
754 config4 = read_c0_config4();
755
756 if (cpu_has_tlb) {
757 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
758 c->options |= MIPS_CPU_TLBINV;
759
760 /*
761 * R6 has dropped the MMUExtDef field from config4.
762 * On R6 the fields always describe the FTLB, and only if it is
763 * present according to Config.MT.
764 */
765 if (!cpu_has_mips_r6)
766 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
767 else if (cpu_has_ftlb)
768 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
769 else
770 mmuextdef = 0;
771
772 switch (mmuextdef) {
773 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
774 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
775 c->tlbsizevtlb = c->tlbsize;
776 break;
777 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
778 c->tlbsizevtlb +=
779 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
780 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
781 c->tlbsize = c->tlbsizevtlb;
782 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
783 /* fall through */
784 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
785 if (mips_ftlb_disabled)
786 break;
787 newcf4 = (config4 & ~ftlb_page) |
788 (page_size_ftlb(mmuextdef) <<
789 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
790 write_c0_config4(newcf4);
791 back_to_back_c0_hazard();
792 config4 = read_c0_config4();
793 if (config4 != newcf4) {
794 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
795 PAGE_SIZE, config4);
796 /* Switch FTLB off */
797 set_ftlb_enable(c, 0);
798 mips_ftlb_disabled = 1;
799 break;
800 }
801 c->tlbsizeftlbsets = 1 <<
802 ((config4 & MIPS_CONF4_FTLBSETS) >>
803 MIPS_CONF4_FTLBSETS_SHIFT);
804 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
805 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
806 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
807 mips_has_ftlb_configured = 1;
808 break;
809 }
810 }
811
812 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
813 >> MIPS_CONF4_KSCREXIST_SHIFT;
814
815 asid_mask = MIPS_ENTRYHI_ASID;
816 if (config4 & MIPS_CONF4_AE)
817 asid_mask |= MIPS_ENTRYHI_ASIDX;
818 set_cpu_asid_mask(c, asid_mask);
819
820 /*
821 * Warn if the computed ASID mask doesn't match the mask the kernel
822 * is built for. This may indicate either a serious problem or an
823 * easy optimisation opportunity, but either way should be addressed.
824 */
825 WARN_ON(asid_mask != cpu_asid_mask(c));
826
827 return config4 & MIPS_CONF_M;
828}
829
830static inline unsigned int decode_config5(struct cpuinfo_mips *c)
831{
832 unsigned int config5;
833
834 config5 = read_c0_config5();
835 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
836 write_c0_config5(config5);
837
838 if (config5 & MIPS_CONF5_EVA)
839 c->options |= MIPS_CPU_EVA;
840 if (config5 & MIPS_CONF5_MRP)
841 c->options |= MIPS_CPU_MAAR;
842 if (config5 & MIPS_CONF5_LLB)
843 c->options |= MIPS_CPU_RW_LLB;
844 if (config5 & MIPS_CONF5_MVH)
845 c->options |= MIPS_CPU_MVH;
846 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
847 c->options |= MIPS_CPU_VP;
848 if (config5 & MIPS_CONF5_CA2)
849 c->ases |= MIPS_ASE_MIPS16E2;
850
851 if (config5 & MIPS_CONF5_CRCP)
852 elf_hwcap |= HWCAP_MIPS_CRC32;
853
854 return config5 & MIPS_CONF_M;
855}
856
857static void decode_configs(struct cpuinfo_mips *c)
858{
859 int ok;
860
861 /* MIPS32 or MIPS64 compliant CPU. */
862 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
863 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
864
865 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
866
867 /* Enable FTLB if present and not disabled */
868 set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN);
869
870 ok = decode_config0(c); /* Read Config registers. */
871 BUG_ON(!ok); /* Arch spec violation! */
872 if (ok)
873 ok = decode_config1(c);
874 if (ok)
875 ok = decode_config2(c);
876 if (ok)
877 ok = decode_config3(c);
878 if (ok)
879 ok = decode_config4(c);
880 if (ok)
881 ok = decode_config5(c);
882
883 /* Probe the EBase.WG bit */
884 if (cpu_has_mips_r2_r6) {
885 u64 ebase;
886 unsigned int status;
887
888 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */
889 ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
890 : (s32)read_c0_ebase();
891 if (ebase & MIPS_EBASE_WG) {
892 /* WG bit already set, we can avoid the clumsy probe */
893 c->options |= MIPS_CPU_EBASE_WG;
894 } else {
895 /* Its UNDEFINED to change EBase while BEV=0 */
896 status = read_c0_status();
897 write_c0_status(status | ST0_BEV);
898 irq_enable_hazard();
899 /*
900 * On pre-r6 cores, this may well clobber the upper bits
901 * of EBase. This is hard to avoid without potentially
902 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit.
903 */
904 if (cpu_has_mips64r6)
905 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
906 else
907 write_c0_ebase(ebase | MIPS_EBASE_WG);
908 back_to_back_c0_hazard();
909 /* Restore BEV */
910 write_c0_status(status);
911 if (read_c0_ebase() & MIPS_EBASE_WG) {
912 c->options |= MIPS_CPU_EBASE_WG;
913 write_c0_ebase(ebase);
914 }
915 }
916 }
917
918 /* configure the FTLB write probability */
919 set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB);
920
921 mips_probe_watch_registers(c);
922
923#ifndef CONFIG_MIPS_CPS
924 if (cpu_has_mips_r2_r6) {
925 unsigned int core;
926
927 core = get_ebase_cpunum();
928 if (cpu_has_mipsmt)
929 core >>= fls(core_nvpes()) - 1;
930 cpu_set_core(c, core);
931 }
932#endif
933}
934
935/*
936 * Probe for certain guest capabilities by writing config bits and reading back.
937 * Finally write back the original value.
938 */
939#define probe_gc0_config(name, maxconf, bits) \
940do { \
941 unsigned int tmp; \
942 tmp = read_gc0_##name(); \
943 write_gc0_##name(tmp | (bits)); \
944 back_to_back_c0_hazard(); \
945 maxconf = read_gc0_##name(); \
946 write_gc0_##name(tmp); \
947} while (0)
948
949/*
950 * Probe for dynamic guest capabilities by changing certain config bits and
951 * reading back to see if they change. Finally write back the original value.
952 */
953#define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \
954do { \
955 maxconf = read_gc0_##name(); \
956 write_gc0_##name(maxconf ^ (bits)); \
957 back_to_back_c0_hazard(); \
958 dynconf = maxconf ^ read_gc0_##name(); \
959 write_gc0_##name(maxconf); \
960 maxconf |= dynconf; \
961} while (0)
962
963static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c)
964{
965 unsigned int config0;
966
967 probe_gc0_config(config, config0, MIPS_CONF_M);
968
969 if (config0 & MIPS_CONF_M)
970 c->guest.conf |= BIT(1);
971 return config0 & MIPS_CONF_M;
972}
973
974static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c)
975{
976 unsigned int config1, config1_dyn;
977
978 probe_gc0_config_dyn(config1, config1, config1_dyn,
979 MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR |
980 MIPS_CONF1_FP);
981
982 if (config1 & MIPS_CONF1_FP)
983 c->guest.options |= MIPS_CPU_FPU;
984 if (config1_dyn & MIPS_CONF1_FP)
985 c->guest.options_dyn |= MIPS_CPU_FPU;
986
987 if (config1 & MIPS_CONF1_WR)
988 c->guest.options |= MIPS_CPU_WATCH;
989 if (config1_dyn & MIPS_CONF1_WR)
990 c->guest.options_dyn |= MIPS_CPU_WATCH;
991
992 if (config1 & MIPS_CONF1_PC)
993 c->guest.options |= MIPS_CPU_PERF;
994 if (config1_dyn & MIPS_CONF1_PC)
995 c->guest.options_dyn |= MIPS_CPU_PERF;
996
997 if (config1 & MIPS_CONF_M)
998 c->guest.conf |= BIT(2);
999 return config1 & MIPS_CONF_M;
1000}
1001
1002static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c)
1003{
1004 unsigned int config2;
1005
1006 probe_gc0_config(config2, config2, MIPS_CONF_M);
1007
1008 if (config2 & MIPS_CONF_M)
1009 c->guest.conf |= BIT(3);
1010 return config2 & MIPS_CONF_M;
1011}
1012
1013static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c)
1014{
1015 unsigned int config3, config3_dyn;
1016
1017 probe_gc0_config_dyn(config3, config3, config3_dyn,
1018 MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI |
1019 MIPS_CONF3_CTXTC);
1020
1021 if (config3 & MIPS_CONF3_CTXTC)
1022 c->guest.options |= MIPS_CPU_CTXTC;
1023 if (config3_dyn & MIPS_CONF3_CTXTC)
1024 c->guest.options_dyn |= MIPS_CPU_CTXTC;
1025
1026 if (config3 & MIPS_CONF3_PW)
1027 c->guest.options |= MIPS_CPU_HTW;
1028
1029 if (config3 & MIPS_CONF3_ULRI)
1030 c->guest.options |= MIPS_CPU_ULRI;
1031
1032 if (config3 & MIPS_CONF3_SC)
1033 c->guest.options |= MIPS_CPU_SEGMENTS;
1034
1035 if (config3 & MIPS_CONF3_BI)
1036 c->guest.options |= MIPS_CPU_BADINSTR;
1037 if (config3 & MIPS_CONF3_BP)
1038 c->guest.options |= MIPS_CPU_BADINSTRP;
1039
1040 if (config3 & MIPS_CONF3_MSA)
1041 c->guest.ases |= MIPS_ASE_MSA;
1042 if (config3_dyn & MIPS_CONF3_MSA)
1043 c->guest.ases_dyn |= MIPS_ASE_MSA;
1044
1045 if (config3 & MIPS_CONF_M)
1046 c->guest.conf |= BIT(4);
1047 return config3 & MIPS_CONF_M;
1048}
1049
1050static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c)
1051{
1052 unsigned int config4;
1053
1054 probe_gc0_config(config4, config4,
1055 MIPS_CONF_M | MIPS_CONF4_KSCREXIST);
1056
1057 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
1058 >> MIPS_CONF4_KSCREXIST_SHIFT;
1059
1060 if (config4 & MIPS_CONF_M)
1061 c->guest.conf |= BIT(5);
1062 return config4 & MIPS_CONF_M;
1063}
1064
1065static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c)
1066{
1067 unsigned int config5, config5_dyn;
1068
1069 probe_gc0_config_dyn(config5, config5, config5_dyn,
1070 MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP);
1071
1072 if (config5 & MIPS_CONF5_MRP)
1073 c->guest.options |= MIPS_CPU_MAAR;
1074 if (config5_dyn & MIPS_CONF5_MRP)
1075 c->guest.options_dyn |= MIPS_CPU_MAAR;
1076
1077 if (config5 & MIPS_CONF5_LLB)
1078 c->guest.options |= MIPS_CPU_RW_LLB;
1079
1080 if (config5 & MIPS_CONF5_MVH)
1081 c->guest.options |= MIPS_CPU_MVH;
1082
1083 if (config5 & MIPS_CONF_M)
1084 c->guest.conf |= BIT(6);
1085 return config5 & MIPS_CONF_M;
1086}
1087
1088static inline void decode_guest_configs(struct cpuinfo_mips *c)
1089{
1090 unsigned int ok;
1091
1092 ok = decode_guest_config0(c);
1093 if (ok)
1094 ok = decode_guest_config1(c);
1095 if (ok)
1096 ok = decode_guest_config2(c);
1097 if (ok)
1098 ok = decode_guest_config3(c);
1099 if (ok)
1100 ok = decode_guest_config4(c);
1101 if (ok)
1102 decode_guest_config5(c);
1103}
1104
1105static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c)
1106{
1107 unsigned int guestctl0, temp;
1108
1109 guestctl0 = read_c0_guestctl0();
1110
1111 if (guestctl0 & MIPS_GCTL0_G0E)
1112 c->options |= MIPS_CPU_GUESTCTL0EXT;
1113 if (guestctl0 & MIPS_GCTL0_G1)
1114 c->options |= MIPS_CPU_GUESTCTL1;
1115 if (guestctl0 & MIPS_GCTL0_G2)
1116 c->options |= MIPS_CPU_GUESTCTL2;
1117 if (!(guestctl0 & MIPS_GCTL0_RAD)) {
1118 c->options |= MIPS_CPU_GUESTID;
1119
1120 /*
1121 * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0
1122 * first, otherwise all data accesses will be fully virtualised
1123 * as if they were performed by guest mode.
1124 */
1125 write_c0_guestctl1(0);
1126 tlbw_use_hazard();
1127
1128 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG);
1129 back_to_back_c0_hazard();
1130 temp = read_c0_guestctl0();
1131
1132 if (temp & MIPS_GCTL0_DRG) {
1133 write_c0_guestctl0(guestctl0);
1134 c->options |= MIPS_CPU_DRG;
1135 }
1136 }
1137}
1138
1139static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c)
1140{
1141 if (cpu_has_guestid) {
1142 /* determine the number of bits of GuestID available */
1143 write_c0_guestctl1(MIPS_GCTL1_ID);
1144 back_to_back_c0_hazard();
1145 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID)
1146 >> MIPS_GCTL1_ID_SHIFT;
1147 write_c0_guestctl1(0);
1148 }
1149}
1150
1151static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c)
1152{
1153 /* determine the number of bits of GTOffset available */
1154 write_c0_gtoffset(0xffffffff);
1155 back_to_back_c0_hazard();
1156 c->gtoffset_mask = read_c0_gtoffset();
1157 write_c0_gtoffset(0);
1158}
1159
1160static inline void cpu_probe_vz(struct cpuinfo_mips *c)
1161{
1162 cpu_probe_guestctl0(c);
1163 if (cpu_has_guestctl1)
1164 cpu_probe_guestctl1(c);
1165
1166 cpu_probe_gtoffset(c);
1167
1168 decode_guest_configs(c);
1169}
1170
1171#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1172 | MIPS_CPU_COUNTER)
1173
1174static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1175{
1176 switch (c->processor_id & PRID_IMP_MASK) {
1177 case PRID_IMP_R2000:
1178 c->cputype = CPU_R2000;
1179 __cpu_name[cpu] = "R2000";
1180 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1181 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1182 MIPS_CPU_NOFPUEX;
1183 if (__cpu_has_fpu())
1184 c->options |= MIPS_CPU_FPU;
1185 c->tlbsize = 64;
1186 break;
1187 case PRID_IMP_R3000:
1188 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
1189 if (cpu_has_confreg()) {
1190 c->cputype = CPU_R3081E;
1191 __cpu_name[cpu] = "R3081";
1192 } else {
1193 c->cputype = CPU_R3000A;
1194 __cpu_name[cpu] = "R3000A";
1195 }
1196 } else {
1197 c->cputype = CPU_R3000;
1198 __cpu_name[cpu] = "R3000";
1199 }
1200 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1201 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1202 MIPS_CPU_NOFPUEX;
1203 if (__cpu_has_fpu())
1204 c->options |= MIPS_CPU_FPU;
1205 c->tlbsize = 64;
1206 break;
1207 case PRID_IMP_R4000:
1208 if (read_c0_config() & CONF_SC) {
1209 if ((c->processor_id & PRID_REV_MASK) >=
1210 PRID_REV_R4400) {
1211 c->cputype = CPU_R4400PC;
1212 __cpu_name[cpu] = "R4400PC";
1213 } else {
1214 c->cputype = CPU_R4000PC;
1215 __cpu_name[cpu] = "R4000PC";
1216 }
1217 } else {
1218 int cca = read_c0_config() & CONF_CM_CMASK;
1219 int mc;
1220
1221 /*
1222 * SC and MC versions can't be reliably told apart,
1223 * but only the latter support coherent caching
1224 * modes so assume the firmware has set the KSEG0
1225 * coherency attribute reasonably (if uncached, we
1226 * assume SC).
1227 */
1228 switch (cca) {
1229 case CONF_CM_CACHABLE_CE:
1230 case CONF_CM_CACHABLE_COW:
1231 case CONF_CM_CACHABLE_CUW:
1232 mc = 1;
1233 break;
1234 default:
1235 mc = 0;
1236 break;
1237 }
1238 if ((c->processor_id & PRID_REV_MASK) >=
1239 PRID_REV_R4400) {
1240 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
1241 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
1242 } else {
1243 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
1244 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
1245 }
1246 }
1247
1248 set_isa(c, MIPS_CPU_ISA_III);
1249 c->fpu_msk31 |= FPU_CSR_CONDX;
1250 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1251 MIPS_CPU_WATCH | MIPS_CPU_VCE |
1252 MIPS_CPU_LLSC;
1253 c->tlbsize = 48;
1254 break;
1255 case PRID_IMP_VR41XX:
1256 set_isa(c, MIPS_CPU_ISA_III);
1257 c->fpu_msk31 |= FPU_CSR_CONDX;
1258 c->options = R4K_OPTS;
1259 c->tlbsize = 32;
1260 switch (c->processor_id & 0xf0) {
1261 case PRID_REV_VR4111:
1262 c->cputype = CPU_VR4111;
1263 __cpu_name[cpu] = "NEC VR4111";
1264 break;
1265 case PRID_REV_VR4121:
1266 c->cputype = CPU_VR4121;
1267 __cpu_name[cpu] = "NEC VR4121";
1268 break;
1269 case PRID_REV_VR4122:
1270 if ((c->processor_id & 0xf) < 0x3) {
1271 c->cputype = CPU_VR4122;
1272 __cpu_name[cpu] = "NEC VR4122";
1273 } else {
1274 c->cputype = CPU_VR4181A;
1275 __cpu_name[cpu] = "NEC VR4181A";
1276 }
1277 break;
1278 case PRID_REV_VR4130:
1279 if ((c->processor_id & 0xf) < 0x4) {
1280 c->cputype = CPU_VR4131;
1281 __cpu_name[cpu] = "NEC VR4131";
1282 } else {
1283 c->cputype = CPU_VR4133;
1284 c->options |= MIPS_CPU_LLSC;
1285 __cpu_name[cpu] = "NEC VR4133";
1286 }
1287 break;
1288 default:
1289 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
1290 c->cputype = CPU_VR41XX;
1291 __cpu_name[cpu] = "NEC Vr41xx";
1292 break;
1293 }
1294 break;
1295 case PRID_IMP_R4300:
1296 c->cputype = CPU_R4300;
1297 __cpu_name[cpu] = "R4300";
1298 set_isa(c, MIPS_CPU_ISA_III);
1299 c->fpu_msk31 |= FPU_CSR_CONDX;
1300 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1301 MIPS_CPU_LLSC;
1302 c->tlbsize = 32;
1303 break;
1304 case PRID_IMP_R4600:
1305 c->cputype = CPU_R4600;
1306 __cpu_name[cpu] = "R4600";
1307 set_isa(c, MIPS_CPU_ISA_III);
1308 c->fpu_msk31 |= FPU_CSR_CONDX;
1309 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1310 MIPS_CPU_LLSC;
1311 c->tlbsize = 48;
1312 break;
1313 #if 0
1314 case PRID_IMP_R4650:
1315 /*
1316 * This processor doesn't have an MMU, so it's not
1317 * "real easy" to run Linux on it. It is left purely
1318 * for documentation. Commented out because it shares
1319 * it's c0_prid id number with the TX3900.
1320 */
1321 c->cputype = CPU_R4650;
1322 __cpu_name[cpu] = "R4650";
1323 set_isa(c, MIPS_CPU_ISA_III);
1324 c->fpu_msk31 |= FPU_CSR_CONDX;
1325 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
1326 c->tlbsize = 48;
1327 break;
1328 #endif
1329 case PRID_IMP_TX39:
1330 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1331 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1332
1333 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1334 c->cputype = CPU_TX3927;
1335 __cpu_name[cpu] = "TX3927";
1336 c->tlbsize = 64;
1337 } else {
1338 switch (c->processor_id & PRID_REV_MASK) {
1339 case PRID_REV_TX3912:
1340 c->cputype = CPU_TX3912;
1341 __cpu_name[cpu] = "TX3912";
1342 c->tlbsize = 32;
1343 break;
1344 case PRID_REV_TX3922:
1345 c->cputype = CPU_TX3922;
1346 __cpu_name[cpu] = "TX3922";
1347 c->tlbsize = 64;
1348 break;
1349 }
1350 }
1351 break;
1352 case PRID_IMP_R4700:
1353 c->cputype = CPU_R4700;
1354 __cpu_name[cpu] = "R4700";
1355 set_isa(c, MIPS_CPU_ISA_III);
1356 c->fpu_msk31 |= FPU_CSR_CONDX;
1357 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1358 MIPS_CPU_LLSC;
1359 c->tlbsize = 48;
1360 break;
1361 case PRID_IMP_TX49:
1362 c->cputype = CPU_TX49XX;
1363 __cpu_name[cpu] = "R49XX";
1364 set_isa(c, MIPS_CPU_ISA_III);
1365 c->fpu_msk31 |= FPU_CSR_CONDX;
1366 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1367 if (!(c->processor_id & 0x08))
1368 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1369 c->tlbsize = 48;
1370 break;
1371 case PRID_IMP_R5000:
1372 c->cputype = CPU_R5000;
1373 __cpu_name[cpu] = "R5000";
1374 set_isa(c, MIPS_CPU_ISA_IV);
1375 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1376 MIPS_CPU_LLSC;
1377 c->tlbsize = 48;
1378 break;
1379 case PRID_IMP_R5432:
1380 c->cputype = CPU_R5432;
1381 __cpu_name[cpu] = "R5432";
1382 set_isa(c, MIPS_CPU_ISA_IV);
1383 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1384 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1385 c->tlbsize = 48;
1386 break;
1387 case PRID_IMP_R5500:
1388 c->cputype = CPU_R5500;
1389 __cpu_name[cpu] = "R5500";
1390 set_isa(c, MIPS_CPU_ISA_IV);
1391 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1392 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1393 c->tlbsize = 48;
1394 break;
1395 case PRID_IMP_NEVADA:
1396 c->cputype = CPU_NEVADA;
1397 __cpu_name[cpu] = "Nevada";
1398 set_isa(c, MIPS_CPU_ISA_IV);
1399 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1400 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1401 c->tlbsize = 48;
1402 break;
1403 case PRID_IMP_RM7000:
1404 c->cputype = CPU_RM7000;
1405 __cpu_name[cpu] = "RM7000";
1406 set_isa(c, MIPS_CPU_ISA_IV);
1407 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1408 MIPS_CPU_LLSC;
1409 /*
1410 * Undocumented RM7000: Bit 29 in the info register of
1411 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1412 * entries.
1413 *
1414 * 29 1 => 64 entry JTLB
1415 * 0 => 48 entry JTLB
1416 */
1417 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1418 break;
1419 case PRID_IMP_R8000:
1420 c->cputype = CPU_R8000;
1421 __cpu_name[cpu] = "RM8000";
1422 set_isa(c, MIPS_CPU_ISA_IV);
1423 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
1424 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1425 MIPS_CPU_LLSC;
1426 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
1427 break;
1428 case PRID_IMP_R10000:
1429 c->cputype = CPU_R10000;
1430 __cpu_name[cpu] = "R10000";
1431 set_isa(c, MIPS_CPU_ISA_IV);
1432 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1433 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1434 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1435 MIPS_CPU_LLSC;
1436 c->tlbsize = 64;
1437 break;
1438 case PRID_IMP_R12000:
1439 c->cputype = CPU_R12000;
1440 __cpu_name[cpu] = "R12000";
1441 set_isa(c, MIPS_CPU_ISA_IV);
1442 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1443 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1444 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1445 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1446 c->tlbsize = 64;
1447 break;
1448 case PRID_IMP_R14000:
1449 if (((c->processor_id >> 4) & 0x0f) > 2) {
1450 c->cputype = CPU_R16000;
1451 __cpu_name[cpu] = "R16000";
1452 } else {
1453 c->cputype = CPU_R14000;
1454 __cpu_name[cpu] = "R14000";
1455 }
1456 set_isa(c, MIPS_CPU_ISA_IV);
1457 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1458 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1459 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1460 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1461 c->tlbsize = 64;
1462 break;
1463 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1464 switch (c->processor_id & PRID_REV_MASK) {
1465 case PRID_REV_LOONGSON2E:
1466 c->cputype = CPU_LOONGSON2;
1467 __cpu_name[cpu] = "ICT Loongson-2";
1468 set_elf_platform(cpu, "loongson2e");
1469 set_isa(c, MIPS_CPU_ISA_III);
1470 c->fpu_msk31 |= FPU_CSR_CONDX;
1471 break;
1472 case PRID_REV_LOONGSON2F:
1473 c->cputype = CPU_LOONGSON2;
1474 __cpu_name[cpu] = "ICT Loongson-2";
1475 set_elf_platform(cpu, "loongson2f");
1476 set_isa(c, MIPS_CPU_ISA_III);
1477 c->fpu_msk31 |= FPU_CSR_CONDX;
1478 break;
1479 case PRID_REV_LOONGSON3A_R1:
1480 c->cputype = CPU_LOONGSON3;
1481 __cpu_name[cpu] = "ICT Loongson-3";
1482 set_elf_platform(cpu, "loongson3a");
1483 set_isa(c, MIPS_CPU_ISA_M64R1);
1484 break;
1485 case PRID_REV_LOONGSON3B_R1:
1486 case PRID_REV_LOONGSON3B_R2:
1487 c->cputype = CPU_LOONGSON3;
1488 __cpu_name[cpu] = "ICT Loongson-3";
1489 set_elf_platform(cpu, "loongson3b");
1490 set_isa(c, MIPS_CPU_ISA_M64R1);
1491 break;
1492 }
1493
1494 c->options = R4K_OPTS |
1495 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1496 MIPS_CPU_32FPR;
1497 c->tlbsize = 64;
1498 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1499 break;
1500 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
1501 decode_configs(c);
1502
1503 c->cputype = CPU_LOONGSON1;
1504
1505 switch (c->processor_id & PRID_REV_MASK) {
1506 case PRID_REV_LOONGSON1B:
1507 __cpu_name[cpu] = "Loongson 1B";
1508 break;
1509 }
1510
1511 break;
1512 }
1513}
1514
1515static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1516{
1517 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1518 switch (c->processor_id & PRID_IMP_MASK) {
1519 case PRID_IMP_QEMU_GENERIC:
1520 c->writecombine = _CACHE_UNCACHED;
1521 c->cputype = CPU_QEMU_GENERIC;
1522 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1523 break;
1524 case PRID_IMP_4KC:
1525 c->cputype = CPU_4KC;
1526 c->writecombine = _CACHE_UNCACHED;
1527 __cpu_name[cpu] = "MIPS 4Kc";
1528 break;
1529 case PRID_IMP_4KEC:
1530 case PRID_IMP_4KECR2:
1531 c->cputype = CPU_4KEC;
1532 c->writecombine = _CACHE_UNCACHED;
1533 __cpu_name[cpu] = "MIPS 4KEc";
1534 break;
1535 case PRID_IMP_4KSC:
1536 case PRID_IMP_4KSD:
1537 c->cputype = CPU_4KSC;
1538 c->writecombine = _CACHE_UNCACHED;
1539 __cpu_name[cpu] = "MIPS 4KSc";
1540 break;
1541 case PRID_IMP_5KC:
1542 c->cputype = CPU_5KC;
1543 c->writecombine = _CACHE_UNCACHED;
1544 __cpu_name[cpu] = "MIPS 5Kc";
1545 break;
1546 case PRID_IMP_5KE:
1547 c->cputype = CPU_5KE;
1548 c->writecombine = _CACHE_UNCACHED;
1549 __cpu_name[cpu] = "MIPS 5KE";
1550 break;
1551 case PRID_IMP_20KC:
1552 c->cputype = CPU_20KC;
1553 c->writecombine = _CACHE_UNCACHED;
1554 __cpu_name[cpu] = "MIPS 20Kc";
1555 break;
1556 case PRID_IMP_24K:
1557 c->cputype = CPU_24K;
1558 c->writecombine = _CACHE_UNCACHED;
1559 __cpu_name[cpu] = "MIPS 24Kc";
1560 break;
1561 case PRID_IMP_24KE:
1562 c->cputype = CPU_24K;
1563 c->writecombine = _CACHE_UNCACHED;
1564 __cpu_name[cpu] = "MIPS 24KEc";
1565 break;
1566 case PRID_IMP_25KF:
1567 c->cputype = CPU_25KF;
1568 c->writecombine = _CACHE_UNCACHED;
1569 __cpu_name[cpu] = "MIPS 25Kc";
1570 break;
1571 case PRID_IMP_34K:
1572 c->cputype = CPU_34K;
1573 c->writecombine = _CACHE_UNCACHED;
1574 __cpu_name[cpu] = "MIPS 34Kc";
1575 break;
1576 case PRID_IMP_74K:
1577 c->cputype = CPU_74K;
1578 c->writecombine = _CACHE_UNCACHED;
1579 __cpu_name[cpu] = "MIPS 74Kc";
1580 break;
1581 case PRID_IMP_M14KC:
1582 c->cputype = CPU_M14KC;
1583 c->writecombine = _CACHE_UNCACHED;
1584 __cpu_name[cpu] = "MIPS M14Kc";
1585 break;
1586 case PRID_IMP_M14KEC:
1587 c->cputype = CPU_M14KEC;
1588 c->writecombine = _CACHE_UNCACHED;
1589 __cpu_name[cpu] = "MIPS M14KEc";
1590 break;
1591 case PRID_IMP_1004K:
1592 c->cputype = CPU_1004K;
1593 c->writecombine = _CACHE_UNCACHED;
1594 __cpu_name[cpu] = "MIPS 1004Kc";
1595 break;
1596 case PRID_IMP_1074K:
1597 c->cputype = CPU_1074K;
1598 c->writecombine = _CACHE_UNCACHED;
1599 __cpu_name[cpu] = "MIPS 1074Kc";
1600 break;
1601 case PRID_IMP_INTERAPTIV_UP:
1602 c->cputype = CPU_INTERAPTIV;
1603 __cpu_name[cpu] = "MIPS interAptiv";
1604 break;
1605 case PRID_IMP_INTERAPTIV_MP:
1606 c->cputype = CPU_INTERAPTIV;
1607 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1608 break;
1609 case PRID_IMP_PROAPTIV_UP:
1610 c->cputype = CPU_PROAPTIV;
1611 __cpu_name[cpu] = "MIPS proAptiv";
1612 break;
1613 case PRID_IMP_PROAPTIV_MP:
1614 c->cputype = CPU_PROAPTIV;
1615 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1616 break;
1617 case PRID_IMP_P5600:
1618 c->cputype = CPU_P5600;
1619 __cpu_name[cpu] = "MIPS P5600";
1620 break;
1621 case PRID_IMP_P6600:
1622 c->cputype = CPU_P6600;
1623 __cpu_name[cpu] = "MIPS P6600";
1624 break;
1625 case PRID_IMP_I6400:
1626 c->cputype = CPU_I6400;
1627 __cpu_name[cpu] = "MIPS I6400";
1628 break;
1629 case PRID_IMP_I6500:
1630 c->cputype = CPU_I6500;
1631 __cpu_name[cpu] = "MIPS I6500";
1632 break;
1633 case PRID_IMP_M5150:
1634 c->cputype = CPU_M5150;
1635 __cpu_name[cpu] = "MIPS M5150";
1636 break;
1637 case PRID_IMP_M6250:
1638 c->cputype = CPU_M6250;
1639 __cpu_name[cpu] = "MIPS M6250";
1640 break;
1641 }
1642
1643 decode_configs(c);
1644
1645 spram_config();
1646
1647 switch (__get_cpu_type(c->cputype)) {
1648 case CPU_I6500:
1649 c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES;
1650 /* fall-through */
1651 case CPU_I6400:
1652 c->options |= MIPS_CPU_SHARED_FTLB_RAM;
1653 /* fall-through */
1654 default:
1655 break;
1656 }
1657}
1658
1659static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1660{
1661 decode_configs(c);
1662 switch (c->processor_id & PRID_IMP_MASK) {
1663 case PRID_IMP_AU1_REV1:
1664 case PRID_IMP_AU1_REV2:
1665 c->cputype = CPU_ALCHEMY;
1666 switch ((c->processor_id >> 24) & 0xff) {
1667 case 0:
1668 __cpu_name[cpu] = "Au1000";
1669 break;
1670 case 1:
1671 __cpu_name[cpu] = "Au1500";
1672 break;
1673 case 2:
1674 __cpu_name[cpu] = "Au1100";
1675 break;
1676 case 3:
1677 __cpu_name[cpu] = "Au1550";
1678 break;
1679 case 4:
1680 __cpu_name[cpu] = "Au1200";
1681 if ((c->processor_id & PRID_REV_MASK) == 2)
1682 __cpu_name[cpu] = "Au1250";
1683 break;
1684 case 5:
1685 __cpu_name[cpu] = "Au1210";
1686 break;
1687 default:
1688 __cpu_name[cpu] = "Au1xxx";
1689 break;
1690 }
1691 break;
1692 }
1693}
1694
1695static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1696{
1697 decode_configs(c);
1698
1699 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1700 switch (c->processor_id & PRID_IMP_MASK) {
1701 case PRID_IMP_SB1:
1702 c->cputype = CPU_SB1;
1703 __cpu_name[cpu] = "SiByte SB1";
1704 /* FPU in pass1 is known to have issues. */
1705 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1706 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1707 break;
1708 case PRID_IMP_SB1A:
1709 c->cputype = CPU_SB1A;
1710 __cpu_name[cpu] = "SiByte SB1A";
1711 break;
1712 }
1713}
1714
1715static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1716{
1717 decode_configs(c);
1718 switch (c->processor_id & PRID_IMP_MASK) {
1719 case PRID_IMP_SR71000:
1720 c->cputype = CPU_SR71000;
1721 __cpu_name[cpu] = "Sandcraft SR71000";
1722 c->scache.ways = 8;
1723 c->tlbsize = 64;
1724 break;
1725 }
1726}
1727
1728static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1729{
1730 decode_configs(c);
1731 switch (c->processor_id & PRID_IMP_MASK) {
1732 case PRID_IMP_PR4450:
1733 c->cputype = CPU_PR4450;
1734 __cpu_name[cpu] = "Philips PR4450";
1735 set_isa(c, MIPS_CPU_ISA_M32R1);
1736 break;
1737 }
1738}
1739
1740static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1741{
1742 decode_configs(c);
1743 switch (c->processor_id & PRID_IMP_MASK) {
1744 case PRID_IMP_BMIPS32_REV4:
1745 case PRID_IMP_BMIPS32_REV8:
1746 c->cputype = CPU_BMIPS32;
1747 __cpu_name[cpu] = "Broadcom BMIPS32";
1748 set_elf_platform(cpu, "bmips32");
1749 break;
1750 case PRID_IMP_BMIPS3300:
1751 case PRID_IMP_BMIPS3300_ALT:
1752 case PRID_IMP_BMIPS3300_BUG:
1753 c->cputype = CPU_BMIPS3300;
1754 __cpu_name[cpu] = "Broadcom BMIPS3300";
1755 set_elf_platform(cpu, "bmips3300");
1756 break;
1757 case PRID_IMP_BMIPS43XX: {
1758 int rev = c->processor_id & PRID_REV_MASK;
1759
1760 if (rev >= PRID_REV_BMIPS4380_LO &&
1761 rev <= PRID_REV_BMIPS4380_HI) {
1762 c->cputype = CPU_BMIPS4380;
1763 __cpu_name[cpu] = "Broadcom BMIPS4380";
1764 set_elf_platform(cpu, "bmips4380");
1765 c->options |= MIPS_CPU_RIXI;
1766 } else {
1767 c->cputype = CPU_BMIPS4350;
1768 __cpu_name[cpu] = "Broadcom BMIPS4350";
1769 set_elf_platform(cpu, "bmips4350");
1770 }
1771 break;
1772 }
1773 case PRID_IMP_BMIPS5000:
1774 case PRID_IMP_BMIPS5200:
1775 c->cputype = CPU_BMIPS5000;
1776 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1777 __cpu_name[cpu] = "Broadcom BMIPS5200";
1778 else
1779 __cpu_name[cpu] = "Broadcom BMIPS5000";
1780 set_elf_platform(cpu, "bmips5000");
1781 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
1782 break;
1783 }
1784}
1785
1786static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1787{
1788 decode_configs(c);
1789 switch (c->processor_id & PRID_IMP_MASK) {
1790 case PRID_IMP_CAVIUM_CN38XX:
1791 case PRID_IMP_CAVIUM_CN31XX:
1792 case PRID_IMP_CAVIUM_CN30XX:
1793 c->cputype = CPU_CAVIUM_OCTEON;
1794 __cpu_name[cpu] = "Cavium Octeon";
1795 goto platform;
1796 case PRID_IMP_CAVIUM_CN58XX:
1797 case PRID_IMP_CAVIUM_CN56XX:
1798 case PRID_IMP_CAVIUM_CN50XX:
1799 case PRID_IMP_CAVIUM_CN52XX:
1800 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1801 __cpu_name[cpu] = "Cavium Octeon+";
1802platform:
1803 set_elf_platform(cpu, "octeon");
1804 break;
1805 case PRID_IMP_CAVIUM_CN61XX:
1806 case PRID_IMP_CAVIUM_CN63XX:
1807 case PRID_IMP_CAVIUM_CN66XX:
1808 case PRID_IMP_CAVIUM_CN68XX:
1809 case PRID_IMP_CAVIUM_CNF71XX:
1810 c->cputype = CPU_CAVIUM_OCTEON2;
1811 __cpu_name[cpu] = "Cavium Octeon II";
1812 set_elf_platform(cpu, "octeon2");
1813 break;
1814 case PRID_IMP_CAVIUM_CN70XX:
1815 case PRID_IMP_CAVIUM_CN73XX:
1816 case PRID_IMP_CAVIUM_CNF75XX:
1817 case PRID_IMP_CAVIUM_CN78XX:
1818 c->cputype = CPU_CAVIUM_OCTEON3;
1819 __cpu_name[cpu] = "Cavium Octeon III";
1820 set_elf_platform(cpu, "octeon3");
1821 break;
1822 default:
1823 printk(KERN_INFO "Unknown Octeon chip!\n");
1824 c->cputype = CPU_UNKNOWN;
1825 break;
1826 }
1827}
1828
1829static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
1830{
1831 switch (c->processor_id & PRID_IMP_MASK) {
1832 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1833 switch (c->processor_id & PRID_REV_MASK) {
1834 case PRID_REV_LOONGSON3A_R2:
1835 c->cputype = CPU_LOONGSON3;
1836 __cpu_name[cpu] = "ICT Loongson-3";
1837 set_elf_platform(cpu, "loongson3a");
1838 set_isa(c, MIPS_CPU_ISA_M64R2);
1839 break;
1840 case PRID_REV_LOONGSON3A_R3:
1841 c->cputype = CPU_LOONGSON3;
1842 __cpu_name[cpu] = "ICT Loongson-3";
1843 set_elf_platform(cpu, "loongson3a");
1844 set_isa(c, MIPS_CPU_ISA_M64R2);
1845 break;
1846 }
1847
1848 decode_configs(c);
1849 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
1850 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1851 break;
1852 default:
1853 panic("Unknown Loongson Processor ID!");
1854 break;
1855 }
1856}
1857
1858static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1859{
1860 decode_configs(c);
1861 /* JZRISC does not implement the CP0 counter. */
1862 c->options &= ~MIPS_CPU_COUNTER;
1863 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1864 switch (c->processor_id & PRID_IMP_MASK) {
1865 case PRID_IMP_JZRISC:
1866 c->cputype = CPU_JZRISC;
1867 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1868 __cpu_name[cpu] = "Ingenic JZRISC";
1869 break;
1870 default:
1871 panic("Unknown Ingenic Processor ID!");
1872 break;
1873 }
1874}
1875
1876static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1877{
1878 decode_configs(c);
1879
1880 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1881 c->cputype = CPU_ALCHEMY;
1882 __cpu_name[cpu] = "Au1300";
1883 /* following stuff is not for Alchemy */
1884 return;
1885 }
1886
1887 c->options = (MIPS_CPU_TLB |
1888 MIPS_CPU_4KEX |
1889 MIPS_CPU_COUNTER |
1890 MIPS_CPU_DIVEC |
1891 MIPS_CPU_WATCH |
1892 MIPS_CPU_EJTAG |
1893 MIPS_CPU_LLSC);
1894
1895 switch (c->processor_id & PRID_IMP_MASK) {
1896 case PRID_IMP_NETLOGIC_XLP2XX:
1897 case PRID_IMP_NETLOGIC_XLP9XX:
1898 case PRID_IMP_NETLOGIC_XLP5XX:
1899 c->cputype = CPU_XLP;
1900 __cpu_name[cpu] = "Broadcom XLPII";
1901 break;
1902
1903 case PRID_IMP_NETLOGIC_XLP8XX:
1904 case PRID_IMP_NETLOGIC_XLP3XX:
1905 c->cputype = CPU_XLP;
1906 __cpu_name[cpu] = "Netlogic XLP";
1907 break;
1908
1909 case PRID_IMP_NETLOGIC_XLR732:
1910 case PRID_IMP_NETLOGIC_XLR716:
1911 case PRID_IMP_NETLOGIC_XLR532:
1912 case PRID_IMP_NETLOGIC_XLR308:
1913 case PRID_IMP_NETLOGIC_XLR532C:
1914 case PRID_IMP_NETLOGIC_XLR516C:
1915 case PRID_IMP_NETLOGIC_XLR508C:
1916 case PRID_IMP_NETLOGIC_XLR308C:
1917 c->cputype = CPU_XLR;
1918 __cpu_name[cpu] = "Netlogic XLR";
1919 break;
1920
1921 case PRID_IMP_NETLOGIC_XLS608:
1922 case PRID_IMP_NETLOGIC_XLS408:
1923 case PRID_IMP_NETLOGIC_XLS404:
1924 case PRID_IMP_NETLOGIC_XLS208:
1925 case PRID_IMP_NETLOGIC_XLS204:
1926 case PRID_IMP_NETLOGIC_XLS108:
1927 case PRID_IMP_NETLOGIC_XLS104:
1928 case PRID_IMP_NETLOGIC_XLS616B:
1929 case PRID_IMP_NETLOGIC_XLS608B:
1930 case PRID_IMP_NETLOGIC_XLS416B:
1931 case PRID_IMP_NETLOGIC_XLS412B:
1932 case PRID_IMP_NETLOGIC_XLS408B:
1933 case PRID_IMP_NETLOGIC_XLS404B:
1934 c->cputype = CPU_XLR;
1935 __cpu_name[cpu] = "Netlogic XLS";
1936 break;
1937
1938 default:
1939 pr_info("Unknown Netlogic chip id [%02x]!\n",
1940 c->processor_id);
1941 c->cputype = CPU_XLR;
1942 break;
1943 }
1944
1945 if (c->cputype == CPU_XLP) {
1946 set_isa(c, MIPS_CPU_ISA_M64R2);
1947 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1948 /* This will be updated again after all threads are woken up */
1949 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1950 } else {
1951 set_isa(c, MIPS_CPU_ISA_M64R1);
1952 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1953 }
1954 c->kscratch_mask = 0xf;
1955}
1956
1957#ifdef CONFIG_64BIT
1958/* For use by uaccess.h */
1959u64 __ua_limit;
1960EXPORT_SYMBOL(__ua_limit);
1961#endif
1962
1963const char *__cpu_name[NR_CPUS];
1964const char *__elf_platform;
1965
1966void cpu_probe(void)
1967{
1968 struct cpuinfo_mips *c = ¤t_cpu_data;
1969 unsigned int cpu = smp_processor_id();
1970
1971 /*
1972 * Set a default elf platform, cpu probe may later
1973 * overwrite it with a more precise value
1974 */
1975 set_elf_platform(cpu, "mips");
1976
1977 c->processor_id = PRID_IMP_UNKNOWN;
1978 c->fpu_id = FPIR_IMP_NONE;
1979 c->cputype = CPU_UNKNOWN;
1980 c->writecombine = _CACHE_UNCACHED;
1981
1982 c->fpu_csr31 = FPU_CSR_RN;
1983 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1984
1985 c->processor_id = read_c0_prid();
1986 switch (c->processor_id & PRID_COMP_MASK) {
1987 case PRID_COMP_LEGACY:
1988 cpu_probe_legacy(c, cpu);
1989 break;
1990 case PRID_COMP_MIPS:
1991 cpu_probe_mips(c, cpu);
1992 break;
1993 case PRID_COMP_ALCHEMY:
1994 cpu_probe_alchemy(c, cpu);
1995 break;
1996 case PRID_COMP_SIBYTE:
1997 cpu_probe_sibyte(c, cpu);
1998 break;
1999 case PRID_COMP_BROADCOM:
2000 cpu_probe_broadcom(c, cpu);
2001 break;
2002 case PRID_COMP_SANDCRAFT:
2003 cpu_probe_sandcraft(c, cpu);
2004 break;
2005 case PRID_COMP_NXP:
2006 cpu_probe_nxp(c, cpu);
2007 break;
2008 case PRID_COMP_CAVIUM:
2009 cpu_probe_cavium(c, cpu);
2010 break;
2011 case PRID_COMP_LOONGSON:
2012 cpu_probe_loongson(c, cpu);
2013 break;
2014 case PRID_COMP_INGENIC_D0:
2015 case PRID_COMP_INGENIC_D1:
2016 case PRID_COMP_INGENIC_E1:
2017 cpu_probe_ingenic(c, cpu);
2018 break;
2019 case PRID_COMP_NETLOGIC:
2020 cpu_probe_netlogic(c, cpu);
2021 break;
2022 }
2023
2024 BUG_ON(!__cpu_name[cpu]);
2025 BUG_ON(c->cputype == CPU_UNKNOWN);
2026
2027 /*
2028 * Platform code can force the cpu type to optimize code
2029 * generation. In that case be sure the cpu type is correctly
2030 * manually setup otherwise it could trigger some nasty bugs.
2031 */
2032 BUG_ON(current_cpu_type() != c->cputype);
2033
2034 if (cpu_has_rixi) {
2035 /* Enable the RIXI exceptions */
2036 set_c0_pagegrain(PG_IEC);
2037 back_to_back_c0_hazard();
2038 /* Verify the IEC bit is set */
2039 if (read_c0_pagegrain() & PG_IEC)
2040 c->options |= MIPS_CPU_RIXIEX;
2041 }
2042
2043 if (mips_fpu_disabled)
2044 c->options &= ~MIPS_CPU_FPU;
2045
2046 if (mips_dsp_disabled)
2047 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
2048
2049 if (mips_htw_disabled) {
2050 c->options &= ~MIPS_CPU_HTW;
2051 write_c0_pwctl(read_c0_pwctl() &
2052 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
2053 }
2054
2055 if (c->options & MIPS_CPU_FPU)
2056 cpu_set_fpu_opts(c);
2057 else
2058 cpu_set_nofpu_opts(c);
2059
2060 if (cpu_has_bp_ghist)
2061 write_c0_r10k_diag(read_c0_r10k_diag() |
2062 R10K_DIAG_E_GHIST);
2063
2064 if (cpu_has_mips_r2_r6) {
2065 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
2066 /* R2 has Performance Counter Interrupt indicator */
2067 c->options |= MIPS_CPU_PCI;
2068 }
2069 else
2070 c->srsets = 1;
2071
2072 if (cpu_has_mips_r6)
2073 elf_hwcap |= HWCAP_MIPS_R6;
2074
2075 if (cpu_has_msa) {
2076 c->msa_id = cpu_get_msa_id();
2077 WARN(c->msa_id & MSA_IR_WRPF,
2078 "Vector register partitioning unimplemented!");
2079 elf_hwcap |= HWCAP_MIPS_MSA;
2080 }
2081
2082 if (cpu_has_vz)
2083 cpu_probe_vz(c);
2084
2085 cpu_probe_vmbits(c);
2086
2087#ifdef CONFIG_64BIT
2088 if (cpu == 0)
2089 __ua_limit = ~((1ull << cpu_vmbits) - 1);
2090#endif
2091}
2092
2093void cpu_report(void)
2094{
2095 struct cpuinfo_mips *c = ¤t_cpu_data;
2096
2097 pr_info("CPU%d revision is: %08x (%s)\n",
2098 smp_processor_id(), c->processor_id, cpu_name_string());
2099 if (c->options & MIPS_CPU_FPU)
2100 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
2101 if (cpu_has_msa)
2102 pr_info("MSA revision is: %08x\n", c->msa_id);
2103}
2104
2105void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster)
2106{
2107 /* Ensure the core number fits in the field */
2108 WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >>
2109 MIPS_GLOBALNUMBER_CLUSTER_SHF));
2110
2111 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER;
2112 cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF;
2113}
2114
2115void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core)
2116{
2117 /* Ensure the core number fits in the field */
2118 WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF));
2119
2120 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE;
2121 cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF;
2122}
2123
2124void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe)
2125{
2126 /* Ensure the VP(E) ID fits in the field */
2127 WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF));
2128
2129 /* Ensure we're not using VP(E)s without support */
2130 WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) &&
2131 !IS_ENABLED(CONFIG_CPU_MIPSR6));
2132
2133 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP;
2134 cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF;
2135}
1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004 MIPS Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
17#include <linux/smp.h>
18#include <linux/stddef.h>
19#include <linux/module.h>
20
21#include <asm/bugs.h>
22#include <asm/cpu.h>
23#include <asm/fpu.h>
24#include <asm/mipsregs.h>
25#include <asm/system.h>
26#include <asm/watch.h>
27#include <asm/spram.h>
28#include <asm/uaccess.h>
29
30/*
31 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
32 * the implementation of the "wait" feature differs between CPU families. This
33 * points to the function that implements CPU specific wait.
34 * The wait instruction stops the pipeline and reduces the power consumption of
35 * the CPU very much.
36 */
37void (*cpu_wait)(void);
38EXPORT_SYMBOL(cpu_wait);
39
40static void r3081_wait(void)
41{
42 unsigned long cfg = read_c0_conf();
43 write_c0_conf(cfg | R30XX_CONF_HALT);
44}
45
46static void r39xx_wait(void)
47{
48 local_irq_disable();
49 if (!need_resched())
50 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
51 local_irq_enable();
52}
53
54extern void r4k_wait(void);
55
56/*
57 * This variant is preferable as it allows testing need_resched and going to
58 * sleep depending on the outcome atomically. Unfortunately the "It is
59 * implementation-dependent whether the pipeline restarts when a non-enabled
60 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
61 * using this version a gamble.
62 */
63void r4k_wait_irqoff(void)
64{
65 local_irq_disable();
66 if (!need_resched())
67 __asm__(" .set push \n"
68 " .set mips3 \n"
69 " wait \n"
70 " .set pop \n");
71 local_irq_enable();
72 __asm__(" .globl __pastwait \n"
73 "__pastwait: \n");
74}
75
76/*
77 * The RM7000 variant has to handle erratum 38. The workaround is to not
78 * have any pending stores when the WAIT instruction is executed.
79 */
80static void rm7k_wait_irqoff(void)
81{
82 local_irq_disable();
83 if (!need_resched())
84 __asm__(
85 " .set push \n"
86 " .set mips3 \n"
87 " .set noat \n"
88 " mfc0 $1, $12 \n"
89 " sync \n"
90 " mtc0 $1, $12 # stalls until W stage \n"
91 " wait \n"
92 " mtc0 $1, $12 # stalls until W stage \n"
93 " .set pop \n");
94 local_irq_enable();
95}
96
97/*
98 * The Au1xxx wait is available only if using 32khz counter or
99 * external timer source, but specifically not CP0 Counter.
100 * alchemy/common/time.c may override cpu_wait!
101 */
102static void au1k_wait(void)
103{
104 __asm__(" .set mips3 \n"
105 " cache 0x14, 0(%0) \n"
106 " cache 0x14, 32(%0) \n"
107 " sync \n"
108 " nop \n"
109 " wait \n"
110 " nop \n"
111 " nop \n"
112 " nop \n"
113 " nop \n"
114 " .set mips0 \n"
115 : : "r" (au1k_wait));
116}
117
118static int __initdata nowait;
119
120static int __init wait_disable(char *s)
121{
122 nowait = 1;
123
124 return 1;
125}
126
127__setup("nowait", wait_disable);
128
129static int __cpuinitdata mips_fpu_disabled;
130
131static int __init fpu_disable(char *s)
132{
133 cpu_data[0].options &= ~MIPS_CPU_FPU;
134 mips_fpu_disabled = 1;
135
136 return 1;
137}
138
139__setup("nofpu", fpu_disable);
140
141int __cpuinitdata mips_dsp_disabled;
142
143static int __init dsp_disable(char *s)
144{
145 cpu_data[0].ases &= ~MIPS_ASE_DSP;
146 mips_dsp_disabled = 1;
147
148 return 1;
149}
150
151__setup("nodsp", dsp_disable);
152
153void __init check_wait(void)
154{
155 struct cpuinfo_mips *c = ¤t_cpu_data;
156
157 if (nowait) {
158 printk("Wait instruction disabled.\n");
159 return;
160 }
161
162 switch (c->cputype) {
163 case CPU_R3081:
164 case CPU_R3081E:
165 cpu_wait = r3081_wait;
166 break;
167 case CPU_TX3927:
168 cpu_wait = r39xx_wait;
169 break;
170 case CPU_R4200:
171/* case CPU_R4300: */
172 case CPU_R4600:
173 case CPU_R4640:
174 case CPU_R4650:
175 case CPU_R4700:
176 case CPU_R5000:
177 case CPU_R5500:
178 case CPU_NEVADA:
179 case CPU_4KC:
180 case CPU_4KEC:
181 case CPU_4KSC:
182 case CPU_5KC:
183 case CPU_25KF:
184 case CPU_PR4450:
185 case CPU_BMIPS3300:
186 case CPU_BMIPS4350:
187 case CPU_BMIPS4380:
188 case CPU_BMIPS5000:
189 case CPU_CAVIUM_OCTEON:
190 case CPU_CAVIUM_OCTEON_PLUS:
191 case CPU_CAVIUM_OCTEON2:
192 case CPU_JZRISC:
193 cpu_wait = r4k_wait;
194 break;
195
196 case CPU_RM7000:
197 cpu_wait = rm7k_wait_irqoff;
198 break;
199
200 case CPU_24K:
201 case CPU_34K:
202 case CPU_1004K:
203 cpu_wait = r4k_wait;
204 if (read_c0_config7() & MIPS_CONF7_WII)
205 cpu_wait = r4k_wait_irqoff;
206 break;
207
208 case CPU_74K:
209 cpu_wait = r4k_wait;
210 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
211 cpu_wait = r4k_wait_irqoff;
212 break;
213
214 case CPU_TX49XX:
215 cpu_wait = r4k_wait_irqoff;
216 break;
217 case CPU_ALCHEMY:
218 cpu_wait = au1k_wait;
219 break;
220 case CPU_20KC:
221 /*
222 * WAIT on Rev1.0 has E1, E2, E3 and E16.
223 * WAIT on Rev2.0 and Rev3.0 has E16.
224 * Rev3.1 WAIT is nop, why bother
225 */
226 if ((c->processor_id & 0xff) <= 0x64)
227 break;
228
229 /*
230 * Another rev is incremeting c0_count at a reduced clock
231 * rate while in WAIT mode. So we basically have the choice
232 * between using the cp0 timer as clocksource or avoiding
233 * the WAIT instruction. Until more details are known,
234 * disable the use of WAIT for 20Kc entirely.
235 cpu_wait = r4k_wait;
236 */
237 break;
238 case CPU_RM9000:
239 if ((c->processor_id & 0x00ff) >= 0x40)
240 cpu_wait = r4k_wait;
241 break;
242 default:
243 break;
244 }
245}
246
247static inline void check_errata(void)
248{
249 struct cpuinfo_mips *c = ¤t_cpu_data;
250
251 switch (c->cputype) {
252 case CPU_34K:
253 /*
254 * Erratum "RPS May Cause Incorrect Instruction Execution"
255 * This code only handles VPE0, any SMP/SMTC/RTOS code
256 * making use of VPE1 will be responsable for that VPE.
257 */
258 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
259 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
260 break;
261 default:
262 break;
263 }
264}
265
266void __init check_bugs32(void)
267{
268 check_errata();
269}
270
271/*
272 * Probe whether cpu has config register by trying to play with
273 * alternate cache bit and see whether it matters.
274 * It's used by cpu_probe to distinguish between R3000A and R3081.
275 */
276static inline int cpu_has_confreg(void)
277{
278#ifdef CONFIG_CPU_R3000
279 extern unsigned long r3k_cache_size(unsigned long);
280 unsigned long size1, size2;
281 unsigned long cfg = read_c0_conf();
282
283 size1 = r3k_cache_size(ST0_ISC);
284 write_c0_conf(cfg ^ R30XX_CONF_AC);
285 size2 = r3k_cache_size(ST0_ISC);
286 write_c0_conf(cfg);
287 return size1 != size2;
288#else
289 return 0;
290#endif
291}
292
293static inline void set_elf_platform(int cpu, const char *plat)
294{
295 if (cpu == 0)
296 __elf_platform = plat;
297}
298
299/*
300 * Get the FPU Implementation/Revision.
301 */
302static inline unsigned long cpu_get_fpu_id(void)
303{
304 unsigned long tmp, fpu_id;
305
306 tmp = read_c0_status();
307 __enable_fpu();
308 fpu_id = read_32bit_cp1_register(CP1_REVISION);
309 write_c0_status(tmp);
310 return fpu_id;
311}
312
313/*
314 * Check the CPU has an FPU the official way.
315 */
316static inline int __cpu_has_fpu(void)
317{
318 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
319}
320
321static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
322{
323#ifdef __NEED_VMBITS_PROBE
324 write_c0_entryhi(0x3fffffffffffe000ULL);
325 back_to_back_c0_hazard();
326 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
327#endif
328}
329
330#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
331 | MIPS_CPU_COUNTER)
332
333static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
334{
335 switch (c->processor_id & 0xff00) {
336 case PRID_IMP_R2000:
337 c->cputype = CPU_R2000;
338 __cpu_name[cpu] = "R2000";
339 c->isa_level = MIPS_CPU_ISA_I;
340 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
341 MIPS_CPU_NOFPUEX;
342 if (__cpu_has_fpu())
343 c->options |= MIPS_CPU_FPU;
344 c->tlbsize = 64;
345 break;
346 case PRID_IMP_R3000:
347 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
348 if (cpu_has_confreg()) {
349 c->cputype = CPU_R3081E;
350 __cpu_name[cpu] = "R3081";
351 } else {
352 c->cputype = CPU_R3000A;
353 __cpu_name[cpu] = "R3000A";
354 }
355 break;
356 } else {
357 c->cputype = CPU_R3000;
358 __cpu_name[cpu] = "R3000";
359 }
360 c->isa_level = MIPS_CPU_ISA_I;
361 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
362 MIPS_CPU_NOFPUEX;
363 if (__cpu_has_fpu())
364 c->options |= MIPS_CPU_FPU;
365 c->tlbsize = 64;
366 break;
367 case PRID_IMP_R4000:
368 if (read_c0_config() & CONF_SC) {
369 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
370 c->cputype = CPU_R4400PC;
371 __cpu_name[cpu] = "R4400PC";
372 } else {
373 c->cputype = CPU_R4000PC;
374 __cpu_name[cpu] = "R4000PC";
375 }
376 } else {
377 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
378 c->cputype = CPU_R4400SC;
379 __cpu_name[cpu] = "R4400SC";
380 } else {
381 c->cputype = CPU_R4000SC;
382 __cpu_name[cpu] = "R4000SC";
383 }
384 }
385
386 c->isa_level = MIPS_CPU_ISA_III;
387 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
388 MIPS_CPU_WATCH | MIPS_CPU_VCE |
389 MIPS_CPU_LLSC;
390 c->tlbsize = 48;
391 break;
392 case PRID_IMP_VR41XX:
393 switch (c->processor_id & 0xf0) {
394 case PRID_REV_VR4111:
395 c->cputype = CPU_VR4111;
396 __cpu_name[cpu] = "NEC VR4111";
397 break;
398 case PRID_REV_VR4121:
399 c->cputype = CPU_VR4121;
400 __cpu_name[cpu] = "NEC VR4121";
401 break;
402 case PRID_REV_VR4122:
403 if ((c->processor_id & 0xf) < 0x3) {
404 c->cputype = CPU_VR4122;
405 __cpu_name[cpu] = "NEC VR4122";
406 } else {
407 c->cputype = CPU_VR4181A;
408 __cpu_name[cpu] = "NEC VR4181A";
409 }
410 break;
411 case PRID_REV_VR4130:
412 if ((c->processor_id & 0xf) < 0x4) {
413 c->cputype = CPU_VR4131;
414 __cpu_name[cpu] = "NEC VR4131";
415 } else {
416 c->cputype = CPU_VR4133;
417 __cpu_name[cpu] = "NEC VR4133";
418 }
419 break;
420 default:
421 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
422 c->cputype = CPU_VR41XX;
423 __cpu_name[cpu] = "NEC Vr41xx";
424 break;
425 }
426 c->isa_level = MIPS_CPU_ISA_III;
427 c->options = R4K_OPTS;
428 c->tlbsize = 32;
429 break;
430 case PRID_IMP_R4300:
431 c->cputype = CPU_R4300;
432 __cpu_name[cpu] = "R4300";
433 c->isa_level = MIPS_CPU_ISA_III;
434 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
435 MIPS_CPU_LLSC;
436 c->tlbsize = 32;
437 break;
438 case PRID_IMP_R4600:
439 c->cputype = CPU_R4600;
440 __cpu_name[cpu] = "R4600";
441 c->isa_level = MIPS_CPU_ISA_III;
442 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
443 MIPS_CPU_LLSC;
444 c->tlbsize = 48;
445 break;
446 #if 0
447 case PRID_IMP_R4650:
448 /*
449 * This processor doesn't have an MMU, so it's not
450 * "real easy" to run Linux on it. It is left purely
451 * for documentation. Commented out because it shares
452 * it's c0_prid id number with the TX3900.
453 */
454 c->cputype = CPU_R4650;
455 __cpu_name[cpu] = "R4650";
456 c->isa_level = MIPS_CPU_ISA_III;
457 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
458 c->tlbsize = 48;
459 break;
460 #endif
461 case PRID_IMP_TX39:
462 c->isa_level = MIPS_CPU_ISA_I;
463 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
464
465 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
466 c->cputype = CPU_TX3927;
467 __cpu_name[cpu] = "TX3927";
468 c->tlbsize = 64;
469 } else {
470 switch (c->processor_id & 0xff) {
471 case PRID_REV_TX3912:
472 c->cputype = CPU_TX3912;
473 __cpu_name[cpu] = "TX3912";
474 c->tlbsize = 32;
475 break;
476 case PRID_REV_TX3922:
477 c->cputype = CPU_TX3922;
478 __cpu_name[cpu] = "TX3922";
479 c->tlbsize = 64;
480 break;
481 }
482 }
483 break;
484 case PRID_IMP_R4700:
485 c->cputype = CPU_R4700;
486 __cpu_name[cpu] = "R4700";
487 c->isa_level = MIPS_CPU_ISA_III;
488 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
489 MIPS_CPU_LLSC;
490 c->tlbsize = 48;
491 break;
492 case PRID_IMP_TX49:
493 c->cputype = CPU_TX49XX;
494 __cpu_name[cpu] = "R49XX";
495 c->isa_level = MIPS_CPU_ISA_III;
496 c->options = R4K_OPTS | MIPS_CPU_LLSC;
497 if (!(c->processor_id & 0x08))
498 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
499 c->tlbsize = 48;
500 break;
501 case PRID_IMP_R5000:
502 c->cputype = CPU_R5000;
503 __cpu_name[cpu] = "R5000";
504 c->isa_level = MIPS_CPU_ISA_IV;
505 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
506 MIPS_CPU_LLSC;
507 c->tlbsize = 48;
508 break;
509 case PRID_IMP_R5432:
510 c->cputype = CPU_R5432;
511 __cpu_name[cpu] = "R5432";
512 c->isa_level = MIPS_CPU_ISA_IV;
513 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
514 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
515 c->tlbsize = 48;
516 break;
517 case PRID_IMP_R5500:
518 c->cputype = CPU_R5500;
519 __cpu_name[cpu] = "R5500";
520 c->isa_level = MIPS_CPU_ISA_IV;
521 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
522 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
523 c->tlbsize = 48;
524 break;
525 case PRID_IMP_NEVADA:
526 c->cputype = CPU_NEVADA;
527 __cpu_name[cpu] = "Nevada";
528 c->isa_level = MIPS_CPU_ISA_IV;
529 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
530 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
531 c->tlbsize = 48;
532 break;
533 case PRID_IMP_R6000:
534 c->cputype = CPU_R6000;
535 __cpu_name[cpu] = "R6000";
536 c->isa_level = MIPS_CPU_ISA_II;
537 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
538 MIPS_CPU_LLSC;
539 c->tlbsize = 32;
540 break;
541 case PRID_IMP_R6000A:
542 c->cputype = CPU_R6000A;
543 __cpu_name[cpu] = "R6000A";
544 c->isa_level = MIPS_CPU_ISA_II;
545 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
546 MIPS_CPU_LLSC;
547 c->tlbsize = 32;
548 break;
549 case PRID_IMP_RM7000:
550 c->cputype = CPU_RM7000;
551 __cpu_name[cpu] = "RM7000";
552 c->isa_level = MIPS_CPU_ISA_IV;
553 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
554 MIPS_CPU_LLSC;
555 /*
556 * Undocumented RM7000: Bit 29 in the info register of
557 * the RM7000 v2.0 indicates if the TLB has 48 or 64
558 * entries.
559 *
560 * 29 1 => 64 entry JTLB
561 * 0 => 48 entry JTLB
562 */
563 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
564 break;
565 case PRID_IMP_RM9000:
566 c->cputype = CPU_RM9000;
567 __cpu_name[cpu] = "RM9000";
568 c->isa_level = MIPS_CPU_ISA_IV;
569 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
570 MIPS_CPU_LLSC;
571 /*
572 * Bit 29 in the info register of the RM9000
573 * indicates if the TLB has 48 or 64 entries.
574 *
575 * 29 1 => 64 entry JTLB
576 * 0 => 48 entry JTLB
577 */
578 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
579 break;
580 case PRID_IMP_R8000:
581 c->cputype = CPU_R8000;
582 __cpu_name[cpu] = "RM8000";
583 c->isa_level = MIPS_CPU_ISA_IV;
584 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
585 MIPS_CPU_FPU | MIPS_CPU_32FPR |
586 MIPS_CPU_LLSC;
587 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
588 break;
589 case PRID_IMP_R10000:
590 c->cputype = CPU_R10000;
591 __cpu_name[cpu] = "R10000";
592 c->isa_level = MIPS_CPU_ISA_IV;
593 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
594 MIPS_CPU_FPU | MIPS_CPU_32FPR |
595 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
596 MIPS_CPU_LLSC;
597 c->tlbsize = 64;
598 break;
599 case PRID_IMP_R12000:
600 c->cputype = CPU_R12000;
601 __cpu_name[cpu] = "R12000";
602 c->isa_level = MIPS_CPU_ISA_IV;
603 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
604 MIPS_CPU_FPU | MIPS_CPU_32FPR |
605 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
606 MIPS_CPU_LLSC;
607 c->tlbsize = 64;
608 break;
609 case PRID_IMP_R14000:
610 c->cputype = CPU_R14000;
611 __cpu_name[cpu] = "R14000";
612 c->isa_level = MIPS_CPU_ISA_IV;
613 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
614 MIPS_CPU_FPU | MIPS_CPU_32FPR |
615 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
616 MIPS_CPU_LLSC;
617 c->tlbsize = 64;
618 break;
619 case PRID_IMP_LOONGSON2:
620 c->cputype = CPU_LOONGSON2;
621 __cpu_name[cpu] = "ICT Loongson-2";
622
623 switch (c->processor_id & PRID_REV_MASK) {
624 case PRID_REV_LOONGSON2E:
625 set_elf_platform(cpu, "loongson2e");
626 break;
627 case PRID_REV_LOONGSON2F:
628 set_elf_platform(cpu, "loongson2f");
629 break;
630 }
631
632 c->isa_level = MIPS_CPU_ISA_III;
633 c->options = R4K_OPTS |
634 MIPS_CPU_FPU | MIPS_CPU_LLSC |
635 MIPS_CPU_32FPR;
636 c->tlbsize = 64;
637 break;
638 }
639}
640
641static char unknown_isa[] __cpuinitdata = KERN_ERR \
642 "Unsupported ISA type, c0.config0: %d.";
643
644static inline unsigned int decode_config0(struct cpuinfo_mips *c)
645{
646 unsigned int config0;
647 int isa;
648
649 config0 = read_c0_config();
650
651 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
652 c->options |= MIPS_CPU_TLB;
653 isa = (config0 & MIPS_CONF_AT) >> 13;
654 switch (isa) {
655 case 0:
656 switch ((config0 & MIPS_CONF_AR) >> 10) {
657 case 0:
658 c->isa_level = MIPS_CPU_ISA_M32R1;
659 break;
660 case 1:
661 c->isa_level = MIPS_CPU_ISA_M32R2;
662 break;
663 default:
664 goto unknown;
665 }
666 break;
667 case 2:
668 switch ((config0 & MIPS_CONF_AR) >> 10) {
669 case 0:
670 c->isa_level = MIPS_CPU_ISA_M64R1;
671 break;
672 case 1:
673 c->isa_level = MIPS_CPU_ISA_M64R2;
674 break;
675 default:
676 goto unknown;
677 }
678 break;
679 default:
680 goto unknown;
681 }
682
683 return config0 & MIPS_CONF_M;
684
685unknown:
686 panic(unknown_isa, config0);
687}
688
689static inline unsigned int decode_config1(struct cpuinfo_mips *c)
690{
691 unsigned int config1;
692
693 config1 = read_c0_config1();
694
695 if (config1 & MIPS_CONF1_MD)
696 c->ases |= MIPS_ASE_MDMX;
697 if (config1 & MIPS_CONF1_WR)
698 c->options |= MIPS_CPU_WATCH;
699 if (config1 & MIPS_CONF1_CA)
700 c->ases |= MIPS_ASE_MIPS16;
701 if (config1 & MIPS_CONF1_EP)
702 c->options |= MIPS_CPU_EJTAG;
703 if (config1 & MIPS_CONF1_FP) {
704 c->options |= MIPS_CPU_FPU;
705 c->options |= MIPS_CPU_32FPR;
706 }
707 if (cpu_has_tlb)
708 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
709
710 return config1 & MIPS_CONF_M;
711}
712
713static inline unsigned int decode_config2(struct cpuinfo_mips *c)
714{
715 unsigned int config2;
716
717 config2 = read_c0_config2();
718
719 if (config2 & MIPS_CONF2_SL)
720 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
721
722 return config2 & MIPS_CONF_M;
723}
724
725static inline unsigned int decode_config3(struct cpuinfo_mips *c)
726{
727 unsigned int config3;
728
729 config3 = read_c0_config3();
730
731 if (config3 & MIPS_CONF3_SM)
732 c->ases |= MIPS_ASE_SMARTMIPS;
733 if (config3 & MIPS_CONF3_DSP)
734 c->ases |= MIPS_ASE_DSP;
735 if (config3 & MIPS_CONF3_VINT)
736 c->options |= MIPS_CPU_VINT;
737 if (config3 & MIPS_CONF3_VEIC)
738 c->options |= MIPS_CPU_VEIC;
739 if (config3 & MIPS_CONF3_MT)
740 c->ases |= MIPS_ASE_MIPSMT;
741 if (config3 & MIPS_CONF3_ULRI)
742 c->options |= MIPS_CPU_ULRI;
743
744 return config3 & MIPS_CONF_M;
745}
746
747static inline unsigned int decode_config4(struct cpuinfo_mips *c)
748{
749 unsigned int config4;
750
751 config4 = read_c0_config4();
752
753 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
754 && cpu_has_tlb)
755 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
756
757 c->kscratch_mask = (config4 >> 16) & 0xff;
758
759 return config4 & MIPS_CONF_M;
760}
761
762static void __cpuinit decode_configs(struct cpuinfo_mips *c)
763{
764 int ok;
765
766 /* MIPS32 or MIPS64 compliant CPU. */
767 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
768 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
769
770 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
771
772 ok = decode_config0(c); /* Read Config registers. */
773 BUG_ON(!ok); /* Arch spec violation! */
774 if (ok)
775 ok = decode_config1(c);
776 if (ok)
777 ok = decode_config2(c);
778 if (ok)
779 ok = decode_config3(c);
780 if (ok)
781 ok = decode_config4(c);
782
783 mips_probe_watch_registers(c);
784
785 if (cpu_has_mips_r2)
786 c->core = read_c0_ebase() & 0x3ff;
787}
788
789static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
790{
791 decode_configs(c);
792 switch (c->processor_id & 0xff00) {
793 case PRID_IMP_4KC:
794 c->cputype = CPU_4KC;
795 __cpu_name[cpu] = "MIPS 4Kc";
796 break;
797 case PRID_IMP_4KEC:
798 case PRID_IMP_4KECR2:
799 c->cputype = CPU_4KEC;
800 __cpu_name[cpu] = "MIPS 4KEc";
801 break;
802 case PRID_IMP_4KSC:
803 case PRID_IMP_4KSD:
804 c->cputype = CPU_4KSC;
805 __cpu_name[cpu] = "MIPS 4KSc";
806 break;
807 case PRID_IMP_5KC:
808 c->cputype = CPU_5KC;
809 __cpu_name[cpu] = "MIPS 5Kc";
810 break;
811 case PRID_IMP_20KC:
812 c->cputype = CPU_20KC;
813 __cpu_name[cpu] = "MIPS 20Kc";
814 break;
815 case PRID_IMP_24K:
816 case PRID_IMP_24KE:
817 c->cputype = CPU_24K;
818 __cpu_name[cpu] = "MIPS 24Kc";
819 break;
820 case PRID_IMP_25KF:
821 c->cputype = CPU_25KF;
822 __cpu_name[cpu] = "MIPS 25Kc";
823 break;
824 case PRID_IMP_34K:
825 c->cputype = CPU_34K;
826 __cpu_name[cpu] = "MIPS 34Kc";
827 break;
828 case PRID_IMP_74K:
829 c->cputype = CPU_74K;
830 __cpu_name[cpu] = "MIPS 74Kc";
831 break;
832 case PRID_IMP_1004K:
833 c->cputype = CPU_1004K;
834 __cpu_name[cpu] = "MIPS 1004Kc";
835 break;
836 }
837
838 spram_config();
839}
840
841static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
842{
843 decode_configs(c);
844 switch (c->processor_id & 0xff00) {
845 case PRID_IMP_AU1_REV1:
846 case PRID_IMP_AU1_REV2:
847 c->cputype = CPU_ALCHEMY;
848 switch ((c->processor_id >> 24) & 0xff) {
849 case 0:
850 __cpu_name[cpu] = "Au1000";
851 break;
852 case 1:
853 __cpu_name[cpu] = "Au1500";
854 break;
855 case 2:
856 __cpu_name[cpu] = "Au1100";
857 break;
858 case 3:
859 __cpu_name[cpu] = "Au1550";
860 break;
861 case 4:
862 __cpu_name[cpu] = "Au1200";
863 if ((c->processor_id & 0xff) == 2)
864 __cpu_name[cpu] = "Au1250";
865 break;
866 case 5:
867 __cpu_name[cpu] = "Au1210";
868 break;
869 default:
870 __cpu_name[cpu] = "Au1xxx";
871 break;
872 }
873 break;
874 }
875}
876
877static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
878{
879 decode_configs(c);
880
881 switch (c->processor_id & 0xff00) {
882 case PRID_IMP_SB1:
883 c->cputype = CPU_SB1;
884 __cpu_name[cpu] = "SiByte SB1";
885 /* FPU in pass1 is known to have issues. */
886 if ((c->processor_id & 0xff) < 0x02)
887 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
888 break;
889 case PRID_IMP_SB1A:
890 c->cputype = CPU_SB1A;
891 __cpu_name[cpu] = "SiByte SB1A";
892 break;
893 }
894}
895
896static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
897{
898 decode_configs(c);
899 switch (c->processor_id & 0xff00) {
900 case PRID_IMP_SR71000:
901 c->cputype = CPU_SR71000;
902 __cpu_name[cpu] = "Sandcraft SR71000";
903 c->scache.ways = 8;
904 c->tlbsize = 64;
905 break;
906 }
907}
908
909static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
910{
911 decode_configs(c);
912 switch (c->processor_id & 0xff00) {
913 case PRID_IMP_PR4450:
914 c->cputype = CPU_PR4450;
915 __cpu_name[cpu] = "Philips PR4450";
916 c->isa_level = MIPS_CPU_ISA_M32R1;
917 break;
918 }
919}
920
921static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
922{
923 decode_configs(c);
924 switch (c->processor_id & 0xff00) {
925 case PRID_IMP_BMIPS32_REV4:
926 case PRID_IMP_BMIPS32_REV8:
927 c->cputype = CPU_BMIPS32;
928 __cpu_name[cpu] = "Broadcom BMIPS32";
929 set_elf_platform(cpu, "bmips32");
930 break;
931 case PRID_IMP_BMIPS3300:
932 case PRID_IMP_BMIPS3300_ALT:
933 case PRID_IMP_BMIPS3300_BUG:
934 c->cputype = CPU_BMIPS3300;
935 __cpu_name[cpu] = "Broadcom BMIPS3300";
936 set_elf_platform(cpu, "bmips3300");
937 break;
938 case PRID_IMP_BMIPS43XX: {
939 int rev = c->processor_id & 0xff;
940
941 if (rev >= PRID_REV_BMIPS4380_LO &&
942 rev <= PRID_REV_BMIPS4380_HI) {
943 c->cputype = CPU_BMIPS4380;
944 __cpu_name[cpu] = "Broadcom BMIPS4380";
945 set_elf_platform(cpu, "bmips4380");
946 } else {
947 c->cputype = CPU_BMIPS4350;
948 __cpu_name[cpu] = "Broadcom BMIPS4350";
949 set_elf_platform(cpu, "bmips4350");
950 }
951 break;
952 }
953 case PRID_IMP_BMIPS5000:
954 c->cputype = CPU_BMIPS5000;
955 __cpu_name[cpu] = "Broadcom BMIPS5000";
956 set_elf_platform(cpu, "bmips5000");
957 c->options |= MIPS_CPU_ULRI;
958 break;
959 }
960}
961
962static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
963{
964 decode_configs(c);
965 switch (c->processor_id & 0xff00) {
966 case PRID_IMP_CAVIUM_CN38XX:
967 case PRID_IMP_CAVIUM_CN31XX:
968 case PRID_IMP_CAVIUM_CN30XX:
969 c->cputype = CPU_CAVIUM_OCTEON;
970 __cpu_name[cpu] = "Cavium Octeon";
971 goto platform;
972 case PRID_IMP_CAVIUM_CN58XX:
973 case PRID_IMP_CAVIUM_CN56XX:
974 case PRID_IMP_CAVIUM_CN50XX:
975 case PRID_IMP_CAVIUM_CN52XX:
976 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
977 __cpu_name[cpu] = "Cavium Octeon+";
978platform:
979 set_elf_platform(cpu, "octeon");
980 break;
981 case PRID_IMP_CAVIUM_CN63XX:
982 c->cputype = CPU_CAVIUM_OCTEON2;
983 __cpu_name[cpu] = "Cavium Octeon II";
984 set_elf_platform(cpu, "octeon2");
985 break;
986 default:
987 printk(KERN_INFO "Unknown Octeon chip!\n");
988 c->cputype = CPU_UNKNOWN;
989 break;
990 }
991}
992
993static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
994{
995 decode_configs(c);
996 /* JZRISC does not implement the CP0 counter. */
997 c->options &= ~MIPS_CPU_COUNTER;
998 switch (c->processor_id & 0xff00) {
999 case PRID_IMP_JZRISC:
1000 c->cputype = CPU_JZRISC;
1001 __cpu_name[cpu] = "Ingenic JZRISC";
1002 break;
1003 default:
1004 panic("Unknown Ingenic Processor ID!");
1005 break;
1006 }
1007}
1008
1009static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1010{
1011 decode_configs(c);
1012
1013 c->options = (MIPS_CPU_TLB |
1014 MIPS_CPU_4KEX |
1015 MIPS_CPU_COUNTER |
1016 MIPS_CPU_DIVEC |
1017 MIPS_CPU_WATCH |
1018 MIPS_CPU_EJTAG |
1019 MIPS_CPU_LLSC);
1020
1021 switch (c->processor_id & 0xff00) {
1022 case PRID_IMP_NETLOGIC_XLR732:
1023 case PRID_IMP_NETLOGIC_XLR716:
1024 case PRID_IMP_NETLOGIC_XLR532:
1025 case PRID_IMP_NETLOGIC_XLR308:
1026 case PRID_IMP_NETLOGIC_XLR532C:
1027 case PRID_IMP_NETLOGIC_XLR516C:
1028 case PRID_IMP_NETLOGIC_XLR508C:
1029 case PRID_IMP_NETLOGIC_XLR308C:
1030 c->cputype = CPU_XLR;
1031 __cpu_name[cpu] = "Netlogic XLR";
1032 break;
1033
1034 case PRID_IMP_NETLOGIC_XLS608:
1035 case PRID_IMP_NETLOGIC_XLS408:
1036 case PRID_IMP_NETLOGIC_XLS404:
1037 case PRID_IMP_NETLOGIC_XLS208:
1038 case PRID_IMP_NETLOGIC_XLS204:
1039 case PRID_IMP_NETLOGIC_XLS108:
1040 case PRID_IMP_NETLOGIC_XLS104:
1041 case PRID_IMP_NETLOGIC_XLS616B:
1042 case PRID_IMP_NETLOGIC_XLS608B:
1043 case PRID_IMP_NETLOGIC_XLS416B:
1044 case PRID_IMP_NETLOGIC_XLS412B:
1045 case PRID_IMP_NETLOGIC_XLS408B:
1046 case PRID_IMP_NETLOGIC_XLS404B:
1047 c->cputype = CPU_XLR;
1048 __cpu_name[cpu] = "Netlogic XLS";
1049 break;
1050
1051 default:
1052 printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n",
1053 c->processor_id);
1054 c->cputype = CPU_XLR;
1055 break;
1056 }
1057
1058 c->isa_level = MIPS_CPU_ISA_M64R1;
1059 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1060}
1061
1062#ifdef CONFIG_64BIT
1063/* For use by uaccess.h */
1064u64 __ua_limit;
1065EXPORT_SYMBOL(__ua_limit);
1066#endif
1067
1068const char *__cpu_name[NR_CPUS];
1069const char *__elf_platform;
1070
1071__cpuinit void cpu_probe(void)
1072{
1073 struct cpuinfo_mips *c = ¤t_cpu_data;
1074 unsigned int cpu = smp_processor_id();
1075
1076 c->processor_id = PRID_IMP_UNKNOWN;
1077 c->fpu_id = FPIR_IMP_NONE;
1078 c->cputype = CPU_UNKNOWN;
1079
1080 c->processor_id = read_c0_prid();
1081 switch (c->processor_id & 0xff0000) {
1082 case PRID_COMP_LEGACY:
1083 cpu_probe_legacy(c, cpu);
1084 break;
1085 case PRID_COMP_MIPS:
1086 cpu_probe_mips(c, cpu);
1087 break;
1088 case PRID_COMP_ALCHEMY:
1089 cpu_probe_alchemy(c, cpu);
1090 break;
1091 case PRID_COMP_SIBYTE:
1092 cpu_probe_sibyte(c, cpu);
1093 break;
1094 case PRID_COMP_BROADCOM:
1095 cpu_probe_broadcom(c, cpu);
1096 break;
1097 case PRID_COMP_SANDCRAFT:
1098 cpu_probe_sandcraft(c, cpu);
1099 break;
1100 case PRID_COMP_NXP:
1101 cpu_probe_nxp(c, cpu);
1102 break;
1103 case PRID_COMP_CAVIUM:
1104 cpu_probe_cavium(c, cpu);
1105 break;
1106 case PRID_COMP_INGENIC:
1107 cpu_probe_ingenic(c, cpu);
1108 break;
1109 case PRID_COMP_NETLOGIC:
1110 cpu_probe_netlogic(c, cpu);
1111 break;
1112 }
1113
1114 BUG_ON(!__cpu_name[cpu]);
1115 BUG_ON(c->cputype == CPU_UNKNOWN);
1116
1117 /*
1118 * Platform code can force the cpu type to optimize code
1119 * generation. In that case be sure the cpu type is correctly
1120 * manually setup otherwise it could trigger some nasty bugs.
1121 */
1122 BUG_ON(current_cpu_type() != c->cputype);
1123
1124 if (mips_fpu_disabled)
1125 c->options &= ~MIPS_CPU_FPU;
1126
1127 if (mips_dsp_disabled)
1128 c->ases &= ~MIPS_ASE_DSP;
1129
1130 if (c->options & MIPS_CPU_FPU) {
1131 c->fpu_id = cpu_get_fpu_id();
1132
1133 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
1134 c->isa_level == MIPS_CPU_ISA_M32R2 ||
1135 c->isa_level == MIPS_CPU_ISA_M64R1 ||
1136 c->isa_level == MIPS_CPU_ISA_M64R2) {
1137 if (c->fpu_id & MIPS_FPIR_3D)
1138 c->ases |= MIPS_ASE_MIPS3D;
1139 }
1140 }
1141
1142 if (cpu_has_mips_r2)
1143 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1144 else
1145 c->srsets = 1;
1146
1147 cpu_probe_vmbits(c);
1148
1149#ifdef CONFIG_64BIT
1150 if (cpu == 0)
1151 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1152#endif
1153}
1154
1155__cpuinit void cpu_report(void)
1156{
1157 struct cpuinfo_mips *c = ¤t_cpu_data;
1158
1159 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1160 c->processor_id, cpu_name_string());
1161 if (c->options & MIPS_CPU_FPU)
1162 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1163}