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1/*
2 * Processor capabilities determination functions.
3 *
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14#include <linux/init.h>
15#include <linux/kernel.h>
16#include <linux/ptrace.h>
17#include <linux/smp.h>
18#include <linux/stddef.h>
19#include <linux/export.h>
20
21#include <asm/bugs.h>
22#include <asm/cpu.h>
23#include <asm/cpu-features.h>
24#include <asm/cpu-type.h>
25#include <asm/fpu.h>
26#include <asm/mipsregs.h>
27#include <asm/mipsmtregs.h>
28#include <asm/msa.h>
29#include <asm/watch.h>
30#include <asm/elf.h>
31#include <asm/pgtable-bits.h>
32#include <asm/spram.h>
33#include <linux/uaccess.h>
34
35/* Hardware capabilities */
36unsigned int elf_hwcap __read_mostly;
37EXPORT_SYMBOL_GPL(elf_hwcap);
38
39/*
40 * Get the FPU Implementation/Revision.
41 */
42static inline unsigned long cpu_get_fpu_id(void)
43{
44 unsigned long tmp, fpu_id;
45
46 tmp = read_c0_status();
47 __enable_fpu(FPU_AS_IS);
48 fpu_id = read_32bit_cp1_register(CP1_REVISION);
49 write_c0_status(tmp);
50 return fpu_id;
51}
52
53/*
54 * Check if the CPU has an external FPU.
55 */
56static inline int __cpu_has_fpu(void)
57{
58 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
59}
60
61static inline unsigned long cpu_get_msa_id(void)
62{
63 unsigned long status, msa_id;
64
65 status = read_c0_status();
66 __enable_fpu(FPU_64BIT);
67 enable_msa();
68 msa_id = read_msa_ir();
69 disable_msa();
70 write_c0_status(status);
71 return msa_id;
72}
73
74/*
75 * Determine the FCSR mask for FPU hardware.
76 */
77static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
78{
79 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
80
81 fcsr = c->fpu_csr31;
82 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
83
84 sr = read_c0_status();
85 __enable_fpu(FPU_AS_IS);
86
87 fcsr0 = fcsr & mask;
88 write_32bit_cp1_register(CP1_STATUS, fcsr0);
89 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
90
91 fcsr1 = fcsr | ~mask;
92 write_32bit_cp1_register(CP1_STATUS, fcsr1);
93 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
94
95 write_32bit_cp1_register(CP1_STATUS, fcsr);
96
97 write_c0_status(sr);
98
99 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
100}
101
102/*
103 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
104 * supported by FPU hardware.
105 */
106static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
107{
108 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
109 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
110 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
111 unsigned long sr, fir, fcsr, fcsr0, fcsr1;
112
113 sr = read_c0_status();
114 __enable_fpu(FPU_AS_IS);
115
116 fir = read_32bit_cp1_register(CP1_REVISION);
117 if (fir & MIPS_FPIR_HAS2008) {
118 fcsr = read_32bit_cp1_register(CP1_STATUS);
119
120 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
121 write_32bit_cp1_register(CP1_STATUS, fcsr0);
122 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
123
124 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
125 write_32bit_cp1_register(CP1_STATUS, fcsr1);
126 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
127
128 write_32bit_cp1_register(CP1_STATUS, fcsr);
129
130 if (!(fcsr0 & FPU_CSR_NAN2008))
131 c->options |= MIPS_CPU_NAN_LEGACY;
132 if (fcsr1 & FPU_CSR_NAN2008)
133 c->options |= MIPS_CPU_NAN_2008;
134
135 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
136 c->fpu_msk31 &= ~FPU_CSR_ABS2008;
137 else
138 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
139
140 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
141 c->fpu_msk31 &= ~FPU_CSR_NAN2008;
142 else
143 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
144 } else {
145 c->options |= MIPS_CPU_NAN_LEGACY;
146 }
147
148 write_c0_status(sr);
149 } else {
150 c->options |= MIPS_CPU_NAN_LEGACY;
151 }
152}
153
154/*
155 * IEEE 754 conformance mode to use. Affects the NaN encoding and the
156 * ABS.fmt/NEG.fmt execution mode.
157 */
158static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
159
160/*
161 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
162 * to support by the FPU emulator according to the IEEE 754 conformance
163 * mode selected. Note that "relaxed" straps the emulator so that it
164 * allows 2008-NaN binaries even for legacy processors.
165 */
166static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
167{
168 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
169 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
170 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
171
172 switch (ieee754) {
173 case STRICT:
174 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
175 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
176 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
177 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
178 } else {
179 c->options |= MIPS_CPU_NAN_LEGACY;
180 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
181 }
182 break;
183 case LEGACY:
184 c->options |= MIPS_CPU_NAN_LEGACY;
185 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
186 break;
187 case STD2008:
188 c->options |= MIPS_CPU_NAN_2008;
189 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
190 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
191 break;
192 case RELAXED:
193 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
194 break;
195 }
196}
197
198/*
199 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
200 * according to the "ieee754=" parameter.
201 */
202static void cpu_set_nan_2008(struct cpuinfo_mips *c)
203{
204 switch (ieee754) {
205 case STRICT:
206 mips_use_nan_legacy = !!cpu_has_nan_legacy;
207 mips_use_nan_2008 = !!cpu_has_nan_2008;
208 break;
209 case LEGACY:
210 mips_use_nan_legacy = !!cpu_has_nan_legacy;
211 mips_use_nan_2008 = !cpu_has_nan_legacy;
212 break;
213 case STD2008:
214 mips_use_nan_legacy = !cpu_has_nan_2008;
215 mips_use_nan_2008 = !!cpu_has_nan_2008;
216 break;
217 case RELAXED:
218 mips_use_nan_legacy = true;
219 mips_use_nan_2008 = true;
220 break;
221 }
222}
223
224/*
225 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
226 * settings:
227 *
228 * strict: accept binaries that request a NaN encoding supported by the FPU
229 * legacy: only accept legacy-NaN binaries
230 * 2008: only accept 2008-NaN binaries
231 * relaxed: accept any binaries regardless of whether supported by the FPU
232 */
233static int __init ieee754_setup(char *s)
234{
235 if (!s)
236 return -1;
237 else if (!strcmp(s, "strict"))
238 ieee754 = STRICT;
239 else if (!strcmp(s, "legacy"))
240 ieee754 = LEGACY;
241 else if (!strcmp(s, "2008"))
242 ieee754 = STD2008;
243 else if (!strcmp(s, "relaxed"))
244 ieee754 = RELAXED;
245 else
246 return -1;
247
248 if (!(boot_cpu_data.options & MIPS_CPU_FPU))
249 cpu_set_nofpu_2008(&boot_cpu_data);
250 cpu_set_nan_2008(&boot_cpu_data);
251
252 return 0;
253}
254
255early_param("ieee754", ieee754_setup);
256
257/*
258 * Set the FIR feature flags for the FPU emulator.
259 */
260static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
261{
262 u32 value;
263
264 value = 0;
265 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
266 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
267 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
268 value |= MIPS_FPIR_D | MIPS_FPIR_S;
269 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
270 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
271 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
272 if (c->options & MIPS_CPU_NAN_2008)
273 value |= MIPS_FPIR_HAS2008;
274 c->fpu_id = value;
275}
276
277/* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
278static unsigned int mips_nofpu_msk31;
279
280/*
281 * Set options for FPU hardware.
282 */
283static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
284{
285 c->fpu_id = cpu_get_fpu_id();
286 mips_nofpu_msk31 = c->fpu_msk31;
287
288 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
289 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
290 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
291 if (c->fpu_id & MIPS_FPIR_3D)
292 c->ases |= MIPS_ASE_MIPS3D;
293 if (c->fpu_id & MIPS_FPIR_UFRP)
294 c->options |= MIPS_CPU_UFR;
295 if (c->fpu_id & MIPS_FPIR_FREP)
296 c->options |= MIPS_CPU_FRE;
297 }
298
299 cpu_set_fpu_fcsr_mask(c);
300 cpu_set_fpu_2008(c);
301 cpu_set_nan_2008(c);
302}
303
304/*
305 * Set options for the FPU emulator.
306 */
307static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
308{
309 c->options &= ~MIPS_CPU_FPU;
310 c->fpu_msk31 = mips_nofpu_msk31;
311
312 cpu_set_nofpu_2008(c);
313 cpu_set_nan_2008(c);
314 cpu_set_nofpu_id(c);
315}
316
317static int mips_fpu_disabled;
318
319static int __init fpu_disable(char *s)
320{
321 cpu_set_nofpu_opts(&boot_cpu_data);
322 mips_fpu_disabled = 1;
323
324 return 1;
325}
326
327__setup("nofpu", fpu_disable);
328
329static int mips_dsp_disabled;
330
331static int __init dsp_disable(char *s)
332{
333 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
334 mips_dsp_disabled = 1;
335
336 return 1;
337}
338
339__setup("nodsp", dsp_disable);
340
341static int mips_htw_disabled;
342
343static int __init htw_disable(char *s)
344{
345 mips_htw_disabled = 1;
346 cpu_data[0].options &= ~MIPS_CPU_HTW;
347 write_c0_pwctl(read_c0_pwctl() &
348 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
349
350 return 1;
351}
352
353__setup("nohtw", htw_disable);
354
355static int mips_ftlb_disabled;
356static int mips_has_ftlb_configured;
357
358enum ftlb_flags {
359 FTLB_EN = 1 << 0,
360 FTLB_SET_PROB = 1 << 1,
361};
362
363static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags);
364
365static int __init ftlb_disable(char *s)
366{
367 unsigned int config4, mmuextdef;
368
369 /*
370 * If the core hasn't done any FTLB configuration, there is nothing
371 * for us to do here.
372 */
373 if (!mips_has_ftlb_configured)
374 return 1;
375
376 /* Disable it in the boot cpu */
377 if (set_ftlb_enable(&cpu_data[0], 0)) {
378 pr_warn("Can't turn FTLB off\n");
379 return 1;
380 }
381
382 config4 = read_c0_config4();
383
384 /* Check that FTLB has been disabled */
385 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
386 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
387 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
388 /* This should never happen */
389 pr_warn("FTLB could not be disabled!\n");
390 return 1;
391 }
392
393 mips_ftlb_disabled = 1;
394 mips_has_ftlb_configured = 0;
395
396 /*
397 * noftlb is mainly used for debug purposes so print
398 * an informative message instead of using pr_debug()
399 */
400 pr_info("FTLB has been disabled\n");
401
402 /*
403 * Some of these bits are duplicated in the decode_config4.
404 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
405 * once FTLB has been disabled so undo what decode_config4 did.
406 */
407 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
408 cpu_data[0].tlbsizeftlbsets;
409 cpu_data[0].tlbsizeftlbsets = 0;
410 cpu_data[0].tlbsizeftlbways = 0;
411
412 return 1;
413}
414
415__setup("noftlb", ftlb_disable);
416
417
418static inline void check_errata(void)
419{
420 struct cpuinfo_mips *c = ¤t_cpu_data;
421
422 switch (current_cpu_type()) {
423 case CPU_34K:
424 /*
425 * Erratum "RPS May Cause Incorrect Instruction Execution"
426 * This code only handles VPE0, any SMP/RTOS code
427 * making use of VPE1 will be responsable for that VPE.
428 */
429 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
430 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
431 break;
432 default:
433 break;
434 }
435}
436
437void __init check_bugs32(void)
438{
439 check_errata();
440}
441
442/*
443 * Probe whether cpu has config register by trying to play with
444 * alternate cache bit and see whether it matters.
445 * It's used by cpu_probe to distinguish between R3000A and R3081.
446 */
447static inline int cpu_has_confreg(void)
448{
449#ifdef CONFIG_CPU_R3000
450 extern unsigned long r3k_cache_size(unsigned long);
451 unsigned long size1, size2;
452 unsigned long cfg = read_c0_conf();
453
454 size1 = r3k_cache_size(ST0_ISC);
455 write_c0_conf(cfg ^ R30XX_CONF_AC);
456 size2 = r3k_cache_size(ST0_ISC);
457 write_c0_conf(cfg);
458 return size1 != size2;
459#else
460 return 0;
461#endif
462}
463
464static inline void set_elf_platform(int cpu, const char *plat)
465{
466 if (cpu == 0)
467 __elf_platform = plat;
468}
469
470static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
471{
472#ifdef __NEED_VMBITS_PROBE
473 write_c0_entryhi(0x3fffffffffffe000ULL);
474 back_to_back_c0_hazard();
475 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
476#endif
477}
478
479static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
480{
481 switch (isa) {
482 case MIPS_CPU_ISA_M64R2:
483 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
484 case MIPS_CPU_ISA_M64R1:
485 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
486 case MIPS_CPU_ISA_V:
487 c->isa_level |= MIPS_CPU_ISA_V;
488 case MIPS_CPU_ISA_IV:
489 c->isa_level |= MIPS_CPU_ISA_IV;
490 case MIPS_CPU_ISA_III:
491 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
492 break;
493
494 /* R6 incompatible with everything else */
495 case MIPS_CPU_ISA_M64R6:
496 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
497 case MIPS_CPU_ISA_M32R6:
498 c->isa_level |= MIPS_CPU_ISA_M32R6;
499 /* Break here so we don't add incompatible ISAs */
500 break;
501 case MIPS_CPU_ISA_M32R2:
502 c->isa_level |= MIPS_CPU_ISA_M32R2;
503 case MIPS_CPU_ISA_M32R1:
504 c->isa_level |= MIPS_CPU_ISA_M32R1;
505 case MIPS_CPU_ISA_II:
506 c->isa_level |= MIPS_CPU_ISA_II;
507 break;
508 }
509}
510
511static char unknown_isa[] = KERN_ERR \
512 "Unsupported ISA type, c0.config0: %d.";
513
514static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
515{
516
517 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
518
519 /*
520 * 0 = All TLBWR instructions go to FTLB
521 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
522 * FTLB and 1 goes to the VTLB.
523 * 2 = 7:1: As above with 7:1 ratio.
524 * 3 = 3:1: As above with 3:1 ratio.
525 *
526 * Use the linear midpoint as the probability threshold.
527 */
528 if (probability >= 12)
529 return 1;
530 else if (probability >= 6)
531 return 2;
532 else
533 /*
534 * So FTLB is less than 4 times bigger than VTLB.
535 * A 3:1 ratio can still be useful though.
536 */
537 return 3;
538}
539
540static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
541{
542 unsigned int config;
543
544 /* It's implementation dependent how the FTLB can be enabled */
545 switch (c->cputype) {
546 case CPU_PROAPTIV:
547 case CPU_P5600:
548 case CPU_P6600:
549 /* proAptiv & related cores use Config6 to enable the FTLB */
550 config = read_c0_config6();
551
552 if (flags & FTLB_EN)
553 config |= MIPS_CONF6_FTLBEN;
554 else
555 config &= ~MIPS_CONF6_FTLBEN;
556
557 if (flags & FTLB_SET_PROB) {
558 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
559 config |= calculate_ftlb_probability(c)
560 << MIPS_CONF6_FTLBP_SHIFT;
561 }
562
563 write_c0_config6(config);
564 back_to_back_c0_hazard();
565 break;
566 case CPU_I6400:
567 case CPU_I6500:
568 /* There's no way to disable the FTLB */
569 if (!(flags & FTLB_EN))
570 return 1;
571 return 0;
572 case CPU_LOONGSON3:
573 /* Flush ITLB, DTLB, VTLB and FTLB */
574 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
575 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
576 /* Loongson-3 cores use Config6 to enable the FTLB */
577 config = read_c0_config6();
578 if (flags & FTLB_EN)
579 /* Enable FTLB */
580 write_c0_config6(config & ~MIPS_CONF6_FTLBDIS);
581 else
582 /* Disable FTLB */
583 write_c0_config6(config | MIPS_CONF6_FTLBDIS);
584 break;
585 default:
586 return 1;
587 }
588
589 return 0;
590}
591
592static inline unsigned int decode_config0(struct cpuinfo_mips *c)
593{
594 unsigned int config0;
595 int isa, mt;
596
597 config0 = read_c0_config();
598
599 /*
600 * Look for Standard TLB or Dual VTLB and FTLB
601 */
602 mt = config0 & MIPS_CONF_MT;
603 if (mt == MIPS_CONF_MT_TLB)
604 c->options |= MIPS_CPU_TLB;
605 else if (mt == MIPS_CONF_MT_FTLB)
606 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
607
608 isa = (config0 & MIPS_CONF_AT) >> 13;
609 switch (isa) {
610 case 0:
611 switch ((config0 & MIPS_CONF_AR) >> 10) {
612 case 0:
613 set_isa(c, MIPS_CPU_ISA_M32R1);
614 break;
615 case 1:
616 set_isa(c, MIPS_CPU_ISA_M32R2);
617 break;
618 case 2:
619 set_isa(c, MIPS_CPU_ISA_M32R6);
620 break;
621 default:
622 goto unknown;
623 }
624 break;
625 case 2:
626 switch ((config0 & MIPS_CONF_AR) >> 10) {
627 case 0:
628 set_isa(c, MIPS_CPU_ISA_M64R1);
629 break;
630 case 1:
631 set_isa(c, MIPS_CPU_ISA_M64R2);
632 break;
633 case 2:
634 set_isa(c, MIPS_CPU_ISA_M64R6);
635 break;
636 default:
637 goto unknown;
638 }
639 break;
640 default:
641 goto unknown;
642 }
643
644 return config0 & MIPS_CONF_M;
645
646unknown:
647 panic(unknown_isa, config0);
648}
649
650static inline unsigned int decode_config1(struct cpuinfo_mips *c)
651{
652 unsigned int config1;
653
654 config1 = read_c0_config1();
655
656 if (config1 & MIPS_CONF1_MD)
657 c->ases |= MIPS_ASE_MDMX;
658 if (config1 & MIPS_CONF1_PC)
659 c->options |= MIPS_CPU_PERF;
660 if (config1 & MIPS_CONF1_WR)
661 c->options |= MIPS_CPU_WATCH;
662 if (config1 & MIPS_CONF1_CA)
663 c->ases |= MIPS_ASE_MIPS16;
664 if (config1 & MIPS_CONF1_EP)
665 c->options |= MIPS_CPU_EJTAG;
666 if (config1 & MIPS_CONF1_FP) {
667 c->options |= MIPS_CPU_FPU;
668 c->options |= MIPS_CPU_32FPR;
669 }
670 if (cpu_has_tlb) {
671 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
672 c->tlbsizevtlb = c->tlbsize;
673 c->tlbsizeftlbsets = 0;
674 }
675
676 return config1 & MIPS_CONF_M;
677}
678
679static inline unsigned int decode_config2(struct cpuinfo_mips *c)
680{
681 unsigned int config2;
682
683 config2 = read_c0_config2();
684
685 if (config2 & MIPS_CONF2_SL)
686 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
687
688 return config2 & MIPS_CONF_M;
689}
690
691static inline unsigned int decode_config3(struct cpuinfo_mips *c)
692{
693 unsigned int config3;
694
695 config3 = read_c0_config3();
696
697 if (config3 & MIPS_CONF3_SM) {
698 c->ases |= MIPS_ASE_SMARTMIPS;
699 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;
700 }
701 if (config3 & MIPS_CONF3_RXI)
702 c->options |= MIPS_CPU_RIXI;
703 if (config3 & MIPS_CONF3_CTXTC)
704 c->options |= MIPS_CPU_CTXTC;
705 if (config3 & MIPS_CONF3_DSP)
706 c->ases |= MIPS_ASE_DSP;
707 if (config3 & MIPS_CONF3_DSP2P) {
708 c->ases |= MIPS_ASE_DSP2P;
709 if (cpu_has_mips_r6)
710 c->ases |= MIPS_ASE_DSP3;
711 }
712 if (config3 & MIPS_CONF3_VINT)
713 c->options |= MIPS_CPU_VINT;
714 if (config3 & MIPS_CONF3_VEIC)
715 c->options |= MIPS_CPU_VEIC;
716 if (config3 & MIPS_CONF3_LPA)
717 c->options |= MIPS_CPU_LPA;
718 if (config3 & MIPS_CONF3_MT)
719 c->ases |= MIPS_ASE_MIPSMT;
720 if (config3 & MIPS_CONF3_ULRI)
721 c->options |= MIPS_CPU_ULRI;
722 if (config3 & MIPS_CONF3_ISA)
723 c->options |= MIPS_CPU_MICROMIPS;
724 if (config3 & MIPS_CONF3_VZ)
725 c->ases |= MIPS_ASE_VZ;
726 if (config3 & MIPS_CONF3_SC)
727 c->options |= MIPS_CPU_SEGMENTS;
728 if (config3 & MIPS_CONF3_BI)
729 c->options |= MIPS_CPU_BADINSTR;
730 if (config3 & MIPS_CONF3_BP)
731 c->options |= MIPS_CPU_BADINSTRP;
732 if (config3 & MIPS_CONF3_MSA)
733 c->ases |= MIPS_ASE_MSA;
734 if (config3 & MIPS_CONF3_PW) {
735 c->htw_seq = 0;
736 c->options |= MIPS_CPU_HTW;
737 }
738 if (config3 & MIPS_CONF3_CDMM)
739 c->options |= MIPS_CPU_CDMM;
740 if (config3 & MIPS_CONF3_SP)
741 c->options |= MIPS_CPU_SP;
742
743 return config3 & MIPS_CONF_M;
744}
745
746static inline unsigned int decode_config4(struct cpuinfo_mips *c)
747{
748 unsigned int config4;
749 unsigned int newcf4;
750 unsigned int mmuextdef;
751 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
752 unsigned long asid_mask;
753
754 config4 = read_c0_config4();
755
756 if (cpu_has_tlb) {
757 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
758 c->options |= MIPS_CPU_TLBINV;
759
760 /*
761 * R6 has dropped the MMUExtDef field from config4.
762 * On R6 the fields always describe the FTLB, and only if it is
763 * present according to Config.MT.
764 */
765 if (!cpu_has_mips_r6)
766 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
767 else if (cpu_has_ftlb)
768 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
769 else
770 mmuextdef = 0;
771
772 switch (mmuextdef) {
773 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
774 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
775 c->tlbsizevtlb = c->tlbsize;
776 break;
777 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
778 c->tlbsizevtlb +=
779 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
780 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
781 c->tlbsize = c->tlbsizevtlb;
782 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
783 /* fall through */
784 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
785 if (mips_ftlb_disabled)
786 break;
787 newcf4 = (config4 & ~ftlb_page) |
788 (page_size_ftlb(mmuextdef) <<
789 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
790 write_c0_config4(newcf4);
791 back_to_back_c0_hazard();
792 config4 = read_c0_config4();
793 if (config4 != newcf4) {
794 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
795 PAGE_SIZE, config4);
796 /* Switch FTLB off */
797 set_ftlb_enable(c, 0);
798 mips_ftlb_disabled = 1;
799 break;
800 }
801 c->tlbsizeftlbsets = 1 <<
802 ((config4 & MIPS_CONF4_FTLBSETS) >>
803 MIPS_CONF4_FTLBSETS_SHIFT);
804 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
805 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
806 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
807 mips_has_ftlb_configured = 1;
808 break;
809 }
810 }
811
812 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
813 >> MIPS_CONF4_KSCREXIST_SHIFT;
814
815 asid_mask = MIPS_ENTRYHI_ASID;
816 if (config4 & MIPS_CONF4_AE)
817 asid_mask |= MIPS_ENTRYHI_ASIDX;
818 set_cpu_asid_mask(c, asid_mask);
819
820 /*
821 * Warn if the computed ASID mask doesn't match the mask the kernel
822 * is built for. This may indicate either a serious problem or an
823 * easy optimisation opportunity, but either way should be addressed.
824 */
825 WARN_ON(asid_mask != cpu_asid_mask(c));
826
827 return config4 & MIPS_CONF_M;
828}
829
830static inline unsigned int decode_config5(struct cpuinfo_mips *c)
831{
832 unsigned int config5;
833
834 config5 = read_c0_config5();
835 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
836 write_c0_config5(config5);
837
838 if (config5 & MIPS_CONF5_EVA)
839 c->options |= MIPS_CPU_EVA;
840 if (config5 & MIPS_CONF5_MRP)
841 c->options |= MIPS_CPU_MAAR;
842 if (config5 & MIPS_CONF5_LLB)
843 c->options |= MIPS_CPU_RW_LLB;
844 if (config5 & MIPS_CONF5_MVH)
845 c->options |= MIPS_CPU_MVH;
846 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
847 c->options |= MIPS_CPU_VP;
848 if (config5 & MIPS_CONF5_CA2)
849 c->ases |= MIPS_ASE_MIPS16E2;
850
851 if (config5 & MIPS_CONF5_CRCP)
852 elf_hwcap |= HWCAP_MIPS_CRC32;
853
854 return config5 & MIPS_CONF_M;
855}
856
857static void decode_configs(struct cpuinfo_mips *c)
858{
859 int ok;
860
861 /* MIPS32 or MIPS64 compliant CPU. */
862 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
863 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
864
865 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
866
867 /* Enable FTLB if present and not disabled */
868 set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN);
869
870 ok = decode_config0(c); /* Read Config registers. */
871 BUG_ON(!ok); /* Arch spec violation! */
872 if (ok)
873 ok = decode_config1(c);
874 if (ok)
875 ok = decode_config2(c);
876 if (ok)
877 ok = decode_config3(c);
878 if (ok)
879 ok = decode_config4(c);
880 if (ok)
881 ok = decode_config5(c);
882
883 /* Probe the EBase.WG bit */
884 if (cpu_has_mips_r2_r6) {
885 u64 ebase;
886 unsigned int status;
887
888 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */
889 ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
890 : (s32)read_c0_ebase();
891 if (ebase & MIPS_EBASE_WG) {
892 /* WG bit already set, we can avoid the clumsy probe */
893 c->options |= MIPS_CPU_EBASE_WG;
894 } else {
895 /* Its UNDEFINED to change EBase while BEV=0 */
896 status = read_c0_status();
897 write_c0_status(status | ST0_BEV);
898 irq_enable_hazard();
899 /*
900 * On pre-r6 cores, this may well clobber the upper bits
901 * of EBase. This is hard to avoid without potentially
902 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit.
903 */
904 if (cpu_has_mips64r6)
905 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
906 else
907 write_c0_ebase(ebase | MIPS_EBASE_WG);
908 back_to_back_c0_hazard();
909 /* Restore BEV */
910 write_c0_status(status);
911 if (read_c0_ebase() & MIPS_EBASE_WG) {
912 c->options |= MIPS_CPU_EBASE_WG;
913 write_c0_ebase(ebase);
914 }
915 }
916 }
917
918 /* configure the FTLB write probability */
919 set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB);
920
921 mips_probe_watch_registers(c);
922
923#ifndef CONFIG_MIPS_CPS
924 if (cpu_has_mips_r2_r6) {
925 unsigned int core;
926
927 core = get_ebase_cpunum();
928 if (cpu_has_mipsmt)
929 core >>= fls(core_nvpes()) - 1;
930 cpu_set_core(c, core);
931 }
932#endif
933}
934
935/*
936 * Probe for certain guest capabilities by writing config bits and reading back.
937 * Finally write back the original value.
938 */
939#define probe_gc0_config(name, maxconf, bits) \
940do { \
941 unsigned int tmp; \
942 tmp = read_gc0_##name(); \
943 write_gc0_##name(tmp | (bits)); \
944 back_to_back_c0_hazard(); \
945 maxconf = read_gc0_##name(); \
946 write_gc0_##name(tmp); \
947} while (0)
948
949/*
950 * Probe for dynamic guest capabilities by changing certain config bits and
951 * reading back to see if they change. Finally write back the original value.
952 */
953#define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \
954do { \
955 maxconf = read_gc0_##name(); \
956 write_gc0_##name(maxconf ^ (bits)); \
957 back_to_back_c0_hazard(); \
958 dynconf = maxconf ^ read_gc0_##name(); \
959 write_gc0_##name(maxconf); \
960 maxconf |= dynconf; \
961} while (0)
962
963static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c)
964{
965 unsigned int config0;
966
967 probe_gc0_config(config, config0, MIPS_CONF_M);
968
969 if (config0 & MIPS_CONF_M)
970 c->guest.conf |= BIT(1);
971 return config0 & MIPS_CONF_M;
972}
973
974static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c)
975{
976 unsigned int config1, config1_dyn;
977
978 probe_gc0_config_dyn(config1, config1, config1_dyn,
979 MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR |
980 MIPS_CONF1_FP);
981
982 if (config1 & MIPS_CONF1_FP)
983 c->guest.options |= MIPS_CPU_FPU;
984 if (config1_dyn & MIPS_CONF1_FP)
985 c->guest.options_dyn |= MIPS_CPU_FPU;
986
987 if (config1 & MIPS_CONF1_WR)
988 c->guest.options |= MIPS_CPU_WATCH;
989 if (config1_dyn & MIPS_CONF1_WR)
990 c->guest.options_dyn |= MIPS_CPU_WATCH;
991
992 if (config1 & MIPS_CONF1_PC)
993 c->guest.options |= MIPS_CPU_PERF;
994 if (config1_dyn & MIPS_CONF1_PC)
995 c->guest.options_dyn |= MIPS_CPU_PERF;
996
997 if (config1 & MIPS_CONF_M)
998 c->guest.conf |= BIT(2);
999 return config1 & MIPS_CONF_M;
1000}
1001
1002static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c)
1003{
1004 unsigned int config2;
1005
1006 probe_gc0_config(config2, config2, MIPS_CONF_M);
1007
1008 if (config2 & MIPS_CONF_M)
1009 c->guest.conf |= BIT(3);
1010 return config2 & MIPS_CONF_M;
1011}
1012
1013static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c)
1014{
1015 unsigned int config3, config3_dyn;
1016
1017 probe_gc0_config_dyn(config3, config3, config3_dyn,
1018 MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI |
1019 MIPS_CONF3_CTXTC);
1020
1021 if (config3 & MIPS_CONF3_CTXTC)
1022 c->guest.options |= MIPS_CPU_CTXTC;
1023 if (config3_dyn & MIPS_CONF3_CTXTC)
1024 c->guest.options_dyn |= MIPS_CPU_CTXTC;
1025
1026 if (config3 & MIPS_CONF3_PW)
1027 c->guest.options |= MIPS_CPU_HTW;
1028
1029 if (config3 & MIPS_CONF3_ULRI)
1030 c->guest.options |= MIPS_CPU_ULRI;
1031
1032 if (config3 & MIPS_CONF3_SC)
1033 c->guest.options |= MIPS_CPU_SEGMENTS;
1034
1035 if (config3 & MIPS_CONF3_BI)
1036 c->guest.options |= MIPS_CPU_BADINSTR;
1037 if (config3 & MIPS_CONF3_BP)
1038 c->guest.options |= MIPS_CPU_BADINSTRP;
1039
1040 if (config3 & MIPS_CONF3_MSA)
1041 c->guest.ases |= MIPS_ASE_MSA;
1042 if (config3_dyn & MIPS_CONF3_MSA)
1043 c->guest.ases_dyn |= MIPS_ASE_MSA;
1044
1045 if (config3 & MIPS_CONF_M)
1046 c->guest.conf |= BIT(4);
1047 return config3 & MIPS_CONF_M;
1048}
1049
1050static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c)
1051{
1052 unsigned int config4;
1053
1054 probe_gc0_config(config4, config4,
1055 MIPS_CONF_M | MIPS_CONF4_KSCREXIST);
1056
1057 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
1058 >> MIPS_CONF4_KSCREXIST_SHIFT;
1059
1060 if (config4 & MIPS_CONF_M)
1061 c->guest.conf |= BIT(5);
1062 return config4 & MIPS_CONF_M;
1063}
1064
1065static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c)
1066{
1067 unsigned int config5, config5_dyn;
1068
1069 probe_gc0_config_dyn(config5, config5, config5_dyn,
1070 MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP);
1071
1072 if (config5 & MIPS_CONF5_MRP)
1073 c->guest.options |= MIPS_CPU_MAAR;
1074 if (config5_dyn & MIPS_CONF5_MRP)
1075 c->guest.options_dyn |= MIPS_CPU_MAAR;
1076
1077 if (config5 & MIPS_CONF5_LLB)
1078 c->guest.options |= MIPS_CPU_RW_LLB;
1079
1080 if (config5 & MIPS_CONF5_MVH)
1081 c->guest.options |= MIPS_CPU_MVH;
1082
1083 if (config5 & MIPS_CONF_M)
1084 c->guest.conf |= BIT(6);
1085 return config5 & MIPS_CONF_M;
1086}
1087
1088static inline void decode_guest_configs(struct cpuinfo_mips *c)
1089{
1090 unsigned int ok;
1091
1092 ok = decode_guest_config0(c);
1093 if (ok)
1094 ok = decode_guest_config1(c);
1095 if (ok)
1096 ok = decode_guest_config2(c);
1097 if (ok)
1098 ok = decode_guest_config3(c);
1099 if (ok)
1100 ok = decode_guest_config4(c);
1101 if (ok)
1102 decode_guest_config5(c);
1103}
1104
1105static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c)
1106{
1107 unsigned int guestctl0, temp;
1108
1109 guestctl0 = read_c0_guestctl0();
1110
1111 if (guestctl0 & MIPS_GCTL0_G0E)
1112 c->options |= MIPS_CPU_GUESTCTL0EXT;
1113 if (guestctl0 & MIPS_GCTL0_G1)
1114 c->options |= MIPS_CPU_GUESTCTL1;
1115 if (guestctl0 & MIPS_GCTL0_G2)
1116 c->options |= MIPS_CPU_GUESTCTL2;
1117 if (!(guestctl0 & MIPS_GCTL0_RAD)) {
1118 c->options |= MIPS_CPU_GUESTID;
1119
1120 /*
1121 * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0
1122 * first, otherwise all data accesses will be fully virtualised
1123 * as if they were performed by guest mode.
1124 */
1125 write_c0_guestctl1(0);
1126 tlbw_use_hazard();
1127
1128 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG);
1129 back_to_back_c0_hazard();
1130 temp = read_c0_guestctl0();
1131
1132 if (temp & MIPS_GCTL0_DRG) {
1133 write_c0_guestctl0(guestctl0);
1134 c->options |= MIPS_CPU_DRG;
1135 }
1136 }
1137}
1138
1139static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c)
1140{
1141 if (cpu_has_guestid) {
1142 /* determine the number of bits of GuestID available */
1143 write_c0_guestctl1(MIPS_GCTL1_ID);
1144 back_to_back_c0_hazard();
1145 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID)
1146 >> MIPS_GCTL1_ID_SHIFT;
1147 write_c0_guestctl1(0);
1148 }
1149}
1150
1151static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c)
1152{
1153 /* determine the number of bits of GTOffset available */
1154 write_c0_gtoffset(0xffffffff);
1155 back_to_back_c0_hazard();
1156 c->gtoffset_mask = read_c0_gtoffset();
1157 write_c0_gtoffset(0);
1158}
1159
1160static inline void cpu_probe_vz(struct cpuinfo_mips *c)
1161{
1162 cpu_probe_guestctl0(c);
1163 if (cpu_has_guestctl1)
1164 cpu_probe_guestctl1(c);
1165
1166 cpu_probe_gtoffset(c);
1167
1168 decode_guest_configs(c);
1169}
1170
1171#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1172 | MIPS_CPU_COUNTER)
1173
1174static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1175{
1176 switch (c->processor_id & PRID_IMP_MASK) {
1177 case PRID_IMP_R2000:
1178 c->cputype = CPU_R2000;
1179 __cpu_name[cpu] = "R2000";
1180 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1181 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1182 MIPS_CPU_NOFPUEX;
1183 if (__cpu_has_fpu())
1184 c->options |= MIPS_CPU_FPU;
1185 c->tlbsize = 64;
1186 break;
1187 case PRID_IMP_R3000:
1188 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
1189 if (cpu_has_confreg()) {
1190 c->cputype = CPU_R3081E;
1191 __cpu_name[cpu] = "R3081";
1192 } else {
1193 c->cputype = CPU_R3000A;
1194 __cpu_name[cpu] = "R3000A";
1195 }
1196 } else {
1197 c->cputype = CPU_R3000;
1198 __cpu_name[cpu] = "R3000";
1199 }
1200 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1201 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1202 MIPS_CPU_NOFPUEX;
1203 if (__cpu_has_fpu())
1204 c->options |= MIPS_CPU_FPU;
1205 c->tlbsize = 64;
1206 break;
1207 case PRID_IMP_R4000:
1208 if (read_c0_config() & CONF_SC) {
1209 if ((c->processor_id & PRID_REV_MASK) >=
1210 PRID_REV_R4400) {
1211 c->cputype = CPU_R4400PC;
1212 __cpu_name[cpu] = "R4400PC";
1213 } else {
1214 c->cputype = CPU_R4000PC;
1215 __cpu_name[cpu] = "R4000PC";
1216 }
1217 } else {
1218 int cca = read_c0_config() & CONF_CM_CMASK;
1219 int mc;
1220
1221 /*
1222 * SC and MC versions can't be reliably told apart,
1223 * but only the latter support coherent caching
1224 * modes so assume the firmware has set the KSEG0
1225 * coherency attribute reasonably (if uncached, we
1226 * assume SC).
1227 */
1228 switch (cca) {
1229 case CONF_CM_CACHABLE_CE:
1230 case CONF_CM_CACHABLE_COW:
1231 case CONF_CM_CACHABLE_CUW:
1232 mc = 1;
1233 break;
1234 default:
1235 mc = 0;
1236 break;
1237 }
1238 if ((c->processor_id & PRID_REV_MASK) >=
1239 PRID_REV_R4400) {
1240 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
1241 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
1242 } else {
1243 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
1244 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
1245 }
1246 }
1247
1248 set_isa(c, MIPS_CPU_ISA_III);
1249 c->fpu_msk31 |= FPU_CSR_CONDX;
1250 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1251 MIPS_CPU_WATCH | MIPS_CPU_VCE |
1252 MIPS_CPU_LLSC;
1253 c->tlbsize = 48;
1254 break;
1255 case PRID_IMP_VR41XX:
1256 set_isa(c, MIPS_CPU_ISA_III);
1257 c->fpu_msk31 |= FPU_CSR_CONDX;
1258 c->options = R4K_OPTS;
1259 c->tlbsize = 32;
1260 switch (c->processor_id & 0xf0) {
1261 case PRID_REV_VR4111:
1262 c->cputype = CPU_VR4111;
1263 __cpu_name[cpu] = "NEC VR4111";
1264 break;
1265 case PRID_REV_VR4121:
1266 c->cputype = CPU_VR4121;
1267 __cpu_name[cpu] = "NEC VR4121";
1268 break;
1269 case PRID_REV_VR4122:
1270 if ((c->processor_id & 0xf) < 0x3) {
1271 c->cputype = CPU_VR4122;
1272 __cpu_name[cpu] = "NEC VR4122";
1273 } else {
1274 c->cputype = CPU_VR4181A;
1275 __cpu_name[cpu] = "NEC VR4181A";
1276 }
1277 break;
1278 case PRID_REV_VR4130:
1279 if ((c->processor_id & 0xf) < 0x4) {
1280 c->cputype = CPU_VR4131;
1281 __cpu_name[cpu] = "NEC VR4131";
1282 } else {
1283 c->cputype = CPU_VR4133;
1284 c->options |= MIPS_CPU_LLSC;
1285 __cpu_name[cpu] = "NEC VR4133";
1286 }
1287 break;
1288 default:
1289 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
1290 c->cputype = CPU_VR41XX;
1291 __cpu_name[cpu] = "NEC Vr41xx";
1292 break;
1293 }
1294 break;
1295 case PRID_IMP_R4300:
1296 c->cputype = CPU_R4300;
1297 __cpu_name[cpu] = "R4300";
1298 set_isa(c, MIPS_CPU_ISA_III);
1299 c->fpu_msk31 |= FPU_CSR_CONDX;
1300 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1301 MIPS_CPU_LLSC;
1302 c->tlbsize = 32;
1303 break;
1304 case PRID_IMP_R4600:
1305 c->cputype = CPU_R4600;
1306 __cpu_name[cpu] = "R4600";
1307 set_isa(c, MIPS_CPU_ISA_III);
1308 c->fpu_msk31 |= FPU_CSR_CONDX;
1309 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1310 MIPS_CPU_LLSC;
1311 c->tlbsize = 48;
1312 break;
1313 #if 0
1314 case PRID_IMP_R4650:
1315 /*
1316 * This processor doesn't have an MMU, so it's not
1317 * "real easy" to run Linux on it. It is left purely
1318 * for documentation. Commented out because it shares
1319 * it's c0_prid id number with the TX3900.
1320 */
1321 c->cputype = CPU_R4650;
1322 __cpu_name[cpu] = "R4650";
1323 set_isa(c, MIPS_CPU_ISA_III);
1324 c->fpu_msk31 |= FPU_CSR_CONDX;
1325 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
1326 c->tlbsize = 48;
1327 break;
1328 #endif
1329 case PRID_IMP_TX39:
1330 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1331 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1332
1333 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1334 c->cputype = CPU_TX3927;
1335 __cpu_name[cpu] = "TX3927";
1336 c->tlbsize = 64;
1337 } else {
1338 switch (c->processor_id & PRID_REV_MASK) {
1339 case PRID_REV_TX3912:
1340 c->cputype = CPU_TX3912;
1341 __cpu_name[cpu] = "TX3912";
1342 c->tlbsize = 32;
1343 break;
1344 case PRID_REV_TX3922:
1345 c->cputype = CPU_TX3922;
1346 __cpu_name[cpu] = "TX3922";
1347 c->tlbsize = 64;
1348 break;
1349 }
1350 }
1351 break;
1352 case PRID_IMP_R4700:
1353 c->cputype = CPU_R4700;
1354 __cpu_name[cpu] = "R4700";
1355 set_isa(c, MIPS_CPU_ISA_III);
1356 c->fpu_msk31 |= FPU_CSR_CONDX;
1357 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1358 MIPS_CPU_LLSC;
1359 c->tlbsize = 48;
1360 break;
1361 case PRID_IMP_TX49:
1362 c->cputype = CPU_TX49XX;
1363 __cpu_name[cpu] = "R49XX";
1364 set_isa(c, MIPS_CPU_ISA_III);
1365 c->fpu_msk31 |= FPU_CSR_CONDX;
1366 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1367 if (!(c->processor_id & 0x08))
1368 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1369 c->tlbsize = 48;
1370 break;
1371 case PRID_IMP_R5000:
1372 c->cputype = CPU_R5000;
1373 __cpu_name[cpu] = "R5000";
1374 set_isa(c, MIPS_CPU_ISA_IV);
1375 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1376 MIPS_CPU_LLSC;
1377 c->tlbsize = 48;
1378 break;
1379 case PRID_IMP_R5432:
1380 c->cputype = CPU_R5432;
1381 __cpu_name[cpu] = "R5432";
1382 set_isa(c, MIPS_CPU_ISA_IV);
1383 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1384 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1385 c->tlbsize = 48;
1386 break;
1387 case PRID_IMP_R5500:
1388 c->cputype = CPU_R5500;
1389 __cpu_name[cpu] = "R5500";
1390 set_isa(c, MIPS_CPU_ISA_IV);
1391 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1392 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1393 c->tlbsize = 48;
1394 break;
1395 case PRID_IMP_NEVADA:
1396 c->cputype = CPU_NEVADA;
1397 __cpu_name[cpu] = "Nevada";
1398 set_isa(c, MIPS_CPU_ISA_IV);
1399 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1400 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1401 c->tlbsize = 48;
1402 break;
1403 case PRID_IMP_RM7000:
1404 c->cputype = CPU_RM7000;
1405 __cpu_name[cpu] = "RM7000";
1406 set_isa(c, MIPS_CPU_ISA_IV);
1407 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1408 MIPS_CPU_LLSC;
1409 /*
1410 * Undocumented RM7000: Bit 29 in the info register of
1411 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1412 * entries.
1413 *
1414 * 29 1 => 64 entry JTLB
1415 * 0 => 48 entry JTLB
1416 */
1417 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1418 break;
1419 case PRID_IMP_R8000:
1420 c->cputype = CPU_R8000;
1421 __cpu_name[cpu] = "RM8000";
1422 set_isa(c, MIPS_CPU_ISA_IV);
1423 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
1424 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1425 MIPS_CPU_LLSC;
1426 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
1427 break;
1428 case PRID_IMP_R10000:
1429 c->cputype = CPU_R10000;
1430 __cpu_name[cpu] = "R10000";
1431 set_isa(c, MIPS_CPU_ISA_IV);
1432 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1433 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1434 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1435 MIPS_CPU_LLSC;
1436 c->tlbsize = 64;
1437 break;
1438 case PRID_IMP_R12000:
1439 c->cputype = CPU_R12000;
1440 __cpu_name[cpu] = "R12000";
1441 set_isa(c, MIPS_CPU_ISA_IV);
1442 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1443 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1444 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1445 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1446 c->tlbsize = 64;
1447 break;
1448 case PRID_IMP_R14000:
1449 if (((c->processor_id >> 4) & 0x0f) > 2) {
1450 c->cputype = CPU_R16000;
1451 __cpu_name[cpu] = "R16000";
1452 } else {
1453 c->cputype = CPU_R14000;
1454 __cpu_name[cpu] = "R14000";
1455 }
1456 set_isa(c, MIPS_CPU_ISA_IV);
1457 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1458 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1459 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1460 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1461 c->tlbsize = 64;
1462 break;
1463 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1464 switch (c->processor_id & PRID_REV_MASK) {
1465 case PRID_REV_LOONGSON2E:
1466 c->cputype = CPU_LOONGSON2;
1467 __cpu_name[cpu] = "ICT Loongson-2";
1468 set_elf_platform(cpu, "loongson2e");
1469 set_isa(c, MIPS_CPU_ISA_III);
1470 c->fpu_msk31 |= FPU_CSR_CONDX;
1471 break;
1472 case PRID_REV_LOONGSON2F:
1473 c->cputype = CPU_LOONGSON2;
1474 __cpu_name[cpu] = "ICT Loongson-2";
1475 set_elf_platform(cpu, "loongson2f");
1476 set_isa(c, MIPS_CPU_ISA_III);
1477 c->fpu_msk31 |= FPU_CSR_CONDX;
1478 break;
1479 case PRID_REV_LOONGSON3A_R1:
1480 c->cputype = CPU_LOONGSON3;
1481 __cpu_name[cpu] = "ICT Loongson-3";
1482 set_elf_platform(cpu, "loongson3a");
1483 set_isa(c, MIPS_CPU_ISA_M64R1);
1484 break;
1485 case PRID_REV_LOONGSON3B_R1:
1486 case PRID_REV_LOONGSON3B_R2:
1487 c->cputype = CPU_LOONGSON3;
1488 __cpu_name[cpu] = "ICT Loongson-3";
1489 set_elf_platform(cpu, "loongson3b");
1490 set_isa(c, MIPS_CPU_ISA_M64R1);
1491 break;
1492 }
1493
1494 c->options = R4K_OPTS |
1495 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1496 MIPS_CPU_32FPR;
1497 c->tlbsize = 64;
1498 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1499 break;
1500 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
1501 decode_configs(c);
1502
1503 c->cputype = CPU_LOONGSON1;
1504
1505 switch (c->processor_id & PRID_REV_MASK) {
1506 case PRID_REV_LOONGSON1B:
1507 __cpu_name[cpu] = "Loongson 1B";
1508 break;
1509 }
1510
1511 break;
1512 }
1513}
1514
1515static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1516{
1517 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1518 switch (c->processor_id & PRID_IMP_MASK) {
1519 case PRID_IMP_QEMU_GENERIC:
1520 c->writecombine = _CACHE_UNCACHED;
1521 c->cputype = CPU_QEMU_GENERIC;
1522 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1523 break;
1524 case PRID_IMP_4KC:
1525 c->cputype = CPU_4KC;
1526 c->writecombine = _CACHE_UNCACHED;
1527 __cpu_name[cpu] = "MIPS 4Kc";
1528 break;
1529 case PRID_IMP_4KEC:
1530 case PRID_IMP_4KECR2:
1531 c->cputype = CPU_4KEC;
1532 c->writecombine = _CACHE_UNCACHED;
1533 __cpu_name[cpu] = "MIPS 4KEc";
1534 break;
1535 case PRID_IMP_4KSC:
1536 case PRID_IMP_4KSD:
1537 c->cputype = CPU_4KSC;
1538 c->writecombine = _CACHE_UNCACHED;
1539 __cpu_name[cpu] = "MIPS 4KSc";
1540 break;
1541 case PRID_IMP_5KC:
1542 c->cputype = CPU_5KC;
1543 c->writecombine = _CACHE_UNCACHED;
1544 __cpu_name[cpu] = "MIPS 5Kc";
1545 break;
1546 case PRID_IMP_5KE:
1547 c->cputype = CPU_5KE;
1548 c->writecombine = _CACHE_UNCACHED;
1549 __cpu_name[cpu] = "MIPS 5KE";
1550 break;
1551 case PRID_IMP_20KC:
1552 c->cputype = CPU_20KC;
1553 c->writecombine = _CACHE_UNCACHED;
1554 __cpu_name[cpu] = "MIPS 20Kc";
1555 break;
1556 case PRID_IMP_24K:
1557 c->cputype = CPU_24K;
1558 c->writecombine = _CACHE_UNCACHED;
1559 __cpu_name[cpu] = "MIPS 24Kc";
1560 break;
1561 case PRID_IMP_24KE:
1562 c->cputype = CPU_24K;
1563 c->writecombine = _CACHE_UNCACHED;
1564 __cpu_name[cpu] = "MIPS 24KEc";
1565 break;
1566 case PRID_IMP_25KF:
1567 c->cputype = CPU_25KF;
1568 c->writecombine = _CACHE_UNCACHED;
1569 __cpu_name[cpu] = "MIPS 25Kc";
1570 break;
1571 case PRID_IMP_34K:
1572 c->cputype = CPU_34K;
1573 c->writecombine = _CACHE_UNCACHED;
1574 __cpu_name[cpu] = "MIPS 34Kc";
1575 break;
1576 case PRID_IMP_74K:
1577 c->cputype = CPU_74K;
1578 c->writecombine = _CACHE_UNCACHED;
1579 __cpu_name[cpu] = "MIPS 74Kc";
1580 break;
1581 case PRID_IMP_M14KC:
1582 c->cputype = CPU_M14KC;
1583 c->writecombine = _CACHE_UNCACHED;
1584 __cpu_name[cpu] = "MIPS M14Kc";
1585 break;
1586 case PRID_IMP_M14KEC:
1587 c->cputype = CPU_M14KEC;
1588 c->writecombine = _CACHE_UNCACHED;
1589 __cpu_name[cpu] = "MIPS M14KEc";
1590 break;
1591 case PRID_IMP_1004K:
1592 c->cputype = CPU_1004K;
1593 c->writecombine = _CACHE_UNCACHED;
1594 __cpu_name[cpu] = "MIPS 1004Kc";
1595 break;
1596 case PRID_IMP_1074K:
1597 c->cputype = CPU_1074K;
1598 c->writecombine = _CACHE_UNCACHED;
1599 __cpu_name[cpu] = "MIPS 1074Kc";
1600 break;
1601 case PRID_IMP_INTERAPTIV_UP:
1602 c->cputype = CPU_INTERAPTIV;
1603 __cpu_name[cpu] = "MIPS interAptiv";
1604 break;
1605 case PRID_IMP_INTERAPTIV_MP:
1606 c->cputype = CPU_INTERAPTIV;
1607 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1608 break;
1609 case PRID_IMP_PROAPTIV_UP:
1610 c->cputype = CPU_PROAPTIV;
1611 __cpu_name[cpu] = "MIPS proAptiv";
1612 break;
1613 case PRID_IMP_PROAPTIV_MP:
1614 c->cputype = CPU_PROAPTIV;
1615 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1616 break;
1617 case PRID_IMP_P5600:
1618 c->cputype = CPU_P5600;
1619 __cpu_name[cpu] = "MIPS P5600";
1620 break;
1621 case PRID_IMP_P6600:
1622 c->cputype = CPU_P6600;
1623 __cpu_name[cpu] = "MIPS P6600";
1624 break;
1625 case PRID_IMP_I6400:
1626 c->cputype = CPU_I6400;
1627 __cpu_name[cpu] = "MIPS I6400";
1628 break;
1629 case PRID_IMP_I6500:
1630 c->cputype = CPU_I6500;
1631 __cpu_name[cpu] = "MIPS I6500";
1632 break;
1633 case PRID_IMP_M5150:
1634 c->cputype = CPU_M5150;
1635 __cpu_name[cpu] = "MIPS M5150";
1636 break;
1637 case PRID_IMP_M6250:
1638 c->cputype = CPU_M6250;
1639 __cpu_name[cpu] = "MIPS M6250";
1640 break;
1641 }
1642
1643 decode_configs(c);
1644
1645 spram_config();
1646
1647 switch (__get_cpu_type(c->cputype)) {
1648 case CPU_I6500:
1649 c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES;
1650 /* fall-through */
1651 case CPU_I6400:
1652 c->options |= MIPS_CPU_SHARED_FTLB_RAM;
1653 /* fall-through */
1654 default:
1655 break;
1656 }
1657}
1658
1659static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1660{
1661 decode_configs(c);
1662 switch (c->processor_id & PRID_IMP_MASK) {
1663 case PRID_IMP_AU1_REV1:
1664 case PRID_IMP_AU1_REV2:
1665 c->cputype = CPU_ALCHEMY;
1666 switch ((c->processor_id >> 24) & 0xff) {
1667 case 0:
1668 __cpu_name[cpu] = "Au1000";
1669 break;
1670 case 1:
1671 __cpu_name[cpu] = "Au1500";
1672 break;
1673 case 2:
1674 __cpu_name[cpu] = "Au1100";
1675 break;
1676 case 3:
1677 __cpu_name[cpu] = "Au1550";
1678 break;
1679 case 4:
1680 __cpu_name[cpu] = "Au1200";
1681 if ((c->processor_id & PRID_REV_MASK) == 2)
1682 __cpu_name[cpu] = "Au1250";
1683 break;
1684 case 5:
1685 __cpu_name[cpu] = "Au1210";
1686 break;
1687 default:
1688 __cpu_name[cpu] = "Au1xxx";
1689 break;
1690 }
1691 break;
1692 }
1693}
1694
1695static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1696{
1697 decode_configs(c);
1698
1699 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1700 switch (c->processor_id & PRID_IMP_MASK) {
1701 case PRID_IMP_SB1:
1702 c->cputype = CPU_SB1;
1703 __cpu_name[cpu] = "SiByte SB1";
1704 /* FPU in pass1 is known to have issues. */
1705 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1706 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1707 break;
1708 case PRID_IMP_SB1A:
1709 c->cputype = CPU_SB1A;
1710 __cpu_name[cpu] = "SiByte SB1A";
1711 break;
1712 }
1713}
1714
1715static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1716{
1717 decode_configs(c);
1718 switch (c->processor_id & PRID_IMP_MASK) {
1719 case PRID_IMP_SR71000:
1720 c->cputype = CPU_SR71000;
1721 __cpu_name[cpu] = "Sandcraft SR71000";
1722 c->scache.ways = 8;
1723 c->tlbsize = 64;
1724 break;
1725 }
1726}
1727
1728static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1729{
1730 decode_configs(c);
1731 switch (c->processor_id & PRID_IMP_MASK) {
1732 case PRID_IMP_PR4450:
1733 c->cputype = CPU_PR4450;
1734 __cpu_name[cpu] = "Philips PR4450";
1735 set_isa(c, MIPS_CPU_ISA_M32R1);
1736 break;
1737 }
1738}
1739
1740static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1741{
1742 decode_configs(c);
1743 switch (c->processor_id & PRID_IMP_MASK) {
1744 case PRID_IMP_BMIPS32_REV4:
1745 case PRID_IMP_BMIPS32_REV8:
1746 c->cputype = CPU_BMIPS32;
1747 __cpu_name[cpu] = "Broadcom BMIPS32";
1748 set_elf_platform(cpu, "bmips32");
1749 break;
1750 case PRID_IMP_BMIPS3300:
1751 case PRID_IMP_BMIPS3300_ALT:
1752 case PRID_IMP_BMIPS3300_BUG:
1753 c->cputype = CPU_BMIPS3300;
1754 __cpu_name[cpu] = "Broadcom BMIPS3300";
1755 set_elf_platform(cpu, "bmips3300");
1756 break;
1757 case PRID_IMP_BMIPS43XX: {
1758 int rev = c->processor_id & PRID_REV_MASK;
1759
1760 if (rev >= PRID_REV_BMIPS4380_LO &&
1761 rev <= PRID_REV_BMIPS4380_HI) {
1762 c->cputype = CPU_BMIPS4380;
1763 __cpu_name[cpu] = "Broadcom BMIPS4380";
1764 set_elf_platform(cpu, "bmips4380");
1765 c->options |= MIPS_CPU_RIXI;
1766 } else {
1767 c->cputype = CPU_BMIPS4350;
1768 __cpu_name[cpu] = "Broadcom BMIPS4350";
1769 set_elf_platform(cpu, "bmips4350");
1770 }
1771 break;
1772 }
1773 case PRID_IMP_BMIPS5000:
1774 case PRID_IMP_BMIPS5200:
1775 c->cputype = CPU_BMIPS5000;
1776 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1777 __cpu_name[cpu] = "Broadcom BMIPS5200";
1778 else
1779 __cpu_name[cpu] = "Broadcom BMIPS5000";
1780 set_elf_platform(cpu, "bmips5000");
1781 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
1782 break;
1783 }
1784}
1785
1786static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1787{
1788 decode_configs(c);
1789 switch (c->processor_id & PRID_IMP_MASK) {
1790 case PRID_IMP_CAVIUM_CN38XX:
1791 case PRID_IMP_CAVIUM_CN31XX:
1792 case PRID_IMP_CAVIUM_CN30XX:
1793 c->cputype = CPU_CAVIUM_OCTEON;
1794 __cpu_name[cpu] = "Cavium Octeon";
1795 goto platform;
1796 case PRID_IMP_CAVIUM_CN58XX:
1797 case PRID_IMP_CAVIUM_CN56XX:
1798 case PRID_IMP_CAVIUM_CN50XX:
1799 case PRID_IMP_CAVIUM_CN52XX:
1800 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1801 __cpu_name[cpu] = "Cavium Octeon+";
1802platform:
1803 set_elf_platform(cpu, "octeon");
1804 break;
1805 case PRID_IMP_CAVIUM_CN61XX:
1806 case PRID_IMP_CAVIUM_CN63XX:
1807 case PRID_IMP_CAVIUM_CN66XX:
1808 case PRID_IMP_CAVIUM_CN68XX:
1809 case PRID_IMP_CAVIUM_CNF71XX:
1810 c->cputype = CPU_CAVIUM_OCTEON2;
1811 __cpu_name[cpu] = "Cavium Octeon II";
1812 set_elf_platform(cpu, "octeon2");
1813 break;
1814 case PRID_IMP_CAVIUM_CN70XX:
1815 case PRID_IMP_CAVIUM_CN73XX:
1816 case PRID_IMP_CAVIUM_CNF75XX:
1817 case PRID_IMP_CAVIUM_CN78XX:
1818 c->cputype = CPU_CAVIUM_OCTEON3;
1819 __cpu_name[cpu] = "Cavium Octeon III";
1820 set_elf_platform(cpu, "octeon3");
1821 break;
1822 default:
1823 printk(KERN_INFO "Unknown Octeon chip!\n");
1824 c->cputype = CPU_UNKNOWN;
1825 break;
1826 }
1827}
1828
1829static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
1830{
1831 switch (c->processor_id & PRID_IMP_MASK) {
1832 case PRID_IMP_LOONGSON_64: /* Loongson-2/3 */
1833 switch (c->processor_id & PRID_REV_MASK) {
1834 case PRID_REV_LOONGSON3A_R2:
1835 c->cputype = CPU_LOONGSON3;
1836 __cpu_name[cpu] = "ICT Loongson-3";
1837 set_elf_platform(cpu, "loongson3a");
1838 set_isa(c, MIPS_CPU_ISA_M64R2);
1839 break;
1840 case PRID_REV_LOONGSON3A_R3:
1841 c->cputype = CPU_LOONGSON3;
1842 __cpu_name[cpu] = "ICT Loongson-3";
1843 set_elf_platform(cpu, "loongson3a");
1844 set_isa(c, MIPS_CPU_ISA_M64R2);
1845 break;
1846 }
1847
1848 decode_configs(c);
1849 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
1850 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1851 break;
1852 default:
1853 panic("Unknown Loongson Processor ID!");
1854 break;
1855 }
1856}
1857
1858static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1859{
1860 decode_configs(c);
1861 /* JZRISC does not implement the CP0 counter. */
1862 c->options &= ~MIPS_CPU_COUNTER;
1863 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1864 switch (c->processor_id & PRID_IMP_MASK) {
1865 case PRID_IMP_JZRISC:
1866 c->cputype = CPU_JZRISC;
1867 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1868 __cpu_name[cpu] = "Ingenic JZRISC";
1869 break;
1870 default:
1871 panic("Unknown Ingenic Processor ID!");
1872 break;
1873 }
1874}
1875
1876static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1877{
1878 decode_configs(c);
1879
1880 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1881 c->cputype = CPU_ALCHEMY;
1882 __cpu_name[cpu] = "Au1300";
1883 /* following stuff is not for Alchemy */
1884 return;
1885 }
1886
1887 c->options = (MIPS_CPU_TLB |
1888 MIPS_CPU_4KEX |
1889 MIPS_CPU_COUNTER |
1890 MIPS_CPU_DIVEC |
1891 MIPS_CPU_WATCH |
1892 MIPS_CPU_EJTAG |
1893 MIPS_CPU_LLSC);
1894
1895 switch (c->processor_id & PRID_IMP_MASK) {
1896 case PRID_IMP_NETLOGIC_XLP2XX:
1897 case PRID_IMP_NETLOGIC_XLP9XX:
1898 case PRID_IMP_NETLOGIC_XLP5XX:
1899 c->cputype = CPU_XLP;
1900 __cpu_name[cpu] = "Broadcom XLPII";
1901 break;
1902
1903 case PRID_IMP_NETLOGIC_XLP8XX:
1904 case PRID_IMP_NETLOGIC_XLP3XX:
1905 c->cputype = CPU_XLP;
1906 __cpu_name[cpu] = "Netlogic XLP";
1907 break;
1908
1909 case PRID_IMP_NETLOGIC_XLR732:
1910 case PRID_IMP_NETLOGIC_XLR716:
1911 case PRID_IMP_NETLOGIC_XLR532:
1912 case PRID_IMP_NETLOGIC_XLR308:
1913 case PRID_IMP_NETLOGIC_XLR532C:
1914 case PRID_IMP_NETLOGIC_XLR516C:
1915 case PRID_IMP_NETLOGIC_XLR508C:
1916 case PRID_IMP_NETLOGIC_XLR308C:
1917 c->cputype = CPU_XLR;
1918 __cpu_name[cpu] = "Netlogic XLR";
1919 break;
1920
1921 case PRID_IMP_NETLOGIC_XLS608:
1922 case PRID_IMP_NETLOGIC_XLS408:
1923 case PRID_IMP_NETLOGIC_XLS404:
1924 case PRID_IMP_NETLOGIC_XLS208:
1925 case PRID_IMP_NETLOGIC_XLS204:
1926 case PRID_IMP_NETLOGIC_XLS108:
1927 case PRID_IMP_NETLOGIC_XLS104:
1928 case PRID_IMP_NETLOGIC_XLS616B:
1929 case PRID_IMP_NETLOGIC_XLS608B:
1930 case PRID_IMP_NETLOGIC_XLS416B:
1931 case PRID_IMP_NETLOGIC_XLS412B:
1932 case PRID_IMP_NETLOGIC_XLS408B:
1933 case PRID_IMP_NETLOGIC_XLS404B:
1934 c->cputype = CPU_XLR;
1935 __cpu_name[cpu] = "Netlogic XLS";
1936 break;
1937
1938 default:
1939 pr_info("Unknown Netlogic chip id [%02x]!\n",
1940 c->processor_id);
1941 c->cputype = CPU_XLR;
1942 break;
1943 }
1944
1945 if (c->cputype == CPU_XLP) {
1946 set_isa(c, MIPS_CPU_ISA_M64R2);
1947 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1948 /* This will be updated again after all threads are woken up */
1949 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1950 } else {
1951 set_isa(c, MIPS_CPU_ISA_M64R1);
1952 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1953 }
1954 c->kscratch_mask = 0xf;
1955}
1956
1957#ifdef CONFIG_64BIT
1958/* For use by uaccess.h */
1959u64 __ua_limit;
1960EXPORT_SYMBOL(__ua_limit);
1961#endif
1962
1963const char *__cpu_name[NR_CPUS];
1964const char *__elf_platform;
1965
1966void cpu_probe(void)
1967{
1968 struct cpuinfo_mips *c = ¤t_cpu_data;
1969 unsigned int cpu = smp_processor_id();
1970
1971 /*
1972 * Set a default elf platform, cpu probe may later
1973 * overwrite it with a more precise value
1974 */
1975 set_elf_platform(cpu, "mips");
1976
1977 c->processor_id = PRID_IMP_UNKNOWN;
1978 c->fpu_id = FPIR_IMP_NONE;
1979 c->cputype = CPU_UNKNOWN;
1980 c->writecombine = _CACHE_UNCACHED;
1981
1982 c->fpu_csr31 = FPU_CSR_RN;
1983 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1984
1985 c->processor_id = read_c0_prid();
1986 switch (c->processor_id & PRID_COMP_MASK) {
1987 case PRID_COMP_LEGACY:
1988 cpu_probe_legacy(c, cpu);
1989 break;
1990 case PRID_COMP_MIPS:
1991 cpu_probe_mips(c, cpu);
1992 break;
1993 case PRID_COMP_ALCHEMY:
1994 cpu_probe_alchemy(c, cpu);
1995 break;
1996 case PRID_COMP_SIBYTE:
1997 cpu_probe_sibyte(c, cpu);
1998 break;
1999 case PRID_COMP_BROADCOM:
2000 cpu_probe_broadcom(c, cpu);
2001 break;
2002 case PRID_COMP_SANDCRAFT:
2003 cpu_probe_sandcraft(c, cpu);
2004 break;
2005 case PRID_COMP_NXP:
2006 cpu_probe_nxp(c, cpu);
2007 break;
2008 case PRID_COMP_CAVIUM:
2009 cpu_probe_cavium(c, cpu);
2010 break;
2011 case PRID_COMP_LOONGSON:
2012 cpu_probe_loongson(c, cpu);
2013 break;
2014 case PRID_COMP_INGENIC_D0:
2015 case PRID_COMP_INGENIC_D1:
2016 case PRID_COMP_INGENIC_E1:
2017 cpu_probe_ingenic(c, cpu);
2018 break;
2019 case PRID_COMP_NETLOGIC:
2020 cpu_probe_netlogic(c, cpu);
2021 break;
2022 }
2023
2024 BUG_ON(!__cpu_name[cpu]);
2025 BUG_ON(c->cputype == CPU_UNKNOWN);
2026
2027 /*
2028 * Platform code can force the cpu type to optimize code
2029 * generation. In that case be sure the cpu type is correctly
2030 * manually setup otherwise it could trigger some nasty bugs.
2031 */
2032 BUG_ON(current_cpu_type() != c->cputype);
2033
2034 if (cpu_has_rixi) {
2035 /* Enable the RIXI exceptions */
2036 set_c0_pagegrain(PG_IEC);
2037 back_to_back_c0_hazard();
2038 /* Verify the IEC bit is set */
2039 if (read_c0_pagegrain() & PG_IEC)
2040 c->options |= MIPS_CPU_RIXIEX;
2041 }
2042
2043 if (mips_fpu_disabled)
2044 c->options &= ~MIPS_CPU_FPU;
2045
2046 if (mips_dsp_disabled)
2047 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
2048
2049 if (mips_htw_disabled) {
2050 c->options &= ~MIPS_CPU_HTW;
2051 write_c0_pwctl(read_c0_pwctl() &
2052 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
2053 }
2054
2055 if (c->options & MIPS_CPU_FPU)
2056 cpu_set_fpu_opts(c);
2057 else
2058 cpu_set_nofpu_opts(c);
2059
2060 if (cpu_has_bp_ghist)
2061 write_c0_r10k_diag(read_c0_r10k_diag() |
2062 R10K_DIAG_E_GHIST);
2063
2064 if (cpu_has_mips_r2_r6) {
2065 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
2066 /* R2 has Performance Counter Interrupt indicator */
2067 c->options |= MIPS_CPU_PCI;
2068 }
2069 else
2070 c->srsets = 1;
2071
2072 if (cpu_has_mips_r6)
2073 elf_hwcap |= HWCAP_MIPS_R6;
2074
2075 if (cpu_has_msa) {
2076 c->msa_id = cpu_get_msa_id();
2077 WARN(c->msa_id & MSA_IR_WRPF,
2078 "Vector register partitioning unimplemented!");
2079 elf_hwcap |= HWCAP_MIPS_MSA;
2080 }
2081
2082 if (cpu_has_vz)
2083 cpu_probe_vz(c);
2084
2085 cpu_probe_vmbits(c);
2086
2087#ifdef CONFIG_64BIT
2088 if (cpu == 0)
2089 __ua_limit = ~((1ull << cpu_vmbits) - 1);
2090#endif
2091}
2092
2093void cpu_report(void)
2094{
2095 struct cpuinfo_mips *c = ¤t_cpu_data;
2096
2097 pr_info("CPU%d revision is: %08x (%s)\n",
2098 smp_processor_id(), c->processor_id, cpu_name_string());
2099 if (c->options & MIPS_CPU_FPU)
2100 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
2101 if (cpu_has_msa)
2102 pr_info("MSA revision is: %08x\n", c->msa_id);
2103}
2104
2105void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster)
2106{
2107 /* Ensure the core number fits in the field */
2108 WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >>
2109 MIPS_GLOBALNUMBER_CLUSTER_SHF));
2110
2111 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER;
2112 cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF;
2113}
2114
2115void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core)
2116{
2117 /* Ensure the core number fits in the field */
2118 WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF));
2119
2120 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE;
2121 cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF;
2122}
2123
2124void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe)
2125{
2126 /* Ensure the VP(E) ID fits in the field */
2127 WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF));
2128
2129 /* Ensure we're not using VP(E)s without support */
2130 WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) &&
2131 !IS_ENABLED(CONFIG_CPU_MIPSR6));
2132
2133 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP;
2134 cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF;
2135}
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Processor capabilities determination functions.
4 *
5 * Copyright (C) xxxx the Anonymous
6 * Copyright (C) 1994 - 2006 Ralf Baechle
7 * Copyright (C) 2003, 2004 Maciej W. Rozycki
8 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
9 */
10#include <linux/init.h>
11#include <linux/kernel.h>
12#include <linux/ptrace.h>
13#include <linux/smp.h>
14#include <linux/stddef.h>
15#include <linux/export.h>
16
17#include <asm/bugs.h>
18#include <asm/cpu.h>
19#include <asm/cpu-features.h>
20#include <asm/cpu-type.h>
21#include <asm/fpu.h>
22#include <asm/mipsregs.h>
23#include <asm/mipsmtregs.h>
24#include <asm/msa.h>
25#include <asm/watch.h>
26#include <asm/elf.h>
27#include <asm/pgtable-bits.h>
28#include <asm/spram.h>
29#include <asm/traps.h>
30#include <linux/uaccess.h>
31
32#include "fpu-probe.h"
33
34#include <asm/mach-loongson64/cpucfg-emul.h>
35
36/* Hardware capabilities */
37unsigned int elf_hwcap __read_mostly;
38EXPORT_SYMBOL_GPL(elf_hwcap);
39
40static inline unsigned long cpu_get_msa_id(void)
41{
42 unsigned long status, msa_id;
43
44 status = read_c0_status();
45 __enable_fpu(FPU_64BIT);
46 enable_msa();
47 msa_id = read_msa_ir();
48 disable_msa();
49 write_c0_status(status);
50 return msa_id;
51}
52
53static int mips_dsp_disabled;
54
55static int __init dsp_disable(char *s)
56{
57 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
58 mips_dsp_disabled = 1;
59
60 return 1;
61}
62
63__setup("nodsp", dsp_disable);
64
65static int mips_htw_disabled;
66
67static int __init htw_disable(char *s)
68{
69 mips_htw_disabled = 1;
70 cpu_data[0].options &= ~MIPS_CPU_HTW;
71 write_c0_pwctl(read_c0_pwctl() &
72 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
73
74 return 1;
75}
76
77__setup("nohtw", htw_disable);
78
79static int mips_ftlb_disabled;
80static int mips_has_ftlb_configured;
81
82enum ftlb_flags {
83 FTLB_EN = 1 << 0,
84 FTLB_SET_PROB = 1 << 1,
85};
86
87static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags);
88
89static int __init ftlb_disable(char *s)
90{
91 unsigned int config4, mmuextdef;
92
93 /*
94 * If the core hasn't done any FTLB configuration, there is nothing
95 * for us to do here.
96 */
97 if (!mips_has_ftlb_configured)
98 return 1;
99
100 /* Disable it in the boot cpu */
101 if (set_ftlb_enable(&cpu_data[0], 0)) {
102 pr_warn("Can't turn FTLB off\n");
103 return 1;
104 }
105
106 config4 = read_c0_config4();
107
108 /* Check that FTLB has been disabled */
109 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
110 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
111 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
112 /* This should never happen */
113 pr_warn("FTLB could not be disabled!\n");
114 return 1;
115 }
116
117 mips_ftlb_disabled = 1;
118 mips_has_ftlb_configured = 0;
119
120 /*
121 * noftlb is mainly used for debug purposes so print
122 * an informative message instead of using pr_debug()
123 */
124 pr_info("FTLB has been disabled\n");
125
126 /*
127 * Some of these bits are duplicated in the decode_config4.
128 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
129 * once FTLB has been disabled so undo what decode_config4 did.
130 */
131 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
132 cpu_data[0].tlbsizeftlbsets;
133 cpu_data[0].tlbsizeftlbsets = 0;
134 cpu_data[0].tlbsizeftlbways = 0;
135
136 return 1;
137}
138
139__setup("noftlb", ftlb_disable);
140
141/*
142 * Check if the CPU has per tc perf counters
143 */
144static inline void cpu_set_mt_per_tc_perf(struct cpuinfo_mips *c)
145{
146 if (read_c0_config7() & MTI_CONF7_PTC)
147 c->options |= MIPS_CPU_MT_PER_TC_PERF_COUNTERS;
148}
149
150static inline void check_errata(void)
151{
152 struct cpuinfo_mips *c = ¤t_cpu_data;
153
154 switch (current_cpu_type()) {
155 case CPU_34K:
156 /*
157 * Erratum "RPS May Cause Incorrect Instruction Execution"
158 * This code only handles VPE0, any SMP/RTOS code
159 * making use of VPE1 will be responsible for that VPE.
160 */
161 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
162 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
163 break;
164 default:
165 break;
166 }
167}
168
169void __init check_bugs32(void)
170{
171 check_errata();
172}
173
174/*
175 * Probe whether cpu has config register by trying to play with
176 * alternate cache bit and see whether it matters.
177 * It's used by cpu_probe to distinguish between R3000A and R3081.
178 */
179static inline int cpu_has_confreg(void)
180{
181#ifdef CONFIG_CPU_R3000
182 extern unsigned long r3k_cache_size(unsigned long);
183 unsigned long size1, size2;
184 unsigned long cfg = read_c0_conf();
185
186 size1 = r3k_cache_size(ST0_ISC);
187 write_c0_conf(cfg ^ R30XX_CONF_AC);
188 size2 = r3k_cache_size(ST0_ISC);
189 write_c0_conf(cfg);
190 return size1 != size2;
191#else
192 return 0;
193#endif
194}
195
196static inline void set_elf_platform(int cpu, const char *plat)
197{
198 if (cpu == 0)
199 __elf_platform = plat;
200}
201
202static inline void set_elf_base_platform(const char *plat)
203{
204 if (__elf_base_platform == NULL) {
205 __elf_base_platform = plat;
206 }
207}
208
209static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
210{
211#ifdef __NEED_VMBITS_PROBE
212 write_c0_entryhi(0x3fffffffffffe000ULL);
213 back_to_back_c0_hazard();
214 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
215#endif
216}
217
218static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
219{
220 switch (isa) {
221 case MIPS_CPU_ISA_M64R5:
222 c->isa_level |= MIPS_CPU_ISA_M32R5 | MIPS_CPU_ISA_M64R5;
223 set_elf_base_platform("mips64r5");
224 fallthrough;
225 case MIPS_CPU_ISA_M64R2:
226 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
227 set_elf_base_platform("mips64r2");
228 fallthrough;
229 case MIPS_CPU_ISA_M64R1:
230 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
231 set_elf_base_platform("mips64");
232 fallthrough;
233 case MIPS_CPU_ISA_V:
234 c->isa_level |= MIPS_CPU_ISA_V;
235 set_elf_base_platform("mips5");
236 fallthrough;
237 case MIPS_CPU_ISA_IV:
238 c->isa_level |= MIPS_CPU_ISA_IV;
239 set_elf_base_platform("mips4");
240 fallthrough;
241 case MIPS_CPU_ISA_III:
242 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
243 set_elf_base_platform("mips3");
244 break;
245
246 /* R6 incompatible with everything else */
247 case MIPS_CPU_ISA_M64R6:
248 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
249 set_elf_base_platform("mips64r6");
250 fallthrough;
251 case MIPS_CPU_ISA_M32R6:
252 c->isa_level |= MIPS_CPU_ISA_M32R6;
253 set_elf_base_platform("mips32r6");
254 /* Break here so we don't add incompatible ISAs */
255 break;
256 case MIPS_CPU_ISA_M32R5:
257 c->isa_level |= MIPS_CPU_ISA_M32R5;
258 set_elf_base_platform("mips32r5");
259 fallthrough;
260 case MIPS_CPU_ISA_M32R2:
261 c->isa_level |= MIPS_CPU_ISA_M32R2;
262 set_elf_base_platform("mips32r2");
263 fallthrough;
264 case MIPS_CPU_ISA_M32R1:
265 c->isa_level |= MIPS_CPU_ISA_M32R1;
266 set_elf_base_platform("mips32");
267 fallthrough;
268 case MIPS_CPU_ISA_II:
269 c->isa_level |= MIPS_CPU_ISA_II;
270 set_elf_base_platform("mips2");
271 break;
272 }
273}
274
275static char unknown_isa[] = KERN_ERR \
276 "Unsupported ISA type, c0.config0: %d.";
277
278static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
279{
280
281 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
282
283 /*
284 * 0 = All TLBWR instructions go to FTLB
285 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
286 * FTLB and 1 goes to the VTLB.
287 * 2 = 7:1: As above with 7:1 ratio.
288 * 3 = 3:1: As above with 3:1 ratio.
289 *
290 * Use the linear midpoint as the probability threshold.
291 */
292 if (probability >= 12)
293 return 1;
294 else if (probability >= 6)
295 return 2;
296 else
297 /*
298 * So FTLB is less than 4 times bigger than VTLB.
299 * A 3:1 ratio can still be useful though.
300 */
301 return 3;
302}
303
304static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
305{
306 unsigned int config;
307
308 /* It's implementation dependent how the FTLB can be enabled */
309 switch (c->cputype) {
310 case CPU_PROAPTIV:
311 case CPU_P5600:
312 case CPU_P6600:
313 /* proAptiv & related cores use Config6 to enable the FTLB */
314 config = read_c0_config6();
315
316 if (flags & FTLB_EN)
317 config |= MTI_CONF6_FTLBEN;
318 else
319 config &= ~MTI_CONF6_FTLBEN;
320
321 if (flags & FTLB_SET_PROB) {
322 config &= ~(3 << MTI_CONF6_FTLBP_SHIFT);
323 config |= calculate_ftlb_probability(c)
324 << MTI_CONF6_FTLBP_SHIFT;
325 }
326
327 write_c0_config6(config);
328 back_to_back_c0_hazard();
329 break;
330 case CPU_I6400:
331 case CPU_I6500:
332 /* There's no way to disable the FTLB */
333 if (!(flags & FTLB_EN))
334 return 1;
335 return 0;
336 case CPU_LOONGSON64:
337 /* Flush ITLB, DTLB, VTLB and FTLB */
338 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
339 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
340 /* Loongson-3 cores use Config6 to enable the FTLB */
341 config = read_c0_config6();
342 if (flags & FTLB_EN)
343 /* Enable FTLB */
344 write_c0_config6(config & ~LOONGSON_CONF6_FTLBDIS);
345 else
346 /* Disable FTLB */
347 write_c0_config6(config | LOONGSON_CONF6_FTLBDIS);
348 break;
349 default:
350 return 1;
351 }
352
353 return 0;
354}
355
356static int mm_config(struct cpuinfo_mips *c)
357{
358 unsigned int config0, update, mm;
359
360 config0 = read_c0_config();
361 mm = config0 & MIPS_CONF_MM;
362
363 /*
364 * It's implementation dependent what type of write-merge is supported
365 * and whether it can be enabled/disabled. If it is settable lets make
366 * the merging allowed by default. Some platforms might have
367 * write-through caching unsupported. In this case just ignore the
368 * CP0.Config.MM bit field value.
369 */
370 switch (c->cputype) {
371 case CPU_24K:
372 case CPU_34K:
373 case CPU_74K:
374 case CPU_P5600:
375 case CPU_P6600:
376 c->options |= MIPS_CPU_MM_FULL;
377 update = MIPS_CONF_MM_FULL;
378 break;
379 case CPU_1004K:
380 case CPU_1074K:
381 case CPU_INTERAPTIV:
382 case CPU_PROAPTIV:
383 mm = 0;
384 fallthrough;
385 default:
386 update = 0;
387 break;
388 }
389
390 if (update) {
391 config0 = (config0 & ~MIPS_CONF_MM) | update;
392 write_c0_config(config0);
393 } else if (mm == MIPS_CONF_MM_SYSAD) {
394 c->options |= MIPS_CPU_MM_SYSAD;
395 } else if (mm == MIPS_CONF_MM_FULL) {
396 c->options |= MIPS_CPU_MM_FULL;
397 }
398
399 return 0;
400}
401
402static inline unsigned int decode_config0(struct cpuinfo_mips *c)
403{
404 unsigned int config0;
405 int isa, mt;
406
407 config0 = read_c0_config();
408
409 /*
410 * Look for Standard TLB or Dual VTLB and FTLB
411 */
412 mt = config0 & MIPS_CONF_MT;
413 if (mt == MIPS_CONF_MT_TLB)
414 c->options |= MIPS_CPU_TLB;
415 else if (mt == MIPS_CONF_MT_FTLB)
416 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
417
418 isa = (config0 & MIPS_CONF_AT) >> 13;
419 switch (isa) {
420 case 0:
421 switch ((config0 & MIPS_CONF_AR) >> 10) {
422 case 0:
423 set_isa(c, MIPS_CPU_ISA_M32R1);
424 break;
425 case 1:
426 set_isa(c, MIPS_CPU_ISA_M32R2);
427 break;
428 case 2:
429 set_isa(c, MIPS_CPU_ISA_M32R6);
430 break;
431 default:
432 goto unknown;
433 }
434 break;
435 case 2:
436 switch ((config0 & MIPS_CONF_AR) >> 10) {
437 case 0:
438 set_isa(c, MIPS_CPU_ISA_M64R1);
439 break;
440 case 1:
441 set_isa(c, MIPS_CPU_ISA_M64R2);
442 break;
443 case 2:
444 set_isa(c, MIPS_CPU_ISA_M64R6);
445 break;
446 default:
447 goto unknown;
448 }
449 break;
450 default:
451 goto unknown;
452 }
453
454 return config0 & MIPS_CONF_M;
455
456unknown:
457 panic(unknown_isa, config0);
458}
459
460static inline unsigned int decode_config1(struct cpuinfo_mips *c)
461{
462 unsigned int config1;
463
464 config1 = read_c0_config1();
465
466 if (config1 & MIPS_CONF1_MD)
467 c->ases |= MIPS_ASE_MDMX;
468 if (config1 & MIPS_CONF1_PC)
469 c->options |= MIPS_CPU_PERF;
470 if (config1 & MIPS_CONF1_WR)
471 c->options |= MIPS_CPU_WATCH;
472 if (config1 & MIPS_CONF1_CA)
473 c->ases |= MIPS_ASE_MIPS16;
474 if (config1 & MIPS_CONF1_EP)
475 c->options |= MIPS_CPU_EJTAG;
476 if (config1 & MIPS_CONF1_FP) {
477 c->options |= MIPS_CPU_FPU;
478 c->options |= MIPS_CPU_32FPR;
479 }
480 if (cpu_has_tlb) {
481 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
482 c->tlbsizevtlb = c->tlbsize;
483 c->tlbsizeftlbsets = 0;
484 }
485
486 return config1 & MIPS_CONF_M;
487}
488
489static inline unsigned int decode_config2(struct cpuinfo_mips *c)
490{
491 unsigned int config2;
492
493 config2 = read_c0_config2();
494
495 if (config2 & MIPS_CONF2_SL)
496 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
497
498 return config2 & MIPS_CONF_M;
499}
500
501static inline unsigned int decode_config3(struct cpuinfo_mips *c)
502{
503 unsigned int config3;
504
505 config3 = read_c0_config3();
506
507 if (config3 & MIPS_CONF3_SM) {
508 c->ases |= MIPS_ASE_SMARTMIPS;
509 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;
510 }
511 if (config3 & MIPS_CONF3_RXI)
512 c->options |= MIPS_CPU_RIXI;
513 if (config3 & MIPS_CONF3_CTXTC)
514 c->options |= MIPS_CPU_CTXTC;
515 if (config3 & MIPS_CONF3_DSP)
516 c->ases |= MIPS_ASE_DSP;
517 if (config3 & MIPS_CONF3_DSP2P) {
518 c->ases |= MIPS_ASE_DSP2P;
519 if (cpu_has_mips_r6)
520 c->ases |= MIPS_ASE_DSP3;
521 }
522 if (config3 & MIPS_CONF3_VINT)
523 c->options |= MIPS_CPU_VINT;
524 if (config3 & MIPS_CONF3_VEIC)
525 c->options |= MIPS_CPU_VEIC;
526 if (config3 & MIPS_CONF3_LPA)
527 c->options |= MIPS_CPU_LPA;
528 if (config3 & MIPS_CONF3_MT)
529 c->ases |= MIPS_ASE_MIPSMT;
530 if (config3 & MIPS_CONF3_ULRI)
531 c->options |= MIPS_CPU_ULRI;
532 if (config3 & MIPS_CONF3_ISA)
533 c->options |= MIPS_CPU_MICROMIPS;
534 if (config3 & MIPS_CONF3_VZ)
535 c->ases |= MIPS_ASE_VZ;
536 if (config3 & MIPS_CONF3_SC)
537 c->options |= MIPS_CPU_SEGMENTS;
538 if (config3 & MIPS_CONF3_BI)
539 c->options |= MIPS_CPU_BADINSTR;
540 if (config3 & MIPS_CONF3_BP)
541 c->options |= MIPS_CPU_BADINSTRP;
542 if (config3 & MIPS_CONF3_MSA)
543 c->ases |= MIPS_ASE_MSA;
544 if (config3 & MIPS_CONF3_PW) {
545 c->htw_seq = 0;
546 c->options |= MIPS_CPU_HTW;
547 }
548 if (config3 & MIPS_CONF3_CDMM)
549 c->options |= MIPS_CPU_CDMM;
550 if (config3 & MIPS_CONF3_SP)
551 c->options |= MIPS_CPU_SP;
552
553 return config3 & MIPS_CONF_M;
554}
555
556static inline unsigned int decode_config4(struct cpuinfo_mips *c)
557{
558 unsigned int config4;
559 unsigned int newcf4;
560 unsigned int mmuextdef;
561 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
562 unsigned long asid_mask;
563
564 config4 = read_c0_config4();
565
566 if (cpu_has_tlb) {
567 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
568 c->options |= MIPS_CPU_TLBINV;
569
570 /*
571 * R6 has dropped the MMUExtDef field from config4.
572 * On R6 the fields always describe the FTLB, and only if it is
573 * present according to Config.MT.
574 */
575 if (!cpu_has_mips_r6)
576 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
577 else if (cpu_has_ftlb)
578 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
579 else
580 mmuextdef = 0;
581
582 switch (mmuextdef) {
583 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
584 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
585 c->tlbsizevtlb = c->tlbsize;
586 break;
587 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
588 c->tlbsizevtlb +=
589 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
590 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
591 c->tlbsize = c->tlbsizevtlb;
592 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
593 fallthrough;
594 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
595 if (mips_ftlb_disabled)
596 break;
597 newcf4 = (config4 & ~ftlb_page) |
598 (page_size_ftlb(mmuextdef) <<
599 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
600 write_c0_config4(newcf4);
601 back_to_back_c0_hazard();
602 config4 = read_c0_config4();
603 if (config4 != newcf4) {
604 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
605 PAGE_SIZE, config4);
606 /* Switch FTLB off */
607 set_ftlb_enable(c, 0);
608 mips_ftlb_disabled = 1;
609 break;
610 }
611 c->tlbsizeftlbsets = 1 <<
612 ((config4 & MIPS_CONF4_FTLBSETS) >>
613 MIPS_CONF4_FTLBSETS_SHIFT);
614 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
615 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
616 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
617 mips_has_ftlb_configured = 1;
618 break;
619 }
620 }
621
622 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
623 >> MIPS_CONF4_KSCREXIST_SHIFT;
624
625 asid_mask = MIPS_ENTRYHI_ASID;
626 if (config4 & MIPS_CONF4_AE)
627 asid_mask |= MIPS_ENTRYHI_ASIDX;
628 set_cpu_asid_mask(c, asid_mask);
629
630 /*
631 * Warn if the computed ASID mask doesn't match the mask the kernel
632 * is built for. This may indicate either a serious problem or an
633 * easy optimisation opportunity, but either way should be addressed.
634 */
635 WARN_ON(asid_mask != cpu_asid_mask(c));
636
637 return config4 & MIPS_CONF_M;
638}
639
640static inline unsigned int decode_config5(struct cpuinfo_mips *c)
641{
642 unsigned int config5, max_mmid_width;
643 unsigned long asid_mask;
644
645 config5 = read_c0_config5();
646 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
647
648 if (cpu_has_mips_r6) {
649 if (!__builtin_constant_p(cpu_has_mmid) || cpu_has_mmid)
650 config5 |= MIPS_CONF5_MI;
651 else
652 config5 &= ~MIPS_CONF5_MI;
653 }
654
655 write_c0_config5(config5);
656
657 if (config5 & MIPS_CONF5_EVA)
658 c->options |= MIPS_CPU_EVA;
659 if (config5 & MIPS_CONF5_MRP)
660 c->options |= MIPS_CPU_MAAR;
661 if (config5 & MIPS_CONF5_LLB)
662 c->options |= MIPS_CPU_RW_LLB;
663 if (config5 & MIPS_CONF5_MVH)
664 c->options |= MIPS_CPU_MVH;
665 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
666 c->options |= MIPS_CPU_VP;
667 if (config5 & MIPS_CONF5_CA2)
668 c->ases |= MIPS_ASE_MIPS16E2;
669
670 if (config5 & MIPS_CONF5_CRCP)
671 elf_hwcap |= HWCAP_MIPS_CRC32;
672
673 if (cpu_has_mips_r6) {
674 /* Ensure the write to config5 above takes effect */
675 back_to_back_c0_hazard();
676
677 /* Check whether we successfully enabled MMID support */
678 config5 = read_c0_config5();
679 if (config5 & MIPS_CONF5_MI)
680 c->options |= MIPS_CPU_MMID;
681
682 /*
683 * Warn if we've hardcoded cpu_has_mmid to a value unsuitable
684 * for the CPU we're running on, or if CPUs in an SMP system
685 * have inconsistent MMID support.
686 */
687 WARN_ON(!!cpu_has_mmid != !!(config5 & MIPS_CONF5_MI));
688
689 if (cpu_has_mmid) {
690 write_c0_memorymapid(~0ul);
691 back_to_back_c0_hazard();
692 asid_mask = read_c0_memorymapid();
693
694 /*
695 * We maintain a bitmap to track MMID allocation, and
696 * need a sensible upper bound on the size of that
697 * bitmap. The initial CPU with MMID support (I6500)
698 * supports 16 bit MMIDs, which gives us an 8KiB
699 * bitmap. The architecture recommends that hardware
700 * support 32 bit MMIDs, which would give us a 512MiB
701 * bitmap - that's too big in most cases.
702 *
703 * Cap MMID width at 16 bits for now & we can revisit
704 * this if & when hardware supports anything wider.
705 */
706 max_mmid_width = 16;
707 if (asid_mask > GENMASK(max_mmid_width - 1, 0)) {
708 pr_info("Capping MMID width at %d bits",
709 max_mmid_width);
710 asid_mask = GENMASK(max_mmid_width - 1, 0);
711 }
712
713 set_cpu_asid_mask(c, asid_mask);
714 }
715 }
716
717 return config5 & MIPS_CONF_M;
718}
719
720static void decode_configs(struct cpuinfo_mips *c)
721{
722 int ok;
723
724 /* MIPS32 or MIPS64 compliant CPU. */
725 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
726 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
727
728 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
729
730 /* Enable FTLB if present and not disabled */
731 set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN);
732
733 ok = decode_config0(c); /* Read Config registers. */
734 BUG_ON(!ok); /* Arch spec violation! */
735 if (ok)
736 ok = decode_config1(c);
737 if (ok)
738 ok = decode_config2(c);
739 if (ok)
740 ok = decode_config3(c);
741 if (ok)
742 ok = decode_config4(c);
743 if (ok)
744 ok = decode_config5(c);
745
746 /* Probe the EBase.WG bit */
747 if (cpu_has_mips_r2_r6) {
748 u64 ebase;
749 unsigned int status;
750
751 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */
752 ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
753 : (s32)read_c0_ebase();
754 if (ebase & MIPS_EBASE_WG) {
755 /* WG bit already set, we can avoid the clumsy probe */
756 c->options |= MIPS_CPU_EBASE_WG;
757 } else {
758 /* Its UNDEFINED to change EBase while BEV=0 */
759 status = read_c0_status();
760 write_c0_status(status | ST0_BEV);
761 irq_enable_hazard();
762 /*
763 * On pre-r6 cores, this may well clobber the upper bits
764 * of EBase. This is hard to avoid without potentially
765 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit.
766 */
767 if (cpu_has_mips64r6)
768 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
769 else
770 write_c0_ebase(ebase | MIPS_EBASE_WG);
771 back_to_back_c0_hazard();
772 /* Restore BEV */
773 write_c0_status(status);
774 if (read_c0_ebase() & MIPS_EBASE_WG) {
775 c->options |= MIPS_CPU_EBASE_WG;
776 write_c0_ebase(ebase);
777 }
778 }
779 }
780
781 /* configure the FTLB write probability */
782 set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB);
783
784 mips_probe_watch_registers(c);
785
786#ifndef CONFIG_MIPS_CPS
787 if (cpu_has_mips_r2_r6) {
788 unsigned int core;
789
790 core = get_ebase_cpunum();
791 if (cpu_has_mipsmt)
792 core >>= fls(core_nvpes()) - 1;
793 cpu_set_core(c, core);
794 }
795#endif
796}
797
798/*
799 * Probe for certain guest capabilities by writing config bits and reading back.
800 * Finally write back the original value.
801 */
802#define probe_gc0_config(name, maxconf, bits) \
803do { \
804 unsigned int tmp; \
805 tmp = read_gc0_##name(); \
806 write_gc0_##name(tmp | (bits)); \
807 back_to_back_c0_hazard(); \
808 maxconf = read_gc0_##name(); \
809 write_gc0_##name(tmp); \
810} while (0)
811
812/*
813 * Probe for dynamic guest capabilities by changing certain config bits and
814 * reading back to see if they change. Finally write back the original value.
815 */
816#define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \
817do { \
818 maxconf = read_gc0_##name(); \
819 write_gc0_##name(maxconf ^ (bits)); \
820 back_to_back_c0_hazard(); \
821 dynconf = maxconf ^ read_gc0_##name(); \
822 write_gc0_##name(maxconf); \
823 maxconf |= dynconf; \
824} while (0)
825
826static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c)
827{
828 unsigned int config0;
829
830 probe_gc0_config(config, config0, MIPS_CONF_M);
831
832 if (config0 & MIPS_CONF_M)
833 c->guest.conf |= BIT(1);
834 return config0 & MIPS_CONF_M;
835}
836
837static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c)
838{
839 unsigned int config1, config1_dyn;
840
841 probe_gc0_config_dyn(config1, config1, config1_dyn,
842 MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR |
843 MIPS_CONF1_FP);
844
845 if (config1 & MIPS_CONF1_FP)
846 c->guest.options |= MIPS_CPU_FPU;
847 if (config1_dyn & MIPS_CONF1_FP)
848 c->guest.options_dyn |= MIPS_CPU_FPU;
849
850 if (config1 & MIPS_CONF1_WR)
851 c->guest.options |= MIPS_CPU_WATCH;
852 if (config1_dyn & MIPS_CONF1_WR)
853 c->guest.options_dyn |= MIPS_CPU_WATCH;
854
855 if (config1 & MIPS_CONF1_PC)
856 c->guest.options |= MIPS_CPU_PERF;
857 if (config1_dyn & MIPS_CONF1_PC)
858 c->guest.options_dyn |= MIPS_CPU_PERF;
859
860 if (config1 & MIPS_CONF_M)
861 c->guest.conf |= BIT(2);
862 return config1 & MIPS_CONF_M;
863}
864
865static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c)
866{
867 unsigned int config2;
868
869 probe_gc0_config(config2, config2, MIPS_CONF_M);
870
871 if (config2 & MIPS_CONF_M)
872 c->guest.conf |= BIT(3);
873 return config2 & MIPS_CONF_M;
874}
875
876static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c)
877{
878 unsigned int config3, config3_dyn;
879
880 probe_gc0_config_dyn(config3, config3, config3_dyn,
881 MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI |
882 MIPS_CONF3_CTXTC);
883
884 if (config3 & MIPS_CONF3_CTXTC)
885 c->guest.options |= MIPS_CPU_CTXTC;
886 if (config3_dyn & MIPS_CONF3_CTXTC)
887 c->guest.options_dyn |= MIPS_CPU_CTXTC;
888
889 if (config3 & MIPS_CONF3_PW)
890 c->guest.options |= MIPS_CPU_HTW;
891
892 if (config3 & MIPS_CONF3_ULRI)
893 c->guest.options |= MIPS_CPU_ULRI;
894
895 if (config3 & MIPS_CONF3_SC)
896 c->guest.options |= MIPS_CPU_SEGMENTS;
897
898 if (config3 & MIPS_CONF3_BI)
899 c->guest.options |= MIPS_CPU_BADINSTR;
900 if (config3 & MIPS_CONF3_BP)
901 c->guest.options |= MIPS_CPU_BADINSTRP;
902
903 if (config3 & MIPS_CONF3_MSA)
904 c->guest.ases |= MIPS_ASE_MSA;
905 if (config3_dyn & MIPS_CONF3_MSA)
906 c->guest.ases_dyn |= MIPS_ASE_MSA;
907
908 if (config3 & MIPS_CONF_M)
909 c->guest.conf |= BIT(4);
910 return config3 & MIPS_CONF_M;
911}
912
913static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c)
914{
915 unsigned int config4;
916
917 probe_gc0_config(config4, config4,
918 MIPS_CONF_M | MIPS_CONF4_KSCREXIST);
919
920 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
921 >> MIPS_CONF4_KSCREXIST_SHIFT;
922
923 if (config4 & MIPS_CONF_M)
924 c->guest.conf |= BIT(5);
925 return config4 & MIPS_CONF_M;
926}
927
928static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c)
929{
930 unsigned int config5, config5_dyn;
931
932 probe_gc0_config_dyn(config5, config5, config5_dyn,
933 MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP);
934
935 if (config5 & MIPS_CONF5_MRP)
936 c->guest.options |= MIPS_CPU_MAAR;
937 if (config5_dyn & MIPS_CONF5_MRP)
938 c->guest.options_dyn |= MIPS_CPU_MAAR;
939
940 if (config5 & MIPS_CONF5_LLB)
941 c->guest.options |= MIPS_CPU_RW_LLB;
942
943 if (config5 & MIPS_CONF5_MVH)
944 c->guest.options |= MIPS_CPU_MVH;
945
946 if (config5 & MIPS_CONF_M)
947 c->guest.conf |= BIT(6);
948 return config5 & MIPS_CONF_M;
949}
950
951static inline void decode_guest_configs(struct cpuinfo_mips *c)
952{
953 unsigned int ok;
954
955 ok = decode_guest_config0(c);
956 if (ok)
957 ok = decode_guest_config1(c);
958 if (ok)
959 ok = decode_guest_config2(c);
960 if (ok)
961 ok = decode_guest_config3(c);
962 if (ok)
963 ok = decode_guest_config4(c);
964 if (ok)
965 decode_guest_config5(c);
966}
967
968static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c)
969{
970 unsigned int guestctl0, temp;
971
972 guestctl0 = read_c0_guestctl0();
973
974 if (guestctl0 & MIPS_GCTL0_G0E)
975 c->options |= MIPS_CPU_GUESTCTL0EXT;
976 if (guestctl0 & MIPS_GCTL0_G1)
977 c->options |= MIPS_CPU_GUESTCTL1;
978 if (guestctl0 & MIPS_GCTL0_G2)
979 c->options |= MIPS_CPU_GUESTCTL2;
980 if (!(guestctl0 & MIPS_GCTL0_RAD)) {
981 c->options |= MIPS_CPU_GUESTID;
982
983 /*
984 * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0
985 * first, otherwise all data accesses will be fully virtualised
986 * as if they were performed by guest mode.
987 */
988 write_c0_guestctl1(0);
989 tlbw_use_hazard();
990
991 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG);
992 back_to_back_c0_hazard();
993 temp = read_c0_guestctl0();
994
995 if (temp & MIPS_GCTL0_DRG) {
996 write_c0_guestctl0(guestctl0);
997 c->options |= MIPS_CPU_DRG;
998 }
999 }
1000}
1001
1002static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c)
1003{
1004 if (cpu_has_guestid) {
1005 /* determine the number of bits of GuestID available */
1006 write_c0_guestctl1(MIPS_GCTL1_ID);
1007 back_to_back_c0_hazard();
1008 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID)
1009 >> MIPS_GCTL1_ID_SHIFT;
1010 write_c0_guestctl1(0);
1011 }
1012}
1013
1014static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c)
1015{
1016 /* determine the number of bits of GTOffset available */
1017 write_c0_gtoffset(0xffffffff);
1018 back_to_back_c0_hazard();
1019 c->gtoffset_mask = read_c0_gtoffset();
1020 write_c0_gtoffset(0);
1021}
1022
1023static inline void cpu_probe_vz(struct cpuinfo_mips *c)
1024{
1025 cpu_probe_guestctl0(c);
1026 if (cpu_has_guestctl1)
1027 cpu_probe_guestctl1(c);
1028
1029 cpu_probe_gtoffset(c);
1030
1031 decode_guest_configs(c);
1032}
1033
1034#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1035 | MIPS_CPU_COUNTER)
1036
1037static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1038{
1039 switch (c->processor_id & PRID_IMP_MASK) {
1040 case PRID_IMP_R2000:
1041 c->cputype = CPU_R2000;
1042 __cpu_name[cpu] = "R2000";
1043 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1044 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1045 MIPS_CPU_NOFPUEX;
1046 if (__cpu_has_fpu())
1047 c->options |= MIPS_CPU_FPU;
1048 c->tlbsize = 64;
1049 break;
1050 case PRID_IMP_R3000:
1051 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
1052 if (cpu_has_confreg()) {
1053 c->cputype = CPU_R3081E;
1054 __cpu_name[cpu] = "R3081";
1055 } else {
1056 c->cputype = CPU_R3000A;
1057 __cpu_name[cpu] = "R3000A";
1058 }
1059 } else {
1060 c->cputype = CPU_R3000;
1061 __cpu_name[cpu] = "R3000";
1062 }
1063 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1064 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1065 MIPS_CPU_NOFPUEX;
1066 if (__cpu_has_fpu())
1067 c->options |= MIPS_CPU_FPU;
1068 c->tlbsize = 64;
1069 break;
1070 case PRID_IMP_R4000:
1071 if (read_c0_config() & CONF_SC) {
1072 if ((c->processor_id & PRID_REV_MASK) >=
1073 PRID_REV_R4400) {
1074 c->cputype = CPU_R4400PC;
1075 __cpu_name[cpu] = "R4400PC";
1076 } else {
1077 c->cputype = CPU_R4000PC;
1078 __cpu_name[cpu] = "R4000PC";
1079 }
1080 } else {
1081 int cca = read_c0_config() & CONF_CM_CMASK;
1082 int mc;
1083
1084 /*
1085 * SC and MC versions can't be reliably told apart,
1086 * but only the latter support coherent caching
1087 * modes so assume the firmware has set the KSEG0
1088 * coherency attribute reasonably (if uncached, we
1089 * assume SC).
1090 */
1091 switch (cca) {
1092 case CONF_CM_CACHABLE_CE:
1093 case CONF_CM_CACHABLE_COW:
1094 case CONF_CM_CACHABLE_CUW:
1095 mc = 1;
1096 break;
1097 default:
1098 mc = 0;
1099 break;
1100 }
1101 if ((c->processor_id & PRID_REV_MASK) >=
1102 PRID_REV_R4400) {
1103 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
1104 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
1105 } else {
1106 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
1107 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
1108 }
1109 }
1110
1111 set_isa(c, MIPS_CPU_ISA_III);
1112 c->fpu_msk31 |= FPU_CSR_CONDX;
1113 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1114 MIPS_CPU_WATCH | MIPS_CPU_VCE |
1115 MIPS_CPU_LLSC;
1116 c->tlbsize = 48;
1117 break;
1118 case PRID_IMP_R4300:
1119 c->cputype = CPU_R4300;
1120 __cpu_name[cpu] = "R4300";
1121 set_isa(c, MIPS_CPU_ISA_III);
1122 c->fpu_msk31 |= FPU_CSR_CONDX;
1123 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1124 MIPS_CPU_LLSC;
1125 c->tlbsize = 32;
1126 break;
1127 case PRID_IMP_R4600:
1128 c->cputype = CPU_R4600;
1129 __cpu_name[cpu] = "R4600";
1130 set_isa(c, MIPS_CPU_ISA_III);
1131 c->fpu_msk31 |= FPU_CSR_CONDX;
1132 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1133 MIPS_CPU_LLSC;
1134 c->tlbsize = 48;
1135 break;
1136 #if 0
1137 case PRID_IMP_R4650:
1138 /*
1139 * This processor doesn't have an MMU, so it's not
1140 * "real easy" to run Linux on it. It is left purely
1141 * for documentation. Commented out because it shares
1142 * it's c0_prid id number with the TX3900.
1143 */
1144 c->cputype = CPU_R4650;
1145 __cpu_name[cpu] = "R4650";
1146 set_isa(c, MIPS_CPU_ISA_III);
1147 c->fpu_msk31 |= FPU_CSR_CONDX;
1148 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
1149 c->tlbsize = 48;
1150 break;
1151 #endif
1152 case PRID_IMP_R4700:
1153 c->cputype = CPU_R4700;
1154 __cpu_name[cpu] = "R4700";
1155 set_isa(c, MIPS_CPU_ISA_III);
1156 c->fpu_msk31 |= FPU_CSR_CONDX;
1157 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1158 MIPS_CPU_LLSC;
1159 c->tlbsize = 48;
1160 break;
1161 case PRID_IMP_TX49:
1162 c->cputype = CPU_TX49XX;
1163 __cpu_name[cpu] = "R49XX";
1164 set_isa(c, MIPS_CPU_ISA_III);
1165 c->fpu_msk31 |= FPU_CSR_CONDX;
1166 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1167 if (!(c->processor_id & 0x08))
1168 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1169 c->tlbsize = 48;
1170 break;
1171 case PRID_IMP_R5000:
1172 c->cputype = CPU_R5000;
1173 __cpu_name[cpu] = "R5000";
1174 set_isa(c, MIPS_CPU_ISA_IV);
1175 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1176 MIPS_CPU_LLSC;
1177 c->tlbsize = 48;
1178 break;
1179 case PRID_IMP_R5500:
1180 c->cputype = CPU_R5500;
1181 __cpu_name[cpu] = "R5500";
1182 set_isa(c, MIPS_CPU_ISA_IV);
1183 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1184 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1185 c->tlbsize = 48;
1186 break;
1187 case PRID_IMP_NEVADA:
1188 c->cputype = CPU_NEVADA;
1189 __cpu_name[cpu] = "Nevada";
1190 set_isa(c, MIPS_CPU_ISA_IV);
1191 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1192 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1193 c->tlbsize = 48;
1194 break;
1195 case PRID_IMP_RM7000:
1196 c->cputype = CPU_RM7000;
1197 __cpu_name[cpu] = "RM7000";
1198 set_isa(c, MIPS_CPU_ISA_IV);
1199 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1200 MIPS_CPU_LLSC;
1201 /*
1202 * Undocumented RM7000: Bit 29 in the info register of
1203 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1204 * entries.
1205 *
1206 * 29 1 => 64 entry JTLB
1207 * 0 => 48 entry JTLB
1208 */
1209 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1210 break;
1211 case PRID_IMP_R10000:
1212 c->cputype = CPU_R10000;
1213 __cpu_name[cpu] = "R10000";
1214 set_isa(c, MIPS_CPU_ISA_IV);
1215 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1216 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1217 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1218 MIPS_CPU_LLSC;
1219 c->tlbsize = 64;
1220 break;
1221 case PRID_IMP_R12000:
1222 c->cputype = CPU_R12000;
1223 __cpu_name[cpu] = "R12000";
1224 set_isa(c, MIPS_CPU_ISA_IV);
1225 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1226 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1227 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1228 MIPS_CPU_LLSC;
1229 c->tlbsize = 64;
1230 write_c0_r10k_diag(read_c0_r10k_diag() | R10K_DIAG_E_GHIST);
1231 break;
1232 case PRID_IMP_R14000:
1233 if (((c->processor_id >> 4) & 0x0f) > 2) {
1234 c->cputype = CPU_R16000;
1235 __cpu_name[cpu] = "R16000";
1236 } else {
1237 c->cputype = CPU_R14000;
1238 __cpu_name[cpu] = "R14000";
1239 }
1240 set_isa(c, MIPS_CPU_ISA_IV);
1241 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1242 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1243 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1244 MIPS_CPU_LLSC;
1245 c->tlbsize = 64;
1246 write_c0_r10k_diag(read_c0_r10k_diag() | R10K_DIAG_E_GHIST);
1247 break;
1248 case PRID_IMP_LOONGSON_64C: /* Loongson-2/3 */
1249 switch (c->processor_id & PRID_REV_MASK) {
1250 case PRID_REV_LOONGSON2E:
1251 c->cputype = CPU_LOONGSON2EF;
1252 __cpu_name[cpu] = "ICT Loongson-2";
1253 set_elf_platform(cpu, "loongson2e");
1254 set_isa(c, MIPS_CPU_ISA_III);
1255 c->fpu_msk31 |= FPU_CSR_CONDX;
1256 break;
1257 case PRID_REV_LOONGSON2F:
1258 c->cputype = CPU_LOONGSON2EF;
1259 __cpu_name[cpu] = "ICT Loongson-2";
1260 set_elf_platform(cpu, "loongson2f");
1261 set_isa(c, MIPS_CPU_ISA_III);
1262 c->fpu_msk31 |= FPU_CSR_CONDX;
1263 break;
1264 case PRID_REV_LOONGSON3A_R1:
1265 c->cputype = CPU_LOONGSON64;
1266 __cpu_name[cpu] = "ICT Loongson-3";
1267 set_elf_platform(cpu, "loongson3a");
1268 set_isa(c, MIPS_CPU_ISA_M64R1);
1269 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1270 MIPS_ASE_LOONGSON_EXT);
1271 break;
1272 case PRID_REV_LOONGSON3B_R1:
1273 case PRID_REV_LOONGSON3B_R2:
1274 c->cputype = CPU_LOONGSON64;
1275 __cpu_name[cpu] = "ICT Loongson-3";
1276 set_elf_platform(cpu, "loongson3b");
1277 set_isa(c, MIPS_CPU_ISA_M64R1);
1278 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1279 MIPS_ASE_LOONGSON_EXT);
1280 break;
1281 }
1282
1283 c->options = R4K_OPTS |
1284 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1285 MIPS_CPU_32FPR;
1286 c->tlbsize = 64;
1287 set_cpu_asid_mask(c, MIPS_ENTRYHI_ASID);
1288 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1289 break;
1290 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
1291 decode_configs(c);
1292
1293 c->cputype = CPU_LOONGSON32;
1294
1295 switch (c->processor_id & PRID_REV_MASK) {
1296 case PRID_REV_LOONGSON1B:
1297 __cpu_name[cpu] = "Loongson 1B";
1298 break;
1299 }
1300
1301 break;
1302 }
1303}
1304
1305static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1306{
1307 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1308 switch (c->processor_id & PRID_IMP_MASK) {
1309 case PRID_IMP_QEMU_GENERIC:
1310 c->writecombine = _CACHE_UNCACHED;
1311 c->cputype = CPU_QEMU_GENERIC;
1312 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1313 break;
1314 case PRID_IMP_4KC:
1315 c->cputype = CPU_4KC;
1316 c->writecombine = _CACHE_UNCACHED;
1317 __cpu_name[cpu] = "MIPS 4Kc";
1318 break;
1319 case PRID_IMP_4KEC:
1320 case PRID_IMP_4KECR2:
1321 c->cputype = CPU_4KEC;
1322 c->writecombine = _CACHE_UNCACHED;
1323 __cpu_name[cpu] = "MIPS 4KEc";
1324 break;
1325 case PRID_IMP_4KSC:
1326 case PRID_IMP_4KSD:
1327 c->cputype = CPU_4KSC;
1328 c->writecombine = _CACHE_UNCACHED;
1329 __cpu_name[cpu] = "MIPS 4KSc";
1330 break;
1331 case PRID_IMP_5KC:
1332 c->cputype = CPU_5KC;
1333 c->writecombine = _CACHE_UNCACHED;
1334 __cpu_name[cpu] = "MIPS 5Kc";
1335 break;
1336 case PRID_IMP_5KE:
1337 c->cputype = CPU_5KE;
1338 c->writecombine = _CACHE_UNCACHED;
1339 __cpu_name[cpu] = "MIPS 5KE";
1340 break;
1341 case PRID_IMP_20KC:
1342 c->cputype = CPU_20KC;
1343 c->writecombine = _CACHE_UNCACHED;
1344 __cpu_name[cpu] = "MIPS 20Kc";
1345 break;
1346 case PRID_IMP_24K:
1347 c->cputype = CPU_24K;
1348 c->writecombine = _CACHE_UNCACHED;
1349 __cpu_name[cpu] = "MIPS 24Kc";
1350 break;
1351 case PRID_IMP_24KE:
1352 c->cputype = CPU_24K;
1353 c->writecombine = _CACHE_UNCACHED;
1354 __cpu_name[cpu] = "MIPS 24KEc";
1355 break;
1356 case PRID_IMP_25KF:
1357 c->cputype = CPU_25KF;
1358 c->writecombine = _CACHE_UNCACHED;
1359 __cpu_name[cpu] = "MIPS 25Kc";
1360 break;
1361 case PRID_IMP_34K:
1362 c->cputype = CPU_34K;
1363 c->writecombine = _CACHE_UNCACHED;
1364 __cpu_name[cpu] = "MIPS 34Kc";
1365 cpu_set_mt_per_tc_perf(c);
1366 break;
1367 case PRID_IMP_74K:
1368 c->cputype = CPU_74K;
1369 c->writecombine = _CACHE_UNCACHED;
1370 __cpu_name[cpu] = "MIPS 74Kc";
1371 break;
1372 case PRID_IMP_M14KC:
1373 c->cputype = CPU_M14KC;
1374 c->writecombine = _CACHE_UNCACHED;
1375 __cpu_name[cpu] = "MIPS M14Kc";
1376 break;
1377 case PRID_IMP_M14KEC:
1378 c->cputype = CPU_M14KEC;
1379 c->writecombine = _CACHE_UNCACHED;
1380 __cpu_name[cpu] = "MIPS M14KEc";
1381 break;
1382 case PRID_IMP_1004K:
1383 c->cputype = CPU_1004K;
1384 c->writecombine = _CACHE_UNCACHED;
1385 __cpu_name[cpu] = "MIPS 1004Kc";
1386 cpu_set_mt_per_tc_perf(c);
1387 break;
1388 case PRID_IMP_1074K:
1389 c->cputype = CPU_1074K;
1390 c->writecombine = _CACHE_UNCACHED;
1391 __cpu_name[cpu] = "MIPS 1074Kc";
1392 break;
1393 case PRID_IMP_INTERAPTIV_UP:
1394 c->cputype = CPU_INTERAPTIV;
1395 __cpu_name[cpu] = "MIPS interAptiv";
1396 cpu_set_mt_per_tc_perf(c);
1397 break;
1398 case PRID_IMP_INTERAPTIV_MP:
1399 c->cputype = CPU_INTERAPTIV;
1400 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1401 cpu_set_mt_per_tc_perf(c);
1402 break;
1403 case PRID_IMP_PROAPTIV_UP:
1404 c->cputype = CPU_PROAPTIV;
1405 __cpu_name[cpu] = "MIPS proAptiv";
1406 break;
1407 case PRID_IMP_PROAPTIV_MP:
1408 c->cputype = CPU_PROAPTIV;
1409 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1410 break;
1411 case PRID_IMP_P5600:
1412 c->cputype = CPU_P5600;
1413 __cpu_name[cpu] = "MIPS P5600";
1414 break;
1415 case PRID_IMP_P6600:
1416 c->cputype = CPU_P6600;
1417 __cpu_name[cpu] = "MIPS P6600";
1418 break;
1419 case PRID_IMP_I6400:
1420 c->cputype = CPU_I6400;
1421 __cpu_name[cpu] = "MIPS I6400";
1422 break;
1423 case PRID_IMP_I6500:
1424 c->cputype = CPU_I6500;
1425 __cpu_name[cpu] = "MIPS I6500";
1426 break;
1427 case PRID_IMP_M5150:
1428 c->cputype = CPU_M5150;
1429 __cpu_name[cpu] = "MIPS M5150";
1430 break;
1431 case PRID_IMP_M6250:
1432 c->cputype = CPU_M6250;
1433 __cpu_name[cpu] = "MIPS M6250";
1434 break;
1435 }
1436
1437 decode_configs(c);
1438
1439 spram_config();
1440
1441 mm_config(c);
1442
1443 switch (__get_cpu_type(c->cputype)) {
1444 case CPU_M5150:
1445 case CPU_P5600:
1446 set_isa(c, MIPS_CPU_ISA_M32R5);
1447 break;
1448 case CPU_I6500:
1449 c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES;
1450 fallthrough;
1451 case CPU_I6400:
1452 c->options |= MIPS_CPU_SHARED_FTLB_RAM;
1453 fallthrough;
1454 default:
1455 break;
1456 }
1457
1458 /* Recent MIPS cores use the implementation-dependent ExcCode 16 for
1459 * cache/FTLB parity exceptions.
1460 */
1461 switch (__get_cpu_type(c->cputype)) {
1462 case CPU_PROAPTIV:
1463 case CPU_P5600:
1464 case CPU_P6600:
1465 case CPU_I6400:
1466 case CPU_I6500:
1467 c->options |= MIPS_CPU_FTLBPAREX;
1468 break;
1469 }
1470}
1471
1472static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1473{
1474 decode_configs(c);
1475 switch (c->processor_id & PRID_IMP_MASK) {
1476 case PRID_IMP_AU1_REV1:
1477 case PRID_IMP_AU1_REV2:
1478 c->cputype = CPU_ALCHEMY;
1479 switch ((c->processor_id >> 24) & 0xff) {
1480 case 0:
1481 __cpu_name[cpu] = "Au1000";
1482 break;
1483 case 1:
1484 __cpu_name[cpu] = "Au1500";
1485 break;
1486 case 2:
1487 __cpu_name[cpu] = "Au1100";
1488 break;
1489 case 3:
1490 __cpu_name[cpu] = "Au1550";
1491 break;
1492 case 4:
1493 __cpu_name[cpu] = "Au1200";
1494 if ((c->processor_id & PRID_REV_MASK) == 2)
1495 __cpu_name[cpu] = "Au1250";
1496 break;
1497 case 5:
1498 __cpu_name[cpu] = "Au1210";
1499 break;
1500 default:
1501 __cpu_name[cpu] = "Au1xxx";
1502 break;
1503 }
1504 break;
1505 }
1506}
1507
1508static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1509{
1510 decode_configs(c);
1511
1512 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1513 switch (c->processor_id & PRID_IMP_MASK) {
1514 case PRID_IMP_SB1:
1515 c->cputype = CPU_SB1;
1516 __cpu_name[cpu] = "SiByte SB1";
1517 /* FPU in pass1 is known to have issues. */
1518 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1519 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1520 break;
1521 case PRID_IMP_SB1A:
1522 c->cputype = CPU_SB1A;
1523 __cpu_name[cpu] = "SiByte SB1A";
1524 break;
1525 }
1526}
1527
1528static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1529{
1530 decode_configs(c);
1531 switch (c->processor_id & PRID_IMP_MASK) {
1532 case PRID_IMP_SR71000:
1533 c->cputype = CPU_SR71000;
1534 __cpu_name[cpu] = "Sandcraft SR71000";
1535 c->scache.ways = 8;
1536 c->tlbsize = 64;
1537 break;
1538 }
1539}
1540
1541static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1542{
1543 decode_configs(c);
1544 switch (c->processor_id & PRID_IMP_MASK) {
1545 case PRID_IMP_PR4450:
1546 c->cputype = CPU_PR4450;
1547 __cpu_name[cpu] = "Philips PR4450";
1548 set_isa(c, MIPS_CPU_ISA_M32R1);
1549 break;
1550 }
1551}
1552
1553static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1554{
1555 decode_configs(c);
1556 switch (c->processor_id & PRID_IMP_MASK) {
1557 case PRID_IMP_BMIPS32_REV4:
1558 case PRID_IMP_BMIPS32_REV8:
1559 c->cputype = CPU_BMIPS32;
1560 __cpu_name[cpu] = "Broadcom BMIPS32";
1561 set_elf_platform(cpu, "bmips32");
1562 break;
1563 case PRID_IMP_BMIPS3300:
1564 case PRID_IMP_BMIPS3300_ALT:
1565 case PRID_IMP_BMIPS3300_BUG:
1566 c->cputype = CPU_BMIPS3300;
1567 __cpu_name[cpu] = "Broadcom BMIPS3300";
1568 set_elf_platform(cpu, "bmips3300");
1569 reserve_exception_space(0x400, VECTORSPACING * 64);
1570 break;
1571 case PRID_IMP_BMIPS43XX: {
1572 int rev = c->processor_id & PRID_REV_MASK;
1573
1574 if (rev >= PRID_REV_BMIPS4380_LO &&
1575 rev <= PRID_REV_BMIPS4380_HI) {
1576 c->cputype = CPU_BMIPS4380;
1577 __cpu_name[cpu] = "Broadcom BMIPS4380";
1578 set_elf_platform(cpu, "bmips4380");
1579 c->options |= MIPS_CPU_RIXI;
1580 reserve_exception_space(0x400, VECTORSPACING * 64);
1581 } else {
1582 c->cputype = CPU_BMIPS4350;
1583 __cpu_name[cpu] = "Broadcom BMIPS4350";
1584 set_elf_platform(cpu, "bmips4350");
1585 }
1586 break;
1587 }
1588 case PRID_IMP_BMIPS5000:
1589 case PRID_IMP_BMIPS5200:
1590 c->cputype = CPU_BMIPS5000;
1591 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1592 __cpu_name[cpu] = "Broadcom BMIPS5200";
1593 else
1594 __cpu_name[cpu] = "Broadcom BMIPS5000";
1595 set_elf_platform(cpu, "bmips5000");
1596 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
1597 reserve_exception_space(0x1000, VECTORSPACING * 64);
1598 break;
1599 }
1600}
1601
1602static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1603{
1604 decode_configs(c);
1605 switch (c->processor_id & PRID_IMP_MASK) {
1606 case PRID_IMP_CAVIUM_CN38XX:
1607 case PRID_IMP_CAVIUM_CN31XX:
1608 case PRID_IMP_CAVIUM_CN30XX:
1609 c->cputype = CPU_CAVIUM_OCTEON;
1610 __cpu_name[cpu] = "Cavium Octeon";
1611 goto platform;
1612 case PRID_IMP_CAVIUM_CN58XX:
1613 case PRID_IMP_CAVIUM_CN56XX:
1614 case PRID_IMP_CAVIUM_CN50XX:
1615 case PRID_IMP_CAVIUM_CN52XX:
1616 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1617 __cpu_name[cpu] = "Cavium Octeon+";
1618platform:
1619 set_elf_platform(cpu, "octeon");
1620 break;
1621 case PRID_IMP_CAVIUM_CN61XX:
1622 case PRID_IMP_CAVIUM_CN63XX:
1623 case PRID_IMP_CAVIUM_CN66XX:
1624 case PRID_IMP_CAVIUM_CN68XX:
1625 case PRID_IMP_CAVIUM_CNF71XX:
1626 c->cputype = CPU_CAVIUM_OCTEON2;
1627 __cpu_name[cpu] = "Cavium Octeon II";
1628 set_elf_platform(cpu, "octeon2");
1629 break;
1630 case PRID_IMP_CAVIUM_CN70XX:
1631 case PRID_IMP_CAVIUM_CN73XX:
1632 case PRID_IMP_CAVIUM_CNF75XX:
1633 case PRID_IMP_CAVIUM_CN78XX:
1634 c->cputype = CPU_CAVIUM_OCTEON3;
1635 __cpu_name[cpu] = "Cavium Octeon III";
1636 set_elf_platform(cpu, "octeon3");
1637 break;
1638 default:
1639 printk(KERN_INFO "Unknown Octeon chip!\n");
1640 c->cputype = CPU_UNKNOWN;
1641 break;
1642 }
1643}
1644
1645#ifdef CONFIG_CPU_LOONGSON64
1646#include <loongson_regs.h>
1647
1648static inline void decode_cpucfg(struct cpuinfo_mips *c)
1649{
1650 u32 cfg1 = read_cpucfg(LOONGSON_CFG1);
1651 u32 cfg2 = read_cpucfg(LOONGSON_CFG2);
1652 u32 cfg3 = read_cpucfg(LOONGSON_CFG3);
1653
1654 if (cfg1 & LOONGSON_CFG1_MMI)
1655 c->ases |= MIPS_ASE_LOONGSON_MMI;
1656
1657 if (cfg2 & LOONGSON_CFG2_LEXT1)
1658 c->ases |= MIPS_ASE_LOONGSON_EXT;
1659
1660 if (cfg2 & LOONGSON_CFG2_LEXT2)
1661 c->ases |= MIPS_ASE_LOONGSON_EXT2;
1662
1663 if (cfg2 & LOONGSON_CFG2_LSPW) {
1664 c->options |= MIPS_CPU_LDPTE;
1665 c->guest.options |= MIPS_CPU_LDPTE;
1666 }
1667
1668 if (cfg3 & LOONGSON_CFG3_LCAMP)
1669 c->ases |= MIPS_ASE_LOONGSON_CAM;
1670}
1671
1672static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
1673{
1674 /* All Loongson processors covered here define ExcCode 16 as GSExc. */
1675 c->options |= MIPS_CPU_GSEXCEX;
1676
1677 switch (c->processor_id & PRID_IMP_MASK) {
1678 case PRID_IMP_LOONGSON_64R: /* Loongson-64 Reduced */
1679 switch (c->processor_id & PRID_REV_MASK) {
1680 case PRID_REV_LOONGSON2K_R1_0:
1681 case PRID_REV_LOONGSON2K_R1_1:
1682 case PRID_REV_LOONGSON2K_R1_2:
1683 case PRID_REV_LOONGSON2K_R1_3:
1684 c->cputype = CPU_LOONGSON64;
1685 __cpu_name[cpu] = "Loongson-2K";
1686 set_elf_platform(cpu, "gs264e");
1687 set_isa(c, MIPS_CPU_ISA_M64R2);
1688 break;
1689 }
1690 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_EXT |
1691 MIPS_ASE_LOONGSON_EXT2);
1692 break;
1693 case PRID_IMP_LOONGSON_64C: /* Loongson-3 Classic */
1694 switch (c->processor_id & PRID_REV_MASK) {
1695 case PRID_REV_LOONGSON3A_R2_0:
1696 case PRID_REV_LOONGSON3A_R2_1:
1697 c->cputype = CPU_LOONGSON64;
1698 __cpu_name[cpu] = "ICT Loongson-3";
1699 set_elf_platform(cpu, "loongson3a");
1700 set_isa(c, MIPS_CPU_ISA_M64R2);
1701 break;
1702 case PRID_REV_LOONGSON3A_R3_0:
1703 case PRID_REV_LOONGSON3A_R3_1:
1704 c->cputype = CPU_LOONGSON64;
1705 __cpu_name[cpu] = "ICT Loongson-3";
1706 set_elf_platform(cpu, "loongson3a");
1707 set_isa(c, MIPS_CPU_ISA_M64R2);
1708 break;
1709 }
1710 /*
1711 * Loongson-3 Classic did not implement MIPS standard TLBINV
1712 * but implemented TLBINVF and EHINV. As currently we're only
1713 * using these two features, enable MIPS_CPU_TLBINV as well.
1714 *
1715 * Also some early Loongson-3A2000 had wrong TLB type in Config
1716 * register, we correct it here.
1717 */
1718 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
1719 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1720 MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
1721 c->ases &= ~MIPS_ASE_VZ; /* VZ of Loongson-3A2000/3000 is incomplete */
1722 break;
1723 case PRID_IMP_LOONGSON_64G:
1724 c->cputype = CPU_LOONGSON64;
1725 __cpu_name[cpu] = "ICT Loongson-3";
1726 set_elf_platform(cpu, "loongson3a");
1727 set_isa(c, MIPS_CPU_ISA_M64R2);
1728 decode_cpucfg(c);
1729 break;
1730 default:
1731 panic("Unknown Loongson Processor ID!");
1732 break;
1733 }
1734
1735 decode_configs(c);
1736}
1737#else
1738static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu) { }
1739#endif
1740
1741static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1742{
1743 decode_configs(c);
1744
1745 /*
1746 * XBurst misses a config2 register, so config3 decode was skipped in
1747 * decode_configs().
1748 */
1749 decode_config3(c);
1750
1751 /* XBurst does not implement the CP0 counter. */
1752 c->options &= ~MIPS_CPU_COUNTER;
1753 BUG_ON(__builtin_constant_p(cpu_has_counter) && cpu_has_counter);
1754
1755 /* XBurst has virtually tagged icache */
1756 c->icache.flags |= MIPS_CACHE_VTAG;
1757
1758 switch (c->processor_id & PRID_IMP_MASK) {
1759
1760 /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
1761 case PRID_IMP_XBURST_REV1:
1762
1763 /*
1764 * The XBurst core by default attempts to avoid branch target
1765 * buffer lookups by detecting & special casing loops. This
1766 * feature will cause BogoMIPS and lpj calculate in error.
1767 * Set cp0 config7 bit 4 to disable this feature.
1768 */
1769 set_c0_config7(MIPS_CONF7_BTB_LOOP_EN);
1770
1771 switch (c->processor_id & PRID_COMP_MASK) {
1772
1773 /*
1774 * The config0 register in the XBurst CPUs with a processor ID of
1775 * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
1776 * but they don't actually support this ISA.
1777 */
1778 case PRID_COMP_INGENIC_D0:
1779 c->isa_level &= ~MIPS_CPU_ISA_M32R2;
1780
1781 /* FPU is not properly detected on JZ4760(B). */
1782 if (c->processor_id == 0x2ed0024f)
1783 c->options |= MIPS_CPU_FPU;
1784
1785 fallthrough;
1786
1787 /*
1788 * The config0 register in the XBurst CPUs with a processor ID of
1789 * PRID_COMP_INGENIC_D0 or PRID_COMP_INGENIC_D1 has an abandoned
1790 * huge page tlb mode, this mode is not compatible with the MIPS
1791 * standard, it will cause tlbmiss and into an infinite loop
1792 * (line 21 in the tlb-funcs.S) when starting the init process.
1793 * After chip reset, the default is HPTLB mode, Write 0xa9000000
1794 * to cp0 register 5 sel 4 to switch back to VTLB mode to prevent
1795 * getting stuck.
1796 */
1797 case PRID_COMP_INGENIC_D1:
1798 write_c0_page_ctrl(XBURST_PAGECTRL_HPTLB_DIS);
1799 break;
1800
1801 default:
1802 break;
1803 }
1804 fallthrough;
1805
1806 /* XBurst®1 with MXU2.0 SIMD ISA */
1807 case PRID_IMP_XBURST_REV2:
1808 /* Ingenic uses the WA bit to achieve write-combine memory writes */
1809 c->writecombine = _CACHE_CACHABLE_WA;
1810 c->cputype = CPU_XBURST;
1811 __cpu_name[cpu] = "Ingenic XBurst";
1812 break;
1813
1814 /* XBurst®2 with MXU2.1 SIMD ISA */
1815 case PRID_IMP_XBURST2:
1816 c->cputype = CPU_XBURST;
1817 __cpu_name[cpu] = "Ingenic XBurst II";
1818 break;
1819
1820 default:
1821 panic("Unknown Ingenic Processor ID!");
1822 break;
1823 }
1824}
1825
1826#ifdef CONFIG_64BIT
1827/* For use by uaccess.h */
1828u64 __ua_limit;
1829EXPORT_SYMBOL(__ua_limit);
1830#endif
1831
1832const char *__cpu_name[NR_CPUS];
1833const char *__elf_platform;
1834const char *__elf_base_platform;
1835
1836void cpu_probe(void)
1837{
1838 struct cpuinfo_mips *c = ¤t_cpu_data;
1839 unsigned int cpu = smp_processor_id();
1840
1841 /*
1842 * Set a default elf platform, cpu probe may later
1843 * overwrite it with a more precise value
1844 */
1845 set_elf_platform(cpu, "mips");
1846
1847 c->processor_id = PRID_IMP_UNKNOWN;
1848 c->fpu_id = FPIR_IMP_NONE;
1849 c->cputype = CPU_UNKNOWN;
1850 c->writecombine = _CACHE_UNCACHED;
1851
1852 c->fpu_csr31 = FPU_CSR_RN;
1853 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1854
1855 c->processor_id = read_c0_prid();
1856 switch (c->processor_id & PRID_COMP_MASK) {
1857 case PRID_COMP_LEGACY:
1858 cpu_probe_legacy(c, cpu);
1859 break;
1860 case PRID_COMP_MIPS:
1861 cpu_probe_mips(c, cpu);
1862 break;
1863 case PRID_COMP_ALCHEMY:
1864 cpu_probe_alchemy(c, cpu);
1865 break;
1866 case PRID_COMP_SIBYTE:
1867 cpu_probe_sibyte(c, cpu);
1868 break;
1869 case PRID_COMP_BROADCOM:
1870 cpu_probe_broadcom(c, cpu);
1871 break;
1872 case PRID_COMP_SANDCRAFT:
1873 cpu_probe_sandcraft(c, cpu);
1874 break;
1875 case PRID_COMP_NXP:
1876 cpu_probe_nxp(c, cpu);
1877 break;
1878 case PRID_COMP_CAVIUM:
1879 cpu_probe_cavium(c, cpu);
1880 break;
1881 case PRID_COMP_LOONGSON:
1882 cpu_probe_loongson(c, cpu);
1883 break;
1884 case PRID_COMP_INGENIC_13:
1885 case PRID_COMP_INGENIC_D0:
1886 case PRID_COMP_INGENIC_D1:
1887 case PRID_COMP_INGENIC_E1:
1888 cpu_probe_ingenic(c, cpu);
1889 break;
1890 }
1891
1892 BUG_ON(!__cpu_name[cpu]);
1893 BUG_ON(c->cputype == CPU_UNKNOWN);
1894
1895 /*
1896 * Platform code can force the cpu type to optimize code
1897 * generation. In that case be sure the cpu type is correctly
1898 * manually setup otherwise it could trigger some nasty bugs.
1899 */
1900 BUG_ON(current_cpu_type() != c->cputype);
1901
1902 if (cpu_has_rixi) {
1903 /* Enable the RIXI exceptions */
1904 set_c0_pagegrain(PG_IEC);
1905 back_to_back_c0_hazard();
1906 /* Verify the IEC bit is set */
1907 if (read_c0_pagegrain() & PG_IEC)
1908 c->options |= MIPS_CPU_RIXIEX;
1909 }
1910
1911 if (mips_fpu_disabled)
1912 c->options &= ~MIPS_CPU_FPU;
1913
1914 if (mips_dsp_disabled)
1915 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
1916
1917 if (mips_htw_disabled) {
1918 c->options &= ~MIPS_CPU_HTW;
1919 write_c0_pwctl(read_c0_pwctl() &
1920 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
1921 }
1922
1923 if (c->options & MIPS_CPU_FPU)
1924 cpu_set_fpu_opts(c);
1925 else
1926 cpu_set_nofpu_opts(c);
1927
1928 if (cpu_has_mips_r2_r6) {
1929 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1930 /* R2 has Performance Counter Interrupt indicator */
1931 c->options |= MIPS_CPU_PCI;
1932 }
1933 else
1934 c->srsets = 1;
1935
1936 if (cpu_has_mips_r6)
1937 elf_hwcap |= HWCAP_MIPS_R6;
1938
1939 if (cpu_has_msa) {
1940 c->msa_id = cpu_get_msa_id();
1941 WARN(c->msa_id & MSA_IR_WRPF,
1942 "Vector register partitioning unimplemented!");
1943 elf_hwcap |= HWCAP_MIPS_MSA;
1944 }
1945
1946 if (cpu_has_mips16)
1947 elf_hwcap |= HWCAP_MIPS_MIPS16;
1948
1949 if (cpu_has_mdmx)
1950 elf_hwcap |= HWCAP_MIPS_MDMX;
1951
1952 if (cpu_has_mips3d)
1953 elf_hwcap |= HWCAP_MIPS_MIPS3D;
1954
1955 if (cpu_has_smartmips)
1956 elf_hwcap |= HWCAP_MIPS_SMARTMIPS;
1957
1958 if (cpu_has_dsp)
1959 elf_hwcap |= HWCAP_MIPS_DSP;
1960
1961 if (cpu_has_dsp2)
1962 elf_hwcap |= HWCAP_MIPS_DSP2;
1963
1964 if (cpu_has_dsp3)
1965 elf_hwcap |= HWCAP_MIPS_DSP3;
1966
1967 if (cpu_has_mips16e2)
1968 elf_hwcap |= HWCAP_MIPS_MIPS16E2;
1969
1970 if (cpu_has_loongson_mmi)
1971 elf_hwcap |= HWCAP_LOONGSON_MMI;
1972
1973 if (cpu_has_loongson_ext)
1974 elf_hwcap |= HWCAP_LOONGSON_EXT;
1975
1976 if (cpu_has_loongson_ext2)
1977 elf_hwcap |= HWCAP_LOONGSON_EXT2;
1978
1979 if (cpu_has_vz)
1980 cpu_probe_vz(c);
1981
1982 cpu_probe_vmbits(c);
1983
1984 /* Synthesize CPUCFG data if running on Loongson processors;
1985 * no-op otherwise.
1986 *
1987 * This looks at previously probed features, so keep this at bottom.
1988 */
1989 loongson3_cpucfg_synthesize_data(c);
1990
1991#ifdef CONFIG_64BIT
1992 if (cpu == 0)
1993 __ua_limit = ~((1ull << cpu_vmbits) - 1);
1994#endif
1995
1996 reserve_exception_space(0, 0x1000);
1997}
1998
1999void cpu_report(void)
2000{
2001 struct cpuinfo_mips *c = ¤t_cpu_data;
2002
2003 pr_info("CPU%d revision is: %08x (%s)\n",
2004 smp_processor_id(), c->processor_id, cpu_name_string());
2005 if (c->options & MIPS_CPU_FPU)
2006 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
2007 if (cpu_has_msa)
2008 pr_info("MSA revision is: %08x\n", c->msa_id);
2009}
2010
2011void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster)
2012{
2013 /* Ensure the core number fits in the field */
2014 WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >>
2015 MIPS_GLOBALNUMBER_CLUSTER_SHF));
2016
2017 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER;
2018 cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF;
2019}
2020
2021void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core)
2022{
2023 /* Ensure the core number fits in the field */
2024 WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF));
2025
2026 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE;
2027 cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF;
2028}
2029
2030void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe)
2031{
2032 /* Ensure the VP(E) ID fits in the field */
2033 WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF));
2034
2035 /* Ensure we're not using VP(E)s without support */
2036 WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) &&
2037 !IS_ENABLED(CONFIG_CPU_MIPSR6));
2038
2039 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP;
2040 cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF;
2041}