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1/*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
22#include <linux/delay.h>
23#include <linux/export.h>
24#include <linux/gpio.h>
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/platform_data/b53.h>
28#include <linux/phy.h>
29#include <linux/etherdevice.h>
30#include <linux/if_bridge.h>
31#include <net/dsa.h>
32#include <net/switchdev.h>
33
34#include "b53_regs.h"
35#include "b53_priv.h"
36
37struct b53_mib_desc {
38 u8 size;
39 u8 offset;
40 const char *name;
41};
42
43/* BCM5365 MIB counters */
44static const struct b53_mib_desc b53_mibs_65[] = {
45 { 8, 0x00, "TxOctets" },
46 { 4, 0x08, "TxDropPkts" },
47 { 4, 0x10, "TxBroadcastPkts" },
48 { 4, 0x14, "TxMulticastPkts" },
49 { 4, 0x18, "TxUnicastPkts" },
50 { 4, 0x1c, "TxCollisions" },
51 { 4, 0x20, "TxSingleCollision" },
52 { 4, 0x24, "TxMultipleCollision" },
53 { 4, 0x28, "TxDeferredTransmit" },
54 { 4, 0x2c, "TxLateCollision" },
55 { 4, 0x30, "TxExcessiveCollision" },
56 { 4, 0x38, "TxPausePkts" },
57 { 8, 0x44, "RxOctets" },
58 { 4, 0x4c, "RxUndersizePkts" },
59 { 4, 0x50, "RxPausePkts" },
60 { 4, 0x54, "Pkts64Octets" },
61 { 4, 0x58, "Pkts65to127Octets" },
62 { 4, 0x5c, "Pkts128to255Octets" },
63 { 4, 0x60, "Pkts256to511Octets" },
64 { 4, 0x64, "Pkts512to1023Octets" },
65 { 4, 0x68, "Pkts1024to1522Octets" },
66 { 4, 0x6c, "RxOversizePkts" },
67 { 4, 0x70, "RxJabbers" },
68 { 4, 0x74, "RxAlignmentErrors" },
69 { 4, 0x78, "RxFCSErrors" },
70 { 8, 0x7c, "RxGoodOctets" },
71 { 4, 0x84, "RxDropPkts" },
72 { 4, 0x88, "RxUnicastPkts" },
73 { 4, 0x8c, "RxMulticastPkts" },
74 { 4, 0x90, "RxBroadcastPkts" },
75 { 4, 0x94, "RxSAChanges" },
76 { 4, 0x98, "RxFragments" },
77};
78
79#define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
80
81/* BCM63xx MIB counters */
82static const struct b53_mib_desc b53_mibs_63xx[] = {
83 { 8, 0x00, "TxOctets" },
84 { 4, 0x08, "TxDropPkts" },
85 { 4, 0x0c, "TxQoSPkts" },
86 { 4, 0x10, "TxBroadcastPkts" },
87 { 4, 0x14, "TxMulticastPkts" },
88 { 4, 0x18, "TxUnicastPkts" },
89 { 4, 0x1c, "TxCollisions" },
90 { 4, 0x20, "TxSingleCollision" },
91 { 4, 0x24, "TxMultipleCollision" },
92 { 4, 0x28, "TxDeferredTransmit" },
93 { 4, 0x2c, "TxLateCollision" },
94 { 4, 0x30, "TxExcessiveCollision" },
95 { 4, 0x38, "TxPausePkts" },
96 { 8, 0x3c, "TxQoSOctets" },
97 { 8, 0x44, "RxOctets" },
98 { 4, 0x4c, "RxUndersizePkts" },
99 { 4, 0x50, "RxPausePkts" },
100 { 4, 0x54, "Pkts64Octets" },
101 { 4, 0x58, "Pkts65to127Octets" },
102 { 4, 0x5c, "Pkts128to255Octets" },
103 { 4, 0x60, "Pkts256to511Octets" },
104 { 4, 0x64, "Pkts512to1023Octets" },
105 { 4, 0x68, "Pkts1024to1522Octets" },
106 { 4, 0x6c, "RxOversizePkts" },
107 { 4, 0x70, "RxJabbers" },
108 { 4, 0x74, "RxAlignmentErrors" },
109 { 4, 0x78, "RxFCSErrors" },
110 { 8, 0x7c, "RxGoodOctets" },
111 { 4, 0x84, "RxDropPkts" },
112 { 4, 0x88, "RxUnicastPkts" },
113 { 4, 0x8c, "RxMulticastPkts" },
114 { 4, 0x90, "RxBroadcastPkts" },
115 { 4, 0x94, "RxSAChanges" },
116 { 4, 0x98, "RxFragments" },
117 { 4, 0xa0, "RxSymbolErrors" },
118 { 4, 0xa4, "RxQoSPkts" },
119 { 8, 0xa8, "RxQoSOctets" },
120 { 4, 0xb0, "Pkts1523to2047Octets" },
121 { 4, 0xb4, "Pkts2048to4095Octets" },
122 { 4, 0xb8, "Pkts4096to8191Octets" },
123 { 4, 0xbc, "Pkts8192to9728Octets" },
124 { 4, 0xc0, "RxDiscarded" },
125};
126
127#define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
128
129/* MIB counters */
130static const struct b53_mib_desc b53_mibs[] = {
131 { 8, 0x00, "TxOctets" },
132 { 4, 0x08, "TxDropPkts" },
133 { 4, 0x10, "TxBroadcastPkts" },
134 { 4, 0x14, "TxMulticastPkts" },
135 { 4, 0x18, "TxUnicastPkts" },
136 { 4, 0x1c, "TxCollisions" },
137 { 4, 0x20, "TxSingleCollision" },
138 { 4, 0x24, "TxMultipleCollision" },
139 { 4, 0x28, "TxDeferredTransmit" },
140 { 4, 0x2c, "TxLateCollision" },
141 { 4, 0x30, "TxExcessiveCollision" },
142 { 4, 0x38, "TxPausePkts" },
143 { 8, 0x50, "RxOctets" },
144 { 4, 0x58, "RxUndersizePkts" },
145 { 4, 0x5c, "RxPausePkts" },
146 { 4, 0x60, "Pkts64Octets" },
147 { 4, 0x64, "Pkts65to127Octets" },
148 { 4, 0x68, "Pkts128to255Octets" },
149 { 4, 0x6c, "Pkts256to511Octets" },
150 { 4, 0x70, "Pkts512to1023Octets" },
151 { 4, 0x74, "Pkts1024to1522Octets" },
152 { 4, 0x78, "RxOversizePkts" },
153 { 4, 0x7c, "RxJabbers" },
154 { 4, 0x80, "RxAlignmentErrors" },
155 { 4, 0x84, "RxFCSErrors" },
156 { 8, 0x88, "RxGoodOctets" },
157 { 4, 0x90, "RxDropPkts" },
158 { 4, 0x94, "RxUnicastPkts" },
159 { 4, 0x98, "RxMulticastPkts" },
160 { 4, 0x9c, "RxBroadcastPkts" },
161 { 4, 0xa0, "RxSAChanges" },
162 { 4, 0xa4, "RxFragments" },
163 { 4, 0xa8, "RxJumboPkts" },
164 { 4, 0xac, "RxSymbolErrors" },
165 { 4, 0xc0, "RxDiscarded" },
166};
167
168#define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
169
170static const struct b53_mib_desc b53_mibs_58xx[] = {
171 { 8, 0x00, "TxOctets" },
172 { 4, 0x08, "TxDropPkts" },
173 { 4, 0x0c, "TxQPKTQ0" },
174 { 4, 0x10, "TxBroadcastPkts" },
175 { 4, 0x14, "TxMulticastPkts" },
176 { 4, 0x18, "TxUnicastPKts" },
177 { 4, 0x1c, "TxCollisions" },
178 { 4, 0x20, "TxSingleCollision" },
179 { 4, 0x24, "TxMultipleCollision" },
180 { 4, 0x28, "TxDeferredCollision" },
181 { 4, 0x2c, "TxLateCollision" },
182 { 4, 0x30, "TxExcessiveCollision" },
183 { 4, 0x34, "TxFrameInDisc" },
184 { 4, 0x38, "TxPausePkts" },
185 { 4, 0x3c, "TxQPKTQ1" },
186 { 4, 0x40, "TxQPKTQ2" },
187 { 4, 0x44, "TxQPKTQ3" },
188 { 4, 0x48, "TxQPKTQ4" },
189 { 4, 0x4c, "TxQPKTQ5" },
190 { 8, 0x50, "RxOctets" },
191 { 4, 0x58, "RxUndersizePkts" },
192 { 4, 0x5c, "RxPausePkts" },
193 { 4, 0x60, "RxPkts64Octets" },
194 { 4, 0x64, "RxPkts65to127Octets" },
195 { 4, 0x68, "RxPkts128to255Octets" },
196 { 4, 0x6c, "RxPkts256to511Octets" },
197 { 4, 0x70, "RxPkts512to1023Octets" },
198 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
199 { 4, 0x78, "RxOversizePkts" },
200 { 4, 0x7c, "RxJabbers" },
201 { 4, 0x80, "RxAlignmentErrors" },
202 { 4, 0x84, "RxFCSErrors" },
203 { 8, 0x88, "RxGoodOctets" },
204 { 4, 0x90, "RxDropPkts" },
205 { 4, 0x94, "RxUnicastPkts" },
206 { 4, 0x98, "RxMulticastPkts" },
207 { 4, 0x9c, "RxBroadcastPkts" },
208 { 4, 0xa0, "RxSAChanges" },
209 { 4, 0xa4, "RxFragments" },
210 { 4, 0xa8, "RxJumboPkt" },
211 { 4, 0xac, "RxSymblErr" },
212 { 4, 0xb0, "InRangeErrCount" },
213 { 4, 0xb4, "OutRangeErrCount" },
214 { 4, 0xb8, "EEELpiEvent" },
215 { 4, 0xbc, "EEELpiDuration" },
216 { 4, 0xc0, "RxDiscard" },
217 { 4, 0xc8, "TxQPKTQ6" },
218 { 4, 0xcc, "TxQPKTQ7" },
219 { 4, 0xd0, "TxPkts64Octets" },
220 { 4, 0xd4, "TxPkts65to127Octets" },
221 { 4, 0xd8, "TxPkts128to255Octets" },
222 { 4, 0xdc, "TxPkts256to511Ocets" },
223 { 4, 0xe0, "TxPkts512to1023Ocets" },
224 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
225};
226
227#define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
228
229static int b53_do_vlan_op(struct b53_device *dev, u8 op)
230{
231 unsigned int i;
232
233 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
234
235 for (i = 0; i < 10; i++) {
236 u8 vta;
237
238 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
239 if (!(vta & VTA_START_CMD))
240 return 0;
241
242 usleep_range(100, 200);
243 }
244
245 return -EIO;
246}
247
248static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
249 struct b53_vlan *vlan)
250{
251 if (is5325(dev)) {
252 u32 entry = 0;
253
254 if (vlan->members) {
255 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
256 VA_UNTAG_S_25) | vlan->members;
257 if (dev->core_rev >= 3)
258 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
259 else
260 entry |= VA_VALID_25;
261 }
262
263 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
264 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
265 VTA_RW_STATE_WR | VTA_RW_OP_EN);
266 } else if (is5365(dev)) {
267 u16 entry = 0;
268
269 if (vlan->members)
270 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
271 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
272
273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
274 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
275 VTA_RW_STATE_WR | VTA_RW_OP_EN);
276 } else {
277 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
278 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
279 (vlan->untag << VTE_UNTAG_S) | vlan->members);
280
281 b53_do_vlan_op(dev, VTA_CMD_WRITE);
282 }
283
284 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
285 vid, vlan->members, vlan->untag);
286}
287
288static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
289 struct b53_vlan *vlan)
290{
291 if (is5325(dev)) {
292 u32 entry = 0;
293
294 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
295 VTA_RW_STATE_RD | VTA_RW_OP_EN);
296 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
297
298 if (dev->core_rev >= 3)
299 vlan->valid = !!(entry & VA_VALID_25_R4);
300 else
301 vlan->valid = !!(entry & VA_VALID_25);
302 vlan->members = entry & VA_MEMBER_MASK;
303 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
304
305 } else if (is5365(dev)) {
306 u16 entry = 0;
307
308 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
309 VTA_RW_STATE_WR | VTA_RW_OP_EN);
310 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
311
312 vlan->valid = !!(entry & VA_VALID_65);
313 vlan->members = entry & VA_MEMBER_MASK;
314 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
315 } else {
316 u32 entry = 0;
317
318 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
319 b53_do_vlan_op(dev, VTA_CMD_READ);
320 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
321 vlan->members = entry & VTE_MEMBERS;
322 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
323 vlan->valid = true;
324 }
325}
326
327static void b53_set_forwarding(struct b53_device *dev, int enable)
328{
329 u8 mgmt;
330
331 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
332
333 if (enable)
334 mgmt |= SM_SW_FWD_EN;
335 else
336 mgmt &= ~SM_SW_FWD_EN;
337
338 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
339}
340
341static void b53_enable_vlan(struct b53_device *dev, bool enable)
342{
343 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
344
345 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
346 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
347 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
348
349 if (is5325(dev) || is5365(dev)) {
350 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
351 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
352 } else if (is63xx(dev)) {
353 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
354 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
355 } else {
356 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
357 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
358 }
359
360 mgmt &= ~SM_SW_FWD_MODE;
361
362 if (enable) {
363 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
364 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
365 vc4 &= ~VC4_ING_VID_CHECK_MASK;
366 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
367 vc5 |= VC5_DROP_VTABLE_MISS;
368
369 if (is5325(dev))
370 vc0 &= ~VC0_RESERVED_1;
371
372 if (is5325(dev) || is5365(dev))
373 vc1 |= VC1_RX_MCST_TAG_EN;
374
375 } else {
376 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
377 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
378 vc4 &= ~VC4_ING_VID_CHECK_MASK;
379 vc5 &= ~VC5_DROP_VTABLE_MISS;
380
381 if (is5325(dev) || is5365(dev))
382 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
383 else
384 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
385
386 if (is5325(dev) || is5365(dev))
387 vc1 &= ~VC1_RX_MCST_TAG_EN;
388 }
389
390 if (!is5325(dev) && !is5365(dev))
391 vc5 &= ~VC5_VID_FFF_EN;
392
393 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
394 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
395
396 if (is5325(dev) || is5365(dev)) {
397 /* enable the high 8 bit vid check on 5325 */
398 if (is5325(dev) && enable)
399 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
400 VC3_HIGH_8BIT_EN);
401 else
402 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
403
404 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
405 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
406 } else if (is63xx(dev)) {
407 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
408 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
409 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
410 } else {
411 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
412 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
413 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
414 }
415
416 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
417}
418
419static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
420{
421 u32 port_mask = 0;
422 u16 max_size = JMS_MIN_SIZE;
423
424 if (is5325(dev) || is5365(dev))
425 return -EINVAL;
426
427 if (enable) {
428 port_mask = dev->enabled_ports;
429 max_size = JMS_MAX_SIZE;
430 if (allow_10_100)
431 port_mask |= JPM_10_100_JUMBO_EN;
432 }
433
434 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
435 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
436}
437
438static int b53_flush_arl(struct b53_device *dev, u8 mask)
439{
440 unsigned int i;
441
442 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
443 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
444
445 for (i = 0; i < 10; i++) {
446 u8 fast_age_ctrl;
447
448 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
449 &fast_age_ctrl);
450
451 if (!(fast_age_ctrl & FAST_AGE_DONE))
452 goto out;
453
454 msleep(1);
455 }
456
457 return -ETIMEDOUT;
458out:
459 /* Only age dynamic entries (default behavior) */
460 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
461 return 0;
462}
463
464static int b53_fast_age_port(struct b53_device *dev, int port)
465{
466 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
467
468 return b53_flush_arl(dev, FAST_AGE_PORT);
469}
470
471static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
472{
473 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
474
475 return b53_flush_arl(dev, FAST_AGE_VLAN);
476}
477
478static void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
479{
480 struct b53_device *dev = ds->priv;
481 unsigned int i;
482 u16 pvlan;
483
484 /* Enable the IMP port to be in the same VLAN as the other ports
485 * on a per-port basis such that we only have Port i and IMP in
486 * the same VLAN.
487 */
488 b53_for_each_port(dev, i) {
489 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
490 pvlan |= BIT(cpu_port);
491 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
492 }
493}
494
495static int b53_enable_port(struct dsa_switch *ds, int port,
496 struct phy_device *phy)
497{
498 struct b53_device *dev = ds->priv;
499 unsigned int cpu_port = dev->cpu_port;
500 u16 pvlan;
501
502 /* Clear the Rx and Tx disable bits and set to no spanning tree */
503 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
504
505 /* Set this port, and only this one to be in the default VLAN,
506 * if member of a bridge, restore its membership prior to
507 * bringing down this port.
508 */
509 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
510 pvlan &= ~0x1ff;
511 pvlan |= BIT(port);
512 pvlan |= dev->ports[port].vlan_ctl_mask;
513 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
514
515 b53_imp_vlan_setup(ds, cpu_port);
516
517 return 0;
518}
519
520static void b53_disable_port(struct dsa_switch *ds, int port,
521 struct phy_device *phy)
522{
523 struct b53_device *dev = ds->priv;
524 u8 reg;
525
526 /* Disable Tx/Rx for the port */
527 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
528 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
529 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
530}
531
532static void b53_enable_cpu_port(struct b53_device *dev)
533{
534 unsigned int cpu_port = dev->cpu_port;
535 u8 port_ctrl;
536
537 /* BCM5325 CPU port is at 8 */
538 if ((is5325(dev) || is5365(dev)) && cpu_port == B53_CPU_PORT_25)
539 cpu_port = B53_CPU_PORT;
540
541 port_ctrl = PORT_CTRL_RX_BCST_EN |
542 PORT_CTRL_RX_MCST_EN |
543 PORT_CTRL_RX_UCST_EN;
544 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(cpu_port), port_ctrl);
545}
546
547static void b53_enable_mib(struct b53_device *dev)
548{
549 u8 gc;
550
551 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
552 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
553 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
554}
555
556static int b53_configure_vlan(struct b53_device *dev)
557{
558 struct b53_vlan vl = { 0 };
559 int i;
560
561 /* clear all vlan entries */
562 if (is5325(dev) || is5365(dev)) {
563 for (i = 1; i < dev->num_vlans; i++)
564 b53_set_vlan_entry(dev, i, &vl);
565 } else {
566 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
567 }
568
569 b53_enable_vlan(dev, false);
570
571 b53_for_each_port(dev, i)
572 b53_write16(dev, B53_VLAN_PAGE,
573 B53_VLAN_PORT_DEF_TAG(i), 1);
574
575 if (!is5325(dev) && !is5365(dev))
576 b53_set_jumbo(dev, dev->enable_jumbo, false);
577
578 return 0;
579}
580
581static void b53_switch_reset_gpio(struct b53_device *dev)
582{
583 int gpio = dev->reset_gpio;
584
585 if (gpio < 0)
586 return;
587
588 /* Reset sequence: RESET low(50ms)->high(20ms)
589 */
590 gpio_set_value(gpio, 0);
591 mdelay(50);
592
593 gpio_set_value(gpio, 1);
594 mdelay(20);
595
596 dev->current_page = 0xff;
597}
598
599static int b53_switch_reset(struct b53_device *dev)
600{
601 u8 mgmt;
602
603 b53_switch_reset_gpio(dev);
604
605 if (is539x(dev)) {
606 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
607 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
608 }
609
610 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
611
612 if (!(mgmt & SM_SW_FWD_EN)) {
613 mgmt &= ~SM_SW_FWD_MODE;
614 mgmt |= SM_SW_FWD_EN;
615
616 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
617 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
618
619 if (!(mgmt & SM_SW_FWD_EN)) {
620 dev_err(dev->dev, "Failed to enable switch!\n");
621 return -EINVAL;
622 }
623 }
624
625 b53_enable_mib(dev);
626
627 return b53_flush_arl(dev, FAST_AGE_STATIC);
628}
629
630static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
631{
632 struct b53_device *priv = ds->priv;
633 u16 value = 0;
634 int ret;
635
636 if (priv->ops->phy_read16)
637 ret = priv->ops->phy_read16(priv, addr, reg, &value);
638 else
639 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
640 reg * 2, &value);
641
642 return ret ? ret : value;
643}
644
645static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
646{
647 struct b53_device *priv = ds->priv;
648
649 if (priv->ops->phy_write16)
650 return priv->ops->phy_write16(priv, addr, reg, val);
651
652 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
653}
654
655static int b53_reset_switch(struct b53_device *priv)
656{
657 /* reset vlans */
658 priv->enable_jumbo = false;
659
660 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
661 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
662
663 return b53_switch_reset(priv);
664}
665
666static int b53_apply_config(struct b53_device *priv)
667{
668 /* disable switching */
669 b53_set_forwarding(priv, 0);
670
671 b53_configure_vlan(priv);
672
673 /* enable switching */
674 b53_set_forwarding(priv, 1);
675
676 return 0;
677}
678
679static void b53_reset_mib(struct b53_device *priv)
680{
681 u8 gc;
682
683 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
684
685 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
686 msleep(1);
687 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
688 msleep(1);
689}
690
691static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
692{
693 if (is5365(dev))
694 return b53_mibs_65;
695 else if (is63xx(dev))
696 return b53_mibs_63xx;
697 else if (is58xx(dev))
698 return b53_mibs_58xx;
699 else
700 return b53_mibs;
701}
702
703static unsigned int b53_get_mib_size(struct b53_device *dev)
704{
705 if (is5365(dev))
706 return B53_MIBS_65_SIZE;
707 else if (is63xx(dev))
708 return B53_MIBS_63XX_SIZE;
709 else if (is58xx(dev))
710 return B53_MIBS_58XX_SIZE;
711 else
712 return B53_MIBS_SIZE;
713}
714
715static void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
716{
717 struct b53_device *dev = ds->priv;
718 const struct b53_mib_desc *mibs = b53_get_mib(dev);
719 unsigned int mib_size = b53_get_mib_size(dev);
720 unsigned int i;
721
722 for (i = 0; i < mib_size; i++)
723 memcpy(data + i * ETH_GSTRING_LEN,
724 mibs[i].name, ETH_GSTRING_LEN);
725}
726
727static void b53_get_ethtool_stats(struct dsa_switch *ds, int port,
728 uint64_t *data)
729{
730 struct b53_device *dev = ds->priv;
731 const struct b53_mib_desc *mibs = b53_get_mib(dev);
732 unsigned int mib_size = b53_get_mib_size(dev);
733 const struct b53_mib_desc *s;
734 unsigned int i;
735 u64 val = 0;
736
737 if (is5365(dev) && port == 5)
738 port = 8;
739
740 mutex_lock(&dev->stats_mutex);
741
742 for (i = 0; i < mib_size; i++) {
743 s = &mibs[i];
744
745 if (s->size == 8) {
746 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
747 } else {
748 u32 val32;
749
750 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
751 &val32);
752 val = val32;
753 }
754 data[i] = (u64)val;
755 }
756
757 mutex_unlock(&dev->stats_mutex);
758}
759
760static int b53_get_sset_count(struct dsa_switch *ds)
761{
762 struct b53_device *dev = ds->priv;
763
764 return b53_get_mib_size(dev);
765}
766
767static int b53_setup(struct dsa_switch *ds)
768{
769 struct b53_device *dev = ds->priv;
770 unsigned int port;
771 int ret;
772
773 ret = b53_reset_switch(dev);
774 if (ret) {
775 dev_err(ds->dev, "failed to reset switch\n");
776 return ret;
777 }
778
779 b53_reset_mib(dev);
780
781 ret = b53_apply_config(dev);
782 if (ret)
783 dev_err(ds->dev, "failed to apply configuration\n");
784
785 for (port = 0; port < dev->num_ports; port++) {
786 if (BIT(port) & ds->enabled_port_mask)
787 b53_enable_port(ds, port, NULL);
788 else if (dsa_is_cpu_port(ds, port))
789 b53_enable_cpu_port(dev);
790 else
791 b53_disable_port(ds, port, NULL);
792 }
793
794 return ret;
795}
796
797static void b53_adjust_link(struct dsa_switch *ds, int port,
798 struct phy_device *phydev)
799{
800 struct b53_device *dev = ds->priv;
801 u8 rgmii_ctrl = 0, reg = 0, off;
802
803 if (!phy_is_pseudo_fixed_link(phydev))
804 return;
805
806 /* Override the port settings */
807 if (port == dev->cpu_port) {
808 off = B53_PORT_OVERRIDE_CTRL;
809 reg = PORT_OVERRIDE_EN;
810 } else {
811 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
812 reg = GMII_PO_EN;
813 }
814
815 /* Set the link UP */
816 if (phydev->link)
817 reg |= PORT_OVERRIDE_LINK;
818
819 if (phydev->duplex == DUPLEX_FULL)
820 reg |= PORT_OVERRIDE_FULL_DUPLEX;
821
822 switch (phydev->speed) {
823 case 2000:
824 reg |= PORT_OVERRIDE_SPEED_2000M;
825 /* fallthrough */
826 case SPEED_1000:
827 reg |= PORT_OVERRIDE_SPEED_1000M;
828 break;
829 case SPEED_100:
830 reg |= PORT_OVERRIDE_SPEED_100M;
831 break;
832 case SPEED_10:
833 reg |= PORT_OVERRIDE_SPEED_10M;
834 break;
835 default:
836 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed);
837 return;
838 }
839
840 /* Enable flow control on BCM5301x's CPU port */
841 if (is5301x(dev) && port == dev->cpu_port)
842 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW;
843
844 if (phydev->pause) {
845 if (phydev->asym_pause)
846 reg |= PORT_OVERRIDE_TX_FLOW;
847 reg |= PORT_OVERRIDE_RX_FLOW;
848 }
849
850 b53_write8(dev, B53_CTRL_PAGE, off, reg);
851
852 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
853 if (port == 8)
854 off = B53_RGMII_CTRL_IMP;
855 else
856 off = B53_RGMII_CTRL_P(port);
857
858 /* Configure the port RGMII clock delay by DLL disabled and
859 * tx_clk aligned timing (restoring to reset defaults)
860 */
861 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
862 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
863 RGMII_CTRL_TIMING_SEL);
864
865 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
866 * sure that we enable the port TX clock internal delay to
867 * account for this internal delay that is inserted, otherwise
868 * the switch won't be able to receive correctly.
869 *
870 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
871 * any delay neither on transmission nor reception, so the
872 * BCM53125 must also be configured accordingly to account for
873 * the lack of delay and introduce
874 *
875 * The BCM53125 switch has its RX clock and TX clock control
876 * swapped, hence the reason why we modify the TX clock path in
877 * the "RGMII" case
878 */
879 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
880 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
881 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
882 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
883 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
884 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
885
886 dev_info(ds->dev, "Configured port %d for %s\n", port,
887 phy_modes(phydev->interface));
888 }
889
890 /* configure MII port if necessary */
891 if (is5325(dev)) {
892 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
893 ®);
894
895 /* reverse mii needs to be enabled */
896 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
897 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
898 reg | PORT_OVERRIDE_RV_MII_25);
899 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
900 ®);
901
902 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
903 dev_err(ds->dev,
904 "Failed to enable reverse MII mode\n");
905 return;
906 }
907 }
908 } else if (is5301x(dev)) {
909 if (port != dev->cpu_port) {
910 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port);
911 u8 gmii_po;
912
913 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
914 gmii_po |= GMII_PO_LINK |
915 GMII_PO_RX_FLOW |
916 GMII_PO_TX_FLOW |
917 GMII_PO_EN |
918 GMII_PO_SPEED_2000M;
919 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
920 }
921 }
922}
923
924static int b53_vlan_filtering(struct dsa_switch *ds, int port,
925 bool vlan_filtering)
926{
927 return 0;
928}
929
930static int b53_vlan_prepare(struct dsa_switch *ds, int port,
931 const struct switchdev_obj_port_vlan *vlan,
932 struct switchdev_trans *trans)
933{
934 struct b53_device *dev = ds->priv;
935
936 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
937 return -EOPNOTSUPP;
938
939 if (vlan->vid_end > dev->num_vlans)
940 return -ERANGE;
941
942 b53_enable_vlan(dev, true);
943
944 return 0;
945}
946
947static void b53_vlan_add(struct dsa_switch *ds, int port,
948 const struct switchdev_obj_port_vlan *vlan,
949 struct switchdev_trans *trans)
950{
951 struct b53_device *dev = ds->priv;
952 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
953 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
954 unsigned int cpu_port = dev->cpu_port;
955 struct b53_vlan *vl;
956 u16 vid;
957
958 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
959 vl = &dev->vlans[vid];
960
961 b53_get_vlan_entry(dev, vid, vl);
962
963 vl->members |= BIT(port) | BIT(cpu_port);
964 if (untagged)
965 vl->untag |= BIT(port);
966 else
967 vl->untag &= ~BIT(port);
968 vl->untag &= ~BIT(cpu_port);
969
970 b53_set_vlan_entry(dev, vid, vl);
971 b53_fast_age_vlan(dev, vid);
972 }
973
974 if (pvid) {
975 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
976 vlan->vid_end);
977 b53_fast_age_vlan(dev, vid);
978 }
979}
980
981static int b53_vlan_del(struct dsa_switch *ds, int port,
982 const struct switchdev_obj_port_vlan *vlan)
983{
984 struct b53_device *dev = ds->priv;
985 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
986 struct b53_vlan *vl;
987 u16 vid;
988 u16 pvid;
989
990 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
991
992 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
993 vl = &dev->vlans[vid];
994
995 b53_get_vlan_entry(dev, vid, vl);
996
997 vl->members &= ~BIT(port);
998
999 if (pvid == vid) {
1000 if (is5325(dev) || is5365(dev))
1001 pvid = 1;
1002 else
1003 pvid = 0;
1004 }
1005
1006 if (untagged)
1007 vl->untag &= ~(BIT(port));
1008
1009 b53_set_vlan_entry(dev, vid, vl);
1010 b53_fast_age_vlan(dev, vid);
1011 }
1012
1013 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1014 b53_fast_age_vlan(dev, pvid);
1015
1016 return 0;
1017}
1018
1019static int b53_vlan_dump(struct dsa_switch *ds, int port,
1020 struct switchdev_obj_port_vlan *vlan,
1021 int (*cb)(struct switchdev_obj *obj))
1022{
1023 struct b53_device *dev = ds->priv;
1024 u16 vid, vid_start = 0, pvid;
1025 struct b53_vlan *vl;
1026 int err = 0;
1027
1028 if (is5325(dev) || is5365(dev))
1029 vid_start = 1;
1030
1031 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1032
1033 /* Use our software cache for dumps, since we do not have any HW
1034 * operation returning only the used/valid VLANs
1035 */
1036 for (vid = vid_start; vid < dev->num_vlans; vid++) {
1037 vl = &dev->vlans[vid];
1038
1039 if (!vl->valid)
1040 continue;
1041
1042 if (!(vl->members & BIT(port)))
1043 continue;
1044
1045 vlan->vid_begin = vlan->vid_end = vid;
1046 vlan->flags = 0;
1047
1048 if (vl->untag & BIT(port))
1049 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1050 if (pvid == vid)
1051 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1052
1053 err = cb(&vlan->obj);
1054 if (err)
1055 break;
1056 }
1057
1058 return err;
1059}
1060
1061/* Address Resolution Logic routines */
1062static int b53_arl_op_wait(struct b53_device *dev)
1063{
1064 unsigned int timeout = 10;
1065 u8 reg;
1066
1067 do {
1068 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1069 if (!(reg & ARLTBL_START_DONE))
1070 return 0;
1071
1072 usleep_range(1000, 2000);
1073 } while (timeout--);
1074
1075 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1076
1077 return -ETIMEDOUT;
1078}
1079
1080static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1081{
1082 u8 reg;
1083
1084 if (op > ARLTBL_RW)
1085 return -EINVAL;
1086
1087 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1088 reg |= ARLTBL_START_DONE;
1089 if (op)
1090 reg |= ARLTBL_RW;
1091 else
1092 reg &= ~ARLTBL_RW;
1093 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1094
1095 return b53_arl_op_wait(dev);
1096}
1097
1098static int b53_arl_read(struct b53_device *dev, u64 mac,
1099 u16 vid, struct b53_arl_entry *ent, u8 *idx,
1100 bool is_valid)
1101{
1102 unsigned int i;
1103 int ret;
1104
1105 ret = b53_arl_op_wait(dev);
1106 if (ret)
1107 return ret;
1108
1109 /* Read the bins */
1110 for (i = 0; i < dev->num_arl_entries; i++) {
1111 u64 mac_vid;
1112 u32 fwd_entry;
1113
1114 b53_read64(dev, B53_ARLIO_PAGE,
1115 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1116 b53_read32(dev, B53_ARLIO_PAGE,
1117 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1118 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1119
1120 if (!(fwd_entry & ARLTBL_VALID))
1121 continue;
1122 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1123 continue;
1124 *idx = i;
1125 }
1126
1127 return -ENOENT;
1128}
1129
1130static int b53_arl_op(struct b53_device *dev, int op, int port,
1131 const unsigned char *addr, u16 vid, bool is_valid)
1132{
1133 struct b53_arl_entry ent;
1134 u32 fwd_entry;
1135 u64 mac, mac_vid = 0;
1136 u8 idx = 0;
1137 int ret;
1138
1139 /* Convert the array into a 64-bit MAC */
1140 mac = b53_mac_to_u64(addr);
1141
1142 /* Perform a read for the given MAC and VID */
1143 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1144 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1145
1146 /* Issue a read operation for this MAC */
1147 ret = b53_arl_rw_op(dev, 1);
1148 if (ret)
1149 return ret;
1150
1151 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
1152 /* If this is a read, just finish now */
1153 if (op)
1154 return ret;
1155
1156 /* We could not find a matching MAC, so reset to a new entry */
1157 if (ret) {
1158 fwd_entry = 0;
1159 idx = 1;
1160 }
1161
1162 memset(&ent, 0, sizeof(ent));
1163 ent.port = port;
1164 ent.is_valid = is_valid;
1165 ent.vid = vid;
1166 ent.is_static = true;
1167 memcpy(ent.mac, addr, ETH_ALEN);
1168 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1169
1170 b53_write64(dev, B53_ARLIO_PAGE,
1171 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1172 b53_write32(dev, B53_ARLIO_PAGE,
1173 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1174
1175 return b53_arl_rw_op(dev, 0);
1176}
1177
1178static int b53_fdb_prepare(struct dsa_switch *ds, int port,
1179 const struct switchdev_obj_port_fdb *fdb,
1180 struct switchdev_trans *trans)
1181{
1182 struct b53_device *priv = ds->priv;
1183
1184 /* 5325 and 5365 require some more massaging, but could
1185 * be supported eventually
1186 */
1187 if (is5325(priv) || is5365(priv))
1188 return -EOPNOTSUPP;
1189
1190 return 0;
1191}
1192
1193static void b53_fdb_add(struct dsa_switch *ds, int port,
1194 const struct switchdev_obj_port_fdb *fdb,
1195 struct switchdev_trans *trans)
1196{
1197 struct b53_device *priv = ds->priv;
1198
1199 if (b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, true))
1200 pr_err("%s: failed to add MAC address\n", __func__);
1201}
1202
1203static int b53_fdb_del(struct dsa_switch *ds, int port,
1204 const struct switchdev_obj_port_fdb *fdb)
1205{
1206 struct b53_device *priv = ds->priv;
1207
1208 return b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, false);
1209}
1210
1211static int b53_arl_search_wait(struct b53_device *dev)
1212{
1213 unsigned int timeout = 1000;
1214 u8 reg;
1215
1216 do {
1217 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®);
1218 if (!(reg & ARL_SRCH_STDN))
1219 return 0;
1220
1221 if (reg & ARL_SRCH_VLID)
1222 return 0;
1223
1224 usleep_range(1000, 2000);
1225 } while (timeout--);
1226
1227 return -ETIMEDOUT;
1228}
1229
1230static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1231 struct b53_arl_entry *ent)
1232{
1233 u64 mac_vid;
1234 u32 fwd_entry;
1235
1236 b53_read64(dev, B53_ARLIO_PAGE,
1237 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1238 b53_read32(dev, B53_ARLIO_PAGE,
1239 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1240 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1241}
1242
1243static int b53_fdb_copy(struct net_device *dev, int port,
1244 const struct b53_arl_entry *ent,
1245 struct switchdev_obj_port_fdb *fdb,
1246 int (*cb)(struct switchdev_obj *obj))
1247{
1248 if (!ent->is_valid)
1249 return 0;
1250
1251 if (port != ent->port)
1252 return 0;
1253
1254 ether_addr_copy(fdb->addr, ent->mac);
1255 fdb->vid = ent->vid;
1256 fdb->ndm_state = ent->is_static ? NUD_NOARP : NUD_REACHABLE;
1257
1258 return cb(&fdb->obj);
1259}
1260
1261static int b53_fdb_dump(struct dsa_switch *ds, int port,
1262 struct switchdev_obj_port_fdb *fdb,
1263 int (*cb)(struct switchdev_obj *obj))
1264{
1265 struct b53_device *priv = ds->priv;
1266 struct net_device *dev = ds->ports[port].netdev;
1267 struct b53_arl_entry results[2];
1268 unsigned int count = 0;
1269 int ret;
1270 u8 reg;
1271
1272 /* Start search operation */
1273 reg = ARL_SRCH_STDN;
1274 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1275
1276 do {
1277 ret = b53_arl_search_wait(priv);
1278 if (ret)
1279 return ret;
1280
1281 b53_arl_search_rd(priv, 0, &results[0]);
1282 ret = b53_fdb_copy(dev, port, &results[0], fdb, cb);
1283 if (ret)
1284 return ret;
1285
1286 if (priv->num_arl_entries > 2) {
1287 b53_arl_search_rd(priv, 1, &results[1]);
1288 ret = b53_fdb_copy(dev, port, &results[1], fdb, cb);
1289 if (ret)
1290 return ret;
1291
1292 if (!results[0].is_valid && !results[1].is_valid)
1293 break;
1294 }
1295
1296 } while (count++ < 1024);
1297
1298 return 0;
1299}
1300
1301static int b53_br_join(struct dsa_switch *ds, int port,
1302 struct net_device *bridge)
1303{
1304 struct b53_device *dev = ds->priv;
1305 s8 cpu_port = ds->dst->cpu_port;
1306 u16 pvlan, reg;
1307 unsigned int i;
1308
1309 /* Make this port leave the all VLANs join since we will have proper
1310 * VLAN entries from now on
1311 */
1312 if (is58xx(dev)) {
1313 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1314 reg &= ~BIT(port);
1315 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1316 reg &= ~BIT(cpu_port);
1317 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1318 }
1319
1320 dev->ports[port].bridge_dev = bridge;
1321 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1322
1323 b53_for_each_port(dev, i) {
1324 if (dev->ports[i].bridge_dev != bridge)
1325 continue;
1326
1327 /* Add this local port to the remote port VLAN control
1328 * membership and update the remote port bitmask
1329 */
1330 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1331 reg |= BIT(port);
1332 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1333 dev->ports[i].vlan_ctl_mask = reg;
1334
1335 pvlan |= BIT(i);
1336 }
1337
1338 /* Configure the local port VLAN control membership to include
1339 * remote ports and update the local port bitmask
1340 */
1341 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1342 dev->ports[port].vlan_ctl_mask = pvlan;
1343
1344 return 0;
1345}
1346
1347static void b53_br_leave(struct dsa_switch *ds, int port)
1348{
1349 struct b53_device *dev = ds->priv;
1350 struct net_device *bridge = dev->ports[port].bridge_dev;
1351 struct b53_vlan *vl = &dev->vlans[0];
1352 s8 cpu_port = ds->dst->cpu_port;
1353 unsigned int i;
1354 u16 pvlan, reg, pvid;
1355
1356 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1357
1358 b53_for_each_port(dev, i) {
1359 /* Don't touch the remaining ports */
1360 if (dev->ports[i].bridge_dev != bridge)
1361 continue;
1362
1363 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1364 reg &= ~BIT(port);
1365 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1366 dev->ports[port].vlan_ctl_mask = reg;
1367
1368 /* Prevent self removal to preserve isolation */
1369 if (port != i)
1370 pvlan &= ~BIT(i);
1371 }
1372
1373 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1374 dev->ports[port].vlan_ctl_mask = pvlan;
1375 dev->ports[port].bridge_dev = NULL;
1376
1377 if (is5325(dev) || is5365(dev))
1378 pvid = 1;
1379 else
1380 pvid = 0;
1381
1382 /* Make this port join all VLANs without VLAN entries */
1383 if (is58xx(dev)) {
1384 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1385 reg |= BIT(port);
1386 if (!(reg & BIT(cpu_port)))
1387 reg |= BIT(cpu_port);
1388 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1389 } else {
1390 b53_get_vlan_entry(dev, pvid, vl);
1391 vl->members |= BIT(port) | BIT(dev->cpu_port);
1392 vl->untag |= BIT(port) | BIT(dev->cpu_port);
1393 b53_set_vlan_entry(dev, pvid, vl);
1394 }
1395}
1396
1397static void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
1398{
1399 struct b53_device *dev = ds->priv;
1400 u8 hw_state;
1401 u8 reg;
1402
1403 switch (state) {
1404 case BR_STATE_DISABLED:
1405 hw_state = PORT_CTRL_DIS_STATE;
1406 break;
1407 case BR_STATE_LISTENING:
1408 hw_state = PORT_CTRL_LISTEN_STATE;
1409 break;
1410 case BR_STATE_LEARNING:
1411 hw_state = PORT_CTRL_LEARN_STATE;
1412 break;
1413 case BR_STATE_FORWARDING:
1414 hw_state = PORT_CTRL_FWD_STATE;
1415 break;
1416 case BR_STATE_BLOCKING:
1417 hw_state = PORT_CTRL_BLOCK_STATE;
1418 break;
1419 default:
1420 dev_err(ds->dev, "invalid STP state: %d\n", state);
1421 return;
1422 }
1423
1424 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
1425 reg &= ~PORT_CTRL_STP_STATE_MASK;
1426 reg |= hw_state;
1427 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1428}
1429
1430static void b53_br_fast_age(struct dsa_switch *ds, int port)
1431{
1432 struct b53_device *dev = ds->priv;
1433
1434 if (b53_fast_age_port(dev, port))
1435 dev_err(ds->dev, "fast ageing failed\n");
1436}
1437
1438static enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds)
1439{
1440 return DSA_TAG_PROTO_NONE;
1441}
1442
1443static struct dsa_switch_ops b53_switch_ops = {
1444 .get_tag_protocol = b53_get_tag_protocol,
1445 .setup = b53_setup,
1446 .get_strings = b53_get_strings,
1447 .get_ethtool_stats = b53_get_ethtool_stats,
1448 .get_sset_count = b53_get_sset_count,
1449 .phy_read = b53_phy_read16,
1450 .phy_write = b53_phy_write16,
1451 .adjust_link = b53_adjust_link,
1452 .port_enable = b53_enable_port,
1453 .port_disable = b53_disable_port,
1454 .port_bridge_join = b53_br_join,
1455 .port_bridge_leave = b53_br_leave,
1456 .port_stp_state_set = b53_br_set_stp_state,
1457 .port_fast_age = b53_br_fast_age,
1458 .port_vlan_filtering = b53_vlan_filtering,
1459 .port_vlan_prepare = b53_vlan_prepare,
1460 .port_vlan_add = b53_vlan_add,
1461 .port_vlan_del = b53_vlan_del,
1462 .port_vlan_dump = b53_vlan_dump,
1463 .port_fdb_prepare = b53_fdb_prepare,
1464 .port_fdb_dump = b53_fdb_dump,
1465 .port_fdb_add = b53_fdb_add,
1466 .port_fdb_del = b53_fdb_del,
1467};
1468
1469struct b53_chip_data {
1470 u32 chip_id;
1471 const char *dev_name;
1472 u16 vlans;
1473 u16 enabled_ports;
1474 u8 cpu_port;
1475 u8 vta_regs[3];
1476 u8 arl_entries;
1477 u8 duplex_reg;
1478 u8 jumbo_pm_reg;
1479 u8 jumbo_size_reg;
1480};
1481
1482#define B53_VTA_REGS \
1483 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1484#define B53_VTA_REGS_9798 \
1485 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1486#define B53_VTA_REGS_63XX \
1487 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1488
1489static const struct b53_chip_data b53_switch_chips[] = {
1490 {
1491 .chip_id = BCM5325_DEVICE_ID,
1492 .dev_name = "BCM5325",
1493 .vlans = 16,
1494 .enabled_ports = 0x1f,
1495 .arl_entries = 2,
1496 .cpu_port = B53_CPU_PORT_25,
1497 .duplex_reg = B53_DUPLEX_STAT_FE,
1498 },
1499 {
1500 .chip_id = BCM5365_DEVICE_ID,
1501 .dev_name = "BCM5365",
1502 .vlans = 256,
1503 .enabled_ports = 0x1f,
1504 .arl_entries = 2,
1505 .cpu_port = B53_CPU_PORT_25,
1506 .duplex_reg = B53_DUPLEX_STAT_FE,
1507 },
1508 {
1509 .chip_id = BCM5395_DEVICE_ID,
1510 .dev_name = "BCM5395",
1511 .vlans = 4096,
1512 .enabled_ports = 0x1f,
1513 .arl_entries = 4,
1514 .cpu_port = B53_CPU_PORT,
1515 .vta_regs = B53_VTA_REGS,
1516 .duplex_reg = B53_DUPLEX_STAT_GE,
1517 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1518 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1519 },
1520 {
1521 .chip_id = BCM5397_DEVICE_ID,
1522 .dev_name = "BCM5397",
1523 .vlans = 4096,
1524 .enabled_ports = 0x1f,
1525 .arl_entries = 4,
1526 .cpu_port = B53_CPU_PORT,
1527 .vta_regs = B53_VTA_REGS_9798,
1528 .duplex_reg = B53_DUPLEX_STAT_GE,
1529 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1530 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1531 },
1532 {
1533 .chip_id = BCM5398_DEVICE_ID,
1534 .dev_name = "BCM5398",
1535 .vlans = 4096,
1536 .enabled_ports = 0x7f,
1537 .arl_entries = 4,
1538 .cpu_port = B53_CPU_PORT,
1539 .vta_regs = B53_VTA_REGS_9798,
1540 .duplex_reg = B53_DUPLEX_STAT_GE,
1541 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1542 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1543 },
1544 {
1545 .chip_id = BCM53115_DEVICE_ID,
1546 .dev_name = "BCM53115",
1547 .vlans = 4096,
1548 .enabled_ports = 0x1f,
1549 .arl_entries = 4,
1550 .vta_regs = B53_VTA_REGS,
1551 .cpu_port = B53_CPU_PORT,
1552 .duplex_reg = B53_DUPLEX_STAT_GE,
1553 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1554 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1555 },
1556 {
1557 .chip_id = BCM53125_DEVICE_ID,
1558 .dev_name = "BCM53125",
1559 .vlans = 4096,
1560 .enabled_ports = 0xff,
1561 .cpu_port = B53_CPU_PORT,
1562 .vta_regs = B53_VTA_REGS,
1563 .duplex_reg = B53_DUPLEX_STAT_GE,
1564 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1565 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1566 },
1567 {
1568 .chip_id = BCM53128_DEVICE_ID,
1569 .dev_name = "BCM53128",
1570 .vlans = 4096,
1571 .enabled_ports = 0x1ff,
1572 .arl_entries = 4,
1573 .cpu_port = B53_CPU_PORT,
1574 .vta_regs = B53_VTA_REGS,
1575 .duplex_reg = B53_DUPLEX_STAT_GE,
1576 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1577 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1578 },
1579 {
1580 .chip_id = BCM63XX_DEVICE_ID,
1581 .dev_name = "BCM63xx",
1582 .vlans = 4096,
1583 .enabled_ports = 0, /* pdata must provide them */
1584 .arl_entries = 4,
1585 .cpu_port = B53_CPU_PORT,
1586 .vta_regs = B53_VTA_REGS_63XX,
1587 .duplex_reg = B53_DUPLEX_STAT_63XX,
1588 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1589 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1590 },
1591 {
1592 .chip_id = BCM53010_DEVICE_ID,
1593 .dev_name = "BCM53010",
1594 .vlans = 4096,
1595 .enabled_ports = 0x1f,
1596 .arl_entries = 4,
1597 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1598 .vta_regs = B53_VTA_REGS,
1599 .duplex_reg = B53_DUPLEX_STAT_GE,
1600 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1601 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1602 },
1603 {
1604 .chip_id = BCM53011_DEVICE_ID,
1605 .dev_name = "BCM53011",
1606 .vlans = 4096,
1607 .enabled_ports = 0x1bf,
1608 .arl_entries = 4,
1609 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1610 .vta_regs = B53_VTA_REGS,
1611 .duplex_reg = B53_DUPLEX_STAT_GE,
1612 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1613 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1614 },
1615 {
1616 .chip_id = BCM53012_DEVICE_ID,
1617 .dev_name = "BCM53012",
1618 .vlans = 4096,
1619 .enabled_ports = 0x1bf,
1620 .arl_entries = 4,
1621 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1622 .vta_regs = B53_VTA_REGS,
1623 .duplex_reg = B53_DUPLEX_STAT_GE,
1624 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1625 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1626 },
1627 {
1628 .chip_id = BCM53018_DEVICE_ID,
1629 .dev_name = "BCM53018",
1630 .vlans = 4096,
1631 .enabled_ports = 0x1f,
1632 .arl_entries = 4,
1633 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1634 .vta_regs = B53_VTA_REGS,
1635 .duplex_reg = B53_DUPLEX_STAT_GE,
1636 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1637 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1638 },
1639 {
1640 .chip_id = BCM53019_DEVICE_ID,
1641 .dev_name = "BCM53019",
1642 .vlans = 4096,
1643 .enabled_ports = 0x1f,
1644 .arl_entries = 4,
1645 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1646 .vta_regs = B53_VTA_REGS,
1647 .duplex_reg = B53_DUPLEX_STAT_GE,
1648 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1649 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1650 },
1651 {
1652 .chip_id = BCM58XX_DEVICE_ID,
1653 .dev_name = "BCM585xx/586xx/88312",
1654 .vlans = 4096,
1655 .enabled_ports = 0x1ff,
1656 .arl_entries = 4,
1657 .cpu_port = B53_CPU_PORT_25,
1658 .vta_regs = B53_VTA_REGS,
1659 .duplex_reg = B53_DUPLEX_STAT_GE,
1660 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1661 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1662 },
1663 {
1664 .chip_id = BCM7445_DEVICE_ID,
1665 .dev_name = "BCM7445",
1666 .vlans = 4096,
1667 .enabled_ports = 0x1ff,
1668 .arl_entries = 4,
1669 .cpu_port = B53_CPU_PORT,
1670 .vta_regs = B53_VTA_REGS,
1671 .duplex_reg = B53_DUPLEX_STAT_GE,
1672 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1673 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1674 },
1675};
1676
1677static int b53_switch_init(struct b53_device *dev)
1678{
1679 unsigned int i;
1680 int ret;
1681
1682 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1683 const struct b53_chip_data *chip = &b53_switch_chips[i];
1684
1685 if (chip->chip_id == dev->chip_id) {
1686 if (!dev->enabled_ports)
1687 dev->enabled_ports = chip->enabled_ports;
1688 dev->name = chip->dev_name;
1689 dev->duplex_reg = chip->duplex_reg;
1690 dev->vta_regs[0] = chip->vta_regs[0];
1691 dev->vta_regs[1] = chip->vta_regs[1];
1692 dev->vta_regs[2] = chip->vta_regs[2];
1693 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
1694 dev->cpu_port = chip->cpu_port;
1695 dev->num_vlans = chip->vlans;
1696 dev->num_arl_entries = chip->arl_entries;
1697 break;
1698 }
1699 }
1700
1701 /* check which BCM5325x version we have */
1702 if (is5325(dev)) {
1703 u8 vc4;
1704
1705 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1706
1707 /* check reserved bits */
1708 switch (vc4 & 3) {
1709 case 1:
1710 /* BCM5325E */
1711 break;
1712 case 3:
1713 /* BCM5325F - do not use port 4 */
1714 dev->enabled_ports &= ~BIT(4);
1715 break;
1716 default:
1717/* On the BCM47XX SoCs this is the supported internal switch.*/
1718#ifndef CONFIG_BCM47XX
1719 /* BCM5325M */
1720 return -EINVAL;
1721#else
1722 break;
1723#endif
1724 }
1725 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1726 u64 strap_value;
1727
1728 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1729 /* use second IMP port if GMII is enabled */
1730 if (strap_value & SV_GMII_CTRL_115)
1731 dev->cpu_port = 5;
1732 }
1733
1734 /* cpu port is always last */
1735 dev->num_ports = dev->cpu_port + 1;
1736 dev->enabled_ports |= BIT(dev->cpu_port);
1737
1738 dev->ports = devm_kzalloc(dev->dev,
1739 sizeof(struct b53_port) * dev->num_ports,
1740 GFP_KERNEL);
1741 if (!dev->ports)
1742 return -ENOMEM;
1743
1744 dev->vlans = devm_kzalloc(dev->dev,
1745 sizeof(struct b53_vlan) * dev->num_vlans,
1746 GFP_KERNEL);
1747 if (!dev->vlans)
1748 return -ENOMEM;
1749
1750 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1751 if (dev->reset_gpio >= 0) {
1752 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1753 GPIOF_OUT_INIT_HIGH, "robo_reset");
1754 if (ret)
1755 return ret;
1756 }
1757
1758 return 0;
1759}
1760
1761struct b53_device *b53_switch_alloc(struct device *base,
1762 const struct b53_io_ops *ops,
1763 void *priv)
1764{
1765 struct dsa_switch *ds;
1766 struct b53_device *dev;
1767
1768 ds = devm_kzalloc(base, sizeof(*ds) + sizeof(*dev), GFP_KERNEL);
1769 if (!ds)
1770 return NULL;
1771
1772 dev = (struct b53_device *)(ds + 1);
1773
1774 ds->priv = dev;
1775 ds->dev = base;
1776 dev->dev = base;
1777
1778 dev->ds = ds;
1779 dev->priv = priv;
1780 dev->ops = ops;
1781 ds->ops = &b53_switch_ops;
1782 mutex_init(&dev->reg_mutex);
1783 mutex_init(&dev->stats_mutex);
1784
1785 return dev;
1786}
1787EXPORT_SYMBOL(b53_switch_alloc);
1788
1789int b53_switch_detect(struct b53_device *dev)
1790{
1791 u32 id32;
1792 u16 tmp;
1793 u8 id8;
1794 int ret;
1795
1796 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1797 if (ret)
1798 return ret;
1799
1800 switch (id8) {
1801 case 0:
1802 /* BCM5325 and BCM5365 do not have this register so reads
1803 * return 0. But the read operation did succeed, so assume this
1804 * is one of them.
1805 *
1806 * Next check if we can write to the 5325's VTA register; for
1807 * 5365 it is read only.
1808 */
1809 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
1810 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
1811
1812 if (tmp == 0xf)
1813 dev->chip_id = BCM5325_DEVICE_ID;
1814 else
1815 dev->chip_id = BCM5365_DEVICE_ID;
1816 break;
1817 case BCM5395_DEVICE_ID:
1818 case BCM5397_DEVICE_ID:
1819 case BCM5398_DEVICE_ID:
1820 dev->chip_id = id8;
1821 break;
1822 default:
1823 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
1824 if (ret)
1825 return ret;
1826
1827 switch (id32) {
1828 case BCM53115_DEVICE_ID:
1829 case BCM53125_DEVICE_ID:
1830 case BCM53128_DEVICE_ID:
1831 case BCM53010_DEVICE_ID:
1832 case BCM53011_DEVICE_ID:
1833 case BCM53012_DEVICE_ID:
1834 case BCM53018_DEVICE_ID:
1835 case BCM53019_DEVICE_ID:
1836 dev->chip_id = id32;
1837 break;
1838 default:
1839 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1840 id8, id32);
1841 return -ENODEV;
1842 }
1843 }
1844
1845 if (dev->chip_id == BCM5325_DEVICE_ID)
1846 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
1847 &dev->core_rev);
1848 else
1849 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
1850 &dev->core_rev);
1851}
1852EXPORT_SYMBOL(b53_switch_detect);
1853
1854int b53_switch_register(struct b53_device *dev)
1855{
1856 int ret;
1857
1858 if (dev->pdata) {
1859 dev->chip_id = dev->pdata->chip_id;
1860 dev->enabled_ports = dev->pdata->enabled_ports;
1861 }
1862
1863 if (!dev->chip_id && b53_switch_detect(dev))
1864 return -EINVAL;
1865
1866 ret = b53_switch_init(dev);
1867 if (ret)
1868 return ret;
1869
1870 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
1871
1872 return dsa_register_switch(dev->ds, dev->ds->dev->of_node);
1873}
1874EXPORT_SYMBOL(b53_switch_register);
1875
1876MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1877MODULE_DESCRIPTION("B53 switch library");
1878MODULE_LICENSE("Dual BSD/GPL");
1/*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#include <linux/delay.h>
21#include <linux/export.h>
22#include <linux/gpio.h>
23#include <linux/kernel.h>
24#include <linux/module.h>
25#include <linux/platform_data/b53.h>
26#include <linux/phy.h>
27#include <linux/phylink.h>
28#include <linux/etherdevice.h>
29#include <linux/if_bridge.h>
30#include <net/dsa.h>
31
32#include "b53_regs.h"
33#include "b53_priv.h"
34
35struct b53_mib_desc {
36 u8 size;
37 u8 offset;
38 const char *name;
39};
40
41/* BCM5365 MIB counters */
42static const struct b53_mib_desc b53_mibs_65[] = {
43 { 8, 0x00, "TxOctets" },
44 { 4, 0x08, "TxDropPkts" },
45 { 4, 0x10, "TxBroadcastPkts" },
46 { 4, 0x14, "TxMulticastPkts" },
47 { 4, 0x18, "TxUnicastPkts" },
48 { 4, 0x1c, "TxCollisions" },
49 { 4, 0x20, "TxSingleCollision" },
50 { 4, 0x24, "TxMultipleCollision" },
51 { 4, 0x28, "TxDeferredTransmit" },
52 { 4, 0x2c, "TxLateCollision" },
53 { 4, 0x30, "TxExcessiveCollision" },
54 { 4, 0x38, "TxPausePkts" },
55 { 8, 0x44, "RxOctets" },
56 { 4, 0x4c, "RxUndersizePkts" },
57 { 4, 0x50, "RxPausePkts" },
58 { 4, 0x54, "Pkts64Octets" },
59 { 4, 0x58, "Pkts65to127Octets" },
60 { 4, 0x5c, "Pkts128to255Octets" },
61 { 4, 0x60, "Pkts256to511Octets" },
62 { 4, 0x64, "Pkts512to1023Octets" },
63 { 4, 0x68, "Pkts1024to1522Octets" },
64 { 4, 0x6c, "RxOversizePkts" },
65 { 4, 0x70, "RxJabbers" },
66 { 4, 0x74, "RxAlignmentErrors" },
67 { 4, 0x78, "RxFCSErrors" },
68 { 8, 0x7c, "RxGoodOctets" },
69 { 4, 0x84, "RxDropPkts" },
70 { 4, 0x88, "RxUnicastPkts" },
71 { 4, 0x8c, "RxMulticastPkts" },
72 { 4, 0x90, "RxBroadcastPkts" },
73 { 4, 0x94, "RxSAChanges" },
74 { 4, 0x98, "RxFragments" },
75};
76
77#define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
78
79/* BCM63xx MIB counters */
80static const struct b53_mib_desc b53_mibs_63xx[] = {
81 { 8, 0x00, "TxOctets" },
82 { 4, 0x08, "TxDropPkts" },
83 { 4, 0x0c, "TxQoSPkts" },
84 { 4, 0x10, "TxBroadcastPkts" },
85 { 4, 0x14, "TxMulticastPkts" },
86 { 4, 0x18, "TxUnicastPkts" },
87 { 4, 0x1c, "TxCollisions" },
88 { 4, 0x20, "TxSingleCollision" },
89 { 4, 0x24, "TxMultipleCollision" },
90 { 4, 0x28, "TxDeferredTransmit" },
91 { 4, 0x2c, "TxLateCollision" },
92 { 4, 0x30, "TxExcessiveCollision" },
93 { 4, 0x38, "TxPausePkts" },
94 { 8, 0x3c, "TxQoSOctets" },
95 { 8, 0x44, "RxOctets" },
96 { 4, 0x4c, "RxUndersizePkts" },
97 { 4, 0x50, "RxPausePkts" },
98 { 4, 0x54, "Pkts64Octets" },
99 { 4, 0x58, "Pkts65to127Octets" },
100 { 4, 0x5c, "Pkts128to255Octets" },
101 { 4, 0x60, "Pkts256to511Octets" },
102 { 4, 0x64, "Pkts512to1023Octets" },
103 { 4, 0x68, "Pkts1024to1522Octets" },
104 { 4, 0x6c, "RxOversizePkts" },
105 { 4, 0x70, "RxJabbers" },
106 { 4, 0x74, "RxAlignmentErrors" },
107 { 4, 0x78, "RxFCSErrors" },
108 { 8, 0x7c, "RxGoodOctets" },
109 { 4, 0x84, "RxDropPkts" },
110 { 4, 0x88, "RxUnicastPkts" },
111 { 4, 0x8c, "RxMulticastPkts" },
112 { 4, 0x90, "RxBroadcastPkts" },
113 { 4, 0x94, "RxSAChanges" },
114 { 4, 0x98, "RxFragments" },
115 { 4, 0xa0, "RxSymbolErrors" },
116 { 4, 0xa4, "RxQoSPkts" },
117 { 8, 0xa8, "RxQoSOctets" },
118 { 4, 0xb0, "Pkts1523to2047Octets" },
119 { 4, 0xb4, "Pkts2048to4095Octets" },
120 { 4, 0xb8, "Pkts4096to8191Octets" },
121 { 4, 0xbc, "Pkts8192to9728Octets" },
122 { 4, 0xc0, "RxDiscarded" },
123};
124
125#define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
126
127/* MIB counters */
128static const struct b53_mib_desc b53_mibs[] = {
129 { 8, 0x00, "TxOctets" },
130 { 4, 0x08, "TxDropPkts" },
131 { 4, 0x10, "TxBroadcastPkts" },
132 { 4, 0x14, "TxMulticastPkts" },
133 { 4, 0x18, "TxUnicastPkts" },
134 { 4, 0x1c, "TxCollisions" },
135 { 4, 0x20, "TxSingleCollision" },
136 { 4, 0x24, "TxMultipleCollision" },
137 { 4, 0x28, "TxDeferredTransmit" },
138 { 4, 0x2c, "TxLateCollision" },
139 { 4, 0x30, "TxExcessiveCollision" },
140 { 4, 0x38, "TxPausePkts" },
141 { 8, 0x50, "RxOctets" },
142 { 4, 0x58, "RxUndersizePkts" },
143 { 4, 0x5c, "RxPausePkts" },
144 { 4, 0x60, "Pkts64Octets" },
145 { 4, 0x64, "Pkts65to127Octets" },
146 { 4, 0x68, "Pkts128to255Octets" },
147 { 4, 0x6c, "Pkts256to511Octets" },
148 { 4, 0x70, "Pkts512to1023Octets" },
149 { 4, 0x74, "Pkts1024to1522Octets" },
150 { 4, 0x78, "RxOversizePkts" },
151 { 4, 0x7c, "RxJabbers" },
152 { 4, 0x80, "RxAlignmentErrors" },
153 { 4, 0x84, "RxFCSErrors" },
154 { 8, 0x88, "RxGoodOctets" },
155 { 4, 0x90, "RxDropPkts" },
156 { 4, 0x94, "RxUnicastPkts" },
157 { 4, 0x98, "RxMulticastPkts" },
158 { 4, 0x9c, "RxBroadcastPkts" },
159 { 4, 0xa0, "RxSAChanges" },
160 { 4, 0xa4, "RxFragments" },
161 { 4, 0xa8, "RxJumboPkts" },
162 { 4, 0xac, "RxSymbolErrors" },
163 { 4, 0xc0, "RxDiscarded" },
164};
165
166#define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
167
168static const struct b53_mib_desc b53_mibs_58xx[] = {
169 { 8, 0x00, "TxOctets" },
170 { 4, 0x08, "TxDropPkts" },
171 { 4, 0x0c, "TxQPKTQ0" },
172 { 4, 0x10, "TxBroadcastPkts" },
173 { 4, 0x14, "TxMulticastPkts" },
174 { 4, 0x18, "TxUnicastPKts" },
175 { 4, 0x1c, "TxCollisions" },
176 { 4, 0x20, "TxSingleCollision" },
177 { 4, 0x24, "TxMultipleCollision" },
178 { 4, 0x28, "TxDeferredCollision" },
179 { 4, 0x2c, "TxLateCollision" },
180 { 4, 0x30, "TxExcessiveCollision" },
181 { 4, 0x34, "TxFrameInDisc" },
182 { 4, 0x38, "TxPausePkts" },
183 { 4, 0x3c, "TxQPKTQ1" },
184 { 4, 0x40, "TxQPKTQ2" },
185 { 4, 0x44, "TxQPKTQ3" },
186 { 4, 0x48, "TxQPKTQ4" },
187 { 4, 0x4c, "TxQPKTQ5" },
188 { 8, 0x50, "RxOctets" },
189 { 4, 0x58, "RxUndersizePkts" },
190 { 4, 0x5c, "RxPausePkts" },
191 { 4, 0x60, "RxPkts64Octets" },
192 { 4, 0x64, "RxPkts65to127Octets" },
193 { 4, 0x68, "RxPkts128to255Octets" },
194 { 4, 0x6c, "RxPkts256to511Octets" },
195 { 4, 0x70, "RxPkts512to1023Octets" },
196 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
197 { 4, 0x78, "RxOversizePkts" },
198 { 4, 0x7c, "RxJabbers" },
199 { 4, 0x80, "RxAlignmentErrors" },
200 { 4, 0x84, "RxFCSErrors" },
201 { 8, 0x88, "RxGoodOctets" },
202 { 4, 0x90, "RxDropPkts" },
203 { 4, 0x94, "RxUnicastPkts" },
204 { 4, 0x98, "RxMulticastPkts" },
205 { 4, 0x9c, "RxBroadcastPkts" },
206 { 4, 0xa0, "RxSAChanges" },
207 { 4, 0xa4, "RxFragments" },
208 { 4, 0xa8, "RxJumboPkt" },
209 { 4, 0xac, "RxSymblErr" },
210 { 4, 0xb0, "InRangeErrCount" },
211 { 4, 0xb4, "OutRangeErrCount" },
212 { 4, 0xb8, "EEELpiEvent" },
213 { 4, 0xbc, "EEELpiDuration" },
214 { 4, 0xc0, "RxDiscard" },
215 { 4, 0xc8, "TxQPKTQ6" },
216 { 4, 0xcc, "TxQPKTQ7" },
217 { 4, 0xd0, "TxPkts64Octets" },
218 { 4, 0xd4, "TxPkts65to127Octets" },
219 { 4, 0xd8, "TxPkts128to255Octets" },
220 { 4, 0xdc, "TxPkts256to511Ocets" },
221 { 4, 0xe0, "TxPkts512to1023Ocets" },
222 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
223};
224
225#define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
226
227static int b53_do_vlan_op(struct b53_device *dev, u8 op)
228{
229 unsigned int i;
230
231 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
232
233 for (i = 0; i < 10; i++) {
234 u8 vta;
235
236 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
237 if (!(vta & VTA_START_CMD))
238 return 0;
239
240 usleep_range(100, 200);
241 }
242
243 return -EIO;
244}
245
246static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
247 struct b53_vlan *vlan)
248{
249 if (is5325(dev)) {
250 u32 entry = 0;
251
252 if (vlan->members) {
253 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
254 VA_UNTAG_S_25) | vlan->members;
255 if (dev->core_rev >= 3)
256 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
257 else
258 entry |= VA_VALID_25;
259 }
260
261 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
262 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
263 VTA_RW_STATE_WR | VTA_RW_OP_EN);
264 } else if (is5365(dev)) {
265 u16 entry = 0;
266
267 if (vlan->members)
268 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
269 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
270
271 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
273 VTA_RW_STATE_WR | VTA_RW_OP_EN);
274 } else {
275 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
276 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
277 (vlan->untag << VTE_UNTAG_S) | vlan->members);
278
279 b53_do_vlan_op(dev, VTA_CMD_WRITE);
280 }
281
282 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
283 vid, vlan->members, vlan->untag);
284}
285
286static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
287 struct b53_vlan *vlan)
288{
289 if (is5325(dev)) {
290 u32 entry = 0;
291
292 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
293 VTA_RW_STATE_RD | VTA_RW_OP_EN);
294 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
295
296 if (dev->core_rev >= 3)
297 vlan->valid = !!(entry & VA_VALID_25_R4);
298 else
299 vlan->valid = !!(entry & VA_VALID_25);
300 vlan->members = entry & VA_MEMBER_MASK;
301 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
302
303 } else if (is5365(dev)) {
304 u16 entry = 0;
305
306 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
307 VTA_RW_STATE_WR | VTA_RW_OP_EN);
308 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
309
310 vlan->valid = !!(entry & VA_VALID_65);
311 vlan->members = entry & VA_MEMBER_MASK;
312 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
313 } else {
314 u32 entry = 0;
315
316 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
317 b53_do_vlan_op(dev, VTA_CMD_READ);
318 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
319 vlan->members = entry & VTE_MEMBERS;
320 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
321 vlan->valid = true;
322 }
323}
324
325static void b53_set_forwarding(struct b53_device *dev, int enable)
326{
327 u8 mgmt;
328
329 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
330
331 if (enable)
332 mgmt |= SM_SW_FWD_EN;
333 else
334 mgmt &= ~SM_SW_FWD_EN;
335
336 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
337
338 /* Include IMP port in dumb forwarding mode
339 */
340 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
341 mgmt |= B53_MII_DUMB_FWDG_EN;
342 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
343
344 /* Look at B53_UC_FWD_EN and B53_MC_FWD_EN to decide whether
345 * frames should be flooded or not.
346 */
347 b53_read8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, &mgmt);
348 mgmt |= B53_UC_FWD_EN | B53_MC_FWD_EN | B53_IPMC_FWD_EN;
349 b53_write8(dev, B53_CTRL_PAGE, B53_IP_MULTICAST_CTRL, mgmt);
350}
351
352static void b53_enable_vlan(struct b53_device *dev, int port, bool enable,
353 bool enable_filtering)
354{
355 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
356
357 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
358 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
360
361 if (is5325(dev) || is5365(dev)) {
362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
363 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
364 } else if (is63xx(dev)) {
365 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
366 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
367 } else {
368 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
369 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
370 }
371
372 if (enable) {
373 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
374 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
375 vc4 &= ~VC4_ING_VID_CHECK_MASK;
376 if (enable_filtering) {
377 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
378 vc5 |= VC5_DROP_VTABLE_MISS;
379 } else {
380 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
381 vc5 &= ~VC5_DROP_VTABLE_MISS;
382 }
383
384 if (is5325(dev))
385 vc0 &= ~VC0_RESERVED_1;
386
387 if (is5325(dev) || is5365(dev))
388 vc1 |= VC1_RX_MCST_TAG_EN;
389
390 } else {
391 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
392 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
393 vc4 &= ~VC4_ING_VID_CHECK_MASK;
394 vc5 &= ~VC5_DROP_VTABLE_MISS;
395
396 if (is5325(dev) || is5365(dev))
397 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
398 else
399 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
400
401 if (is5325(dev) || is5365(dev))
402 vc1 &= ~VC1_RX_MCST_TAG_EN;
403 }
404
405 if (!is5325(dev) && !is5365(dev))
406 vc5 &= ~VC5_VID_FFF_EN;
407
408 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
409 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
410
411 if (is5325(dev) || is5365(dev)) {
412 /* enable the high 8 bit vid check on 5325 */
413 if (is5325(dev) && enable)
414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
415 VC3_HIGH_8BIT_EN);
416 else
417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
418
419 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
420 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
421 } else if (is63xx(dev)) {
422 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
423 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
424 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
425 } else {
426 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
427 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
428 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
429 }
430
431 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
432
433 dev->vlan_enabled = enable;
434
435 dev_dbg(dev->dev, "Port %d VLAN enabled: %d, filtering: %d\n",
436 port, enable, enable_filtering);
437}
438
439static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
440{
441 u32 port_mask = 0;
442 u16 max_size = JMS_MIN_SIZE;
443
444 if (is5325(dev) || is5365(dev))
445 return -EINVAL;
446
447 if (enable) {
448 port_mask = dev->enabled_ports;
449 max_size = JMS_MAX_SIZE;
450 if (allow_10_100)
451 port_mask |= JPM_10_100_JUMBO_EN;
452 }
453
454 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
455 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
456}
457
458static int b53_flush_arl(struct b53_device *dev, u8 mask)
459{
460 unsigned int i;
461
462 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
463 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
464
465 for (i = 0; i < 10; i++) {
466 u8 fast_age_ctrl;
467
468 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
469 &fast_age_ctrl);
470
471 if (!(fast_age_ctrl & FAST_AGE_DONE))
472 goto out;
473
474 msleep(1);
475 }
476
477 return -ETIMEDOUT;
478out:
479 /* Only age dynamic entries (default behavior) */
480 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
481 return 0;
482}
483
484static int b53_fast_age_port(struct b53_device *dev, int port)
485{
486 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
487
488 return b53_flush_arl(dev, FAST_AGE_PORT);
489}
490
491static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
492{
493 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
494
495 return b53_flush_arl(dev, FAST_AGE_VLAN);
496}
497
498void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
499{
500 struct b53_device *dev = ds->priv;
501 unsigned int i;
502 u16 pvlan;
503
504 /* Enable the IMP port to be in the same VLAN as the other ports
505 * on a per-port basis such that we only have Port i and IMP in
506 * the same VLAN.
507 */
508 b53_for_each_port(dev, i) {
509 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
510 pvlan |= BIT(cpu_port);
511 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
512 }
513}
514EXPORT_SYMBOL(b53_imp_vlan_setup);
515
516static void b53_port_set_ucast_flood(struct b53_device *dev, int port,
517 bool unicast)
518{
519 u16 uc;
520
521 b53_read16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, &uc);
522 if (unicast)
523 uc |= BIT(port);
524 else
525 uc &= ~BIT(port);
526 b53_write16(dev, B53_CTRL_PAGE, B53_UC_FLOOD_MASK, uc);
527}
528
529static void b53_port_set_mcast_flood(struct b53_device *dev, int port,
530 bool multicast)
531{
532 u16 mc;
533
534 b53_read16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, &mc);
535 if (multicast)
536 mc |= BIT(port);
537 else
538 mc &= ~BIT(port);
539 b53_write16(dev, B53_CTRL_PAGE, B53_MC_FLOOD_MASK, mc);
540
541 b53_read16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, &mc);
542 if (multicast)
543 mc |= BIT(port);
544 else
545 mc &= ~BIT(port);
546 b53_write16(dev, B53_CTRL_PAGE, B53_IPMC_FLOOD_MASK, mc);
547}
548
549static void b53_port_set_learning(struct b53_device *dev, int port,
550 bool learning)
551{
552 u16 reg;
553
554 b53_read16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, ®);
555 if (learning)
556 reg &= ~BIT(port);
557 else
558 reg |= BIT(port);
559 b53_write16(dev, B53_CTRL_PAGE, B53_DIS_LEARNING, reg);
560}
561
562static void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
563{
564 struct b53_device *dev = ds->priv;
565 u16 reg;
566
567 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®);
568 if (enable)
569 reg |= BIT(port);
570 else
571 reg &= ~BIT(port);
572 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
573}
574
575int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
576{
577 struct b53_device *dev = ds->priv;
578 unsigned int cpu_port;
579 int ret = 0;
580 u16 pvlan;
581
582 if (!dsa_is_user_port(ds, port))
583 return 0;
584
585 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
586
587 b53_port_set_ucast_flood(dev, port, true);
588 b53_port_set_mcast_flood(dev, port, true);
589 b53_port_set_learning(dev, port, false);
590
591 if (dev->ops->irq_enable)
592 ret = dev->ops->irq_enable(dev, port);
593 if (ret)
594 return ret;
595
596 /* Clear the Rx and Tx disable bits and set to no spanning tree */
597 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
598
599 /* Set this port, and only this one to be in the default VLAN,
600 * if member of a bridge, restore its membership prior to
601 * bringing down this port.
602 */
603 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
604 pvlan &= ~0x1ff;
605 pvlan |= BIT(port);
606 pvlan |= dev->ports[port].vlan_ctl_mask;
607 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
608
609 b53_imp_vlan_setup(ds, cpu_port);
610
611 /* If EEE was enabled, restore it */
612 if (dev->ports[port].eee.eee_enabled)
613 b53_eee_enable_set(ds, port, true);
614
615 return 0;
616}
617EXPORT_SYMBOL(b53_enable_port);
618
619void b53_disable_port(struct dsa_switch *ds, int port)
620{
621 struct b53_device *dev = ds->priv;
622 u8 reg;
623
624 /* Disable Tx/Rx for the port */
625 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
626 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
627 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
628
629 if (dev->ops->irq_disable)
630 dev->ops->irq_disable(dev, port);
631}
632EXPORT_SYMBOL(b53_disable_port);
633
634void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
635{
636 struct b53_device *dev = ds->priv;
637 bool tag_en = !(dev->tag_protocol == DSA_TAG_PROTO_NONE);
638 u8 hdr_ctl, val;
639 u16 reg;
640
641 /* Resolve which bit controls the Broadcom tag */
642 switch (port) {
643 case 8:
644 val = BRCM_HDR_P8_EN;
645 break;
646 case 7:
647 val = BRCM_HDR_P7_EN;
648 break;
649 case 5:
650 val = BRCM_HDR_P5_EN;
651 break;
652 default:
653 val = 0;
654 break;
655 }
656
657 /* Enable management mode if tagging is requested */
658 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &hdr_ctl);
659 if (tag_en)
660 hdr_ctl |= SM_SW_FWD_MODE;
661 else
662 hdr_ctl &= ~SM_SW_FWD_MODE;
663 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, hdr_ctl);
664
665 /* Configure the appropriate IMP port */
666 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &hdr_ctl);
667 if (port == 8)
668 hdr_ctl |= GC_FRM_MGMT_PORT_MII;
669 else if (port == 5)
670 hdr_ctl |= GC_FRM_MGMT_PORT_M;
671 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, hdr_ctl);
672
673 /* Enable Broadcom tags for IMP port */
674 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
675 if (tag_en)
676 hdr_ctl |= val;
677 else
678 hdr_ctl &= ~val;
679 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
680
681 /* Registers below are only accessible on newer devices */
682 if (!is58xx(dev))
683 return;
684
685 /* Enable reception Broadcom tag for CPU TX (switch RX) to
686 * allow us to tag outgoing frames
687 */
688 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®);
689 if (tag_en)
690 reg &= ~BIT(port);
691 else
692 reg |= BIT(port);
693 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
694
695 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
696 * allow delivering frames to the per-port net_devices
697 */
698 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®);
699 if (tag_en)
700 reg &= ~BIT(port);
701 else
702 reg |= BIT(port);
703 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
704}
705EXPORT_SYMBOL(b53_brcm_hdr_setup);
706
707static void b53_enable_cpu_port(struct b53_device *dev, int port)
708{
709 u8 port_ctrl;
710
711 /* BCM5325 CPU port is at 8 */
712 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
713 port = B53_CPU_PORT;
714
715 port_ctrl = PORT_CTRL_RX_BCST_EN |
716 PORT_CTRL_RX_MCST_EN |
717 PORT_CTRL_RX_UCST_EN;
718 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
719
720 b53_brcm_hdr_setup(dev->ds, port);
721
722 b53_port_set_ucast_flood(dev, port, true);
723 b53_port_set_mcast_flood(dev, port, true);
724 b53_port_set_learning(dev, port, false);
725}
726
727static void b53_enable_mib(struct b53_device *dev)
728{
729 u8 gc;
730
731 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
732 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
733 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
734}
735
736static u16 b53_default_pvid(struct b53_device *dev)
737{
738 if (is5325(dev) || is5365(dev))
739 return 1;
740 else
741 return 0;
742}
743
744static bool b53_vlan_port_needs_forced_tagged(struct dsa_switch *ds, int port)
745{
746 struct b53_device *dev = ds->priv;
747
748 return dev->tag_protocol == DSA_TAG_PROTO_NONE && dsa_is_cpu_port(ds, port);
749}
750
751int b53_configure_vlan(struct dsa_switch *ds)
752{
753 struct b53_device *dev = ds->priv;
754 struct b53_vlan vl = { 0 };
755 struct b53_vlan *v;
756 int i, def_vid;
757 u16 vid;
758
759 def_vid = b53_default_pvid(dev);
760
761 /* clear all vlan entries */
762 if (is5325(dev) || is5365(dev)) {
763 for (i = def_vid; i < dev->num_vlans; i++)
764 b53_set_vlan_entry(dev, i, &vl);
765 } else {
766 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
767 }
768
769 b53_enable_vlan(dev, -1, dev->vlan_enabled, ds->vlan_filtering);
770
771 /* Create an untagged VLAN entry for the default PVID in case
772 * CONFIG_VLAN_8021Q is disabled and there are no calls to
773 * dsa_user_vlan_rx_add_vid() to create the default VLAN
774 * entry. Do this only when the tagging protocol is not
775 * DSA_TAG_PROTO_NONE
776 */
777 b53_for_each_port(dev, i) {
778 v = &dev->vlans[def_vid];
779 v->members |= BIT(i);
780 if (!b53_vlan_port_needs_forced_tagged(ds, i))
781 v->untag = v->members;
782 b53_write16(dev, B53_VLAN_PAGE,
783 B53_VLAN_PORT_DEF_TAG(i), def_vid);
784 }
785
786 /* Upon initial call we have not set-up any VLANs, but upon
787 * system resume, we need to restore all VLAN entries.
788 */
789 for (vid = def_vid; vid < dev->num_vlans; vid++) {
790 v = &dev->vlans[vid];
791
792 if (!v->members)
793 continue;
794
795 b53_set_vlan_entry(dev, vid, v);
796 b53_fast_age_vlan(dev, vid);
797 }
798
799 return 0;
800}
801EXPORT_SYMBOL(b53_configure_vlan);
802
803static void b53_switch_reset_gpio(struct b53_device *dev)
804{
805 int gpio = dev->reset_gpio;
806
807 if (gpio < 0)
808 return;
809
810 /* Reset sequence: RESET low(50ms)->high(20ms)
811 */
812 gpio_set_value(gpio, 0);
813 mdelay(50);
814
815 gpio_set_value(gpio, 1);
816 mdelay(20);
817
818 dev->current_page = 0xff;
819}
820
821static int b53_switch_reset(struct b53_device *dev)
822{
823 unsigned int timeout = 1000;
824 u8 mgmt, reg;
825
826 b53_switch_reset_gpio(dev);
827
828 if (is539x(dev)) {
829 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
830 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
831 }
832
833 /* This is specific to 58xx devices here, do not use is58xx() which
834 * covers the larger Starfigther 2 family, including 7445/7278 which
835 * still use this driver as a library and need to perform the reset
836 * earlier.
837 */
838 if (dev->chip_id == BCM58XX_DEVICE_ID ||
839 dev->chip_id == BCM583XX_DEVICE_ID) {
840 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
841 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
842 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
843
844 do {
845 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
846 if (!(reg & SW_RST))
847 break;
848
849 usleep_range(1000, 2000);
850 } while (timeout-- > 0);
851
852 if (timeout == 0) {
853 dev_err(dev->dev,
854 "Timeout waiting for SW_RST to clear!\n");
855 return -ETIMEDOUT;
856 }
857 }
858
859 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
860
861 if (!(mgmt & SM_SW_FWD_EN)) {
862 mgmt &= ~SM_SW_FWD_MODE;
863 mgmt |= SM_SW_FWD_EN;
864
865 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
866 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
867
868 if (!(mgmt & SM_SW_FWD_EN)) {
869 dev_err(dev->dev, "Failed to enable switch!\n");
870 return -EINVAL;
871 }
872 }
873
874 b53_enable_mib(dev);
875
876 return b53_flush_arl(dev, FAST_AGE_STATIC);
877}
878
879static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
880{
881 struct b53_device *priv = ds->priv;
882 u16 value = 0;
883 int ret;
884
885 if (priv->ops->phy_read16)
886 ret = priv->ops->phy_read16(priv, addr, reg, &value);
887 else
888 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
889 reg * 2, &value);
890
891 return ret ? ret : value;
892}
893
894static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
895{
896 struct b53_device *priv = ds->priv;
897
898 if (priv->ops->phy_write16)
899 return priv->ops->phy_write16(priv, addr, reg, val);
900
901 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
902}
903
904static int b53_reset_switch(struct b53_device *priv)
905{
906 /* reset vlans */
907 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
908 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
909
910 priv->serdes_lane = B53_INVALID_LANE;
911
912 return b53_switch_reset(priv);
913}
914
915static int b53_apply_config(struct b53_device *priv)
916{
917 /* disable switching */
918 b53_set_forwarding(priv, 0);
919
920 b53_configure_vlan(priv->ds);
921
922 /* enable switching */
923 b53_set_forwarding(priv, 1);
924
925 return 0;
926}
927
928static void b53_reset_mib(struct b53_device *priv)
929{
930 u8 gc;
931
932 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
933
934 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
935 msleep(1);
936 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
937 msleep(1);
938}
939
940static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
941{
942 if (is5365(dev))
943 return b53_mibs_65;
944 else if (is63xx(dev))
945 return b53_mibs_63xx;
946 else if (is58xx(dev))
947 return b53_mibs_58xx;
948 else
949 return b53_mibs;
950}
951
952static unsigned int b53_get_mib_size(struct b53_device *dev)
953{
954 if (is5365(dev))
955 return B53_MIBS_65_SIZE;
956 else if (is63xx(dev))
957 return B53_MIBS_63XX_SIZE;
958 else if (is58xx(dev))
959 return B53_MIBS_58XX_SIZE;
960 else
961 return B53_MIBS_SIZE;
962}
963
964static struct phy_device *b53_get_phy_device(struct dsa_switch *ds, int port)
965{
966 /* These ports typically do not have built-in PHYs */
967 switch (port) {
968 case B53_CPU_PORT_25:
969 case 7:
970 case B53_CPU_PORT:
971 return NULL;
972 }
973
974 return mdiobus_get_phy(ds->user_mii_bus, port);
975}
976
977void b53_get_strings(struct dsa_switch *ds, int port, u32 stringset,
978 uint8_t *data)
979{
980 struct b53_device *dev = ds->priv;
981 const struct b53_mib_desc *mibs = b53_get_mib(dev);
982 unsigned int mib_size = b53_get_mib_size(dev);
983 struct phy_device *phydev;
984 unsigned int i;
985
986 if (stringset == ETH_SS_STATS) {
987 for (i = 0; i < mib_size; i++)
988 strscpy(data + i * ETH_GSTRING_LEN,
989 mibs[i].name, ETH_GSTRING_LEN);
990 } else if (stringset == ETH_SS_PHY_STATS) {
991 phydev = b53_get_phy_device(ds, port);
992 if (!phydev)
993 return;
994
995 phy_ethtool_get_strings(phydev, data);
996 }
997}
998EXPORT_SYMBOL(b53_get_strings);
999
1000void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
1001{
1002 struct b53_device *dev = ds->priv;
1003 const struct b53_mib_desc *mibs = b53_get_mib(dev);
1004 unsigned int mib_size = b53_get_mib_size(dev);
1005 const struct b53_mib_desc *s;
1006 unsigned int i;
1007 u64 val = 0;
1008
1009 if (is5365(dev) && port == 5)
1010 port = 8;
1011
1012 mutex_lock(&dev->stats_mutex);
1013
1014 for (i = 0; i < mib_size; i++) {
1015 s = &mibs[i];
1016
1017 if (s->size == 8) {
1018 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
1019 } else {
1020 u32 val32;
1021
1022 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
1023 &val32);
1024 val = val32;
1025 }
1026 data[i] = (u64)val;
1027 }
1028
1029 mutex_unlock(&dev->stats_mutex);
1030}
1031EXPORT_SYMBOL(b53_get_ethtool_stats);
1032
1033void b53_get_ethtool_phy_stats(struct dsa_switch *ds, int port, uint64_t *data)
1034{
1035 struct phy_device *phydev;
1036
1037 phydev = b53_get_phy_device(ds, port);
1038 if (!phydev)
1039 return;
1040
1041 phy_ethtool_get_stats(phydev, NULL, data);
1042}
1043EXPORT_SYMBOL(b53_get_ethtool_phy_stats);
1044
1045int b53_get_sset_count(struct dsa_switch *ds, int port, int sset)
1046{
1047 struct b53_device *dev = ds->priv;
1048 struct phy_device *phydev;
1049
1050 if (sset == ETH_SS_STATS) {
1051 return b53_get_mib_size(dev);
1052 } else if (sset == ETH_SS_PHY_STATS) {
1053 phydev = b53_get_phy_device(ds, port);
1054 if (!phydev)
1055 return 0;
1056
1057 return phy_ethtool_get_sset_count(phydev);
1058 }
1059
1060 return 0;
1061}
1062EXPORT_SYMBOL(b53_get_sset_count);
1063
1064enum b53_devlink_resource_id {
1065 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1066};
1067
1068static u64 b53_devlink_vlan_table_get(void *priv)
1069{
1070 struct b53_device *dev = priv;
1071 struct b53_vlan *vl;
1072 unsigned int i;
1073 u64 count = 0;
1074
1075 for (i = 0; i < dev->num_vlans; i++) {
1076 vl = &dev->vlans[i];
1077 if (vl->members)
1078 count++;
1079 }
1080
1081 return count;
1082}
1083
1084int b53_setup_devlink_resources(struct dsa_switch *ds)
1085{
1086 struct devlink_resource_size_params size_params;
1087 struct b53_device *dev = ds->priv;
1088 int err;
1089
1090 devlink_resource_size_params_init(&size_params, dev->num_vlans,
1091 dev->num_vlans,
1092 1, DEVLINK_RESOURCE_UNIT_ENTRY);
1093
1094 err = dsa_devlink_resource_register(ds, "VLAN", dev->num_vlans,
1095 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1096 DEVLINK_RESOURCE_ID_PARENT_TOP,
1097 &size_params);
1098 if (err)
1099 goto out;
1100
1101 dsa_devlink_resource_occ_get_register(ds,
1102 B53_DEVLINK_PARAM_ID_VLAN_TABLE,
1103 b53_devlink_vlan_table_get, dev);
1104
1105 return 0;
1106out:
1107 dsa_devlink_resources_unregister(ds);
1108 return err;
1109}
1110EXPORT_SYMBOL(b53_setup_devlink_resources);
1111
1112static int b53_setup(struct dsa_switch *ds)
1113{
1114 struct b53_device *dev = ds->priv;
1115 unsigned int port;
1116 int ret;
1117
1118 /* Request bridge PVID untagged when DSA_TAG_PROTO_NONE is set
1119 * which forces the CPU port to be tagged in all VLANs.
1120 */
1121 ds->untag_bridge_pvid = dev->tag_protocol == DSA_TAG_PROTO_NONE;
1122
1123 ret = b53_reset_switch(dev);
1124 if (ret) {
1125 dev_err(ds->dev, "failed to reset switch\n");
1126 return ret;
1127 }
1128
1129 b53_reset_mib(dev);
1130
1131 ret = b53_apply_config(dev);
1132 if (ret) {
1133 dev_err(ds->dev, "failed to apply configuration\n");
1134 return ret;
1135 }
1136
1137 /* Configure IMP/CPU port, disable all other ports. Enabled
1138 * ports will be configured with .port_enable
1139 */
1140 for (port = 0; port < dev->num_ports; port++) {
1141 if (dsa_is_cpu_port(ds, port))
1142 b53_enable_cpu_port(dev, port);
1143 else
1144 b53_disable_port(ds, port);
1145 }
1146
1147 return b53_setup_devlink_resources(ds);
1148}
1149
1150static void b53_teardown(struct dsa_switch *ds)
1151{
1152 dsa_devlink_resources_unregister(ds);
1153}
1154
1155static void b53_force_link(struct b53_device *dev, int port, int link)
1156{
1157 u8 reg, val, off;
1158
1159 /* Override the port settings */
1160 if (port == dev->imp_port) {
1161 off = B53_PORT_OVERRIDE_CTRL;
1162 val = PORT_OVERRIDE_EN;
1163 } else {
1164 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1165 val = GMII_PO_EN;
1166 }
1167
1168 b53_read8(dev, B53_CTRL_PAGE, off, ®);
1169 reg |= val;
1170 if (link)
1171 reg |= PORT_OVERRIDE_LINK;
1172 else
1173 reg &= ~PORT_OVERRIDE_LINK;
1174 b53_write8(dev, B53_CTRL_PAGE, off, reg);
1175}
1176
1177static void b53_force_port_config(struct b53_device *dev, int port,
1178 int speed, int duplex,
1179 bool tx_pause, bool rx_pause)
1180{
1181 u8 reg, val, off;
1182
1183 /* Override the port settings */
1184 if (port == dev->imp_port) {
1185 off = B53_PORT_OVERRIDE_CTRL;
1186 val = PORT_OVERRIDE_EN;
1187 } else {
1188 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
1189 val = GMII_PO_EN;
1190 }
1191
1192 b53_read8(dev, B53_CTRL_PAGE, off, ®);
1193 reg |= val;
1194 if (duplex == DUPLEX_FULL)
1195 reg |= PORT_OVERRIDE_FULL_DUPLEX;
1196 else
1197 reg &= ~PORT_OVERRIDE_FULL_DUPLEX;
1198
1199 switch (speed) {
1200 case 2000:
1201 reg |= PORT_OVERRIDE_SPEED_2000M;
1202 fallthrough;
1203 case SPEED_1000:
1204 reg |= PORT_OVERRIDE_SPEED_1000M;
1205 break;
1206 case SPEED_100:
1207 reg |= PORT_OVERRIDE_SPEED_100M;
1208 break;
1209 case SPEED_10:
1210 reg |= PORT_OVERRIDE_SPEED_10M;
1211 break;
1212 default:
1213 dev_err(dev->dev, "unknown speed: %d\n", speed);
1214 return;
1215 }
1216
1217 if (rx_pause)
1218 reg |= PORT_OVERRIDE_RX_FLOW;
1219 if (tx_pause)
1220 reg |= PORT_OVERRIDE_TX_FLOW;
1221
1222 b53_write8(dev, B53_CTRL_PAGE, off, reg);
1223}
1224
1225static void b53_adjust_63xx_rgmii(struct dsa_switch *ds, int port,
1226 phy_interface_t interface)
1227{
1228 struct b53_device *dev = ds->priv;
1229 u8 rgmii_ctrl = 0, off;
1230
1231 if (port == dev->imp_port)
1232 off = B53_RGMII_CTRL_IMP;
1233 else
1234 off = B53_RGMII_CTRL_P(port);
1235
1236 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
1237
1238 switch (interface) {
1239 case PHY_INTERFACE_MODE_RGMII_ID:
1240 rgmii_ctrl |= (RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC);
1241 break;
1242 case PHY_INTERFACE_MODE_RGMII_RXID:
1243 rgmii_ctrl &= ~(RGMII_CTRL_DLL_TXC);
1244 rgmii_ctrl |= RGMII_CTRL_DLL_RXC;
1245 break;
1246 case PHY_INTERFACE_MODE_RGMII_TXID:
1247 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC);
1248 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
1249 break;
1250 case PHY_INTERFACE_MODE_RGMII:
1251 default:
1252 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC);
1253 break;
1254 }
1255
1256 if (port != dev->imp_port) {
1257 if (is63268(dev))
1258 rgmii_ctrl |= RGMII_CTRL_MII_OVERRIDE;
1259
1260 rgmii_ctrl |= RGMII_CTRL_ENABLE_GMII;
1261 }
1262
1263 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1264
1265 dev_dbg(ds->dev, "Configured port %d for %s\n", port,
1266 phy_modes(interface));
1267}
1268
1269static void b53_adjust_link(struct dsa_switch *ds, int port,
1270 struct phy_device *phydev)
1271{
1272 struct b53_device *dev = ds->priv;
1273 struct ethtool_keee *p = &dev->ports[port].eee;
1274 u8 rgmii_ctrl = 0, reg = 0, off;
1275 bool tx_pause = false;
1276 bool rx_pause = false;
1277
1278 if (!phy_is_pseudo_fixed_link(phydev))
1279 return;
1280
1281 /* Enable flow control on BCM5301x's CPU port */
1282 if (is5301x(dev) && dsa_is_cpu_port(ds, port))
1283 tx_pause = rx_pause = true;
1284
1285 if (phydev->pause) {
1286 if (phydev->asym_pause)
1287 tx_pause = true;
1288 rx_pause = true;
1289 }
1290
1291 b53_force_port_config(dev, port, phydev->speed, phydev->duplex,
1292 tx_pause, rx_pause);
1293 b53_force_link(dev, port, phydev->link);
1294
1295 if (is63xx(dev) && port >= B53_63XX_RGMII0)
1296 b53_adjust_63xx_rgmii(ds, port, phydev->interface);
1297
1298 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
1299 if (port == dev->imp_port)
1300 off = B53_RGMII_CTRL_IMP;
1301 else
1302 off = B53_RGMII_CTRL_P(port);
1303
1304 /* Configure the port RGMII clock delay by DLL disabled and
1305 * tx_clk aligned timing (restoring to reset defaults)
1306 */
1307 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
1308 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
1309 RGMII_CTRL_TIMING_SEL);
1310
1311 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
1312 * sure that we enable the port TX clock internal delay to
1313 * account for this internal delay that is inserted, otherwise
1314 * the switch won't be able to receive correctly.
1315 *
1316 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
1317 * any delay neither on transmission nor reception, so the
1318 * BCM53125 must also be configured accordingly to account for
1319 * the lack of delay and introduce
1320 *
1321 * The BCM53125 switch has its RX clock and TX clock control
1322 * swapped, hence the reason why we modify the TX clock path in
1323 * the "RGMII" case
1324 */
1325 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1326 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
1327 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
1328 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
1329 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
1330 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
1331
1332 dev_info(ds->dev, "Configured port %d for %s\n", port,
1333 phy_modes(phydev->interface));
1334 }
1335
1336 /* configure MII port if necessary */
1337 if (is5325(dev)) {
1338 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1339 ®);
1340
1341 /* reverse mii needs to be enabled */
1342 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1343 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1344 reg | PORT_OVERRIDE_RV_MII_25);
1345 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
1346 ®);
1347
1348 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1349 dev_err(ds->dev,
1350 "Failed to enable reverse MII mode\n");
1351 return;
1352 }
1353 }
1354 }
1355
1356 /* Re-negotiate EEE if it was enabled already */
1357 p->eee_enabled = b53_eee_init(ds, port, phydev);
1358}
1359
1360void b53_port_event(struct dsa_switch *ds, int port)
1361{
1362 struct b53_device *dev = ds->priv;
1363 bool link;
1364 u16 sts;
1365
1366 b53_read16(dev, B53_STAT_PAGE, B53_LINK_STAT, &sts);
1367 link = !!(sts & BIT(port));
1368 dsa_port_phylink_mac_change(ds, port, link);
1369}
1370EXPORT_SYMBOL(b53_port_event);
1371
1372static void b53_phylink_get_caps(struct dsa_switch *ds, int port,
1373 struct phylink_config *config)
1374{
1375 struct b53_device *dev = ds->priv;
1376
1377 /* Internal ports need GMII for PHYLIB */
1378 __set_bit(PHY_INTERFACE_MODE_GMII, config->supported_interfaces);
1379
1380 /* These switches appear to support MII and RevMII too, but beyond
1381 * this, the code gives very few clues. FIXME: We probably need more
1382 * interface modes here.
1383 *
1384 * According to b53_srab_mux_init(), ports 3..5 can support:
1385 * SGMII, MII, GMII, RGMII or INTERNAL depending on the MUX setting.
1386 * However, the interface mode read from the MUX configuration is
1387 * not passed back to DSA, so phylink uses NA.
1388 * DT can specify RGMII for ports 0, 1.
1389 * For MDIO, port 8 can be RGMII_TXID.
1390 */
1391 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces);
1392 __set_bit(PHY_INTERFACE_MODE_REVMII, config->supported_interfaces);
1393
1394 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
1395 MAC_10 | MAC_100;
1396
1397 /* 5325/5365 are not capable of gigabit speeds, everything else is.
1398 * Note: the original code also exclulded Gigagbit for MII, RevMII
1399 * and 802.3z modes. MII and RevMII are not able to work above 100M,
1400 * so will be excluded by the generic validator implementation.
1401 * However, the exclusion of Gigabit for 802.3z just seems wrong.
1402 */
1403 if (!(is5325(dev) || is5365(dev)))
1404 config->mac_capabilities |= MAC_1000;
1405
1406 /* Get the implementation specific capabilities */
1407 if (dev->ops->phylink_get_caps)
1408 dev->ops->phylink_get_caps(dev, port, config);
1409}
1410
1411static struct phylink_pcs *b53_phylink_mac_select_pcs(struct dsa_switch *ds,
1412 int port,
1413 phy_interface_t interface)
1414{
1415 struct b53_device *dev = ds->priv;
1416
1417 if (!dev->ops->phylink_mac_select_pcs)
1418 return NULL;
1419
1420 return dev->ops->phylink_mac_select_pcs(dev, port, interface);
1421}
1422
1423void b53_phylink_mac_config(struct dsa_switch *ds, int port,
1424 unsigned int mode,
1425 const struct phylink_link_state *state)
1426{
1427}
1428EXPORT_SYMBOL(b53_phylink_mac_config);
1429
1430void b53_phylink_mac_link_down(struct dsa_switch *ds, int port,
1431 unsigned int mode,
1432 phy_interface_t interface)
1433{
1434 struct b53_device *dev = ds->priv;
1435
1436 if (mode == MLO_AN_PHY)
1437 return;
1438
1439 if (mode == MLO_AN_FIXED) {
1440 b53_force_link(dev, port, false);
1441 return;
1442 }
1443
1444 if (phy_interface_mode_is_8023z(interface) &&
1445 dev->ops->serdes_link_set)
1446 dev->ops->serdes_link_set(dev, port, mode, interface, false);
1447}
1448EXPORT_SYMBOL(b53_phylink_mac_link_down);
1449
1450void b53_phylink_mac_link_up(struct dsa_switch *ds, int port,
1451 unsigned int mode,
1452 phy_interface_t interface,
1453 struct phy_device *phydev,
1454 int speed, int duplex,
1455 bool tx_pause, bool rx_pause)
1456{
1457 struct b53_device *dev = ds->priv;
1458
1459 if (is63xx(dev) && port >= B53_63XX_RGMII0)
1460 b53_adjust_63xx_rgmii(ds, port, interface);
1461
1462 if (mode == MLO_AN_PHY)
1463 return;
1464
1465 if (mode == MLO_AN_FIXED) {
1466 b53_force_port_config(dev, port, speed, duplex,
1467 tx_pause, rx_pause);
1468 b53_force_link(dev, port, true);
1469 return;
1470 }
1471
1472 if (phy_interface_mode_is_8023z(interface) &&
1473 dev->ops->serdes_link_set)
1474 dev->ops->serdes_link_set(dev, port, mode, interface, true);
1475}
1476EXPORT_SYMBOL(b53_phylink_mac_link_up);
1477
1478int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
1479 struct netlink_ext_ack *extack)
1480{
1481 struct b53_device *dev = ds->priv;
1482
1483 b53_enable_vlan(dev, port, dev->vlan_enabled, vlan_filtering);
1484
1485 return 0;
1486}
1487EXPORT_SYMBOL(b53_vlan_filtering);
1488
1489static int b53_vlan_prepare(struct dsa_switch *ds, int port,
1490 const struct switchdev_obj_port_vlan *vlan)
1491{
1492 struct b53_device *dev = ds->priv;
1493
1494 if ((is5325(dev) || is5365(dev)) && vlan->vid == 0)
1495 return -EOPNOTSUPP;
1496
1497 /* Port 7 on 7278 connects to the ASP's UniMAC which is not capable of
1498 * receiving VLAN tagged frames at all, we can still allow the port to
1499 * be configured for egress untagged.
1500 */
1501 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7 &&
1502 !(vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED))
1503 return -EINVAL;
1504
1505 if (vlan->vid >= dev->num_vlans)
1506 return -ERANGE;
1507
1508 b53_enable_vlan(dev, port, true, ds->vlan_filtering);
1509
1510 return 0;
1511}
1512
1513int b53_vlan_add(struct dsa_switch *ds, int port,
1514 const struct switchdev_obj_port_vlan *vlan,
1515 struct netlink_ext_ack *extack)
1516{
1517 struct b53_device *dev = ds->priv;
1518 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1519 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1520 struct b53_vlan *vl;
1521 int err;
1522
1523 err = b53_vlan_prepare(ds, port, vlan);
1524 if (err)
1525 return err;
1526
1527 vl = &dev->vlans[vlan->vid];
1528
1529 b53_get_vlan_entry(dev, vlan->vid, vl);
1530
1531 if (vlan->vid == 0 && vlan->vid == b53_default_pvid(dev))
1532 untagged = true;
1533
1534 vl->members |= BIT(port);
1535 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port))
1536 vl->untag |= BIT(port);
1537 else
1538 vl->untag &= ~BIT(port);
1539
1540 b53_set_vlan_entry(dev, vlan->vid, vl);
1541 b53_fast_age_vlan(dev, vlan->vid);
1542
1543 if (pvid && !dsa_is_cpu_port(ds, port)) {
1544 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1545 vlan->vid);
1546 b53_fast_age_vlan(dev, vlan->vid);
1547 }
1548
1549 return 0;
1550}
1551EXPORT_SYMBOL(b53_vlan_add);
1552
1553int b53_vlan_del(struct dsa_switch *ds, int port,
1554 const struct switchdev_obj_port_vlan *vlan)
1555{
1556 struct b53_device *dev = ds->priv;
1557 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1558 struct b53_vlan *vl;
1559 u16 pvid;
1560
1561 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1562
1563 vl = &dev->vlans[vlan->vid];
1564
1565 b53_get_vlan_entry(dev, vlan->vid, vl);
1566
1567 vl->members &= ~BIT(port);
1568
1569 if (pvid == vlan->vid)
1570 pvid = b53_default_pvid(dev);
1571
1572 if (untagged && !b53_vlan_port_needs_forced_tagged(ds, port))
1573 vl->untag &= ~(BIT(port));
1574
1575 b53_set_vlan_entry(dev, vlan->vid, vl);
1576 b53_fast_age_vlan(dev, vlan->vid);
1577
1578 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1579 b53_fast_age_vlan(dev, pvid);
1580
1581 return 0;
1582}
1583EXPORT_SYMBOL(b53_vlan_del);
1584
1585/* Address Resolution Logic routines. Caller must hold &dev->arl_mutex. */
1586static int b53_arl_op_wait(struct b53_device *dev)
1587{
1588 unsigned int timeout = 10;
1589 u8 reg;
1590
1591 do {
1592 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1593 if (!(reg & ARLTBL_START_DONE))
1594 return 0;
1595
1596 usleep_range(1000, 2000);
1597 } while (timeout--);
1598
1599 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1600
1601 return -ETIMEDOUT;
1602}
1603
1604static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1605{
1606 u8 reg;
1607
1608 if (op > ARLTBL_RW)
1609 return -EINVAL;
1610
1611 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1612 reg |= ARLTBL_START_DONE;
1613 if (op)
1614 reg |= ARLTBL_RW;
1615 else
1616 reg &= ~ARLTBL_RW;
1617 if (dev->vlan_enabled)
1618 reg &= ~ARLTBL_IVL_SVL_SELECT;
1619 else
1620 reg |= ARLTBL_IVL_SVL_SELECT;
1621 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1622
1623 return b53_arl_op_wait(dev);
1624}
1625
1626static int b53_arl_read(struct b53_device *dev, u64 mac,
1627 u16 vid, struct b53_arl_entry *ent, u8 *idx)
1628{
1629 DECLARE_BITMAP(free_bins, B53_ARLTBL_MAX_BIN_ENTRIES);
1630 unsigned int i;
1631 int ret;
1632
1633 ret = b53_arl_op_wait(dev);
1634 if (ret)
1635 return ret;
1636
1637 bitmap_zero(free_bins, dev->num_arl_bins);
1638
1639 /* Read the bins */
1640 for (i = 0; i < dev->num_arl_bins; i++) {
1641 u64 mac_vid;
1642 u32 fwd_entry;
1643
1644 b53_read64(dev, B53_ARLIO_PAGE,
1645 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1646 b53_read32(dev, B53_ARLIO_PAGE,
1647 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1648 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1649
1650 if (!(fwd_entry & ARLTBL_VALID)) {
1651 set_bit(i, free_bins);
1652 continue;
1653 }
1654 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1655 continue;
1656 if (dev->vlan_enabled &&
1657 ((mac_vid >> ARLTBL_VID_S) & ARLTBL_VID_MASK) != vid)
1658 continue;
1659 *idx = i;
1660 return 0;
1661 }
1662
1663 *idx = find_first_bit(free_bins, dev->num_arl_bins);
1664 return *idx >= dev->num_arl_bins ? -ENOSPC : -ENOENT;
1665}
1666
1667static int b53_arl_op(struct b53_device *dev, int op, int port,
1668 const unsigned char *addr, u16 vid, bool is_valid)
1669{
1670 struct b53_arl_entry ent;
1671 u32 fwd_entry;
1672 u64 mac, mac_vid = 0;
1673 u8 idx = 0;
1674 int ret;
1675
1676 /* Convert the array into a 64-bit MAC */
1677 mac = ether_addr_to_u64(addr);
1678
1679 /* Perform a read for the given MAC and VID */
1680 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1681 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1682
1683 /* Issue a read operation for this MAC */
1684 ret = b53_arl_rw_op(dev, 1);
1685 if (ret)
1686 return ret;
1687
1688 ret = b53_arl_read(dev, mac, vid, &ent, &idx);
1689
1690 /* If this is a read, just finish now */
1691 if (op)
1692 return ret;
1693
1694 switch (ret) {
1695 case -ETIMEDOUT:
1696 return ret;
1697 case -ENOSPC:
1698 dev_dbg(dev->dev, "{%pM,%.4d} no space left in ARL\n",
1699 addr, vid);
1700 return is_valid ? ret : 0;
1701 case -ENOENT:
1702 /* We could not find a matching MAC, so reset to a new entry */
1703 dev_dbg(dev->dev, "{%pM,%.4d} not found, using idx: %d\n",
1704 addr, vid, idx);
1705 fwd_entry = 0;
1706 break;
1707 default:
1708 dev_dbg(dev->dev, "{%pM,%.4d} found, using idx: %d\n",
1709 addr, vid, idx);
1710 break;
1711 }
1712
1713 /* For multicast address, the port is a bitmask and the validity
1714 * is determined by having at least one port being still active
1715 */
1716 if (!is_multicast_ether_addr(addr)) {
1717 ent.port = port;
1718 ent.is_valid = is_valid;
1719 } else {
1720 if (is_valid)
1721 ent.port |= BIT(port);
1722 else
1723 ent.port &= ~BIT(port);
1724
1725 ent.is_valid = !!(ent.port);
1726 }
1727
1728 ent.vid = vid;
1729 ent.is_static = true;
1730 ent.is_age = false;
1731 memcpy(ent.mac, addr, ETH_ALEN);
1732 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1733
1734 b53_write64(dev, B53_ARLIO_PAGE,
1735 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1736 b53_write32(dev, B53_ARLIO_PAGE,
1737 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1738
1739 return b53_arl_rw_op(dev, 0);
1740}
1741
1742int b53_fdb_add(struct dsa_switch *ds, int port,
1743 const unsigned char *addr, u16 vid,
1744 struct dsa_db db)
1745{
1746 struct b53_device *priv = ds->priv;
1747 int ret;
1748
1749 /* 5325 and 5365 require some more massaging, but could
1750 * be supported eventually
1751 */
1752 if (is5325(priv) || is5365(priv))
1753 return -EOPNOTSUPP;
1754
1755 mutex_lock(&priv->arl_mutex);
1756 ret = b53_arl_op(priv, 0, port, addr, vid, true);
1757 mutex_unlock(&priv->arl_mutex);
1758
1759 return ret;
1760}
1761EXPORT_SYMBOL(b53_fdb_add);
1762
1763int b53_fdb_del(struct dsa_switch *ds, int port,
1764 const unsigned char *addr, u16 vid,
1765 struct dsa_db db)
1766{
1767 struct b53_device *priv = ds->priv;
1768 int ret;
1769
1770 mutex_lock(&priv->arl_mutex);
1771 ret = b53_arl_op(priv, 0, port, addr, vid, false);
1772 mutex_unlock(&priv->arl_mutex);
1773
1774 return ret;
1775}
1776EXPORT_SYMBOL(b53_fdb_del);
1777
1778static int b53_arl_search_wait(struct b53_device *dev)
1779{
1780 unsigned int timeout = 1000;
1781 u8 reg;
1782
1783 do {
1784 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®);
1785 if (!(reg & ARL_SRCH_STDN))
1786 return 0;
1787
1788 if (reg & ARL_SRCH_VLID)
1789 return 0;
1790
1791 usleep_range(1000, 2000);
1792 } while (timeout--);
1793
1794 return -ETIMEDOUT;
1795}
1796
1797static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1798 struct b53_arl_entry *ent)
1799{
1800 u64 mac_vid;
1801 u32 fwd_entry;
1802
1803 b53_read64(dev, B53_ARLIO_PAGE,
1804 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1805 b53_read32(dev, B53_ARLIO_PAGE,
1806 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1807 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1808}
1809
1810static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
1811 dsa_fdb_dump_cb_t *cb, void *data)
1812{
1813 if (!ent->is_valid)
1814 return 0;
1815
1816 if (port != ent->port)
1817 return 0;
1818
1819 return cb(ent->mac, ent->vid, ent->is_static, data);
1820}
1821
1822int b53_fdb_dump(struct dsa_switch *ds, int port,
1823 dsa_fdb_dump_cb_t *cb, void *data)
1824{
1825 struct b53_device *priv = ds->priv;
1826 struct b53_arl_entry results[2];
1827 unsigned int count = 0;
1828 int ret;
1829 u8 reg;
1830
1831 mutex_lock(&priv->arl_mutex);
1832
1833 /* Start search operation */
1834 reg = ARL_SRCH_STDN;
1835 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1836
1837 do {
1838 ret = b53_arl_search_wait(priv);
1839 if (ret)
1840 break;
1841
1842 b53_arl_search_rd(priv, 0, &results[0]);
1843 ret = b53_fdb_copy(port, &results[0], cb, data);
1844 if (ret)
1845 break;
1846
1847 if (priv->num_arl_bins > 2) {
1848 b53_arl_search_rd(priv, 1, &results[1]);
1849 ret = b53_fdb_copy(port, &results[1], cb, data);
1850 if (ret)
1851 break;
1852
1853 if (!results[0].is_valid && !results[1].is_valid)
1854 break;
1855 }
1856
1857 } while (count++ < b53_max_arl_entries(priv) / 2);
1858
1859 mutex_unlock(&priv->arl_mutex);
1860
1861 return 0;
1862}
1863EXPORT_SYMBOL(b53_fdb_dump);
1864
1865int b53_mdb_add(struct dsa_switch *ds, int port,
1866 const struct switchdev_obj_port_mdb *mdb,
1867 struct dsa_db db)
1868{
1869 struct b53_device *priv = ds->priv;
1870 int ret;
1871
1872 /* 5325 and 5365 require some more massaging, but could
1873 * be supported eventually
1874 */
1875 if (is5325(priv) || is5365(priv))
1876 return -EOPNOTSUPP;
1877
1878 mutex_lock(&priv->arl_mutex);
1879 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, true);
1880 mutex_unlock(&priv->arl_mutex);
1881
1882 return ret;
1883}
1884EXPORT_SYMBOL(b53_mdb_add);
1885
1886int b53_mdb_del(struct dsa_switch *ds, int port,
1887 const struct switchdev_obj_port_mdb *mdb,
1888 struct dsa_db db)
1889{
1890 struct b53_device *priv = ds->priv;
1891 int ret;
1892
1893 mutex_lock(&priv->arl_mutex);
1894 ret = b53_arl_op(priv, 0, port, mdb->addr, mdb->vid, false);
1895 mutex_unlock(&priv->arl_mutex);
1896 if (ret)
1897 dev_err(ds->dev, "failed to delete MDB entry\n");
1898
1899 return ret;
1900}
1901EXPORT_SYMBOL(b53_mdb_del);
1902
1903int b53_br_join(struct dsa_switch *ds, int port, struct dsa_bridge bridge,
1904 bool *tx_fwd_offload, struct netlink_ext_ack *extack)
1905{
1906 struct b53_device *dev = ds->priv;
1907 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1908 u16 pvlan, reg;
1909 unsigned int i;
1910
1911 /* On 7278, port 7 which connects to the ASP should only receive
1912 * traffic from matching CFP rules.
1913 */
1914 if (dev->chip_id == BCM7278_DEVICE_ID && port == 7)
1915 return -EINVAL;
1916
1917 /* Make this port leave the all VLANs join since we will have proper
1918 * VLAN entries from now on
1919 */
1920 if (is58xx(dev)) {
1921 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1922 reg &= ~BIT(port);
1923 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1924 reg &= ~BIT(cpu_port);
1925 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1926 }
1927
1928 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1929
1930 b53_for_each_port(dev, i) {
1931 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1932 continue;
1933
1934 /* Add this local port to the remote port VLAN control
1935 * membership and update the remote port bitmask
1936 */
1937 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1938 reg |= BIT(port);
1939 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1940 dev->ports[i].vlan_ctl_mask = reg;
1941
1942 pvlan |= BIT(i);
1943 }
1944
1945 /* Configure the local port VLAN control membership to include
1946 * remote ports and update the local port bitmask
1947 */
1948 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1949 dev->ports[port].vlan_ctl_mask = pvlan;
1950
1951 return 0;
1952}
1953EXPORT_SYMBOL(b53_br_join);
1954
1955void b53_br_leave(struct dsa_switch *ds, int port, struct dsa_bridge bridge)
1956{
1957 struct b53_device *dev = ds->priv;
1958 struct b53_vlan *vl = &dev->vlans[0];
1959 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
1960 unsigned int i;
1961 u16 pvlan, reg, pvid;
1962
1963 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1964
1965 b53_for_each_port(dev, i) {
1966 /* Don't touch the remaining ports */
1967 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
1968 continue;
1969
1970 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1971 reg &= ~BIT(port);
1972 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1973 dev->ports[port].vlan_ctl_mask = reg;
1974
1975 /* Prevent self removal to preserve isolation */
1976 if (port != i)
1977 pvlan &= ~BIT(i);
1978 }
1979
1980 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1981 dev->ports[port].vlan_ctl_mask = pvlan;
1982
1983 pvid = b53_default_pvid(dev);
1984
1985 /* Make this port join all VLANs without VLAN entries */
1986 if (is58xx(dev)) {
1987 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1988 reg |= BIT(port);
1989 if (!(reg & BIT(cpu_port)))
1990 reg |= BIT(cpu_port);
1991 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1992 } else {
1993 b53_get_vlan_entry(dev, pvid, vl);
1994 vl->members |= BIT(port) | BIT(cpu_port);
1995 vl->untag |= BIT(port) | BIT(cpu_port);
1996 b53_set_vlan_entry(dev, pvid, vl);
1997 }
1998}
1999EXPORT_SYMBOL(b53_br_leave);
2000
2001void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
2002{
2003 struct b53_device *dev = ds->priv;
2004 u8 hw_state;
2005 u8 reg;
2006
2007 switch (state) {
2008 case BR_STATE_DISABLED:
2009 hw_state = PORT_CTRL_DIS_STATE;
2010 break;
2011 case BR_STATE_LISTENING:
2012 hw_state = PORT_CTRL_LISTEN_STATE;
2013 break;
2014 case BR_STATE_LEARNING:
2015 hw_state = PORT_CTRL_LEARN_STATE;
2016 break;
2017 case BR_STATE_FORWARDING:
2018 hw_state = PORT_CTRL_FWD_STATE;
2019 break;
2020 case BR_STATE_BLOCKING:
2021 hw_state = PORT_CTRL_BLOCK_STATE;
2022 break;
2023 default:
2024 dev_err(ds->dev, "invalid STP state: %d\n", state);
2025 return;
2026 }
2027
2028 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
2029 reg &= ~PORT_CTRL_STP_STATE_MASK;
2030 reg |= hw_state;
2031 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
2032}
2033EXPORT_SYMBOL(b53_br_set_stp_state);
2034
2035void b53_br_fast_age(struct dsa_switch *ds, int port)
2036{
2037 struct b53_device *dev = ds->priv;
2038
2039 if (b53_fast_age_port(dev, port))
2040 dev_err(ds->dev, "fast ageing failed\n");
2041}
2042EXPORT_SYMBOL(b53_br_fast_age);
2043
2044int b53_br_flags_pre(struct dsa_switch *ds, int port,
2045 struct switchdev_brport_flags flags,
2046 struct netlink_ext_ack *extack)
2047{
2048 if (flags.mask & ~(BR_FLOOD | BR_MCAST_FLOOD | BR_LEARNING))
2049 return -EINVAL;
2050
2051 return 0;
2052}
2053EXPORT_SYMBOL(b53_br_flags_pre);
2054
2055int b53_br_flags(struct dsa_switch *ds, int port,
2056 struct switchdev_brport_flags flags,
2057 struct netlink_ext_ack *extack)
2058{
2059 if (flags.mask & BR_FLOOD)
2060 b53_port_set_ucast_flood(ds->priv, port,
2061 !!(flags.val & BR_FLOOD));
2062 if (flags.mask & BR_MCAST_FLOOD)
2063 b53_port_set_mcast_flood(ds->priv, port,
2064 !!(flags.val & BR_MCAST_FLOOD));
2065 if (flags.mask & BR_LEARNING)
2066 b53_port_set_learning(ds->priv, port,
2067 !!(flags.val & BR_LEARNING));
2068
2069 return 0;
2070}
2071EXPORT_SYMBOL(b53_br_flags);
2072
2073static bool b53_possible_cpu_port(struct dsa_switch *ds, int port)
2074{
2075 /* Broadcom switches will accept enabling Broadcom tags on the
2076 * following ports: 5, 7 and 8, any other port is not supported
2077 */
2078 switch (port) {
2079 case B53_CPU_PORT_25:
2080 case 7:
2081 case B53_CPU_PORT:
2082 return true;
2083 }
2084
2085 return false;
2086}
2087
2088static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port,
2089 enum dsa_tag_protocol tag_protocol)
2090{
2091 bool ret = b53_possible_cpu_port(ds, port);
2092
2093 if (!ret) {
2094 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n",
2095 port);
2096 return ret;
2097 }
2098
2099 switch (tag_protocol) {
2100 case DSA_TAG_PROTO_BRCM:
2101 case DSA_TAG_PROTO_BRCM_PREPEND:
2102 dev_warn(ds->dev,
2103 "Port %d is stacked to Broadcom tag switch\n", port);
2104 ret = false;
2105 break;
2106 default:
2107 ret = true;
2108 break;
2109 }
2110
2111 return ret;
2112}
2113
2114enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port,
2115 enum dsa_tag_protocol mprot)
2116{
2117 struct b53_device *dev = ds->priv;
2118
2119 if (!b53_can_enable_brcm_tags(ds, port, mprot)) {
2120 dev->tag_protocol = DSA_TAG_PROTO_NONE;
2121 goto out;
2122 }
2123
2124 /* Older models require a different 6 byte tag */
2125 if (is5325(dev) || is5365(dev) || is63xx(dev)) {
2126 dev->tag_protocol = DSA_TAG_PROTO_BRCM_LEGACY;
2127 goto out;
2128 }
2129
2130 /* Broadcom BCM58xx chips have a flow accelerator on Port 8
2131 * which requires us to use the prepended Broadcom tag type
2132 */
2133 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT) {
2134 dev->tag_protocol = DSA_TAG_PROTO_BRCM_PREPEND;
2135 goto out;
2136 }
2137
2138 dev->tag_protocol = DSA_TAG_PROTO_BRCM;
2139out:
2140 return dev->tag_protocol;
2141}
2142EXPORT_SYMBOL(b53_get_tag_protocol);
2143
2144int b53_mirror_add(struct dsa_switch *ds, int port,
2145 struct dsa_mall_mirror_tc_entry *mirror, bool ingress,
2146 struct netlink_ext_ack *extack)
2147{
2148 struct b53_device *dev = ds->priv;
2149 u16 reg, loc;
2150
2151 if (ingress)
2152 loc = B53_IG_MIR_CTL;
2153 else
2154 loc = B53_EG_MIR_CTL;
2155
2156 b53_read16(dev, B53_MGMT_PAGE, loc, ®);
2157 reg |= BIT(port);
2158 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2159
2160 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®);
2161 reg &= ~CAP_PORT_MASK;
2162 reg |= mirror->to_local_port;
2163 reg |= MIRROR_EN;
2164 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2165
2166 return 0;
2167}
2168EXPORT_SYMBOL(b53_mirror_add);
2169
2170void b53_mirror_del(struct dsa_switch *ds, int port,
2171 struct dsa_mall_mirror_tc_entry *mirror)
2172{
2173 struct b53_device *dev = ds->priv;
2174 bool loc_disable = false, other_loc_disable = false;
2175 u16 reg, loc;
2176
2177 if (mirror->ingress)
2178 loc = B53_IG_MIR_CTL;
2179 else
2180 loc = B53_EG_MIR_CTL;
2181
2182 /* Update the desired ingress/egress register */
2183 b53_read16(dev, B53_MGMT_PAGE, loc, ®);
2184 reg &= ~BIT(port);
2185 if (!(reg & MIRROR_MASK))
2186 loc_disable = true;
2187 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
2188
2189 /* Now look at the other one to know if we can disable mirroring
2190 * entirely
2191 */
2192 if (mirror->ingress)
2193 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®);
2194 else
2195 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®);
2196 if (!(reg & MIRROR_MASK))
2197 other_loc_disable = true;
2198
2199 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®);
2200 /* Both no longer have ports, let's disable mirroring */
2201 if (loc_disable && other_loc_disable) {
2202 reg &= ~MIRROR_EN;
2203 reg &= ~mirror->to_local_port;
2204 }
2205 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
2206}
2207EXPORT_SYMBOL(b53_mirror_del);
2208
2209/* Returns 0 if EEE was not enabled, or 1 otherwise
2210 */
2211int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
2212{
2213 int ret;
2214
2215 ret = phy_init_eee(phy, false);
2216 if (ret)
2217 return 0;
2218
2219 b53_eee_enable_set(ds, port, true);
2220
2221 return 1;
2222}
2223EXPORT_SYMBOL(b53_eee_init);
2224
2225int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *e)
2226{
2227 struct b53_device *dev = ds->priv;
2228
2229 if (is5325(dev) || is5365(dev))
2230 return -EOPNOTSUPP;
2231
2232 return 0;
2233}
2234EXPORT_SYMBOL(b53_get_mac_eee);
2235
2236int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_keee *e)
2237{
2238 struct b53_device *dev = ds->priv;
2239 struct ethtool_keee *p = &dev->ports[port].eee;
2240
2241 if (is5325(dev) || is5365(dev))
2242 return -EOPNOTSUPP;
2243
2244 p->eee_enabled = e->eee_enabled;
2245 b53_eee_enable_set(ds, port, e->eee_enabled);
2246
2247 return 0;
2248}
2249EXPORT_SYMBOL(b53_set_mac_eee);
2250
2251static int b53_change_mtu(struct dsa_switch *ds, int port, int mtu)
2252{
2253 struct b53_device *dev = ds->priv;
2254 bool enable_jumbo;
2255 bool allow_10_100;
2256
2257 if (is5325(dev) || is5365(dev))
2258 return -EOPNOTSUPP;
2259
2260 enable_jumbo = (mtu >= JMS_MIN_SIZE);
2261 allow_10_100 = (dev->chip_id == BCM583XX_DEVICE_ID);
2262
2263 return b53_set_jumbo(dev, enable_jumbo, allow_10_100);
2264}
2265
2266static int b53_get_max_mtu(struct dsa_switch *ds, int port)
2267{
2268 return JMS_MAX_SIZE;
2269}
2270
2271static const struct dsa_switch_ops b53_switch_ops = {
2272 .get_tag_protocol = b53_get_tag_protocol,
2273 .setup = b53_setup,
2274 .teardown = b53_teardown,
2275 .get_strings = b53_get_strings,
2276 .get_ethtool_stats = b53_get_ethtool_stats,
2277 .get_sset_count = b53_get_sset_count,
2278 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
2279 .phy_read = b53_phy_read16,
2280 .phy_write = b53_phy_write16,
2281 .adjust_link = b53_adjust_link,
2282 .phylink_get_caps = b53_phylink_get_caps,
2283 .phylink_mac_select_pcs = b53_phylink_mac_select_pcs,
2284 .phylink_mac_config = b53_phylink_mac_config,
2285 .phylink_mac_link_down = b53_phylink_mac_link_down,
2286 .phylink_mac_link_up = b53_phylink_mac_link_up,
2287 .port_enable = b53_enable_port,
2288 .port_disable = b53_disable_port,
2289 .get_mac_eee = b53_get_mac_eee,
2290 .set_mac_eee = b53_set_mac_eee,
2291 .port_bridge_join = b53_br_join,
2292 .port_bridge_leave = b53_br_leave,
2293 .port_pre_bridge_flags = b53_br_flags_pre,
2294 .port_bridge_flags = b53_br_flags,
2295 .port_stp_state_set = b53_br_set_stp_state,
2296 .port_fast_age = b53_br_fast_age,
2297 .port_vlan_filtering = b53_vlan_filtering,
2298 .port_vlan_add = b53_vlan_add,
2299 .port_vlan_del = b53_vlan_del,
2300 .port_fdb_dump = b53_fdb_dump,
2301 .port_fdb_add = b53_fdb_add,
2302 .port_fdb_del = b53_fdb_del,
2303 .port_mirror_add = b53_mirror_add,
2304 .port_mirror_del = b53_mirror_del,
2305 .port_mdb_add = b53_mdb_add,
2306 .port_mdb_del = b53_mdb_del,
2307 .port_max_mtu = b53_get_max_mtu,
2308 .port_change_mtu = b53_change_mtu,
2309};
2310
2311struct b53_chip_data {
2312 u32 chip_id;
2313 const char *dev_name;
2314 u16 vlans;
2315 u16 enabled_ports;
2316 u8 imp_port;
2317 u8 cpu_port;
2318 u8 vta_regs[3];
2319 u8 arl_bins;
2320 u16 arl_buckets;
2321 u8 duplex_reg;
2322 u8 jumbo_pm_reg;
2323 u8 jumbo_size_reg;
2324};
2325
2326#define B53_VTA_REGS \
2327 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
2328#define B53_VTA_REGS_9798 \
2329 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
2330#define B53_VTA_REGS_63XX \
2331 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
2332
2333static const struct b53_chip_data b53_switch_chips[] = {
2334 {
2335 .chip_id = BCM5325_DEVICE_ID,
2336 .dev_name = "BCM5325",
2337 .vlans = 16,
2338 .enabled_ports = 0x3f,
2339 .arl_bins = 2,
2340 .arl_buckets = 1024,
2341 .imp_port = 5,
2342 .duplex_reg = B53_DUPLEX_STAT_FE,
2343 },
2344 {
2345 .chip_id = BCM5365_DEVICE_ID,
2346 .dev_name = "BCM5365",
2347 .vlans = 256,
2348 .enabled_ports = 0x3f,
2349 .arl_bins = 2,
2350 .arl_buckets = 1024,
2351 .imp_port = 5,
2352 .duplex_reg = B53_DUPLEX_STAT_FE,
2353 },
2354 {
2355 .chip_id = BCM5389_DEVICE_ID,
2356 .dev_name = "BCM5389",
2357 .vlans = 4096,
2358 .enabled_ports = 0x11f,
2359 .arl_bins = 4,
2360 .arl_buckets = 1024,
2361 .imp_port = 8,
2362 .vta_regs = B53_VTA_REGS,
2363 .duplex_reg = B53_DUPLEX_STAT_GE,
2364 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2365 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2366 },
2367 {
2368 .chip_id = BCM5395_DEVICE_ID,
2369 .dev_name = "BCM5395",
2370 .vlans = 4096,
2371 .enabled_ports = 0x11f,
2372 .arl_bins = 4,
2373 .arl_buckets = 1024,
2374 .imp_port = 8,
2375 .vta_regs = B53_VTA_REGS,
2376 .duplex_reg = B53_DUPLEX_STAT_GE,
2377 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2378 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2379 },
2380 {
2381 .chip_id = BCM5397_DEVICE_ID,
2382 .dev_name = "BCM5397",
2383 .vlans = 4096,
2384 .enabled_ports = 0x11f,
2385 .arl_bins = 4,
2386 .arl_buckets = 1024,
2387 .imp_port = 8,
2388 .vta_regs = B53_VTA_REGS_9798,
2389 .duplex_reg = B53_DUPLEX_STAT_GE,
2390 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2391 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2392 },
2393 {
2394 .chip_id = BCM5398_DEVICE_ID,
2395 .dev_name = "BCM5398",
2396 .vlans = 4096,
2397 .enabled_ports = 0x17f,
2398 .arl_bins = 4,
2399 .arl_buckets = 1024,
2400 .imp_port = 8,
2401 .vta_regs = B53_VTA_REGS_9798,
2402 .duplex_reg = B53_DUPLEX_STAT_GE,
2403 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2404 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2405 },
2406 {
2407 .chip_id = BCM53115_DEVICE_ID,
2408 .dev_name = "BCM53115",
2409 .vlans = 4096,
2410 .enabled_ports = 0x11f,
2411 .arl_bins = 4,
2412 .arl_buckets = 1024,
2413 .vta_regs = B53_VTA_REGS,
2414 .imp_port = 8,
2415 .duplex_reg = B53_DUPLEX_STAT_GE,
2416 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2417 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2418 },
2419 {
2420 .chip_id = BCM53125_DEVICE_ID,
2421 .dev_name = "BCM53125",
2422 .vlans = 4096,
2423 .enabled_ports = 0x1ff,
2424 .arl_bins = 4,
2425 .arl_buckets = 1024,
2426 .imp_port = 8,
2427 .vta_regs = B53_VTA_REGS,
2428 .duplex_reg = B53_DUPLEX_STAT_GE,
2429 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2430 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2431 },
2432 {
2433 .chip_id = BCM53128_DEVICE_ID,
2434 .dev_name = "BCM53128",
2435 .vlans = 4096,
2436 .enabled_ports = 0x1ff,
2437 .arl_bins = 4,
2438 .arl_buckets = 1024,
2439 .imp_port = 8,
2440 .vta_regs = B53_VTA_REGS,
2441 .duplex_reg = B53_DUPLEX_STAT_GE,
2442 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2443 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2444 },
2445 {
2446 .chip_id = BCM63XX_DEVICE_ID,
2447 .dev_name = "BCM63xx",
2448 .vlans = 4096,
2449 .enabled_ports = 0, /* pdata must provide them */
2450 .arl_bins = 4,
2451 .arl_buckets = 1024,
2452 .imp_port = 8,
2453 .vta_regs = B53_VTA_REGS_63XX,
2454 .duplex_reg = B53_DUPLEX_STAT_63XX,
2455 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
2456 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
2457 },
2458 {
2459 .chip_id = BCM63268_DEVICE_ID,
2460 .dev_name = "BCM63268",
2461 .vlans = 4096,
2462 .enabled_ports = 0, /* pdata must provide them */
2463 .arl_bins = 4,
2464 .arl_buckets = 1024,
2465 .imp_port = 8,
2466 .vta_regs = B53_VTA_REGS_63XX,
2467 .duplex_reg = B53_DUPLEX_STAT_63XX,
2468 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
2469 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
2470 },
2471 {
2472 .chip_id = BCM53010_DEVICE_ID,
2473 .dev_name = "BCM53010",
2474 .vlans = 4096,
2475 .enabled_ports = 0x1bf,
2476 .arl_bins = 4,
2477 .arl_buckets = 1024,
2478 .imp_port = 8,
2479 .vta_regs = B53_VTA_REGS,
2480 .duplex_reg = B53_DUPLEX_STAT_GE,
2481 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2482 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2483 },
2484 {
2485 .chip_id = BCM53011_DEVICE_ID,
2486 .dev_name = "BCM53011",
2487 .vlans = 4096,
2488 .enabled_ports = 0x1bf,
2489 .arl_bins = 4,
2490 .arl_buckets = 1024,
2491 .imp_port = 8,
2492 .vta_regs = B53_VTA_REGS,
2493 .duplex_reg = B53_DUPLEX_STAT_GE,
2494 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2495 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2496 },
2497 {
2498 .chip_id = BCM53012_DEVICE_ID,
2499 .dev_name = "BCM53012",
2500 .vlans = 4096,
2501 .enabled_ports = 0x1bf,
2502 .arl_bins = 4,
2503 .arl_buckets = 1024,
2504 .imp_port = 8,
2505 .vta_regs = B53_VTA_REGS,
2506 .duplex_reg = B53_DUPLEX_STAT_GE,
2507 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2508 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2509 },
2510 {
2511 .chip_id = BCM53018_DEVICE_ID,
2512 .dev_name = "BCM53018",
2513 .vlans = 4096,
2514 .enabled_ports = 0x1bf,
2515 .arl_bins = 4,
2516 .arl_buckets = 1024,
2517 .imp_port = 8,
2518 .vta_regs = B53_VTA_REGS,
2519 .duplex_reg = B53_DUPLEX_STAT_GE,
2520 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2521 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2522 },
2523 {
2524 .chip_id = BCM53019_DEVICE_ID,
2525 .dev_name = "BCM53019",
2526 .vlans = 4096,
2527 .enabled_ports = 0x1bf,
2528 .arl_bins = 4,
2529 .arl_buckets = 1024,
2530 .imp_port = 8,
2531 .vta_regs = B53_VTA_REGS,
2532 .duplex_reg = B53_DUPLEX_STAT_GE,
2533 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2534 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2535 },
2536 {
2537 .chip_id = BCM58XX_DEVICE_ID,
2538 .dev_name = "BCM585xx/586xx/88312",
2539 .vlans = 4096,
2540 .enabled_ports = 0x1ff,
2541 .arl_bins = 4,
2542 .arl_buckets = 1024,
2543 .imp_port = 8,
2544 .vta_regs = B53_VTA_REGS,
2545 .duplex_reg = B53_DUPLEX_STAT_GE,
2546 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2547 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2548 },
2549 {
2550 .chip_id = BCM583XX_DEVICE_ID,
2551 .dev_name = "BCM583xx/11360",
2552 .vlans = 4096,
2553 .enabled_ports = 0x103,
2554 .arl_bins = 4,
2555 .arl_buckets = 1024,
2556 .imp_port = 8,
2557 .vta_regs = B53_VTA_REGS,
2558 .duplex_reg = B53_DUPLEX_STAT_GE,
2559 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2560 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2561 },
2562 /* Starfighter 2 */
2563 {
2564 .chip_id = BCM4908_DEVICE_ID,
2565 .dev_name = "BCM4908",
2566 .vlans = 4096,
2567 .enabled_ports = 0x1bf,
2568 .arl_bins = 4,
2569 .arl_buckets = 256,
2570 .imp_port = 8,
2571 .vta_regs = B53_VTA_REGS,
2572 .duplex_reg = B53_DUPLEX_STAT_GE,
2573 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2574 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2575 },
2576 {
2577 .chip_id = BCM7445_DEVICE_ID,
2578 .dev_name = "BCM7445",
2579 .vlans = 4096,
2580 .enabled_ports = 0x1ff,
2581 .arl_bins = 4,
2582 .arl_buckets = 1024,
2583 .imp_port = 8,
2584 .vta_regs = B53_VTA_REGS,
2585 .duplex_reg = B53_DUPLEX_STAT_GE,
2586 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2587 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2588 },
2589 {
2590 .chip_id = BCM7278_DEVICE_ID,
2591 .dev_name = "BCM7278",
2592 .vlans = 4096,
2593 .enabled_ports = 0x1ff,
2594 .arl_bins = 4,
2595 .arl_buckets = 256,
2596 .imp_port = 8,
2597 .vta_regs = B53_VTA_REGS,
2598 .duplex_reg = B53_DUPLEX_STAT_GE,
2599 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2600 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2601 },
2602 {
2603 .chip_id = BCM53134_DEVICE_ID,
2604 .dev_name = "BCM53134",
2605 .vlans = 4096,
2606 .enabled_ports = 0x12f,
2607 .imp_port = 8,
2608 .cpu_port = B53_CPU_PORT,
2609 .vta_regs = B53_VTA_REGS,
2610 .arl_bins = 4,
2611 .arl_buckets = 1024,
2612 .duplex_reg = B53_DUPLEX_STAT_GE,
2613 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
2614 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
2615 },
2616};
2617
2618static int b53_switch_init(struct b53_device *dev)
2619{
2620 unsigned int i;
2621 int ret;
2622
2623 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
2624 const struct b53_chip_data *chip = &b53_switch_chips[i];
2625
2626 if (chip->chip_id == dev->chip_id) {
2627 if (!dev->enabled_ports)
2628 dev->enabled_ports = chip->enabled_ports;
2629 dev->name = chip->dev_name;
2630 dev->duplex_reg = chip->duplex_reg;
2631 dev->vta_regs[0] = chip->vta_regs[0];
2632 dev->vta_regs[1] = chip->vta_regs[1];
2633 dev->vta_regs[2] = chip->vta_regs[2];
2634 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
2635 dev->imp_port = chip->imp_port;
2636 dev->num_vlans = chip->vlans;
2637 dev->num_arl_bins = chip->arl_bins;
2638 dev->num_arl_buckets = chip->arl_buckets;
2639 break;
2640 }
2641 }
2642
2643 /* check which BCM5325x version we have */
2644 if (is5325(dev)) {
2645 u8 vc4;
2646
2647 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
2648
2649 /* check reserved bits */
2650 switch (vc4 & 3) {
2651 case 1:
2652 /* BCM5325E */
2653 break;
2654 case 3:
2655 /* BCM5325F - do not use port 4 */
2656 dev->enabled_ports &= ~BIT(4);
2657 break;
2658 default:
2659/* On the BCM47XX SoCs this is the supported internal switch.*/
2660#ifndef CONFIG_BCM47XX
2661 /* BCM5325M */
2662 return -EINVAL;
2663#else
2664 break;
2665#endif
2666 }
2667 }
2668
2669 dev->num_ports = fls(dev->enabled_ports);
2670
2671 dev->ds->num_ports = min_t(unsigned int, dev->num_ports, DSA_MAX_PORTS);
2672
2673 /* Include non standard CPU port built-in PHYs to be probed */
2674 if (is539x(dev) || is531x5(dev)) {
2675 for (i = 0; i < dev->num_ports; i++) {
2676 if (!(dev->ds->phys_mii_mask & BIT(i)) &&
2677 !b53_possible_cpu_port(dev->ds, i))
2678 dev->ds->phys_mii_mask |= BIT(i);
2679 }
2680 }
2681
2682 dev->ports = devm_kcalloc(dev->dev,
2683 dev->num_ports, sizeof(struct b53_port),
2684 GFP_KERNEL);
2685 if (!dev->ports)
2686 return -ENOMEM;
2687
2688 dev->vlans = devm_kcalloc(dev->dev,
2689 dev->num_vlans, sizeof(struct b53_vlan),
2690 GFP_KERNEL);
2691 if (!dev->vlans)
2692 return -ENOMEM;
2693
2694 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
2695 if (dev->reset_gpio >= 0) {
2696 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
2697 GPIOF_OUT_INIT_HIGH, "robo_reset");
2698 if (ret)
2699 return ret;
2700 }
2701
2702 return 0;
2703}
2704
2705struct b53_device *b53_switch_alloc(struct device *base,
2706 const struct b53_io_ops *ops,
2707 void *priv)
2708{
2709 struct dsa_switch *ds;
2710 struct b53_device *dev;
2711
2712 ds = devm_kzalloc(base, sizeof(*ds), GFP_KERNEL);
2713 if (!ds)
2714 return NULL;
2715
2716 ds->dev = base;
2717
2718 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
2719 if (!dev)
2720 return NULL;
2721
2722 ds->priv = dev;
2723 dev->dev = base;
2724
2725 dev->ds = ds;
2726 dev->priv = priv;
2727 dev->ops = ops;
2728 ds->ops = &b53_switch_ops;
2729 dev->vlan_enabled = true;
2730 /* Let DSA handle the case were multiple bridges span the same switch
2731 * device and different VLAN awareness settings are requested, which
2732 * would be breaking filtering semantics for any of the other bridge
2733 * devices. (not hardware supported)
2734 */
2735 ds->vlan_filtering_is_global = true;
2736
2737 mutex_init(&dev->reg_mutex);
2738 mutex_init(&dev->stats_mutex);
2739 mutex_init(&dev->arl_mutex);
2740
2741 return dev;
2742}
2743EXPORT_SYMBOL(b53_switch_alloc);
2744
2745int b53_switch_detect(struct b53_device *dev)
2746{
2747 u32 id32;
2748 u16 tmp;
2749 u8 id8;
2750 int ret;
2751
2752 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
2753 if (ret)
2754 return ret;
2755
2756 switch (id8) {
2757 case 0:
2758 /* BCM5325 and BCM5365 do not have this register so reads
2759 * return 0. But the read operation did succeed, so assume this
2760 * is one of them.
2761 *
2762 * Next check if we can write to the 5325's VTA register; for
2763 * 5365 it is read only.
2764 */
2765 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
2766 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2767
2768 if (tmp == 0xf)
2769 dev->chip_id = BCM5325_DEVICE_ID;
2770 else
2771 dev->chip_id = BCM5365_DEVICE_ID;
2772 break;
2773 case BCM5389_DEVICE_ID:
2774 case BCM5395_DEVICE_ID:
2775 case BCM5397_DEVICE_ID:
2776 case BCM5398_DEVICE_ID:
2777 dev->chip_id = id8;
2778 break;
2779 default:
2780 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2781 if (ret)
2782 return ret;
2783
2784 switch (id32) {
2785 case BCM53115_DEVICE_ID:
2786 case BCM53125_DEVICE_ID:
2787 case BCM53128_DEVICE_ID:
2788 case BCM53010_DEVICE_ID:
2789 case BCM53011_DEVICE_ID:
2790 case BCM53012_DEVICE_ID:
2791 case BCM53018_DEVICE_ID:
2792 case BCM53019_DEVICE_ID:
2793 case BCM53134_DEVICE_ID:
2794 dev->chip_id = id32;
2795 break;
2796 default:
2797 dev_err(dev->dev,
2798 "unsupported switch detected (BCM53%02x/BCM%x)\n",
2799 id8, id32);
2800 return -ENODEV;
2801 }
2802 }
2803
2804 if (dev->chip_id == BCM5325_DEVICE_ID)
2805 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2806 &dev->core_rev);
2807 else
2808 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2809 &dev->core_rev);
2810}
2811EXPORT_SYMBOL(b53_switch_detect);
2812
2813int b53_switch_register(struct b53_device *dev)
2814{
2815 int ret;
2816
2817 if (dev->pdata) {
2818 dev->chip_id = dev->pdata->chip_id;
2819 dev->enabled_ports = dev->pdata->enabled_ports;
2820 }
2821
2822 if (!dev->chip_id && b53_switch_detect(dev))
2823 return -EINVAL;
2824
2825 ret = b53_switch_init(dev);
2826 if (ret)
2827 return ret;
2828
2829 dev_info(dev->dev, "found switch: %s, rev %i\n",
2830 dev->name, dev->core_rev);
2831
2832 return dsa_register_switch(dev->ds);
2833}
2834EXPORT_SYMBOL(b53_switch_register);
2835
2836MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2837MODULE_DESCRIPTION("B53 switch library");
2838MODULE_LICENSE("Dual BSD/GPL");