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1/*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
22#include <linux/delay.h>
23#include <linux/export.h>
24#include <linux/gpio.h>
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/platform_data/b53.h>
28#include <linux/phy.h>
29#include <linux/etherdevice.h>
30#include <linux/if_bridge.h>
31#include <net/dsa.h>
32#include <net/switchdev.h>
33
34#include "b53_regs.h"
35#include "b53_priv.h"
36
37struct b53_mib_desc {
38 u8 size;
39 u8 offset;
40 const char *name;
41};
42
43/* BCM5365 MIB counters */
44static const struct b53_mib_desc b53_mibs_65[] = {
45 { 8, 0x00, "TxOctets" },
46 { 4, 0x08, "TxDropPkts" },
47 { 4, 0x10, "TxBroadcastPkts" },
48 { 4, 0x14, "TxMulticastPkts" },
49 { 4, 0x18, "TxUnicastPkts" },
50 { 4, 0x1c, "TxCollisions" },
51 { 4, 0x20, "TxSingleCollision" },
52 { 4, 0x24, "TxMultipleCollision" },
53 { 4, 0x28, "TxDeferredTransmit" },
54 { 4, 0x2c, "TxLateCollision" },
55 { 4, 0x30, "TxExcessiveCollision" },
56 { 4, 0x38, "TxPausePkts" },
57 { 8, 0x44, "RxOctets" },
58 { 4, 0x4c, "RxUndersizePkts" },
59 { 4, 0x50, "RxPausePkts" },
60 { 4, 0x54, "Pkts64Octets" },
61 { 4, 0x58, "Pkts65to127Octets" },
62 { 4, 0x5c, "Pkts128to255Octets" },
63 { 4, 0x60, "Pkts256to511Octets" },
64 { 4, 0x64, "Pkts512to1023Octets" },
65 { 4, 0x68, "Pkts1024to1522Octets" },
66 { 4, 0x6c, "RxOversizePkts" },
67 { 4, 0x70, "RxJabbers" },
68 { 4, 0x74, "RxAlignmentErrors" },
69 { 4, 0x78, "RxFCSErrors" },
70 { 8, 0x7c, "RxGoodOctets" },
71 { 4, 0x84, "RxDropPkts" },
72 { 4, 0x88, "RxUnicastPkts" },
73 { 4, 0x8c, "RxMulticastPkts" },
74 { 4, 0x90, "RxBroadcastPkts" },
75 { 4, 0x94, "RxSAChanges" },
76 { 4, 0x98, "RxFragments" },
77};
78
79#define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
80
81/* BCM63xx MIB counters */
82static const struct b53_mib_desc b53_mibs_63xx[] = {
83 { 8, 0x00, "TxOctets" },
84 { 4, 0x08, "TxDropPkts" },
85 { 4, 0x0c, "TxQoSPkts" },
86 { 4, 0x10, "TxBroadcastPkts" },
87 { 4, 0x14, "TxMulticastPkts" },
88 { 4, 0x18, "TxUnicastPkts" },
89 { 4, 0x1c, "TxCollisions" },
90 { 4, 0x20, "TxSingleCollision" },
91 { 4, 0x24, "TxMultipleCollision" },
92 { 4, 0x28, "TxDeferredTransmit" },
93 { 4, 0x2c, "TxLateCollision" },
94 { 4, 0x30, "TxExcessiveCollision" },
95 { 4, 0x38, "TxPausePkts" },
96 { 8, 0x3c, "TxQoSOctets" },
97 { 8, 0x44, "RxOctets" },
98 { 4, 0x4c, "RxUndersizePkts" },
99 { 4, 0x50, "RxPausePkts" },
100 { 4, 0x54, "Pkts64Octets" },
101 { 4, 0x58, "Pkts65to127Octets" },
102 { 4, 0x5c, "Pkts128to255Octets" },
103 { 4, 0x60, "Pkts256to511Octets" },
104 { 4, 0x64, "Pkts512to1023Octets" },
105 { 4, 0x68, "Pkts1024to1522Octets" },
106 { 4, 0x6c, "RxOversizePkts" },
107 { 4, 0x70, "RxJabbers" },
108 { 4, 0x74, "RxAlignmentErrors" },
109 { 4, 0x78, "RxFCSErrors" },
110 { 8, 0x7c, "RxGoodOctets" },
111 { 4, 0x84, "RxDropPkts" },
112 { 4, 0x88, "RxUnicastPkts" },
113 { 4, 0x8c, "RxMulticastPkts" },
114 { 4, 0x90, "RxBroadcastPkts" },
115 { 4, 0x94, "RxSAChanges" },
116 { 4, 0x98, "RxFragments" },
117 { 4, 0xa0, "RxSymbolErrors" },
118 { 4, 0xa4, "RxQoSPkts" },
119 { 8, 0xa8, "RxQoSOctets" },
120 { 4, 0xb0, "Pkts1523to2047Octets" },
121 { 4, 0xb4, "Pkts2048to4095Octets" },
122 { 4, 0xb8, "Pkts4096to8191Octets" },
123 { 4, 0xbc, "Pkts8192to9728Octets" },
124 { 4, 0xc0, "RxDiscarded" },
125};
126
127#define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
128
129/* MIB counters */
130static const struct b53_mib_desc b53_mibs[] = {
131 { 8, 0x00, "TxOctets" },
132 { 4, 0x08, "TxDropPkts" },
133 { 4, 0x10, "TxBroadcastPkts" },
134 { 4, 0x14, "TxMulticastPkts" },
135 { 4, 0x18, "TxUnicastPkts" },
136 { 4, 0x1c, "TxCollisions" },
137 { 4, 0x20, "TxSingleCollision" },
138 { 4, 0x24, "TxMultipleCollision" },
139 { 4, 0x28, "TxDeferredTransmit" },
140 { 4, 0x2c, "TxLateCollision" },
141 { 4, 0x30, "TxExcessiveCollision" },
142 { 4, 0x38, "TxPausePkts" },
143 { 8, 0x50, "RxOctets" },
144 { 4, 0x58, "RxUndersizePkts" },
145 { 4, 0x5c, "RxPausePkts" },
146 { 4, 0x60, "Pkts64Octets" },
147 { 4, 0x64, "Pkts65to127Octets" },
148 { 4, 0x68, "Pkts128to255Octets" },
149 { 4, 0x6c, "Pkts256to511Octets" },
150 { 4, 0x70, "Pkts512to1023Octets" },
151 { 4, 0x74, "Pkts1024to1522Octets" },
152 { 4, 0x78, "RxOversizePkts" },
153 { 4, 0x7c, "RxJabbers" },
154 { 4, 0x80, "RxAlignmentErrors" },
155 { 4, 0x84, "RxFCSErrors" },
156 { 8, 0x88, "RxGoodOctets" },
157 { 4, 0x90, "RxDropPkts" },
158 { 4, 0x94, "RxUnicastPkts" },
159 { 4, 0x98, "RxMulticastPkts" },
160 { 4, 0x9c, "RxBroadcastPkts" },
161 { 4, 0xa0, "RxSAChanges" },
162 { 4, 0xa4, "RxFragments" },
163 { 4, 0xa8, "RxJumboPkts" },
164 { 4, 0xac, "RxSymbolErrors" },
165 { 4, 0xc0, "RxDiscarded" },
166};
167
168#define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
169
170static const struct b53_mib_desc b53_mibs_58xx[] = {
171 { 8, 0x00, "TxOctets" },
172 { 4, 0x08, "TxDropPkts" },
173 { 4, 0x0c, "TxQPKTQ0" },
174 { 4, 0x10, "TxBroadcastPkts" },
175 { 4, 0x14, "TxMulticastPkts" },
176 { 4, 0x18, "TxUnicastPKts" },
177 { 4, 0x1c, "TxCollisions" },
178 { 4, 0x20, "TxSingleCollision" },
179 { 4, 0x24, "TxMultipleCollision" },
180 { 4, 0x28, "TxDeferredCollision" },
181 { 4, 0x2c, "TxLateCollision" },
182 { 4, 0x30, "TxExcessiveCollision" },
183 { 4, 0x34, "TxFrameInDisc" },
184 { 4, 0x38, "TxPausePkts" },
185 { 4, 0x3c, "TxQPKTQ1" },
186 { 4, 0x40, "TxQPKTQ2" },
187 { 4, 0x44, "TxQPKTQ3" },
188 { 4, 0x48, "TxQPKTQ4" },
189 { 4, 0x4c, "TxQPKTQ5" },
190 { 8, 0x50, "RxOctets" },
191 { 4, 0x58, "RxUndersizePkts" },
192 { 4, 0x5c, "RxPausePkts" },
193 { 4, 0x60, "RxPkts64Octets" },
194 { 4, 0x64, "RxPkts65to127Octets" },
195 { 4, 0x68, "RxPkts128to255Octets" },
196 { 4, 0x6c, "RxPkts256to511Octets" },
197 { 4, 0x70, "RxPkts512to1023Octets" },
198 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
199 { 4, 0x78, "RxOversizePkts" },
200 { 4, 0x7c, "RxJabbers" },
201 { 4, 0x80, "RxAlignmentErrors" },
202 { 4, 0x84, "RxFCSErrors" },
203 { 8, 0x88, "RxGoodOctets" },
204 { 4, 0x90, "RxDropPkts" },
205 { 4, 0x94, "RxUnicastPkts" },
206 { 4, 0x98, "RxMulticastPkts" },
207 { 4, 0x9c, "RxBroadcastPkts" },
208 { 4, 0xa0, "RxSAChanges" },
209 { 4, 0xa4, "RxFragments" },
210 { 4, 0xa8, "RxJumboPkt" },
211 { 4, 0xac, "RxSymblErr" },
212 { 4, 0xb0, "InRangeErrCount" },
213 { 4, 0xb4, "OutRangeErrCount" },
214 { 4, 0xb8, "EEELpiEvent" },
215 { 4, 0xbc, "EEELpiDuration" },
216 { 4, 0xc0, "RxDiscard" },
217 { 4, 0xc8, "TxQPKTQ6" },
218 { 4, 0xcc, "TxQPKTQ7" },
219 { 4, 0xd0, "TxPkts64Octets" },
220 { 4, 0xd4, "TxPkts65to127Octets" },
221 { 4, 0xd8, "TxPkts128to255Octets" },
222 { 4, 0xdc, "TxPkts256to511Ocets" },
223 { 4, 0xe0, "TxPkts512to1023Ocets" },
224 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
225};
226
227#define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
228
229static int b53_do_vlan_op(struct b53_device *dev, u8 op)
230{
231 unsigned int i;
232
233 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
234
235 for (i = 0; i < 10; i++) {
236 u8 vta;
237
238 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
239 if (!(vta & VTA_START_CMD))
240 return 0;
241
242 usleep_range(100, 200);
243 }
244
245 return -EIO;
246}
247
248static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
249 struct b53_vlan *vlan)
250{
251 if (is5325(dev)) {
252 u32 entry = 0;
253
254 if (vlan->members) {
255 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
256 VA_UNTAG_S_25) | vlan->members;
257 if (dev->core_rev >= 3)
258 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
259 else
260 entry |= VA_VALID_25;
261 }
262
263 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
264 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
265 VTA_RW_STATE_WR | VTA_RW_OP_EN);
266 } else if (is5365(dev)) {
267 u16 entry = 0;
268
269 if (vlan->members)
270 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
271 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
272
273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
274 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
275 VTA_RW_STATE_WR | VTA_RW_OP_EN);
276 } else {
277 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
278 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
279 (vlan->untag << VTE_UNTAG_S) | vlan->members);
280
281 b53_do_vlan_op(dev, VTA_CMD_WRITE);
282 }
283
284 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
285 vid, vlan->members, vlan->untag);
286}
287
288static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
289 struct b53_vlan *vlan)
290{
291 if (is5325(dev)) {
292 u32 entry = 0;
293
294 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
295 VTA_RW_STATE_RD | VTA_RW_OP_EN);
296 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
297
298 if (dev->core_rev >= 3)
299 vlan->valid = !!(entry & VA_VALID_25_R4);
300 else
301 vlan->valid = !!(entry & VA_VALID_25);
302 vlan->members = entry & VA_MEMBER_MASK;
303 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
304
305 } else if (is5365(dev)) {
306 u16 entry = 0;
307
308 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
309 VTA_RW_STATE_WR | VTA_RW_OP_EN);
310 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
311
312 vlan->valid = !!(entry & VA_VALID_65);
313 vlan->members = entry & VA_MEMBER_MASK;
314 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
315 } else {
316 u32 entry = 0;
317
318 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
319 b53_do_vlan_op(dev, VTA_CMD_READ);
320 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
321 vlan->members = entry & VTE_MEMBERS;
322 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
323 vlan->valid = true;
324 }
325}
326
327static void b53_set_forwarding(struct b53_device *dev, int enable)
328{
329 u8 mgmt;
330
331 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
332
333 if (enable)
334 mgmt |= SM_SW_FWD_EN;
335 else
336 mgmt &= ~SM_SW_FWD_EN;
337
338 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
339}
340
341static void b53_enable_vlan(struct b53_device *dev, bool enable)
342{
343 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
344
345 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
346 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
347 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
348
349 if (is5325(dev) || is5365(dev)) {
350 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
351 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
352 } else if (is63xx(dev)) {
353 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
354 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
355 } else {
356 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
357 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
358 }
359
360 mgmt &= ~SM_SW_FWD_MODE;
361
362 if (enable) {
363 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
364 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
365 vc4 &= ~VC4_ING_VID_CHECK_MASK;
366 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
367 vc5 |= VC5_DROP_VTABLE_MISS;
368
369 if (is5325(dev))
370 vc0 &= ~VC0_RESERVED_1;
371
372 if (is5325(dev) || is5365(dev))
373 vc1 |= VC1_RX_MCST_TAG_EN;
374
375 } else {
376 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
377 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
378 vc4 &= ~VC4_ING_VID_CHECK_MASK;
379 vc5 &= ~VC5_DROP_VTABLE_MISS;
380
381 if (is5325(dev) || is5365(dev))
382 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
383 else
384 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
385
386 if (is5325(dev) || is5365(dev))
387 vc1 &= ~VC1_RX_MCST_TAG_EN;
388 }
389
390 if (!is5325(dev) && !is5365(dev))
391 vc5 &= ~VC5_VID_FFF_EN;
392
393 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
394 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
395
396 if (is5325(dev) || is5365(dev)) {
397 /* enable the high 8 bit vid check on 5325 */
398 if (is5325(dev) && enable)
399 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
400 VC3_HIGH_8BIT_EN);
401 else
402 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
403
404 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
405 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
406 } else if (is63xx(dev)) {
407 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
408 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
409 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
410 } else {
411 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
412 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
413 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
414 }
415
416 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
417}
418
419static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
420{
421 u32 port_mask = 0;
422 u16 max_size = JMS_MIN_SIZE;
423
424 if (is5325(dev) || is5365(dev))
425 return -EINVAL;
426
427 if (enable) {
428 port_mask = dev->enabled_ports;
429 max_size = JMS_MAX_SIZE;
430 if (allow_10_100)
431 port_mask |= JPM_10_100_JUMBO_EN;
432 }
433
434 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
435 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
436}
437
438static int b53_flush_arl(struct b53_device *dev, u8 mask)
439{
440 unsigned int i;
441
442 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
443 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
444
445 for (i = 0; i < 10; i++) {
446 u8 fast_age_ctrl;
447
448 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
449 &fast_age_ctrl);
450
451 if (!(fast_age_ctrl & FAST_AGE_DONE))
452 goto out;
453
454 msleep(1);
455 }
456
457 return -ETIMEDOUT;
458out:
459 /* Only age dynamic entries (default behavior) */
460 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
461 return 0;
462}
463
464static int b53_fast_age_port(struct b53_device *dev, int port)
465{
466 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
467
468 return b53_flush_arl(dev, FAST_AGE_PORT);
469}
470
471static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
472{
473 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
474
475 return b53_flush_arl(dev, FAST_AGE_VLAN);
476}
477
478static void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
479{
480 struct b53_device *dev = ds->priv;
481 unsigned int i;
482 u16 pvlan;
483
484 /* Enable the IMP port to be in the same VLAN as the other ports
485 * on a per-port basis such that we only have Port i and IMP in
486 * the same VLAN.
487 */
488 b53_for_each_port(dev, i) {
489 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
490 pvlan |= BIT(cpu_port);
491 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
492 }
493}
494
495static int b53_enable_port(struct dsa_switch *ds, int port,
496 struct phy_device *phy)
497{
498 struct b53_device *dev = ds->priv;
499 unsigned int cpu_port = dev->cpu_port;
500 u16 pvlan;
501
502 /* Clear the Rx and Tx disable bits and set to no spanning tree */
503 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
504
505 /* Set this port, and only this one to be in the default VLAN,
506 * if member of a bridge, restore its membership prior to
507 * bringing down this port.
508 */
509 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
510 pvlan &= ~0x1ff;
511 pvlan |= BIT(port);
512 pvlan |= dev->ports[port].vlan_ctl_mask;
513 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
514
515 b53_imp_vlan_setup(ds, cpu_port);
516
517 return 0;
518}
519
520static void b53_disable_port(struct dsa_switch *ds, int port,
521 struct phy_device *phy)
522{
523 struct b53_device *dev = ds->priv;
524 u8 reg;
525
526 /* Disable Tx/Rx for the port */
527 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
528 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
529 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
530}
531
532static void b53_enable_cpu_port(struct b53_device *dev)
533{
534 unsigned int cpu_port = dev->cpu_port;
535 u8 port_ctrl;
536
537 /* BCM5325 CPU port is at 8 */
538 if ((is5325(dev) || is5365(dev)) && cpu_port == B53_CPU_PORT_25)
539 cpu_port = B53_CPU_PORT;
540
541 port_ctrl = PORT_CTRL_RX_BCST_EN |
542 PORT_CTRL_RX_MCST_EN |
543 PORT_CTRL_RX_UCST_EN;
544 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(cpu_port), port_ctrl);
545}
546
547static void b53_enable_mib(struct b53_device *dev)
548{
549 u8 gc;
550
551 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
552 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
553 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
554}
555
556static int b53_configure_vlan(struct b53_device *dev)
557{
558 struct b53_vlan vl = { 0 };
559 int i;
560
561 /* clear all vlan entries */
562 if (is5325(dev) || is5365(dev)) {
563 for (i = 1; i < dev->num_vlans; i++)
564 b53_set_vlan_entry(dev, i, &vl);
565 } else {
566 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
567 }
568
569 b53_enable_vlan(dev, false);
570
571 b53_for_each_port(dev, i)
572 b53_write16(dev, B53_VLAN_PAGE,
573 B53_VLAN_PORT_DEF_TAG(i), 1);
574
575 if (!is5325(dev) && !is5365(dev))
576 b53_set_jumbo(dev, dev->enable_jumbo, false);
577
578 return 0;
579}
580
581static void b53_switch_reset_gpio(struct b53_device *dev)
582{
583 int gpio = dev->reset_gpio;
584
585 if (gpio < 0)
586 return;
587
588 /* Reset sequence: RESET low(50ms)->high(20ms)
589 */
590 gpio_set_value(gpio, 0);
591 mdelay(50);
592
593 gpio_set_value(gpio, 1);
594 mdelay(20);
595
596 dev->current_page = 0xff;
597}
598
599static int b53_switch_reset(struct b53_device *dev)
600{
601 u8 mgmt;
602
603 b53_switch_reset_gpio(dev);
604
605 if (is539x(dev)) {
606 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
607 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
608 }
609
610 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
611
612 if (!(mgmt & SM_SW_FWD_EN)) {
613 mgmt &= ~SM_SW_FWD_MODE;
614 mgmt |= SM_SW_FWD_EN;
615
616 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
617 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
618
619 if (!(mgmt & SM_SW_FWD_EN)) {
620 dev_err(dev->dev, "Failed to enable switch!\n");
621 return -EINVAL;
622 }
623 }
624
625 b53_enable_mib(dev);
626
627 return b53_flush_arl(dev, FAST_AGE_STATIC);
628}
629
630static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
631{
632 struct b53_device *priv = ds->priv;
633 u16 value = 0;
634 int ret;
635
636 if (priv->ops->phy_read16)
637 ret = priv->ops->phy_read16(priv, addr, reg, &value);
638 else
639 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
640 reg * 2, &value);
641
642 return ret ? ret : value;
643}
644
645static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
646{
647 struct b53_device *priv = ds->priv;
648
649 if (priv->ops->phy_write16)
650 return priv->ops->phy_write16(priv, addr, reg, val);
651
652 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
653}
654
655static int b53_reset_switch(struct b53_device *priv)
656{
657 /* reset vlans */
658 priv->enable_jumbo = false;
659
660 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
661 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
662
663 return b53_switch_reset(priv);
664}
665
666static int b53_apply_config(struct b53_device *priv)
667{
668 /* disable switching */
669 b53_set_forwarding(priv, 0);
670
671 b53_configure_vlan(priv);
672
673 /* enable switching */
674 b53_set_forwarding(priv, 1);
675
676 return 0;
677}
678
679static void b53_reset_mib(struct b53_device *priv)
680{
681 u8 gc;
682
683 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
684
685 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
686 msleep(1);
687 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
688 msleep(1);
689}
690
691static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
692{
693 if (is5365(dev))
694 return b53_mibs_65;
695 else if (is63xx(dev))
696 return b53_mibs_63xx;
697 else if (is58xx(dev))
698 return b53_mibs_58xx;
699 else
700 return b53_mibs;
701}
702
703static unsigned int b53_get_mib_size(struct b53_device *dev)
704{
705 if (is5365(dev))
706 return B53_MIBS_65_SIZE;
707 else if (is63xx(dev))
708 return B53_MIBS_63XX_SIZE;
709 else if (is58xx(dev))
710 return B53_MIBS_58XX_SIZE;
711 else
712 return B53_MIBS_SIZE;
713}
714
715static void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
716{
717 struct b53_device *dev = ds->priv;
718 const struct b53_mib_desc *mibs = b53_get_mib(dev);
719 unsigned int mib_size = b53_get_mib_size(dev);
720 unsigned int i;
721
722 for (i = 0; i < mib_size; i++)
723 memcpy(data + i * ETH_GSTRING_LEN,
724 mibs[i].name, ETH_GSTRING_LEN);
725}
726
727static void b53_get_ethtool_stats(struct dsa_switch *ds, int port,
728 uint64_t *data)
729{
730 struct b53_device *dev = ds->priv;
731 const struct b53_mib_desc *mibs = b53_get_mib(dev);
732 unsigned int mib_size = b53_get_mib_size(dev);
733 const struct b53_mib_desc *s;
734 unsigned int i;
735 u64 val = 0;
736
737 if (is5365(dev) && port == 5)
738 port = 8;
739
740 mutex_lock(&dev->stats_mutex);
741
742 for (i = 0; i < mib_size; i++) {
743 s = &mibs[i];
744
745 if (s->size == 8) {
746 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
747 } else {
748 u32 val32;
749
750 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
751 &val32);
752 val = val32;
753 }
754 data[i] = (u64)val;
755 }
756
757 mutex_unlock(&dev->stats_mutex);
758}
759
760static int b53_get_sset_count(struct dsa_switch *ds)
761{
762 struct b53_device *dev = ds->priv;
763
764 return b53_get_mib_size(dev);
765}
766
767static int b53_setup(struct dsa_switch *ds)
768{
769 struct b53_device *dev = ds->priv;
770 unsigned int port;
771 int ret;
772
773 ret = b53_reset_switch(dev);
774 if (ret) {
775 dev_err(ds->dev, "failed to reset switch\n");
776 return ret;
777 }
778
779 b53_reset_mib(dev);
780
781 ret = b53_apply_config(dev);
782 if (ret)
783 dev_err(ds->dev, "failed to apply configuration\n");
784
785 for (port = 0; port < dev->num_ports; port++) {
786 if (BIT(port) & ds->enabled_port_mask)
787 b53_enable_port(ds, port, NULL);
788 else if (dsa_is_cpu_port(ds, port))
789 b53_enable_cpu_port(dev);
790 else
791 b53_disable_port(ds, port, NULL);
792 }
793
794 return ret;
795}
796
797static void b53_adjust_link(struct dsa_switch *ds, int port,
798 struct phy_device *phydev)
799{
800 struct b53_device *dev = ds->priv;
801 u8 rgmii_ctrl = 0, reg = 0, off;
802
803 if (!phy_is_pseudo_fixed_link(phydev))
804 return;
805
806 /* Override the port settings */
807 if (port == dev->cpu_port) {
808 off = B53_PORT_OVERRIDE_CTRL;
809 reg = PORT_OVERRIDE_EN;
810 } else {
811 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
812 reg = GMII_PO_EN;
813 }
814
815 /* Set the link UP */
816 if (phydev->link)
817 reg |= PORT_OVERRIDE_LINK;
818
819 if (phydev->duplex == DUPLEX_FULL)
820 reg |= PORT_OVERRIDE_FULL_DUPLEX;
821
822 switch (phydev->speed) {
823 case 2000:
824 reg |= PORT_OVERRIDE_SPEED_2000M;
825 /* fallthrough */
826 case SPEED_1000:
827 reg |= PORT_OVERRIDE_SPEED_1000M;
828 break;
829 case SPEED_100:
830 reg |= PORT_OVERRIDE_SPEED_100M;
831 break;
832 case SPEED_10:
833 reg |= PORT_OVERRIDE_SPEED_10M;
834 break;
835 default:
836 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed);
837 return;
838 }
839
840 /* Enable flow control on BCM5301x's CPU port */
841 if (is5301x(dev) && port == dev->cpu_port)
842 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW;
843
844 if (phydev->pause) {
845 if (phydev->asym_pause)
846 reg |= PORT_OVERRIDE_TX_FLOW;
847 reg |= PORT_OVERRIDE_RX_FLOW;
848 }
849
850 b53_write8(dev, B53_CTRL_PAGE, off, reg);
851
852 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
853 if (port == 8)
854 off = B53_RGMII_CTRL_IMP;
855 else
856 off = B53_RGMII_CTRL_P(port);
857
858 /* Configure the port RGMII clock delay by DLL disabled and
859 * tx_clk aligned timing (restoring to reset defaults)
860 */
861 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
862 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
863 RGMII_CTRL_TIMING_SEL);
864
865 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
866 * sure that we enable the port TX clock internal delay to
867 * account for this internal delay that is inserted, otherwise
868 * the switch won't be able to receive correctly.
869 *
870 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
871 * any delay neither on transmission nor reception, so the
872 * BCM53125 must also be configured accordingly to account for
873 * the lack of delay and introduce
874 *
875 * The BCM53125 switch has its RX clock and TX clock control
876 * swapped, hence the reason why we modify the TX clock path in
877 * the "RGMII" case
878 */
879 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
880 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
881 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
882 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
883 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
884 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
885
886 dev_info(ds->dev, "Configured port %d for %s\n", port,
887 phy_modes(phydev->interface));
888 }
889
890 /* configure MII port if necessary */
891 if (is5325(dev)) {
892 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
893 ®);
894
895 /* reverse mii needs to be enabled */
896 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
897 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
898 reg | PORT_OVERRIDE_RV_MII_25);
899 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
900 ®);
901
902 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
903 dev_err(ds->dev,
904 "Failed to enable reverse MII mode\n");
905 return;
906 }
907 }
908 } else if (is5301x(dev)) {
909 if (port != dev->cpu_port) {
910 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port);
911 u8 gmii_po;
912
913 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
914 gmii_po |= GMII_PO_LINK |
915 GMII_PO_RX_FLOW |
916 GMII_PO_TX_FLOW |
917 GMII_PO_EN |
918 GMII_PO_SPEED_2000M;
919 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
920 }
921 }
922}
923
924static int b53_vlan_filtering(struct dsa_switch *ds, int port,
925 bool vlan_filtering)
926{
927 return 0;
928}
929
930static int b53_vlan_prepare(struct dsa_switch *ds, int port,
931 const struct switchdev_obj_port_vlan *vlan,
932 struct switchdev_trans *trans)
933{
934 struct b53_device *dev = ds->priv;
935
936 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
937 return -EOPNOTSUPP;
938
939 if (vlan->vid_end > dev->num_vlans)
940 return -ERANGE;
941
942 b53_enable_vlan(dev, true);
943
944 return 0;
945}
946
947static void b53_vlan_add(struct dsa_switch *ds, int port,
948 const struct switchdev_obj_port_vlan *vlan,
949 struct switchdev_trans *trans)
950{
951 struct b53_device *dev = ds->priv;
952 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
953 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
954 unsigned int cpu_port = dev->cpu_port;
955 struct b53_vlan *vl;
956 u16 vid;
957
958 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
959 vl = &dev->vlans[vid];
960
961 b53_get_vlan_entry(dev, vid, vl);
962
963 vl->members |= BIT(port) | BIT(cpu_port);
964 if (untagged)
965 vl->untag |= BIT(port);
966 else
967 vl->untag &= ~BIT(port);
968 vl->untag &= ~BIT(cpu_port);
969
970 b53_set_vlan_entry(dev, vid, vl);
971 b53_fast_age_vlan(dev, vid);
972 }
973
974 if (pvid) {
975 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
976 vlan->vid_end);
977 b53_fast_age_vlan(dev, vid);
978 }
979}
980
981static int b53_vlan_del(struct dsa_switch *ds, int port,
982 const struct switchdev_obj_port_vlan *vlan)
983{
984 struct b53_device *dev = ds->priv;
985 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
986 struct b53_vlan *vl;
987 u16 vid;
988 u16 pvid;
989
990 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
991
992 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
993 vl = &dev->vlans[vid];
994
995 b53_get_vlan_entry(dev, vid, vl);
996
997 vl->members &= ~BIT(port);
998
999 if (pvid == vid) {
1000 if (is5325(dev) || is5365(dev))
1001 pvid = 1;
1002 else
1003 pvid = 0;
1004 }
1005
1006 if (untagged)
1007 vl->untag &= ~(BIT(port));
1008
1009 b53_set_vlan_entry(dev, vid, vl);
1010 b53_fast_age_vlan(dev, vid);
1011 }
1012
1013 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1014 b53_fast_age_vlan(dev, pvid);
1015
1016 return 0;
1017}
1018
1019static int b53_vlan_dump(struct dsa_switch *ds, int port,
1020 struct switchdev_obj_port_vlan *vlan,
1021 int (*cb)(struct switchdev_obj *obj))
1022{
1023 struct b53_device *dev = ds->priv;
1024 u16 vid, vid_start = 0, pvid;
1025 struct b53_vlan *vl;
1026 int err = 0;
1027
1028 if (is5325(dev) || is5365(dev))
1029 vid_start = 1;
1030
1031 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1032
1033 /* Use our software cache for dumps, since we do not have any HW
1034 * operation returning only the used/valid VLANs
1035 */
1036 for (vid = vid_start; vid < dev->num_vlans; vid++) {
1037 vl = &dev->vlans[vid];
1038
1039 if (!vl->valid)
1040 continue;
1041
1042 if (!(vl->members & BIT(port)))
1043 continue;
1044
1045 vlan->vid_begin = vlan->vid_end = vid;
1046 vlan->flags = 0;
1047
1048 if (vl->untag & BIT(port))
1049 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED;
1050 if (pvid == vid)
1051 vlan->flags |= BRIDGE_VLAN_INFO_PVID;
1052
1053 err = cb(&vlan->obj);
1054 if (err)
1055 break;
1056 }
1057
1058 return err;
1059}
1060
1061/* Address Resolution Logic routines */
1062static int b53_arl_op_wait(struct b53_device *dev)
1063{
1064 unsigned int timeout = 10;
1065 u8 reg;
1066
1067 do {
1068 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1069 if (!(reg & ARLTBL_START_DONE))
1070 return 0;
1071
1072 usleep_range(1000, 2000);
1073 } while (timeout--);
1074
1075 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1076
1077 return -ETIMEDOUT;
1078}
1079
1080static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1081{
1082 u8 reg;
1083
1084 if (op > ARLTBL_RW)
1085 return -EINVAL;
1086
1087 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1088 reg |= ARLTBL_START_DONE;
1089 if (op)
1090 reg |= ARLTBL_RW;
1091 else
1092 reg &= ~ARLTBL_RW;
1093 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1094
1095 return b53_arl_op_wait(dev);
1096}
1097
1098static int b53_arl_read(struct b53_device *dev, u64 mac,
1099 u16 vid, struct b53_arl_entry *ent, u8 *idx,
1100 bool is_valid)
1101{
1102 unsigned int i;
1103 int ret;
1104
1105 ret = b53_arl_op_wait(dev);
1106 if (ret)
1107 return ret;
1108
1109 /* Read the bins */
1110 for (i = 0; i < dev->num_arl_entries; i++) {
1111 u64 mac_vid;
1112 u32 fwd_entry;
1113
1114 b53_read64(dev, B53_ARLIO_PAGE,
1115 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1116 b53_read32(dev, B53_ARLIO_PAGE,
1117 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1118 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1119
1120 if (!(fwd_entry & ARLTBL_VALID))
1121 continue;
1122 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1123 continue;
1124 *idx = i;
1125 }
1126
1127 return -ENOENT;
1128}
1129
1130static int b53_arl_op(struct b53_device *dev, int op, int port,
1131 const unsigned char *addr, u16 vid, bool is_valid)
1132{
1133 struct b53_arl_entry ent;
1134 u32 fwd_entry;
1135 u64 mac, mac_vid = 0;
1136 u8 idx = 0;
1137 int ret;
1138
1139 /* Convert the array into a 64-bit MAC */
1140 mac = b53_mac_to_u64(addr);
1141
1142 /* Perform a read for the given MAC and VID */
1143 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1144 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1145
1146 /* Issue a read operation for this MAC */
1147 ret = b53_arl_rw_op(dev, 1);
1148 if (ret)
1149 return ret;
1150
1151 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
1152 /* If this is a read, just finish now */
1153 if (op)
1154 return ret;
1155
1156 /* We could not find a matching MAC, so reset to a new entry */
1157 if (ret) {
1158 fwd_entry = 0;
1159 idx = 1;
1160 }
1161
1162 memset(&ent, 0, sizeof(ent));
1163 ent.port = port;
1164 ent.is_valid = is_valid;
1165 ent.vid = vid;
1166 ent.is_static = true;
1167 memcpy(ent.mac, addr, ETH_ALEN);
1168 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1169
1170 b53_write64(dev, B53_ARLIO_PAGE,
1171 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1172 b53_write32(dev, B53_ARLIO_PAGE,
1173 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1174
1175 return b53_arl_rw_op(dev, 0);
1176}
1177
1178static int b53_fdb_prepare(struct dsa_switch *ds, int port,
1179 const struct switchdev_obj_port_fdb *fdb,
1180 struct switchdev_trans *trans)
1181{
1182 struct b53_device *priv = ds->priv;
1183
1184 /* 5325 and 5365 require some more massaging, but could
1185 * be supported eventually
1186 */
1187 if (is5325(priv) || is5365(priv))
1188 return -EOPNOTSUPP;
1189
1190 return 0;
1191}
1192
1193static void b53_fdb_add(struct dsa_switch *ds, int port,
1194 const struct switchdev_obj_port_fdb *fdb,
1195 struct switchdev_trans *trans)
1196{
1197 struct b53_device *priv = ds->priv;
1198
1199 if (b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, true))
1200 pr_err("%s: failed to add MAC address\n", __func__);
1201}
1202
1203static int b53_fdb_del(struct dsa_switch *ds, int port,
1204 const struct switchdev_obj_port_fdb *fdb)
1205{
1206 struct b53_device *priv = ds->priv;
1207
1208 return b53_arl_op(priv, 0, port, fdb->addr, fdb->vid, false);
1209}
1210
1211static int b53_arl_search_wait(struct b53_device *dev)
1212{
1213 unsigned int timeout = 1000;
1214 u8 reg;
1215
1216 do {
1217 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®);
1218 if (!(reg & ARL_SRCH_STDN))
1219 return 0;
1220
1221 if (reg & ARL_SRCH_VLID)
1222 return 0;
1223
1224 usleep_range(1000, 2000);
1225 } while (timeout--);
1226
1227 return -ETIMEDOUT;
1228}
1229
1230static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1231 struct b53_arl_entry *ent)
1232{
1233 u64 mac_vid;
1234 u32 fwd_entry;
1235
1236 b53_read64(dev, B53_ARLIO_PAGE,
1237 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1238 b53_read32(dev, B53_ARLIO_PAGE,
1239 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1240 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1241}
1242
1243static int b53_fdb_copy(struct net_device *dev, int port,
1244 const struct b53_arl_entry *ent,
1245 struct switchdev_obj_port_fdb *fdb,
1246 int (*cb)(struct switchdev_obj *obj))
1247{
1248 if (!ent->is_valid)
1249 return 0;
1250
1251 if (port != ent->port)
1252 return 0;
1253
1254 ether_addr_copy(fdb->addr, ent->mac);
1255 fdb->vid = ent->vid;
1256 fdb->ndm_state = ent->is_static ? NUD_NOARP : NUD_REACHABLE;
1257
1258 return cb(&fdb->obj);
1259}
1260
1261static int b53_fdb_dump(struct dsa_switch *ds, int port,
1262 struct switchdev_obj_port_fdb *fdb,
1263 int (*cb)(struct switchdev_obj *obj))
1264{
1265 struct b53_device *priv = ds->priv;
1266 struct net_device *dev = ds->ports[port].netdev;
1267 struct b53_arl_entry results[2];
1268 unsigned int count = 0;
1269 int ret;
1270 u8 reg;
1271
1272 /* Start search operation */
1273 reg = ARL_SRCH_STDN;
1274 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1275
1276 do {
1277 ret = b53_arl_search_wait(priv);
1278 if (ret)
1279 return ret;
1280
1281 b53_arl_search_rd(priv, 0, &results[0]);
1282 ret = b53_fdb_copy(dev, port, &results[0], fdb, cb);
1283 if (ret)
1284 return ret;
1285
1286 if (priv->num_arl_entries > 2) {
1287 b53_arl_search_rd(priv, 1, &results[1]);
1288 ret = b53_fdb_copy(dev, port, &results[1], fdb, cb);
1289 if (ret)
1290 return ret;
1291
1292 if (!results[0].is_valid && !results[1].is_valid)
1293 break;
1294 }
1295
1296 } while (count++ < 1024);
1297
1298 return 0;
1299}
1300
1301static int b53_br_join(struct dsa_switch *ds, int port,
1302 struct net_device *bridge)
1303{
1304 struct b53_device *dev = ds->priv;
1305 s8 cpu_port = ds->dst->cpu_port;
1306 u16 pvlan, reg;
1307 unsigned int i;
1308
1309 /* Make this port leave the all VLANs join since we will have proper
1310 * VLAN entries from now on
1311 */
1312 if (is58xx(dev)) {
1313 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1314 reg &= ~BIT(port);
1315 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1316 reg &= ~BIT(cpu_port);
1317 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1318 }
1319
1320 dev->ports[port].bridge_dev = bridge;
1321 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1322
1323 b53_for_each_port(dev, i) {
1324 if (dev->ports[i].bridge_dev != bridge)
1325 continue;
1326
1327 /* Add this local port to the remote port VLAN control
1328 * membership and update the remote port bitmask
1329 */
1330 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1331 reg |= BIT(port);
1332 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1333 dev->ports[i].vlan_ctl_mask = reg;
1334
1335 pvlan |= BIT(i);
1336 }
1337
1338 /* Configure the local port VLAN control membership to include
1339 * remote ports and update the local port bitmask
1340 */
1341 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1342 dev->ports[port].vlan_ctl_mask = pvlan;
1343
1344 return 0;
1345}
1346
1347static void b53_br_leave(struct dsa_switch *ds, int port)
1348{
1349 struct b53_device *dev = ds->priv;
1350 struct net_device *bridge = dev->ports[port].bridge_dev;
1351 struct b53_vlan *vl = &dev->vlans[0];
1352 s8 cpu_port = ds->dst->cpu_port;
1353 unsigned int i;
1354 u16 pvlan, reg, pvid;
1355
1356 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1357
1358 b53_for_each_port(dev, i) {
1359 /* Don't touch the remaining ports */
1360 if (dev->ports[i].bridge_dev != bridge)
1361 continue;
1362
1363 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1364 reg &= ~BIT(port);
1365 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1366 dev->ports[port].vlan_ctl_mask = reg;
1367
1368 /* Prevent self removal to preserve isolation */
1369 if (port != i)
1370 pvlan &= ~BIT(i);
1371 }
1372
1373 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1374 dev->ports[port].vlan_ctl_mask = pvlan;
1375 dev->ports[port].bridge_dev = NULL;
1376
1377 if (is5325(dev) || is5365(dev))
1378 pvid = 1;
1379 else
1380 pvid = 0;
1381
1382 /* Make this port join all VLANs without VLAN entries */
1383 if (is58xx(dev)) {
1384 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1385 reg |= BIT(port);
1386 if (!(reg & BIT(cpu_port)))
1387 reg |= BIT(cpu_port);
1388 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1389 } else {
1390 b53_get_vlan_entry(dev, pvid, vl);
1391 vl->members |= BIT(port) | BIT(dev->cpu_port);
1392 vl->untag |= BIT(port) | BIT(dev->cpu_port);
1393 b53_set_vlan_entry(dev, pvid, vl);
1394 }
1395}
1396
1397static void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
1398{
1399 struct b53_device *dev = ds->priv;
1400 u8 hw_state;
1401 u8 reg;
1402
1403 switch (state) {
1404 case BR_STATE_DISABLED:
1405 hw_state = PORT_CTRL_DIS_STATE;
1406 break;
1407 case BR_STATE_LISTENING:
1408 hw_state = PORT_CTRL_LISTEN_STATE;
1409 break;
1410 case BR_STATE_LEARNING:
1411 hw_state = PORT_CTRL_LEARN_STATE;
1412 break;
1413 case BR_STATE_FORWARDING:
1414 hw_state = PORT_CTRL_FWD_STATE;
1415 break;
1416 case BR_STATE_BLOCKING:
1417 hw_state = PORT_CTRL_BLOCK_STATE;
1418 break;
1419 default:
1420 dev_err(ds->dev, "invalid STP state: %d\n", state);
1421 return;
1422 }
1423
1424 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
1425 reg &= ~PORT_CTRL_STP_STATE_MASK;
1426 reg |= hw_state;
1427 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1428}
1429
1430static void b53_br_fast_age(struct dsa_switch *ds, int port)
1431{
1432 struct b53_device *dev = ds->priv;
1433
1434 if (b53_fast_age_port(dev, port))
1435 dev_err(ds->dev, "fast ageing failed\n");
1436}
1437
1438static enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds)
1439{
1440 return DSA_TAG_PROTO_NONE;
1441}
1442
1443static struct dsa_switch_ops b53_switch_ops = {
1444 .get_tag_protocol = b53_get_tag_protocol,
1445 .setup = b53_setup,
1446 .get_strings = b53_get_strings,
1447 .get_ethtool_stats = b53_get_ethtool_stats,
1448 .get_sset_count = b53_get_sset_count,
1449 .phy_read = b53_phy_read16,
1450 .phy_write = b53_phy_write16,
1451 .adjust_link = b53_adjust_link,
1452 .port_enable = b53_enable_port,
1453 .port_disable = b53_disable_port,
1454 .port_bridge_join = b53_br_join,
1455 .port_bridge_leave = b53_br_leave,
1456 .port_stp_state_set = b53_br_set_stp_state,
1457 .port_fast_age = b53_br_fast_age,
1458 .port_vlan_filtering = b53_vlan_filtering,
1459 .port_vlan_prepare = b53_vlan_prepare,
1460 .port_vlan_add = b53_vlan_add,
1461 .port_vlan_del = b53_vlan_del,
1462 .port_vlan_dump = b53_vlan_dump,
1463 .port_fdb_prepare = b53_fdb_prepare,
1464 .port_fdb_dump = b53_fdb_dump,
1465 .port_fdb_add = b53_fdb_add,
1466 .port_fdb_del = b53_fdb_del,
1467};
1468
1469struct b53_chip_data {
1470 u32 chip_id;
1471 const char *dev_name;
1472 u16 vlans;
1473 u16 enabled_ports;
1474 u8 cpu_port;
1475 u8 vta_regs[3];
1476 u8 arl_entries;
1477 u8 duplex_reg;
1478 u8 jumbo_pm_reg;
1479 u8 jumbo_size_reg;
1480};
1481
1482#define B53_VTA_REGS \
1483 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1484#define B53_VTA_REGS_9798 \
1485 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1486#define B53_VTA_REGS_63XX \
1487 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1488
1489static const struct b53_chip_data b53_switch_chips[] = {
1490 {
1491 .chip_id = BCM5325_DEVICE_ID,
1492 .dev_name = "BCM5325",
1493 .vlans = 16,
1494 .enabled_ports = 0x1f,
1495 .arl_entries = 2,
1496 .cpu_port = B53_CPU_PORT_25,
1497 .duplex_reg = B53_DUPLEX_STAT_FE,
1498 },
1499 {
1500 .chip_id = BCM5365_DEVICE_ID,
1501 .dev_name = "BCM5365",
1502 .vlans = 256,
1503 .enabled_ports = 0x1f,
1504 .arl_entries = 2,
1505 .cpu_port = B53_CPU_PORT_25,
1506 .duplex_reg = B53_DUPLEX_STAT_FE,
1507 },
1508 {
1509 .chip_id = BCM5395_DEVICE_ID,
1510 .dev_name = "BCM5395",
1511 .vlans = 4096,
1512 .enabled_ports = 0x1f,
1513 .arl_entries = 4,
1514 .cpu_port = B53_CPU_PORT,
1515 .vta_regs = B53_VTA_REGS,
1516 .duplex_reg = B53_DUPLEX_STAT_GE,
1517 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1518 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1519 },
1520 {
1521 .chip_id = BCM5397_DEVICE_ID,
1522 .dev_name = "BCM5397",
1523 .vlans = 4096,
1524 .enabled_ports = 0x1f,
1525 .arl_entries = 4,
1526 .cpu_port = B53_CPU_PORT,
1527 .vta_regs = B53_VTA_REGS_9798,
1528 .duplex_reg = B53_DUPLEX_STAT_GE,
1529 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1530 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1531 },
1532 {
1533 .chip_id = BCM5398_DEVICE_ID,
1534 .dev_name = "BCM5398",
1535 .vlans = 4096,
1536 .enabled_ports = 0x7f,
1537 .arl_entries = 4,
1538 .cpu_port = B53_CPU_PORT,
1539 .vta_regs = B53_VTA_REGS_9798,
1540 .duplex_reg = B53_DUPLEX_STAT_GE,
1541 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1542 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1543 },
1544 {
1545 .chip_id = BCM53115_DEVICE_ID,
1546 .dev_name = "BCM53115",
1547 .vlans = 4096,
1548 .enabled_ports = 0x1f,
1549 .arl_entries = 4,
1550 .vta_regs = B53_VTA_REGS,
1551 .cpu_port = B53_CPU_PORT,
1552 .duplex_reg = B53_DUPLEX_STAT_GE,
1553 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1554 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1555 },
1556 {
1557 .chip_id = BCM53125_DEVICE_ID,
1558 .dev_name = "BCM53125",
1559 .vlans = 4096,
1560 .enabled_ports = 0xff,
1561 .cpu_port = B53_CPU_PORT,
1562 .vta_regs = B53_VTA_REGS,
1563 .duplex_reg = B53_DUPLEX_STAT_GE,
1564 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1565 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1566 },
1567 {
1568 .chip_id = BCM53128_DEVICE_ID,
1569 .dev_name = "BCM53128",
1570 .vlans = 4096,
1571 .enabled_ports = 0x1ff,
1572 .arl_entries = 4,
1573 .cpu_port = B53_CPU_PORT,
1574 .vta_regs = B53_VTA_REGS,
1575 .duplex_reg = B53_DUPLEX_STAT_GE,
1576 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1577 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1578 },
1579 {
1580 .chip_id = BCM63XX_DEVICE_ID,
1581 .dev_name = "BCM63xx",
1582 .vlans = 4096,
1583 .enabled_ports = 0, /* pdata must provide them */
1584 .arl_entries = 4,
1585 .cpu_port = B53_CPU_PORT,
1586 .vta_regs = B53_VTA_REGS_63XX,
1587 .duplex_reg = B53_DUPLEX_STAT_63XX,
1588 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1589 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1590 },
1591 {
1592 .chip_id = BCM53010_DEVICE_ID,
1593 .dev_name = "BCM53010",
1594 .vlans = 4096,
1595 .enabled_ports = 0x1f,
1596 .arl_entries = 4,
1597 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1598 .vta_regs = B53_VTA_REGS,
1599 .duplex_reg = B53_DUPLEX_STAT_GE,
1600 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1601 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1602 },
1603 {
1604 .chip_id = BCM53011_DEVICE_ID,
1605 .dev_name = "BCM53011",
1606 .vlans = 4096,
1607 .enabled_ports = 0x1bf,
1608 .arl_entries = 4,
1609 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1610 .vta_regs = B53_VTA_REGS,
1611 .duplex_reg = B53_DUPLEX_STAT_GE,
1612 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1613 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1614 },
1615 {
1616 .chip_id = BCM53012_DEVICE_ID,
1617 .dev_name = "BCM53012",
1618 .vlans = 4096,
1619 .enabled_ports = 0x1bf,
1620 .arl_entries = 4,
1621 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1622 .vta_regs = B53_VTA_REGS,
1623 .duplex_reg = B53_DUPLEX_STAT_GE,
1624 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1625 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1626 },
1627 {
1628 .chip_id = BCM53018_DEVICE_ID,
1629 .dev_name = "BCM53018",
1630 .vlans = 4096,
1631 .enabled_ports = 0x1f,
1632 .arl_entries = 4,
1633 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1634 .vta_regs = B53_VTA_REGS,
1635 .duplex_reg = B53_DUPLEX_STAT_GE,
1636 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1637 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1638 },
1639 {
1640 .chip_id = BCM53019_DEVICE_ID,
1641 .dev_name = "BCM53019",
1642 .vlans = 4096,
1643 .enabled_ports = 0x1f,
1644 .arl_entries = 4,
1645 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1646 .vta_regs = B53_VTA_REGS,
1647 .duplex_reg = B53_DUPLEX_STAT_GE,
1648 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1649 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1650 },
1651 {
1652 .chip_id = BCM58XX_DEVICE_ID,
1653 .dev_name = "BCM585xx/586xx/88312",
1654 .vlans = 4096,
1655 .enabled_ports = 0x1ff,
1656 .arl_entries = 4,
1657 .cpu_port = B53_CPU_PORT_25,
1658 .vta_regs = B53_VTA_REGS,
1659 .duplex_reg = B53_DUPLEX_STAT_GE,
1660 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1661 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1662 },
1663 {
1664 .chip_id = BCM7445_DEVICE_ID,
1665 .dev_name = "BCM7445",
1666 .vlans = 4096,
1667 .enabled_ports = 0x1ff,
1668 .arl_entries = 4,
1669 .cpu_port = B53_CPU_PORT,
1670 .vta_regs = B53_VTA_REGS,
1671 .duplex_reg = B53_DUPLEX_STAT_GE,
1672 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1673 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1674 },
1675};
1676
1677static int b53_switch_init(struct b53_device *dev)
1678{
1679 unsigned int i;
1680 int ret;
1681
1682 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1683 const struct b53_chip_data *chip = &b53_switch_chips[i];
1684
1685 if (chip->chip_id == dev->chip_id) {
1686 if (!dev->enabled_ports)
1687 dev->enabled_ports = chip->enabled_ports;
1688 dev->name = chip->dev_name;
1689 dev->duplex_reg = chip->duplex_reg;
1690 dev->vta_regs[0] = chip->vta_regs[0];
1691 dev->vta_regs[1] = chip->vta_regs[1];
1692 dev->vta_regs[2] = chip->vta_regs[2];
1693 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
1694 dev->cpu_port = chip->cpu_port;
1695 dev->num_vlans = chip->vlans;
1696 dev->num_arl_entries = chip->arl_entries;
1697 break;
1698 }
1699 }
1700
1701 /* check which BCM5325x version we have */
1702 if (is5325(dev)) {
1703 u8 vc4;
1704
1705 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1706
1707 /* check reserved bits */
1708 switch (vc4 & 3) {
1709 case 1:
1710 /* BCM5325E */
1711 break;
1712 case 3:
1713 /* BCM5325F - do not use port 4 */
1714 dev->enabled_ports &= ~BIT(4);
1715 break;
1716 default:
1717/* On the BCM47XX SoCs this is the supported internal switch.*/
1718#ifndef CONFIG_BCM47XX
1719 /* BCM5325M */
1720 return -EINVAL;
1721#else
1722 break;
1723#endif
1724 }
1725 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1726 u64 strap_value;
1727
1728 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1729 /* use second IMP port if GMII is enabled */
1730 if (strap_value & SV_GMII_CTRL_115)
1731 dev->cpu_port = 5;
1732 }
1733
1734 /* cpu port is always last */
1735 dev->num_ports = dev->cpu_port + 1;
1736 dev->enabled_ports |= BIT(dev->cpu_port);
1737
1738 dev->ports = devm_kzalloc(dev->dev,
1739 sizeof(struct b53_port) * dev->num_ports,
1740 GFP_KERNEL);
1741 if (!dev->ports)
1742 return -ENOMEM;
1743
1744 dev->vlans = devm_kzalloc(dev->dev,
1745 sizeof(struct b53_vlan) * dev->num_vlans,
1746 GFP_KERNEL);
1747 if (!dev->vlans)
1748 return -ENOMEM;
1749
1750 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1751 if (dev->reset_gpio >= 0) {
1752 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1753 GPIOF_OUT_INIT_HIGH, "robo_reset");
1754 if (ret)
1755 return ret;
1756 }
1757
1758 return 0;
1759}
1760
1761struct b53_device *b53_switch_alloc(struct device *base,
1762 const struct b53_io_ops *ops,
1763 void *priv)
1764{
1765 struct dsa_switch *ds;
1766 struct b53_device *dev;
1767
1768 ds = devm_kzalloc(base, sizeof(*ds) + sizeof(*dev), GFP_KERNEL);
1769 if (!ds)
1770 return NULL;
1771
1772 dev = (struct b53_device *)(ds + 1);
1773
1774 ds->priv = dev;
1775 ds->dev = base;
1776 dev->dev = base;
1777
1778 dev->ds = ds;
1779 dev->priv = priv;
1780 dev->ops = ops;
1781 ds->ops = &b53_switch_ops;
1782 mutex_init(&dev->reg_mutex);
1783 mutex_init(&dev->stats_mutex);
1784
1785 return dev;
1786}
1787EXPORT_SYMBOL(b53_switch_alloc);
1788
1789int b53_switch_detect(struct b53_device *dev)
1790{
1791 u32 id32;
1792 u16 tmp;
1793 u8 id8;
1794 int ret;
1795
1796 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
1797 if (ret)
1798 return ret;
1799
1800 switch (id8) {
1801 case 0:
1802 /* BCM5325 and BCM5365 do not have this register so reads
1803 * return 0. But the read operation did succeed, so assume this
1804 * is one of them.
1805 *
1806 * Next check if we can write to the 5325's VTA register; for
1807 * 5365 it is read only.
1808 */
1809 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
1810 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
1811
1812 if (tmp == 0xf)
1813 dev->chip_id = BCM5325_DEVICE_ID;
1814 else
1815 dev->chip_id = BCM5365_DEVICE_ID;
1816 break;
1817 case BCM5395_DEVICE_ID:
1818 case BCM5397_DEVICE_ID:
1819 case BCM5398_DEVICE_ID:
1820 dev->chip_id = id8;
1821 break;
1822 default:
1823 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
1824 if (ret)
1825 return ret;
1826
1827 switch (id32) {
1828 case BCM53115_DEVICE_ID:
1829 case BCM53125_DEVICE_ID:
1830 case BCM53128_DEVICE_ID:
1831 case BCM53010_DEVICE_ID:
1832 case BCM53011_DEVICE_ID:
1833 case BCM53012_DEVICE_ID:
1834 case BCM53018_DEVICE_ID:
1835 case BCM53019_DEVICE_ID:
1836 dev->chip_id = id32;
1837 break;
1838 default:
1839 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
1840 id8, id32);
1841 return -ENODEV;
1842 }
1843 }
1844
1845 if (dev->chip_id == BCM5325_DEVICE_ID)
1846 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
1847 &dev->core_rev);
1848 else
1849 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
1850 &dev->core_rev);
1851}
1852EXPORT_SYMBOL(b53_switch_detect);
1853
1854int b53_switch_register(struct b53_device *dev)
1855{
1856 int ret;
1857
1858 if (dev->pdata) {
1859 dev->chip_id = dev->pdata->chip_id;
1860 dev->enabled_ports = dev->pdata->enabled_ports;
1861 }
1862
1863 if (!dev->chip_id && b53_switch_detect(dev))
1864 return -EINVAL;
1865
1866 ret = b53_switch_init(dev);
1867 if (ret)
1868 return ret;
1869
1870 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
1871
1872 return dsa_register_switch(dev->ds, dev->ds->dev->of_node);
1873}
1874EXPORT_SYMBOL(b53_switch_register);
1875
1876MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
1877MODULE_DESCRIPTION("B53 switch library");
1878MODULE_LICENSE("Dual BSD/GPL");
1/*
2 * B53 switch driver main logic
3 *
4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
6 *
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19
20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
21
22#include <linux/delay.h>
23#include <linux/export.h>
24#include <linux/gpio.h>
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/platform_data/b53.h>
28#include <linux/phy.h>
29#include <linux/etherdevice.h>
30#include <linux/if_bridge.h>
31#include <net/dsa.h>
32
33#include "b53_regs.h"
34#include "b53_priv.h"
35
36struct b53_mib_desc {
37 u8 size;
38 u8 offset;
39 const char *name;
40};
41
42/* BCM5365 MIB counters */
43static const struct b53_mib_desc b53_mibs_65[] = {
44 { 8, 0x00, "TxOctets" },
45 { 4, 0x08, "TxDropPkts" },
46 { 4, 0x10, "TxBroadcastPkts" },
47 { 4, 0x14, "TxMulticastPkts" },
48 { 4, 0x18, "TxUnicastPkts" },
49 { 4, 0x1c, "TxCollisions" },
50 { 4, 0x20, "TxSingleCollision" },
51 { 4, 0x24, "TxMultipleCollision" },
52 { 4, 0x28, "TxDeferredTransmit" },
53 { 4, 0x2c, "TxLateCollision" },
54 { 4, 0x30, "TxExcessiveCollision" },
55 { 4, 0x38, "TxPausePkts" },
56 { 8, 0x44, "RxOctets" },
57 { 4, 0x4c, "RxUndersizePkts" },
58 { 4, 0x50, "RxPausePkts" },
59 { 4, 0x54, "Pkts64Octets" },
60 { 4, 0x58, "Pkts65to127Octets" },
61 { 4, 0x5c, "Pkts128to255Octets" },
62 { 4, 0x60, "Pkts256to511Octets" },
63 { 4, 0x64, "Pkts512to1023Octets" },
64 { 4, 0x68, "Pkts1024to1522Octets" },
65 { 4, 0x6c, "RxOversizePkts" },
66 { 4, 0x70, "RxJabbers" },
67 { 4, 0x74, "RxAlignmentErrors" },
68 { 4, 0x78, "RxFCSErrors" },
69 { 8, 0x7c, "RxGoodOctets" },
70 { 4, 0x84, "RxDropPkts" },
71 { 4, 0x88, "RxUnicastPkts" },
72 { 4, 0x8c, "RxMulticastPkts" },
73 { 4, 0x90, "RxBroadcastPkts" },
74 { 4, 0x94, "RxSAChanges" },
75 { 4, 0x98, "RxFragments" },
76};
77
78#define B53_MIBS_65_SIZE ARRAY_SIZE(b53_mibs_65)
79
80/* BCM63xx MIB counters */
81static const struct b53_mib_desc b53_mibs_63xx[] = {
82 { 8, 0x00, "TxOctets" },
83 { 4, 0x08, "TxDropPkts" },
84 { 4, 0x0c, "TxQoSPkts" },
85 { 4, 0x10, "TxBroadcastPkts" },
86 { 4, 0x14, "TxMulticastPkts" },
87 { 4, 0x18, "TxUnicastPkts" },
88 { 4, 0x1c, "TxCollisions" },
89 { 4, 0x20, "TxSingleCollision" },
90 { 4, 0x24, "TxMultipleCollision" },
91 { 4, 0x28, "TxDeferredTransmit" },
92 { 4, 0x2c, "TxLateCollision" },
93 { 4, 0x30, "TxExcessiveCollision" },
94 { 4, 0x38, "TxPausePkts" },
95 { 8, 0x3c, "TxQoSOctets" },
96 { 8, 0x44, "RxOctets" },
97 { 4, 0x4c, "RxUndersizePkts" },
98 { 4, 0x50, "RxPausePkts" },
99 { 4, 0x54, "Pkts64Octets" },
100 { 4, 0x58, "Pkts65to127Octets" },
101 { 4, 0x5c, "Pkts128to255Octets" },
102 { 4, 0x60, "Pkts256to511Octets" },
103 { 4, 0x64, "Pkts512to1023Octets" },
104 { 4, 0x68, "Pkts1024to1522Octets" },
105 { 4, 0x6c, "RxOversizePkts" },
106 { 4, 0x70, "RxJabbers" },
107 { 4, 0x74, "RxAlignmentErrors" },
108 { 4, 0x78, "RxFCSErrors" },
109 { 8, 0x7c, "RxGoodOctets" },
110 { 4, 0x84, "RxDropPkts" },
111 { 4, 0x88, "RxUnicastPkts" },
112 { 4, 0x8c, "RxMulticastPkts" },
113 { 4, 0x90, "RxBroadcastPkts" },
114 { 4, 0x94, "RxSAChanges" },
115 { 4, 0x98, "RxFragments" },
116 { 4, 0xa0, "RxSymbolErrors" },
117 { 4, 0xa4, "RxQoSPkts" },
118 { 8, 0xa8, "RxQoSOctets" },
119 { 4, 0xb0, "Pkts1523to2047Octets" },
120 { 4, 0xb4, "Pkts2048to4095Octets" },
121 { 4, 0xb8, "Pkts4096to8191Octets" },
122 { 4, 0xbc, "Pkts8192to9728Octets" },
123 { 4, 0xc0, "RxDiscarded" },
124};
125
126#define B53_MIBS_63XX_SIZE ARRAY_SIZE(b53_mibs_63xx)
127
128/* MIB counters */
129static const struct b53_mib_desc b53_mibs[] = {
130 { 8, 0x00, "TxOctets" },
131 { 4, 0x08, "TxDropPkts" },
132 { 4, 0x10, "TxBroadcastPkts" },
133 { 4, 0x14, "TxMulticastPkts" },
134 { 4, 0x18, "TxUnicastPkts" },
135 { 4, 0x1c, "TxCollisions" },
136 { 4, 0x20, "TxSingleCollision" },
137 { 4, 0x24, "TxMultipleCollision" },
138 { 4, 0x28, "TxDeferredTransmit" },
139 { 4, 0x2c, "TxLateCollision" },
140 { 4, 0x30, "TxExcessiveCollision" },
141 { 4, 0x38, "TxPausePkts" },
142 { 8, 0x50, "RxOctets" },
143 { 4, 0x58, "RxUndersizePkts" },
144 { 4, 0x5c, "RxPausePkts" },
145 { 4, 0x60, "Pkts64Octets" },
146 { 4, 0x64, "Pkts65to127Octets" },
147 { 4, 0x68, "Pkts128to255Octets" },
148 { 4, 0x6c, "Pkts256to511Octets" },
149 { 4, 0x70, "Pkts512to1023Octets" },
150 { 4, 0x74, "Pkts1024to1522Octets" },
151 { 4, 0x78, "RxOversizePkts" },
152 { 4, 0x7c, "RxJabbers" },
153 { 4, 0x80, "RxAlignmentErrors" },
154 { 4, 0x84, "RxFCSErrors" },
155 { 8, 0x88, "RxGoodOctets" },
156 { 4, 0x90, "RxDropPkts" },
157 { 4, 0x94, "RxUnicastPkts" },
158 { 4, 0x98, "RxMulticastPkts" },
159 { 4, 0x9c, "RxBroadcastPkts" },
160 { 4, 0xa0, "RxSAChanges" },
161 { 4, 0xa4, "RxFragments" },
162 { 4, 0xa8, "RxJumboPkts" },
163 { 4, 0xac, "RxSymbolErrors" },
164 { 4, 0xc0, "RxDiscarded" },
165};
166
167#define B53_MIBS_SIZE ARRAY_SIZE(b53_mibs)
168
169static const struct b53_mib_desc b53_mibs_58xx[] = {
170 { 8, 0x00, "TxOctets" },
171 { 4, 0x08, "TxDropPkts" },
172 { 4, 0x0c, "TxQPKTQ0" },
173 { 4, 0x10, "TxBroadcastPkts" },
174 { 4, 0x14, "TxMulticastPkts" },
175 { 4, 0x18, "TxUnicastPKts" },
176 { 4, 0x1c, "TxCollisions" },
177 { 4, 0x20, "TxSingleCollision" },
178 { 4, 0x24, "TxMultipleCollision" },
179 { 4, 0x28, "TxDeferredCollision" },
180 { 4, 0x2c, "TxLateCollision" },
181 { 4, 0x30, "TxExcessiveCollision" },
182 { 4, 0x34, "TxFrameInDisc" },
183 { 4, 0x38, "TxPausePkts" },
184 { 4, 0x3c, "TxQPKTQ1" },
185 { 4, 0x40, "TxQPKTQ2" },
186 { 4, 0x44, "TxQPKTQ3" },
187 { 4, 0x48, "TxQPKTQ4" },
188 { 4, 0x4c, "TxQPKTQ5" },
189 { 8, 0x50, "RxOctets" },
190 { 4, 0x58, "RxUndersizePkts" },
191 { 4, 0x5c, "RxPausePkts" },
192 { 4, 0x60, "RxPkts64Octets" },
193 { 4, 0x64, "RxPkts65to127Octets" },
194 { 4, 0x68, "RxPkts128to255Octets" },
195 { 4, 0x6c, "RxPkts256to511Octets" },
196 { 4, 0x70, "RxPkts512to1023Octets" },
197 { 4, 0x74, "RxPkts1024toMaxPktsOctets" },
198 { 4, 0x78, "RxOversizePkts" },
199 { 4, 0x7c, "RxJabbers" },
200 { 4, 0x80, "RxAlignmentErrors" },
201 { 4, 0x84, "RxFCSErrors" },
202 { 8, 0x88, "RxGoodOctets" },
203 { 4, 0x90, "RxDropPkts" },
204 { 4, 0x94, "RxUnicastPkts" },
205 { 4, 0x98, "RxMulticastPkts" },
206 { 4, 0x9c, "RxBroadcastPkts" },
207 { 4, 0xa0, "RxSAChanges" },
208 { 4, 0xa4, "RxFragments" },
209 { 4, 0xa8, "RxJumboPkt" },
210 { 4, 0xac, "RxSymblErr" },
211 { 4, 0xb0, "InRangeErrCount" },
212 { 4, 0xb4, "OutRangeErrCount" },
213 { 4, 0xb8, "EEELpiEvent" },
214 { 4, 0xbc, "EEELpiDuration" },
215 { 4, 0xc0, "RxDiscard" },
216 { 4, 0xc8, "TxQPKTQ6" },
217 { 4, 0xcc, "TxQPKTQ7" },
218 { 4, 0xd0, "TxPkts64Octets" },
219 { 4, 0xd4, "TxPkts65to127Octets" },
220 { 4, 0xd8, "TxPkts128to255Octets" },
221 { 4, 0xdc, "TxPkts256to511Ocets" },
222 { 4, 0xe0, "TxPkts512to1023Ocets" },
223 { 4, 0xe4, "TxPkts1024toMaxPktOcets" },
224};
225
226#define B53_MIBS_58XX_SIZE ARRAY_SIZE(b53_mibs_58xx)
227
228static int b53_do_vlan_op(struct b53_device *dev, u8 op)
229{
230 unsigned int i;
231
232 b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
233
234 for (i = 0; i < 10; i++) {
235 u8 vta;
236
237 b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
238 if (!(vta & VTA_START_CMD))
239 return 0;
240
241 usleep_range(100, 200);
242 }
243
244 return -EIO;
245}
246
247static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
248 struct b53_vlan *vlan)
249{
250 if (is5325(dev)) {
251 u32 entry = 0;
252
253 if (vlan->members) {
254 entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
255 VA_UNTAG_S_25) | vlan->members;
256 if (dev->core_rev >= 3)
257 entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
258 else
259 entry |= VA_VALID_25;
260 }
261
262 b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
263 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
264 VTA_RW_STATE_WR | VTA_RW_OP_EN);
265 } else if (is5365(dev)) {
266 u16 entry = 0;
267
268 if (vlan->members)
269 entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
270 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
271
272 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
273 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
274 VTA_RW_STATE_WR | VTA_RW_OP_EN);
275 } else {
276 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
277 b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
278 (vlan->untag << VTE_UNTAG_S) | vlan->members);
279
280 b53_do_vlan_op(dev, VTA_CMD_WRITE);
281 }
282
283 dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
284 vid, vlan->members, vlan->untag);
285}
286
287static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
288 struct b53_vlan *vlan)
289{
290 if (is5325(dev)) {
291 u32 entry = 0;
292
293 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
294 VTA_RW_STATE_RD | VTA_RW_OP_EN);
295 b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
296
297 if (dev->core_rev >= 3)
298 vlan->valid = !!(entry & VA_VALID_25_R4);
299 else
300 vlan->valid = !!(entry & VA_VALID_25);
301 vlan->members = entry & VA_MEMBER_MASK;
302 vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
303
304 } else if (is5365(dev)) {
305 u16 entry = 0;
306
307 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
308 VTA_RW_STATE_WR | VTA_RW_OP_EN);
309 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
310
311 vlan->valid = !!(entry & VA_VALID_65);
312 vlan->members = entry & VA_MEMBER_MASK;
313 vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
314 } else {
315 u32 entry = 0;
316
317 b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
318 b53_do_vlan_op(dev, VTA_CMD_READ);
319 b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
320 vlan->members = entry & VTE_MEMBERS;
321 vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
322 vlan->valid = true;
323 }
324}
325
326static void b53_set_forwarding(struct b53_device *dev, int enable)
327{
328 u8 mgmt;
329
330 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
331
332 if (enable)
333 mgmt |= SM_SW_FWD_EN;
334 else
335 mgmt &= ~SM_SW_FWD_EN;
336
337 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
338
339 /* Include IMP port in dumb forwarding mode
340 */
341 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
342 mgmt |= B53_MII_DUMB_FWDG_EN;
343 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
344}
345
346static void b53_enable_vlan(struct b53_device *dev, bool enable)
347{
348 u8 mgmt, vc0, vc1, vc4 = 0, vc5;
349
350 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
351 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
352 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
353
354 if (is5325(dev) || is5365(dev)) {
355 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
356 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
357 } else if (is63xx(dev)) {
358 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
359 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
360 } else {
361 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
362 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
363 }
364
365 mgmt &= ~SM_SW_FWD_MODE;
366
367 if (enable) {
368 vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
369 vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
370 vc4 &= ~VC4_ING_VID_CHECK_MASK;
371 vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
372 vc5 |= VC5_DROP_VTABLE_MISS;
373
374 if (is5325(dev))
375 vc0 &= ~VC0_RESERVED_1;
376
377 if (is5325(dev) || is5365(dev))
378 vc1 |= VC1_RX_MCST_TAG_EN;
379
380 } else {
381 vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
382 vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
383 vc4 &= ~VC4_ING_VID_CHECK_MASK;
384 vc5 &= ~VC5_DROP_VTABLE_MISS;
385
386 if (is5325(dev) || is5365(dev))
387 vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
388 else
389 vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
390
391 if (is5325(dev) || is5365(dev))
392 vc1 &= ~VC1_RX_MCST_TAG_EN;
393 }
394
395 if (!is5325(dev) && !is5365(dev))
396 vc5 &= ~VC5_VID_FFF_EN;
397
398 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
399 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
400
401 if (is5325(dev) || is5365(dev)) {
402 /* enable the high 8 bit vid check on 5325 */
403 if (is5325(dev) && enable)
404 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
405 VC3_HIGH_8BIT_EN);
406 else
407 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
408
409 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
410 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
411 } else if (is63xx(dev)) {
412 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
413 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
414 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
415 } else {
416 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
417 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
418 b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
419 }
420
421 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
422}
423
424static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
425{
426 u32 port_mask = 0;
427 u16 max_size = JMS_MIN_SIZE;
428
429 if (is5325(dev) || is5365(dev))
430 return -EINVAL;
431
432 if (enable) {
433 port_mask = dev->enabled_ports;
434 max_size = JMS_MAX_SIZE;
435 if (allow_10_100)
436 port_mask |= JPM_10_100_JUMBO_EN;
437 }
438
439 b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
440 return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
441}
442
443static int b53_flush_arl(struct b53_device *dev, u8 mask)
444{
445 unsigned int i;
446
447 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
448 FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
449
450 for (i = 0; i < 10; i++) {
451 u8 fast_age_ctrl;
452
453 b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
454 &fast_age_ctrl);
455
456 if (!(fast_age_ctrl & FAST_AGE_DONE))
457 goto out;
458
459 msleep(1);
460 }
461
462 return -ETIMEDOUT;
463out:
464 /* Only age dynamic entries (default behavior) */
465 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
466 return 0;
467}
468
469static int b53_fast_age_port(struct b53_device *dev, int port)
470{
471 b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
472
473 return b53_flush_arl(dev, FAST_AGE_PORT);
474}
475
476static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
477{
478 b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
479
480 return b53_flush_arl(dev, FAST_AGE_VLAN);
481}
482
483void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
484{
485 struct b53_device *dev = ds->priv;
486 unsigned int i;
487 u16 pvlan;
488
489 /* Enable the IMP port to be in the same VLAN as the other ports
490 * on a per-port basis such that we only have Port i and IMP in
491 * the same VLAN.
492 */
493 b53_for_each_port(dev, i) {
494 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
495 pvlan |= BIT(cpu_port);
496 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
497 }
498}
499EXPORT_SYMBOL(b53_imp_vlan_setup);
500
501int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
502{
503 struct b53_device *dev = ds->priv;
504 unsigned int cpu_port = ds->ports[port].cpu_dp->index;
505 u16 pvlan;
506
507 /* Clear the Rx and Tx disable bits and set to no spanning tree */
508 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
509
510 /* Set this port, and only this one to be in the default VLAN,
511 * if member of a bridge, restore its membership prior to
512 * bringing down this port.
513 */
514 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
515 pvlan &= ~0x1ff;
516 pvlan |= BIT(port);
517 pvlan |= dev->ports[port].vlan_ctl_mask;
518 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
519
520 b53_imp_vlan_setup(ds, cpu_port);
521
522 /* If EEE was enabled, restore it */
523 if (dev->ports[port].eee.eee_enabled)
524 b53_eee_enable_set(ds, port, true);
525
526 return 0;
527}
528EXPORT_SYMBOL(b53_enable_port);
529
530void b53_disable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
531{
532 struct b53_device *dev = ds->priv;
533 u8 reg;
534
535 /* Disable Tx/Rx for the port */
536 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
537 reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
538 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
539}
540EXPORT_SYMBOL(b53_disable_port);
541
542void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
543{
544 bool tag_en = !(ds->ops->get_tag_protocol(ds, port) ==
545 DSA_TAG_PROTO_NONE);
546 struct b53_device *dev = ds->priv;
547 u8 hdr_ctl, val;
548 u16 reg;
549
550 /* Resolve which bit controls the Broadcom tag */
551 switch (port) {
552 case 8:
553 val = BRCM_HDR_P8_EN;
554 break;
555 case 7:
556 val = BRCM_HDR_P7_EN;
557 break;
558 case 5:
559 val = BRCM_HDR_P5_EN;
560 break;
561 default:
562 val = 0;
563 break;
564 }
565
566 /* Enable Broadcom tags for IMP port */
567 b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
568 if (tag_en)
569 hdr_ctl |= val;
570 else
571 hdr_ctl &= ~val;
572 b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
573
574 /* Registers below are only accessible on newer devices */
575 if (!is58xx(dev))
576 return;
577
578 /* Enable reception Broadcom tag for CPU TX (switch RX) to
579 * allow us to tag outgoing frames
580 */
581 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, ®);
582 if (tag_en)
583 reg &= ~BIT(port);
584 else
585 reg |= BIT(port);
586 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
587
588 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
589 * allow delivering frames to the per-port net_devices
590 */
591 b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, ®);
592 if (tag_en)
593 reg &= ~BIT(port);
594 else
595 reg |= BIT(port);
596 b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
597}
598EXPORT_SYMBOL(b53_brcm_hdr_setup);
599
600static void b53_enable_cpu_port(struct b53_device *dev, int port)
601{
602 u8 port_ctrl;
603
604 /* BCM5325 CPU port is at 8 */
605 if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
606 port = B53_CPU_PORT;
607
608 port_ctrl = PORT_CTRL_RX_BCST_EN |
609 PORT_CTRL_RX_MCST_EN |
610 PORT_CTRL_RX_UCST_EN;
611 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
612
613 b53_brcm_hdr_setup(dev->ds, port);
614}
615
616static void b53_enable_mib(struct b53_device *dev)
617{
618 u8 gc;
619
620 b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
621 gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
622 b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
623}
624
625int b53_configure_vlan(struct dsa_switch *ds)
626{
627 struct b53_device *dev = ds->priv;
628 struct b53_vlan vl = { 0 };
629 int i;
630
631 /* clear all vlan entries */
632 if (is5325(dev) || is5365(dev)) {
633 for (i = 1; i < dev->num_vlans; i++)
634 b53_set_vlan_entry(dev, i, &vl);
635 } else {
636 b53_do_vlan_op(dev, VTA_CMD_CLEAR);
637 }
638
639 b53_enable_vlan(dev, false);
640
641 b53_for_each_port(dev, i)
642 b53_write16(dev, B53_VLAN_PAGE,
643 B53_VLAN_PORT_DEF_TAG(i), 1);
644
645 if (!is5325(dev) && !is5365(dev))
646 b53_set_jumbo(dev, dev->enable_jumbo, false);
647
648 return 0;
649}
650EXPORT_SYMBOL(b53_configure_vlan);
651
652static void b53_switch_reset_gpio(struct b53_device *dev)
653{
654 int gpio = dev->reset_gpio;
655
656 if (gpio < 0)
657 return;
658
659 /* Reset sequence: RESET low(50ms)->high(20ms)
660 */
661 gpio_set_value(gpio, 0);
662 mdelay(50);
663
664 gpio_set_value(gpio, 1);
665 mdelay(20);
666
667 dev->current_page = 0xff;
668}
669
670static int b53_switch_reset(struct b53_device *dev)
671{
672 unsigned int timeout = 1000;
673 u8 mgmt, reg;
674
675 b53_switch_reset_gpio(dev);
676
677 if (is539x(dev)) {
678 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
679 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
680 }
681
682 /* This is specific to 58xx devices here, do not use is58xx() which
683 * covers the larger Starfigther 2 family, including 7445/7278 which
684 * still use this driver as a library and need to perform the reset
685 * earlier.
686 */
687 if (dev->chip_id == BCM58XX_DEVICE_ID) {
688 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
689 reg |= SW_RST | EN_SW_RST | EN_CH_RST;
690 b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
691
692 do {
693 b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, ®);
694 if (!(reg & SW_RST))
695 break;
696
697 usleep_range(1000, 2000);
698 } while (timeout-- > 0);
699
700 if (timeout == 0)
701 return -ETIMEDOUT;
702 }
703
704 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
705
706 if (!(mgmt & SM_SW_FWD_EN)) {
707 mgmt &= ~SM_SW_FWD_MODE;
708 mgmt |= SM_SW_FWD_EN;
709
710 b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
711 b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
712
713 if (!(mgmt & SM_SW_FWD_EN)) {
714 dev_err(dev->dev, "Failed to enable switch!\n");
715 return -EINVAL;
716 }
717 }
718
719 b53_enable_mib(dev);
720
721 return b53_flush_arl(dev, FAST_AGE_STATIC);
722}
723
724static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
725{
726 struct b53_device *priv = ds->priv;
727 u16 value = 0;
728 int ret;
729
730 if (priv->ops->phy_read16)
731 ret = priv->ops->phy_read16(priv, addr, reg, &value);
732 else
733 ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
734 reg * 2, &value);
735
736 return ret ? ret : value;
737}
738
739static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
740{
741 struct b53_device *priv = ds->priv;
742
743 if (priv->ops->phy_write16)
744 return priv->ops->phy_write16(priv, addr, reg, val);
745
746 return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
747}
748
749static int b53_reset_switch(struct b53_device *priv)
750{
751 /* reset vlans */
752 priv->enable_jumbo = false;
753
754 memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
755 memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
756
757 return b53_switch_reset(priv);
758}
759
760static int b53_apply_config(struct b53_device *priv)
761{
762 /* disable switching */
763 b53_set_forwarding(priv, 0);
764
765 b53_configure_vlan(priv->ds);
766
767 /* enable switching */
768 b53_set_forwarding(priv, 1);
769
770 return 0;
771}
772
773static void b53_reset_mib(struct b53_device *priv)
774{
775 u8 gc;
776
777 b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
778
779 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
780 msleep(1);
781 b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
782 msleep(1);
783}
784
785static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
786{
787 if (is5365(dev))
788 return b53_mibs_65;
789 else if (is63xx(dev))
790 return b53_mibs_63xx;
791 else if (is58xx(dev))
792 return b53_mibs_58xx;
793 else
794 return b53_mibs;
795}
796
797static unsigned int b53_get_mib_size(struct b53_device *dev)
798{
799 if (is5365(dev))
800 return B53_MIBS_65_SIZE;
801 else if (is63xx(dev))
802 return B53_MIBS_63XX_SIZE;
803 else if (is58xx(dev))
804 return B53_MIBS_58XX_SIZE;
805 else
806 return B53_MIBS_SIZE;
807}
808
809void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
810{
811 struct b53_device *dev = ds->priv;
812 const struct b53_mib_desc *mibs = b53_get_mib(dev);
813 unsigned int mib_size = b53_get_mib_size(dev);
814 unsigned int i;
815
816 for (i = 0; i < mib_size; i++)
817 strlcpy(data + i * ETH_GSTRING_LEN,
818 mibs[i].name, ETH_GSTRING_LEN);
819}
820EXPORT_SYMBOL(b53_get_strings);
821
822void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
823{
824 struct b53_device *dev = ds->priv;
825 const struct b53_mib_desc *mibs = b53_get_mib(dev);
826 unsigned int mib_size = b53_get_mib_size(dev);
827 const struct b53_mib_desc *s;
828 unsigned int i;
829 u64 val = 0;
830
831 if (is5365(dev) && port == 5)
832 port = 8;
833
834 mutex_lock(&dev->stats_mutex);
835
836 for (i = 0; i < mib_size; i++) {
837 s = &mibs[i];
838
839 if (s->size == 8) {
840 b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
841 } else {
842 u32 val32;
843
844 b53_read32(dev, B53_MIB_PAGE(port), s->offset,
845 &val32);
846 val = val32;
847 }
848 data[i] = (u64)val;
849 }
850
851 mutex_unlock(&dev->stats_mutex);
852}
853EXPORT_SYMBOL(b53_get_ethtool_stats);
854
855int b53_get_sset_count(struct dsa_switch *ds, int port)
856{
857 struct b53_device *dev = ds->priv;
858
859 return b53_get_mib_size(dev);
860}
861EXPORT_SYMBOL(b53_get_sset_count);
862
863static int b53_setup(struct dsa_switch *ds)
864{
865 struct b53_device *dev = ds->priv;
866 unsigned int port;
867 int ret;
868
869 ret = b53_reset_switch(dev);
870 if (ret) {
871 dev_err(ds->dev, "failed to reset switch\n");
872 return ret;
873 }
874
875 b53_reset_mib(dev);
876
877 ret = b53_apply_config(dev);
878 if (ret)
879 dev_err(ds->dev, "failed to apply configuration\n");
880
881 /* Configure IMP/CPU port, disable unused ports. Enabled
882 * ports will be configured with .port_enable
883 */
884 for (port = 0; port < dev->num_ports; port++) {
885 if (dsa_is_cpu_port(ds, port))
886 b53_enable_cpu_port(dev, port);
887 else if (dsa_is_unused_port(ds, port))
888 b53_disable_port(ds, port, NULL);
889 }
890
891 return ret;
892}
893
894static void b53_adjust_link(struct dsa_switch *ds, int port,
895 struct phy_device *phydev)
896{
897 struct b53_device *dev = ds->priv;
898 struct ethtool_eee *p = &dev->ports[port].eee;
899 u8 rgmii_ctrl = 0, reg = 0, off;
900
901 if (!phy_is_pseudo_fixed_link(phydev))
902 return;
903
904 /* Override the port settings */
905 if (port == dev->cpu_port) {
906 off = B53_PORT_OVERRIDE_CTRL;
907 reg = PORT_OVERRIDE_EN;
908 } else {
909 off = B53_GMII_PORT_OVERRIDE_CTRL(port);
910 reg = GMII_PO_EN;
911 }
912
913 /* Set the link UP */
914 if (phydev->link)
915 reg |= PORT_OVERRIDE_LINK;
916
917 if (phydev->duplex == DUPLEX_FULL)
918 reg |= PORT_OVERRIDE_FULL_DUPLEX;
919
920 switch (phydev->speed) {
921 case 2000:
922 reg |= PORT_OVERRIDE_SPEED_2000M;
923 /* fallthrough */
924 case SPEED_1000:
925 reg |= PORT_OVERRIDE_SPEED_1000M;
926 break;
927 case SPEED_100:
928 reg |= PORT_OVERRIDE_SPEED_100M;
929 break;
930 case SPEED_10:
931 reg |= PORT_OVERRIDE_SPEED_10M;
932 break;
933 default:
934 dev_err(ds->dev, "unknown speed: %d\n", phydev->speed);
935 return;
936 }
937
938 /* Enable flow control on BCM5301x's CPU port */
939 if (is5301x(dev) && port == dev->cpu_port)
940 reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW;
941
942 if (phydev->pause) {
943 if (phydev->asym_pause)
944 reg |= PORT_OVERRIDE_TX_FLOW;
945 reg |= PORT_OVERRIDE_RX_FLOW;
946 }
947
948 b53_write8(dev, B53_CTRL_PAGE, off, reg);
949
950 if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
951 if (port == 8)
952 off = B53_RGMII_CTRL_IMP;
953 else
954 off = B53_RGMII_CTRL_P(port);
955
956 /* Configure the port RGMII clock delay by DLL disabled and
957 * tx_clk aligned timing (restoring to reset defaults)
958 */
959 b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
960 rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
961 RGMII_CTRL_TIMING_SEL);
962
963 /* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
964 * sure that we enable the port TX clock internal delay to
965 * account for this internal delay that is inserted, otherwise
966 * the switch won't be able to receive correctly.
967 *
968 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
969 * any delay neither on transmission nor reception, so the
970 * BCM53125 must also be configured accordingly to account for
971 * the lack of delay and introduce
972 *
973 * The BCM53125 switch has its RX clock and TX clock control
974 * swapped, hence the reason why we modify the TX clock path in
975 * the "RGMII" case
976 */
977 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
978 rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
979 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
980 rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
981 rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
982 b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
983
984 dev_info(ds->dev, "Configured port %d for %s\n", port,
985 phy_modes(phydev->interface));
986 }
987
988 /* configure MII port if necessary */
989 if (is5325(dev)) {
990 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
991 ®);
992
993 /* reverse mii needs to be enabled */
994 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
995 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
996 reg | PORT_OVERRIDE_RV_MII_25);
997 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
998 ®);
999
1000 if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1001 dev_err(ds->dev,
1002 "Failed to enable reverse MII mode\n");
1003 return;
1004 }
1005 }
1006 } else if (is5301x(dev)) {
1007 if (port != dev->cpu_port) {
1008 u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port);
1009 u8 gmii_po;
1010
1011 b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
1012 gmii_po |= GMII_PO_LINK |
1013 GMII_PO_RX_FLOW |
1014 GMII_PO_TX_FLOW |
1015 GMII_PO_EN |
1016 GMII_PO_SPEED_2000M;
1017 b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
1018 }
1019 }
1020
1021 /* Re-negotiate EEE if it was enabled already */
1022 p->eee_enabled = b53_eee_init(ds, port, phydev);
1023}
1024
1025int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering)
1026{
1027 return 0;
1028}
1029EXPORT_SYMBOL(b53_vlan_filtering);
1030
1031int b53_vlan_prepare(struct dsa_switch *ds, int port,
1032 const struct switchdev_obj_port_vlan *vlan)
1033{
1034 struct b53_device *dev = ds->priv;
1035
1036 if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
1037 return -EOPNOTSUPP;
1038
1039 if (vlan->vid_end > dev->num_vlans)
1040 return -ERANGE;
1041
1042 b53_enable_vlan(dev, true);
1043
1044 return 0;
1045}
1046EXPORT_SYMBOL(b53_vlan_prepare);
1047
1048void b53_vlan_add(struct dsa_switch *ds, int port,
1049 const struct switchdev_obj_port_vlan *vlan)
1050{
1051 struct b53_device *dev = ds->priv;
1052 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1053 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1054 struct b53_vlan *vl;
1055 u16 vid;
1056
1057 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1058 vl = &dev->vlans[vid];
1059
1060 b53_get_vlan_entry(dev, vid, vl);
1061
1062 vl->members |= BIT(port);
1063 if (untagged)
1064 vl->untag |= BIT(port);
1065 else
1066 vl->untag &= ~BIT(port);
1067
1068 b53_set_vlan_entry(dev, vid, vl);
1069 b53_fast_age_vlan(dev, vid);
1070 }
1071
1072 if (pvid) {
1073 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1074 vlan->vid_end);
1075 b53_fast_age_vlan(dev, vid);
1076 }
1077}
1078EXPORT_SYMBOL(b53_vlan_add);
1079
1080int b53_vlan_del(struct dsa_switch *ds, int port,
1081 const struct switchdev_obj_port_vlan *vlan)
1082{
1083 struct b53_device *dev = ds->priv;
1084 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1085 struct b53_vlan *vl;
1086 u16 vid;
1087 u16 pvid;
1088
1089 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1090
1091 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1092 vl = &dev->vlans[vid];
1093
1094 b53_get_vlan_entry(dev, vid, vl);
1095
1096 vl->members &= ~BIT(port);
1097
1098 if (pvid == vid) {
1099 if (is5325(dev) || is5365(dev))
1100 pvid = 1;
1101 else
1102 pvid = 0;
1103 }
1104
1105 if (untagged)
1106 vl->untag &= ~(BIT(port));
1107
1108 b53_set_vlan_entry(dev, vid, vl);
1109 b53_fast_age_vlan(dev, vid);
1110 }
1111
1112 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1113 b53_fast_age_vlan(dev, pvid);
1114
1115 return 0;
1116}
1117EXPORT_SYMBOL(b53_vlan_del);
1118
1119/* Address Resolution Logic routines */
1120static int b53_arl_op_wait(struct b53_device *dev)
1121{
1122 unsigned int timeout = 10;
1123 u8 reg;
1124
1125 do {
1126 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1127 if (!(reg & ARLTBL_START_DONE))
1128 return 0;
1129
1130 usleep_range(1000, 2000);
1131 } while (timeout--);
1132
1133 dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1134
1135 return -ETIMEDOUT;
1136}
1137
1138static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1139{
1140 u8 reg;
1141
1142 if (op > ARLTBL_RW)
1143 return -EINVAL;
1144
1145 b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, ®);
1146 reg |= ARLTBL_START_DONE;
1147 if (op)
1148 reg |= ARLTBL_RW;
1149 else
1150 reg &= ~ARLTBL_RW;
1151 b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1152
1153 return b53_arl_op_wait(dev);
1154}
1155
1156static int b53_arl_read(struct b53_device *dev, u64 mac,
1157 u16 vid, struct b53_arl_entry *ent, u8 *idx,
1158 bool is_valid)
1159{
1160 unsigned int i;
1161 int ret;
1162
1163 ret = b53_arl_op_wait(dev);
1164 if (ret)
1165 return ret;
1166
1167 /* Read the bins */
1168 for (i = 0; i < dev->num_arl_entries; i++) {
1169 u64 mac_vid;
1170 u32 fwd_entry;
1171
1172 b53_read64(dev, B53_ARLIO_PAGE,
1173 B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1174 b53_read32(dev, B53_ARLIO_PAGE,
1175 B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1176 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1177
1178 if (!(fwd_entry & ARLTBL_VALID))
1179 continue;
1180 if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1181 continue;
1182 *idx = i;
1183 }
1184
1185 return -ENOENT;
1186}
1187
1188static int b53_arl_op(struct b53_device *dev, int op, int port,
1189 const unsigned char *addr, u16 vid, bool is_valid)
1190{
1191 struct b53_arl_entry ent;
1192 u32 fwd_entry;
1193 u64 mac, mac_vid = 0;
1194 u8 idx = 0;
1195 int ret;
1196
1197 /* Convert the array into a 64-bit MAC */
1198 mac = ether_addr_to_u64(addr);
1199
1200 /* Perform a read for the given MAC and VID */
1201 b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1202 b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1203
1204 /* Issue a read operation for this MAC */
1205 ret = b53_arl_rw_op(dev, 1);
1206 if (ret)
1207 return ret;
1208
1209 ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
1210 /* If this is a read, just finish now */
1211 if (op)
1212 return ret;
1213
1214 /* We could not find a matching MAC, so reset to a new entry */
1215 if (ret) {
1216 fwd_entry = 0;
1217 idx = 1;
1218 }
1219
1220 memset(&ent, 0, sizeof(ent));
1221 ent.port = port;
1222 ent.is_valid = is_valid;
1223 ent.vid = vid;
1224 ent.is_static = true;
1225 memcpy(ent.mac, addr, ETH_ALEN);
1226 b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1227
1228 b53_write64(dev, B53_ARLIO_PAGE,
1229 B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1230 b53_write32(dev, B53_ARLIO_PAGE,
1231 B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1232
1233 return b53_arl_rw_op(dev, 0);
1234}
1235
1236int b53_fdb_add(struct dsa_switch *ds, int port,
1237 const unsigned char *addr, u16 vid)
1238{
1239 struct b53_device *priv = ds->priv;
1240
1241 /* 5325 and 5365 require some more massaging, but could
1242 * be supported eventually
1243 */
1244 if (is5325(priv) || is5365(priv))
1245 return -EOPNOTSUPP;
1246
1247 return b53_arl_op(priv, 0, port, addr, vid, true);
1248}
1249EXPORT_SYMBOL(b53_fdb_add);
1250
1251int b53_fdb_del(struct dsa_switch *ds, int port,
1252 const unsigned char *addr, u16 vid)
1253{
1254 struct b53_device *priv = ds->priv;
1255
1256 return b53_arl_op(priv, 0, port, addr, vid, false);
1257}
1258EXPORT_SYMBOL(b53_fdb_del);
1259
1260static int b53_arl_search_wait(struct b53_device *dev)
1261{
1262 unsigned int timeout = 1000;
1263 u8 reg;
1264
1265 do {
1266 b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, ®);
1267 if (!(reg & ARL_SRCH_STDN))
1268 return 0;
1269
1270 if (reg & ARL_SRCH_VLID)
1271 return 0;
1272
1273 usleep_range(1000, 2000);
1274 } while (timeout--);
1275
1276 return -ETIMEDOUT;
1277}
1278
1279static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1280 struct b53_arl_entry *ent)
1281{
1282 u64 mac_vid;
1283 u32 fwd_entry;
1284
1285 b53_read64(dev, B53_ARLIO_PAGE,
1286 B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1287 b53_read32(dev, B53_ARLIO_PAGE,
1288 B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1289 b53_arl_to_entry(ent, mac_vid, fwd_entry);
1290}
1291
1292static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
1293 dsa_fdb_dump_cb_t *cb, void *data)
1294{
1295 if (!ent->is_valid)
1296 return 0;
1297
1298 if (port != ent->port)
1299 return 0;
1300
1301 return cb(ent->mac, ent->vid, ent->is_static, data);
1302}
1303
1304int b53_fdb_dump(struct dsa_switch *ds, int port,
1305 dsa_fdb_dump_cb_t *cb, void *data)
1306{
1307 struct b53_device *priv = ds->priv;
1308 struct b53_arl_entry results[2];
1309 unsigned int count = 0;
1310 int ret;
1311 u8 reg;
1312
1313 /* Start search operation */
1314 reg = ARL_SRCH_STDN;
1315 b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1316
1317 do {
1318 ret = b53_arl_search_wait(priv);
1319 if (ret)
1320 return ret;
1321
1322 b53_arl_search_rd(priv, 0, &results[0]);
1323 ret = b53_fdb_copy(port, &results[0], cb, data);
1324 if (ret)
1325 return ret;
1326
1327 if (priv->num_arl_entries > 2) {
1328 b53_arl_search_rd(priv, 1, &results[1]);
1329 ret = b53_fdb_copy(port, &results[1], cb, data);
1330 if (ret)
1331 return ret;
1332
1333 if (!results[0].is_valid && !results[1].is_valid)
1334 break;
1335 }
1336
1337 } while (count++ < 1024);
1338
1339 return 0;
1340}
1341EXPORT_SYMBOL(b53_fdb_dump);
1342
1343int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br)
1344{
1345 struct b53_device *dev = ds->priv;
1346 s8 cpu_port = ds->ports[port].cpu_dp->index;
1347 u16 pvlan, reg;
1348 unsigned int i;
1349
1350 /* Make this port leave the all VLANs join since we will have proper
1351 * VLAN entries from now on
1352 */
1353 if (is58xx(dev)) {
1354 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1355 reg &= ~BIT(port);
1356 if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1357 reg &= ~BIT(cpu_port);
1358 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1359 }
1360
1361 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1362
1363 b53_for_each_port(dev, i) {
1364 if (dsa_to_port(ds, i)->bridge_dev != br)
1365 continue;
1366
1367 /* Add this local port to the remote port VLAN control
1368 * membership and update the remote port bitmask
1369 */
1370 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1371 reg |= BIT(port);
1372 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1373 dev->ports[i].vlan_ctl_mask = reg;
1374
1375 pvlan |= BIT(i);
1376 }
1377
1378 /* Configure the local port VLAN control membership to include
1379 * remote ports and update the local port bitmask
1380 */
1381 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1382 dev->ports[port].vlan_ctl_mask = pvlan;
1383
1384 return 0;
1385}
1386EXPORT_SYMBOL(b53_br_join);
1387
1388void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br)
1389{
1390 struct b53_device *dev = ds->priv;
1391 struct b53_vlan *vl = &dev->vlans[0];
1392 s8 cpu_port = ds->ports[port].cpu_dp->index;
1393 unsigned int i;
1394 u16 pvlan, reg, pvid;
1395
1396 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1397
1398 b53_for_each_port(dev, i) {
1399 /* Don't touch the remaining ports */
1400 if (dsa_to_port(ds, i)->bridge_dev != br)
1401 continue;
1402
1403 b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), ®);
1404 reg &= ~BIT(port);
1405 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1406 dev->ports[port].vlan_ctl_mask = reg;
1407
1408 /* Prevent self removal to preserve isolation */
1409 if (port != i)
1410 pvlan &= ~BIT(i);
1411 }
1412
1413 b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1414 dev->ports[port].vlan_ctl_mask = pvlan;
1415
1416 if (is5325(dev) || is5365(dev))
1417 pvid = 1;
1418 else
1419 pvid = 0;
1420
1421 /* Make this port join all VLANs without VLAN entries */
1422 if (is58xx(dev)) {
1423 b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, ®);
1424 reg |= BIT(port);
1425 if (!(reg & BIT(cpu_port)))
1426 reg |= BIT(cpu_port);
1427 b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1428 } else {
1429 b53_get_vlan_entry(dev, pvid, vl);
1430 vl->members |= BIT(port) | BIT(cpu_port);
1431 vl->untag |= BIT(port) | BIT(cpu_port);
1432 b53_set_vlan_entry(dev, pvid, vl);
1433 }
1434}
1435EXPORT_SYMBOL(b53_br_leave);
1436
1437void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
1438{
1439 struct b53_device *dev = ds->priv;
1440 u8 hw_state;
1441 u8 reg;
1442
1443 switch (state) {
1444 case BR_STATE_DISABLED:
1445 hw_state = PORT_CTRL_DIS_STATE;
1446 break;
1447 case BR_STATE_LISTENING:
1448 hw_state = PORT_CTRL_LISTEN_STATE;
1449 break;
1450 case BR_STATE_LEARNING:
1451 hw_state = PORT_CTRL_LEARN_STATE;
1452 break;
1453 case BR_STATE_FORWARDING:
1454 hw_state = PORT_CTRL_FWD_STATE;
1455 break;
1456 case BR_STATE_BLOCKING:
1457 hw_state = PORT_CTRL_BLOCK_STATE;
1458 break;
1459 default:
1460 dev_err(ds->dev, "invalid STP state: %d\n", state);
1461 return;
1462 }
1463
1464 b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), ®);
1465 reg &= ~PORT_CTRL_STP_STATE_MASK;
1466 reg |= hw_state;
1467 b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1468}
1469EXPORT_SYMBOL(b53_br_set_stp_state);
1470
1471void b53_br_fast_age(struct dsa_switch *ds, int port)
1472{
1473 struct b53_device *dev = ds->priv;
1474
1475 if (b53_fast_age_port(dev, port))
1476 dev_err(ds->dev, "fast ageing failed\n");
1477}
1478EXPORT_SYMBOL(b53_br_fast_age);
1479
1480static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port)
1481{
1482 /* Broadcom switches will accept enabling Broadcom tags on the
1483 * following ports: 5, 7 and 8, any other port is not supported
1484 */
1485 switch (port) {
1486 case B53_CPU_PORT_25:
1487 case 7:
1488 case B53_CPU_PORT:
1489 return true;
1490 }
1491
1492 dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", port);
1493 return false;
1494}
1495
1496enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port)
1497{
1498 struct b53_device *dev = ds->priv;
1499
1500 /* Older models (5325, 5365) support a different tag format that we do
1501 * not support in net/dsa/tag_brcm.c yet. 539x and 531x5 require managed
1502 * mode to be turned on which means we need to specifically manage ARL
1503 * misses on multicast addresses (TBD).
1504 */
1505 if (is5325(dev) || is5365(dev) || is539x(dev) || is531x5(dev) ||
1506 !b53_can_enable_brcm_tags(ds, port))
1507 return DSA_TAG_PROTO_NONE;
1508
1509 /* Broadcom BCM58xx chips have a flow accelerator on Port 8
1510 * which requires us to use the prepended Broadcom tag type
1511 */
1512 if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT)
1513 return DSA_TAG_PROTO_BRCM_PREPEND;
1514
1515 return DSA_TAG_PROTO_BRCM;
1516}
1517EXPORT_SYMBOL(b53_get_tag_protocol);
1518
1519int b53_mirror_add(struct dsa_switch *ds, int port,
1520 struct dsa_mall_mirror_tc_entry *mirror, bool ingress)
1521{
1522 struct b53_device *dev = ds->priv;
1523 u16 reg, loc;
1524
1525 if (ingress)
1526 loc = B53_IG_MIR_CTL;
1527 else
1528 loc = B53_EG_MIR_CTL;
1529
1530 b53_read16(dev, B53_MGMT_PAGE, loc, ®);
1531 reg &= ~MIRROR_MASK;
1532 reg |= BIT(port);
1533 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1534
1535 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®);
1536 reg &= ~CAP_PORT_MASK;
1537 reg |= mirror->to_local_port;
1538 reg |= MIRROR_EN;
1539 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1540
1541 return 0;
1542}
1543EXPORT_SYMBOL(b53_mirror_add);
1544
1545void b53_mirror_del(struct dsa_switch *ds, int port,
1546 struct dsa_mall_mirror_tc_entry *mirror)
1547{
1548 struct b53_device *dev = ds->priv;
1549 bool loc_disable = false, other_loc_disable = false;
1550 u16 reg, loc;
1551
1552 if (mirror->ingress)
1553 loc = B53_IG_MIR_CTL;
1554 else
1555 loc = B53_EG_MIR_CTL;
1556
1557 /* Update the desired ingress/egress register */
1558 b53_read16(dev, B53_MGMT_PAGE, loc, ®);
1559 reg &= ~BIT(port);
1560 if (!(reg & MIRROR_MASK))
1561 loc_disable = true;
1562 b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1563
1564 /* Now look at the other one to know if we can disable mirroring
1565 * entirely
1566 */
1567 if (mirror->ingress)
1568 b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, ®);
1569 else
1570 b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, ®);
1571 if (!(reg & MIRROR_MASK))
1572 other_loc_disable = true;
1573
1574 b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, ®);
1575 /* Both no longer have ports, let's disable mirroring */
1576 if (loc_disable && other_loc_disable) {
1577 reg &= ~MIRROR_EN;
1578 reg &= ~mirror->to_local_port;
1579 }
1580 b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1581}
1582EXPORT_SYMBOL(b53_mirror_del);
1583
1584void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
1585{
1586 struct b53_device *dev = ds->priv;
1587 u16 reg;
1588
1589 b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, ®);
1590 if (enable)
1591 reg |= BIT(port);
1592 else
1593 reg &= ~BIT(port);
1594 b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
1595}
1596EXPORT_SYMBOL(b53_eee_enable_set);
1597
1598
1599/* Returns 0 if EEE was not enabled, or 1 otherwise
1600 */
1601int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
1602{
1603 int ret;
1604
1605 ret = phy_init_eee(phy, 0);
1606 if (ret)
1607 return 0;
1608
1609 b53_eee_enable_set(ds, port, true);
1610
1611 return 1;
1612}
1613EXPORT_SYMBOL(b53_eee_init);
1614
1615int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1616{
1617 struct b53_device *dev = ds->priv;
1618 struct ethtool_eee *p = &dev->ports[port].eee;
1619 u16 reg;
1620
1621 if (is5325(dev) || is5365(dev))
1622 return -EOPNOTSUPP;
1623
1624 b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, ®);
1625 e->eee_enabled = p->eee_enabled;
1626 e->eee_active = !!(reg & BIT(port));
1627
1628 return 0;
1629}
1630EXPORT_SYMBOL(b53_get_mac_eee);
1631
1632int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1633{
1634 struct b53_device *dev = ds->priv;
1635 struct ethtool_eee *p = &dev->ports[port].eee;
1636
1637 if (is5325(dev) || is5365(dev))
1638 return -EOPNOTSUPP;
1639
1640 p->eee_enabled = e->eee_enabled;
1641 b53_eee_enable_set(ds, port, e->eee_enabled);
1642
1643 return 0;
1644}
1645EXPORT_SYMBOL(b53_set_mac_eee);
1646
1647static const struct dsa_switch_ops b53_switch_ops = {
1648 .get_tag_protocol = b53_get_tag_protocol,
1649 .setup = b53_setup,
1650 .get_strings = b53_get_strings,
1651 .get_ethtool_stats = b53_get_ethtool_stats,
1652 .get_sset_count = b53_get_sset_count,
1653 .phy_read = b53_phy_read16,
1654 .phy_write = b53_phy_write16,
1655 .adjust_link = b53_adjust_link,
1656 .port_enable = b53_enable_port,
1657 .port_disable = b53_disable_port,
1658 .get_mac_eee = b53_get_mac_eee,
1659 .set_mac_eee = b53_set_mac_eee,
1660 .port_bridge_join = b53_br_join,
1661 .port_bridge_leave = b53_br_leave,
1662 .port_stp_state_set = b53_br_set_stp_state,
1663 .port_fast_age = b53_br_fast_age,
1664 .port_vlan_filtering = b53_vlan_filtering,
1665 .port_vlan_prepare = b53_vlan_prepare,
1666 .port_vlan_add = b53_vlan_add,
1667 .port_vlan_del = b53_vlan_del,
1668 .port_fdb_dump = b53_fdb_dump,
1669 .port_fdb_add = b53_fdb_add,
1670 .port_fdb_del = b53_fdb_del,
1671 .port_mirror_add = b53_mirror_add,
1672 .port_mirror_del = b53_mirror_del,
1673};
1674
1675struct b53_chip_data {
1676 u32 chip_id;
1677 const char *dev_name;
1678 u16 vlans;
1679 u16 enabled_ports;
1680 u8 cpu_port;
1681 u8 vta_regs[3];
1682 u8 arl_entries;
1683 u8 duplex_reg;
1684 u8 jumbo_pm_reg;
1685 u8 jumbo_size_reg;
1686};
1687
1688#define B53_VTA_REGS \
1689 { B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1690#define B53_VTA_REGS_9798 \
1691 { B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1692#define B53_VTA_REGS_63XX \
1693 { B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1694
1695static const struct b53_chip_data b53_switch_chips[] = {
1696 {
1697 .chip_id = BCM5325_DEVICE_ID,
1698 .dev_name = "BCM5325",
1699 .vlans = 16,
1700 .enabled_ports = 0x1f,
1701 .arl_entries = 2,
1702 .cpu_port = B53_CPU_PORT_25,
1703 .duplex_reg = B53_DUPLEX_STAT_FE,
1704 },
1705 {
1706 .chip_id = BCM5365_DEVICE_ID,
1707 .dev_name = "BCM5365",
1708 .vlans = 256,
1709 .enabled_ports = 0x1f,
1710 .arl_entries = 2,
1711 .cpu_port = B53_CPU_PORT_25,
1712 .duplex_reg = B53_DUPLEX_STAT_FE,
1713 },
1714 {
1715 .chip_id = BCM5389_DEVICE_ID,
1716 .dev_name = "BCM5389",
1717 .vlans = 4096,
1718 .enabled_ports = 0x1f,
1719 .arl_entries = 4,
1720 .cpu_port = B53_CPU_PORT,
1721 .vta_regs = B53_VTA_REGS,
1722 .duplex_reg = B53_DUPLEX_STAT_GE,
1723 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1724 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1725 },
1726 {
1727 .chip_id = BCM5395_DEVICE_ID,
1728 .dev_name = "BCM5395",
1729 .vlans = 4096,
1730 .enabled_ports = 0x1f,
1731 .arl_entries = 4,
1732 .cpu_port = B53_CPU_PORT,
1733 .vta_regs = B53_VTA_REGS,
1734 .duplex_reg = B53_DUPLEX_STAT_GE,
1735 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1736 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1737 },
1738 {
1739 .chip_id = BCM5397_DEVICE_ID,
1740 .dev_name = "BCM5397",
1741 .vlans = 4096,
1742 .enabled_ports = 0x1f,
1743 .arl_entries = 4,
1744 .cpu_port = B53_CPU_PORT,
1745 .vta_regs = B53_VTA_REGS_9798,
1746 .duplex_reg = B53_DUPLEX_STAT_GE,
1747 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1748 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1749 },
1750 {
1751 .chip_id = BCM5398_DEVICE_ID,
1752 .dev_name = "BCM5398",
1753 .vlans = 4096,
1754 .enabled_ports = 0x7f,
1755 .arl_entries = 4,
1756 .cpu_port = B53_CPU_PORT,
1757 .vta_regs = B53_VTA_REGS_9798,
1758 .duplex_reg = B53_DUPLEX_STAT_GE,
1759 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1760 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1761 },
1762 {
1763 .chip_id = BCM53115_DEVICE_ID,
1764 .dev_name = "BCM53115",
1765 .vlans = 4096,
1766 .enabled_ports = 0x1f,
1767 .arl_entries = 4,
1768 .vta_regs = B53_VTA_REGS,
1769 .cpu_port = B53_CPU_PORT,
1770 .duplex_reg = B53_DUPLEX_STAT_GE,
1771 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1772 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1773 },
1774 {
1775 .chip_id = BCM53125_DEVICE_ID,
1776 .dev_name = "BCM53125",
1777 .vlans = 4096,
1778 .enabled_ports = 0xff,
1779 .arl_entries = 4,
1780 .cpu_port = B53_CPU_PORT,
1781 .vta_regs = B53_VTA_REGS,
1782 .duplex_reg = B53_DUPLEX_STAT_GE,
1783 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1784 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1785 },
1786 {
1787 .chip_id = BCM53128_DEVICE_ID,
1788 .dev_name = "BCM53128",
1789 .vlans = 4096,
1790 .enabled_ports = 0x1ff,
1791 .arl_entries = 4,
1792 .cpu_port = B53_CPU_PORT,
1793 .vta_regs = B53_VTA_REGS,
1794 .duplex_reg = B53_DUPLEX_STAT_GE,
1795 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1796 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1797 },
1798 {
1799 .chip_id = BCM63XX_DEVICE_ID,
1800 .dev_name = "BCM63xx",
1801 .vlans = 4096,
1802 .enabled_ports = 0, /* pdata must provide them */
1803 .arl_entries = 4,
1804 .cpu_port = B53_CPU_PORT,
1805 .vta_regs = B53_VTA_REGS_63XX,
1806 .duplex_reg = B53_DUPLEX_STAT_63XX,
1807 .jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1808 .jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1809 },
1810 {
1811 .chip_id = BCM53010_DEVICE_ID,
1812 .dev_name = "BCM53010",
1813 .vlans = 4096,
1814 .enabled_ports = 0x1f,
1815 .arl_entries = 4,
1816 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1817 .vta_regs = B53_VTA_REGS,
1818 .duplex_reg = B53_DUPLEX_STAT_GE,
1819 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1820 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1821 },
1822 {
1823 .chip_id = BCM53011_DEVICE_ID,
1824 .dev_name = "BCM53011",
1825 .vlans = 4096,
1826 .enabled_ports = 0x1bf,
1827 .arl_entries = 4,
1828 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1829 .vta_regs = B53_VTA_REGS,
1830 .duplex_reg = B53_DUPLEX_STAT_GE,
1831 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1832 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1833 },
1834 {
1835 .chip_id = BCM53012_DEVICE_ID,
1836 .dev_name = "BCM53012",
1837 .vlans = 4096,
1838 .enabled_ports = 0x1bf,
1839 .arl_entries = 4,
1840 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1841 .vta_regs = B53_VTA_REGS,
1842 .duplex_reg = B53_DUPLEX_STAT_GE,
1843 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1844 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1845 },
1846 {
1847 .chip_id = BCM53018_DEVICE_ID,
1848 .dev_name = "BCM53018",
1849 .vlans = 4096,
1850 .enabled_ports = 0x1f,
1851 .arl_entries = 4,
1852 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1853 .vta_regs = B53_VTA_REGS,
1854 .duplex_reg = B53_DUPLEX_STAT_GE,
1855 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1856 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1857 },
1858 {
1859 .chip_id = BCM53019_DEVICE_ID,
1860 .dev_name = "BCM53019",
1861 .vlans = 4096,
1862 .enabled_ports = 0x1f,
1863 .arl_entries = 4,
1864 .cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1865 .vta_regs = B53_VTA_REGS,
1866 .duplex_reg = B53_DUPLEX_STAT_GE,
1867 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1868 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1869 },
1870 {
1871 .chip_id = BCM58XX_DEVICE_ID,
1872 .dev_name = "BCM585xx/586xx/88312",
1873 .vlans = 4096,
1874 .enabled_ports = 0x1ff,
1875 .arl_entries = 4,
1876 .cpu_port = B53_CPU_PORT,
1877 .vta_regs = B53_VTA_REGS,
1878 .duplex_reg = B53_DUPLEX_STAT_GE,
1879 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1880 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1881 },
1882 {
1883 .chip_id = BCM7445_DEVICE_ID,
1884 .dev_name = "BCM7445",
1885 .vlans = 4096,
1886 .enabled_ports = 0x1ff,
1887 .arl_entries = 4,
1888 .cpu_port = B53_CPU_PORT,
1889 .vta_regs = B53_VTA_REGS,
1890 .duplex_reg = B53_DUPLEX_STAT_GE,
1891 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1892 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1893 },
1894 {
1895 .chip_id = BCM7278_DEVICE_ID,
1896 .dev_name = "BCM7278",
1897 .vlans = 4096,
1898 .enabled_ports = 0x1ff,
1899 .arl_entries= 4,
1900 .cpu_port = B53_CPU_PORT,
1901 .vta_regs = B53_VTA_REGS,
1902 .duplex_reg = B53_DUPLEX_STAT_GE,
1903 .jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1904 .jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1905 },
1906};
1907
1908static int b53_switch_init(struct b53_device *dev)
1909{
1910 unsigned int i;
1911 int ret;
1912
1913 for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1914 const struct b53_chip_data *chip = &b53_switch_chips[i];
1915
1916 if (chip->chip_id == dev->chip_id) {
1917 if (!dev->enabled_ports)
1918 dev->enabled_ports = chip->enabled_ports;
1919 dev->name = chip->dev_name;
1920 dev->duplex_reg = chip->duplex_reg;
1921 dev->vta_regs[0] = chip->vta_regs[0];
1922 dev->vta_regs[1] = chip->vta_regs[1];
1923 dev->vta_regs[2] = chip->vta_regs[2];
1924 dev->jumbo_pm_reg = chip->jumbo_pm_reg;
1925 dev->cpu_port = chip->cpu_port;
1926 dev->num_vlans = chip->vlans;
1927 dev->num_arl_entries = chip->arl_entries;
1928 break;
1929 }
1930 }
1931
1932 /* check which BCM5325x version we have */
1933 if (is5325(dev)) {
1934 u8 vc4;
1935
1936 b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1937
1938 /* check reserved bits */
1939 switch (vc4 & 3) {
1940 case 1:
1941 /* BCM5325E */
1942 break;
1943 case 3:
1944 /* BCM5325F - do not use port 4 */
1945 dev->enabled_ports &= ~BIT(4);
1946 break;
1947 default:
1948/* On the BCM47XX SoCs this is the supported internal switch.*/
1949#ifndef CONFIG_BCM47XX
1950 /* BCM5325M */
1951 return -EINVAL;
1952#else
1953 break;
1954#endif
1955 }
1956 } else if (dev->chip_id == BCM53115_DEVICE_ID) {
1957 u64 strap_value;
1958
1959 b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1960 /* use second IMP port if GMII is enabled */
1961 if (strap_value & SV_GMII_CTRL_115)
1962 dev->cpu_port = 5;
1963 }
1964
1965 /* cpu port is always last */
1966 dev->num_ports = dev->cpu_port + 1;
1967 dev->enabled_ports |= BIT(dev->cpu_port);
1968
1969 dev->ports = devm_kzalloc(dev->dev,
1970 sizeof(struct b53_port) * dev->num_ports,
1971 GFP_KERNEL);
1972 if (!dev->ports)
1973 return -ENOMEM;
1974
1975 dev->vlans = devm_kzalloc(dev->dev,
1976 sizeof(struct b53_vlan) * dev->num_vlans,
1977 GFP_KERNEL);
1978 if (!dev->vlans)
1979 return -ENOMEM;
1980
1981 dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1982 if (dev->reset_gpio >= 0) {
1983 ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1984 GPIOF_OUT_INIT_HIGH, "robo_reset");
1985 if (ret)
1986 return ret;
1987 }
1988
1989 return 0;
1990}
1991
1992struct b53_device *b53_switch_alloc(struct device *base,
1993 const struct b53_io_ops *ops,
1994 void *priv)
1995{
1996 struct dsa_switch *ds;
1997 struct b53_device *dev;
1998
1999 ds = dsa_switch_alloc(base, DSA_MAX_PORTS);
2000 if (!ds)
2001 return NULL;
2002
2003 dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
2004 if (!dev)
2005 return NULL;
2006
2007 ds->priv = dev;
2008 dev->dev = base;
2009
2010 dev->ds = ds;
2011 dev->priv = priv;
2012 dev->ops = ops;
2013 ds->ops = &b53_switch_ops;
2014 mutex_init(&dev->reg_mutex);
2015 mutex_init(&dev->stats_mutex);
2016
2017 return dev;
2018}
2019EXPORT_SYMBOL(b53_switch_alloc);
2020
2021int b53_switch_detect(struct b53_device *dev)
2022{
2023 u32 id32;
2024 u16 tmp;
2025 u8 id8;
2026 int ret;
2027
2028 ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
2029 if (ret)
2030 return ret;
2031
2032 switch (id8) {
2033 case 0:
2034 /* BCM5325 and BCM5365 do not have this register so reads
2035 * return 0. But the read operation did succeed, so assume this
2036 * is one of them.
2037 *
2038 * Next check if we can write to the 5325's VTA register; for
2039 * 5365 it is read only.
2040 */
2041 b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
2042 b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2043
2044 if (tmp == 0xf)
2045 dev->chip_id = BCM5325_DEVICE_ID;
2046 else
2047 dev->chip_id = BCM5365_DEVICE_ID;
2048 break;
2049 case BCM5389_DEVICE_ID:
2050 case BCM5395_DEVICE_ID:
2051 case BCM5397_DEVICE_ID:
2052 case BCM5398_DEVICE_ID:
2053 dev->chip_id = id8;
2054 break;
2055 default:
2056 ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2057 if (ret)
2058 return ret;
2059
2060 switch (id32) {
2061 case BCM53115_DEVICE_ID:
2062 case BCM53125_DEVICE_ID:
2063 case BCM53128_DEVICE_ID:
2064 case BCM53010_DEVICE_ID:
2065 case BCM53011_DEVICE_ID:
2066 case BCM53012_DEVICE_ID:
2067 case BCM53018_DEVICE_ID:
2068 case BCM53019_DEVICE_ID:
2069 dev->chip_id = id32;
2070 break;
2071 default:
2072 pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
2073 id8, id32);
2074 return -ENODEV;
2075 }
2076 }
2077
2078 if (dev->chip_id == BCM5325_DEVICE_ID)
2079 return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2080 &dev->core_rev);
2081 else
2082 return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2083 &dev->core_rev);
2084}
2085EXPORT_SYMBOL(b53_switch_detect);
2086
2087int b53_switch_register(struct b53_device *dev)
2088{
2089 int ret;
2090
2091 if (dev->pdata) {
2092 dev->chip_id = dev->pdata->chip_id;
2093 dev->enabled_ports = dev->pdata->enabled_ports;
2094 }
2095
2096 if (!dev->chip_id && b53_switch_detect(dev))
2097 return -EINVAL;
2098
2099 ret = b53_switch_init(dev);
2100 if (ret)
2101 return ret;
2102
2103 pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
2104
2105 return dsa_register_switch(dev->ds);
2106}
2107EXPORT_SYMBOL(b53_switch_register);
2108
2109MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2110MODULE_DESCRIPTION("B53 switch library");
2111MODULE_LICENSE("Dual BSD/GPL");