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1#
2# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
3#
4# This program is free software; you can redistribute it and/or modify
5# it under the terms of the GNU General Public License version 2 as
6# published by the Free Software Foundation.
7#
8
9config ARC
10 def_bool y
11 select ARC_TIMERS
12 select ARCH_HAS_SG_CHAIN
13 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
14 select BUILDTIME_EXTABLE_SORT
15 select CLONE_BACKWARDS
16 select COMMON_CLK
17 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
18 select GENERIC_CLOCKEVENTS
19 select GENERIC_FIND_FIRST_BIT
20 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
21 select GENERIC_IRQ_SHOW
22 select GENERIC_PCI_IOMAP
23 select GENERIC_PENDING_IRQ if SMP
24 select GENERIC_SMP_IDLE_THREAD
25 select HAVE_ARCH_KGDB
26 select HAVE_ARCH_TRACEHOOK
27 select HAVE_FUTEX_CMPXCHG
28 select HAVE_IOREMAP_PROT
29 select HAVE_KPROBES
30 select HAVE_KRETPROBES
31 select HAVE_MEMBLOCK
32 select HAVE_MOD_ARCH_SPECIFIC
33 select HAVE_OPROFILE
34 select HAVE_PERF_EVENTS
35 select HANDLE_DOMAIN_IRQ
36 select IRQ_DOMAIN
37 select MODULES_USE_ELF_RELA
38 select NO_BOOTMEM
39 select OF
40 select OF_EARLY_FLATTREE
41 select OF_RESERVED_MEM
42 select PERF_USE_VMALLOC
43 select HAVE_DEBUG_STACKOVERFLOW
44 select HAVE_GENERIC_DMA_COHERENT
45 select HAVE_KERNEL_GZIP
46 select HAVE_KERNEL_LZMA
47
48config MIGHT_HAVE_PCI
49 bool
50
51config TRACE_IRQFLAGS_SUPPORT
52 def_bool y
53
54config LOCKDEP_SUPPORT
55 def_bool y
56
57config SCHED_OMIT_FRAME_POINTER
58 def_bool y
59
60config GENERIC_CSUM
61 def_bool y
62
63config RWSEM_GENERIC_SPINLOCK
64 def_bool y
65
66config ARCH_DISCONTIGMEM_ENABLE
67 def_bool n
68
69config ARCH_FLATMEM_ENABLE
70 def_bool y
71
72config MMU
73 def_bool y
74
75config NO_IOPORT_MAP
76 def_bool y
77
78config GENERIC_CALIBRATE_DELAY
79 def_bool y
80
81config GENERIC_HWEIGHT
82 def_bool y
83
84config STACKTRACE_SUPPORT
85 def_bool y
86 select STACKTRACE
87
88config HAVE_ARCH_TRANSPARENT_HUGEPAGE
89 def_bool y
90 depends on ARC_MMU_V4
91
92source "init/Kconfig"
93source "kernel/Kconfig.freezer"
94
95menu "ARC Architecture Configuration"
96
97menu "ARC Platform/SoC/Board"
98
99source "arch/arc/plat-sim/Kconfig"
100source "arch/arc/plat-tb10x/Kconfig"
101source "arch/arc/plat-axs10x/Kconfig"
102#New platform adds here
103source "arch/arc/plat-eznps/Kconfig"
104
105endmenu
106
107choice
108 prompt "ARC Instruction Set"
109 default ISA_ARCOMPACT
110
111config ISA_ARCOMPACT
112 bool "ARCompact ISA"
113 select CPU_NO_EFFICIENT_FFS
114 help
115 The original ARC ISA of ARC600/700 cores
116
117config ISA_ARCV2
118 bool "ARC ISA v2"
119 select ARC_TIMERS_64BIT
120 help
121 ISA for the Next Generation ARC-HS cores
122
123endchoice
124
125menu "ARC CPU Configuration"
126
127choice
128 prompt "ARC Core"
129 default ARC_CPU_770 if ISA_ARCOMPACT
130 default ARC_CPU_HS if ISA_ARCV2
131
132if ISA_ARCOMPACT
133
134config ARC_CPU_750D
135 bool "ARC750D"
136 select ARC_CANT_LLSC
137 help
138 Support for ARC750 core
139
140config ARC_CPU_770
141 bool "ARC770"
142 select ARC_HAS_SWAPE
143 help
144 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
145 This core has a bunch of cool new features:
146 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
147 Shared Address Spaces (for sharing TLB entires in MMU)
148 -Caches: New Prog Model, Region Flush
149 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
150
151endif #ISA_ARCOMPACT
152
153config ARC_CPU_HS
154 bool "ARC-HS"
155 depends on ISA_ARCV2
156 help
157 Support for ARC HS38x Cores based on ARCv2 ISA
158 The notable features are:
159 - SMP configurations of upto 4 core with coherency
160 - Optional L2 Cache and IO-Coherency
161 - Revised Interrupt Architecture (multiple priorites, reg banks,
162 auto stack switch, auto regfile save/restore)
163 - MMUv4 (PIPT dcache, Huge Pages)
164 - Instructions for
165 * 64bit load/store: LDD, STD
166 * Hardware assisted divide/remainder: DIV, REM
167 * Function prologue/epilogue: ENTER_S, LEAVE_S
168 * IRQ enable/disable: CLRI, SETI
169 * pop count: FFS, FLS
170 * SETcc, BMSKN, XBFU...
171
172endchoice
173
174config CPU_BIG_ENDIAN
175 bool "Enable Big Endian Mode"
176 default n
177 help
178 Build kernel for Big Endian Mode of ARC CPU
179
180config SMP
181 bool "Symmetric Multi-Processing"
182 default n
183 select ARC_HAS_COH_CACHES if ISA_ARCV2
184 select ARC_MCIP if ISA_ARCV2
185 help
186 This enables support for systems with more than one CPU.
187
188if SMP
189
190config ARC_HAS_COH_CACHES
191 def_bool n
192
193config NR_CPUS
194 int "Maximum number of CPUs (2-4096)"
195 range 2 4096
196 default "4"
197
198config ARC_SMP_HALT_ON_RESET
199 bool "Enable Halt-on-reset boot mode"
200 default y if ARC_UBOOT_SUPPORT
201 help
202 In SMP configuration cores can be configured as Halt-on-reset
203 or they could all start at same time. For Halt-on-reset, non
204 masters are parked until Master kicks them so they can start of
205 at designated entry point. For other case, all jump to common
206 entry point and spin wait for Master's signal.
207
208endif #SMP
209
210config ARC_MCIP
211 bool "ARConnect Multicore IP (MCIP) Support "
212 depends on ISA_ARCV2
213 default y if SMP
214 help
215 This IP block enables SMP in ARC-HS38 cores.
216 It provides for cross-core interrupts, multi-core debug
217 hardware semaphores, shared memory,....
218
219menuconfig ARC_CACHE
220 bool "Enable Cache Support"
221 default y
222 # if SMP, cache enabled ONLY if ARC implementation has cache coherency
223 depends on !SMP || ARC_HAS_COH_CACHES
224
225if ARC_CACHE
226
227config ARC_CACHE_LINE_SHIFT
228 int "Cache Line Length (as power of 2)"
229 range 5 7
230 default "6"
231 help
232 Starting with ARC700 4.9, Cache line length is configurable,
233 This option specifies "N", with Line-len = 2 power N
234 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
235 Linux only supports same line lengths for I and D caches.
236
237config ARC_HAS_ICACHE
238 bool "Use Instruction Cache"
239 default y
240
241config ARC_HAS_DCACHE
242 bool "Use Data Cache"
243 default y
244
245config ARC_CACHE_PAGES
246 bool "Per Page Cache Control"
247 default y
248 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
249 help
250 This can be used to over-ride the global I/D Cache Enable on a
251 per-page basis (but only for pages accessed via MMU such as
252 Kernel Virtual address or User Virtual Address)
253 TLB entries have a per-page Cache Enable Bit.
254 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
255 Global DISABLE + Per Page ENABLE won't work
256
257config ARC_CACHE_VIPT_ALIASING
258 bool "Support VIPT Aliasing D$"
259 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
260 default n
261
262endif #ARC_CACHE
263
264config ARC_HAS_ICCM
265 bool "Use ICCM"
266 help
267 Single Cycle RAMS to store Fast Path Code
268 default n
269
270config ARC_ICCM_SZ
271 int "ICCM Size in KB"
272 default "64"
273 depends on ARC_HAS_ICCM
274
275config ARC_HAS_DCCM
276 bool "Use DCCM"
277 help
278 Single Cycle RAMS to store Fast Path Data
279 default n
280
281config ARC_DCCM_SZ
282 int "DCCM Size in KB"
283 default "64"
284 depends on ARC_HAS_DCCM
285
286config ARC_DCCM_BASE
287 hex "DCCM map address"
288 default "0xA0000000"
289 depends on ARC_HAS_DCCM
290
291choice
292 prompt "MMU Version"
293 default ARC_MMU_V3 if ARC_CPU_770
294 default ARC_MMU_V2 if ARC_CPU_750D
295 default ARC_MMU_V4 if ARC_CPU_HS
296
297if ISA_ARCOMPACT
298
299config ARC_MMU_V1
300 bool "MMU v1"
301 help
302 Orig ARC700 MMU
303
304config ARC_MMU_V2
305 bool "MMU v2"
306 help
307 Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
308 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
309
310config ARC_MMU_V3
311 bool "MMU v3"
312 depends on ARC_CPU_770
313 help
314 Introduced with ARC700 4.10: New Features
315 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
316 Shared Address Spaces (SASID)
317
318endif
319
320config ARC_MMU_V4
321 bool "MMU v4"
322 depends on ISA_ARCV2
323
324endchoice
325
326
327choice
328 prompt "MMU Page Size"
329 default ARC_PAGE_SIZE_8K
330
331config ARC_PAGE_SIZE_8K
332 bool "8KB"
333 help
334 Choose between 8k vs 16k
335
336config ARC_PAGE_SIZE_16K
337 bool "16KB"
338 depends on ARC_MMU_V3 || ARC_MMU_V4
339
340config ARC_PAGE_SIZE_4K
341 bool "4KB"
342 depends on ARC_MMU_V3 || ARC_MMU_V4
343
344endchoice
345
346choice
347 prompt "MMU Super Page Size"
348 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
349 default ARC_HUGEPAGE_2M
350
351config ARC_HUGEPAGE_2M
352 bool "2MB"
353
354config ARC_HUGEPAGE_16M
355 bool "16MB"
356
357endchoice
358
359config NODES_SHIFT
360 int "Maximum NUMA Nodes (as a power of 2)"
361 default "0" if !DISCONTIGMEM
362 default "1" if DISCONTIGMEM
363 depends on NEED_MULTIPLE_NODES
364 ---help---
365 Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
366 zones.
367
368if ISA_ARCOMPACT
369
370config ARC_COMPACT_IRQ_LEVELS
371 bool "Setup Timer IRQ as high Priority"
372 default n
373 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
374 depends on !SMP
375
376config ARC_FPU_SAVE_RESTORE
377 bool "Enable FPU state persistence across context switch"
378 default n
379 help
380 Double Precision Floating Point unit had dedictaed regs which
381 need to be saved/restored across context-switch.
382 Note that ARC FPU is overly simplistic, unlike say x86, which has
383 hardware pieces to allow software to conditionally save/restore,
384 based on actual usage of FPU by a task. Thus our implemn does
385 this for all tasks in system.
386
387endif #ISA_ARCOMPACT
388
389config ARC_CANT_LLSC
390 def_bool n
391
392config ARC_HAS_LLSC
393 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
394 default y
395 depends on !ARC_CANT_LLSC
396
397config ARC_HAS_SWAPE
398 bool "Insn: SWAPE (endian-swap)"
399 default y
400
401if ISA_ARCV2
402
403config ARC_HAS_LL64
404 bool "Insn: 64bit LDD/STD"
405 help
406 Enable gcc to generate 64-bit load/store instructions
407 ISA mandates even/odd registers to allow encoding of two
408 dest operands with 2 possible source operands.
409 default y
410
411config ARC_HAS_DIV_REM
412 bool "Insn: div, divu, rem, remu"
413 default y
414
415config ARC_NUMBER_OF_INTERRUPTS
416 int "Number of interrupts"
417 range 8 240
418 default 32
419 help
420 This defines the number of interrupts on the ARCv2HS core.
421 It affects the size of vector table.
422 The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable
423 in hardware, it keep things simple for Linux to assume they are always
424 present.
425
426endif # ISA_ARCV2
427
428endmenu # "ARC CPU Configuration"
429
430config LINUX_LINK_BASE
431 hex "Linux Link Address"
432 default "0x80000000"
433 help
434 ARC700 divides the 32 bit phy address space into two equal halves
435 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
436 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
437 Typically Linux kernel is linked at the start of untransalted addr,
438 hence the default value of 0x8zs.
439 However some customers have peripherals mapped at this addr, so
440 Linux needs to be scooted a bit.
441 If you don't know what the above means, leave this setting alone.
442 This needs to match memory start address specified in Device Tree
443
444config HIGHMEM
445 bool "High Memory Support"
446 select ARCH_DISCONTIGMEM_ENABLE
447 help
448 With ARC 2G:2G address split, only upper 2G is directly addressable by
449 kernel. Enable this to potentially allow access to rest of 2G and PAE
450 in future
451
452config ARC_HAS_PAE40
453 bool "Support for the 40-bit Physical Address Extension"
454 default n
455 depends on ISA_ARCV2
456 help
457 Enable access to physical memory beyond 4G, only supported on
458 ARC cores with 40 bit Physical Addressing support
459
460config ARCH_PHYS_ADDR_T_64BIT
461 def_bool ARC_HAS_PAE40
462
463config ARCH_DMA_ADDR_T_64BIT
464 bool
465
466config ARC_PLAT_NEEDS_PHYS_TO_DMA
467 bool
468
469config ARC_KVADDR_SIZE
470 int "Kernel Virtaul Address Space size (MB)"
471 range 0 512
472 default "256"
473 help
474 The kernel address space is carved out of 256MB of translated address
475 space for catering to vmalloc, modules, pkmap, fixmap. This however may
476 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
477 this to be stretched to 512 MB (by extending into the reserved
478 kernel-user gutter)
479
480config ARC_CURR_IN_REG
481 bool "Dedicate Register r25 for current_task pointer"
482 default y
483 help
484 This reserved Register R25 to point to Current Task in
485 kernel mode. This saves memory access for each such access
486
487
488config ARC_EMUL_UNALIGNED
489 bool "Emulate unaligned memory access (userspace only)"
490 default N
491 select SYSCTL_ARCH_UNALIGN_NO_WARN
492 select SYSCTL_ARCH_UNALIGN_ALLOW
493 depends on ISA_ARCOMPACT
494 help
495 This enables misaligned 16 & 32 bit memory access from user space.
496 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
497 potential bugs in code
498
499config HZ
500 int "Timer Frequency"
501 default 100
502
503config ARC_METAWARE_HLINK
504 bool "Support for Metaware debugger assisted Host access"
505 default n
506 help
507 This options allows a Linux userland apps to directly access
508 host file system (open/creat/read/write etc) with help from
509 Metaware Debugger. This can come in handy for Linux-host communication
510 when there is no real usable peripheral such as EMAC.
511
512menuconfig ARC_DBG
513 bool "ARC debugging"
514 default y
515
516if ARC_DBG
517
518config ARC_DW2_UNWIND
519 bool "Enable DWARF specific kernel stack unwind"
520 default y
521 select KALLSYMS
522 help
523 Compiles the kernel with DWARF unwind information and can be used
524 to get stack backtraces.
525
526 If you say Y here the resulting kernel image will be slightly larger
527 but not slower, and it will give very useful debugging information.
528 If you don't debug the kernel, you can say N, but we may not be able
529 to solve problems without frame unwind information
530
531config ARC_DBG_TLB_PARANOIA
532 bool "Paranoia Checks in Low Level TLB Handlers"
533 default n
534
535endif
536
537config ARC_UBOOT_SUPPORT
538 bool "Support uboot arg Handling"
539 default n
540 help
541 ARC Linux by default checks for uboot provided args as pointers to
542 external cmdline or DTB. This however breaks in absence of uboot,
543 when booting from Metaware debugger directly, as the registers are
544 not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
545 registers look like uboot args to kernel which then chokes.
546 So only enable the uboot arg checking/processing if users are sure
547 of uboot being in play.
548
549config ARC_BUILTIN_DTB_NAME
550 string "Built in DTB"
551 help
552 Set the name of the DTB to embed in the vmlinux binary
553 Leaving it blank selects the minimal "skeleton" dtb
554
555source "kernel/Kconfig.preempt"
556
557menu "Executable file formats"
558source "fs/Kconfig.binfmt"
559endmenu
560
561endmenu # "ARC Architecture Configuration"
562
563source "mm/Kconfig"
564
565config FORCE_MAX_ZONEORDER
566 int "Maximum zone order"
567 default "12" if ARC_HUGEPAGE_16M
568 default "11"
569
570source "net/Kconfig"
571source "drivers/Kconfig"
572
573menu "Bus Support"
574
575config PCI
576 bool "PCI support" if MIGHT_HAVE_PCI
577 help
578 PCI is the name of a bus system, i.e., the way the CPU talks to
579 the other stuff inside your box. Find out if your board/platform
580 has PCI.
581
582 Note: PCIe support for Synopsys Device will be available only
583 when HAPS DX is configured with PCIe RC bitmap. If you have PCI,
584 say Y, otherwise N.
585
586config PCI_SYSCALL
587 def_bool PCI
588
589source "drivers/pci/Kconfig"
590
591endmenu
592
593source "fs/Kconfig"
594source "arch/arc/Kconfig.debug"
595source "security/Kconfig"
596source "crypto/Kconfig"
597source "lib/Kconfig"
598source "kernel/power/Kconfig"
1# SPDX-License-Identifier: GPL-2.0-only
2#
3# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
4#
5
6config ARC
7 def_bool y
8 select ARC_TIMERS
9 select ARCH_HAS_CACHE_LINE_SIZE
10 select ARCH_HAS_DEBUG_VM_PGTABLE
11 select ARCH_HAS_DMA_PREP_COHERENT
12 select ARCH_HAS_PTE_SPECIAL
13 select ARCH_HAS_SETUP_DMA_OPS
14 select ARCH_HAS_SYNC_DMA_FOR_CPU
15 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
16 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
17 select ARCH_32BIT_OFF_T
18 select BUILDTIME_TABLE_SORT
19 select CLONE_BACKWARDS
20 select COMMON_CLK
21 select DMA_DIRECT_REMAP
22 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
23 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
24 select GENERIC_IRQ_SHOW
25 select GENERIC_PCI_IOMAP
26 select GENERIC_PENDING_IRQ if SMP
27 select GENERIC_SCHED_CLOCK
28 select GENERIC_SMP_IDLE_THREAD
29 select GENERIC_IOREMAP
30 select GENERIC_STRNCPY_FROM_USER if MMU
31 select GENERIC_STRNLEN_USER if MMU
32 select HAVE_ARCH_KGDB
33 select HAVE_ARCH_TRACEHOOK
34 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4
35 select HAVE_DEBUG_STACKOVERFLOW
36 select HAVE_DEBUG_KMEMLEAK
37 select HAVE_IOREMAP_PROT
38 select HAVE_KERNEL_GZIP
39 select HAVE_KERNEL_LZMA
40 select HAVE_KPROBES
41 select HAVE_KRETPROBES
42 select HAVE_REGS_AND_STACK_ACCESS_API
43 select HAVE_MOD_ARCH_SPECIFIC
44 select HAVE_PERF_EVENTS
45 select HAVE_SYSCALL_TRACEPOINTS
46 select IRQ_DOMAIN
47 select LOCK_MM_AND_FIND_VMA
48 select MODULES_USE_ELF_RELA
49 select OF
50 select OF_EARLY_FLATTREE
51 select PCI_SYSCALL if PCI
52 select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32
53 select TRACE_IRQFLAGS_SUPPORT
54
55config LOCKDEP_SUPPORT
56 def_bool y
57
58config SCHED_OMIT_FRAME_POINTER
59 def_bool y
60
61config GENERIC_CSUM
62 def_bool y
63
64config ARCH_FLATMEM_ENABLE
65 def_bool y
66
67config MMU
68 def_bool y
69
70config NO_IOPORT_MAP
71 def_bool y
72
73config GENERIC_CALIBRATE_DELAY
74 def_bool y
75
76config GENERIC_HWEIGHT
77 def_bool y
78
79config STACKTRACE_SUPPORT
80 def_bool y
81 select STACKTRACE
82
83menu "ARC Architecture Configuration"
84
85menu "ARC Platform/SoC/Board"
86
87source "arch/arc/plat-tb10x/Kconfig"
88source "arch/arc/plat-axs10x/Kconfig"
89source "arch/arc/plat-hsdk/Kconfig"
90
91endmenu
92
93choice
94 prompt "ARC Instruction Set"
95 default ISA_ARCV2
96
97config ISA_ARCOMPACT
98 bool "ARCompact ISA"
99 select CPU_NO_EFFICIENT_FFS
100 help
101 The original ARC ISA of ARC600/700 cores
102
103config ISA_ARCV2
104 bool "ARC ISA v2"
105 select ARC_TIMERS_64BIT
106 help
107 ISA for the Next Generation ARC-HS cores
108
109endchoice
110
111menu "ARC CPU Configuration"
112
113choice
114 prompt "ARC Core"
115 default ARC_CPU_770 if ISA_ARCOMPACT
116 default ARC_CPU_HS if ISA_ARCV2
117
118config ARC_CPU_770
119 bool "ARC770"
120 depends on ISA_ARCOMPACT
121 select ARC_HAS_SWAPE
122 help
123 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
124 This core has a bunch of cool new features:
125 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
126 Shared Address Spaces (for sharing TLB entries in MMU)
127 -Caches: New Prog Model, Region Flush
128 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
129
130config ARC_CPU_HS
131 bool "ARC-HS"
132 depends on ISA_ARCV2
133 help
134 Support for ARC HS38x Cores based on ARCv2 ISA
135 The notable features are:
136 - SMP configurations of up to 4 cores with coherency
137 - Optional L2 Cache and IO-Coherency
138 - Revised Interrupt Architecture (multiple priorites, reg banks,
139 auto stack switch, auto regfile save/restore)
140 - MMUv4 (PIPT dcache, Huge Pages)
141 - Instructions for
142 * 64bit load/store: LDD, STD
143 * Hardware assisted divide/remainder: DIV, REM
144 * Function prologue/epilogue: ENTER_S, LEAVE_S
145 * IRQ enable/disable: CLRI, SETI
146 * pop count: FFS, FLS
147 * SETcc, BMSKN, XBFU...
148
149endchoice
150
151config ARC_TUNE_MCPU
152 string "Override default -mcpu compiler flag"
153 default ""
154 help
155 Override default -mcpu=xxx compiler flag (which is set depending on
156 the ISA version) with the specified value.
157 NOTE: If specified flag isn't supported by current compiler the
158 ISA default value will be used as a fallback.
159
160config CPU_BIG_ENDIAN
161 bool "Enable Big Endian Mode"
162 help
163 Build kernel for Big Endian Mode of ARC CPU
164
165config SMP
166 bool "Symmetric Multi-Processing"
167 select ARC_MCIP if ISA_ARCV2
168 help
169 This enables support for systems with more than one CPU.
170
171if SMP
172
173config NR_CPUS
174 int "Maximum number of CPUs (2-4096)"
175 range 2 4096
176 default "4"
177
178config ARC_SMP_HALT_ON_RESET
179 bool "Enable Halt-on-reset boot mode"
180 help
181 In SMP configuration cores can be configured as Halt-on-reset
182 or they could all start at same time. For Halt-on-reset, non
183 masters are parked until Master kicks them so they can start off
184 at designated entry point. For other case, all jump to common
185 entry point and spin wait for Master's signal.
186
187endif #SMP
188
189config ARC_MCIP
190 bool "ARConnect Multicore IP (MCIP) Support "
191 depends on ISA_ARCV2
192 default y if SMP
193 help
194 This IP block enables SMP in ARC-HS38 cores.
195 It provides for cross-core interrupts, multi-core debug
196 hardware semaphores, shared memory,....
197
198menuconfig ARC_CACHE
199 bool "Enable Cache Support"
200 default y
201
202if ARC_CACHE
203
204config ARC_CACHE_LINE_SHIFT
205 int "Cache Line Length (as power of 2)"
206 range 5 7
207 default "6"
208 help
209 Starting with ARC700 4.9, Cache line length is configurable,
210 This option specifies "N", with Line-len = 2 power N
211 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
212 Linux only supports same line lengths for I and D caches.
213
214config ARC_HAS_ICACHE
215 bool "Use Instruction Cache"
216 default y
217
218config ARC_HAS_DCACHE
219 bool "Use Data Cache"
220 default y
221
222config ARC_CACHE_PAGES
223 bool "Per Page Cache Control"
224 default y
225 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
226 help
227 This can be used to over-ride the global I/D Cache Enable on a
228 per-page basis (but only for pages accessed via MMU such as
229 Kernel Virtual address or User Virtual Address)
230 TLB entries have a per-page Cache Enable Bit.
231 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
232 Global DISABLE + Per Page ENABLE won't work
233
234endif #ARC_CACHE
235
236config ARC_HAS_ICCM
237 bool "Use ICCM"
238 help
239 Single Cycle RAMS to store Fast Path Code
240
241config ARC_ICCM_SZ
242 int "ICCM Size in KB"
243 default "64"
244 depends on ARC_HAS_ICCM
245
246config ARC_HAS_DCCM
247 bool "Use DCCM"
248 help
249 Single Cycle RAMS to store Fast Path Data
250
251config ARC_DCCM_SZ
252 int "DCCM Size in KB"
253 default "64"
254 depends on ARC_HAS_DCCM
255
256config ARC_DCCM_BASE
257 hex "DCCM map address"
258 default "0xA0000000"
259 depends on ARC_HAS_DCCM
260
261choice
262 prompt "MMU Version"
263 default ARC_MMU_V3 if ISA_ARCOMPACT
264 default ARC_MMU_V4 if ISA_ARCV2
265
266config ARC_MMU_V3
267 bool "MMU v3"
268 depends on ISA_ARCOMPACT
269 help
270 Introduced with ARC700 4.10: New Features
271 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
272 Shared Address Spaces (SASID)
273
274config ARC_MMU_V4
275 bool "MMU v4"
276 depends on ISA_ARCV2
277
278endchoice
279
280
281choice
282 prompt "MMU Page Size"
283 default ARC_PAGE_SIZE_8K
284
285config ARC_PAGE_SIZE_8K
286 bool "8KB"
287 help
288 Choose between 8k vs 16k
289
290config ARC_PAGE_SIZE_16K
291 bool "16KB"
292
293config ARC_PAGE_SIZE_4K
294 bool "4KB"
295 depends on ARC_MMU_V3 || ARC_MMU_V4
296
297endchoice
298
299choice
300 prompt "MMU Super Page Size"
301 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
302 default ARC_HUGEPAGE_2M
303
304config ARC_HUGEPAGE_2M
305 bool "2MB"
306
307config ARC_HUGEPAGE_16M
308 bool "16MB"
309
310endchoice
311
312config PGTABLE_LEVELS
313 int "Number of Page table levels"
314 default 2
315
316config ARC_COMPACT_IRQ_LEVELS
317 depends on ISA_ARCOMPACT
318 bool "Setup Timer IRQ as high Priority"
319 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
320 depends on !SMP
321
322config ARC_FPU_SAVE_RESTORE
323 bool "Enable FPU state persistence across context switch"
324 help
325 ARCompact FPU has internal registers to assist with Double precision
326 Floating Point operations. There are control and stauts registers
327 for floating point exceptions and rounding modes. These are
328 preserved across task context switch when enabled.
329
330config ARC_CANT_LLSC
331 def_bool n
332
333config ARC_HAS_LLSC
334 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
335 default y
336 depends on !ARC_CANT_LLSC
337
338config ARC_HAS_SWAPE
339 bool "Insn: SWAPE (endian-swap)"
340 default y
341
342if ISA_ARCV2
343
344config ARC_USE_UNALIGNED_MEM_ACCESS
345 bool "Enable unaligned access in HW"
346 default y
347 select HAVE_EFFICIENT_UNALIGNED_ACCESS
348 help
349 The ARC HS architecture supports unaligned memory access
350 which is disabled by default. Enable unaligned access in
351 hardware and use software to use it
352
353config ARC_HAS_LL64
354 bool "Insn: 64bit LDD/STD"
355 help
356 Enable gcc to generate 64-bit load/store instructions
357 ISA mandates even/odd registers to allow encoding of two
358 dest operands with 2 possible source operands.
359 default y
360
361config ARC_HAS_DIV_REM
362 bool "Insn: div, divu, rem, remu"
363 default y
364
365config ARC_HAS_ACCL_REGS
366 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)"
367 default y
368 help
369 Depending on the configuration, CPU can contain accumulator reg-pair
370 (also referred to as r58:r59). These can also be used by gcc as GPR so
371 kernel needs to save/restore per process
372
373config ARC_DSP_HANDLED
374 def_bool n
375
376config ARC_DSP_SAVE_RESTORE_REGS
377 def_bool n
378
379choice
380 prompt "DSP support"
381 default ARC_DSP_NONE
382 help
383 Depending on the configuration, CPU can contain DSP registers
384 (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL).
385 Below are options describing how to handle these registers in
386 interrupt entry / exit and in context switch.
387
388config ARC_DSP_NONE
389 bool "No DSP extension presence in HW"
390 help
391 No DSP extension presence in HW
392
393config ARC_DSP_KERNEL
394 bool "DSP extension in HW, no support for userspace"
395 select ARC_HAS_ACCL_REGS
396 select ARC_DSP_HANDLED
397 help
398 DSP extension presence in HW, no support for DSP-enabled userspace
399 applications. We don't save / restore DSP registers and only do
400 some minimal preparations so userspace won't be able to break kernel
401
402config ARC_DSP_USERSPACE
403 bool "Support DSP for userspace apps"
404 select ARC_HAS_ACCL_REGS
405 select ARC_DSP_HANDLED
406 select ARC_DSP_SAVE_RESTORE_REGS
407 help
408 DSP extension presence in HW, support save / restore DSP registers to
409 run DSP-enabled userspace applications
410
411config ARC_DSP_AGU_USERSPACE
412 bool "Support DSP with AGU for userspace apps"
413 select ARC_HAS_ACCL_REGS
414 select ARC_DSP_HANDLED
415 select ARC_DSP_SAVE_RESTORE_REGS
416 help
417 DSP and AGU extensions presence in HW, support save / restore DSP
418 and AGU registers to run DSP-enabled userspace applications
419endchoice
420
421config ARC_IRQ_NO_AUTOSAVE
422 bool "Disable hardware autosave regfile on interrupts"
423 default n
424 help
425 On HS cores, taken interrupt auto saves the regfile on stack.
426 This is programmable and can be optionally disabled in which case
427 software INTERRUPT_PROLOGUE/EPILGUE do the needed work
428
429config ARC_LPB_DISABLE
430 bool "Disable loop buffer (LPB)"
431 help
432 On HS cores, loop buffer (LPB) is programmable in runtime and can
433 be optionally disabled.
434
435endif # ISA_ARCV2
436
437endmenu # "ARC CPU Configuration"
438
439config LINUX_LINK_BASE
440 hex "Kernel link address"
441 default "0x80000000"
442 help
443 ARC700 divides the 32 bit phy address space into two equal halves
444 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
445 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
446 Typically Linux kernel is linked at the start of untransalted addr,
447 hence the default value of 0x8zs.
448 However some customers have peripherals mapped at this addr, so
449 Linux needs to be scooted a bit.
450 If you don't know what the above means, leave this setting alone.
451 This needs to match memory start address specified in Device Tree
452
453config LINUX_RAM_BASE
454 hex "RAM base address"
455 default LINUX_LINK_BASE
456 help
457 By default Linux is linked at base of RAM. However in some special
458 cases (such as HSDK), Linux can't be linked at start of DDR, hence
459 this option.
460
461config HIGHMEM
462 bool "High Memory Support"
463 select HAVE_ARCH_PFN_VALID
464 select KMAP_LOCAL
465 help
466 With ARC 2G:2G address split, only upper 2G is directly addressable by
467 kernel. Enable this to potentially allow access to rest of 2G and PAE
468 in future
469
470config ARC_HAS_PAE40
471 bool "Support for the 40-bit Physical Address Extension"
472 depends on ISA_ARCV2
473 select HIGHMEM
474 select PHYS_ADDR_T_64BIT
475 help
476 Enable access to physical memory beyond 4G, only supported on
477 ARC cores with 40 bit Physical Addressing support
478
479config ARC_KVADDR_SIZE
480 int "Kernel Virtual Address Space size (MB)"
481 range 0 512
482 default "256"
483 help
484 The kernel address space is carved out of 256MB of translated address
485 space for catering to vmalloc, modules, pkmap, fixmap. This however may
486 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
487 this to be stretched to 512 MB (by extending into the reserved
488 kernel-user gutter)
489
490config ARC_CURR_IN_REG
491 bool "cache current task pointer in gp"
492 default y
493 help
494 This reserves gp register to point to Current Task in
495 kernel mode eliding memory access for each access
496
497
498config ARC_EMUL_UNALIGNED
499 bool "Emulate unaligned memory access (userspace only)"
500 select SYSCTL_ARCH_UNALIGN_NO_WARN
501 select SYSCTL_ARCH_UNALIGN_ALLOW
502 depends on ISA_ARCOMPACT
503 help
504 This enables misaligned 16 & 32 bit memory access from user space.
505 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
506 potential bugs in code
507
508config HZ
509 int "Timer Frequency"
510 default 100
511
512config ARC_METAWARE_HLINK
513 bool "Support for Metaware debugger assisted Host access"
514 help
515 This options allows a Linux userland apps to directly access
516 host file system (open/creat/read/write etc) with help from
517 Metaware Debugger. This can come in handy for Linux-host communication
518 when there is no real usable peripheral such as EMAC.
519
520menuconfig ARC_DBG
521 bool "ARC debugging"
522 default y
523
524if ARC_DBG
525
526config ARC_DW2_UNWIND
527 bool "Enable DWARF specific kernel stack unwind"
528 default y
529 select KALLSYMS
530 help
531 Compiles the kernel with DWARF unwind information and can be used
532 to get stack backtraces.
533
534 If you say Y here the resulting kernel image will be slightly larger
535 but not slower, and it will give very useful debugging information.
536 If you don't debug the kernel, you can say N, but we may not be able
537 to solve problems without frame unwind information
538
539config ARC_DBG_JUMP_LABEL
540 bool "Paranoid checks in Static Keys (jump labels) code"
541 depends on JUMP_LABEL
542 default y if STATIC_KEYS_SELFTEST
543 help
544 Enable paranoid checks and self-test of both ARC-specific and generic
545 part of static keys (jump labels) related code.
546endif
547
548config ARC_BUILTIN_DTB_NAME
549 string "Built in DTB"
550 help
551 Set the name of the DTB to embed in the vmlinux binary
552 Leaving it blank selects the minimal "skeleton" dtb
553
554endmenu # "ARC Architecture Configuration"
555
556config ARCH_FORCE_MAX_ORDER
557 int "Maximum zone order"
558 default "11" if ARC_HUGEPAGE_16M
559 default "10"
560
561source "kernel/power/Kconfig"