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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
12 */
13#ifndef _ASM_MIPSREGS_H
14#define _ASM_MIPSREGS_H
15
16#include <linux/linkage.h>
17#include <linux/types.h>
18#include <asm/hazards.h>
19#include <asm/war.h>
20
21/*
22 * The following macros are especially useful for __asm__
23 * inline assembler.
24 */
25#ifndef __STR
26#define __STR(x) #x
27#endif
28#ifndef STR
29#define STR(x) __STR(x)
30#endif
31
32/*
33 * Configure language
34 */
35#ifdef __ASSEMBLY__
36#define _ULCAST_
37#else
38#define _ULCAST_ (unsigned long)
39#endif
40
41/*
42 * Coprocessor 0 register names
43 */
44#define CP0_INDEX $0
45#define CP0_RANDOM $1
46#define CP0_ENTRYLO0 $2
47#define CP0_ENTRYLO1 $3
48#define CP0_CONF $3
49#define CP0_CONTEXT $4
50#define CP0_PAGEMASK $5
51#define CP0_SEGCTL0 $5, 2
52#define CP0_SEGCTL1 $5, 3
53#define CP0_SEGCTL2 $5, 4
54#define CP0_WIRED $6
55#define CP0_INFO $7
56#define CP0_HWRENA $7
57#define CP0_BADVADDR $8
58#define CP0_BADINSTR $8, 1
59#define CP0_COUNT $9
60#define CP0_ENTRYHI $10
61#define CP0_GUESTCTL1 $10, 4
62#define CP0_GUESTCTL2 $10, 5
63#define CP0_GUESTCTL3 $10, 6
64#define CP0_COMPARE $11
65#define CP0_GUESTCTL0EXT $11, 4
66#define CP0_STATUS $12
67#define CP0_GUESTCTL0 $12, 6
68#define CP0_GTOFFSET $12, 7
69#define CP0_CAUSE $13
70#define CP0_EPC $14
71#define CP0_PRID $15
72#define CP0_EBASE $15, 1
73#define CP0_CMGCRBASE $15, 3
74#define CP0_CONFIG $16
75#define CP0_CONFIG3 $16, 3
76#define CP0_CONFIG5 $16, 5
77#define CP0_LLADDR $17
78#define CP0_WATCHLO $18
79#define CP0_WATCHHI $19
80#define CP0_XCONTEXT $20
81#define CP0_FRAMEMASK $21
82#define CP0_DIAGNOSTIC $22
83#define CP0_DEBUG $23
84#define CP0_DEPC $24
85#define CP0_PERFORMANCE $25
86#define CP0_ECC $26
87#define CP0_CACHEERR $27
88#define CP0_TAGLO $28
89#define CP0_TAGHI $29
90#define CP0_ERROREPC $30
91#define CP0_DESAVE $31
92
93/*
94 * R4640/R4650 cp0 register names. These registers are listed
95 * here only for completeness; without MMU these CPUs are not useable
96 * by Linux. A future ELKS port might take make Linux run on them
97 * though ...
98 */
99#define CP0_IBASE $0
100#define CP0_IBOUND $1
101#define CP0_DBASE $2
102#define CP0_DBOUND $3
103#define CP0_CALG $17
104#define CP0_IWATCH $18
105#define CP0_DWATCH $19
106
107/*
108 * Coprocessor 0 Set 1 register names
109 */
110#define CP0_S1_DERRADDR0 $26
111#define CP0_S1_DERRADDR1 $27
112#define CP0_S1_INTCONTROL $20
113
114/*
115 * Coprocessor 0 Set 2 register names
116 */
117#define CP0_S2_SRSCTL $12 /* MIPSR2 */
118
119/*
120 * Coprocessor 0 Set 3 register names
121 */
122#define CP0_S3_SRSMAP $12 /* MIPSR2 */
123
124/*
125 * TX39 Series
126 */
127#define CP0_TX39_CACHE $7
128
129
130/* Generic EntryLo bit definitions */
131#define ENTRYLO_G (_ULCAST_(1) << 0)
132#define ENTRYLO_V (_ULCAST_(1) << 1)
133#define ENTRYLO_D (_ULCAST_(1) << 2)
134#define ENTRYLO_C_SHIFT 3
135#define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT)
136
137/* R3000 EntryLo bit definitions */
138#define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
139#define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
140#define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
141#define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
142
143/* MIPS32/64 EntryLo bit definitions */
144#define MIPS_ENTRYLO_PFN_SHIFT 6
145#define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
146#define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
147
148/*
149 * Values for PageMask register
150 */
151#ifdef CONFIG_CPU_VR41XX
152
153/* Why doesn't stupidity hurt ... */
154
155#define PM_1K 0x00000000
156#define PM_4K 0x00001800
157#define PM_16K 0x00007800
158#define PM_64K 0x0001f800
159#define PM_256K 0x0007f800
160
161#else
162
163#define PM_4K 0x00000000
164#define PM_8K 0x00002000
165#define PM_16K 0x00006000
166#define PM_32K 0x0000e000
167#define PM_64K 0x0001e000
168#define PM_128K 0x0003e000
169#define PM_256K 0x0007e000
170#define PM_512K 0x000fe000
171#define PM_1M 0x001fe000
172#define PM_2M 0x003fe000
173#define PM_4M 0x007fe000
174#define PM_8M 0x00ffe000
175#define PM_16M 0x01ffe000
176#define PM_32M 0x03ffe000
177#define PM_64M 0x07ffe000
178#define PM_256M 0x1fffe000
179#define PM_1G 0x7fffe000
180
181#endif
182
183/*
184 * Default page size for a given kernel configuration
185 */
186#ifdef CONFIG_PAGE_SIZE_4KB
187#define PM_DEFAULT_MASK PM_4K
188#elif defined(CONFIG_PAGE_SIZE_8KB)
189#define PM_DEFAULT_MASK PM_8K
190#elif defined(CONFIG_PAGE_SIZE_16KB)
191#define PM_DEFAULT_MASK PM_16K
192#elif defined(CONFIG_PAGE_SIZE_32KB)
193#define PM_DEFAULT_MASK PM_32K
194#elif defined(CONFIG_PAGE_SIZE_64KB)
195#define PM_DEFAULT_MASK PM_64K
196#else
197#error Bad page size configuration!
198#endif
199
200/*
201 * Default huge tlb size for a given kernel configuration
202 */
203#ifdef CONFIG_PAGE_SIZE_4KB
204#define PM_HUGE_MASK PM_1M
205#elif defined(CONFIG_PAGE_SIZE_8KB)
206#define PM_HUGE_MASK PM_4M
207#elif defined(CONFIG_PAGE_SIZE_16KB)
208#define PM_HUGE_MASK PM_16M
209#elif defined(CONFIG_PAGE_SIZE_32KB)
210#define PM_HUGE_MASK PM_64M
211#elif defined(CONFIG_PAGE_SIZE_64KB)
212#define PM_HUGE_MASK PM_256M
213#elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
214#error Bad page size configuration for hugetlbfs!
215#endif
216
217/*
218 * Wired register bits
219 */
220#define MIPSR6_WIRED_LIMIT (_ULCAST_(0xffff) << 16)
221#define MIPSR6_WIRED_WIRED (_ULCAST_(0xffff) << 0)
222
223/*
224 * Values used for computation of new tlb entries
225 */
226#define PL_4K 12
227#define PL_16K 14
228#define PL_64K 16
229#define PL_256K 18
230#define PL_1M 20
231#define PL_4M 22
232#define PL_16M 24
233#define PL_64M 26
234#define PL_256M 28
235
236/*
237 * PageGrain bits
238 */
239#define PG_RIE (_ULCAST_(1) << 31)
240#define PG_XIE (_ULCAST_(1) << 30)
241#define PG_ELPA (_ULCAST_(1) << 29)
242#define PG_ESP (_ULCAST_(1) << 28)
243#define PG_IEC (_ULCAST_(1) << 27)
244
245/* MIPS32/64 EntryHI bit definitions */
246#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
247#define MIPS_ENTRYHI_ASIDX (_ULCAST_(0x3) << 8)
248#define MIPS_ENTRYHI_ASID (_ULCAST_(0xff) << 0)
249
250/*
251 * R4x00 interrupt enable / cause bits
252 */
253#define IE_SW0 (_ULCAST_(1) << 8)
254#define IE_SW1 (_ULCAST_(1) << 9)
255#define IE_IRQ0 (_ULCAST_(1) << 10)
256#define IE_IRQ1 (_ULCAST_(1) << 11)
257#define IE_IRQ2 (_ULCAST_(1) << 12)
258#define IE_IRQ3 (_ULCAST_(1) << 13)
259#define IE_IRQ4 (_ULCAST_(1) << 14)
260#define IE_IRQ5 (_ULCAST_(1) << 15)
261
262/*
263 * R4x00 interrupt cause bits
264 */
265#define C_SW0 (_ULCAST_(1) << 8)
266#define C_SW1 (_ULCAST_(1) << 9)
267#define C_IRQ0 (_ULCAST_(1) << 10)
268#define C_IRQ1 (_ULCAST_(1) << 11)
269#define C_IRQ2 (_ULCAST_(1) << 12)
270#define C_IRQ3 (_ULCAST_(1) << 13)
271#define C_IRQ4 (_ULCAST_(1) << 14)
272#define C_IRQ5 (_ULCAST_(1) << 15)
273
274/*
275 * Bitfields in the R4xx0 cp0 status register
276 */
277#define ST0_IE 0x00000001
278#define ST0_EXL 0x00000002
279#define ST0_ERL 0x00000004
280#define ST0_KSU 0x00000018
281# define KSU_USER 0x00000010
282# define KSU_SUPERVISOR 0x00000008
283# define KSU_KERNEL 0x00000000
284#define ST0_UX 0x00000020
285#define ST0_SX 0x00000040
286#define ST0_KX 0x00000080
287#define ST0_DE 0x00010000
288#define ST0_CE 0x00020000
289
290/*
291 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
292 * cacheops in userspace. This bit exists only on RM7000 and RM9000
293 * processors.
294 */
295#define ST0_CO 0x08000000
296
297/*
298 * Bitfields in the R[23]000 cp0 status register.
299 */
300#define ST0_IEC 0x00000001
301#define ST0_KUC 0x00000002
302#define ST0_IEP 0x00000004
303#define ST0_KUP 0x00000008
304#define ST0_IEO 0x00000010
305#define ST0_KUO 0x00000020
306/* bits 6 & 7 are reserved on R[23]000 */
307#define ST0_ISC 0x00010000
308#define ST0_SWC 0x00020000
309#define ST0_CM 0x00080000
310
311/*
312 * Bits specific to the R4640/R4650
313 */
314#define ST0_UM (_ULCAST_(1) << 4)
315#define ST0_IL (_ULCAST_(1) << 23)
316#define ST0_DL (_ULCAST_(1) << 24)
317
318/*
319 * Enable the MIPS MDMX and DSP ASEs
320 */
321#define ST0_MX 0x01000000
322
323/*
324 * Status register bits available in all MIPS CPUs.
325 */
326#define ST0_IM 0x0000ff00
327#define STATUSB_IP0 8
328#define STATUSF_IP0 (_ULCAST_(1) << 8)
329#define STATUSB_IP1 9
330#define STATUSF_IP1 (_ULCAST_(1) << 9)
331#define STATUSB_IP2 10
332#define STATUSF_IP2 (_ULCAST_(1) << 10)
333#define STATUSB_IP3 11
334#define STATUSF_IP3 (_ULCAST_(1) << 11)
335#define STATUSB_IP4 12
336#define STATUSF_IP4 (_ULCAST_(1) << 12)
337#define STATUSB_IP5 13
338#define STATUSF_IP5 (_ULCAST_(1) << 13)
339#define STATUSB_IP6 14
340#define STATUSF_IP6 (_ULCAST_(1) << 14)
341#define STATUSB_IP7 15
342#define STATUSF_IP7 (_ULCAST_(1) << 15)
343#define STATUSB_IP8 0
344#define STATUSF_IP8 (_ULCAST_(1) << 0)
345#define STATUSB_IP9 1
346#define STATUSF_IP9 (_ULCAST_(1) << 1)
347#define STATUSB_IP10 2
348#define STATUSF_IP10 (_ULCAST_(1) << 2)
349#define STATUSB_IP11 3
350#define STATUSF_IP11 (_ULCAST_(1) << 3)
351#define STATUSB_IP12 4
352#define STATUSF_IP12 (_ULCAST_(1) << 4)
353#define STATUSB_IP13 5
354#define STATUSF_IP13 (_ULCAST_(1) << 5)
355#define STATUSB_IP14 6
356#define STATUSF_IP14 (_ULCAST_(1) << 6)
357#define STATUSB_IP15 7
358#define STATUSF_IP15 (_ULCAST_(1) << 7)
359#define ST0_CH 0x00040000
360#define ST0_NMI 0x00080000
361#define ST0_SR 0x00100000
362#define ST0_TS 0x00200000
363#define ST0_BEV 0x00400000
364#define ST0_RE 0x02000000
365#define ST0_FR 0x04000000
366#define ST0_CU 0xf0000000
367#define ST0_CU0 0x10000000
368#define ST0_CU1 0x20000000
369#define ST0_CU2 0x40000000
370#define ST0_CU3 0x80000000
371#define ST0_XX 0x80000000 /* MIPS IV naming */
372
373/*
374 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
375 */
376#define INTCTLB_IPFDC 23
377#define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
378#define INTCTLB_IPPCI 26
379#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
380#define INTCTLB_IPTI 29
381#define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
382
383/*
384 * Bitfields and bit numbers in the coprocessor 0 cause register.
385 *
386 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
387 */
388#define CAUSEB_EXCCODE 2
389#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
390#define CAUSEB_IP 8
391#define CAUSEF_IP (_ULCAST_(255) << 8)
392#define CAUSEB_IP0 8
393#define CAUSEF_IP0 (_ULCAST_(1) << 8)
394#define CAUSEB_IP1 9
395#define CAUSEF_IP1 (_ULCAST_(1) << 9)
396#define CAUSEB_IP2 10
397#define CAUSEF_IP2 (_ULCAST_(1) << 10)
398#define CAUSEB_IP3 11
399#define CAUSEF_IP3 (_ULCAST_(1) << 11)
400#define CAUSEB_IP4 12
401#define CAUSEF_IP4 (_ULCAST_(1) << 12)
402#define CAUSEB_IP5 13
403#define CAUSEF_IP5 (_ULCAST_(1) << 13)
404#define CAUSEB_IP6 14
405#define CAUSEF_IP6 (_ULCAST_(1) << 14)
406#define CAUSEB_IP7 15
407#define CAUSEF_IP7 (_ULCAST_(1) << 15)
408#define CAUSEB_FDCI 21
409#define CAUSEF_FDCI (_ULCAST_(1) << 21)
410#define CAUSEB_WP 22
411#define CAUSEF_WP (_ULCAST_(1) << 22)
412#define CAUSEB_IV 23
413#define CAUSEF_IV (_ULCAST_(1) << 23)
414#define CAUSEB_PCI 26
415#define CAUSEF_PCI (_ULCAST_(1) << 26)
416#define CAUSEB_DC 27
417#define CAUSEF_DC (_ULCAST_(1) << 27)
418#define CAUSEB_CE 28
419#define CAUSEF_CE (_ULCAST_(3) << 28)
420#define CAUSEB_TI 30
421#define CAUSEF_TI (_ULCAST_(1) << 30)
422#define CAUSEB_BD 31
423#define CAUSEF_BD (_ULCAST_(1) << 31)
424
425/*
426 * Cause.ExcCode trap codes.
427 */
428#define EXCCODE_INT 0 /* Interrupt pending */
429#define EXCCODE_MOD 1 /* TLB modified fault */
430#define EXCCODE_TLBL 2 /* TLB miss on load or ifetch */
431#define EXCCODE_TLBS 3 /* TLB miss on a store */
432#define EXCCODE_ADEL 4 /* Address error on a load or ifetch */
433#define EXCCODE_ADES 5 /* Address error on a store */
434#define EXCCODE_IBE 6 /* Bus error on an ifetch */
435#define EXCCODE_DBE 7 /* Bus error on a load or store */
436#define EXCCODE_SYS 8 /* System call */
437#define EXCCODE_BP 9 /* Breakpoint */
438#define EXCCODE_RI 10 /* Reserved instruction exception */
439#define EXCCODE_CPU 11 /* Coprocessor unusable */
440#define EXCCODE_OV 12 /* Arithmetic overflow */
441#define EXCCODE_TR 13 /* Trap instruction */
442#define EXCCODE_MSAFPE 14 /* MSA floating point exception */
443#define EXCCODE_FPE 15 /* Floating point exception */
444#define EXCCODE_TLBRI 19 /* TLB Read-Inhibit exception */
445#define EXCCODE_TLBXI 20 /* TLB Execution-Inhibit exception */
446#define EXCCODE_MSADIS 21 /* MSA disabled exception */
447#define EXCCODE_MDMX 22 /* MDMX unusable exception */
448#define EXCCODE_WATCH 23 /* Watch address reference */
449#define EXCCODE_MCHECK 24 /* Machine check */
450#define EXCCODE_THREAD 25 /* Thread exceptions (MT) */
451#define EXCCODE_DSPDIS 26 /* DSP disabled exception */
452#define EXCCODE_GE 27 /* Virtualized guest exception (VZ) */
453
454/* Implementation specific trap codes used by MIPS cores */
455#define MIPS_EXCCODE_TLBPAR 16 /* TLB parity error exception */
456
457/*
458 * Bits in the coprocessor 0 config register.
459 */
460/* Generic bits. */
461#define CONF_CM_CACHABLE_NO_WA 0
462#define CONF_CM_CACHABLE_WA 1
463#define CONF_CM_UNCACHED 2
464#define CONF_CM_CACHABLE_NONCOHERENT 3
465#define CONF_CM_CACHABLE_CE 4
466#define CONF_CM_CACHABLE_COW 5
467#define CONF_CM_CACHABLE_CUW 6
468#define CONF_CM_CACHABLE_ACCELERATED 7
469#define CONF_CM_CMASK 7
470#define CONF_BE (_ULCAST_(1) << 15)
471
472/* Bits common to various processors. */
473#define CONF_CU (_ULCAST_(1) << 3)
474#define CONF_DB (_ULCAST_(1) << 4)
475#define CONF_IB (_ULCAST_(1) << 5)
476#define CONF_DC (_ULCAST_(7) << 6)
477#define CONF_IC (_ULCAST_(7) << 9)
478#define CONF_EB (_ULCAST_(1) << 13)
479#define CONF_EM (_ULCAST_(1) << 14)
480#define CONF_SM (_ULCAST_(1) << 16)
481#define CONF_SC (_ULCAST_(1) << 17)
482#define CONF_EW (_ULCAST_(3) << 18)
483#define CONF_EP (_ULCAST_(15)<< 24)
484#define CONF_EC (_ULCAST_(7) << 28)
485#define CONF_CM (_ULCAST_(1) << 31)
486
487/* Bits specific to the R4xx0. */
488#define R4K_CONF_SW (_ULCAST_(1) << 20)
489#define R4K_CONF_SS (_ULCAST_(1) << 21)
490#define R4K_CONF_SB (_ULCAST_(3) << 22)
491
492/* Bits specific to the R5000. */
493#define R5K_CONF_SE (_ULCAST_(1) << 12)
494#define R5K_CONF_SS (_ULCAST_(3) << 20)
495
496/* Bits specific to the RM7000. */
497#define RM7K_CONF_SE (_ULCAST_(1) << 3)
498#define RM7K_CONF_TE (_ULCAST_(1) << 12)
499#define RM7K_CONF_CLK (_ULCAST_(1) << 16)
500#define RM7K_CONF_TC (_ULCAST_(1) << 17)
501#define RM7K_CONF_SI (_ULCAST_(3) << 20)
502#define RM7K_CONF_SC (_ULCAST_(1) << 31)
503
504/* Bits specific to the R10000. */
505#define R10K_CONF_DN (_ULCAST_(3) << 3)
506#define R10K_CONF_CT (_ULCAST_(1) << 5)
507#define R10K_CONF_PE (_ULCAST_(1) << 6)
508#define R10K_CONF_PM (_ULCAST_(3) << 7)
509#define R10K_CONF_EC (_ULCAST_(15)<< 9)
510#define R10K_CONF_SB (_ULCAST_(1) << 13)
511#define R10K_CONF_SK (_ULCAST_(1) << 14)
512#define R10K_CONF_SS (_ULCAST_(7) << 16)
513#define R10K_CONF_SC (_ULCAST_(7) << 19)
514#define R10K_CONF_DC (_ULCAST_(7) << 26)
515#define R10K_CONF_IC (_ULCAST_(7) << 29)
516
517/* Bits specific to the VR41xx. */
518#define VR41_CONF_CS (_ULCAST_(1) << 12)
519#define VR41_CONF_P4K (_ULCAST_(1) << 13)
520#define VR41_CONF_BP (_ULCAST_(1) << 16)
521#define VR41_CONF_M16 (_ULCAST_(1) << 20)
522#define VR41_CONF_AD (_ULCAST_(1) << 23)
523
524/* Bits specific to the R30xx. */
525#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
526#define R30XX_CONF_REV (_ULCAST_(1) << 22)
527#define R30XX_CONF_AC (_ULCAST_(1) << 23)
528#define R30XX_CONF_RF (_ULCAST_(1) << 24)
529#define R30XX_CONF_HALT (_ULCAST_(1) << 25)
530#define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
531#define R30XX_CONF_DBR (_ULCAST_(1) << 29)
532#define R30XX_CONF_SB (_ULCAST_(1) << 30)
533#define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
534
535/* Bits specific to the TX49. */
536#define TX49_CONF_DC (_ULCAST_(1) << 16)
537#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
538#define TX49_CONF_HALT (_ULCAST_(1) << 18)
539#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
540
541/* Bits specific to the MIPS32/64 PRA. */
542#define MIPS_CONF_VI (_ULCAST_(1) << 3)
543#define MIPS_CONF_MT (_ULCAST_(7) << 7)
544#define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7)
545#define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
546#define MIPS_CONF_AR (_ULCAST_(7) << 10)
547#define MIPS_CONF_AT (_ULCAST_(3) << 13)
548#define MIPS_CONF_M (_ULCAST_(1) << 31)
549
550/*
551 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
552 */
553#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
554#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
555#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
556#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
557#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
558#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
559#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
560#define MIPS_CONF1_DA_SHF 7
561#define MIPS_CONF1_DA_SZ 3
562#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
563#define MIPS_CONF1_DL_SHF 10
564#define MIPS_CONF1_DL_SZ 3
565#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
566#define MIPS_CONF1_DS_SHF 13
567#define MIPS_CONF1_DS_SZ 3
568#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
569#define MIPS_CONF1_IA_SHF 16
570#define MIPS_CONF1_IA_SZ 3
571#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
572#define MIPS_CONF1_IL_SHF 19
573#define MIPS_CONF1_IL_SZ 3
574#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
575#define MIPS_CONF1_IS_SHF 22
576#define MIPS_CONF1_IS_SZ 3
577#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
578#define MIPS_CONF1_TLBS_SHIFT (25)
579#define MIPS_CONF1_TLBS_SIZE (6)
580#define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
581
582#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
583#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
584#define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
585#define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
586#define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
587#define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
588#define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
589#define MIPS_CONF2_TU (_ULCAST_(7) << 28)
590
591#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
592#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
593#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
594#define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
595#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
596#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
597#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
598#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
599#define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
600#define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
601#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
602#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
603#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
604#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
605#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
606#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
607#define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
608#define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
609#define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
610#define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
611#define MIPS_CONF3_PW (_ULCAST_(1) << 24)
612#define MIPS_CONF3_SC (_ULCAST_(1) << 25)
613#define MIPS_CONF3_BI (_ULCAST_(1) << 26)
614#define MIPS_CONF3_BP (_ULCAST_(1) << 27)
615#define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
616#define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
617#define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
618
619#define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
620#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
621#define MIPS_CONF4_FTLBSETS_SHIFT (0)
622#define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
623#define MIPS_CONF4_FTLBWAYS_SHIFT (4)
624#define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
625#define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
626/* bits 10:8 in FTLB-only configurations */
627#define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
628/* bits 12:8 in VTLB-FTLB only configurations */
629#define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
630#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
631#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
632#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
633#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
634#define MIPS_CONF4_KSCREXIST_SHIFT (16)
635#define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << MIPS_CONF4_KSCREXIST_SHIFT)
636#define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
637#define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
638#define MIPS_CONF4_AE (_ULCAST_(1) << 28)
639#define MIPS_CONF4_IE (_ULCAST_(3) << 29)
640#define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
641
642#define MIPS_CONF5_NF (_ULCAST_(1) << 0)
643#define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
644#define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
645#define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
646#define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
647#define MIPS_CONF5_VP (_ULCAST_(1) << 7)
648#define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
649#define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
650#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
651#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
652#define MIPS_CONF5_CV (_ULCAST_(1) << 29)
653#define MIPS_CONF5_K (_ULCAST_(1) << 30)
654
655#define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
656/* proAptiv FTLB on/off bit */
657#define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
658/* Loongson-3 FTLB on/off bit */
659#define MIPS_CONF6_FTLBDIS (_ULCAST_(1) << 22)
660/* FTLB probability bits */
661#define MIPS_CONF6_FTLBP_SHIFT (16)
662
663#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
664
665#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
666
667#define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
668#define MIPS_CONF7_AR (_ULCAST_(1) << 16)
669
670/* WatchLo* register definitions */
671#define MIPS_WATCHLO_IRW (_ULCAST_(0x7) << 0)
672
673/* WatchHi* register definitions */
674#define MIPS_WATCHHI_M (_ULCAST_(1) << 31)
675#define MIPS_WATCHHI_G (_ULCAST_(1) << 30)
676#define MIPS_WATCHHI_WM (_ULCAST_(0x3) << 28)
677#define MIPS_WATCHHI_WM_R_RVA (_ULCAST_(0) << 28)
678#define MIPS_WATCHHI_WM_R_GPA (_ULCAST_(1) << 28)
679#define MIPS_WATCHHI_WM_G_GVA (_ULCAST_(2) << 28)
680#define MIPS_WATCHHI_EAS (_ULCAST_(0x3) << 24)
681#define MIPS_WATCHHI_ASID (_ULCAST_(0xff) << 16)
682#define MIPS_WATCHHI_MASK (_ULCAST_(0x1ff) << 3)
683#define MIPS_WATCHHI_I (_ULCAST_(1) << 2)
684#define MIPS_WATCHHI_R (_ULCAST_(1) << 1)
685#define MIPS_WATCHHI_W (_ULCAST_(1) << 0)
686#define MIPS_WATCHHI_IRW (_ULCAST_(0x7) << 0)
687
688/* MAAR bit definitions */
689#define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
690#define MIPS_MAAR_ADDR_SHIFT 12
691#define MIPS_MAAR_S (_ULCAST_(1) << 1)
692#define MIPS_MAAR_V (_ULCAST_(1) << 0)
693
694/* EBase bit definitions */
695#define MIPS_EBASE_CPUNUM_SHIFT 0
696#define MIPS_EBASE_CPUNUM (_ULCAST_(0x3ff) << 0)
697#define MIPS_EBASE_WG_SHIFT 11
698#define MIPS_EBASE_WG (_ULCAST_(1) << 11)
699#define MIPS_EBASE_BASE_SHIFT 12
700#define MIPS_EBASE_BASE (~_ULCAST_((1 << MIPS_EBASE_BASE_SHIFT) - 1))
701
702/* CMGCRBase bit definitions */
703#define MIPS_CMGCRB_BASE 11
704#define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
705
706/*
707 * Bits in the MIPS32 Memory Segmentation registers.
708 */
709#define MIPS_SEGCFG_PA_SHIFT 9
710#define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
711#define MIPS_SEGCFG_AM_SHIFT 4
712#define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
713#define MIPS_SEGCFG_EU_SHIFT 3
714#define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
715#define MIPS_SEGCFG_C_SHIFT 0
716#define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
717
718#define MIPS_SEGCFG_UUSK _ULCAST_(7)
719#define MIPS_SEGCFG_USK _ULCAST_(5)
720#define MIPS_SEGCFG_MUSUK _ULCAST_(4)
721#define MIPS_SEGCFG_MUSK _ULCAST_(3)
722#define MIPS_SEGCFG_MSK _ULCAST_(2)
723#define MIPS_SEGCFG_MK _ULCAST_(1)
724#define MIPS_SEGCFG_UK _ULCAST_(0)
725
726#define MIPS_PWFIELD_GDI_SHIFT 24
727#define MIPS_PWFIELD_GDI_MASK 0x3f000000
728#define MIPS_PWFIELD_UDI_SHIFT 18
729#define MIPS_PWFIELD_UDI_MASK 0x00fc0000
730#define MIPS_PWFIELD_MDI_SHIFT 12
731#define MIPS_PWFIELD_MDI_MASK 0x0003f000
732#define MIPS_PWFIELD_PTI_SHIFT 6
733#define MIPS_PWFIELD_PTI_MASK 0x00000fc0
734#define MIPS_PWFIELD_PTEI_SHIFT 0
735#define MIPS_PWFIELD_PTEI_MASK 0x0000003f
736
737#define MIPS_PWSIZE_PS_SHIFT 30
738#define MIPS_PWSIZE_PS_MASK 0x40000000
739#define MIPS_PWSIZE_GDW_SHIFT 24
740#define MIPS_PWSIZE_GDW_MASK 0x3f000000
741#define MIPS_PWSIZE_UDW_SHIFT 18
742#define MIPS_PWSIZE_UDW_MASK 0x00fc0000
743#define MIPS_PWSIZE_MDW_SHIFT 12
744#define MIPS_PWSIZE_MDW_MASK 0x0003f000
745#define MIPS_PWSIZE_PTW_SHIFT 6
746#define MIPS_PWSIZE_PTW_MASK 0x00000fc0
747#define MIPS_PWSIZE_PTEW_SHIFT 0
748#define MIPS_PWSIZE_PTEW_MASK 0x0000003f
749
750#define MIPS_PWCTL_PWEN_SHIFT 31
751#define MIPS_PWCTL_PWEN_MASK 0x80000000
752#define MIPS_PWCTL_XK_SHIFT 28
753#define MIPS_PWCTL_XK_MASK 0x10000000
754#define MIPS_PWCTL_XS_SHIFT 27
755#define MIPS_PWCTL_XS_MASK 0x08000000
756#define MIPS_PWCTL_XU_SHIFT 26
757#define MIPS_PWCTL_XU_MASK 0x04000000
758#define MIPS_PWCTL_DPH_SHIFT 7
759#define MIPS_PWCTL_DPH_MASK 0x00000080
760#define MIPS_PWCTL_HUGEPG_SHIFT 6
761#define MIPS_PWCTL_HUGEPG_MASK 0x00000060
762#define MIPS_PWCTL_PSN_SHIFT 0
763#define MIPS_PWCTL_PSN_MASK 0x0000003f
764
765/* GuestCtl0 fields */
766#define MIPS_GCTL0_GM_SHIFT 31
767#define MIPS_GCTL0_GM (_ULCAST_(1) << MIPS_GCTL0_GM_SHIFT)
768#define MIPS_GCTL0_RI_SHIFT 30
769#define MIPS_GCTL0_RI (_ULCAST_(1) << MIPS_GCTL0_RI_SHIFT)
770#define MIPS_GCTL0_MC_SHIFT 29
771#define MIPS_GCTL0_MC (_ULCAST_(1) << MIPS_GCTL0_MC_SHIFT)
772#define MIPS_GCTL0_CP0_SHIFT 28
773#define MIPS_GCTL0_CP0 (_ULCAST_(1) << MIPS_GCTL0_CP0_SHIFT)
774#define MIPS_GCTL0_AT_SHIFT 26
775#define MIPS_GCTL0_AT (_ULCAST_(0x3) << MIPS_GCTL0_AT_SHIFT)
776#define MIPS_GCTL0_GT_SHIFT 25
777#define MIPS_GCTL0_GT (_ULCAST_(1) << MIPS_GCTL0_GT_SHIFT)
778#define MIPS_GCTL0_CG_SHIFT 24
779#define MIPS_GCTL0_CG (_ULCAST_(1) << MIPS_GCTL0_CG_SHIFT)
780#define MIPS_GCTL0_CF_SHIFT 23
781#define MIPS_GCTL0_CF (_ULCAST_(1) << MIPS_GCTL0_CF_SHIFT)
782#define MIPS_GCTL0_G1_SHIFT 22
783#define MIPS_GCTL0_G1 (_ULCAST_(1) << MIPS_GCTL0_G1_SHIFT)
784#define MIPS_GCTL0_G0E_SHIFT 19
785#define MIPS_GCTL0_G0E (_ULCAST_(1) << MIPS_GCTL0_G0E_SHIFT)
786#define MIPS_GCTL0_PT_SHIFT 18
787#define MIPS_GCTL0_PT (_ULCAST_(1) << MIPS_GCTL0_PT_SHIFT)
788#define MIPS_GCTL0_RAD_SHIFT 9
789#define MIPS_GCTL0_RAD (_ULCAST_(1) << MIPS_GCTL0_RAD_SHIFT)
790#define MIPS_GCTL0_DRG_SHIFT 8
791#define MIPS_GCTL0_DRG (_ULCAST_(1) << MIPS_GCTL0_DRG_SHIFT)
792#define MIPS_GCTL0_G2_SHIFT 7
793#define MIPS_GCTL0_G2 (_ULCAST_(1) << MIPS_GCTL0_G2_SHIFT)
794#define MIPS_GCTL0_GEXC_SHIFT 2
795#define MIPS_GCTL0_GEXC (_ULCAST_(0x1f) << MIPS_GCTL0_GEXC_SHIFT)
796#define MIPS_GCTL0_SFC2_SHIFT 1
797#define MIPS_GCTL0_SFC2 (_ULCAST_(1) << MIPS_GCTL0_SFC2_SHIFT)
798#define MIPS_GCTL0_SFC1_SHIFT 0
799#define MIPS_GCTL0_SFC1 (_ULCAST_(1) << MIPS_GCTL0_SFC1_SHIFT)
800
801/* GuestCtl0.AT Guest address translation control */
802#define MIPS_GCTL0_AT_ROOT 1 /* Guest MMU under Root control */
803#define MIPS_GCTL0_AT_GUEST 3 /* Guest MMU under Guest control */
804
805/* GuestCtl0.GExcCode Hypervisor exception cause codes */
806#define MIPS_GCTL0_GEXC_GPSI 0 /* Guest Privileged Sensitive Instruction */
807#define MIPS_GCTL0_GEXC_GSFC 1 /* Guest Software Field Change */
808#define MIPS_GCTL0_GEXC_HC 2 /* Hypercall */
809#define MIPS_GCTL0_GEXC_GRR 3 /* Guest Reserved Instruction Redirect */
810#define MIPS_GCTL0_GEXC_GVA 8 /* Guest Virtual Address available */
811#define MIPS_GCTL0_GEXC_GHFC 9 /* Guest Hardware Field Change */
812#define MIPS_GCTL0_GEXC_GPA 10 /* Guest Physical Address available */
813
814/* GuestCtl0Ext fields */
815#define MIPS_GCTL0EXT_RPW_SHIFT 8
816#define MIPS_GCTL0EXT_RPW (_ULCAST_(0x3) << MIPS_GCTL0EXT_RPW_SHIFT)
817#define MIPS_GCTL0EXT_NCC_SHIFT 6
818#define MIPS_GCTL0EXT_NCC (_ULCAST_(0x3) << MIPS_GCTL0EXT_NCC_SHIFT)
819#define MIPS_GCTL0EXT_CGI_SHIFT 4
820#define MIPS_GCTL0EXT_CGI (_ULCAST_(1) << MIPS_GCTL0EXT_CGI_SHIFT)
821#define MIPS_GCTL0EXT_FCD_SHIFT 3
822#define MIPS_GCTL0EXT_FCD (_ULCAST_(1) << MIPS_GCTL0EXT_FCD_SHIFT)
823#define MIPS_GCTL0EXT_OG_SHIFT 2
824#define MIPS_GCTL0EXT_OG (_ULCAST_(1) << MIPS_GCTL0EXT_OG_SHIFT)
825#define MIPS_GCTL0EXT_BG_SHIFT 1
826#define MIPS_GCTL0EXT_BG (_ULCAST_(1) << MIPS_GCTL0EXT_BG_SHIFT)
827#define MIPS_GCTL0EXT_MG_SHIFT 0
828#define MIPS_GCTL0EXT_MG (_ULCAST_(1) << MIPS_GCTL0EXT_MG_SHIFT)
829
830/* GuestCtl0Ext.RPW Root page walk configuration */
831#define MIPS_GCTL0EXT_RPW_BOTH 0 /* Root PW for GPA->RPA and RVA->RPA */
832#define MIPS_GCTL0EXT_RPW_GPA 2 /* Root PW for GPA->RPA */
833#define MIPS_GCTL0EXT_RPW_RVA 3 /* Root PW for RVA->RPA */
834
835/* GuestCtl0Ext.NCC Nested cache coherency attributes */
836#define MIPS_GCTL0EXT_NCC_IND 0 /* Guest CCA independent of Root CCA */
837#define MIPS_GCTL0EXT_NCC_MOD 1 /* Guest CCA modified by Root CCA */
838
839/* GuestCtl1 fields */
840#define MIPS_GCTL1_ID_SHIFT 0
841#define MIPS_GCTL1_ID_WIDTH 8
842#define MIPS_GCTL1_ID (_ULCAST_(0xff) << MIPS_GCTL1_ID_SHIFT)
843#define MIPS_GCTL1_RID_SHIFT 16
844#define MIPS_GCTL1_RID_WIDTH 8
845#define MIPS_GCTL1_RID (_ULCAST_(0xff) << MIPS_GCTL1_RID_SHIFT)
846#define MIPS_GCTL1_EID_SHIFT 24
847#define MIPS_GCTL1_EID_WIDTH 8
848#define MIPS_GCTL1_EID (_ULCAST_(0xff) << MIPS_GCTL1_EID_SHIFT)
849
850/* GuestID reserved for root context */
851#define MIPS_GCTL1_ROOT_GUESTID 0
852
853/* CDMMBase register bit definitions */
854#define MIPS_CDMMBASE_SIZE_SHIFT 0
855#define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
856#define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
857#define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
858#define MIPS_CDMMBASE_ADDR_SHIFT 11
859#define MIPS_CDMMBASE_ADDR_START 15
860
861/* RDHWR register numbers */
862#define MIPS_HWR_CPUNUM 0 /* CPU number */
863#define MIPS_HWR_SYNCISTEP 1 /* SYNCI step size */
864#define MIPS_HWR_CC 2 /* Cycle counter */
865#define MIPS_HWR_CCRES 3 /* Cycle counter resolution */
866#define MIPS_HWR_ULR 29 /* UserLocal */
867#define MIPS_HWR_IMPL1 30 /* Implementation dependent */
868#define MIPS_HWR_IMPL2 31 /* Implementation dependent */
869
870/* Bits in HWREna register */
871#define MIPS_HWRENA_CPUNUM (_ULCAST_(1) << MIPS_HWR_CPUNUM)
872#define MIPS_HWRENA_SYNCISTEP (_ULCAST_(1) << MIPS_HWR_SYNCISTEP)
873#define MIPS_HWRENA_CC (_ULCAST_(1) << MIPS_HWR_CC)
874#define MIPS_HWRENA_CCRES (_ULCAST_(1) << MIPS_HWR_CCRES)
875#define MIPS_HWRENA_ULR (_ULCAST_(1) << MIPS_HWR_ULR)
876#define MIPS_HWRENA_IMPL1 (_ULCAST_(1) << MIPS_HWR_IMPL1)
877#define MIPS_HWRENA_IMPL2 (_ULCAST_(1) << MIPS_HWR_IMPL2)
878
879/*
880 * Bitfields in the TX39 family CP0 Configuration Register 3
881 */
882#define TX39_CONF_ICS_SHIFT 19
883#define TX39_CONF_ICS_MASK 0x00380000
884#define TX39_CONF_ICS_1KB 0x00000000
885#define TX39_CONF_ICS_2KB 0x00080000
886#define TX39_CONF_ICS_4KB 0x00100000
887#define TX39_CONF_ICS_8KB 0x00180000
888#define TX39_CONF_ICS_16KB 0x00200000
889
890#define TX39_CONF_DCS_SHIFT 16
891#define TX39_CONF_DCS_MASK 0x00070000
892#define TX39_CONF_DCS_1KB 0x00000000
893#define TX39_CONF_DCS_2KB 0x00010000
894#define TX39_CONF_DCS_4KB 0x00020000
895#define TX39_CONF_DCS_8KB 0x00030000
896#define TX39_CONF_DCS_16KB 0x00040000
897
898#define TX39_CONF_CWFON 0x00004000
899#define TX39_CONF_WBON 0x00002000
900#define TX39_CONF_RF_SHIFT 10
901#define TX39_CONF_RF_MASK 0x00000c00
902#define TX39_CONF_DOZE 0x00000200
903#define TX39_CONF_HALT 0x00000100
904#define TX39_CONF_LOCK 0x00000080
905#define TX39_CONF_ICE 0x00000020
906#define TX39_CONF_DCE 0x00000010
907#define TX39_CONF_IRSIZE_SHIFT 2
908#define TX39_CONF_IRSIZE_MASK 0x0000000c
909#define TX39_CONF_DRSIZE_SHIFT 0
910#define TX39_CONF_DRSIZE_MASK 0x00000003
911
912/*
913 * Interesting Bits in the R10K CP0 Branch Diagnostic Register
914 */
915/* Disable Branch Target Address Cache */
916#define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27)
917/* Enable Branch Prediction Global History */
918#define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26)
919/* Disable Branch Return Cache */
920#define R10K_DIAG_D_BRC (_ULCAST_(1) << 22)
921
922/* Flush ITLB */
923#define LOONGSON_DIAG_ITLB (_ULCAST_(1) << 2)
924/* Flush DTLB */
925#define LOONGSON_DIAG_DTLB (_ULCAST_(1) << 3)
926/* Flush VTLB */
927#define LOONGSON_DIAG_VTLB (_ULCAST_(1) << 12)
928/* Flush FTLB */
929#define LOONGSON_DIAG_FTLB (_ULCAST_(1) << 13)
930
931/*
932 * Coprocessor 1 (FPU) register names
933 */
934#define CP1_REVISION $0
935#define CP1_UFR $1
936#define CP1_UNFR $4
937#define CP1_FCCR $25
938#define CP1_FEXR $26
939#define CP1_FENR $28
940#define CP1_STATUS $31
941
942
943/*
944 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
945 */
946#define MIPS_FPIR_S (_ULCAST_(1) << 16)
947#define MIPS_FPIR_D (_ULCAST_(1) << 17)
948#define MIPS_FPIR_PS (_ULCAST_(1) << 18)
949#define MIPS_FPIR_3D (_ULCAST_(1) << 19)
950#define MIPS_FPIR_W (_ULCAST_(1) << 20)
951#define MIPS_FPIR_L (_ULCAST_(1) << 21)
952#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
953#define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
954#define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
955#define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
956
957/*
958 * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
959 */
960#define MIPS_FCCR_CONDX_S 0
961#define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
962#define MIPS_FCCR_COND0_S 0
963#define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
964#define MIPS_FCCR_COND1_S 1
965#define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
966#define MIPS_FCCR_COND2_S 2
967#define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
968#define MIPS_FCCR_COND3_S 3
969#define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
970#define MIPS_FCCR_COND4_S 4
971#define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
972#define MIPS_FCCR_COND5_S 5
973#define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
974#define MIPS_FCCR_COND6_S 6
975#define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
976#define MIPS_FCCR_COND7_S 7
977#define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
978
979/*
980 * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
981 */
982#define MIPS_FENR_FS_S 2
983#define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
984
985/*
986 * FPU Status Register Values
987 */
988#define FPU_CSR_COND_S 23 /* $fcc0 */
989#define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
990
991#define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
992#define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
993
994#define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
995#define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
996#define FPU_CSR_COND1_S 25 /* $fcc1 */
997#define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
998#define FPU_CSR_COND2_S 26 /* $fcc2 */
999#define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
1000#define FPU_CSR_COND3_S 27 /* $fcc3 */
1001#define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
1002#define FPU_CSR_COND4_S 28 /* $fcc4 */
1003#define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
1004#define FPU_CSR_COND5_S 29 /* $fcc5 */
1005#define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
1006#define FPU_CSR_COND6_S 30 /* $fcc6 */
1007#define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
1008#define FPU_CSR_COND7_S 31 /* $fcc7 */
1009#define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
1010
1011/*
1012 * Bits 22:20 of the FPU Status Register will be read as 0,
1013 * and should be written as zero.
1014 */
1015#define FPU_CSR_RSVD (_ULCAST_(7) << 20)
1016
1017#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
1018#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
1019
1020/*
1021 * X the exception cause indicator
1022 * E the exception enable
1023 * S the sticky/flag bit
1024*/
1025#define FPU_CSR_ALL_X 0x0003f000
1026#define FPU_CSR_UNI_X 0x00020000
1027#define FPU_CSR_INV_X 0x00010000
1028#define FPU_CSR_DIV_X 0x00008000
1029#define FPU_CSR_OVF_X 0x00004000
1030#define FPU_CSR_UDF_X 0x00002000
1031#define FPU_CSR_INE_X 0x00001000
1032
1033#define FPU_CSR_ALL_E 0x00000f80
1034#define FPU_CSR_INV_E 0x00000800
1035#define FPU_CSR_DIV_E 0x00000400
1036#define FPU_CSR_OVF_E 0x00000200
1037#define FPU_CSR_UDF_E 0x00000100
1038#define FPU_CSR_INE_E 0x00000080
1039
1040#define FPU_CSR_ALL_S 0x0000007c
1041#define FPU_CSR_INV_S 0x00000040
1042#define FPU_CSR_DIV_S 0x00000020
1043#define FPU_CSR_OVF_S 0x00000010
1044#define FPU_CSR_UDF_S 0x00000008
1045#define FPU_CSR_INE_S 0x00000004
1046
1047/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
1048#define FPU_CSR_RM 0x00000003
1049#define FPU_CSR_RN 0x0 /* nearest */
1050#define FPU_CSR_RZ 0x1 /* towards zero */
1051#define FPU_CSR_RU 0x2 /* towards +Infinity */
1052#define FPU_CSR_RD 0x3 /* towards -Infinity */
1053
1054
1055#ifndef __ASSEMBLY__
1056
1057/*
1058 * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
1059 */
1060#if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
1061 defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
1062#define get_isa16_mode(x) ((x) & 0x1)
1063#define msk_isa16_mode(x) ((x) & ~0x1)
1064#define set_isa16_mode(x) do { (x) |= 0x1; } while(0)
1065#else
1066#define get_isa16_mode(x) 0
1067#define msk_isa16_mode(x) (x)
1068#define set_isa16_mode(x) do { } while(0)
1069#endif
1070
1071/*
1072 * microMIPS instructions can be 16-bit or 32-bit in length. This
1073 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
1074 */
1075static inline int mm_insn_16bit(u16 insn)
1076{
1077 u16 opcode = (insn >> 10) & 0x7;
1078
1079 return (opcode >= 1 && opcode <= 3) ? 1 : 0;
1080}
1081
1082/*
1083 * Helper macros for generating raw instruction encodings in inline asm.
1084 */
1085#ifdef CONFIG_CPU_MICROMIPS
1086#define _ASM_INSN16_IF_MM(_enc) \
1087 ".insn\n\t" \
1088 ".hword (" #_enc ")\n\t"
1089#define _ASM_INSN32_IF_MM(_enc) \
1090 ".insn\n\t" \
1091 ".hword ((" #_enc ") >> 16)\n\t" \
1092 ".hword ((" #_enc ") & 0xffff)\n\t"
1093#else
1094#define _ASM_INSN_IF_MIPS(_enc) \
1095 ".insn\n\t" \
1096 ".word (" #_enc ")\n\t"
1097#endif
1098
1099#ifndef _ASM_INSN16_IF_MM
1100#define _ASM_INSN16_IF_MM(_enc)
1101#endif
1102#ifndef _ASM_INSN32_IF_MM
1103#define _ASM_INSN32_IF_MM(_enc)
1104#endif
1105#ifndef _ASM_INSN_IF_MIPS
1106#define _ASM_INSN_IF_MIPS(_enc)
1107#endif
1108
1109/*
1110 * TLB Invalidate Flush
1111 */
1112static inline void tlbinvf(void)
1113{
1114 __asm__ __volatile__(
1115 ".set push\n\t"
1116 ".set noreorder\n\t"
1117 "# tlbinvf\n\t"
1118 _ASM_INSN_IF_MIPS(0x42000004)
1119 _ASM_INSN32_IF_MM(0x0000537c)
1120 ".set pop");
1121}
1122
1123
1124/*
1125 * Functions to access the R10000 performance counters. These are basically
1126 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
1127 * performance counter number encoded into bits 1 ... 5 of the instruction.
1128 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
1129 * disassembler these will look like an access to sel 0 or 1.
1130 */
1131#define read_r10k_perf_cntr(counter) \
1132({ \
1133 unsigned int __res; \
1134 __asm__ __volatile__( \
1135 "mfpc\t%0, %1" \
1136 : "=r" (__res) \
1137 : "i" (counter)); \
1138 \
1139 __res; \
1140})
1141
1142#define write_r10k_perf_cntr(counter,val) \
1143do { \
1144 __asm__ __volatile__( \
1145 "mtpc\t%0, %1" \
1146 : \
1147 : "r" (val), "i" (counter)); \
1148} while (0)
1149
1150#define read_r10k_perf_event(counter) \
1151({ \
1152 unsigned int __res; \
1153 __asm__ __volatile__( \
1154 "mfps\t%0, %1" \
1155 : "=r" (__res) \
1156 : "i" (counter)); \
1157 \
1158 __res; \
1159})
1160
1161#define write_r10k_perf_cntl(counter,val) \
1162do { \
1163 __asm__ __volatile__( \
1164 "mtps\t%0, %1" \
1165 : \
1166 : "r" (val), "i" (counter)); \
1167} while (0)
1168
1169
1170/*
1171 * Macros to access the system control coprocessor
1172 */
1173
1174#define __read_32bit_c0_register(source, sel) \
1175({ unsigned int __res; \
1176 if (sel == 0) \
1177 __asm__ __volatile__( \
1178 "mfc0\t%0, " #source "\n\t" \
1179 : "=r" (__res)); \
1180 else \
1181 __asm__ __volatile__( \
1182 ".set\tmips32\n\t" \
1183 "mfc0\t%0, " #source ", " #sel "\n\t" \
1184 ".set\tmips0\n\t" \
1185 : "=r" (__res)); \
1186 __res; \
1187})
1188
1189#define __read_64bit_c0_register(source, sel) \
1190({ unsigned long long __res; \
1191 if (sizeof(unsigned long) == 4) \
1192 __res = __read_64bit_c0_split(source, sel); \
1193 else if (sel == 0) \
1194 __asm__ __volatile__( \
1195 ".set\tmips3\n\t" \
1196 "dmfc0\t%0, " #source "\n\t" \
1197 ".set\tmips0" \
1198 : "=r" (__res)); \
1199 else \
1200 __asm__ __volatile__( \
1201 ".set\tmips64\n\t" \
1202 "dmfc0\t%0, " #source ", " #sel "\n\t" \
1203 ".set\tmips0" \
1204 : "=r" (__res)); \
1205 __res; \
1206})
1207
1208#define __write_32bit_c0_register(register, sel, value) \
1209do { \
1210 if (sel == 0) \
1211 __asm__ __volatile__( \
1212 "mtc0\t%z0, " #register "\n\t" \
1213 : : "Jr" ((unsigned int)(value))); \
1214 else \
1215 __asm__ __volatile__( \
1216 ".set\tmips32\n\t" \
1217 "mtc0\t%z0, " #register ", " #sel "\n\t" \
1218 ".set\tmips0" \
1219 : : "Jr" ((unsigned int)(value))); \
1220} while (0)
1221
1222#define __write_64bit_c0_register(register, sel, value) \
1223do { \
1224 if (sizeof(unsigned long) == 4) \
1225 __write_64bit_c0_split(register, sel, value); \
1226 else if (sel == 0) \
1227 __asm__ __volatile__( \
1228 ".set\tmips3\n\t" \
1229 "dmtc0\t%z0, " #register "\n\t" \
1230 ".set\tmips0" \
1231 : : "Jr" (value)); \
1232 else \
1233 __asm__ __volatile__( \
1234 ".set\tmips64\n\t" \
1235 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
1236 ".set\tmips0" \
1237 : : "Jr" (value)); \
1238} while (0)
1239
1240#define __read_ulong_c0_register(reg, sel) \
1241 ((sizeof(unsigned long) == 4) ? \
1242 (unsigned long) __read_32bit_c0_register(reg, sel) : \
1243 (unsigned long) __read_64bit_c0_register(reg, sel))
1244
1245#define __write_ulong_c0_register(reg, sel, val) \
1246do { \
1247 if (sizeof(unsigned long) == 4) \
1248 __write_32bit_c0_register(reg, sel, val); \
1249 else \
1250 __write_64bit_c0_register(reg, sel, val); \
1251} while (0)
1252
1253/*
1254 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1255 */
1256#define __read_32bit_c0_ctrl_register(source) \
1257({ unsigned int __res; \
1258 __asm__ __volatile__( \
1259 "cfc0\t%0, " #source "\n\t" \
1260 : "=r" (__res)); \
1261 __res; \
1262})
1263
1264#define __write_32bit_c0_ctrl_register(register, value) \
1265do { \
1266 __asm__ __volatile__( \
1267 "ctc0\t%z0, " #register "\n\t" \
1268 : : "Jr" ((unsigned int)(value))); \
1269} while (0)
1270
1271/*
1272 * These versions are only needed for systems with more than 38 bits of
1273 * physical address space running the 32-bit kernel. That's none atm :-)
1274 */
1275#define __read_64bit_c0_split(source, sel) \
1276({ \
1277 unsigned long long __val; \
1278 unsigned long __flags; \
1279 \
1280 local_irq_save(__flags); \
1281 if (sel == 0) \
1282 __asm__ __volatile__( \
1283 ".set\tmips64\n\t" \
1284 "dmfc0\t%M0, " #source "\n\t" \
1285 "dsll\t%L0, %M0, 32\n\t" \
1286 "dsra\t%M0, %M0, 32\n\t" \
1287 "dsra\t%L0, %L0, 32\n\t" \
1288 ".set\tmips0" \
1289 : "=r" (__val)); \
1290 else \
1291 __asm__ __volatile__( \
1292 ".set\tmips64\n\t" \
1293 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
1294 "dsll\t%L0, %M0, 32\n\t" \
1295 "dsra\t%M0, %M0, 32\n\t" \
1296 "dsra\t%L0, %L0, 32\n\t" \
1297 ".set\tmips0" \
1298 : "=r" (__val)); \
1299 local_irq_restore(__flags); \
1300 \
1301 __val; \
1302})
1303
1304#define __write_64bit_c0_split(source, sel, val) \
1305do { \
1306 unsigned long __flags; \
1307 \
1308 local_irq_save(__flags); \
1309 if (sel == 0) \
1310 __asm__ __volatile__( \
1311 ".set\tmips64\n\t" \
1312 "dsll\t%L0, %L0, 32\n\t" \
1313 "dsrl\t%L0, %L0, 32\n\t" \
1314 "dsll\t%M0, %M0, 32\n\t" \
1315 "or\t%L0, %L0, %M0\n\t" \
1316 "dmtc0\t%L0, " #source "\n\t" \
1317 ".set\tmips0" \
1318 : : "r" (val)); \
1319 else \
1320 __asm__ __volatile__( \
1321 ".set\tmips64\n\t" \
1322 "dsll\t%L0, %L0, 32\n\t" \
1323 "dsrl\t%L0, %L0, 32\n\t" \
1324 "dsll\t%M0, %M0, 32\n\t" \
1325 "or\t%L0, %L0, %M0\n\t" \
1326 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1327 ".set\tmips0" \
1328 : : "r" (val)); \
1329 local_irq_restore(__flags); \
1330} while (0)
1331
1332#define __readx_32bit_c0_register(source) \
1333({ \
1334 unsigned int __res; \
1335 \
1336 __asm__ __volatile__( \
1337 " .set push \n" \
1338 " .set noat \n" \
1339 " .set mips32r2 \n" \
1340 " # mfhc0 $1, %1 \n" \
1341 _ASM_INSN_IF_MIPS(0x40410000 | ((%1 & 0x1f) << 11)) \
1342 _ASM_INSN32_IF_MM(0x002000f4 | ((%1 & 0x1f) << 16)) \
1343 " move %0, $1 \n" \
1344 " .set pop \n" \
1345 : "=r" (__res) \
1346 : "i" (source)); \
1347 __res; \
1348})
1349
1350#define __writex_32bit_c0_register(register, value) \
1351do { \
1352 __asm__ __volatile__( \
1353 " .set push \n" \
1354 " .set noat \n" \
1355 " .set mips32r2 \n" \
1356 " move $1, %0 \n" \
1357 " # mthc0 $1, %1 \n" \
1358 _ASM_INSN_IF_MIPS(0x40c10000 | ((%1 & 0x1f) << 11)) \
1359 _ASM_INSN32_IF_MM(0x002002f4 | ((%1 & 0x1f) << 16)) \
1360 " .set pop \n" \
1361 : \
1362 : "r" (value), "i" (register)); \
1363} while (0)
1364
1365#define read_c0_index() __read_32bit_c0_register($0, 0)
1366#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
1367
1368#define read_c0_random() __read_32bit_c0_register($1, 0)
1369#define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
1370
1371#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
1372#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
1373
1374#define readx_c0_entrylo0() __readx_32bit_c0_register(2)
1375#define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1376
1377#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
1378#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
1379
1380#define readx_c0_entrylo1() __readx_32bit_c0_register(3)
1381#define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1382
1383#define read_c0_conf() __read_32bit_c0_register($3, 0)
1384#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
1385
1386#define read_c0_context() __read_ulong_c0_register($4, 0)
1387#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
1388
1389#define read_c0_contextconfig() __read_32bit_c0_register($4, 1)
1390#define write_c0_contextconfig(val) __write_32bit_c0_register($4, 1, val)
1391
1392#define read_c0_userlocal() __read_ulong_c0_register($4, 2)
1393#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1394
1395#define read_c0_xcontextconfig() __read_ulong_c0_register($4, 3)
1396#define write_c0_xcontextconfig(val) __write_ulong_c0_register($4, 3, val)
1397
1398#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
1399#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
1400
1401#define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
1402#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1403
1404#define read_c0_wired() __read_32bit_c0_register($6, 0)
1405#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
1406
1407#define read_c0_info() __read_32bit_c0_register($7, 0)
1408
1409#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
1410#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
1411
1412#define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
1413#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
1414
1415#define read_c0_badinstr() __read_32bit_c0_register($8, 1)
1416#define read_c0_badinstrp() __read_32bit_c0_register($8, 2)
1417
1418#define read_c0_count() __read_32bit_c0_register($9, 0)
1419#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
1420
1421#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
1422#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
1423
1424#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
1425#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
1426
1427#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
1428#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
1429
1430#define read_c0_guestctl1() __read_32bit_c0_register($10, 4)
1431#define write_c0_guestctl1(val) __write_32bit_c0_register($10, 4, val)
1432
1433#define read_c0_guestctl2() __read_32bit_c0_register($10, 5)
1434#define write_c0_guestctl2(val) __write_32bit_c0_register($10, 5, val)
1435
1436#define read_c0_guestctl3() __read_32bit_c0_register($10, 6)
1437#define write_c0_guestctl3(val) __write_32bit_c0_register($10, 6, val)
1438
1439#define read_c0_compare() __read_32bit_c0_register($11, 0)
1440#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
1441
1442#define read_c0_guestctl0ext() __read_32bit_c0_register($11, 4)
1443#define write_c0_guestctl0ext(val) __write_32bit_c0_register($11, 4, val)
1444
1445#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
1446#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
1447
1448#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
1449#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
1450
1451#define read_c0_status() __read_32bit_c0_register($12, 0)
1452
1453#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
1454
1455#define read_c0_guestctl0() __read_32bit_c0_register($12, 6)
1456#define write_c0_guestctl0(val) __write_32bit_c0_register($12, 6, val)
1457
1458#define read_c0_gtoffset() __read_32bit_c0_register($12, 7)
1459#define write_c0_gtoffset(val) __write_32bit_c0_register($12, 7, val)
1460
1461#define read_c0_cause() __read_32bit_c0_register($13, 0)
1462#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
1463
1464#define read_c0_epc() __read_ulong_c0_register($14, 0)
1465#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
1466
1467#define read_c0_prid() __read_32bit_c0_register($15, 0)
1468
1469#define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3)
1470
1471#define read_c0_config() __read_32bit_c0_register($16, 0)
1472#define read_c0_config1() __read_32bit_c0_register($16, 1)
1473#define read_c0_config2() __read_32bit_c0_register($16, 2)
1474#define read_c0_config3() __read_32bit_c0_register($16, 3)
1475#define read_c0_config4() __read_32bit_c0_register($16, 4)
1476#define read_c0_config5() __read_32bit_c0_register($16, 5)
1477#define read_c0_config6() __read_32bit_c0_register($16, 6)
1478#define read_c0_config7() __read_32bit_c0_register($16, 7)
1479#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
1480#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
1481#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
1482#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
1483#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
1484#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
1485#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
1486#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
1487
1488#define read_c0_lladdr() __read_ulong_c0_register($17, 0)
1489#define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
1490#define read_c0_maar() __read_ulong_c0_register($17, 1)
1491#define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
1492#define read_c0_maari() __read_32bit_c0_register($17, 2)
1493#define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
1494
1495/*
1496 * The WatchLo register. There may be up to 8 of them.
1497 */
1498#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
1499#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
1500#define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
1501#define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
1502#define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
1503#define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
1504#define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
1505#define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
1506#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1507#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
1508#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
1509#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
1510#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
1511#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
1512#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
1513#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
1514
1515/*
1516 * The WatchHi register. There may be up to 8 of them.
1517 */
1518#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
1519#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
1520#define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
1521#define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
1522#define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
1523#define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
1524#define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
1525#define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
1526
1527#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
1528#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
1529#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
1530#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
1531#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
1532#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
1533#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
1534#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
1535
1536#define read_c0_xcontext() __read_ulong_c0_register($20, 0)
1537#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
1538
1539#define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
1540#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1541
1542#define read_c0_framemask() __read_32bit_c0_register($21, 0)
1543#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1544
1545#define read_c0_diag() __read_32bit_c0_register($22, 0)
1546#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
1547
1548/* R10K CP0 Branch Diagnostic register is 64bits wide */
1549#define read_c0_r10k_diag() __read_64bit_c0_register($22, 0)
1550#define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1551
1552#define read_c0_diag1() __read_32bit_c0_register($22, 1)
1553#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
1554
1555#define read_c0_diag2() __read_32bit_c0_register($22, 2)
1556#define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
1557
1558#define read_c0_diag3() __read_32bit_c0_register($22, 3)
1559#define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
1560
1561#define read_c0_diag4() __read_32bit_c0_register($22, 4)
1562#define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
1563
1564#define read_c0_diag5() __read_32bit_c0_register($22, 5)
1565#define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
1566
1567#define read_c0_debug() __read_32bit_c0_register($23, 0)
1568#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
1569
1570#define read_c0_depc() __read_ulong_c0_register($24, 0)
1571#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
1572
1573/*
1574 * MIPS32 / MIPS64 performance counters
1575 */
1576#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1577#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1578#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
1579#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1580#define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
1581#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1582#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
1583#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1584#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
1585#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1586#define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
1587#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1588#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
1589#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1590#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
1591#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1592#define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
1593#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1594#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
1595#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1596#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
1597#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1598#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1599#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1600
1601#define read_c0_ecc() __read_32bit_c0_register($26, 0)
1602#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1603
1604#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
1605#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1606
1607#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1608
1609#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1610#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1611
1612#define read_c0_taglo() __read_32bit_c0_register($28, 0)
1613#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1614
1615#define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
1616#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1617
1618#define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
1619#define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
1620
1621#define read_c0_staglo() __read_32bit_c0_register($28, 4)
1622#define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
1623
1624#define read_c0_taghi() __read_32bit_c0_register($29, 0)
1625#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1626
1627#define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1628#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1629
1630/* MIPSR2 */
1631#define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1632#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1633
1634#define read_c0_intctl() __read_32bit_c0_register($12, 1)
1635#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1636
1637#define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1638#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1639
1640#define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1641#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1642
1643#define read_c0_ebase() __read_32bit_c0_register($15, 1)
1644#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1645
1646#define read_c0_ebase_64() __read_64bit_c0_register($15, 1)
1647#define write_c0_ebase_64(val) __write_64bit_c0_register($15, 1, val)
1648
1649#define read_c0_cdmmbase() __read_ulong_c0_register($15, 2)
1650#define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
1651
1652/* MIPSR3 */
1653#define read_c0_segctl0() __read_32bit_c0_register($5, 2)
1654#define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
1655
1656#define read_c0_segctl1() __read_32bit_c0_register($5, 3)
1657#define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
1658
1659#define read_c0_segctl2() __read_32bit_c0_register($5, 4)
1660#define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
1661
1662/* Hardware Page Table Walker */
1663#define read_c0_pwbase() __read_ulong_c0_register($5, 5)
1664#define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
1665
1666#define read_c0_pwfield() __read_ulong_c0_register($5, 6)
1667#define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
1668
1669#define read_c0_pwsize() __read_ulong_c0_register($5, 7)
1670#define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
1671
1672#define read_c0_pwctl() __read_32bit_c0_register($6, 6)
1673#define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
1674
1675#define read_c0_pgd() __read_64bit_c0_register($9, 7)
1676#define write_c0_pgd(val) __write_64bit_c0_register($9, 7, val)
1677
1678#define read_c0_kpgd() __read_64bit_c0_register($31, 7)
1679#define write_c0_kpgd(val) __write_64bit_c0_register($31, 7, val)
1680
1681/* Cavium OCTEON (cnMIPS) */
1682#define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1683#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1684
1685#define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1686#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1687
1688#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1689#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1690/*
1691 * The cacheerr registers are not standardized. On OCTEON, they are
1692 * 64 bits wide.
1693 */
1694#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1695#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1696
1697#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1698#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1699
1700/* BMIPS3300 */
1701#define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
1702#define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
1703
1704#define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
1705#define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
1706
1707#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
1708#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
1709
1710/* BMIPS43xx */
1711#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
1712#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
1713
1714#define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
1715#define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
1716
1717#define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
1718#define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
1719
1720#define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
1721#define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
1722
1723#define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
1724#define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
1725
1726/* BMIPS5000 */
1727#define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
1728#define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
1729
1730#define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
1731#define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
1732
1733#define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
1734#define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
1735
1736#define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
1737#define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
1738
1739#define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
1740#define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
1741
1742#define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
1743#define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
1744
1745/*
1746 * Macros to access the guest system control coprocessor
1747 */
1748
1749#ifdef TOOLCHAIN_SUPPORTS_VIRT
1750
1751#define __read_32bit_gc0_register(source, sel) \
1752({ int __res; \
1753 __asm__ __volatile__( \
1754 ".set\tpush\n\t" \
1755 ".set\tmips32r2\n\t" \
1756 ".set\tvirt\n\t" \
1757 "mfgc0\t%0, $%1, %2\n\t" \
1758 ".set\tpop" \
1759 : "=r" (__res) \
1760 : "i" (source), "i" (sel)); \
1761 __res; \
1762})
1763
1764#define __read_64bit_gc0_register(source, sel) \
1765({ unsigned long long __res; \
1766 __asm__ __volatile__( \
1767 ".set\tpush\n\t" \
1768 ".set\tmips64r2\n\t" \
1769 ".set\tvirt\n\t" \
1770 "dmfgc0\t%0, $%1, %2\n\t" \
1771 ".set\tpop" \
1772 : "=r" (__res) \
1773 : "i" (source), "i" (sel)); \
1774 __res; \
1775})
1776
1777#define __write_32bit_gc0_register(register, sel, value) \
1778do { \
1779 __asm__ __volatile__( \
1780 ".set\tpush\n\t" \
1781 ".set\tmips32r2\n\t" \
1782 ".set\tvirt\n\t" \
1783 "mtgc0\t%z0, $%1, %2\n\t" \
1784 ".set\tpop" \
1785 : : "Jr" ((unsigned int)(value)), \
1786 "i" (register), "i" (sel)); \
1787} while (0)
1788
1789#define __write_64bit_gc0_register(register, sel, value) \
1790do { \
1791 __asm__ __volatile__( \
1792 ".set\tpush\n\t" \
1793 ".set\tmips64r2\n\t" \
1794 ".set\tvirt\n\t" \
1795 "dmtgc0\t%z0, $%1, %2\n\t" \
1796 ".set\tpop" \
1797 : : "Jr" (value), \
1798 "i" (register), "i" (sel)); \
1799} while (0)
1800
1801#else /* TOOLCHAIN_SUPPORTS_VIRT */
1802
1803#define __read_32bit_gc0_register(source, sel) \
1804({ int __res; \
1805 __asm__ __volatile__( \
1806 ".set\tpush\n\t" \
1807 ".set\tnoat\n\t" \
1808 "# mfgc0\t$1, $%1, %2\n\t" \
1809 _ASM_INSN_IF_MIPS(0x40610000 | %1 << 11 | %2) \
1810 _ASM_INSN32_IF_MM(0x002004fc | %1 << 16 | %2 << 11) \
1811 "move\t%0, $1\n\t" \
1812 ".set\tpop" \
1813 : "=r" (__res) \
1814 : "i" (source), "i" (sel)); \
1815 __res; \
1816})
1817
1818#define __read_64bit_gc0_register(source, sel) \
1819({ unsigned long long __res; \
1820 __asm__ __volatile__( \
1821 ".set\tpush\n\t" \
1822 ".set\tnoat\n\t" \
1823 "# dmfgc0\t$1, $%1, %2\n\t" \
1824 _ASM_INSN_IF_MIPS(0x40610100 | %1 << 11 | %2) \
1825 _ASM_INSN32_IF_MM(0x582004fc | %1 << 16 | %2 << 11) \
1826 "move\t%0, $1\n\t" \
1827 ".set\tpop" \
1828 : "=r" (__res) \
1829 : "i" (source), "i" (sel)); \
1830 __res; \
1831})
1832
1833#define __write_32bit_gc0_register(register, sel, value) \
1834do { \
1835 __asm__ __volatile__( \
1836 ".set\tpush\n\t" \
1837 ".set\tnoat\n\t" \
1838 "move\t$1, %z0\n\t" \
1839 "# mtgc0\t$1, $%1, %2\n\t" \
1840 _ASM_INSN_IF_MIPS(0x40610200 | %1 << 11 | %2) \
1841 _ASM_INSN32_IF_MM(0x002006fc | %1 << 16 | %2 << 11) \
1842 ".set\tpop" \
1843 : : "Jr" ((unsigned int)(value)), \
1844 "i" (register), "i" (sel)); \
1845} while (0)
1846
1847#define __write_64bit_gc0_register(register, sel, value) \
1848do { \
1849 __asm__ __volatile__( \
1850 ".set\tpush\n\t" \
1851 ".set\tnoat\n\t" \
1852 "move\t$1, %z0\n\t" \
1853 "# dmtgc0\t$1, $%1, %2\n\t" \
1854 _ASM_INSN_IF_MIPS(0x40610300 | %1 << 11 | %2) \
1855 _ASM_INSN32_IF_MM(0x582006fc | %1 << 16 | %2 << 11) \
1856 ".set\tpop" \
1857 : : "Jr" (value), \
1858 "i" (register), "i" (sel)); \
1859} while (0)
1860
1861#endif /* !TOOLCHAIN_SUPPORTS_VIRT */
1862
1863#define __read_ulong_gc0_register(reg, sel) \
1864 ((sizeof(unsigned long) == 4) ? \
1865 (unsigned long) __read_32bit_gc0_register(reg, sel) : \
1866 (unsigned long) __read_64bit_gc0_register(reg, sel))
1867
1868#define __write_ulong_gc0_register(reg, sel, val) \
1869do { \
1870 if (sizeof(unsigned long) == 4) \
1871 __write_32bit_gc0_register(reg, sel, val); \
1872 else \
1873 __write_64bit_gc0_register(reg, sel, val); \
1874} while (0)
1875
1876#define read_gc0_index() __read_32bit_gc0_register(0, 0)
1877#define write_gc0_index(val) __write_32bit_gc0_register(0, 0, val)
1878
1879#define read_gc0_entrylo0() __read_ulong_gc0_register(2, 0)
1880#define write_gc0_entrylo0(val) __write_ulong_gc0_register(2, 0, val)
1881
1882#define read_gc0_entrylo1() __read_ulong_gc0_register(3, 0)
1883#define write_gc0_entrylo1(val) __write_ulong_gc0_register(3, 0, val)
1884
1885#define read_gc0_context() __read_ulong_gc0_register(4, 0)
1886#define write_gc0_context(val) __write_ulong_gc0_register(4, 0, val)
1887
1888#define read_gc0_contextconfig() __read_32bit_gc0_register(4, 1)
1889#define write_gc0_contextconfig(val) __write_32bit_gc0_register(4, 1, val)
1890
1891#define read_gc0_userlocal() __read_ulong_gc0_register(4, 2)
1892#define write_gc0_userlocal(val) __write_ulong_gc0_register(4, 2, val)
1893
1894#define read_gc0_xcontextconfig() __read_ulong_gc0_register(4, 3)
1895#define write_gc0_xcontextconfig(val) __write_ulong_gc0_register(4, 3, val)
1896
1897#define read_gc0_pagemask() __read_32bit_gc0_register(5, 0)
1898#define write_gc0_pagemask(val) __write_32bit_gc0_register(5, 0, val)
1899
1900#define read_gc0_pagegrain() __read_32bit_gc0_register(5, 1)
1901#define write_gc0_pagegrain(val) __write_32bit_gc0_register(5, 1, val)
1902
1903#define read_gc0_segctl0() __read_ulong_gc0_register(5, 2)
1904#define write_gc0_segctl0(val) __write_ulong_gc0_register(5, 2, val)
1905
1906#define read_gc0_segctl1() __read_ulong_gc0_register(5, 3)
1907#define write_gc0_segctl1(val) __write_ulong_gc0_register(5, 3, val)
1908
1909#define read_gc0_segctl2() __read_ulong_gc0_register(5, 4)
1910#define write_gc0_segctl2(val) __write_ulong_gc0_register(5, 4, val)
1911
1912#define read_gc0_pwbase() __read_ulong_gc0_register(5, 5)
1913#define write_gc0_pwbase(val) __write_ulong_gc0_register(5, 5, val)
1914
1915#define read_gc0_pwfield() __read_ulong_gc0_register(5, 6)
1916#define write_gc0_pwfield(val) __write_ulong_gc0_register(5, 6, val)
1917
1918#define read_gc0_pwsize() __read_ulong_gc0_register(5, 7)
1919#define write_gc0_pwsize(val) __write_ulong_gc0_register(5, 7, val)
1920
1921#define read_gc0_wired() __read_32bit_gc0_register(6, 0)
1922#define write_gc0_wired(val) __write_32bit_gc0_register(6, 0, val)
1923
1924#define read_gc0_pwctl() __read_32bit_gc0_register(6, 6)
1925#define write_gc0_pwctl(val) __write_32bit_gc0_register(6, 6, val)
1926
1927#define read_gc0_hwrena() __read_32bit_gc0_register(7, 0)
1928#define write_gc0_hwrena(val) __write_32bit_gc0_register(7, 0, val)
1929
1930#define read_gc0_badvaddr() __read_ulong_gc0_register(8, 0)
1931#define write_gc0_badvaddr(val) __write_ulong_gc0_register(8, 0, val)
1932
1933#define read_gc0_badinstr() __read_32bit_gc0_register(8, 1)
1934#define write_gc0_badinstr(val) __write_32bit_gc0_register(8, 1, val)
1935
1936#define read_gc0_badinstrp() __read_32bit_gc0_register(8, 2)
1937#define write_gc0_badinstrp(val) __write_32bit_gc0_register(8, 2, val)
1938
1939#define read_gc0_count() __read_32bit_gc0_register(9, 0)
1940
1941#define read_gc0_entryhi() __read_ulong_gc0_register(10, 0)
1942#define write_gc0_entryhi(val) __write_ulong_gc0_register(10, 0, val)
1943
1944#define read_gc0_compare() __read_32bit_gc0_register(11, 0)
1945#define write_gc0_compare(val) __write_32bit_gc0_register(11, 0, val)
1946
1947#define read_gc0_status() __read_32bit_gc0_register(12, 0)
1948#define write_gc0_status(val) __write_32bit_gc0_register(12, 0, val)
1949
1950#define read_gc0_intctl() __read_32bit_gc0_register(12, 1)
1951#define write_gc0_intctl(val) __write_32bit_gc0_register(12, 1, val)
1952
1953#define read_gc0_cause() __read_32bit_gc0_register(13, 0)
1954#define write_gc0_cause(val) __write_32bit_gc0_register(13, 0, val)
1955
1956#define read_gc0_epc() __read_ulong_gc0_register(14, 0)
1957#define write_gc0_epc(val) __write_ulong_gc0_register(14, 0, val)
1958
1959#define read_gc0_ebase() __read_32bit_gc0_register(15, 1)
1960#define write_gc0_ebase(val) __write_32bit_gc0_register(15, 1, val)
1961
1962#define read_gc0_ebase_64() __read_64bit_gc0_register(15, 1)
1963#define write_gc0_ebase_64(val) __write_64bit_gc0_register(15, 1, val)
1964
1965#define read_gc0_config() __read_32bit_gc0_register(16, 0)
1966#define read_gc0_config1() __read_32bit_gc0_register(16, 1)
1967#define read_gc0_config2() __read_32bit_gc0_register(16, 2)
1968#define read_gc0_config3() __read_32bit_gc0_register(16, 3)
1969#define read_gc0_config4() __read_32bit_gc0_register(16, 4)
1970#define read_gc0_config5() __read_32bit_gc0_register(16, 5)
1971#define read_gc0_config6() __read_32bit_gc0_register(16, 6)
1972#define read_gc0_config7() __read_32bit_gc0_register(16, 7)
1973#define write_gc0_config(val) __write_32bit_gc0_register(16, 0, val)
1974#define write_gc0_config1(val) __write_32bit_gc0_register(16, 1, val)
1975#define write_gc0_config2(val) __write_32bit_gc0_register(16, 2, val)
1976#define write_gc0_config3(val) __write_32bit_gc0_register(16, 3, val)
1977#define write_gc0_config4(val) __write_32bit_gc0_register(16, 4, val)
1978#define write_gc0_config5(val) __write_32bit_gc0_register(16, 5, val)
1979#define write_gc0_config6(val) __write_32bit_gc0_register(16, 6, val)
1980#define write_gc0_config7(val) __write_32bit_gc0_register(16, 7, val)
1981
1982#define read_gc0_watchlo0() __read_ulong_gc0_register(18, 0)
1983#define read_gc0_watchlo1() __read_ulong_gc0_register(18, 1)
1984#define read_gc0_watchlo2() __read_ulong_gc0_register(18, 2)
1985#define read_gc0_watchlo3() __read_ulong_gc0_register(18, 3)
1986#define read_gc0_watchlo4() __read_ulong_gc0_register(18, 4)
1987#define read_gc0_watchlo5() __read_ulong_gc0_register(18, 5)
1988#define read_gc0_watchlo6() __read_ulong_gc0_register(18, 6)
1989#define read_gc0_watchlo7() __read_ulong_gc0_register(18, 7)
1990#define write_gc0_watchlo0(val) __write_ulong_gc0_register(18, 0, val)
1991#define write_gc0_watchlo1(val) __write_ulong_gc0_register(18, 1, val)
1992#define write_gc0_watchlo2(val) __write_ulong_gc0_register(18, 2, val)
1993#define write_gc0_watchlo3(val) __write_ulong_gc0_register(18, 3, val)
1994#define write_gc0_watchlo4(val) __write_ulong_gc0_register(18, 4, val)
1995#define write_gc0_watchlo5(val) __write_ulong_gc0_register(18, 5, val)
1996#define write_gc0_watchlo6(val) __write_ulong_gc0_register(18, 6, val)
1997#define write_gc0_watchlo7(val) __write_ulong_gc0_register(18, 7, val)
1998
1999#define read_gc0_watchhi0() __read_32bit_gc0_register(19, 0)
2000#define read_gc0_watchhi1() __read_32bit_gc0_register(19, 1)
2001#define read_gc0_watchhi2() __read_32bit_gc0_register(19, 2)
2002#define read_gc0_watchhi3() __read_32bit_gc0_register(19, 3)
2003#define read_gc0_watchhi4() __read_32bit_gc0_register(19, 4)
2004#define read_gc0_watchhi5() __read_32bit_gc0_register(19, 5)
2005#define read_gc0_watchhi6() __read_32bit_gc0_register(19, 6)
2006#define read_gc0_watchhi7() __read_32bit_gc0_register(19, 7)
2007#define write_gc0_watchhi0(val) __write_32bit_gc0_register(19, 0, val)
2008#define write_gc0_watchhi1(val) __write_32bit_gc0_register(19, 1, val)
2009#define write_gc0_watchhi2(val) __write_32bit_gc0_register(19, 2, val)
2010#define write_gc0_watchhi3(val) __write_32bit_gc0_register(19, 3, val)
2011#define write_gc0_watchhi4(val) __write_32bit_gc0_register(19, 4, val)
2012#define write_gc0_watchhi5(val) __write_32bit_gc0_register(19, 5, val)
2013#define write_gc0_watchhi6(val) __write_32bit_gc0_register(19, 6, val)
2014#define write_gc0_watchhi7(val) __write_32bit_gc0_register(19, 7, val)
2015
2016#define read_gc0_xcontext() __read_ulong_gc0_register(20, 0)
2017#define write_gc0_xcontext(val) __write_ulong_gc0_register(20, 0, val)
2018
2019#define read_gc0_perfctrl0() __read_32bit_gc0_register(25, 0)
2020#define write_gc0_perfctrl0(val) __write_32bit_gc0_register(25, 0, val)
2021#define read_gc0_perfcntr0() __read_32bit_gc0_register(25, 1)
2022#define write_gc0_perfcntr0(val) __write_32bit_gc0_register(25, 1, val)
2023#define read_gc0_perfcntr0_64() __read_64bit_gc0_register(25, 1)
2024#define write_gc0_perfcntr0_64(val) __write_64bit_gc0_register(25, 1, val)
2025#define read_gc0_perfctrl1() __read_32bit_gc0_register(25, 2)
2026#define write_gc0_perfctrl1(val) __write_32bit_gc0_register(25, 2, val)
2027#define read_gc0_perfcntr1() __read_32bit_gc0_register(25, 3)
2028#define write_gc0_perfcntr1(val) __write_32bit_gc0_register(25, 3, val)
2029#define read_gc0_perfcntr1_64() __read_64bit_gc0_register(25, 3)
2030#define write_gc0_perfcntr1_64(val) __write_64bit_gc0_register(25, 3, val)
2031#define read_gc0_perfctrl2() __read_32bit_gc0_register(25, 4)
2032#define write_gc0_perfctrl2(val) __write_32bit_gc0_register(25, 4, val)
2033#define read_gc0_perfcntr2() __read_32bit_gc0_register(25, 5)
2034#define write_gc0_perfcntr2(val) __write_32bit_gc0_register(25, 5, val)
2035#define read_gc0_perfcntr2_64() __read_64bit_gc0_register(25, 5)
2036#define write_gc0_perfcntr2_64(val) __write_64bit_gc0_register(25, 5, val)
2037#define read_gc0_perfctrl3() __read_32bit_gc0_register(25, 6)
2038#define write_gc0_perfctrl3(val) __write_32bit_gc0_register(25, 6, val)
2039#define read_gc0_perfcntr3() __read_32bit_gc0_register(25, 7)
2040#define write_gc0_perfcntr3(val) __write_32bit_gc0_register(25, 7, val)
2041#define read_gc0_perfcntr3_64() __read_64bit_gc0_register(25, 7)
2042#define write_gc0_perfcntr3_64(val) __write_64bit_gc0_register(25, 7, val)
2043
2044#define read_gc0_errorepc() __read_ulong_gc0_register(30, 0)
2045#define write_gc0_errorepc(val) __write_ulong_gc0_register(30, 0, val)
2046
2047#define read_gc0_kscratch1() __read_ulong_gc0_register(31, 2)
2048#define read_gc0_kscratch2() __read_ulong_gc0_register(31, 3)
2049#define read_gc0_kscratch3() __read_ulong_gc0_register(31, 4)
2050#define read_gc0_kscratch4() __read_ulong_gc0_register(31, 5)
2051#define read_gc0_kscratch5() __read_ulong_gc0_register(31, 6)
2052#define read_gc0_kscratch6() __read_ulong_gc0_register(31, 7)
2053#define write_gc0_kscratch1(val) __write_ulong_gc0_register(31, 2, val)
2054#define write_gc0_kscratch2(val) __write_ulong_gc0_register(31, 3, val)
2055#define write_gc0_kscratch3(val) __write_ulong_gc0_register(31, 4, val)
2056#define write_gc0_kscratch4(val) __write_ulong_gc0_register(31, 5, val)
2057#define write_gc0_kscratch5(val) __write_ulong_gc0_register(31, 6, val)
2058#define write_gc0_kscratch6(val) __write_ulong_gc0_register(31, 7, val)
2059
2060/*
2061 * Macros to access the floating point coprocessor control registers
2062 */
2063#define _read_32bit_cp1_register(source, gas_hardfloat) \
2064({ \
2065 unsigned int __res; \
2066 \
2067 __asm__ __volatile__( \
2068 " .set push \n" \
2069 " .set reorder \n" \
2070 " # gas fails to assemble cfc1 for some archs, \n" \
2071 " # like Octeon. \n" \
2072 " .set mips1 \n" \
2073 " "STR(gas_hardfloat)" \n" \
2074 " cfc1 %0,"STR(source)" \n" \
2075 " .set pop \n" \
2076 : "=r" (__res)); \
2077 __res; \
2078})
2079
2080#define _write_32bit_cp1_register(dest, val, gas_hardfloat) \
2081do { \
2082 __asm__ __volatile__( \
2083 " .set push \n" \
2084 " .set reorder \n" \
2085 " "STR(gas_hardfloat)" \n" \
2086 " ctc1 %0,"STR(dest)" \n" \
2087 " .set pop \n" \
2088 : : "r" (val)); \
2089} while (0)
2090
2091#ifdef GAS_HAS_SET_HARDFLOAT
2092#define read_32bit_cp1_register(source) \
2093 _read_32bit_cp1_register(source, .set hardfloat)
2094#define write_32bit_cp1_register(dest, val) \
2095 _write_32bit_cp1_register(dest, val, .set hardfloat)
2096#else
2097#define read_32bit_cp1_register(source) \
2098 _read_32bit_cp1_register(source, )
2099#define write_32bit_cp1_register(dest, val) \
2100 _write_32bit_cp1_register(dest, val, )
2101#endif
2102
2103#ifdef HAVE_AS_DSP
2104#define rddsp(mask) \
2105({ \
2106 unsigned int __dspctl; \
2107 \
2108 __asm__ __volatile__( \
2109 " .set push \n" \
2110 " .set dsp \n" \
2111 " rddsp %0, %x1 \n" \
2112 " .set pop \n" \
2113 : "=r" (__dspctl) \
2114 : "i" (mask)); \
2115 __dspctl; \
2116})
2117
2118#define wrdsp(val, mask) \
2119do { \
2120 __asm__ __volatile__( \
2121 " .set push \n" \
2122 " .set dsp \n" \
2123 " wrdsp %0, %x1 \n" \
2124 " .set pop \n" \
2125 : \
2126 : "r" (val), "i" (mask)); \
2127} while (0)
2128
2129#define mflo0() \
2130({ \
2131 long mflo0; \
2132 __asm__( \
2133 " .set push \n" \
2134 " .set dsp \n" \
2135 " mflo %0, $ac0 \n" \
2136 " .set pop \n" \
2137 : "=r" (mflo0)); \
2138 mflo0; \
2139})
2140
2141#define mflo1() \
2142({ \
2143 long mflo1; \
2144 __asm__( \
2145 " .set push \n" \
2146 " .set dsp \n" \
2147 " mflo %0, $ac1 \n" \
2148 " .set pop \n" \
2149 : "=r" (mflo1)); \
2150 mflo1; \
2151})
2152
2153#define mflo2() \
2154({ \
2155 long mflo2; \
2156 __asm__( \
2157 " .set push \n" \
2158 " .set dsp \n" \
2159 " mflo %0, $ac2 \n" \
2160 " .set pop \n" \
2161 : "=r" (mflo2)); \
2162 mflo2; \
2163})
2164
2165#define mflo3() \
2166({ \
2167 long mflo3; \
2168 __asm__( \
2169 " .set push \n" \
2170 " .set dsp \n" \
2171 " mflo %0, $ac3 \n" \
2172 " .set pop \n" \
2173 : "=r" (mflo3)); \
2174 mflo3; \
2175})
2176
2177#define mfhi0() \
2178({ \
2179 long mfhi0; \
2180 __asm__( \
2181 " .set push \n" \
2182 " .set dsp \n" \
2183 " mfhi %0, $ac0 \n" \
2184 " .set pop \n" \
2185 : "=r" (mfhi0)); \
2186 mfhi0; \
2187})
2188
2189#define mfhi1() \
2190({ \
2191 long mfhi1; \
2192 __asm__( \
2193 " .set push \n" \
2194 " .set dsp \n" \
2195 " mfhi %0, $ac1 \n" \
2196 " .set pop \n" \
2197 : "=r" (mfhi1)); \
2198 mfhi1; \
2199})
2200
2201#define mfhi2() \
2202({ \
2203 long mfhi2; \
2204 __asm__( \
2205 " .set push \n" \
2206 " .set dsp \n" \
2207 " mfhi %0, $ac2 \n" \
2208 " .set pop \n" \
2209 : "=r" (mfhi2)); \
2210 mfhi2; \
2211})
2212
2213#define mfhi3() \
2214({ \
2215 long mfhi3; \
2216 __asm__( \
2217 " .set push \n" \
2218 " .set dsp \n" \
2219 " mfhi %0, $ac3 \n" \
2220 " .set pop \n" \
2221 : "=r" (mfhi3)); \
2222 mfhi3; \
2223})
2224
2225
2226#define mtlo0(x) \
2227({ \
2228 __asm__( \
2229 " .set push \n" \
2230 " .set dsp \n" \
2231 " mtlo %0, $ac0 \n" \
2232 " .set pop \n" \
2233 : \
2234 : "r" (x)); \
2235})
2236
2237#define mtlo1(x) \
2238({ \
2239 __asm__( \
2240 " .set push \n" \
2241 " .set dsp \n" \
2242 " mtlo %0, $ac1 \n" \
2243 " .set pop \n" \
2244 : \
2245 : "r" (x)); \
2246})
2247
2248#define mtlo2(x) \
2249({ \
2250 __asm__( \
2251 " .set push \n" \
2252 " .set dsp \n" \
2253 " mtlo %0, $ac2 \n" \
2254 " .set pop \n" \
2255 : \
2256 : "r" (x)); \
2257})
2258
2259#define mtlo3(x) \
2260({ \
2261 __asm__( \
2262 " .set push \n" \
2263 " .set dsp \n" \
2264 " mtlo %0, $ac3 \n" \
2265 " .set pop \n" \
2266 : \
2267 : "r" (x)); \
2268})
2269
2270#define mthi0(x) \
2271({ \
2272 __asm__( \
2273 " .set push \n" \
2274 " .set dsp \n" \
2275 " mthi %0, $ac0 \n" \
2276 " .set pop \n" \
2277 : \
2278 : "r" (x)); \
2279})
2280
2281#define mthi1(x) \
2282({ \
2283 __asm__( \
2284 " .set push \n" \
2285 " .set dsp \n" \
2286 " mthi %0, $ac1 \n" \
2287 " .set pop \n" \
2288 : \
2289 : "r" (x)); \
2290})
2291
2292#define mthi2(x) \
2293({ \
2294 __asm__( \
2295 " .set push \n" \
2296 " .set dsp \n" \
2297 " mthi %0, $ac2 \n" \
2298 " .set pop \n" \
2299 : \
2300 : "r" (x)); \
2301})
2302
2303#define mthi3(x) \
2304({ \
2305 __asm__( \
2306 " .set push \n" \
2307 " .set dsp \n" \
2308 " mthi %0, $ac3 \n" \
2309 " .set pop \n" \
2310 : \
2311 : "r" (x)); \
2312})
2313
2314#else
2315
2316#define rddsp(mask) \
2317({ \
2318 unsigned int __res; \
2319 \
2320 __asm__ __volatile__( \
2321 " .set push \n" \
2322 " .set noat \n" \
2323 " # rddsp $1, %x1 \n" \
2324 _ASM_INSN_IF_MIPS(0x7c000cb8 | (%x1 << 16)) \
2325 _ASM_INSN32_IF_MM(0x0020067c | (%x1 << 14)) \
2326 " move %0, $1 \n" \
2327 " .set pop \n" \
2328 : "=r" (__res) \
2329 : "i" (mask)); \
2330 __res; \
2331})
2332
2333#define wrdsp(val, mask) \
2334do { \
2335 __asm__ __volatile__( \
2336 " .set push \n" \
2337 " .set noat \n" \
2338 " move $1, %0 \n" \
2339 " # wrdsp $1, %x1 \n" \
2340 _ASM_INSN_IF_MIPS(0x7c2004f8 | (%x1 << 11)) \
2341 _ASM_INSN32_IF_MM(0x0020167c | (%x1 << 14)) \
2342 " .set pop \n" \
2343 : \
2344 : "r" (val), "i" (mask)); \
2345} while (0)
2346
2347#define _dsp_mfxxx(ins) \
2348({ \
2349 unsigned long __treg; \
2350 \
2351 __asm__ __volatile__( \
2352 " .set push \n" \
2353 " .set noat \n" \
2354 _ASM_INSN_IF_MIPS(0x00000810 | %X1) \
2355 _ASM_INSN32_IF_MM(0x0001007c | %x1) \
2356 " move %0, $1 \n" \
2357 " .set pop \n" \
2358 : "=r" (__treg) \
2359 : "i" (ins)); \
2360 __treg; \
2361})
2362
2363#define _dsp_mtxxx(val, ins) \
2364do { \
2365 __asm__ __volatile__( \
2366 " .set push \n" \
2367 " .set noat \n" \
2368 " move $1, %0 \n" \
2369 _ASM_INSN_IF_MIPS(0x00200011 | %X1) \
2370 _ASM_INSN32_IF_MM(0x0001207c | %x1) \
2371 " .set pop \n" \
2372 : \
2373 : "r" (val), "i" (ins)); \
2374} while (0)
2375
2376#ifdef CONFIG_CPU_MICROMIPS
2377
2378#define _dsp_mflo(reg) _dsp_mfxxx((reg << 14) | 0x1000)
2379#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 14) | 0x0000)
2380
2381#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x1000))
2382#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 14) | 0x0000))
2383
2384#else /* !CONFIG_CPU_MICROMIPS */
2385
2386#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
2387#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
2388
2389#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
2390#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
2391
2392#endif /* CONFIG_CPU_MICROMIPS */
2393
2394#define mflo0() _dsp_mflo(0)
2395#define mflo1() _dsp_mflo(1)
2396#define mflo2() _dsp_mflo(2)
2397#define mflo3() _dsp_mflo(3)
2398
2399#define mfhi0() _dsp_mfhi(0)
2400#define mfhi1() _dsp_mfhi(1)
2401#define mfhi2() _dsp_mfhi(2)
2402#define mfhi3() _dsp_mfhi(3)
2403
2404#define mtlo0(x) _dsp_mtlo(x, 0)
2405#define mtlo1(x) _dsp_mtlo(x, 1)
2406#define mtlo2(x) _dsp_mtlo(x, 2)
2407#define mtlo3(x) _dsp_mtlo(x, 3)
2408
2409#define mthi0(x) _dsp_mthi(x, 0)
2410#define mthi1(x) _dsp_mthi(x, 1)
2411#define mthi2(x) _dsp_mthi(x, 2)
2412#define mthi3(x) _dsp_mthi(x, 3)
2413
2414#endif
2415
2416/*
2417 * TLB operations.
2418 *
2419 * It is responsibility of the caller to take care of any TLB hazards.
2420 */
2421static inline void tlb_probe(void)
2422{
2423 __asm__ __volatile__(
2424 ".set noreorder\n\t"
2425 "tlbp\n\t"
2426 ".set reorder");
2427}
2428
2429static inline void tlb_read(void)
2430{
2431#if MIPS34K_MISSED_ITLB_WAR
2432 int res = 0;
2433
2434 __asm__ __volatile__(
2435 " .set push \n"
2436 " .set noreorder \n"
2437 " .set noat \n"
2438 " .set mips32r2 \n"
2439 " .word 0x41610001 # dvpe $1 \n"
2440 " move %0, $1 \n"
2441 " ehb \n"
2442 " .set pop \n"
2443 : "=r" (res));
2444
2445 instruction_hazard();
2446#endif
2447
2448 __asm__ __volatile__(
2449 ".set noreorder\n\t"
2450 "tlbr\n\t"
2451 ".set reorder");
2452
2453#if MIPS34K_MISSED_ITLB_WAR
2454 if ((res & _ULCAST_(1)))
2455 __asm__ __volatile__(
2456 " .set push \n"
2457 " .set noreorder \n"
2458 " .set noat \n"
2459 " .set mips32r2 \n"
2460 " .word 0x41600021 # evpe \n"
2461 " ehb \n"
2462 " .set pop \n");
2463#endif
2464}
2465
2466static inline void tlb_write_indexed(void)
2467{
2468 __asm__ __volatile__(
2469 ".set noreorder\n\t"
2470 "tlbwi\n\t"
2471 ".set reorder");
2472}
2473
2474static inline void tlb_write_random(void)
2475{
2476 __asm__ __volatile__(
2477 ".set noreorder\n\t"
2478 "tlbwr\n\t"
2479 ".set reorder");
2480}
2481
2482#ifdef TOOLCHAIN_SUPPORTS_VIRT
2483
2484/*
2485 * Guest TLB operations.
2486 *
2487 * It is responsibility of the caller to take care of any TLB hazards.
2488 */
2489static inline void guest_tlb_probe(void)
2490{
2491 __asm__ __volatile__(
2492 ".set push\n\t"
2493 ".set noreorder\n\t"
2494 ".set virt\n\t"
2495 "tlbgp\n\t"
2496 ".set pop");
2497}
2498
2499static inline void guest_tlb_read(void)
2500{
2501 __asm__ __volatile__(
2502 ".set push\n\t"
2503 ".set noreorder\n\t"
2504 ".set virt\n\t"
2505 "tlbgr\n\t"
2506 ".set pop");
2507}
2508
2509static inline void guest_tlb_write_indexed(void)
2510{
2511 __asm__ __volatile__(
2512 ".set push\n\t"
2513 ".set noreorder\n\t"
2514 ".set virt\n\t"
2515 "tlbgwi\n\t"
2516 ".set pop");
2517}
2518
2519static inline void guest_tlb_write_random(void)
2520{
2521 __asm__ __volatile__(
2522 ".set push\n\t"
2523 ".set noreorder\n\t"
2524 ".set virt\n\t"
2525 "tlbgwr\n\t"
2526 ".set pop");
2527}
2528
2529/*
2530 * Guest TLB Invalidate Flush
2531 */
2532static inline void guest_tlbinvf(void)
2533{
2534 __asm__ __volatile__(
2535 ".set push\n\t"
2536 ".set noreorder\n\t"
2537 ".set virt\n\t"
2538 "tlbginvf\n\t"
2539 ".set pop");
2540}
2541
2542#else /* TOOLCHAIN_SUPPORTS_VIRT */
2543
2544/*
2545 * Guest TLB operations.
2546 *
2547 * It is responsibility of the caller to take care of any TLB hazards.
2548 */
2549static inline void guest_tlb_probe(void)
2550{
2551 __asm__ __volatile__(
2552 "# tlbgp\n\t"
2553 _ASM_INSN_IF_MIPS(0x42000010)
2554 _ASM_INSN32_IF_MM(0x0000017c));
2555}
2556
2557static inline void guest_tlb_read(void)
2558{
2559 __asm__ __volatile__(
2560 "# tlbgr\n\t"
2561 _ASM_INSN_IF_MIPS(0x42000009)
2562 _ASM_INSN32_IF_MM(0x0000117c));
2563}
2564
2565static inline void guest_tlb_write_indexed(void)
2566{
2567 __asm__ __volatile__(
2568 "# tlbgwi\n\t"
2569 _ASM_INSN_IF_MIPS(0x4200000a)
2570 _ASM_INSN32_IF_MM(0x0000217c));
2571}
2572
2573static inline void guest_tlb_write_random(void)
2574{
2575 __asm__ __volatile__(
2576 "# tlbgwr\n\t"
2577 _ASM_INSN_IF_MIPS(0x4200000e)
2578 _ASM_INSN32_IF_MM(0x0000317c));
2579}
2580
2581/*
2582 * Guest TLB Invalidate Flush
2583 */
2584static inline void guest_tlbinvf(void)
2585{
2586 __asm__ __volatile__(
2587 "# tlbginvf\n\t"
2588 _ASM_INSN_IF_MIPS(0x4200000c)
2589 _ASM_INSN32_IF_MM(0x0000517c));
2590}
2591
2592#endif /* !TOOLCHAIN_SUPPORTS_VIRT */
2593
2594/*
2595 * Manipulate bits in a register.
2596 */
2597#define __BUILD_SET_COMMON(name) \
2598static inline unsigned int \
2599set_##name(unsigned int set) \
2600{ \
2601 unsigned int res, new; \
2602 \
2603 res = read_##name(); \
2604 new = res | set; \
2605 write_##name(new); \
2606 \
2607 return res; \
2608} \
2609 \
2610static inline unsigned int \
2611clear_##name(unsigned int clear) \
2612{ \
2613 unsigned int res, new; \
2614 \
2615 res = read_##name(); \
2616 new = res & ~clear; \
2617 write_##name(new); \
2618 \
2619 return res; \
2620} \
2621 \
2622static inline unsigned int \
2623change_##name(unsigned int change, unsigned int val) \
2624{ \
2625 unsigned int res, new; \
2626 \
2627 res = read_##name(); \
2628 new = res & ~change; \
2629 new |= (val & change); \
2630 write_##name(new); \
2631 \
2632 return res; \
2633}
2634
2635/*
2636 * Manipulate bits in a c0 register.
2637 */
2638#define __BUILD_SET_C0(name) __BUILD_SET_COMMON(c0_##name)
2639
2640__BUILD_SET_C0(status)
2641__BUILD_SET_C0(cause)
2642__BUILD_SET_C0(config)
2643__BUILD_SET_C0(config5)
2644__BUILD_SET_C0(intcontrol)
2645__BUILD_SET_C0(intctl)
2646__BUILD_SET_C0(srsmap)
2647__BUILD_SET_C0(pagegrain)
2648__BUILD_SET_C0(guestctl0)
2649__BUILD_SET_C0(guestctl0ext)
2650__BUILD_SET_C0(guestctl1)
2651__BUILD_SET_C0(guestctl2)
2652__BUILD_SET_C0(guestctl3)
2653__BUILD_SET_C0(brcm_config_0)
2654__BUILD_SET_C0(brcm_bus_pll)
2655__BUILD_SET_C0(brcm_reset)
2656__BUILD_SET_C0(brcm_cmt_intr)
2657__BUILD_SET_C0(brcm_cmt_ctrl)
2658__BUILD_SET_C0(brcm_config)
2659__BUILD_SET_C0(brcm_mode)
2660
2661/*
2662 * Manipulate bits in a guest c0 register.
2663 */
2664#define __BUILD_SET_GC0(name) __BUILD_SET_COMMON(gc0_##name)
2665
2666__BUILD_SET_GC0(status)
2667__BUILD_SET_GC0(cause)
2668__BUILD_SET_GC0(ebase)
2669
2670/*
2671 * Return low 10 bits of ebase.
2672 * Note that under KVM (MIPSVZ) this returns vcpu id.
2673 */
2674static inline unsigned int get_ebase_cpunum(void)
2675{
2676 return read_c0_ebase() & MIPS_EBASE_CPUNUM;
2677}
2678
2679#endif /* !__ASSEMBLY__ */
2680
2681#endif /* _ASM_MIPSREGS_H */
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
12 */
13#ifndef _ASM_MIPSREGS_H
14#define _ASM_MIPSREGS_H
15
16#include <linux/linkage.h>
17#include <linux/types.h>
18#include <asm/hazards.h>
19#include <asm/war.h>
20
21/*
22 * The following macros are especially useful for __asm__
23 * inline assembler.
24 */
25#ifndef __STR
26#define __STR(x) #x
27#endif
28#ifndef STR
29#define STR(x) __STR(x)
30#endif
31
32/*
33 * Configure language
34 */
35#ifdef __ASSEMBLY__
36#define _ULCAST_
37#else
38#define _ULCAST_ (unsigned long)
39#endif
40
41/*
42 * Coprocessor 0 register names
43 */
44#define CP0_INDEX $0
45#define CP0_RANDOM $1
46#define CP0_ENTRYLO0 $2
47#define CP0_ENTRYLO1 $3
48#define CP0_CONF $3
49#define CP0_CONTEXT $4
50#define CP0_PAGEMASK $5
51#define CP0_WIRED $6
52#define CP0_INFO $7
53#define CP0_HWRENA $7, 0
54#define CP0_BADVADDR $8
55#define CP0_BADINSTR $8, 1
56#define CP0_COUNT $9
57#define CP0_ENTRYHI $10
58#define CP0_COMPARE $11
59#define CP0_STATUS $12
60#define CP0_CAUSE $13
61#define CP0_EPC $14
62#define CP0_PRID $15
63#define CP0_EBASE $15, 1
64#define CP0_CMGCRBASE $15, 3
65#define CP0_CONFIG $16
66#define CP0_CONFIG3 $16, 3
67#define CP0_CONFIG5 $16, 5
68#define CP0_LLADDR $17
69#define CP0_WATCHLO $18
70#define CP0_WATCHHI $19
71#define CP0_XCONTEXT $20
72#define CP0_FRAMEMASK $21
73#define CP0_DIAGNOSTIC $22
74#define CP0_DEBUG $23
75#define CP0_DEPC $24
76#define CP0_PERFORMANCE $25
77#define CP0_ECC $26
78#define CP0_CACHEERR $27
79#define CP0_TAGLO $28
80#define CP0_TAGHI $29
81#define CP0_ERROREPC $30
82#define CP0_DESAVE $31
83
84/*
85 * R4640/R4650 cp0 register names. These registers are listed
86 * here only for completeness; without MMU these CPUs are not useable
87 * by Linux. A future ELKS port might take make Linux run on them
88 * though ...
89 */
90#define CP0_IBASE $0
91#define CP0_IBOUND $1
92#define CP0_DBASE $2
93#define CP0_DBOUND $3
94#define CP0_CALG $17
95#define CP0_IWATCH $18
96#define CP0_DWATCH $19
97
98/*
99 * Coprocessor 0 Set 1 register names
100 */
101#define CP0_S1_DERRADDR0 $26
102#define CP0_S1_DERRADDR1 $27
103#define CP0_S1_INTCONTROL $20
104
105/*
106 * Coprocessor 0 Set 2 register names
107 */
108#define CP0_S2_SRSCTL $12 /* MIPSR2 */
109
110/*
111 * Coprocessor 0 Set 3 register names
112 */
113#define CP0_S3_SRSMAP $12 /* MIPSR2 */
114
115/*
116 * TX39 Series
117 */
118#define CP0_TX39_CACHE $7
119
120
121/* Generic EntryLo bit definitions */
122#define ENTRYLO_G (_ULCAST_(1) << 0)
123#define ENTRYLO_V (_ULCAST_(1) << 1)
124#define ENTRYLO_D (_ULCAST_(1) << 2)
125#define ENTRYLO_C_SHIFT 3
126#define ENTRYLO_C (_ULCAST_(7) << ENTRYLO_C_SHIFT)
127
128/* R3000 EntryLo bit definitions */
129#define R3K_ENTRYLO_G (_ULCAST_(1) << 8)
130#define R3K_ENTRYLO_V (_ULCAST_(1) << 9)
131#define R3K_ENTRYLO_D (_ULCAST_(1) << 10)
132#define R3K_ENTRYLO_N (_ULCAST_(1) << 11)
133
134/* MIPS32/64 EntryLo bit definitions */
135#define MIPS_ENTRYLO_PFN_SHIFT 6
136#define MIPS_ENTRYLO_XI (_ULCAST_(1) << (BITS_PER_LONG - 2))
137#define MIPS_ENTRYLO_RI (_ULCAST_(1) << (BITS_PER_LONG - 1))
138
139/*
140 * Values for PageMask register
141 */
142#ifdef CONFIG_CPU_VR41XX
143
144/* Why doesn't stupidity hurt ... */
145
146#define PM_1K 0x00000000
147#define PM_4K 0x00001800
148#define PM_16K 0x00007800
149#define PM_64K 0x0001f800
150#define PM_256K 0x0007f800
151
152#else
153
154#define PM_4K 0x00000000
155#define PM_8K 0x00002000
156#define PM_16K 0x00006000
157#define PM_32K 0x0000e000
158#define PM_64K 0x0001e000
159#define PM_128K 0x0003e000
160#define PM_256K 0x0007e000
161#define PM_512K 0x000fe000
162#define PM_1M 0x001fe000
163#define PM_2M 0x003fe000
164#define PM_4M 0x007fe000
165#define PM_8M 0x00ffe000
166#define PM_16M 0x01ffe000
167#define PM_32M 0x03ffe000
168#define PM_64M 0x07ffe000
169#define PM_256M 0x1fffe000
170#define PM_1G 0x7fffe000
171
172#endif
173
174/*
175 * Default page size for a given kernel configuration
176 */
177#ifdef CONFIG_PAGE_SIZE_4KB
178#define PM_DEFAULT_MASK PM_4K
179#elif defined(CONFIG_PAGE_SIZE_8KB)
180#define PM_DEFAULT_MASK PM_8K
181#elif defined(CONFIG_PAGE_SIZE_16KB)
182#define PM_DEFAULT_MASK PM_16K
183#elif defined(CONFIG_PAGE_SIZE_32KB)
184#define PM_DEFAULT_MASK PM_32K
185#elif defined(CONFIG_PAGE_SIZE_64KB)
186#define PM_DEFAULT_MASK PM_64K
187#else
188#error Bad page size configuration!
189#endif
190
191/*
192 * Default huge tlb size for a given kernel configuration
193 */
194#ifdef CONFIG_PAGE_SIZE_4KB
195#define PM_HUGE_MASK PM_1M
196#elif defined(CONFIG_PAGE_SIZE_8KB)
197#define PM_HUGE_MASK PM_4M
198#elif defined(CONFIG_PAGE_SIZE_16KB)
199#define PM_HUGE_MASK PM_16M
200#elif defined(CONFIG_PAGE_SIZE_32KB)
201#define PM_HUGE_MASK PM_64M
202#elif defined(CONFIG_PAGE_SIZE_64KB)
203#define PM_HUGE_MASK PM_256M
204#elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
205#error Bad page size configuration for hugetlbfs!
206#endif
207
208/*
209 * Values used for computation of new tlb entries
210 */
211#define PL_4K 12
212#define PL_16K 14
213#define PL_64K 16
214#define PL_256K 18
215#define PL_1M 20
216#define PL_4M 22
217#define PL_16M 24
218#define PL_64M 26
219#define PL_256M 28
220
221/*
222 * PageGrain bits
223 */
224#define PG_RIE (_ULCAST_(1) << 31)
225#define PG_XIE (_ULCAST_(1) << 30)
226#define PG_ELPA (_ULCAST_(1) << 29)
227#define PG_ESP (_ULCAST_(1) << 28)
228#define PG_IEC (_ULCAST_(1) << 27)
229
230/* MIPS32/64 EntryHI bit definitions */
231#define MIPS_ENTRYHI_EHINV (_ULCAST_(1) << 10)
232
233/*
234 * R4x00 interrupt enable / cause bits
235 */
236#define IE_SW0 (_ULCAST_(1) << 8)
237#define IE_SW1 (_ULCAST_(1) << 9)
238#define IE_IRQ0 (_ULCAST_(1) << 10)
239#define IE_IRQ1 (_ULCAST_(1) << 11)
240#define IE_IRQ2 (_ULCAST_(1) << 12)
241#define IE_IRQ3 (_ULCAST_(1) << 13)
242#define IE_IRQ4 (_ULCAST_(1) << 14)
243#define IE_IRQ5 (_ULCAST_(1) << 15)
244
245/*
246 * R4x00 interrupt cause bits
247 */
248#define C_SW0 (_ULCAST_(1) << 8)
249#define C_SW1 (_ULCAST_(1) << 9)
250#define C_IRQ0 (_ULCAST_(1) << 10)
251#define C_IRQ1 (_ULCAST_(1) << 11)
252#define C_IRQ2 (_ULCAST_(1) << 12)
253#define C_IRQ3 (_ULCAST_(1) << 13)
254#define C_IRQ4 (_ULCAST_(1) << 14)
255#define C_IRQ5 (_ULCAST_(1) << 15)
256
257/*
258 * Bitfields in the R4xx0 cp0 status register
259 */
260#define ST0_IE 0x00000001
261#define ST0_EXL 0x00000002
262#define ST0_ERL 0x00000004
263#define ST0_KSU 0x00000018
264# define KSU_USER 0x00000010
265# define KSU_SUPERVISOR 0x00000008
266# define KSU_KERNEL 0x00000000
267#define ST0_UX 0x00000020
268#define ST0_SX 0x00000040
269#define ST0_KX 0x00000080
270#define ST0_DE 0x00010000
271#define ST0_CE 0x00020000
272
273/*
274 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
275 * cacheops in userspace. This bit exists only on RM7000 and RM9000
276 * processors.
277 */
278#define ST0_CO 0x08000000
279
280/*
281 * Bitfields in the R[23]000 cp0 status register.
282 */
283#define ST0_IEC 0x00000001
284#define ST0_KUC 0x00000002
285#define ST0_IEP 0x00000004
286#define ST0_KUP 0x00000008
287#define ST0_IEO 0x00000010
288#define ST0_KUO 0x00000020
289/* bits 6 & 7 are reserved on R[23]000 */
290#define ST0_ISC 0x00010000
291#define ST0_SWC 0x00020000
292#define ST0_CM 0x00080000
293
294/*
295 * Bits specific to the R4640/R4650
296 */
297#define ST0_UM (_ULCAST_(1) << 4)
298#define ST0_IL (_ULCAST_(1) << 23)
299#define ST0_DL (_ULCAST_(1) << 24)
300
301/*
302 * Enable the MIPS MDMX and DSP ASEs
303 */
304#define ST0_MX 0x01000000
305
306/*
307 * Status register bits available in all MIPS CPUs.
308 */
309#define ST0_IM 0x0000ff00
310#define STATUSB_IP0 8
311#define STATUSF_IP0 (_ULCAST_(1) << 8)
312#define STATUSB_IP1 9
313#define STATUSF_IP1 (_ULCAST_(1) << 9)
314#define STATUSB_IP2 10
315#define STATUSF_IP2 (_ULCAST_(1) << 10)
316#define STATUSB_IP3 11
317#define STATUSF_IP3 (_ULCAST_(1) << 11)
318#define STATUSB_IP4 12
319#define STATUSF_IP4 (_ULCAST_(1) << 12)
320#define STATUSB_IP5 13
321#define STATUSF_IP5 (_ULCAST_(1) << 13)
322#define STATUSB_IP6 14
323#define STATUSF_IP6 (_ULCAST_(1) << 14)
324#define STATUSB_IP7 15
325#define STATUSF_IP7 (_ULCAST_(1) << 15)
326#define STATUSB_IP8 0
327#define STATUSF_IP8 (_ULCAST_(1) << 0)
328#define STATUSB_IP9 1
329#define STATUSF_IP9 (_ULCAST_(1) << 1)
330#define STATUSB_IP10 2
331#define STATUSF_IP10 (_ULCAST_(1) << 2)
332#define STATUSB_IP11 3
333#define STATUSF_IP11 (_ULCAST_(1) << 3)
334#define STATUSB_IP12 4
335#define STATUSF_IP12 (_ULCAST_(1) << 4)
336#define STATUSB_IP13 5
337#define STATUSF_IP13 (_ULCAST_(1) << 5)
338#define STATUSB_IP14 6
339#define STATUSF_IP14 (_ULCAST_(1) << 6)
340#define STATUSB_IP15 7
341#define STATUSF_IP15 (_ULCAST_(1) << 7)
342#define ST0_CH 0x00040000
343#define ST0_NMI 0x00080000
344#define ST0_SR 0x00100000
345#define ST0_TS 0x00200000
346#define ST0_BEV 0x00400000
347#define ST0_RE 0x02000000
348#define ST0_FR 0x04000000
349#define ST0_CU 0xf0000000
350#define ST0_CU0 0x10000000
351#define ST0_CU1 0x20000000
352#define ST0_CU2 0x40000000
353#define ST0_CU3 0x80000000
354#define ST0_XX 0x80000000 /* MIPS IV naming */
355
356/*
357 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
358 */
359#define INTCTLB_IPFDC 23
360#define INTCTLF_IPFDC (_ULCAST_(7) << INTCTLB_IPFDC)
361#define INTCTLB_IPPCI 26
362#define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
363#define INTCTLB_IPTI 29
364#define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
365
366/*
367 * Bitfields and bit numbers in the coprocessor 0 cause register.
368 *
369 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
370 */
371#define CAUSEB_EXCCODE 2
372#define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
373#define CAUSEB_IP 8
374#define CAUSEF_IP (_ULCAST_(255) << 8)
375#define CAUSEB_IP0 8
376#define CAUSEF_IP0 (_ULCAST_(1) << 8)
377#define CAUSEB_IP1 9
378#define CAUSEF_IP1 (_ULCAST_(1) << 9)
379#define CAUSEB_IP2 10
380#define CAUSEF_IP2 (_ULCAST_(1) << 10)
381#define CAUSEB_IP3 11
382#define CAUSEF_IP3 (_ULCAST_(1) << 11)
383#define CAUSEB_IP4 12
384#define CAUSEF_IP4 (_ULCAST_(1) << 12)
385#define CAUSEB_IP5 13
386#define CAUSEF_IP5 (_ULCAST_(1) << 13)
387#define CAUSEB_IP6 14
388#define CAUSEF_IP6 (_ULCAST_(1) << 14)
389#define CAUSEB_IP7 15
390#define CAUSEF_IP7 (_ULCAST_(1) << 15)
391#define CAUSEB_FDCI 21
392#define CAUSEF_FDCI (_ULCAST_(1) << 21)
393#define CAUSEB_IV 23
394#define CAUSEF_IV (_ULCAST_(1) << 23)
395#define CAUSEB_PCI 26
396#define CAUSEF_PCI (_ULCAST_(1) << 26)
397#define CAUSEB_DC 27
398#define CAUSEF_DC (_ULCAST_(1) << 27)
399#define CAUSEB_CE 28
400#define CAUSEF_CE (_ULCAST_(3) << 28)
401#define CAUSEB_TI 30
402#define CAUSEF_TI (_ULCAST_(1) << 30)
403#define CAUSEB_BD 31
404#define CAUSEF_BD (_ULCAST_(1) << 31)
405
406/*
407 * Cause.ExcCode trap codes.
408 */
409#define EXCCODE_INT 0 /* Interrupt pending */
410#define EXCCODE_MOD 1 /* TLB modified fault */
411#define EXCCODE_TLBL 2 /* TLB miss on load or ifetch */
412#define EXCCODE_TLBS 3 /* TLB miss on a store */
413#define EXCCODE_ADEL 4 /* Address error on a load or ifetch */
414#define EXCCODE_ADES 5 /* Address error on a store */
415#define EXCCODE_IBE 6 /* Bus error on an ifetch */
416#define EXCCODE_DBE 7 /* Bus error on a load or store */
417#define EXCCODE_SYS 8 /* System call */
418#define EXCCODE_BP 9 /* Breakpoint */
419#define EXCCODE_RI 10 /* Reserved instruction exception */
420#define EXCCODE_CPU 11 /* Coprocessor unusable */
421#define EXCCODE_OV 12 /* Arithmetic overflow */
422#define EXCCODE_TR 13 /* Trap instruction */
423#define EXCCODE_MSAFPE 14 /* MSA floating point exception */
424#define EXCCODE_FPE 15 /* Floating point exception */
425#define EXCCODE_TLBRI 19 /* TLB Read-Inhibit exception */
426#define EXCCODE_TLBXI 20 /* TLB Execution-Inhibit exception */
427#define EXCCODE_MSADIS 21 /* MSA disabled exception */
428#define EXCCODE_MDMX 22 /* MDMX unusable exception */
429#define EXCCODE_WATCH 23 /* Watch address reference */
430#define EXCCODE_MCHECK 24 /* Machine check */
431#define EXCCODE_THREAD 25 /* Thread exceptions (MT) */
432#define EXCCODE_DSPDIS 26 /* DSP disabled exception */
433#define EXCCODE_GE 27 /* Virtualized guest exception (VZ) */
434
435/* Implementation specific trap codes used by MIPS cores */
436#define MIPS_EXCCODE_TLBPAR 16 /* TLB parity error exception */
437
438/*
439 * Bits in the coprocessor 0 config register.
440 */
441/* Generic bits. */
442#define CONF_CM_CACHABLE_NO_WA 0
443#define CONF_CM_CACHABLE_WA 1
444#define CONF_CM_UNCACHED 2
445#define CONF_CM_CACHABLE_NONCOHERENT 3
446#define CONF_CM_CACHABLE_CE 4
447#define CONF_CM_CACHABLE_COW 5
448#define CONF_CM_CACHABLE_CUW 6
449#define CONF_CM_CACHABLE_ACCELERATED 7
450#define CONF_CM_CMASK 7
451#define CONF_BE (_ULCAST_(1) << 15)
452
453/* Bits common to various processors. */
454#define CONF_CU (_ULCAST_(1) << 3)
455#define CONF_DB (_ULCAST_(1) << 4)
456#define CONF_IB (_ULCAST_(1) << 5)
457#define CONF_DC (_ULCAST_(7) << 6)
458#define CONF_IC (_ULCAST_(7) << 9)
459#define CONF_EB (_ULCAST_(1) << 13)
460#define CONF_EM (_ULCAST_(1) << 14)
461#define CONF_SM (_ULCAST_(1) << 16)
462#define CONF_SC (_ULCAST_(1) << 17)
463#define CONF_EW (_ULCAST_(3) << 18)
464#define CONF_EP (_ULCAST_(15)<< 24)
465#define CONF_EC (_ULCAST_(7) << 28)
466#define CONF_CM (_ULCAST_(1) << 31)
467
468/* Bits specific to the R4xx0. */
469#define R4K_CONF_SW (_ULCAST_(1) << 20)
470#define R4K_CONF_SS (_ULCAST_(1) << 21)
471#define R4K_CONF_SB (_ULCAST_(3) << 22)
472
473/* Bits specific to the R5000. */
474#define R5K_CONF_SE (_ULCAST_(1) << 12)
475#define R5K_CONF_SS (_ULCAST_(3) << 20)
476
477/* Bits specific to the RM7000. */
478#define RM7K_CONF_SE (_ULCAST_(1) << 3)
479#define RM7K_CONF_TE (_ULCAST_(1) << 12)
480#define RM7K_CONF_CLK (_ULCAST_(1) << 16)
481#define RM7K_CONF_TC (_ULCAST_(1) << 17)
482#define RM7K_CONF_SI (_ULCAST_(3) << 20)
483#define RM7K_CONF_SC (_ULCAST_(1) << 31)
484
485/* Bits specific to the R10000. */
486#define R10K_CONF_DN (_ULCAST_(3) << 3)
487#define R10K_CONF_CT (_ULCAST_(1) << 5)
488#define R10K_CONF_PE (_ULCAST_(1) << 6)
489#define R10K_CONF_PM (_ULCAST_(3) << 7)
490#define R10K_CONF_EC (_ULCAST_(15)<< 9)
491#define R10K_CONF_SB (_ULCAST_(1) << 13)
492#define R10K_CONF_SK (_ULCAST_(1) << 14)
493#define R10K_CONF_SS (_ULCAST_(7) << 16)
494#define R10K_CONF_SC (_ULCAST_(7) << 19)
495#define R10K_CONF_DC (_ULCAST_(7) << 26)
496#define R10K_CONF_IC (_ULCAST_(7) << 29)
497
498/* Bits specific to the VR41xx. */
499#define VR41_CONF_CS (_ULCAST_(1) << 12)
500#define VR41_CONF_P4K (_ULCAST_(1) << 13)
501#define VR41_CONF_BP (_ULCAST_(1) << 16)
502#define VR41_CONF_M16 (_ULCAST_(1) << 20)
503#define VR41_CONF_AD (_ULCAST_(1) << 23)
504
505/* Bits specific to the R30xx. */
506#define R30XX_CONF_FDM (_ULCAST_(1) << 19)
507#define R30XX_CONF_REV (_ULCAST_(1) << 22)
508#define R30XX_CONF_AC (_ULCAST_(1) << 23)
509#define R30XX_CONF_RF (_ULCAST_(1) << 24)
510#define R30XX_CONF_HALT (_ULCAST_(1) << 25)
511#define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
512#define R30XX_CONF_DBR (_ULCAST_(1) << 29)
513#define R30XX_CONF_SB (_ULCAST_(1) << 30)
514#define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
515
516/* Bits specific to the TX49. */
517#define TX49_CONF_DC (_ULCAST_(1) << 16)
518#define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
519#define TX49_CONF_HALT (_ULCAST_(1) << 18)
520#define TX49_CONF_CWFON (_ULCAST_(1) << 27)
521
522/* Bits specific to the MIPS32/64 PRA. */
523#define MIPS_CONF_MT (_ULCAST_(7) << 7)
524#define MIPS_CONF_MT_TLB (_ULCAST_(1) << 7)
525#define MIPS_CONF_MT_FTLB (_ULCAST_(4) << 7)
526#define MIPS_CONF_AR (_ULCAST_(7) << 10)
527#define MIPS_CONF_AT (_ULCAST_(3) << 13)
528#define MIPS_CONF_M (_ULCAST_(1) << 31)
529
530/*
531 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
532 */
533#define MIPS_CONF1_FP (_ULCAST_(1) << 0)
534#define MIPS_CONF1_EP (_ULCAST_(1) << 1)
535#define MIPS_CONF1_CA (_ULCAST_(1) << 2)
536#define MIPS_CONF1_WR (_ULCAST_(1) << 3)
537#define MIPS_CONF1_PC (_ULCAST_(1) << 4)
538#define MIPS_CONF1_MD (_ULCAST_(1) << 5)
539#define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
540#define MIPS_CONF1_DA_SHF 7
541#define MIPS_CONF1_DA_SZ 3
542#define MIPS_CONF1_DA (_ULCAST_(7) << 7)
543#define MIPS_CONF1_DL_SHF 10
544#define MIPS_CONF1_DL_SZ 3
545#define MIPS_CONF1_DL (_ULCAST_(7) << 10)
546#define MIPS_CONF1_DS_SHF 13
547#define MIPS_CONF1_DS_SZ 3
548#define MIPS_CONF1_DS (_ULCAST_(7) << 13)
549#define MIPS_CONF1_IA_SHF 16
550#define MIPS_CONF1_IA_SZ 3
551#define MIPS_CONF1_IA (_ULCAST_(7) << 16)
552#define MIPS_CONF1_IL_SHF 19
553#define MIPS_CONF1_IL_SZ 3
554#define MIPS_CONF1_IL (_ULCAST_(7) << 19)
555#define MIPS_CONF1_IS_SHF 22
556#define MIPS_CONF1_IS_SZ 3
557#define MIPS_CONF1_IS (_ULCAST_(7) << 22)
558#define MIPS_CONF1_TLBS_SHIFT (25)
559#define MIPS_CONF1_TLBS_SIZE (6)
560#define MIPS_CONF1_TLBS (_ULCAST_(63) << MIPS_CONF1_TLBS_SHIFT)
561
562#define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
563#define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
564#define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
565#define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
566#define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
567#define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
568#define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
569#define MIPS_CONF2_TU (_ULCAST_(7) << 28)
570
571#define MIPS_CONF3_TL (_ULCAST_(1) << 0)
572#define MIPS_CONF3_SM (_ULCAST_(1) << 1)
573#define MIPS_CONF3_MT (_ULCAST_(1) << 2)
574#define MIPS_CONF3_CDMM (_ULCAST_(1) << 3)
575#define MIPS_CONF3_SP (_ULCAST_(1) << 4)
576#define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
577#define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
578#define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
579#define MIPS_CONF3_ITL (_ULCAST_(1) << 8)
580#define MIPS_CONF3_CTXTC (_ULCAST_(1) << 9)
581#define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
582#define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
583#define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
584#define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
585#define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
586#define MIPS_CONF3_ISA_OE (_ULCAST_(1) << 16)
587#define MIPS_CONF3_MCU (_ULCAST_(1) << 17)
588#define MIPS_CONF3_MMAR (_ULCAST_(7) << 18)
589#define MIPS_CONF3_IPLW (_ULCAST_(3) << 21)
590#define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
591#define MIPS_CONF3_PW (_ULCAST_(1) << 24)
592#define MIPS_CONF3_SC (_ULCAST_(1) << 25)
593#define MIPS_CONF3_BI (_ULCAST_(1) << 26)
594#define MIPS_CONF3_BP (_ULCAST_(1) << 27)
595#define MIPS_CONF3_MSA (_ULCAST_(1) << 28)
596#define MIPS_CONF3_CMGCR (_ULCAST_(1) << 29)
597#define MIPS_CONF3_BPG (_ULCAST_(1) << 30)
598
599#define MIPS_CONF4_MMUSIZEEXT_SHIFT (0)
600#define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
601#define MIPS_CONF4_FTLBSETS_SHIFT (0)
602#define MIPS_CONF4_FTLBSETS (_ULCAST_(15) << MIPS_CONF4_FTLBSETS_SHIFT)
603#define MIPS_CONF4_FTLBWAYS_SHIFT (4)
604#define MIPS_CONF4_FTLBWAYS (_ULCAST_(15) << MIPS_CONF4_FTLBWAYS_SHIFT)
605#define MIPS_CONF4_FTLBPAGESIZE_SHIFT (8)
606/* bits 10:8 in FTLB-only configurations */
607#define MIPS_CONF4_FTLBPAGESIZE (_ULCAST_(7) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
608/* bits 12:8 in VTLB-FTLB only configurations */
609#define MIPS_CONF4_VFTLBPAGESIZE (_ULCAST_(31) << MIPS_CONF4_FTLBPAGESIZE_SHIFT)
610#define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
611#define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
612#define MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT (_ULCAST_(2) << 14)
613#define MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT (_ULCAST_(3) << 14)
614#define MIPS_CONF4_KSCREXIST (_ULCAST_(255) << 16)
615#define MIPS_CONF4_VTLBSIZEEXT_SHIFT (24)
616#define MIPS_CONF4_VTLBSIZEEXT (_ULCAST_(15) << MIPS_CONF4_VTLBSIZEEXT_SHIFT)
617#define MIPS_CONF4_AE (_ULCAST_(1) << 28)
618#define MIPS_CONF4_IE (_ULCAST_(3) << 29)
619#define MIPS_CONF4_TLBINV (_ULCAST_(2) << 29)
620
621#define MIPS_CONF5_NF (_ULCAST_(1) << 0)
622#define MIPS_CONF5_UFR (_ULCAST_(1) << 2)
623#define MIPS_CONF5_MRP (_ULCAST_(1) << 3)
624#define MIPS_CONF5_LLB (_ULCAST_(1) << 4)
625#define MIPS_CONF5_MVH (_ULCAST_(1) << 5)
626#define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
627#define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
628#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
629#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
630#define MIPS_CONF5_CV (_ULCAST_(1) << 29)
631#define MIPS_CONF5_K (_ULCAST_(1) << 30)
632
633#define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
634/* proAptiv FTLB on/off bit */
635#define MIPS_CONF6_FTLBEN (_ULCAST_(1) << 15)
636/* FTLB probability bits */
637#define MIPS_CONF6_FTLBP_SHIFT (16)
638
639#define MIPS_CONF7_WII (_ULCAST_(1) << 31)
640
641#define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
642
643#define MIPS_CONF7_IAR (_ULCAST_(1) << 10)
644#define MIPS_CONF7_AR (_ULCAST_(1) << 16)
645/* FTLB probability bits for R6 */
646#define MIPS_CONF7_FTLBP_SHIFT (18)
647
648/* MAAR bit definitions */
649#define MIPS_MAAR_ADDR ((BIT_ULL(BITS_PER_LONG - 12) - 1) << 12)
650#define MIPS_MAAR_ADDR_SHIFT 12
651#define MIPS_MAAR_S (_ULCAST_(1) << 1)
652#define MIPS_MAAR_V (_ULCAST_(1) << 0)
653
654/* CMGCRBase bit definitions */
655#define MIPS_CMGCRB_BASE 11
656#define MIPS_CMGCRF_BASE (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
657
658/*
659 * Bits in the MIPS32 Memory Segmentation registers.
660 */
661#define MIPS_SEGCFG_PA_SHIFT 9
662#define MIPS_SEGCFG_PA (_ULCAST_(127) << MIPS_SEGCFG_PA_SHIFT)
663#define MIPS_SEGCFG_AM_SHIFT 4
664#define MIPS_SEGCFG_AM (_ULCAST_(7) << MIPS_SEGCFG_AM_SHIFT)
665#define MIPS_SEGCFG_EU_SHIFT 3
666#define MIPS_SEGCFG_EU (_ULCAST_(1) << MIPS_SEGCFG_EU_SHIFT)
667#define MIPS_SEGCFG_C_SHIFT 0
668#define MIPS_SEGCFG_C (_ULCAST_(7) << MIPS_SEGCFG_C_SHIFT)
669
670#define MIPS_SEGCFG_UUSK _ULCAST_(7)
671#define MIPS_SEGCFG_USK _ULCAST_(5)
672#define MIPS_SEGCFG_MUSUK _ULCAST_(4)
673#define MIPS_SEGCFG_MUSK _ULCAST_(3)
674#define MIPS_SEGCFG_MSK _ULCAST_(2)
675#define MIPS_SEGCFG_MK _ULCAST_(1)
676#define MIPS_SEGCFG_UK _ULCAST_(0)
677
678#define MIPS_PWFIELD_GDI_SHIFT 24
679#define MIPS_PWFIELD_GDI_MASK 0x3f000000
680#define MIPS_PWFIELD_UDI_SHIFT 18
681#define MIPS_PWFIELD_UDI_MASK 0x00fc0000
682#define MIPS_PWFIELD_MDI_SHIFT 12
683#define MIPS_PWFIELD_MDI_MASK 0x0003f000
684#define MIPS_PWFIELD_PTI_SHIFT 6
685#define MIPS_PWFIELD_PTI_MASK 0x00000fc0
686#define MIPS_PWFIELD_PTEI_SHIFT 0
687#define MIPS_PWFIELD_PTEI_MASK 0x0000003f
688
689#define MIPS_PWSIZE_GDW_SHIFT 24
690#define MIPS_PWSIZE_GDW_MASK 0x3f000000
691#define MIPS_PWSIZE_UDW_SHIFT 18
692#define MIPS_PWSIZE_UDW_MASK 0x00fc0000
693#define MIPS_PWSIZE_MDW_SHIFT 12
694#define MIPS_PWSIZE_MDW_MASK 0x0003f000
695#define MIPS_PWSIZE_PTW_SHIFT 6
696#define MIPS_PWSIZE_PTW_MASK 0x00000fc0
697#define MIPS_PWSIZE_PTEW_SHIFT 0
698#define MIPS_PWSIZE_PTEW_MASK 0x0000003f
699
700#define MIPS_PWCTL_PWEN_SHIFT 31
701#define MIPS_PWCTL_PWEN_MASK 0x80000000
702#define MIPS_PWCTL_DPH_SHIFT 7
703#define MIPS_PWCTL_DPH_MASK 0x00000080
704#define MIPS_PWCTL_HUGEPG_SHIFT 6
705#define MIPS_PWCTL_HUGEPG_MASK 0x00000060
706#define MIPS_PWCTL_PSN_SHIFT 0
707#define MIPS_PWCTL_PSN_MASK 0x0000003f
708
709/* CDMMBase register bit definitions */
710#define MIPS_CDMMBASE_SIZE_SHIFT 0
711#define MIPS_CDMMBASE_SIZE (_ULCAST_(511) << MIPS_CDMMBASE_SIZE_SHIFT)
712#define MIPS_CDMMBASE_CI (_ULCAST_(1) << 9)
713#define MIPS_CDMMBASE_EN (_ULCAST_(1) << 10)
714#define MIPS_CDMMBASE_ADDR_SHIFT 11
715#define MIPS_CDMMBASE_ADDR_START 15
716
717/*
718 * Bitfields in the TX39 family CP0 Configuration Register 3
719 */
720#define TX39_CONF_ICS_SHIFT 19
721#define TX39_CONF_ICS_MASK 0x00380000
722#define TX39_CONF_ICS_1KB 0x00000000
723#define TX39_CONF_ICS_2KB 0x00080000
724#define TX39_CONF_ICS_4KB 0x00100000
725#define TX39_CONF_ICS_8KB 0x00180000
726#define TX39_CONF_ICS_16KB 0x00200000
727
728#define TX39_CONF_DCS_SHIFT 16
729#define TX39_CONF_DCS_MASK 0x00070000
730#define TX39_CONF_DCS_1KB 0x00000000
731#define TX39_CONF_DCS_2KB 0x00010000
732#define TX39_CONF_DCS_4KB 0x00020000
733#define TX39_CONF_DCS_8KB 0x00030000
734#define TX39_CONF_DCS_16KB 0x00040000
735
736#define TX39_CONF_CWFON 0x00004000
737#define TX39_CONF_WBON 0x00002000
738#define TX39_CONF_RF_SHIFT 10
739#define TX39_CONF_RF_MASK 0x00000c00
740#define TX39_CONF_DOZE 0x00000200
741#define TX39_CONF_HALT 0x00000100
742#define TX39_CONF_LOCK 0x00000080
743#define TX39_CONF_ICE 0x00000020
744#define TX39_CONF_DCE 0x00000010
745#define TX39_CONF_IRSIZE_SHIFT 2
746#define TX39_CONF_IRSIZE_MASK 0x0000000c
747#define TX39_CONF_DRSIZE_SHIFT 0
748#define TX39_CONF_DRSIZE_MASK 0x00000003
749
750/*
751 * Interesting Bits in the R10K CP0 Branch Diagnostic Register
752 */
753/* Disable Branch Target Address Cache */
754#define R10K_DIAG_D_BTAC (_ULCAST_(1) << 27)
755/* Enable Branch Prediction Global History */
756#define R10K_DIAG_E_GHIST (_ULCAST_(1) << 26)
757/* Disable Branch Return Cache */
758#define R10K_DIAG_D_BRC (_ULCAST_(1) << 22)
759
760/*
761 * Coprocessor 1 (FPU) register names
762 */
763#define CP1_REVISION $0
764#define CP1_UFR $1
765#define CP1_UNFR $4
766#define CP1_FCCR $25
767#define CP1_FEXR $26
768#define CP1_FENR $28
769#define CP1_STATUS $31
770
771
772/*
773 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
774 */
775#define MIPS_FPIR_S (_ULCAST_(1) << 16)
776#define MIPS_FPIR_D (_ULCAST_(1) << 17)
777#define MIPS_FPIR_PS (_ULCAST_(1) << 18)
778#define MIPS_FPIR_3D (_ULCAST_(1) << 19)
779#define MIPS_FPIR_W (_ULCAST_(1) << 20)
780#define MIPS_FPIR_L (_ULCAST_(1) << 21)
781#define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
782#define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
783#define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
784#define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
785
786/*
787 * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
788 */
789#define MIPS_FCCR_CONDX_S 0
790#define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
791#define MIPS_FCCR_COND0_S 0
792#define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
793#define MIPS_FCCR_COND1_S 1
794#define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
795#define MIPS_FCCR_COND2_S 2
796#define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
797#define MIPS_FCCR_COND3_S 3
798#define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
799#define MIPS_FCCR_COND4_S 4
800#define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
801#define MIPS_FCCR_COND5_S 5
802#define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
803#define MIPS_FCCR_COND6_S 6
804#define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
805#define MIPS_FCCR_COND7_S 7
806#define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
807
808/*
809 * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
810 */
811#define MIPS_FENR_FS_S 2
812#define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
813
814/*
815 * FPU Status Register Values
816 */
817#define FPU_CSR_COND_S 23 /* $fcc0 */
818#define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
819
820#define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
821#define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
822
823#define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
824#define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
825#define FPU_CSR_COND1_S 25 /* $fcc1 */
826#define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
827#define FPU_CSR_COND2_S 26 /* $fcc2 */
828#define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
829#define FPU_CSR_COND3_S 27 /* $fcc3 */
830#define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
831#define FPU_CSR_COND4_S 28 /* $fcc4 */
832#define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
833#define FPU_CSR_COND5_S 29 /* $fcc5 */
834#define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
835#define FPU_CSR_COND6_S 30 /* $fcc6 */
836#define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
837#define FPU_CSR_COND7_S 31 /* $fcc7 */
838#define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
839
840/*
841 * Bits 22:20 of the FPU Status Register will be read as 0,
842 * and should be written as zero.
843 */
844#define FPU_CSR_RSVD (_ULCAST_(7) << 20)
845
846#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
847#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
848
849/*
850 * X the exception cause indicator
851 * E the exception enable
852 * S the sticky/flag bit
853*/
854#define FPU_CSR_ALL_X 0x0003f000
855#define FPU_CSR_UNI_X 0x00020000
856#define FPU_CSR_INV_X 0x00010000
857#define FPU_CSR_DIV_X 0x00008000
858#define FPU_CSR_OVF_X 0x00004000
859#define FPU_CSR_UDF_X 0x00002000
860#define FPU_CSR_INE_X 0x00001000
861
862#define FPU_CSR_ALL_E 0x00000f80
863#define FPU_CSR_INV_E 0x00000800
864#define FPU_CSR_DIV_E 0x00000400
865#define FPU_CSR_OVF_E 0x00000200
866#define FPU_CSR_UDF_E 0x00000100
867#define FPU_CSR_INE_E 0x00000080
868
869#define FPU_CSR_ALL_S 0x0000007c
870#define FPU_CSR_INV_S 0x00000040
871#define FPU_CSR_DIV_S 0x00000020
872#define FPU_CSR_OVF_S 0x00000010
873#define FPU_CSR_UDF_S 0x00000008
874#define FPU_CSR_INE_S 0x00000004
875
876/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
877#define FPU_CSR_RM 0x00000003
878#define FPU_CSR_RN 0x0 /* nearest */
879#define FPU_CSR_RZ 0x1 /* towards zero */
880#define FPU_CSR_RU 0x2 /* towards +Infinity */
881#define FPU_CSR_RD 0x3 /* towards -Infinity */
882
883
884#ifndef __ASSEMBLY__
885
886/*
887 * Macros for handling the ISA mode bit for MIPS16 and microMIPS.
888 */
889#if defined(CONFIG_SYS_SUPPORTS_MIPS16) || \
890 defined(CONFIG_SYS_SUPPORTS_MICROMIPS)
891#define get_isa16_mode(x) ((x) & 0x1)
892#define msk_isa16_mode(x) ((x) & ~0x1)
893#define set_isa16_mode(x) do { (x) |= 0x1; } while(0)
894#else
895#define get_isa16_mode(x) 0
896#define msk_isa16_mode(x) (x)
897#define set_isa16_mode(x) do { } while(0)
898#endif
899
900/*
901 * microMIPS instructions can be 16-bit or 32-bit in length. This
902 * returns a 1 if the instruction is 16-bit and a 0 if 32-bit.
903 */
904static inline int mm_insn_16bit(u16 insn)
905{
906 u16 opcode = (insn >> 10) & 0x7;
907
908 return (opcode >= 1 && opcode <= 3) ? 1 : 0;
909}
910
911/*
912 * TLB Invalidate Flush
913 */
914static inline void tlbinvf(void)
915{
916 __asm__ __volatile__(
917 ".set push\n\t"
918 ".set noreorder\n\t"
919 ".word 0x42000004\n\t" /* tlbinvf */
920 ".set pop");
921}
922
923
924/*
925 * Functions to access the R10000 performance counters. These are basically
926 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
927 * performance counter number encoded into bits 1 ... 5 of the instruction.
928 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
929 * disassembler these will look like an access to sel 0 or 1.
930 */
931#define read_r10k_perf_cntr(counter) \
932({ \
933 unsigned int __res; \
934 __asm__ __volatile__( \
935 "mfpc\t%0, %1" \
936 : "=r" (__res) \
937 : "i" (counter)); \
938 \
939 __res; \
940})
941
942#define write_r10k_perf_cntr(counter,val) \
943do { \
944 __asm__ __volatile__( \
945 "mtpc\t%0, %1" \
946 : \
947 : "r" (val), "i" (counter)); \
948} while (0)
949
950#define read_r10k_perf_event(counter) \
951({ \
952 unsigned int __res; \
953 __asm__ __volatile__( \
954 "mfps\t%0, %1" \
955 : "=r" (__res) \
956 : "i" (counter)); \
957 \
958 __res; \
959})
960
961#define write_r10k_perf_cntl(counter,val) \
962do { \
963 __asm__ __volatile__( \
964 "mtps\t%0, %1" \
965 : \
966 : "r" (val), "i" (counter)); \
967} while (0)
968
969
970/*
971 * Macros to access the system control coprocessor
972 */
973
974#define __read_32bit_c0_register(source, sel) \
975({ unsigned int __res; \
976 if (sel == 0) \
977 __asm__ __volatile__( \
978 "mfc0\t%0, " #source "\n\t" \
979 : "=r" (__res)); \
980 else \
981 __asm__ __volatile__( \
982 ".set\tmips32\n\t" \
983 "mfc0\t%0, " #source ", " #sel "\n\t" \
984 ".set\tmips0\n\t" \
985 : "=r" (__res)); \
986 __res; \
987})
988
989#define __read_64bit_c0_register(source, sel) \
990({ unsigned long long __res; \
991 if (sizeof(unsigned long) == 4) \
992 __res = __read_64bit_c0_split(source, sel); \
993 else if (sel == 0) \
994 __asm__ __volatile__( \
995 ".set\tmips3\n\t" \
996 "dmfc0\t%0, " #source "\n\t" \
997 ".set\tmips0" \
998 : "=r" (__res)); \
999 else \
1000 __asm__ __volatile__( \
1001 ".set\tmips64\n\t" \
1002 "dmfc0\t%0, " #source ", " #sel "\n\t" \
1003 ".set\tmips0" \
1004 : "=r" (__res)); \
1005 __res; \
1006})
1007
1008#define __write_32bit_c0_register(register, sel, value) \
1009do { \
1010 if (sel == 0) \
1011 __asm__ __volatile__( \
1012 "mtc0\t%z0, " #register "\n\t" \
1013 : : "Jr" ((unsigned int)(value))); \
1014 else \
1015 __asm__ __volatile__( \
1016 ".set\tmips32\n\t" \
1017 "mtc0\t%z0, " #register ", " #sel "\n\t" \
1018 ".set\tmips0" \
1019 : : "Jr" ((unsigned int)(value))); \
1020} while (0)
1021
1022#define __write_64bit_c0_register(register, sel, value) \
1023do { \
1024 if (sizeof(unsigned long) == 4) \
1025 __write_64bit_c0_split(register, sel, value); \
1026 else if (sel == 0) \
1027 __asm__ __volatile__( \
1028 ".set\tmips3\n\t" \
1029 "dmtc0\t%z0, " #register "\n\t" \
1030 ".set\tmips0" \
1031 : : "Jr" (value)); \
1032 else \
1033 __asm__ __volatile__( \
1034 ".set\tmips64\n\t" \
1035 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
1036 ".set\tmips0" \
1037 : : "Jr" (value)); \
1038} while (0)
1039
1040#define __read_ulong_c0_register(reg, sel) \
1041 ((sizeof(unsigned long) == 4) ? \
1042 (unsigned long) __read_32bit_c0_register(reg, sel) : \
1043 (unsigned long) __read_64bit_c0_register(reg, sel))
1044
1045#define __write_ulong_c0_register(reg, sel, val) \
1046do { \
1047 if (sizeof(unsigned long) == 4) \
1048 __write_32bit_c0_register(reg, sel, val); \
1049 else \
1050 __write_64bit_c0_register(reg, sel, val); \
1051} while (0)
1052
1053/*
1054 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
1055 */
1056#define __read_32bit_c0_ctrl_register(source) \
1057({ unsigned int __res; \
1058 __asm__ __volatile__( \
1059 "cfc0\t%0, " #source "\n\t" \
1060 : "=r" (__res)); \
1061 __res; \
1062})
1063
1064#define __write_32bit_c0_ctrl_register(register, value) \
1065do { \
1066 __asm__ __volatile__( \
1067 "ctc0\t%z0, " #register "\n\t" \
1068 : : "Jr" ((unsigned int)(value))); \
1069} while (0)
1070
1071/*
1072 * These versions are only needed for systems with more than 38 bits of
1073 * physical address space running the 32-bit kernel. That's none atm :-)
1074 */
1075#define __read_64bit_c0_split(source, sel) \
1076({ \
1077 unsigned long long __val; \
1078 unsigned long __flags; \
1079 \
1080 local_irq_save(__flags); \
1081 if (sel == 0) \
1082 __asm__ __volatile__( \
1083 ".set\tmips64\n\t" \
1084 "dmfc0\t%M0, " #source "\n\t" \
1085 "dsll\t%L0, %M0, 32\n\t" \
1086 "dsra\t%M0, %M0, 32\n\t" \
1087 "dsra\t%L0, %L0, 32\n\t" \
1088 ".set\tmips0" \
1089 : "=r" (__val)); \
1090 else \
1091 __asm__ __volatile__( \
1092 ".set\tmips64\n\t" \
1093 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
1094 "dsll\t%L0, %M0, 32\n\t" \
1095 "dsra\t%M0, %M0, 32\n\t" \
1096 "dsra\t%L0, %L0, 32\n\t" \
1097 ".set\tmips0" \
1098 : "=r" (__val)); \
1099 local_irq_restore(__flags); \
1100 \
1101 __val; \
1102})
1103
1104#define __write_64bit_c0_split(source, sel, val) \
1105do { \
1106 unsigned long __flags; \
1107 \
1108 local_irq_save(__flags); \
1109 if (sel == 0) \
1110 __asm__ __volatile__( \
1111 ".set\tmips64\n\t" \
1112 "dsll\t%L0, %L0, 32\n\t" \
1113 "dsrl\t%L0, %L0, 32\n\t" \
1114 "dsll\t%M0, %M0, 32\n\t" \
1115 "or\t%L0, %L0, %M0\n\t" \
1116 "dmtc0\t%L0, " #source "\n\t" \
1117 ".set\tmips0" \
1118 : : "r" (val)); \
1119 else \
1120 __asm__ __volatile__( \
1121 ".set\tmips64\n\t" \
1122 "dsll\t%L0, %L0, 32\n\t" \
1123 "dsrl\t%L0, %L0, 32\n\t" \
1124 "dsll\t%M0, %M0, 32\n\t" \
1125 "or\t%L0, %L0, %M0\n\t" \
1126 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
1127 ".set\tmips0" \
1128 : : "r" (val)); \
1129 local_irq_restore(__flags); \
1130} while (0)
1131
1132#define __readx_32bit_c0_register(source) \
1133({ \
1134 unsigned int __res; \
1135 \
1136 __asm__ __volatile__( \
1137 " .set push \n" \
1138 " .set noat \n" \
1139 " .set mips32r2 \n" \
1140 " .insn \n" \
1141 " # mfhc0 $1, %1 \n" \
1142 " .word (0x40410000 | ((%1 & 0x1f) << 11)) \n" \
1143 " move %0, $1 \n" \
1144 " .set pop \n" \
1145 : "=r" (__res) \
1146 : "i" (source)); \
1147 __res; \
1148})
1149
1150#define __writex_32bit_c0_register(register, value) \
1151do { \
1152 __asm__ __volatile__( \
1153 " .set push \n" \
1154 " .set noat \n" \
1155 " .set mips32r2 \n" \
1156 " move $1, %0 \n" \
1157 " # mthc0 $1, %1 \n" \
1158 " .insn \n" \
1159 " .word (0x40c10000 | ((%1 & 0x1f) << 11)) \n" \
1160 " .set pop \n" \
1161 : \
1162 : "r" (value), "i" (register)); \
1163} while (0)
1164
1165#define read_c0_index() __read_32bit_c0_register($0, 0)
1166#define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
1167
1168#define read_c0_random() __read_32bit_c0_register($1, 0)
1169#define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
1170
1171#define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
1172#define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
1173
1174#define readx_c0_entrylo0() __readx_32bit_c0_register(2)
1175#define writex_c0_entrylo0(val) __writex_32bit_c0_register(2, val)
1176
1177#define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
1178#define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
1179
1180#define readx_c0_entrylo1() __readx_32bit_c0_register(3)
1181#define writex_c0_entrylo1(val) __writex_32bit_c0_register(3, val)
1182
1183#define read_c0_conf() __read_32bit_c0_register($3, 0)
1184#define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
1185
1186#define read_c0_context() __read_ulong_c0_register($4, 0)
1187#define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
1188
1189#define read_c0_userlocal() __read_ulong_c0_register($4, 2)
1190#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
1191
1192#define read_c0_pagemask() __read_32bit_c0_register($5, 0)
1193#define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
1194
1195#define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
1196#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
1197
1198#define read_c0_wired() __read_32bit_c0_register($6, 0)
1199#define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
1200
1201#define read_c0_info() __read_32bit_c0_register($7, 0)
1202
1203#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
1204#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
1205
1206#define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
1207#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
1208
1209#define read_c0_count() __read_32bit_c0_register($9, 0)
1210#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
1211
1212#define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
1213#define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
1214
1215#define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
1216#define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
1217
1218#define read_c0_entryhi() __read_ulong_c0_register($10, 0)
1219#define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
1220
1221#define read_c0_compare() __read_32bit_c0_register($11, 0)
1222#define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
1223
1224#define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
1225#define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
1226
1227#define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
1228#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
1229
1230#define read_c0_status() __read_32bit_c0_register($12, 0)
1231
1232#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
1233
1234#define read_c0_cause() __read_32bit_c0_register($13, 0)
1235#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
1236
1237#define read_c0_epc() __read_ulong_c0_register($14, 0)
1238#define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
1239
1240#define read_c0_prid() __read_32bit_c0_register($15, 0)
1241
1242#define read_c0_cmgcrbase() __read_ulong_c0_register($15, 3)
1243
1244#define read_c0_config() __read_32bit_c0_register($16, 0)
1245#define read_c0_config1() __read_32bit_c0_register($16, 1)
1246#define read_c0_config2() __read_32bit_c0_register($16, 2)
1247#define read_c0_config3() __read_32bit_c0_register($16, 3)
1248#define read_c0_config4() __read_32bit_c0_register($16, 4)
1249#define read_c0_config5() __read_32bit_c0_register($16, 5)
1250#define read_c0_config6() __read_32bit_c0_register($16, 6)
1251#define read_c0_config7() __read_32bit_c0_register($16, 7)
1252#define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
1253#define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
1254#define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
1255#define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
1256#define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
1257#define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
1258#define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
1259#define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
1260
1261#define read_c0_lladdr() __read_ulong_c0_register($17, 0)
1262#define write_c0_lladdr(val) __write_ulong_c0_register($17, 0, val)
1263#define read_c0_maar() __read_ulong_c0_register($17, 1)
1264#define write_c0_maar(val) __write_ulong_c0_register($17, 1, val)
1265#define read_c0_maari() __read_32bit_c0_register($17, 2)
1266#define write_c0_maari(val) __write_32bit_c0_register($17, 2, val)
1267
1268/*
1269 * The WatchLo register. There may be up to 8 of them.
1270 */
1271#define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
1272#define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
1273#define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
1274#define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
1275#define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
1276#define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
1277#define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
1278#define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
1279#define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
1280#define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
1281#define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
1282#define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
1283#define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
1284#define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
1285#define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
1286#define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
1287
1288/*
1289 * The WatchHi register. There may be up to 8 of them.
1290 */
1291#define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
1292#define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
1293#define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
1294#define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
1295#define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
1296#define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
1297#define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
1298#define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
1299
1300#define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
1301#define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
1302#define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
1303#define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
1304#define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
1305#define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
1306#define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
1307#define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
1308
1309#define read_c0_xcontext() __read_ulong_c0_register($20, 0)
1310#define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
1311
1312#define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
1313#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
1314
1315#define read_c0_framemask() __read_32bit_c0_register($21, 0)
1316#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
1317
1318#define read_c0_diag() __read_32bit_c0_register($22, 0)
1319#define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
1320
1321/* R10K CP0 Branch Diagnostic register is 64bits wide */
1322#define read_c0_r10k_diag() __read_64bit_c0_register($22, 0)
1323#define write_c0_r10k_diag(val) __write_64bit_c0_register($22, 0, val)
1324
1325#define read_c0_diag1() __read_32bit_c0_register($22, 1)
1326#define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
1327
1328#define read_c0_diag2() __read_32bit_c0_register($22, 2)
1329#define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
1330
1331#define read_c0_diag3() __read_32bit_c0_register($22, 3)
1332#define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
1333
1334#define read_c0_diag4() __read_32bit_c0_register($22, 4)
1335#define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
1336
1337#define read_c0_diag5() __read_32bit_c0_register($22, 5)
1338#define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
1339
1340#define read_c0_debug() __read_32bit_c0_register($23, 0)
1341#define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
1342
1343#define read_c0_depc() __read_ulong_c0_register($24, 0)
1344#define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
1345
1346/*
1347 * MIPS32 / MIPS64 performance counters
1348 */
1349#define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1350#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1351#define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
1352#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1353#define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
1354#define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1355#define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
1356#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1357#define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
1358#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1359#define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
1360#define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1361#define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
1362#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1363#define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
1364#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1365#define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
1366#define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1367#define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
1368#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1369#define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
1370#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1371#define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1372#define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1373
1374#define read_c0_ecc() __read_32bit_c0_register($26, 0)
1375#define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1376
1377#define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
1378#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1379
1380#define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1381
1382#define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1383#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1384
1385#define read_c0_taglo() __read_32bit_c0_register($28, 0)
1386#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1387
1388#define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
1389#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1390
1391#define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
1392#define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
1393
1394#define read_c0_staglo() __read_32bit_c0_register($28, 4)
1395#define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
1396
1397#define read_c0_taghi() __read_32bit_c0_register($29, 0)
1398#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1399
1400#define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1401#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1402
1403/* MIPSR2 */
1404#define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1405#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1406
1407#define read_c0_intctl() __read_32bit_c0_register($12, 1)
1408#define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1409
1410#define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1411#define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1412
1413#define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1414#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1415
1416#define read_c0_ebase() __read_32bit_c0_register($15, 1)
1417#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1418
1419#define read_c0_cdmmbase() __read_ulong_c0_register($15, 2)
1420#define write_c0_cdmmbase(val) __write_ulong_c0_register($15, 2, val)
1421
1422/* MIPSR3 */
1423#define read_c0_segctl0() __read_32bit_c0_register($5, 2)
1424#define write_c0_segctl0(val) __write_32bit_c0_register($5, 2, val)
1425
1426#define read_c0_segctl1() __read_32bit_c0_register($5, 3)
1427#define write_c0_segctl1(val) __write_32bit_c0_register($5, 3, val)
1428
1429#define read_c0_segctl2() __read_32bit_c0_register($5, 4)
1430#define write_c0_segctl2(val) __write_32bit_c0_register($5, 4, val)
1431
1432/* Hardware Page Table Walker */
1433#define read_c0_pwbase() __read_ulong_c0_register($5, 5)
1434#define write_c0_pwbase(val) __write_ulong_c0_register($5, 5, val)
1435
1436#define read_c0_pwfield() __read_ulong_c0_register($5, 6)
1437#define write_c0_pwfield(val) __write_ulong_c0_register($5, 6, val)
1438
1439#define read_c0_pwsize() __read_ulong_c0_register($5, 7)
1440#define write_c0_pwsize(val) __write_ulong_c0_register($5, 7, val)
1441
1442#define read_c0_pwctl() __read_32bit_c0_register($6, 6)
1443#define write_c0_pwctl(val) __write_32bit_c0_register($6, 6, val)
1444
1445/* Cavium OCTEON (cnMIPS) */
1446#define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1447#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1448
1449#define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1450#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1451
1452#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1453#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1454/*
1455 * The cacheerr registers are not standardized. On OCTEON, they are
1456 * 64 bits wide.
1457 */
1458#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1459#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1460
1461#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1462#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1463
1464/* BMIPS3300 */
1465#define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
1466#define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
1467
1468#define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
1469#define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
1470
1471#define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
1472#define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
1473
1474/* BMIPS43xx */
1475#define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
1476#define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
1477
1478#define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
1479#define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
1480
1481#define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
1482#define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
1483
1484#define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
1485#define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
1486
1487#define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
1488#define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
1489
1490/* BMIPS5000 */
1491#define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
1492#define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
1493
1494#define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
1495#define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
1496
1497#define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
1498#define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
1499
1500#define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
1501#define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
1502
1503#define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
1504#define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
1505
1506#define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
1507#define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
1508
1509/*
1510 * Macros to access the floating point coprocessor control registers
1511 */
1512#define _read_32bit_cp1_register(source, gas_hardfloat) \
1513({ \
1514 unsigned int __res; \
1515 \
1516 __asm__ __volatile__( \
1517 " .set push \n" \
1518 " .set reorder \n" \
1519 " # gas fails to assemble cfc1 for some archs, \n" \
1520 " # like Octeon. \n" \
1521 " .set mips1 \n" \
1522 " "STR(gas_hardfloat)" \n" \
1523 " cfc1 %0,"STR(source)" \n" \
1524 " .set pop \n" \
1525 : "=r" (__res)); \
1526 __res; \
1527})
1528
1529#define _write_32bit_cp1_register(dest, val, gas_hardfloat) \
1530do { \
1531 __asm__ __volatile__( \
1532 " .set push \n" \
1533 " .set reorder \n" \
1534 " "STR(gas_hardfloat)" \n" \
1535 " ctc1 %0,"STR(dest)" \n" \
1536 " .set pop \n" \
1537 : : "r" (val)); \
1538} while (0)
1539
1540#ifdef GAS_HAS_SET_HARDFLOAT
1541#define read_32bit_cp1_register(source) \
1542 _read_32bit_cp1_register(source, .set hardfloat)
1543#define write_32bit_cp1_register(dest, val) \
1544 _write_32bit_cp1_register(dest, val, .set hardfloat)
1545#else
1546#define read_32bit_cp1_register(source) \
1547 _read_32bit_cp1_register(source, )
1548#define write_32bit_cp1_register(dest, val) \
1549 _write_32bit_cp1_register(dest, val, )
1550#endif
1551
1552#ifdef HAVE_AS_DSP
1553#define rddsp(mask) \
1554({ \
1555 unsigned int __dspctl; \
1556 \
1557 __asm__ __volatile__( \
1558 " .set push \n" \
1559 " .set dsp \n" \
1560 " rddsp %0, %x1 \n" \
1561 " .set pop \n" \
1562 : "=r" (__dspctl) \
1563 : "i" (mask)); \
1564 __dspctl; \
1565})
1566
1567#define wrdsp(val, mask) \
1568do { \
1569 __asm__ __volatile__( \
1570 " .set push \n" \
1571 " .set dsp \n" \
1572 " wrdsp %0, %x1 \n" \
1573 " .set pop \n" \
1574 : \
1575 : "r" (val), "i" (mask)); \
1576} while (0)
1577
1578#define mflo0() \
1579({ \
1580 long mflo0; \
1581 __asm__( \
1582 " .set push \n" \
1583 " .set dsp \n" \
1584 " mflo %0, $ac0 \n" \
1585 " .set pop \n" \
1586 : "=r" (mflo0)); \
1587 mflo0; \
1588})
1589
1590#define mflo1() \
1591({ \
1592 long mflo1; \
1593 __asm__( \
1594 " .set push \n" \
1595 " .set dsp \n" \
1596 " mflo %0, $ac1 \n" \
1597 " .set pop \n" \
1598 : "=r" (mflo1)); \
1599 mflo1; \
1600})
1601
1602#define mflo2() \
1603({ \
1604 long mflo2; \
1605 __asm__( \
1606 " .set push \n" \
1607 " .set dsp \n" \
1608 " mflo %0, $ac2 \n" \
1609 " .set pop \n" \
1610 : "=r" (mflo2)); \
1611 mflo2; \
1612})
1613
1614#define mflo3() \
1615({ \
1616 long mflo3; \
1617 __asm__( \
1618 " .set push \n" \
1619 " .set dsp \n" \
1620 " mflo %0, $ac3 \n" \
1621 " .set pop \n" \
1622 : "=r" (mflo3)); \
1623 mflo3; \
1624})
1625
1626#define mfhi0() \
1627({ \
1628 long mfhi0; \
1629 __asm__( \
1630 " .set push \n" \
1631 " .set dsp \n" \
1632 " mfhi %0, $ac0 \n" \
1633 " .set pop \n" \
1634 : "=r" (mfhi0)); \
1635 mfhi0; \
1636})
1637
1638#define mfhi1() \
1639({ \
1640 long mfhi1; \
1641 __asm__( \
1642 " .set push \n" \
1643 " .set dsp \n" \
1644 " mfhi %0, $ac1 \n" \
1645 " .set pop \n" \
1646 : "=r" (mfhi1)); \
1647 mfhi1; \
1648})
1649
1650#define mfhi2() \
1651({ \
1652 long mfhi2; \
1653 __asm__( \
1654 " .set push \n" \
1655 " .set dsp \n" \
1656 " mfhi %0, $ac2 \n" \
1657 " .set pop \n" \
1658 : "=r" (mfhi2)); \
1659 mfhi2; \
1660})
1661
1662#define mfhi3() \
1663({ \
1664 long mfhi3; \
1665 __asm__( \
1666 " .set push \n" \
1667 " .set dsp \n" \
1668 " mfhi %0, $ac3 \n" \
1669 " .set pop \n" \
1670 : "=r" (mfhi3)); \
1671 mfhi3; \
1672})
1673
1674
1675#define mtlo0(x) \
1676({ \
1677 __asm__( \
1678 " .set push \n" \
1679 " .set dsp \n" \
1680 " mtlo %0, $ac0 \n" \
1681 " .set pop \n" \
1682 : \
1683 : "r" (x)); \
1684})
1685
1686#define mtlo1(x) \
1687({ \
1688 __asm__( \
1689 " .set push \n" \
1690 " .set dsp \n" \
1691 " mtlo %0, $ac1 \n" \
1692 " .set pop \n" \
1693 : \
1694 : "r" (x)); \
1695})
1696
1697#define mtlo2(x) \
1698({ \
1699 __asm__( \
1700 " .set push \n" \
1701 " .set dsp \n" \
1702 " mtlo %0, $ac2 \n" \
1703 " .set pop \n" \
1704 : \
1705 : "r" (x)); \
1706})
1707
1708#define mtlo3(x) \
1709({ \
1710 __asm__( \
1711 " .set push \n" \
1712 " .set dsp \n" \
1713 " mtlo %0, $ac3 \n" \
1714 " .set pop \n" \
1715 : \
1716 : "r" (x)); \
1717})
1718
1719#define mthi0(x) \
1720({ \
1721 __asm__( \
1722 " .set push \n" \
1723 " .set dsp \n" \
1724 " mthi %0, $ac0 \n" \
1725 " .set pop \n" \
1726 : \
1727 : "r" (x)); \
1728})
1729
1730#define mthi1(x) \
1731({ \
1732 __asm__( \
1733 " .set push \n" \
1734 " .set dsp \n" \
1735 " mthi %0, $ac1 \n" \
1736 " .set pop \n" \
1737 : \
1738 : "r" (x)); \
1739})
1740
1741#define mthi2(x) \
1742({ \
1743 __asm__( \
1744 " .set push \n" \
1745 " .set dsp \n" \
1746 " mthi %0, $ac2 \n" \
1747 " .set pop \n" \
1748 : \
1749 : "r" (x)); \
1750})
1751
1752#define mthi3(x) \
1753({ \
1754 __asm__( \
1755 " .set push \n" \
1756 " .set dsp \n" \
1757 " mthi %0, $ac3 \n" \
1758 " .set pop \n" \
1759 : \
1760 : "r" (x)); \
1761})
1762
1763#else
1764
1765#ifdef CONFIG_CPU_MICROMIPS
1766#define rddsp(mask) \
1767({ \
1768 unsigned int __res; \
1769 \
1770 __asm__ __volatile__( \
1771 " .set push \n" \
1772 " .set noat \n" \
1773 " # rddsp $1, %x1 \n" \
1774 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \
1775 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \
1776 " move %0, $1 \n" \
1777 " .set pop \n" \
1778 : "=r" (__res) \
1779 : "i" (mask)); \
1780 __res; \
1781})
1782
1783#define wrdsp(val, mask) \
1784do { \
1785 __asm__ __volatile__( \
1786 " .set push \n" \
1787 " .set noat \n" \
1788 " move $1, %0 \n" \
1789 " # wrdsp $1, %x1 \n" \
1790 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \
1791 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \
1792 " .set pop \n" \
1793 : \
1794 : "r" (val), "i" (mask)); \
1795} while (0)
1796
1797#define _umips_dsp_mfxxx(ins) \
1798({ \
1799 unsigned long __treg; \
1800 \
1801 __asm__ __volatile__( \
1802 " .set push \n" \
1803 " .set noat \n" \
1804 " .hword 0x0001 \n" \
1805 " .hword %x1 \n" \
1806 " move %0, $1 \n" \
1807 " .set pop \n" \
1808 : "=r" (__treg) \
1809 : "i" (ins)); \
1810 __treg; \
1811})
1812
1813#define _umips_dsp_mtxxx(val, ins) \
1814do { \
1815 __asm__ __volatile__( \
1816 " .set push \n" \
1817 " .set noat \n" \
1818 " move $1, %0 \n" \
1819 " .hword 0x0001 \n" \
1820 " .hword %x1 \n" \
1821 " .set pop \n" \
1822 : \
1823 : "r" (val), "i" (ins)); \
1824} while (0)
1825
1826#define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
1827#define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
1828
1829#define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1830#define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1831
1832#define mflo0() _umips_dsp_mflo(0)
1833#define mflo1() _umips_dsp_mflo(1)
1834#define mflo2() _umips_dsp_mflo(2)
1835#define mflo3() _umips_dsp_mflo(3)
1836
1837#define mfhi0() _umips_dsp_mfhi(0)
1838#define mfhi1() _umips_dsp_mfhi(1)
1839#define mfhi2() _umips_dsp_mfhi(2)
1840#define mfhi3() _umips_dsp_mfhi(3)
1841
1842#define mtlo0(x) _umips_dsp_mtlo(x, 0)
1843#define mtlo1(x) _umips_dsp_mtlo(x, 1)
1844#define mtlo2(x) _umips_dsp_mtlo(x, 2)
1845#define mtlo3(x) _umips_dsp_mtlo(x, 3)
1846
1847#define mthi0(x) _umips_dsp_mthi(x, 0)
1848#define mthi1(x) _umips_dsp_mthi(x, 1)
1849#define mthi2(x) _umips_dsp_mthi(x, 2)
1850#define mthi3(x) _umips_dsp_mthi(x, 3)
1851
1852#else /* !CONFIG_CPU_MICROMIPS */
1853#define rddsp(mask) \
1854({ \
1855 unsigned int __res; \
1856 \
1857 __asm__ __volatile__( \
1858 " .set push \n" \
1859 " .set noat \n" \
1860 " # rddsp $1, %x1 \n" \
1861 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1862 " move %0, $1 \n" \
1863 " .set pop \n" \
1864 : "=r" (__res) \
1865 : "i" (mask)); \
1866 __res; \
1867})
1868
1869#define wrdsp(val, mask) \
1870do { \
1871 __asm__ __volatile__( \
1872 " .set push \n" \
1873 " .set noat \n" \
1874 " move $1, %0 \n" \
1875 " # wrdsp $1, %x1 \n" \
1876 " .word 0x7c2004f8 | (%x1 << 11) \n" \
1877 " .set pop \n" \
1878 : \
1879 : "r" (val), "i" (mask)); \
1880} while (0)
1881
1882#define _dsp_mfxxx(ins) \
1883({ \
1884 unsigned long __treg; \
1885 \
1886 __asm__ __volatile__( \
1887 " .set push \n" \
1888 " .set noat \n" \
1889 " .word (0x00000810 | %1) \n" \
1890 " move %0, $1 \n" \
1891 " .set pop \n" \
1892 : "=r" (__treg) \
1893 : "i" (ins)); \
1894 __treg; \
1895})
1896
1897#define _dsp_mtxxx(val, ins) \
1898do { \
1899 __asm__ __volatile__( \
1900 " .set push \n" \
1901 " .set noat \n" \
1902 " move $1, %0 \n" \
1903 " .word (0x00200011 | %1) \n" \
1904 " .set pop \n" \
1905 : \
1906 : "r" (val), "i" (ins)); \
1907} while (0)
1908
1909#define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
1910#define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1911
1912#define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1913#define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1914
1915#define mflo0() _dsp_mflo(0)
1916#define mflo1() _dsp_mflo(1)
1917#define mflo2() _dsp_mflo(2)
1918#define mflo3() _dsp_mflo(3)
1919
1920#define mfhi0() _dsp_mfhi(0)
1921#define mfhi1() _dsp_mfhi(1)
1922#define mfhi2() _dsp_mfhi(2)
1923#define mfhi3() _dsp_mfhi(3)
1924
1925#define mtlo0(x) _dsp_mtlo(x, 0)
1926#define mtlo1(x) _dsp_mtlo(x, 1)
1927#define mtlo2(x) _dsp_mtlo(x, 2)
1928#define mtlo3(x) _dsp_mtlo(x, 3)
1929
1930#define mthi0(x) _dsp_mthi(x, 0)
1931#define mthi1(x) _dsp_mthi(x, 1)
1932#define mthi2(x) _dsp_mthi(x, 2)
1933#define mthi3(x) _dsp_mthi(x, 3)
1934
1935#endif /* CONFIG_CPU_MICROMIPS */
1936#endif
1937
1938/*
1939 * TLB operations.
1940 *
1941 * It is responsibility of the caller to take care of any TLB hazards.
1942 */
1943static inline void tlb_probe(void)
1944{
1945 __asm__ __volatile__(
1946 ".set noreorder\n\t"
1947 "tlbp\n\t"
1948 ".set reorder");
1949}
1950
1951static inline void tlb_read(void)
1952{
1953#if MIPS34K_MISSED_ITLB_WAR
1954 int res = 0;
1955
1956 __asm__ __volatile__(
1957 " .set push \n"
1958 " .set noreorder \n"
1959 " .set noat \n"
1960 " .set mips32r2 \n"
1961 " .word 0x41610001 # dvpe $1 \n"
1962 " move %0, $1 \n"
1963 " ehb \n"
1964 " .set pop \n"
1965 : "=r" (res));
1966
1967 instruction_hazard();
1968#endif
1969
1970 __asm__ __volatile__(
1971 ".set noreorder\n\t"
1972 "tlbr\n\t"
1973 ".set reorder");
1974
1975#if MIPS34K_MISSED_ITLB_WAR
1976 if ((res & _ULCAST_(1)))
1977 __asm__ __volatile__(
1978 " .set push \n"
1979 " .set noreorder \n"
1980 " .set noat \n"
1981 " .set mips32r2 \n"
1982 " .word 0x41600021 # evpe \n"
1983 " ehb \n"
1984 " .set pop \n");
1985#endif
1986}
1987
1988static inline void tlb_write_indexed(void)
1989{
1990 __asm__ __volatile__(
1991 ".set noreorder\n\t"
1992 "tlbwi\n\t"
1993 ".set reorder");
1994}
1995
1996static inline void tlb_write_random(void)
1997{
1998 __asm__ __volatile__(
1999 ".set noreorder\n\t"
2000 "tlbwr\n\t"
2001 ".set reorder");
2002}
2003
2004/*
2005 * Manipulate bits in a c0 register.
2006 */
2007#define __BUILD_SET_C0(name) \
2008static inline unsigned int \
2009set_c0_##name(unsigned int set) \
2010{ \
2011 unsigned int res, new; \
2012 \
2013 res = read_c0_##name(); \
2014 new = res | set; \
2015 write_c0_##name(new); \
2016 \
2017 return res; \
2018} \
2019 \
2020static inline unsigned int \
2021clear_c0_##name(unsigned int clear) \
2022{ \
2023 unsigned int res, new; \
2024 \
2025 res = read_c0_##name(); \
2026 new = res & ~clear; \
2027 write_c0_##name(new); \
2028 \
2029 return res; \
2030} \
2031 \
2032static inline unsigned int \
2033change_c0_##name(unsigned int change, unsigned int val) \
2034{ \
2035 unsigned int res, new; \
2036 \
2037 res = read_c0_##name(); \
2038 new = res & ~change; \
2039 new |= (val & change); \
2040 write_c0_##name(new); \
2041 \
2042 return res; \
2043}
2044
2045__BUILD_SET_C0(status)
2046__BUILD_SET_C0(cause)
2047__BUILD_SET_C0(config)
2048__BUILD_SET_C0(config5)
2049__BUILD_SET_C0(intcontrol)
2050__BUILD_SET_C0(intctl)
2051__BUILD_SET_C0(srsmap)
2052__BUILD_SET_C0(pagegrain)
2053__BUILD_SET_C0(brcm_config_0)
2054__BUILD_SET_C0(brcm_bus_pll)
2055__BUILD_SET_C0(brcm_reset)
2056__BUILD_SET_C0(brcm_cmt_intr)
2057__BUILD_SET_C0(brcm_cmt_ctrl)
2058__BUILD_SET_C0(brcm_config)
2059__BUILD_SET_C0(brcm_mode)
2060
2061/*
2062 * Return low 10 bits of ebase.
2063 * Note that under KVM (MIPSVZ) this returns vcpu id.
2064 */
2065static inline unsigned int get_ebase_cpunum(void)
2066{
2067 return read_c0_ebase() & 0x3ff;
2068}
2069
2070#endif /* !__ASSEMBLY__ */
2071
2072#endif /* _ASM_MIPSREGS_H */