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1/*
2 * hcd.c - DesignWare HS OTG Controller host-mode routines
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37/*
38 * This file contains the core HCD code, and implements the Linux hc_driver
39 * API
40 */
41#include <linux/kernel.h>
42#include <linux/module.h>
43#include <linux/spinlock.h>
44#include <linux/interrupt.h>
45#include <linux/dma-mapping.h>
46#include <linux/delay.h>
47#include <linux/io.h>
48#include <linux/slab.h>
49#include <linux/usb.h>
50
51#include <linux/usb/hcd.h>
52#include <linux/usb/ch11.h>
53
54#include "core.h"
55#include "hcd.h"
56
57/*
58 * =========================================================================
59 * Host Core Layer Functions
60 * =========================================================================
61 */
62
63/**
64 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
65 * used in both device and host modes
66 *
67 * @hsotg: Programming view of the DWC_otg controller
68 */
69static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
70{
71 u32 intmsk;
72
73 /* Clear any pending OTG Interrupts */
74 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
75
76 /* Clear any pending interrupts */
77 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
78
79 /* Enable the interrupts in the GINTMSK */
80 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
81
82 if (hsotg->params.host_dma <= 0)
83 intmsk |= GINTSTS_RXFLVL;
84 if (hsotg->params.external_id_pin_ctl <= 0)
85 intmsk |= GINTSTS_CONIDSTSCHNG;
86
87 intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP |
88 GINTSTS_SESSREQINT;
89
90 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
91}
92
93/*
94 * Initializes the FSLSPClkSel field of the HCFG register depending on the
95 * PHY type
96 */
97static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
98{
99 u32 hcfg, val;
100
101 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
102 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
103 hsotg->params.ulpi_fs_ls > 0) ||
104 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
105 /* Full speed PHY */
106 val = HCFG_FSLSPCLKSEL_48_MHZ;
107 } else {
108 /* High speed PHY running at full speed or high speed */
109 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
110 }
111
112 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
113 hcfg = dwc2_readl(hsotg->regs + HCFG);
114 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
115 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
116 dwc2_writel(hcfg, hsotg->regs + HCFG);
117}
118
119static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
120{
121 u32 usbcfg, i2cctl;
122 int retval = 0;
123
124 /*
125 * core_init() is now called on every switch so only call the
126 * following for the first time through
127 */
128 if (select_phy) {
129 dev_dbg(hsotg->dev, "FS PHY selected\n");
130
131 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
132 if (!(usbcfg & GUSBCFG_PHYSEL)) {
133 usbcfg |= GUSBCFG_PHYSEL;
134 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
135
136 /* Reset after a PHY select */
137 retval = dwc2_core_reset_and_force_dr_mode(hsotg);
138
139 if (retval) {
140 dev_err(hsotg->dev,
141 "%s: Reset failed, aborting", __func__);
142 return retval;
143 }
144 }
145 }
146
147 /*
148 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
149 * do this on HNP Dev/Host mode switches (done in dev_init and
150 * host_init).
151 */
152 if (dwc2_is_host_mode(hsotg))
153 dwc2_init_fs_ls_pclk_sel(hsotg);
154
155 if (hsotg->params.i2c_enable > 0) {
156 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
157
158 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
159 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
160 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
161 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
162
163 /* Program GI2CCTL.I2CEn */
164 i2cctl = dwc2_readl(hsotg->regs + GI2CCTL);
165 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
166 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
167 i2cctl &= ~GI2CCTL_I2CEN;
168 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
169 i2cctl |= GI2CCTL_I2CEN;
170 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
171 }
172
173 return retval;
174}
175
176static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
177{
178 u32 usbcfg, usbcfg_old;
179 int retval = 0;
180
181 if (!select_phy)
182 return 0;
183
184 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
185 usbcfg_old = usbcfg;
186
187 /*
188 * HS PHY parameters. These parameters are preserved during soft reset
189 * so only program the first time. Do a soft reset immediately after
190 * setting phyif.
191 */
192 switch (hsotg->params.phy_type) {
193 case DWC2_PHY_TYPE_PARAM_ULPI:
194 /* ULPI interface */
195 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
196 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
197 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
198 if (hsotg->params.phy_ulpi_ddr > 0)
199 usbcfg |= GUSBCFG_DDRSEL;
200 break;
201 case DWC2_PHY_TYPE_PARAM_UTMI:
202 /* UTMI+ interface */
203 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
204 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
205 if (hsotg->params.phy_utmi_width == 16)
206 usbcfg |= GUSBCFG_PHYIF16;
207 break;
208 default:
209 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
210 break;
211 }
212
213 if (usbcfg != usbcfg_old) {
214 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
215
216 /* Reset after setting the PHY parameters */
217 retval = dwc2_core_reset_and_force_dr_mode(hsotg);
218 if (retval) {
219 dev_err(hsotg->dev,
220 "%s: Reset failed, aborting", __func__);
221 return retval;
222 }
223 }
224
225 return retval;
226}
227
228static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
229{
230 u32 usbcfg;
231 int retval = 0;
232
233 if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
234 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) &&
235 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
236 /* If FS/LS mode with FS/LS PHY */
237 retval = dwc2_fs_phy_init(hsotg, select_phy);
238 if (retval)
239 return retval;
240 } else {
241 /* High speed PHY */
242 retval = dwc2_hs_phy_init(hsotg, select_phy);
243 if (retval)
244 return retval;
245 }
246
247 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
248 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
249 hsotg->params.ulpi_fs_ls > 0) {
250 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
251 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
252 usbcfg |= GUSBCFG_ULPI_FS_LS;
253 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
254 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
255 } else {
256 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
257 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
258 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
259 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
260 }
261
262 return retval;
263}
264
265static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
266{
267 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
268
269 switch (hsotg->hw_params.arch) {
270 case GHWCFG2_EXT_DMA_ARCH:
271 dev_err(hsotg->dev, "External DMA Mode not supported\n");
272 return -EINVAL;
273
274 case GHWCFG2_INT_DMA_ARCH:
275 dev_dbg(hsotg->dev, "Internal DMA Mode\n");
276 if (hsotg->params.ahbcfg != -1) {
277 ahbcfg &= GAHBCFG_CTRL_MASK;
278 ahbcfg |= hsotg->params.ahbcfg &
279 ~GAHBCFG_CTRL_MASK;
280 }
281 break;
282
283 case GHWCFG2_SLAVE_ONLY_ARCH:
284 default:
285 dev_dbg(hsotg->dev, "Slave Only Mode\n");
286 break;
287 }
288
289 dev_dbg(hsotg->dev, "host_dma:%d dma_desc_enable:%d\n",
290 hsotg->params.host_dma,
291 hsotg->params.dma_desc_enable);
292
293 if (hsotg->params.host_dma > 0) {
294 if (hsotg->params.dma_desc_enable > 0)
295 dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n");
296 else
297 dev_dbg(hsotg->dev, "Using Buffer DMA mode\n");
298 } else {
299 dev_dbg(hsotg->dev, "Using Slave mode\n");
300 hsotg->params.dma_desc_enable = 0;
301 }
302
303 if (hsotg->params.host_dma > 0)
304 ahbcfg |= GAHBCFG_DMA_EN;
305
306 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
307
308 return 0;
309}
310
311static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
312{
313 u32 usbcfg;
314
315 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
316 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
317
318 switch (hsotg->hw_params.op_mode) {
319 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
320 if (hsotg->params.otg_cap ==
321 DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
322 usbcfg |= GUSBCFG_HNPCAP;
323 if (hsotg->params.otg_cap !=
324 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
325 usbcfg |= GUSBCFG_SRPCAP;
326 break;
327
328 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
329 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
330 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
331 if (hsotg->params.otg_cap !=
332 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
333 usbcfg |= GUSBCFG_SRPCAP;
334 break;
335
336 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE:
337 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE:
338 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST:
339 default:
340 break;
341 }
342
343 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
344}
345
346/**
347 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
348 *
349 * @hsotg: Programming view of DWC_otg controller
350 */
351static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
352{
353 u32 intmsk;
354
355 dev_dbg(hsotg->dev, "%s()\n", __func__);
356
357 /* Disable all interrupts */
358 dwc2_writel(0, hsotg->regs + GINTMSK);
359 dwc2_writel(0, hsotg->regs + HAINTMSK);
360
361 /* Enable the common interrupts */
362 dwc2_enable_common_interrupts(hsotg);
363
364 /* Enable host mode interrupts without disturbing common interrupts */
365 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
366 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
367 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
368}
369
370/**
371 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
372 *
373 * @hsotg: Programming view of DWC_otg controller
374 */
375static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
376{
377 u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
378
379 /* Disable host mode interrupts without disturbing common interrupts */
380 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
381 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT);
382 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
383}
384
385/*
386 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size
387 * For system that have a total fifo depth that is smaller than the default
388 * RX + TX fifo size.
389 *
390 * @hsotg: Programming view of DWC_otg controller
391 */
392static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)
393{
394 struct dwc2_core_params *params = &hsotg->params;
395 struct dwc2_hw_params *hw = &hsotg->hw_params;
396 u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size;
397
398 total_fifo_size = hw->total_fifo_size;
399 rxfsiz = params->host_rx_fifo_size;
400 nptxfsiz = params->host_nperio_tx_fifo_size;
401 ptxfsiz = params->host_perio_tx_fifo_size;
402
403 /*
404 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth
405 * allocation with support for high bandwidth endpoints. Synopsys
406 * defines MPS(Max Packet size) for a periodic EP=1024, and for
407 * non-periodic as 512.
408 */
409 if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) {
410 /*
411 * For Buffer DMA mode/Scatter Gather DMA mode
412 * 2 * ((Largest Packet size / 4) + 1 + 1) + n
413 * with n = number of host channel.
414 * 2 * ((1024/4) + 2) = 516
415 */
416 rxfsiz = 516 + hw->host_channels;
417
418 /*
419 * min non-periodic tx fifo depth
420 * 2 * (largest non-periodic USB packet used / 4)
421 * 2 * (512/4) = 256
422 */
423 nptxfsiz = 256;
424
425 /*
426 * min periodic tx fifo depth
427 * (largest packet size*MC)/4
428 * (1024 * 3)/4 = 768
429 */
430 ptxfsiz = 768;
431
432 params->host_rx_fifo_size = rxfsiz;
433 params->host_nperio_tx_fifo_size = nptxfsiz;
434 params->host_perio_tx_fifo_size = ptxfsiz;
435 }
436
437 /*
438 * If the summation of RX, NPTX and PTX fifo sizes is still
439 * bigger than the total_fifo_size, then we have a problem.
440 *
441 * We won't be able to allocate as many endpoints. Right now,
442 * we're just printing an error message, but ideally this FIFO
443 * allocation algorithm would be improved in the future.
444 *
445 * FIXME improve this FIFO allocation algorithm.
446 */
447 if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)))
448 dev_err(hsotg->dev, "invalid fifo sizes\n");
449}
450
451static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
452{
453 struct dwc2_core_params *params = &hsotg->params;
454 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;
455
456 if (!params->enable_dynamic_fifo)
457 return;
458
459 dwc2_calculate_dynamic_fifo(hsotg);
460
461 /* Rx FIFO */
462 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
463 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
464 grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
465 grxfsiz |= params->host_rx_fifo_size <<
466 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
467 dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ);
468 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
469 dwc2_readl(hsotg->regs + GRXFSIZ));
470
471 /* Non-periodic Tx FIFO */
472 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
473 dwc2_readl(hsotg->regs + GNPTXFSIZ));
474 nptxfsiz = params->host_nperio_tx_fifo_size <<
475 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
476 nptxfsiz |= params->host_rx_fifo_size <<
477 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
478 dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ);
479 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
480 dwc2_readl(hsotg->regs + GNPTXFSIZ));
481
482 /* Periodic Tx FIFO */
483 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
484 dwc2_readl(hsotg->regs + HPTXFSIZ));
485 hptxfsiz = params->host_perio_tx_fifo_size <<
486 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
487 hptxfsiz |= (params->host_rx_fifo_size +
488 params->host_nperio_tx_fifo_size) <<
489 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
490 dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ);
491 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
492 dwc2_readl(hsotg->regs + HPTXFSIZ));
493
494 if (hsotg->params.en_multiple_tx_fifo > 0 &&
495 hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) {
496 /*
497 * Global DFIFOCFG calculation for Host mode -
498 * include RxFIFO, NPTXFIFO and HPTXFIFO
499 */
500 dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
501 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
502 dfifocfg |= (params->host_rx_fifo_size +
503 params->host_nperio_tx_fifo_size +
504 params->host_perio_tx_fifo_size) <<
505 GDFIFOCFG_EPINFOBASE_SHIFT &
506 GDFIFOCFG_EPINFOBASE_MASK;
507 dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG);
508 }
509}
510
511/**
512 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
513 * the HFIR register according to PHY type and speed
514 *
515 * @hsotg: Programming view of DWC_otg controller
516 *
517 * NOTE: The caller can modify the value of the HFIR register only after the
518 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort)
519 * has been set
520 */
521u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
522{
523 u32 usbcfg;
524 u32 hprt0;
525 int clock = 60; /* default value */
526
527 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
528 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
529
530 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
531 !(usbcfg & GUSBCFG_PHYIF16))
532 clock = 60;
533 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type ==
534 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
535 clock = 48;
536 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
537 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
538 clock = 30;
539 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
540 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16))
541 clock = 60;
542 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
543 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
544 clock = 48;
545 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
546 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
547 clock = 48;
548 if ((usbcfg & GUSBCFG_PHYSEL) &&
549 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
550 clock = 48;
551
552 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)
553 /* High speed case */
554 return 125 * clock - 1;
555
556 /* FS/LS case */
557 return 1000 * clock - 1;
558}
559
560/**
561 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
562 * buffer
563 *
564 * @core_if: Programming view of DWC_otg controller
565 * @dest: Destination buffer for the packet
566 * @bytes: Number of bytes to copy to the destination
567 */
568void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
569{
570 u32 __iomem *fifo = hsotg->regs + HCFIFO(0);
571 u32 *data_buf = (u32 *)dest;
572 int word_count = (bytes + 3) / 4;
573 int i;
574
575 /*
576 * Todo: Account for the case where dest is not dword aligned. This
577 * requires reading data from the FIFO into a u32 temp buffer, then
578 * moving it into the data buffer.
579 */
580
581 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
582
583 for (i = 0; i < word_count; i++, data_buf++)
584 *data_buf = dwc2_readl(fifo);
585}
586
587/**
588 * dwc2_dump_channel_info() - Prints the state of a host channel
589 *
590 * @hsotg: Programming view of DWC_otg controller
591 * @chan: Pointer to the channel to dump
592 *
593 * Must be called with interrupt disabled and spinlock held
594 *
595 * NOTE: This function will be removed once the peripheral controller code
596 * is integrated and the driver is stable
597 */
598static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
599 struct dwc2_host_chan *chan)
600{
601#ifdef VERBOSE_DEBUG
602 int num_channels = hsotg->params.host_channels;
603 struct dwc2_qh *qh;
604 u32 hcchar;
605 u32 hcsplt;
606 u32 hctsiz;
607 u32 hc_dma;
608 int i;
609
610 if (!chan)
611 return;
612
613 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
614 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
615 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num));
616 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num));
617
618 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
619 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
620 hcchar, hcsplt);
621 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n",
622 hctsiz, hc_dma);
623 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
624 chan->dev_addr, chan->ep_num, chan->ep_is_in);
625 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
626 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
627 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start);
628 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started);
629 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
630 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
631 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
632 (unsigned long)chan->xfer_dma);
633 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
634 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
635 dev_dbg(hsotg->dev, " NP inactive sched:\n");
636 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
637 qh_list_entry)
638 dev_dbg(hsotg->dev, " %p\n", qh);
639 dev_dbg(hsotg->dev, " NP active sched:\n");
640 list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
641 qh_list_entry)
642 dev_dbg(hsotg->dev, " %p\n", qh);
643 dev_dbg(hsotg->dev, " Channels:\n");
644 for (i = 0; i < num_channels; i++) {
645 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
646
647 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan);
648 }
649#endif /* VERBOSE_DEBUG */
650}
651
652static int _dwc2_hcd_start(struct usb_hcd *hcd);
653
654static void dwc2_host_start(struct dwc2_hsotg *hsotg)
655{
656 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
657
658 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
659 _dwc2_hcd_start(hcd);
660}
661
662static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
663{
664 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
665
666 hcd->self.is_b_host = 0;
667}
668
669static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context,
670 int *hub_addr, int *hub_port)
671{
672 struct urb *urb = context;
673
674 if (urb->dev->tt)
675 *hub_addr = urb->dev->tt->hub->devnum;
676 else
677 *hub_addr = 0;
678 *hub_port = urb->dev->ttport;
679}
680
681/*
682 * =========================================================================
683 * Low Level Host Channel Access Functions
684 * =========================================================================
685 */
686
687static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
688 struct dwc2_host_chan *chan)
689{
690 u32 hcintmsk = HCINTMSK_CHHLTD;
691
692 switch (chan->ep_type) {
693 case USB_ENDPOINT_XFER_CONTROL:
694 case USB_ENDPOINT_XFER_BULK:
695 dev_vdbg(hsotg->dev, "control/bulk\n");
696 hcintmsk |= HCINTMSK_XFERCOMPL;
697 hcintmsk |= HCINTMSK_STALL;
698 hcintmsk |= HCINTMSK_XACTERR;
699 hcintmsk |= HCINTMSK_DATATGLERR;
700 if (chan->ep_is_in) {
701 hcintmsk |= HCINTMSK_BBLERR;
702 } else {
703 hcintmsk |= HCINTMSK_NAK;
704 hcintmsk |= HCINTMSK_NYET;
705 if (chan->do_ping)
706 hcintmsk |= HCINTMSK_ACK;
707 }
708
709 if (chan->do_split) {
710 hcintmsk |= HCINTMSK_NAK;
711 if (chan->complete_split)
712 hcintmsk |= HCINTMSK_NYET;
713 else
714 hcintmsk |= HCINTMSK_ACK;
715 }
716
717 if (chan->error_state)
718 hcintmsk |= HCINTMSK_ACK;
719 break;
720
721 case USB_ENDPOINT_XFER_INT:
722 if (dbg_perio())
723 dev_vdbg(hsotg->dev, "intr\n");
724 hcintmsk |= HCINTMSK_XFERCOMPL;
725 hcintmsk |= HCINTMSK_NAK;
726 hcintmsk |= HCINTMSK_STALL;
727 hcintmsk |= HCINTMSK_XACTERR;
728 hcintmsk |= HCINTMSK_DATATGLERR;
729 hcintmsk |= HCINTMSK_FRMOVRUN;
730
731 if (chan->ep_is_in)
732 hcintmsk |= HCINTMSK_BBLERR;
733 if (chan->error_state)
734 hcintmsk |= HCINTMSK_ACK;
735 if (chan->do_split) {
736 if (chan->complete_split)
737 hcintmsk |= HCINTMSK_NYET;
738 else
739 hcintmsk |= HCINTMSK_ACK;
740 }
741 break;
742
743 case USB_ENDPOINT_XFER_ISOC:
744 if (dbg_perio())
745 dev_vdbg(hsotg->dev, "isoc\n");
746 hcintmsk |= HCINTMSK_XFERCOMPL;
747 hcintmsk |= HCINTMSK_FRMOVRUN;
748 hcintmsk |= HCINTMSK_ACK;
749
750 if (chan->ep_is_in) {
751 hcintmsk |= HCINTMSK_XACTERR;
752 hcintmsk |= HCINTMSK_BBLERR;
753 }
754 break;
755 default:
756 dev_err(hsotg->dev, "## Unknown EP type ##\n");
757 break;
758 }
759
760 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
761 if (dbg_hc(chan))
762 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
763}
764
765static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
766 struct dwc2_host_chan *chan)
767{
768 u32 hcintmsk = HCINTMSK_CHHLTD;
769
770 /*
771 * For Descriptor DMA mode core halts the channel on AHB error.
772 * Interrupt is not required.
773 */
774 if (hsotg->params.dma_desc_enable <= 0) {
775 if (dbg_hc(chan))
776 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
777 hcintmsk |= HCINTMSK_AHBERR;
778 } else {
779 if (dbg_hc(chan))
780 dev_vdbg(hsotg->dev, "desc DMA enabled\n");
781 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
782 hcintmsk |= HCINTMSK_XFERCOMPL;
783 }
784
785 if (chan->error_state && !chan->do_split &&
786 chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
787 if (dbg_hc(chan))
788 dev_vdbg(hsotg->dev, "setting ACK\n");
789 hcintmsk |= HCINTMSK_ACK;
790 if (chan->ep_is_in) {
791 hcintmsk |= HCINTMSK_DATATGLERR;
792 if (chan->ep_type != USB_ENDPOINT_XFER_INT)
793 hcintmsk |= HCINTMSK_NAK;
794 }
795 }
796
797 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
798 if (dbg_hc(chan))
799 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
800}
801
802static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
803 struct dwc2_host_chan *chan)
804{
805 u32 intmsk;
806
807 if (hsotg->params.host_dma > 0) {
808 if (dbg_hc(chan))
809 dev_vdbg(hsotg->dev, "DMA enabled\n");
810 dwc2_hc_enable_dma_ints(hsotg, chan);
811 } else {
812 if (dbg_hc(chan))
813 dev_vdbg(hsotg->dev, "DMA disabled\n");
814 dwc2_hc_enable_slave_ints(hsotg, chan);
815 }
816
817 /* Enable the top level host channel interrupt */
818 intmsk = dwc2_readl(hsotg->regs + HAINTMSK);
819 intmsk |= 1 << chan->hc_num;
820 dwc2_writel(intmsk, hsotg->regs + HAINTMSK);
821 if (dbg_hc(chan))
822 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
823
824 /* Make sure host channel interrupts are enabled */
825 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
826 intmsk |= GINTSTS_HCHINT;
827 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
828 if (dbg_hc(chan))
829 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
830}
831
832/**
833 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
834 * a specific endpoint
835 *
836 * @hsotg: Programming view of DWC_otg controller
837 * @chan: Information needed to initialize the host channel
838 *
839 * The HCCHARn register is set up with the characteristics specified in chan.
840 * Host channel interrupts that may need to be serviced while this transfer is
841 * in progress are enabled.
842 */
843static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
844{
845 u8 hc_num = chan->hc_num;
846 u32 hcintmsk;
847 u32 hcchar;
848 u32 hcsplt = 0;
849
850 if (dbg_hc(chan))
851 dev_vdbg(hsotg->dev, "%s()\n", __func__);
852
853 /* Clear old interrupt conditions for this host channel */
854 hcintmsk = 0xffffffff;
855 hcintmsk &= ~HCINTMSK_RESERVED14_31;
856 dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num));
857
858 /* Enable channel interrupts required for this transfer */
859 dwc2_hc_enable_ints(hsotg, chan);
860
861 /*
862 * Program the HCCHARn register with the endpoint characteristics for
863 * the current transfer
864 */
865 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK;
866 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK;
867 if (chan->ep_is_in)
868 hcchar |= HCCHAR_EPDIR;
869 if (chan->speed == USB_SPEED_LOW)
870 hcchar |= HCCHAR_LSPDDEV;
871 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
872 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
873 dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num));
874 if (dbg_hc(chan)) {
875 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
876 hc_num, hcchar);
877
878 dev_vdbg(hsotg->dev, "%s: Channel %d\n",
879 __func__, hc_num);
880 dev_vdbg(hsotg->dev, " Dev Addr: %d\n",
881 chan->dev_addr);
882 dev_vdbg(hsotg->dev, " Ep Num: %d\n",
883 chan->ep_num);
884 dev_vdbg(hsotg->dev, " Is In: %d\n",
885 chan->ep_is_in);
886 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n",
887 chan->speed == USB_SPEED_LOW);
888 dev_vdbg(hsotg->dev, " Ep Type: %d\n",
889 chan->ep_type);
890 dev_vdbg(hsotg->dev, " Max Pkt: %d\n",
891 chan->max_packet);
892 }
893
894 /* Program the HCSPLT register for SPLITs */
895 if (chan->do_split) {
896 if (dbg_hc(chan))
897 dev_vdbg(hsotg->dev,
898 "Programming HC %d with split --> %s\n",
899 hc_num,
900 chan->complete_split ? "CSPLIT" : "SSPLIT");
901 if (chan->complete_split)
902 hcsplt |= HCSPLT_COMPSPLT;
903 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT &
904 HCSPLT_XACTPOS_MASK;
905 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT &
906 HCSPLT_HUBADDR_MASK;
907 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT &
908 HCSPLT_PRTADDR_MASK;
909 if (dbg_hc(chan)) {
910 dev_vdbg(hsotg->dev, " comp split %d\n",
911 chan->complete_split);
912 dev_vdbg(hsotg->dev, " xact pos %d\n",
913 chan->xact_pos);
914 dev_vdbg(hsotg->dev, " hub addr %d\n",
915 chan->hub_addr);
916 dev_vdbg(hsotg->dev, " hub port %d\n",
917 chan->hub_port);
918 dev_vdbg(hsotg->dev, " is_in %d\n",
919 chan->ep_is_in);
920 dev_vdbg(hsotg->dev, " Max Pkt %d\n",
921 chan->max_packet);
922 dev_vdbg(hsotg->dev, " xferlen %d\n",
923 chan->xfer_len);
924 }
925 }
926
927 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num));
928}
929
930/**
931 * dwc2_hc_halt() - Attempts to halt a host channel
932 *
933 * @hsotg: Controller register interface
934 * @chan: Host channel to halt
935 * @halt_status: Reason for halting the channel
936 *
937 * This function should only be called in Slave mode or to abort a transfer in
938 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
939 * controller halts the channel when the transfer is complete or a condition
940 * occurs that requires application intervention.
941 *
942 * In slave mode, checks for a free request queue entry, then sets the Channel
943 * Enable and Channel Disable bits of the Host Channel Characteristics
944 * register of the specified channel to intiate the halt. If there is no free
945 * request queue entry, sets only the Channel Disable bit of the HCCHARn
946 * register to flush requests for this channel. In the latter case, sets a
947 * flag to indicate that the host channel needs to be halted when a request
948 * queue slot is open.
949 *
950 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
951 * HCCHARn register. The controller ensures there is space in the request
952 * queue before submitting the halt request.
953 *
954 * Some time may elapse before the core flushes any posted requests for this
955 * host channel and halts. The Channel Halted interrupt handler completes the
956 * deactivation of the host channel.
957 */
958void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
959 enum dwc2_halt_status halt_status)
960{
961 u32 nptxsts, hptxsts, hcchar;
962
963 if (dbg_hc(chan))
964 dev_vdbg(hsotg->dev, "%s()\n", __func__);
965 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS)
966 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
967
968 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
969 halt_status == DWC2_HC_XFER_AHB_ERR) {
970 /*
971 * Disable all channel interrupts except Ch Halted. The QTD
972 * and QH state associated with this transfer has been cleared
973 * (in the case of URB_DEQUEUE), so the channel needs to be
974 * shut down carefully to prevent crashes.
975 */
976 u32 hcintmsk = HCINTMSK_CHHLTD;
977
978 dev_vdbg(hsotg->dev, "dequeue/error\n");
979 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
980
981 /*
982 * Make sure no other interrupts besides halt are currently
983 * pending. Handling another interrupt could cause a crash due
984 * to the QTD and QH state.
985 */
986 dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num));
987
988 /*
989 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
990 * even if the channel was already halted for some other
991 * reason
992 */
993 chan->halt_status = halt_status;
994
995 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
996 if (!(hcchar & HCCHAR_CHENA)) {
997 /*
998 * The channel is either already halted or it hasn't
999 * started yet. In DMA mode, the transfer may halt if
1000 * it finishes normally or a condition occurs that
1001 * requires driver intervention. Don't want to halt
1002 * the channel again. In either Slave or DMA mode,
1003 * it's possible that the transfer has been assigned
1004 * to a channel, but not started yet when an URB is
1005 * dequeued. Don't want to halt a channel that hasn't
1006 * started yet.
1007 */
1008 return;
1009 }
1010 }
1011 if (chan->halt_pending) {
1012 /*
1013 * A halt has already been issued for this channel. This might
1014 * happen when a transfer is aborted by a higher level in
1015 * the stack.
1016 */
1017 dev_vdbg(hsotg->dev,
1018 "*** %s: Channel %d, chan->halt_pending already set ***\n",
1019 __func__, chan->hc_num);
1020 return;
1021 }
1022
1023 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1024
1025 /* No need to set the bit in DDMA for disabling the channel */
1026 /* TODO check it everywhere channel is disabled */
1027 if (hsotg->params.dma_desc_enable <= 0) {
1028 if (dbg_hc(chan))
1029 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
1030 hcchar |= HCCHAR_CHENA;
1031 } else {
1032 if (dbg_hc(chan))
1033 dev_dbg(hsotg->dev, "desc DMA enabled\n");
1034 }
1035 hcchar |= HCCHAR_CHDIS;
1036
1037 if (hsotg->params.host_dma <= 0) {
1038 if (dbg_hc(chan))
1039 dev_vdbg(hsotg->dev, "DMA not enabled\n");
1040 hcchar |= HCCHAR_CHENA;
1041
1042 /* Check for space in the request queue to issue the halt */
1043 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1044 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
1045 dev_vdbg(hsotg->dev, "control/bulk\n");
1046 nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
1047 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
1048 dev_vdbg(hsotg->dev, "Disabling channel\n");
1049 hcchar &= ~HCCHAR_CHENA;
1050 }
1051 } else {
1052 if (dbg_perio())
1053 dev_vdbg(hsotg->dev, "isoc/intr\n");
1054 hptxsts = dwc2_readl(hsotg->regs + HPTXSTS);
1055 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
1056 hsotg->queuing_high_bandwidth) {
1057 if (dbg_perio())
1058 dev_vdbg(hsotg->dev, "Disabling channel\n");
1059 hcchar &= ~HCCHAR_CHENA;
1060 }
1061 }
1062 } else {
1063 if (dbg_hc(chan))
1064 dev_vdbg(hsotg->dev, "DMA enabled\n");
1065 }
1066
1067 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1068 chan->halt_status = halt_status;
1069
1070 if (hcchar & HCCHAR_CHENA) {
1071 if (dbg_hc(chan))
1072 dev_vdbg(hsotg->dev, "Channel enabled\n");
1073 chan->halt_pending = 1;
1074 chan->halt_on_queue = 0;
1075 } else {
1076 if (dbg_hc(chan))
1077 dev_vdbg(hsotg->dev, "Channel disabled\n");
1078 chan->halt_on_queue = 1;
1079 }
1080
1081 if (dbg_hc(chan)) {
1082 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1083 chan->hc_num);
1084 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n",
1085 hcchar);
1086 dev_vdbg(hsotg->dev, " halt_pending: %d\n",
1087 chan->halt_pending);
1088 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n",
1089 chan->halt_on_queue);
1090 dev_vdbg(hsotg->dev, " halt_status: %d\n",
1091 chan->halt_status);
1092 }
1093}
1094
1095/**
1096 * dwc2_hc_cleanup() - Clears the transfer state for a host channel
1097 *
1098 * @hsotg: Programming view of DWC_otg controller
1099 * @chan: Identifies the host channel to clean up
1100 *
1101 * This function is normally called after a transfer is done and the host
1102 * channel is being released
1103 */
1104void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1105{
1106 u32 hcintmsk;
1107
1108 chan->xfer_started = 0;
1109
1110 list_del_init(&chan->split_order_list_entry);
1111
1112 /*
1113 * Clear channel interrupt enables and any unhandled channel interrupt
1114 * conditions
1115 */
1116 dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num));
1117 hcintmsk = 0xffffffff;
1118 hcintmsk &= ~HCINTMSK_RESERVED14_31;
1119 dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1120}
1121
1122/**
1123 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
1124 * which frame a periodic transfer should occur
1125 *
1126 * @hsotg: Programming view of DWC_otg controller
1127 * @chan: Identifies the host channel to set up and its properties
1128 * @hcchar: Current value of the HCCHAR register for the specified host channel
1129 *
1130 * This function has no effect on non-periodic transfers
1131 */
1132static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
1133 struct dwc2_host_chan *chan, u32 *hcchar)
1134{
1135 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1136 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1137 int host_speed;
1138 int xfer_ns;
1139 int xfer_us;
1140 int bytes_in_fifo;
1141 u16 fifo_space;
1142 u16 frame_number;
1143 u16 wire_frame;
1144
1145 /*
1146 * Try to figure out if we're an even or odd frame. If we set
1147 * even and the current frame number is even the the transfer
1148 * will happen immediately. Similar if both are odd. If one is
1149 * even and the other is odd then the transfer will happen when
1150 * the frame number ticks.
1151 *
1152 * There's a bit of a balancing act to get this right.
1153 * Sometimes we may want to send data in the current frame (AK
1154 * right away). We might want to do this if the frame number
1155 * _just_ ticked, but we might also want to do this in order
1156 * to continue a split transaction that happened late in a
1157 * microframe (so we didn't know to queue the next transfer
1158 * until the frame number had ticked). The problem is that we
1159 * need a lot of knowledge to know if there's actually still
1160 * time to send things or if it would be better to wait until
1161 * the next frame.
1162 *
1163 * We can look at how much time is left in the current frame
1164 * and make a guess about whether we'll have time to transfer.
1165 * We'll do that.
1166 */
1167
1168 /* Get speed host is running at */
1169 host_speed = (chan->speed != USB_SPEED_HIGH &&
1170 !chan->do_split) ? chan->speed : USB_SPEED_HIGH;
1171
1172 /* See how many bytes are in the periodic FIFO right now */
1173 fifo_space = (dwc2_readl(hsotg->regs + HPTXSTS) &
1174 TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT;
1175 bytes_in_fifo = sizeof(u32) *
1176 (hsotg->params.host_perio_tx_fifo_size -
1177 fifo_space);
1178
1179 /*
1180 * Roughly estimate bus time for everything in the periodic
1181 * queue + our new transfer. This is "rough" because we're
1182 * using a function that makes takes into account IN/OUT
1183 * and INT/ISO and we're just slamming in one value for all
1184 * transfers. This should be an over-estimate and that should
1185 * be OK, but we can probably tighten it.
1186 */
1187 xfer_ns = usb_calc_bus_time(host_speed, false, false,
1188 chan->xfer_len + bytes_in_fifo);
1189 xfer_us = NS_TO_US(xfer_ns);
1190
1191 /* See what frame number we'll be at by the time we finish */
1192 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us);
1193
1194 /* This is when we were scheduled to be on the wire */
1195 wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1);
1196
1197 /*
1198 * If we'd finish _after_ the frame we're scheduled in then
1199 * it's hopeless. Just schedule right away and hope for the
1200 * best. Note that it _might_ be wise to call back into the
1201 * scheduler to pick a better frame, but this is better than
1202 * nothing.
1203 */
1204 if (dwc2_frame_num_gt(frame_number, wire_frame)) {
1205 dwc2_sch_vdbg(hsotg,
1206 "QH=%p EO MISS fr=%04x=>%04x (%+d)\n",
1207 chan->qh, wire_frame, frame_number,
1208 dwc2_frame_num_dec(frame_number,
1209 wire_frame));
1210 wire_frame = frame_number;
1211
1212 /*
1213 * We picked a different frame number; communicate this
1214 * back to the scheduler so it doesn't try to schedule
1215 * another in the same frame.
1216 *
1217 * Remember that next_active_frame is 1 before the wire
1218 * frame.
1219 */
1220 chan->qh->next_active_frame =
1221 dwc2_frame_num_dec(frame_number, 1);
1222 }
1223
1224 if (wire_frame & 1)
1225 *hcchar |= HCCHAR_ODDFRM;
1226 else
1227 *hcchar &= ~HCCHAR_ODDFRM;
1228 }
1229}
1230
1231static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan)
1232{
1233 /* Set up the initial PID for the transfer */
1234 if (chan->speed == USB_SPEED_HIGH) {
1235 if (chan->ep_is_in) {
1236 if (chan->multi_count == 1)
1237 chan->data_pid_start = DWC2_HC_PID_DATA0;
1238 else if (chan->multi_count == 2)
1239 chan->data_pid_start = DWC2_HC_PID_DATA1;
1240 else
1241 chan->data_pid_start = DWC2_HC_PID_DATA2;
1242 } else {
1243 if (chan->multi_count == 1)
1244 chan->data_pid_start = DWC2_HC_PID_DATA0;
1245 else
1246 chan->data_pid_start = DWC2_HC_PID_MDATA;
1247 }
1248 } else {
1249 chan->data_pid_start = DWC2_HC_PID_DATA0;
1250 }
1251}
1252
1253/**
1254 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
1255 * the Host Channel
1256 *
1257 * @hsotg: Programming view of DWC_otg controller
1258 * @chan: Information needed to initialize the host channel
1259 *
1260 * This function should only be called in Slave mode. For a channel associated
1261 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1262 * associated with a periodic EP, the periodic Tx FIFO is written.
1263 *
1264 * Upon return the xfer_buf and xfer_count fields in chan are incremented by
1265 * the number of bytes written to the Tx FIFO.
1266 */
1267static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1268 struct dwc2_host_chan *chan)
1269{
1270 u32 i;
1271 u32 remaining_count;
1272 u32 byte_count;
1273 u32 dword_count;
1274 u32 __iomem *data_fifo;
1275 u32 *data_buf = (u32 *)chan->xfer_buf;
1276
1277 if (dbg_hc(chan))
1278 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1279
1280 data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num));
1281
1282 remaining_count = chan->xfer_len - chan->xfer_count;
1283 if (remaining_count > chan->max_packet)
1284 byte_count = chan->max_packet;
1285 else
1286 byte_count = remaining_count;
1287
1288 dword_count = (byte_count + 3) / 4;
1289
1290 if (((unsigned long)data_buf & 0x3) == 0) {
1291 /* xfer_buf is DWORD aligned */
1292 for (i = 0; i < dword_count; i++, data_buf++)
1293 dwc2_writel(*data_buf, data_fifo);
1294 } else {
1295 /* xfer_buf is not DWORD aligned */
1296 for (i = 0; i < dword_count; i++, data_buf++) {
1297 u32 data = data_buf[0] | data_buf[1] << 8 |
1298 data_buf[2] << 16 | data_buf[3] << 24;
1299 dwc2_writel(data, data_fifo);
1300 }
1301 }
1302
1303 chan->xfer_count += byte_count;
1304 chan->xfer_buf += byte_count;
1305}
1306
1307/**
1308 * dwc2_hc_do_ping() - Starts a PING transfer
1309 *
1310 * @hsotg: Programming view of DWC_otg controller
1311 * @chan: Information needed to initialize the host channel
1312 *
1313 * This function should only be called in Slave mode. The Do Ping bit is set in
1314 * the HCTSIZ register, then the channel is enabled.
1315 */
1316static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
1317 struct dwc2_host_chan *chan)
1318{
1319 u32 hcchar;
1320 u32 hctsiz;
1321
1322 if (dbg_hc(chan))
1323 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1324 chan->hc_num);
1325
1326 hctsiz = TSIZ_DOPNG;
1327 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
1328 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1329
1330 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1331 hcchar |= HCCHAR_CHENA;
1332 hcchar &= ~HCCHAR_CHDIS;
1333 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1334}
1335
1336/**
1337 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1338 * channel and starts the transfer
1339 *
1340 * @hsotg: Programming view of DWC_otg controller
1341 * @chan: Information needed to initialize the host channel. The xfer_len value
1342 * may be reduced to accommodate the max widths of the XferSize and
1343 * PktCnt fields in the HCTSIZn register. The multi_count value may be
1344 * changed to reflect the final xfer_len value.
1345 *
1346 * This function may be called in either Slave mode or DMA mode. In Slave mode,
1347 * the caller must ensure that there is sufficient space in the request queue
1348 * and Tx Data FIFO.
1349 *
1350 * For an OUT transfer in Slave mode, it loads a data packet into the
1351 * appropriate FIFO. If necessary, additional data packets are loaded in the
1352 * Host ISR.
1353 *
1354 * For an IN transfer in Slave mode, a data packet is requested. The data
1355 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
1356 * additional data packets are requested in the Host ISR.
1357 *
1358 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1359 * register along with a packet count of 1 and the channel is enabled. This
1360 * causes a single PING transaction to occur. Other fields in HCTSIZ are
1361 * simply set to 0 since no data transfer occurs in this case.
1362 *
1363 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1364 * all the information required to perform the subsequent data transfer. In
1365 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
1366 * controller performs the entire PING protocol, then starts the data
1367 * transfer.
1368 */
1369static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1370 struct dwc2_host_chan *chan)
1371{
1372 u32 max_hc_xfer_size = hsotg->params.max_transfer_size;
1373 u16 max_hc_pkt_count = hsotg->params.max_packet_count;
1374 u32 hcchar;
1375 u32 hctsiz = 0;
1376 u16 num_packets;
1377 u32 ec_mc;
1378
1379 if (dbg_hc(chan))
1380 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1381
1382 if (chan->do_ping) {
1383 if (hsotg->params.host_dma <= 0) {
1384 if (dbg_hc(chan))
1385 dev_vdbg(hsotg->dev, "ping, no DMA\n");
1386 dwc2_hc_do_ping(hsotg, chan);
1387 chan->xfer_started = 1;
1388 return;
1389 }
1390
1391 if (dbg_hc(chan))
1392 dev_vdbg(hsotg->dev, "ping, DMA\n");
1393
1394 hctsiz |= TSIZ_DOPNG;
1395 }
1396
1397 if (chan->do_split) {
1398 if (dbg_hc(chan))
1399 dev_vdbg(hsotg->dev, "split\n");
1400 num_packets = 1;
1401
1402 if (chan->complete_split && !chan->ep_is_in)
1403 /*
1404 * For CSPLIT OUT Transfer, set the size to 0 so the
1405 * core doesn't expect any data written to the FIFO
1406 */
1407 chan->xfer_len = 0;
1408 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet)
1409 chan->xfer_len = chan->max_packet;
1410 else if (!chan->ep_is_in && chan->xfer_len > 188)
1411 chan->xfer_len = 188;
1412
1413 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1414 TSIZ_XFERSIZE_MASK;
1415
1416 /* For split set ec_mc for immediate retries */
1417 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1418 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1419 ec_mc = 3;
1420 else
1421 ec_mc = 1;
1422 } else {
1423 if (dbg_hc(chan))
1424 dev_vdbg(hsotg->dev, "no split\n");
1425 /*
1426 * Ensure that the transfer length and packet count will fit
1427 * in the widths allocated for them in the HCTSIZn register
1428 */
1429 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1430 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1431 /*
1432 * Make sure the transfer size is no larger than one
1433 * (micro)frame's worth of data. (A check was done
1434 * when the periodic transfer was accepted to ensure
1435 * that a (micro)frame's worth of data can be
1436 * programmed into a channel.)
1437 */
1438 u32 max_periodic_len =
1439 chan->multi_count * chan->max_packet;
1440
1441 if (chan->xfer_len > max_periodic_len)
1442 chan->xfer_len = max_periodic_len;
1443 } else if (chan->xfer_len > max_hc_xfer_size) {
1444 /*
1445 * Make sure that xfer_len is a multiple of max packet
1446 * size
1447 */
1448 chan->xfer_len =
1449 max_hc_xfer_size - chan->max_packet + 1;
1450 }
1451
1452 if (chan->xfer_len > 0) {
1453 num_packets = (chan->xfer_len + chan->max_packet - 1) /
1454 chan->max_packet;
1455 if (num_packets > max_hc_pkt_count) {
1456 num_packets = max_hc_pkt_count;
1457 chan->xfer_len = num_packets * chan->max_packet;
1458 }
1459 } else {
1460 /* Need 1 packet for transfer length of 0 */
1461 num_packets = 1;
1462 }
1463
1464 if (chan->ep_is_in)
1465 /*
1466 * Always program an integral # of max packets for IN
1467 * transfers
1468 */
1469 chan->xfer_len = num_packets * chan->max_packet;
1470
1471 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1472 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1473 /*
1474 * Make sure that the multi_count field matches the
1475 * actual transfer length
1476 */
1477 chan->multi_count = num_packets;
1478
1479 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1480 dwc2_set_pid_isoc(chan);
1481
1482 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1483 TSIZ_XFERSIZE_MASK;
1484
1485 /* The ec_mc gets the multi_count for non-split */
1486 ec_mc = chan->multi_count;
1487 }
1488
1489 chan->start_pkt_count = num_packets;
1490 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
1491 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1492 TSIZ_SC_MC_PID_MASK;
1493 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1494 if (dbg_hc(chan)) {
1495 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1496 hctsiz, chan->hc_num);
1497
1498 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1499 chan->hc_num);
1500 dev_vdbg(hsotg->dev, " Xfer Size: %d\n",
1501 (hctsiz & TSIZ_XFERSIZE_MASK) >>
1502 TSIZ_XFERSIZE_SHIFT);
1503 dev_vdbg(hsotg->dev, " Num Pkts: %d\n",
1504 (hctsiz & TSIZ_PKTCNT_MASK) >>
1505 TSIZ_PKTCNT_SHIFT);
1506 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1507 (hctsiz & TSIZ_SC_MC_PID_MASK) >>
1508 TSIZ_SC_MC_PID_SHIFT);
1509 }
1510
1511 if (hsotg->params.host_dma > 0) {
1512 dwc2_writel((u32)chan->xfer_dma,
1513 hsotg->regs + HCDMA(chan->hc_num));
1514 if (dbg_hc(chan))
1515 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
1516 (unsigned long)chan->xfer_dma, chan->hc_num);
1517 }
1518
1519 /* Start the split */
1520 if (chan->do_split) {
1521 u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
1522
1523 hcsplt |= HCSPLT_SPLTENA;
1524 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num));
1525 }
1526
1527 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1528 hcchar &= ~HCCHAR_MULTICNT_MASK;
1529 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK;
1530 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1531
1532 if (hcchar & HCCHAR_CHDIS)
1533 dev_warn(hsotg->dev,
1534 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1535 __func__, chan->hc_num, hcchar);
1536
1537 /* Set host channel enable after all other setup is complete */
1538 hcchar |= HCCHAR_CHENA;
1539 hcchar &= ~HCCHAR_CHDIS;
1540
1541 if (dbg_hc(chan))
1542 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1543 (hcchar & HCCHAR_MULTICNT_MASK) >>
1544 HCCHAR_MULTICNT_SHIFT);
1545
1546 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1547 if (dbg_hc(chan))
1548 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1549 chan->hc_num);
1550
1551 chan->xfer_started = 1;
1552 chan->requests++;
1553
1554 if (hsotg->params.host_dma <= 0 &&
1555 !chan->ep_is_in && chan->xfer_len > 0)
1556 /* Load OUT packet into the appropriate Tx FIFO */
1557 dwc2_hc_write_packet(hsotg, chan);
1558}
1559
1560/**
1561 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
1562 * host channel and starts the transfer in Descriptor DMA mode
1563 *
1564 * @hsotg: Programming view of DWC_otg controller
1565 * @chan: Information needed to initialize the host channel
1566 *
1567 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
1568 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field
1569 * with micro-frame bitmap.
1570 *
1571 * Initializes HCDMA register with descriptor list address and CTD value then
1572 * starts the transfer via enabling the channel.
1573 */
1574void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1575 struct dwc2_host_chan *chan)
1576{
1577 u32 hcchar;
1578 u32 hctsiz = 0;
1579
1580 if (chan->do_ping)
1581 hctsiz |= TSIZ_DOPNG;
1582
1583 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1584 dwc2_set_pid_isoc(chan);
1585
1586 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
1587 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1588 TSIZ_SC_MC_PID_MASK;
1589
1590 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
1591 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK;
1592
1593 /* Non-zero only for high-speed interrupt endpoints */
1594 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;
1595
1596 if (dbg_hc(chan)) {
1597 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1598 chan->hc_num);
1599 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1600 chan->data_pid_start);
1601 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1);
1602 }
1603
1604 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1605
1606 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr,
1607 chan->desc_list_sz, DMA_TO_DEVICE);
1608
1609 dwc2_writel(chan->desc_list_addr, hsotg->regs + HCDMA(chan->hc_num));
1610
1611 if (dbg_hc(chan))
1612 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n",
1613 &chan->desc_list_addr, chan->hc_num);
1614
1615 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1616 hcchar &= ~HCCHAR_MULTICNT_MASK;
1617 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1618 HCCHAR_MULTICNT_MASK;
1619
1620 if (hcchar & HCCHAR_CHDIS)
1621 dev_warn(hsotg->dev,
1622 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1623 __func__, chan->hc_num, hcchar);
1624
1625 /* Set host channel enable after all other setup is complete */
1626 hcchar |= HCCHAR_CHENA;
1627 hcchar &= ~HCCHAR_CHDIS;
1628
1629 if (dbg_hc(chan))
1630 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1631 (hcchar & HCCHAR_MULTICNT_MASK) >>
1632 HCCHAR_MULTICNT_SHIFT);
1633
1634 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1635 if (dbg_hc(chan))
1636 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1637 chan->hc_num);
1638
1639 chan->xfer_started = 1;
1640 chan->requests++;
1641}
1642
1643/**
1644 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
1645 * a previous call to dwc2_hc_start_transfer()
1646 *
1647 * @hsotg: Programming view of DWC_otg controller
1648 * @chan: Information needed to initialize the host channel
1649 *
1650 * The caller must ensure there is sufficient space in the request queue and Tx
1651 * Data FIFO. This function should only be called in Slave mode. In DMA mode,
1652 * the controller acts autonomously to complete transfers programmed to a host
1653 * channel.
1654 *
1655 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
1656 * if there is any data remaining to be queued. For an IN transfer, another
1657 * data packet is always requested. For the SETUP phase of a control transfer,
1658 * this function does nothing.
1659 *
1660 * Return: 1 if a new request is queued, 0 if no more requests are required
1661 * for this transfer
1662 */
1663static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1664 struct dwc2_host_chan *chan)
1665{
1666 if (dbg_hc(chan))
1667 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1668 chan->hc_num);
1669
1670 if (chan->do_split)
1671 /* SPLITs always queue just once per channel */
1672 return 0;
1673
1674 if (chan->data_pid_start == DWC2_HC_PID_SETUP)
1675 /* SETUPs are queued only once since they can't be NAK'd */
1676 return 0;
1677
1678 if (chan->ep_is_in) {
1679 /*
1680 * Always queue another request for other IN transfers. If
1681 * back-to-back INs are issued and NAKs are received for both,
1682 * the driver may still be processing the first NAK when the
1683 * second NAK is received. When the interrupt handler clears
1684 * the NAK interrupt for the first NAK, the second NAK will
1685 * not be seen. So we can't depend on the NAK interrupt
1686 * handler to requeue a NAK'd request. Instead, IN requests
1687 * are issued each time this function is called. When the
1688 * transfer completes, the extra requests for the channel will
1689 * be flushed.
1690 */
1691 u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1692
1693 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1694 hcchar |= HCCHAR_CHENA;
1695 hcchar &= ~HCCHAR_CHDIS;
1696 if (dbg_hc(chan))
1697 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n",
1698 hcchar);
1699 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1700 chan->requests++;
1701 return 1;
1702 }
1703
1704 /* OUT transfers */
1705
1706 if (chan->xfer_count < chan->xfer_len) {
1707 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1708 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1709 u32 hcchar = dwc2_readl(hsotg->regs +
1710 HCCHAR(chan->hc_num));
1711
1712 dwc2_hc_set_even_odd_frame(hsotg, chan,
1713 &hcchar);
1714 }
1715
1716 /* Load OUT packet into the appropriate Tx FIFO */
1717 dwc2_hc_write_packet(hsotg, chan);
1718 chan->requests++;
1719 return 1;
1720 }
1721
1722 return 0;
1723}
1724
1725/*
1726 * =========================================================================
1727 * HCD
1728 * =========================================================================
1729 */
1730
1731/*
1732 * Processes all the URBs in a single list of QHs. Completes them with
1733 * -ETIMEDOUT and frees the QTD.
1734 *
1735 * Must be called with interrupt disabled and spinlock held
1736 */
1737static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
1738 struct list_head *qh_list)
1739{
1740 struct dwc2_qh *qh, *qh_tmp;
1741 struct dwc2_qtd *qtd, *qtd_tmp;
1742
1743 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1744 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1745 qtd_list_entry) {
1746 dwc2_host_complete(hsotg, qtd, -ECONNRESET);
1747 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1748 }
1749 }
1750}
1751
1752static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
1753 struct list_head *qh_list)
1754{
1755 struct dwc2_qtd *qtd, *qtd_tmp;
1756 struct dwc2_qh *qh, *qh_tmp;
1757 unsigned long flags;
1758
1759 if (!qh_list->next)
1760 /* The list hasn't been initialized yet */
1761 return;
1762
1763 spin_lock_irqsave(&hsotg->lock, flags);
1764
1765 /* Ensure there are no QTDs or URBs left */
1766 dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
1767
1768 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1769 dwc2_hcd_qh_unlink(hsotg, qh);
1770
1771 /* Free each QTD in the QH's QTD list */
1772 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1773 qtd_list_entry)
1774 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1775
1776 if (qh->channel && qh->channel->qh == qh)
1777 qh->channel->qh = NULL;
1778
1779 spin_unlock_irqrestore(&hsotg->lock, flags);
1780 dwc2_hcd_qh_free(hsotg, qh);
1781 spin_lock_irqsave(&hsotg->lock, flags);
1782 }
1783
1784 spin_unlock_irqrestore(&hsotg->lock, flags);
1785}
1786
1787/*
1788 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
1789 * and periodic schedules. The QTD associated with each URB is removed from
1790 * the schedule and freed. This function may be called when a disconnect is
1791 * detected or when the HCD is being stopped.
1792 *
1793 * Must be called with interrupt disabled and spinlock held
1794 */
1795static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
1796{
1797 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
1798 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
1799 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
1800 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
1801 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
1802 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
1803}
1804
1805/**
1806 * dwc2_hcd_start() - Starts the HCD when switching to Host mode
1807 *
1808 * @hsotg: Pointer to struct dwc2_hsotg
1809 */
1810void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
1811{
1812 u32 hprt0;
1813
1814 if (hsotg->op_state == OTG_STATE_B_HOST) {
1815 /*
1816 * Reset the port. During a HNP mode switch the reset
1817 * needs to occur within 1ms and have a duration of at
1818 * least 50ms.
1819 */
1820 hprt0 = dwc2_read_hprt0(hsotg);
1821 hprt0 |= HPRT0_RST;
1822 dwc2_writel(hprt0, hsotg->regs + HPRT0);
1823 }
1824
1825 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
1826 msecs_to_jiffies(50));
1827}
1828
1829/* Must be called with interrupt disabled and spinlock held */
1830static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
1831{
1832 int num_channels = hsotg->params.host_channels;
1833 struct dwc2_host_chan *channel;
1834 u32 hcchar;
1835 int i;
1836
1837 if (hsotg->params.host_dma <= 0) {
1838 /* Flush out any channel requests in slave mode */
1839 for (i = 0; i < num_channels; i++) {
1840 channel = hsotg->hc_ptr_array[i];
1841 if (!list_empty(&channel->hc_list_entry))
1842 continue;
1843 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1844 if (hcchar & HCCHAR_CHENA) {
1845 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
1846 hcchar |= HCCHAR_CHDIS;
1847 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1848 }
1849 }
1850 }
1851
1852 for (i = 0; i < num_channels; i++) {
1853 channel = hsotg->hc_ptr_array[i];
1854 if (!list_empty(&channel->hc_list_entry))
1855 continue;
1856 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1857 if (hcchar & HCCHAR_CHENA) {
1858 /* Halt the channel */
1859 hcchar |= HCCHAR_CHDIS;
1860 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1861 }
1862
1863 dwc2_hc_cleanup(hsotg, channel);
1864 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
1865 /*
1866 * Added for Descriptor DMA to prevent channel double cleanup in
1867 * release_channel_ddma(), which is called from ep_disable when
1868 * device disconnects
1869 */
1870 channel->qh = NULL;
1871 }
1872 /* All channels have been freed, mark them available */
1873 if (hsotg->params.uframe_sched > 0) {
1874 hsotg->available_host_channels =
1875 hsotg->params.host_channels;
1876 } else {
1877 hsotg->non_periodic_channels = 0;
1878 hsotg->periodic_channels = 0;
1879 }
1880}
1881
1882/**
1883 * dwc2_hcd_connect() - Handles connect of the HCD
1884 *
1885 * @hsotg: Pointer to struct dwc2_hsotg
1886 *
1887 * Must be called with interrupt disabled and spinlock held
1888 */
1889void dwc2_hcd_connect(struct dwc2_hsotg *hsotg)
1890{
1891 if (hsotg->lx_state != DWC2_L0)
1892 usb_hcd_resume_root_hub(hsotg->priv);
1893
1894 hsotg->flags.b.port_connect_status_change = 1;
1895 hsotg->flags.b.port_connect_status = 1;
1896}
1897
1898/**
1899 * dwc2_hcd_disconnect() - Handles disconnect of the HCD
1900 *
1901 * @hsotg: Pointer to struct dwc2_hsotg
1902 * @force: If true, we won't try to reconnect even if we see device connected.
1903 *
1904 * Must be called with interrupt disabled and spinlock held
1905 */
1906void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
1907{
1908 u32 intr;
1909 u32 hprt0;
1910
1911 /* Set status flags for the hub driver */
1912 hsotg->flags.b.port_connect_status_change = 1;
1913 hsotg->flags.b.port_connect_status = 0;
1914
1915 /*
1916 * Shutdown any transfers in process by clearing the Tx FIFO Empty
1917 * interrupt mask and status bits and disabling subsequent host
1918 * channel interrupts.
1919 */
1920 intr = dwc2_readl(hsotg->regs + GINTMSK);
1921 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
1922 dwc2_writel(intr, hsotg->regs + GINTMSK);
1923 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
1924 dwc2_writel(intr, hsotg->regs + GINTSTS);
1925
1926 /*
1927 * Turn off the vbus power only if the core has transitioned to device
1928 * mode. If still in host mode, need to keep power on to detect a
1929 * reconnection.
1930 */
1931 if (dwc2_is_device_mode(hsotg)) {
1932 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
1933 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
1934 dwc2_writel(0, hsotg->regs + HPRT0);
1935 }
1936
1937 dwc2_disable_host_interrupts(hsotg);
1938 }
1939
1940 /* Respond with an error status to all URBs in the schedule */
1941 dwc2_kill_all_urbs(hsotg);
1942
1943 if (dwc2_is_host_mode(hsotg))
1944 /* Clean up any host channels that were in use */
1945 dwc2_hcd_cleanup_channels(hsotg);
1946
1947 dwc2_host_disconnect(hsotg);
1948
1949 /*
1950 * Add an extra check here to see if we're actually connected but
1951 * we don't have a detection interrupt pending. This can happen if:
1952 * 1. hardware sees connect
1953 * 2. hardware sees disconnect
1954 * 3. hardware sees connect
1955 * 4. dwc2_port_intr() - clears connect interrupt
1956 * 5. dwc2_handle_common_intr() - calls here
1957 *
1958 * Without the extra check here we will end calling disconnect
1959 * and won't get any future interrupts to handle the connect.
1960 */
1961 if (!force) {
1962 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
1963 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS))
1964 dwc2_hcd_connect(hsotg);
1965 }
1966}
1967
1968/**
1969 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
1970 *
1971 * @hsotg: Pointer to struct dwc2_hsotg
1972 */
1973static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
1974{
1975 if (hsotg->bus_suspended) {
1976 hsotg->flags.b.port_suspend_change = 1;
1977 usb_hcd_resume_root_hub(hsotg->priv);
1978 }
1979
1980 if (hsotg->lx_state == DWC2_L1)
1981 hsotg->flags.b.port_l1_change = 1;
1982}
1983
1984/**
1985 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
1986 *
1987 * @hsotg: Pointer to struct dwc2_hsotg
1988 *
1989 * Must be called with interrupt disabled and spinlock held
1990 */
1991void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
1992{
1993 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
1994
1995 /*
1996 * The root hub should be disconnected before this function is called.
1997 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
1998 * and the QH lists (via ..._hcd_endpoint_disable).
1999 */
2000
2001 /* Turn off all host-specific interrupts */
2002 dwc2_disable_host_interrupts(hsotg);
2003
2004 /* Turn off the vbus power */
2005 dev_dbg(hsotg->dev, "PortPower off\n");
2006 dwc2_writel(0, hsotg->regs + HPRT0);
2007}
2008
2009/* Caller must hold driver lock */
2010static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
2011 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh,
2012 struct dwc2_qtd *qtd)
2013{
2014 u32 intr_mask;
2015 int retval;
2016 int dev_speed;
2017
2018 if (!hsotg->flags.b.port_connect_status) {
2019 /* No longer connected */
2020 dev_err(hsotg->dev, "Not connected\n");
2021 return -ENODEV;
2022 }
2023
2024 dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
2025
2026 /* Some configurations cannot support LS traffic on a FS root port */
2027 if ((dev_speed == USB_SPEED_LOW) &&
2028 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
2029 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
2030 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
2031 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
2032
2033 if (prtspd == HPRT0_SPD_FULL_SPEED)
2034 return -ENODEV;
2035 }
2036
2037 if (!qtd)
2038 return -EINVAL;
2039
2040 dwc2_hcd_qtd_init(qtd, urb);
2041 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
2042 if (retval) {
2043 dev_err(hsotg->dev,
2044 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
2045 retval);
2046 return retval;
2047 }
2048
2049 intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
2050 if (!(intr_mask & GINTSTS_SOF)) {
2051 enum dwc2_transaction_type tr_type;
2052
2053 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
2054 !(qtd->urb->flags & URB_GIVEBACK_ASAP))
2055 /*
2056 * Do not schedule SG transactions until qtd has
2057 * URB_GIVEBACK_ASAP set
2058 */
2059 return 0;
2060
2061 tr_type = dwc2_hcd_select_transactions(hsotg);
2062 if (tr_type != DWC2_TRANSACTION_NONE)
2063 dwc2_hcd_queue_transactions(hsotg, tr_type);
2064 }
2065
2066 return 0;
2067}
2068
2069/* Must be called with interrupt disabled and spinlock held */
2070static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
2071 struct dwc2_hcd_urb *urb)
2072{
2073 struct dwc2_qh *qh;
2074 struct dwc2_qtd *urb_qtd;
2075
2076 urb_qtd = urb->qtd;
2077 if (!urb_qtd) {
2078 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
2079 return -EINVAL;
2080 }
2081
2082 qh = urb_qtd->qh;
2083 if (!qh) {
2084 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
2085 return -EINVAL;
2086 }
2087
2088 urb->priv = NULL;
2089
2090 if (urb_qtd->in_process && qh->channel) {
2091 dwc2_dump_channel_info(hsotg, qh->channel);
2092
2093 /* The QTD is in process (it has been assigned to a channel) */
2094 if (hsotg->flags.b.port_connect_status)
2095 /*
2096 * If still connected (i.e. in host mode), halt the
2097 * channel so it can be used for other transfers. If
2098 * no longer connected, the host registers can't be
2099 * written to halt the channel since the core is in
2100 * device mode.
2101 */
2102 dwc2_hc_halt(hsotg, qh->channel,
2103 DWC2_HC_XFER_URB_DEQUEUE);
2104 }
2105
2106 /*
2107 * Free the QTD and clean up the associated QH. Leave the QH in the
2108 * schedule if it has any remaining QTDs.
2109 */
2110 if (hsotg->params.dma_desc_enable <= 0) {
2111 u8 in_process = urb_qtd->in_process;
2112
2113 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
2114 if (in_process) {
2115 dwc2_hcd_qh_deactivate(hsotg, qh, 0);
2116 qh->channel = NULL;
2117 } else if (list_empty(&qh->qtd_list)) {
2118 dwc2_hcd_qh_unlink(hsotg, qh);
2119 }
2120 } else {
2121 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
2122 }
2123
2124 return 0;
2125}
2126
2127/* Must NOT be called with interrupt disabled or spinlock held */
2128static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
2129 struct usb_host_endpoint *ep, int retry)
2130{
2131 struct dwc2_qtd *qtd, *qtd_tmp;
2132 struct dwc2_qh *qh;
2133 unsigned long flags;
2134 int rc;
2135
2136 spin_lock_irqsave(&hsotg->lock, flags);
2137
2138 qh = ep->hcpriv;
2139 if (!qh) {
2140 rc = -EINVAL;
2141 goto err;
2142 }
2143
2144 while (!list_empty(&qh->qtd_list) && retry--) {
2145 if (retry == 0) {
2146 dev_err(hsotg->dev,
2147 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
2148 rc = -EBUSY;
2149 goto err;
2150 }
2151
2152 spin_unlock_irqrestore(&hsotg->lock, flags);
2153 usleep_range(20000, 40000);
2154 spin_lock_irqsave(&hsotg->lock, flags);
2155 qh = ep->hcpriv;
2156 if (!qh) {
2157 rc = -EINVAL;
2158 goto err;
2159 }
2160 }
2161
2162 dwc2_hcd_qh_unlink(hsotg, qh);
2163
2164 /* Free each QTD in the QH's QTD list */
2165 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
2166 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
2167
2168 ep->hcpriv = NULL;
2169
2170 if (qh->channel && qh->channel->qh == qh)
2171 qh->channel->qh = NULL;
2172
2173 spin_unlock_irqrestore(&hsotg->lock, flags);
2174
2175 dwc2_hcd_qh_free(hsotg, qh);
2176
2177 return 0;
2178
2179err:
2180 ep->hcpriv = NULL;
2181 spin_unlock_irqrestore(&hsotg->lock, flags);
2182
2183 return rc;
2184}
2185
2186/* Must be called with interrupt disabled and spinlock held */
2187static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
2188 struct usb_host_endpoint *ep)
2189{
2190 struct dwc2_qh *qh = ep->hcpriv;
2191
2192 if (!qh)
2193 return -EINVAL;
2194
2195 qh->data_toggle = DWC2_HC_PID_DATA0;
2196
2197 return 0;
2198}
2199
2200/**
2201 * dwc2_core_init() - Initializes the DWC_otg controller registers and
2202 * prepares the core for device mode or host mode operation
2203 *
2204 * @hsotg: Programming view of the DWC_otg controller
2205 * @initial_setup: If true then this is the first init for this instance.
2206 */
2207static int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
2208{
2209 u32 usbcfg, otgctl;
2210 int retval;
2211
2212 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2213
2214 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2215
2216 /* Set ULPI External VBUS bit if needed */
2217 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
2218 if (hsotg->params.phy_ulpi_ext_vbus ==
2219 DWC2_PHY_ULPI_EXTERNAL_VBUS)
2220 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;
2221
2222 /* Set external TS Dline pulsing bit if needed */
2223 usbcfg &= ~GUSBCFG_TERMSELDLPULSE;
2224 if (hsotg->params.ts_dline > 0)
2225 usbcfg |= GUSBCFG_TERMSELDLPULSE;
2226
2227 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
2228
2229 /*
2230 * Reset the Controller
2231 *
2232 * We only need to reset the controller if this is a re-init.
2233 * For the first init we know for sure that earlier code reset us (it
2234 * needed to in order to properly detect various parameters).
2235 */
2236 if (!initial_setup) {
2237 retval = dwc2_core_reset_and_force_dr_mode(hsotg);
2238 if (retval) {
2239 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n",
2240 __func__);
2241 return retval;
2242 }
2243 }
2244
2245 /*
2246 * This needs to happen in FS mode before any other programming occurs
2247 */
2248 retval = dwc2_phy_init(hsotg, initial_setup);
2249 if (retval)
2250 return retval;
2251
2252 /* Program the GAHBCFG Register */
2253 retval = dwc2_gahbcfg_init(hsotg);
2254 if (retval)
2255 return retval;
2256
2257 /* Program the GUSBCFG register */
2258 dwc2_gusbcfg_init(hsotg);
2259
2260 /* Program the GOTGCTL register */
2261 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2262 otgctl &= ~GOTGCTL_OTGVER;
2263 if (hsotg->params.otg_ver > 0)
2264 otgctl |= GOTGCTL_OTGVER;
2265 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2266 dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->params.otg_ver);
2267
2268 /* Clear the SRP success bit for FS-I2c */
2269 hsotg->srp_success = 0;
2270
2271 /* Enable common interrupts */
2272 dwc2_enable_common_interrupts(hsotg);
2273
2274 /*
2275 * Do device or host initialization based on mode during PCD and
2276 * HCD initialization
2277 */
2278 if (dwc2_is_host_mode(hsotg)) {
2279 dev_dbg(hsotg->dev, "Host Mode\n");
2280 hsotg->op_state = OTG_STATE_A_HOST;
2281 } else {
2282 dev_dbg(hsotg->dev, "Device Mode\n");
2283 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
2284 }
2285
2286 return 0;
2287}
2288
2289/**
2290 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
2291 * Host mode
2292 *
2293 * @hsotg: Programming view of DWC_otg controller
2294 *
2295 * This function flushes the Tx and Rx FIFOs and flushes any entries in the
2296 * request queues. Host channels are reset to ensure that they are ready for
2297 * performing transfers.
2298 */
2299static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2300{
2301 u32 hcfg, hfir, otgctl;
2302
2303 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2304
2305 /* Restart the Phy Clock */
2306 dwc2_writel(0, hsotg->regs + PCGCTL);
2307
2308 /* Initialize Host Configuration Register */
2309 dwc2_init_fs_ls_pclk_sel(hsotg);
2310 if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
2311 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) {
2312 hcfg = dwc2_readl(hsotg->regs + HCFG);
2313 hcfg |= HCFG_FSLSSUPP;
2314 dwc2_writel(hcfg, hsotg->regs + HCFG);
2315 }
2316
2317 /*
2318 * This bit allows dynamic reloading of the HFIR register during
2319 * runtime. This bit needs to be programmed during initial configuration
2320 * and its value must not be changed during runtime.
2321 */
2322 if (hsotg->params.reload_ctl > 0) {
2323 hfir = dwc2_readl(hsotg->regs + HFIR);
2324 hfir |= HFIR_RLDCTRL;
2325 dwc2_writel(hfir, hsotg->regs + HFIR);
2326 }
2327
2328 if (hsotg->params.dma_desc_enable > 0) {
2329 u32 op_mode = hsotg->hw_params.op_mode;
2330
2331 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
2332 !hsotg->hw_params.dma_desc_enable ||
2333 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
2334 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
2335 op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
2336 dev_err(hsotg->dev,
2337 "Hardware does not support descriptor DMA mode -\n");
2338 dev_err(hsotg->dev,
2339 "falling back to buffer DMA mode.\n");
2340 hsotg->params.dma_desc_enable = 0;
2341 } else {
2342 hcfg = dwc2_readl(hsotg->regs + HCFG);
2343 hcfg |= HCFG_DESCDMA;
2344 dwc2_writel(hcfg, hsotg->regs + HCFG);
2345 }
2346 }
2347
2348 /* Configure data FIFO sizes */
2349 dwc2_config_fifos(hsotg);
2350
2351 /* TODO - check this */
2352 /* Clear Host Set HNP Enable in the OTG Control Register */
2353 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2354 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2355 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2356
2357 /* Make sure the FIFOs are flushed */
2358 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
2359 dwc2_flush_rx_fifo(hsotg);
2360
2361 /* Clear Host Set HNP Enable in the OTG Control Register */
2362 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2363 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2364 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2365
2366 if (hsotg->params.dma_desc_enable <= 0) {
2367 int num_channels, i;
2368 u32 hcchar;
2369
2370 /* Flush out any leftover queued requests */
2371 num_channels = hsotg->params.host_channels;
2372 for (i = 0; i < num_channels; i++) {
2373 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2374 hcchar &= ~HCCHAR_CHENA;
2375 hcchar |= HCCHAR_CHDIS;
2376 hcchar &= ~HCCHAR_EPDIR;
2377 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
2378 }
2379
2380 /* Halt all channels to put them into a known state */
2381 for (i = 0; i < num_channels; i++) {
2382 int count = 0;
2383
2384 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2385 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
2386 hcchar &= ~HCCHAR_EPDIR;
2387 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
2388 dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
2389 __func__, i);
2390 do {
2391 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2392 if (++count > 1000) {
2393 dev_err(hsotg->dev,
2394 "Unable to clear enable on channel %d\n",
2395 i);
2396 break;
2397 }
2398 udelay(1);
2399 } while (hcchar & HCCHAR_CHENA);
2400 }
2401 }
2402
2403 /* Turn on the vbus power */
2404 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
2405 if (hsotg->op_state == OTG_STATE_A_HOST) {
2406 u32 hprt0 = dwc2_read_hprt0(hsotg);
2407
2408 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
2409 !!(hprt0 & HPRT0_PWR));
2410 if (!(hprt0 & HPRT0_PWR)) {
2411 hprt0 |= HPRT0_PWR;
2412 dwc2_writel(hprt0, hsotg->regs + HPRT0);
2413 }
2414 }
2415
2416 dwc2_enable_host_interrupts(hsotg);
2417}
2418
2419/*
2420 * Initializes dynamic portions of the DWC_otg HCD state
2421 *
2422 * Must be called with interrupt disabled and spinlock held
2423 */
2424static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
2425{
2426 struct dwc2_host_chan *chan, *chan_tmp;
2427 int num_channels;
2428 int i;
2429
2430 hsotg->flags.d32 = 0;
2431 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
2432
2433 if (hsotg->params.uframe_sched > 0) {
2434 hsotg->available_host_channels =
2435 hsotg->params.host_channels;
2436 } else {
2437 hsotg->non_periodic_channels = 0;
2438 hsotg->periodic_channels = 0;
2439 }
2440
2441 /*
2442 * Put all channels in the free channel list and clean up channel
2443 * states
2444 */
2445 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
2446 hc_list_entry)
2447 list_del_init(&chan->hc_list_entry);
2448
2449 num_channels = hsotg->params.host_channels;
2450 for (i = 0; i < num_channels; i++) {
2451 chan = hsotg->hc_ptr_array[i];
2452 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
2453 dwc2_hc_cleanup(hsotg, chan);
2454 }
2455
2456 /* Initialize the DWC core for host mode operation */
2457 dwc2_core_host_init(hsotg);
2458}
2459
2460static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
2461 struct dwc2_host_chan *chan,
2462 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
2463{
2464 int hub_addr, hub_port;
2465
2466 chan->do_split = 1;
2467 chan->xact_pos = qtd->isoc_split_pos;
2468 chan->complete_split = qtd->complete_split;
2469 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
2470 chan->hub_addr = (u8)hub_addr;
2471 chan->hub_port = (u8)hub_port;
2472}
2473
2474static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
2475 struct dwc2_host_chan *chan,
2476 struct dwc2_qtd *qtd)
2477{
2478 struct dwc2_hcd_urb *urb = qtd->urb;
2479 struct dwc2_hcd_iso_packet_desc *frame_desc;
2480
2481 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
2482 case USB_ENDPOINT_XFER_CONTROL:
2483 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
2484
2485 switch (qtd->control_phase) {
2486 case DWC2_CONTROL_SETUP:
2487 dev_vdbg(hsotg->dev, " Control setup transaction\n");
2488 chan->do_ping = 0;
2489 chan->ep_is_in = 0;
2490 chan->data_pid_start = DWC2_HC_PID_SETUP;
2491 if (hsotg->params.host_dma > 0)
2492 chan->xfer_dma = urb->setup_dma;
2493 else
2494 chan->xfer_buf = urb->setup_packet;
2495 chan->xfer_len = 8;
2496 break;
2497
2498 case DWC2_CONTROL_DATA:
2499 dev_vdbg(hsotg->dev, " Control data transaction\n");
2500 chan->data_pid_start = qtd->data_toggle;
2501 break;
2502
2503 case DWC2_CONTROL_STATUS:
2504 /*
2505 * Direction is opposite of data direction or IN if no
2506 * data
2507 */
2508 dev_vdbg(hsotg->dev, " Control status transaction\n");
2509 if (urb->length == 0)
2510 chan->ep_is_in = 1;
2511 else
2512 chan->ep_is_in =
2513 dwc2_hcd_is_pipe_out(&urb->pipe_info);
2514 if (chan->ep_is_in)
2515 chan->do_ping = 0;
2516 chan->data_pid_start = DWC2_HC_PID_DATA1;
2517 chan->xfer_len = 0;
2518 if (hsotg->params.host_dma > 0)
2519 chan->xfer_dma = hsotg->status_buf_dma;
2520 else
2521 chan->xfer_buf = hsotg->status_buf;
2522 break;
2523 }
2524 break;
2525
2526 case USB_ENDPOINT_XFER_BULK:
2527 chan->ep_type = USB_ENDPOINT_XFER_BULK;
2528 break;
2529
2530 case USB_ENDPOINT_XFER_INT:
2531 chan->ep_type = USB_ENDPOINT_XFER_INT;
2532 break;
2533
2534 case USB_ENDPOINT_XFER_ISOC:
2535 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
2536 if (hsotg->params.dma_desc_enable > 0)
2537 break;
2538
2539 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
2540 frame_desc->status = 0;
2541
2542 if (hsotg->params.host_dma > 0) {
2543 chan->xfer_dma = urb->dma;
2544 chan->xfer_dma += frame_desc->offset +
2545 qtd->isoc_split_offset;
2546 } else {
2547 chan->xfer_buf = urb->buf;
2548 chan->xfer_buf += frame_desc->offset +
2549 qtd->isoc_split_offset;
2550 }
2551
2552 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
2553
2554 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
2555 if (chan->xfer_len <= 188)
2556 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
2557 else
2558 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
2559 }
2560 break;
2561 }
2562}
2563
2564#define DWC2_USB_DMA_ALIGN 4
2565
2566struct dma_aligned_buffer {
2567 void *kmalloc_ptr;
2568 void *old_xfer_buffer;
2569 u8 data[0];
2570};
2571
2572static void dwc2_free_dma_aligned_buffer(struct urb *urb)
2573{
2574 struct dma_aligned_buffer *temp;
2575
2576 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
2577 return;
2578
2579 temp = container_of(urb->transfer_buffer,
2580 struct dma_aligned_buffer, data);
2581
2582 if (usb_urb_dir_in(urb))
2583 memcpy(temp->old_xfer_buffer, temp->data,
2584 urb->transfer_buffer_length);
2585 urb->transfer_buffer = temp->old_xfer_buffer;
2586 kfree(temp->kmalloc_ptr);
2587
2588 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
2589}
2590
2591static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
2592{
2593 struct dma_aligned_buffer *temp, *kmalloc_ptr;
2594 size_t kmalloc_size;
2595
2596 if (urb->num_sgs || urb->sg ||
2597 urb->transfer_buffer_length == 0 ||
2598 !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1)))
2599 return 0;
2600
2601 /* Allocate a buffer with enough padding for alignment */
2602 kmalloc_size = urb->transfer_buffer_length +
2603 sizeof(struct dma_aligned_buffer) + DWC2_USB_DMA_ALIGN - 1;
2604
2605 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
2606 if (!kmalloc_ptr)
2607 return -ENOMEM;
2608
2609 /* Position our struct dma_aligned_buffer such that data is aligned */
2610 temp = PTR_ALIGN(kmalloc_ptr + 1, DWC2_USB_DMA_ALIGN) - 1;
2611 temp->kmalloc_ptr = kmalloc_ptr;
2612 temp->old_xfer_buffer = urb->transfer_buffer;
2613 if (usb_urb_dir_out(urb))
2614 memcpy(temp->data, urb->transfer_buffer,
2615 urb->transfer_buffer_length);
2616 urb->transfer_buffer = temp->data;
2617
2618 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
2619
2620 return 0;
2621}
2622
2623static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
2624 gfp_t mem_flags)
2625{
2626 int ret;
2627
2628 /* We assume setup_dma is always aligned; warn if not */
2629 WARN_ON_ONCE(urb->setup_dma &&
2630 (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1)));
2631
2632 ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags);
2633 if (ret)
2634 return ret;
2635
2636 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2637 if (ret)
2638 dwc2_free_dma_aligned_buffer(urb);
2639
2640 return ret;
2641}
2642
2643static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
2644{
2645 usb_hcd_unmap_urb_for_dma(hcd, urb);
2646 dwc2_free_dma_aligned_buffer(urb);
2647}
2648
2649/**
2650 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
2651 * channel and initializes the host channel to perform the transactions. The
2652 * host channel is removed from the free list.
2653 *
2654 * @hsotg: The HCD state structure
2655 * @qh: Transactions from the first QTD for this QH are selected and assigned
2656 * to a free host channel
2657 */
2658static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
2659{
2660 struct dwc2_host_chan *chan;
2661 struct dwc2_hcd_urb *urb;
2662 struct dwc2_qtd *qtd;
2663
2664 if (dbg_qh(qh))
2665 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
2666
2667 if (list_empty(&qh->qtd_list)) {
2668 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
2669 return -ENOMEM;
2670 }
2671
2672 if (list_empty(&hsotg->free_hc_list)) {
2673 dev_dbg(hsotg->dev, "No free channel to assign\n");
2674 return -ENOMEM;
2675 }
2676
2677 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
2678 hc_list_entry);
2679
2680 /* Remove host channel from free list */
2681 list_del_init(&chan->hc_list_entry);
2682
2683 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
2684 urb = qtd->urb;
2685 qh->channel = chan;
2686 qtd->in_process = 1;
2687
2688 /*
2689 * Use usb_pipedevice to determine device address. This address is
2690 * 0 before the SET_ADDRESS command and the correct address afterward.
2691 */
2692 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
2693 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
2694 chan->speed = qh->dev_speed;
2695 chan->max_packet = dwc2_max_packet(qh->maxp);
2696
2697 chan->xfer_started = 0;
2698 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2699 chan->error_state = (qtd->error_count > 0);
2700 chan->halt_on_queue = 0;
2701 chan->halt_pending = 0;
2702 chan->requests = 0;
2703
2704 /*
2705 * The following values may be modified in the transfer type section
2706 * below. The xfer_len value may be reduced when the transfer is
2707 * started to accommodate the max widths of the XferSize and PktCnt
2708 * fields in the HCTSIZn register.
2709 */
2710
2711 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
2712 if (chan->ep_is_in)
2713 chan->do_ping = 0;
2714 else
2715 chan->do_ping = qh->ping_state;
2716
2717 chan->data_pid_start = qh->data_toggle;
2718 chan->multi_count = 1;
2719
2720 if (urb->actual_length > urb->length &&
2721 !dwc2_hcd_is_pipe_in(&urb->pipe_info))
2722 urb->actual_length = urb->length;
2723
2724 if (hsotg->params.host_dma > 0)
2725 chan->xfer_dma = urb->dma + urb->actual_length;
2726 else
2727 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
2728
2729 chan->xfer_len = urb->length - urb->actual_length;
2730 chan->xfer_count = 0;
2731
2732 /* Set the split attributes if required */
2733 if (qh->do_split)
2734 dwc2_hc_init_split(hsotg, chan, qtd, urb);
2735 else
2736 chan->do_split = 0;
2737
2738 /* Set the transfer attributes */
2739 dwc2_hc_init_xfer(hsotg, chan, qtd);
2740
2741 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
2742 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
2743 /*
2744 * This value may be modified when the transfer is started
2745 * to reflect the actual transfer length
2746 */
2747 chan->multi_count = dwc2_hb_mult(qh->maxp);
2748
2749 if (hsotg->params.dma_desc_enable > 0) {
2750 chan->desc_list_addr = qh->desc_list_dma;
2751 chan->desc_list_sz = qh->desc_list_sz;
2752 }
2753
2754 dwc2_hc_init(hsotg, chan);
2755 chan->qh = qh;
2756
2757 return 0;
2758}
2759
2760/**
2761 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
2762 * schedule and assigns them to available host channels. Called from the HCD
2763 * interrupt handler functions.
2764 *
2765 * @hsotg: The HCD state structure
2766 *
2767 * Return: The types of new transactions that were assigned to host channels
2768 */
2769enum dwc2_transaction_type dwc2_hcd_select_transactions(
2770 struct dwc2_hsotg *hsotg)
2771{
2772 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
2773 struct list_head *qh_ptr;
2774 struct dwc2_qh *qh;
2775 int num_channels;
2776
2777#ifdef DWC2_DEBUG_SOF
2778 dev_vdbg(hsotg->dev, " Select Transactions\n");
2779#endif
2780
2781 /* Process entries in the periodic ready list */
2782 qh_ptr = hsotg->periodic_sched_ready.next;
2783 while (qh_ptr != &hsotg->periodic_sched_ready) {
2784 if (list_empty(&hsotg->free_hc_list))
2785 break;
2786 if (hsotg->params.uframe_sched > 0) {
2787 if (hsotg->available_host_channels <= 1)
2788 break;
2789 hsotg->available_host_channels--;
2790 }
2791 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2792 if (dwc2_assign_and_init_hc(hsotg, qh))
2793 break;
2794
2795 /*
2796 * Move the QH from the periodic ready schedule to the
2797 * periodic assigned schedule
2798 */
2799 qh_ptr = qh_ptr->next;
2800 list_move_tail(&qh->qh_list_entry,
2801 &hsotg->periodic_sched_assigned);
2802 ret_val = DWC2_TRANSACTION_PERIODIC;
2803 }
2804
2805 /*
2806 * Process entries in the inactive portion of the non-periodic
2807 * schedule. Some free host channels may not be used if they are
2808 * reserved for periodic transfers.
2809 */
2810 num_channels = hsotg->params.host_channels;
2811 qh_ptr = hsotg->non_periodic_sched_inactive.next;
2812 while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
2813 if (hsotg->params.uframe_sched <= 0 &&
2814 hsotg->non_periodic_channels >= num_channels -
2815 hsotg->periodic_channels)
2816 break;
2817 if (list_empty(&hsotg->free_hc_list))
2818 break;
2819 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2820 if (hsotg->params.uframe_sched > 0) {
2821 if (hsotg->available_host_channels < 1)
2822 break;
2823 hsotg->available_host_channels--;
2824 }
2825
2826 if (dwc2_assign_and_init_hc(hsotg, qh))
2827 break;
2828
2829 /*
2830 * Move the QH from the non-periodic inactive schedule to the
2831 * non-periodic active schedule
2832 */
2833 qh_ptr = qh_ptr->next;
2834 list_move_tail(&qh->qh_list_entry,
2835 &hsotg->non_periodic_sched_active);
2836
2837 if (ret_val == DWC2_TRANSACTION_NONE)
2838 ret_val = DWC2_TRANSACTION_NON_PERIODIC;
2839 else
2840 ret_val = DWC2_TRANSACTION_ALL;
2841
2842 if (hsotg->params.uframe_sched <= 0)
2843 hsotg->non_periodic_channels++;
2844 }
2845
2846 return ret_val;
2847}
2848
2849/**
2850 * dwc2_queue_transaction() - Attempts to queue a single transaction request for
2851 * a host channel associated with either a periodic or non-periodic transfer
2852 *
2853 * @hsotg: The HCD state structure
2854 * @chan: Host channel descriptor associated with either a periodic or
2855 * non-periodic transfer
2856 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
2857 * for periodic transfers or the non-periodic Tx FIFO
2858 * for non-periodic transfers
2859 *
2860 * Return: 1 if a request is queued and more requests may be needed to
2861 * complete the transfer, 0 if no more requests are required for this
2862 * transfer, -1 if there is insufficient space in the Tx FIFO
2863 *
2864 * This function assumes that there is space available in the appropriate
2865 * request queue. For an OUT transfer or SETUP transaction in Slave mode,
2866 * it checks whether space is available in the appropriate Tx FIFO.
2867 *
2868 * Must be called with interrupt disabled and spinlock held
2869 */
2870static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
2871 struct dwc2_host_chan *chan,
2872 u16 fifo_dwords_avail)
2873{
2874 int retval = 0;
2875
2876 if (chan->do_split)
2877 /* Put ourselves on the list to keep order straight */
2878 list_move_tail(&chan->split_order_list_entry,
2879 &hsotg->split_order);
2880
2881 if (hsotg->params.host_dma > 0) {
2882 if (hsotg->params.dma_desc_enable > 0) {
2883 if (!chan->xfer_started ||
2884 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
2885 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
2886 chan->qh->ping_state = 0;
2887 }
2888 } else if (!chan->xfer_started) {
2889 dwc2_hc_start_transfer(hsotg, chan);
2890 chan->qh->ping_state = 0;
2891 }
2892 } else if (chan->halt_pending) {
2893 /* Don't queue a request if the channel has been halted */
2894 } else if (chan->halt_on_queue) {
2895 dwc2_hc_halt(hsotg, chan, chan->halt_status);
2896 } else if (chan->do_ping) {
2897 if (!chan->xfer_started)
2898 dwc2_hc_start_transfer(hsotg, chan);
2899 } else if (!chan->ep_is_in ||
2900 chan->data_pid_start == DWC2_HC_PID_SETUP) {
2901 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
2902 if (!chan->xfer_started) {
2903 dwc2_hc_start_transfer(hsotg, chan);
2904 retval = 1;
2905 } else {
2906 retval = dwc2_hc_continue_transfer(hsotg, chan);
2907 }
2908 } else {
2909 retval = -1;
2910 }
2911 } else {
2912 if (!chan->xfer_started) {
2913 dwc2_hc_start_transfer(hsotg, chan);
2914 retval = 1;
2915 } else {
2916 retval = dwc2_hc_continue_transfer(hsotg, chan);
2917 }
2918 }
2919
2920 return retval;
2921}
2922
2923/*
2924 * Processes periodic channels for the next frame and queues transactions for
2925 * these channels to the DWC_otg controller. After queueing transactions, the
2926 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
2927 * to queue as Periodic Tx FIFO or request queue space becomes available.
2928 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
2929 *
2930 * Must be called with interrupt disabled and spinlock held
2931 */
2932static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
2933{
2934 struct list_head *qh_ptr;
2935 struct dwc2_qh *qh;
2936 u32 tx_status;
2937 u32 fspcavail;
2938 u32 gintmsk;
2939 int status;
2940 bool no_queue_space = false;
2941 bool no_fifo_space = false;
2942 u32 qspcavail;
2943
2944 /* If empty list then just adjust interrupt enables */
2945 if (list_empty(&hsotg->periodic_sched_assigned))
2946 goto exit;
2947
2948 if (dbg_perio())
2949 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
2950
2951 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
2952 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2953 TXSTS_QSPCAVAIL_SHIFT;
2954 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
2955 TXSTS_FSPCAVAIL_SHIFT;
2956
2957 if (dbg_perio()) {
2958 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n",
2959 qspcavail);
2960 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n",
2961 fspcavail);
2962 }
2963
2964 qh_ptr = hsotg->periodic_sched_assigned.next;
2965 while (qh_ptr != &hsotg->periodic_sched_assigned) {
2966 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
2967 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
2968 TXSTS_QSPCAVAIL_SHIFT;
2969 if (qspcavail == 0) {
2970 no_queue_space = 1;
2971 break;
2972 }
2973
2974 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2975 if (!qh->channel) {
2976 qh_ptr = qh_ptr->next;
2977 continue;
2978 }
2979
2980 /* Make sure EP's TT buffer is clean before queueing qtds */
2981 if (qh->tt_buffer_dirty) {
2982 qh_ptr = qh_ptr->next;
2983 continue;
2984 }
2985
2986 /*
2987 * Set a flag if we're queuing high-bandwidth in slave mode.
2988 * The flag prevents any halts to get into the request queue in
2989 * the middle of multiple high-bandwidth packets getting queued.
2990 */
2991 if (hsotg->params.host_dma <= 0 &&
2992 qh->channel->multi_count > 1)
2993 hsotg->queuing_high_bandwidth = 1;
2994
2995 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
2996 TXSTS_FSPCAVAIL_SHIFT;
2997 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
2998 if (status < 0) {
2999 no_fifo_space = 1;
3000 break;
3001 }
3002
3003 /*
3004 * In Slave mode, stay on the current transfer until there is
3005 * nothing more to do or the high-bandwidth request count is
3006 * reached. In DMA mode, only need to queue one request. The
3007 * controller automatically handles multiple packets for
3008 * high-bandwidth transfers.
3009 */
3010 if (hsotg->params.host_dma > 0 || status == 0 ||
3011 qh->channel->requests == qh->channel->multi_count) {
3012 qh_ptr = qh_ptr->next;
3013 /*
3014 * Move the QH from the periodic assigned schedule to
3015 * the periodic queued schedule
3016 */
3017 list_move_tail(&qh->qh_list_entry,
3018 &hsotg->periodic_sched_queued);
3019
3020 /* done queuing high bandwidth */
3021 hsotg->queuing_high_bandwidth = 0;
3022 }
3023 }
3024
3025exit:
3026 if (no_queue_space || no_fifo_space ||
3027 (hsotg->params.host_dma <= 0 &&
3028 !list_empty(&hsotg->periodic_sched_assigned))) {
3029 /*
3030 * May need to queue more transactions as the request
3031 * queue or Tx FIFO empties. Enable the periodic Tx
3032 * FIFO empty interrupt. (Always use the half-empty
3033 * level to ensure that new requests are loaded as
3034 * soon as possible.)
3035 */
3036 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3037 if (!(gintmsk & GINTSTS_PTXFEMP)) {
3038 gintmsk |= GINTSTS_PTXFEMP;
3039 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3040 }
3041 } else {
3042 /*
3043 * Disable the Tx FIFO empty interrupt since there are
3044 * no more transactions that need to be queued right
3045 * now. This function is called from interrupt
3046 * handlers to queue more transactions as transfer
3047 * states change.
3048 */
3049 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3050 if (gintmsk & GINTSTS_PTXFEMP) {
3051 gintmsk &= ~GINTSTS_PTXFEMP;
3052 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3053 }
3054 }
3055}
3056
3057/*
3058 * Processes active non-periodic channels and queues transactions for these
3059 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
3060 * FIFO Empty interrupt is enabled if there are more transactions to queue as
3061 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
3062 * FIFO Empty interrupt is disabled.
3063 *
3064 * Must be called with interrupt disabled and spinlock held
3065 */
3066static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
3067{
3068 struct list_head *orig_qh_ptr;
3069 struct dwc2_qh *qh;
3070 u32 tx_status;
3071 u32 qspcavail;
3072 u32 fspcavail;
3073 u32 gintmsk;
3074 int status;
3075 int no_queue_space = 0;
3076 int no_fifo_space = 0;
3077 int more_to_do = 0;
3078
3079 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
3080
3081 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3082 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3083 TXSTS_QSPCAVAIL_SHIFT;
3084 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3085 TXSTS_FSPCAVAIL_SHIFT;
3086 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n",
3087 qspcavail);
3088 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n",
3089 fspcavail);
3090
3091 /*
3092 * Keep track of the starting point. Skip over the start-of-list
3093 * entry.
3094 */
3095 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
3096 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3097 orig_qh_ptr = hsotg->non_periodic_qh_ptr;
3098
3099 /*
3100 * Process once through the active list or until no more space is
3101 * available in the request queue or the Tx FIFO
3102 */
3103 do {
3104 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3105 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3106 TXSTS_QSPCAVAIL_SHIFT;
3107 if (hsotg->params.host_dma <= 0 && qspcavail == 0) {
3108 no_queue_space = 1;
3109 break;
3110 }
3111
3112 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
3113 qh_list_entry);
3114 if (!qh->channel)
3115 goto next;
3116
3117 /* Make sure EP's TT buffer is clean before queueing qtds */
3118 if (qh->tt_buffer_dirty)
3119 goto next;
3120
3121 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3122 TXSTS_FSPCAVAIL_SHIFT;
3123 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3124
3125 if (status > 0) {
3126 more_to_do = 1;
3127 } else if (status < 0) {
3128 no_fifo_space = 1;
3129 break;
3130 }
3131next:
3132 /* Advance to next QH, skipping start-of-list entry */
3133 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3134 if (hsotg->non_periodic_qh_ptr ==
3135 &hsotg->non_periodic_sched_active)
3136 hsotg->non_periodic_qh_ptr =
3137 hsotg->non_periodic_qh_ptr->next;
3138 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
3139
3140 if (hsotg->params.host_dma <= 0) {
3141 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3142 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3143 TXSTS_QSPCAVAIL_SHIFT;
3144 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3145 TXSTS_FSPCAVAIL_SHIFT;
3146 dev_vdbg(hsotg->dev,
3147 " NP Tx Req Queue Space Avail (after queue): %d\n",
3148 qspcavail);
3149 dev_vdbg(hsotg->dev,
3150 " NP Tx FIFO Space Avail (after queue): %d\n",
3151 fspcavail);
3152
3153 if (more_to_do || no_queue_space || no_fifo_space) {
3154 /*
3155 * May need to queue more transactions as the request
3156 * queue or Tx FIFO empties. Enable the non-periodic
3157 * Tx FIFO empty interrupt. (Always use the half-empty
3158 * level to ensure that new requests are loaded as
3159 * soon as possible.)
3160 */
3161 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3162 gintmsk |= GINTSTS_NPTXFEMP;
3163 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3164 } else {
3165 /*
3166 * Disable the Tx FIFO empty interrupt since there are
3167 * no more transactions that need to be queued right
3168 * now. This function is called from interrupt
3169 * handlers to queue more transactions as transfer
3170 * states change.
3171 */
3172 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3173 gintmsk &= ~GINTSTS_NPTXFEMP;
3174 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3175 }
3176 }
3177}
3178
3179/**
3180 * dwc2_hcd_queue_transactions() - Processes the currently active host channels
3181 * and queues transactions for these channels to the DWC_otg controller. Called
3182 * from the HCD interrupt handler functions.
3183 *
3184 * @hsotg: The HCD state structure
3185 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
3186 * or both)
3187 *
3188 * Must be called with interrupt disabled and spinlock held
3189 */
3190void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
3191 enum dwc2_transaction_type tr_type)
3192{
3193#ifdef DWC2_DEBUG_SOF
3194 dev_vdbg(hsotg->dev, "Queue Transactions\n");
3195#endif
3196 /* Process host channels associated with periodic transfers */
3197 if (tr_type == DWC2_TRANSACTION_PERIODIC ||
3198 tr_type == DWC2_TRANSACTION_ALL)
3199 dwc2_process_periodic_channels(hsotg);
3200
3201 /* Process host channels associated with non-periodic transfers */
3202 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
3203 tr_type == DWC2_TRANSACTION_ALL) {
3204 if (!list_empty(&hsotg->non_periodic_sched_active)) {
3205 dwc2_process_non_periodic_channels(hsotg);
3206 } else {
3207 /*
3208 * Ensure NP Tx FIFO empty interrupt is disabled when
3209 * there are no non-periodic transfers to process
3210 */
3211 u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3212
3213 gintmsk &= ~GINTSTS_NPTXFEMP;
3214 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3215 }
3216 }
3217}
3218
3219static void dwc2_conn_id_status_change(struct work_struct *work)
3220{
3221 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
3222 wf_otg);
3223 u32 count = 0;
3224 u32 gotgctl;
3225 unsigned long flags;
3226
3227 dev_dbg(hsotg->dev, "%s()\n", __func__);
3228
3229 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
3230 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
3231 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
3232 !!(gotgctl & GOTGCTL_CONID_B));
3233
3234 /* B-Device connector (Device Mode) */
3235 if (gotgctl & GOTGCTL_CONID_B) {
3236 /* Wait for switch to device mode */
3237 dev_dbg(hsotg->dev, "connId B\n");
3238 while (!dwc2_is_device_mode(hsotg)) {
3239 dev_info(hsotg->dev,
3240 "Waiting for Peripheral Mode, Mode=%s\n",
3241 dwc2_is_host_mode(hsotg) ? "Host" :
3242 "Peripheral");
3243 usleep_range(20000, 40000);
3244 if (++count > 250)
3245 break;
3246 }
3247 if (count > 250)
3248 dev_err(hsotg->dev,
3249 "Connection id status change timed out\n");
3250 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3251 dwc2_core_init(hsotg, false);
3252 dwc2_enable_global_interrupts(hsotg);
3253 spin_lock_irqsave(&hsotg->lock, flags);
3254 dwc2_hsotg_core_init_disconnected(hsotg, false);
3255 spin_unlock_irqrestore(&hsotg->lock, flags);
3256 dwc2_hsotg_core_connect(hsotg);
3257 } else {
3258 /* A-Device connector (Host Mode) */
3259 dev_dbg(hsotg->dev, "connId A\n");
3260 while (!dwc2_is_host_mode(hsotg)) {
3261 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
3262 dwc2_is_host_mode(hsotg) ?
3263 "Host" : "Peripheral");
3264 usleep_range(20000, 40000);
3265 if (++count > 250)
3266 break;
3267 }
3268 if (count > 250)
3269 dev_err(hsotg->dev,
3270 "Connection id status change timed out\n");
3271 hsotg->op_state = OTG_STATE_A_HOST;
3272
3273 /* Initialize the Core for Host mode */
3274 dwc2_core_init(hsotg, false);
3275 dwc2_enable_global_interrupts(hsotg);
3276 dwc2_hcd_start(hsotg);
3277 }
3278}
3279
3280static void dwc2_wakeup_detected(unsigned long data)
3281{
3282 struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data;
3283 u32 hprt0;
3284
3285 dev_dbg(hsotg->dev, "%s()\n", __func__);
3286
3287 /*
3288 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
3289 * so that OPT tests pass with all PHYs.)
3290 */
3291 hprt0 = dwc2_read_hprt0(hsotg);
3292 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
3293 hprt0 &= ~HPRT0_RES;
3294 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3295 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
3296 dwc2_readl(hsotg->regs + HPRT0));
3297
3298 dwc2_hcd_rem_wakeup(hsotg);
3299 hsotg->bus_suspended = 0;
3300
3301 /* Change to L0 state */
3302 hsotg->lx_state = DWC2_L0;
3303}
3304
3305static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
3306{
3307 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
3308
3309 return hcd->self.b_hnp_enable;
3310}
3311
3312/* Must NOT be called with interrupt disabled or spinlock held */
3313static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
3314{
3315 unsigned long flags;
3316 u32 hprt0;
3317 u32 pcgctl;
3318 u32 gotgctl;
3319
3320 dev_dbg(hsotg->dev, "%s()\n", __func__);
3321
3322 spin_lock_irqsave(&hsotg->lock, flags);
3323
3324 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
3325 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
3326 gotgctl |= GOTGCTL_HSTSETHNPEN;
3327 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
3328 hsotg->op_state = OTG_STATE_A_SUSPEND;
3329 }
3330
3331 hprt0 = dwc2_read_hprt0(hsotg);
3332 hprt0 |= HPRT0_SUSP;
3333 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3334
3335 hsotg->bus_suspended = 1;
3336
3337 /*
3338 * If hibernation is supported, Phy clock will be suspended
3339 * after registers are backuped.
3340 */
3341 if (!hsotg->params.hibernation) {
3342 /* Suspend the Phy Clock */
3343 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3344 pcgctl |= PCGCTL_STOPPCLK;
3345 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3346 udelay(10);
3347 }
3348
3349 /* For HNP the bus must be suspended for at least 200ms */
3350 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
3351 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3352 pcgctl &= ~PCGCTL_STOPPCLK;
3353 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3354
3355 spin_unlock_irqrestore(&hsotg->lock, flags);
3356
3357 usleep_range(200000, 250000);
3358 } else {
3359 spin_unlock_irqrestore(&hsotg->lock, flags);
3360 }
3361}
3362
3363/* Must NOT be called with interrupt disabled or spinlock held */
3364static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
3365{
3366 unsigned long flags;
3367 u32 hprt0;
3368 u32 pcgctl;
3369
3370 spin_lock_irqsave(&hsotg->lock, flags);
3371
3372 /*
3373 * If hibernation is supported, Phy clock is already resumed
3374 * after registers restore.
3375 */
3376 if (!hsotg->params.hibernation) {
3377 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3378 pcgctl &= ~PCGCTL_STOPPCLK;
3379 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3380 spin_unlock_irqrestore(&hsotg->lock, flags);
3381 usleep_range(20000, 40000);
3382 spin_lock_irqsave(&hsotg->lock, flags);
3383 }
3384
3385 hprt0 = dwc2_read_hprt0(hsotg);
3386 hprt0 |= HPRT0_RES;
3387 hprt0 &= ~HPRT0_SUSP;
3388 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3389 spin_unlock_irqrestore(&hsotg->lock, flags);
3390
3391 msleep(USB_RESUME_TIMEOUT);
3392
3393 spin_lock_irqsave(&hsotg->lock, flags);
3394 hprt0 = dwc2_read_hprt0(hsotg);
3395 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP);
3396 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3397 hsotg->bus_suspended = 0;
3398 spin_unlock_irqrestore(&hsotg->lock, flags);
3399}
3400
3401/* Handles hub class-specific requests */
3402static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3403 u16 wvalue, u16 windex, char *buf, u16 wlength)
3404{
3405 struct usb_hub_descriptor *hub_desc;
3406 int retval = 0;
3407 u32 hprt0;
3408 u32 port_status;
3409 u32 speed;
3410 u32 pcgctl;
3411
3412 switch (typereq) {
3413 case ClearHubFeature:
3414 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
3415
3416 switch (wvalue) {
3417 case C_HUB_LOCAL_POWER:
3418 case C_HUB_OVER_CURRENT:
3419 /* Nothing required here */
3420 break;
3421
3422 default:
3423 retval = -EINVAL;
3424 dev_err(hsotg->dev,
3425 "ClearHubFeature request %1xh unknown\n",
3426 wvalue);
3427 }
3428 break;
3429
3430 case ClearPortFeature:
3431 if (wvalue != USB_PORT_FEAT_L1)
3432 if (!windex || windex > 1)
3433 goto error;
3434 switch (wvalue) {
3435 case USB_PORT_FEAT_ENABLE:
3436 dev_dbg(hsotg->dev,
3437 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
3438 hprt0 = dwc2_read_hprt0(hsotg);
3439 hprt0 |= HPRT0_ENA;
3440 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3441 break;
3442
3443 case USB_PORT_FEAT_SUSPEND:
3444 dev_dbg(hsotg->dev,
3445 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
3446
3447 if (hsotg->bus_suspended)
3448 dwc2_port_resume(hsotg);
3449 break;
3450
3451 case USB_PORT_FEAT_POWER:
3452 dev_dbg(hsotg->dev,
3453 "ClearPortFeature USB_PORT_FEAT_POWER\n");
3454 hprt0 = dwc2_read_hprt0(hsotg);
3455 hprt0 &= ~HPRT0_PWR;
3456 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3457 break;
3458
3459 case USB_PORT_FEAT_INDICATOR:
3460 dev_dbg(hsotg->dev,
3461 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
3462 /* Port indicator not supported */
3463 break;
3464
3465 case USB_PORT_FEAT_C_CONNECTION:
3466 /*
3467 * Clears driver's internal Connect Status Change flag
3468 */
3469 dev_dbg(hsotg->dev,
3470 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
3471 hsotg->flags.b.port_connect_status_change = 0;
3472 break;
3473
3474 case USB_PORT_FEAT_C_RESET:
3475 /* Clears driver's internal Port Reset Change flag */
3476 dev_dbg(hsotg->dev,
3477 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
3478 hsotg->flags.b.port_reset_change = 0;
3479 break;
3480
3481 case USB_PORT_FEAT_C_ENABLE:
3482 /*
3483 * Clears the driver's internal Port Enable/Disable
3484 * Change flag
3485 */
3486 dev_dbg(hsotg->dev,
3487 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
3488 hsotg->flags.b.port_enable_change = 0;
3489 break;
3490
3491 case USB_PORT_FEAT_C_SUSPEND:
3492 /*
3493 * Clears the driver's internal Port Suspend Change
3494 * flag, which is set when resume signaling on the host
3495 * port is complete
3496 */
3497 dev_dbg(hsotg->dev,
3498 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
3499 hsotg->flags.b.port_suspend_change = 0;
3500 break;
3501
3502 case USB_PORT_FEAT_C_PORT_L1:
3503 dev_dbg(hsotg->dev,
3504 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
3505 hsotg->flags.b.port_l1_change = 0;
3506 break;
3507
3508 case USB_PORT_FEAT_C_OVER_CURRENT:
3509 dev_dbg(hsotg->dev,
3510 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
3511 hsotg->flags.b.port_over_current_change = 0;
3512 break;
3513
3514 default:
3515 retval = -EINVAL;
3516 dev_err(hsotg->dev,
3517 "ClearPortFeature request %1xh unknown or unsupported\n",
3518 wvalue);
3519 }
3520 break;
3521
3522 case GetHubDescriptor:
3523 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
3524 hub_desc = (struct usb_hub_descriptor *)buf;
3525 hub_desc->bDescLength = 9;
3526 hub_desc->bDescriptorType = USB_DT_HUB;
3527 hub_desc->bNbrPorts = 1;
3528 hub_desc->wHubCharacteristics =
3529 cpu_to_le16(HUB_CHAR_COMMON_LPSM |
3530 HUB_CHAR_INDV_PORT_OCPM);
3531 hub_desc->bPwrOn2PwrGood = 1;
3532 hub_desc->bHubContrCurrent = 0;
3533 hub_desc->u.hs.DeviceRemovable[0] = 0;
3534 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
3535 break;
3536
3537 case GetHubStatus:
3538 dev_dbg(hsotg->dev, "GetHubStatus\n");
3539 memset(buf, 0, 4);
3540 break;
3541
3542 case GetPortStatus:
3543 dev_vdbg(hsotg->dev,
3544 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
3545 hsotg->flags.d32);
3546 if (!windex || windex > 1)
3547 goto error;
3548
3549 port_status = 0;
3550 if (hsotg->flags.b.port_connect_status_change)
3551 port_status |= USB_PORT_STAT_C_CONNECTION << 16;
3552 if (hsotg->flags.b.port_enable_change)
3553 port_status |= USB_PORT_STAT_C_ENABLE << 16;
3554 if (hsotg->flags.b.port_suspend_change)
3555 port_status |= USB_PORT_STAT_C_SUSPEND << 16;
3556 if (hsotg->flags.b.port_l1_change)
3557 port_status |= USB_PORT_STAT_C_L1 << 16;
3558 if (hsotg->flags.b.port_reset_change)
3559 port_status |= USB_PORT_STAT_C_RESET << 16;
3560 if (hsotg->flags.b.port_over_current_change) {
3561 dev_warn(hsotg->dev, "Overcurrent change detected\n");
3562 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
3563 }
3564
3565 if (!hsotg->flags.b.port_connect_status) {
3566 /*
3567 * The port is disconnected, which means the core is
3568 * either in device mode or it soon will be. Just
3569 * return 0's for the remainder of the port status
3570 * since the port register can't be read if the core
3571 * is in device mode.
3572 */
3573 *(__le32 *)buf = cpu_to_le32(port_status);
3574 break;
3575 }
3576
3577 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
3578 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
3579
3580 if (hprt0 & HPRT0_CONNSTS)
3581 port_status |= USB_PORT_STAT_CONNECTION;
3582 if (hprt0 & HPRT0_ENA)
3583 port_status |= USB_PORT_STAT_ENABLE;
3584 if (hprt0 & HPRT0_SUSP)
3585 port_status |= USB_PORT_STAT_SUSPEND;
3586 if (hprt0 & HPRT0_OVRCURRACT)
3587 port_status |= USB_PORT_STAT_OVERCURRENT;
3588 if (hprt0 & HPRT0_RST)
3589 port_status |= USB_PORT_STAT_RESET;
3590 if (hprt0 & HPRT0_PWR)
3591 port_status |= USB_PORT_STAT_POWER;
3592
3593 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
3594 if (speed == HPRT0_SPD_HIGH_SPEED)
3595 port_status |= USB_PORT_STAT_HIGH_SPEED;
3596 else if (speed == HPRT0_SPD_LOW_SPEED)
3597 port_status |= USB_PORT_STAT_LOW_SPEED;
3598
3599 if (hprt0 & HPRT0_TSTCTL_MASK)
3600 port_status |= USB_PORT_STAT_TEST;
3601 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
3602
3603 if (hsotg->params.dma_desc_fs_enable) {
3604 /*
3605 * Enable descriptor DMA only if a full speed
3606 * device is connected.
3607 */
3608 if (hsotg->new_connection &&
3609 ((port_status &
3610 (USB_PORT_STAT_CONNECTION |
3611 USB_PORT_STAT_HIGH_SPEED |
3612 USB_PORT_STAT_LOW_SPEED)) ==
3613 USB_PORT_STAT_CONNECTION)) {
3614 u32 hcfg;
3615
3616 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");
3617 hsotg->params.dma_desc_enable = 1;
3618 hcfg = dwc2_readl(hsotg->regs + HCFG);
3619 hcfg |= HCFG_DESCDMA;
3620 dwc2_writel(hcfg, hsotg->regs + HCFG);
3621 hsotg->new_connection = false;
3622 }
3623 }
3624
3625 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
3626 *(__le32 *)buf = cpu_to_le32(port_status);
3627 break;
3628
3629 case SetHubFeature:
3630 dev_dbg(hsotg->dev, "SetHubFeature\n");
3631 /* No HUB features supported */
3632 break;
3633
3634 case SetPortFeature:
3635 dev_dbg(hsotg->dev, "SetPortFeature\n");
3636 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
3637 goto error;
3638
3639 if (!hsotg->flags.b.port_connect_status) {
3640 /*
3641 * The port is disconnected, which means the core is
3642 * either in device mode or it soon will be. Just
3643 * return without doing anything since the port
3644 * register can't be written if the core is in device
3645 * mode.
3646 */
3647 break;
3648 }
3649
3650 switch (wvalue) {
3651 case USB_PORT_FEAT_SUSPEND:
3652 dev_dbg(hsotg->dev,
3653 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
3654 if (windex != hsotg->otg_port)
3655 goto error;
3656 dwc2_port_suspend(hsotg, windex);
3657 break;
3658
3659 case USB_PORT_FEAT_POWER:
3660 dev_dbg(hsotg->dev,
3661 "SetPortFeature - USB_PORT_FEAT_POWER\n");
3662 hprt0 = dwc2_read_hprt0(hsotg);
3663 hprt0 |= HPRT0_PWR;
3664 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3665 break;
3666
3667 case USB_PORT_FEAT_RESET:
3668 hprt0 = dwc2_read_hprt0(hsotg);
3669 dev_dbg(hsotg->dev,
3670 "SetPortFeature - USB_PORT_FEAT_RESET\n");
3671 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3672 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
3673 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3674 /* ??? Original driver does this */
3675 dwc2_writel(0, hsotg->regs + PCGCTL);
3676
3677 hprt0 = dwc2_read_hprt0(hsotg);
3678 /* Clear suspend bit if resetting from suspend state */
3679 hprt0 &= ~HPRT0_SUSP;
3680
3681 /*
3682 * When B-Host the Port reset bit is set in the Start
3683 * HCD Callback function, so that the reset is started
3684 * within 1ms of the HNP success interrupt
3685 */
3686 if (!dwc2_hcd_is_b_host(hsotg)) {
3687 hprt0 |= HPRT0_PWR | HPRT0_RST;
3688 dev_dbg(hsotg->dev,
3689 "In host mode, hprt0=%08x\n", hprt0);
3690 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3691 }
3692
3693 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
3694 usleep_range(50000, 70000);
3695 hprt0 &= ~HPRT0_RST;
3696 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3697 hsotg->lx_state = DWC2_L0; /* Now back to On state */
3698 break;
3699
3700 case USB_PORT_FEAT_INDICATOR:
3701 dev_dbg(hsotg->dev,
3702 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
3703 /* Not supported */
3704 break;
3705
3706 case USB_PORT_FEAT_TEST:
3707 hprt0 = dwc2_read_hprt0(hsotg);
3708 dev_dbg(hsotg->dev,
3709 "SetPortFeature - USB_PORT_FEAT_TEST\n");
3710 hprt0 &= ~HPRT0_TSTCTL_MASK;
3711 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
3712 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3713 break;
3714
3715 default:
3716 retval = -EINVAL;
3717 dev_err(hsotg->dev,
3718 "SetPortFeature %1xh unknown or unsupported\n",
3719 wvalue);
3720 break;
3721 }
3722 break;
3723
3724 default:
3725error:
3726 retval = -EINVAL;
3727 dev_dbg(hsotg->dev,
3728 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
3729 typereq, windex, wvalue);
3730 break;
3731 }
3732
3733 return retval;
3734}
3735
3736static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
3737{
3738 int retval;
3739
3740 if (port != 1)
3741 return -EINVAL;
3742
3743 retval = (hsotg->flags.b.port_connect_status_change ||
3744 hsotg->flags.b.port_reset_change ||
3745 hsotg->flags.b.port_enable_change ||
3746 hsotg->flags.b.port_suspend_change ||
3747 hsotg->flags.b.port_over_current_change);
3748
3749 if (retval) {
3750 dev_dbg(hsotg->dev,
3751 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
3752 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n",
3753 hsotg->flags.b.port_connect_status_change);
3754 dev_dbg(hsotg->dev, " port_reset_change: %d\n",
3755 hsotg->flags.b.port_reset_change);
3756 dev_dbg(hsotg->dev, " port_enable_change: %d\n",
3757 hsotg->flags.b.port_enable_change);
3758 dev_dbg(hsotg->dev, " port_suspend_change: %d\n",
3759 hsotg->flags.b.port_suspend_change);
3760 dev_dbg(hsotg->dev, " port_over_current_change: %d\n",
3761 hsotg->flags.b.port_over_current_change);
3762 }
3763
3764 return retval;
3765}
3766
3767int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
3768{
3769 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
3770
3771#ifdef DWC2_DEBUG_SOF
3772 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
3773 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
3774#endif
3775 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3776}
3777
3778int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us)
3779{
3780 u32 hprt = dwc2_readl(hsotg->regs + HPRT0);
3781 u32 hfir = dwc2_readl(hsotg->regs + HFIR);
3782 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
3783 unsigned int us_per_frame;
3784 unsigned int frame_number;
3785 unsigned int remaining;
3786 unsigned int interval;
3787 unsigned int phy_clks;
3788
3789 /* High speed has 125 us per (micro) frame; others are 1 ms per */
3790 us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125;
3791
3792 /* Extract fields */
3793 frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3794 remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT;
3795 interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT;
3796
3797 /*
3798 * Number of phy clocks since the last tick of the frame number after
3799 * "us" has passed.
3800 */
3801 phy_clks = (interval - remaining) +
3802 DIV_ROUND_UP(interval * us, us_per_frame);
3803
3804 return dwc2_frame_num_inc(frame_number, phy_clks / interval);
3805}
3806
3807int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
3808{
3809 return hsotg->op_state == OTG_STATE_B_HOST;
3810}
3811
3812static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
3813 int iso_desc_count,
3814 gfp_t mem_flags)
3815{
3816 struct dwc2_hcd_urb *urb;
3817 u32 size = sizeof(*urb) + iso_desc_count *
3818 sizeof(struct dwc2_hcd_iso_packet_desc);
3819
3820 urb = kzalloc(size, mem_flags);
3821 if (urb)
3822 urb->packet_count = iso_desc_count;
3823 return urb;
3824}
3825
3826static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
3827 struct dwc2_hcd_urb *urb, u8 dev_addr,
3828 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
3829{
3830 if (dbg_perio() ||
3831 ep_type == USB_ENDPOINT_XFER_BULK ||
3832 ep_type == USB_ENDPOINT_XFER_CONTROL)
3833 dev_vdbg(hsotg->dev,
3834 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
3835 dev_addr, ep_num, ep_dir, ep_type, mps);
3836 urb->pipe_info.dev_addr = dev_addr;
3837 urb->pipe_info.ep_num = ep_num;
3838 urb->pipe_info.pipe_type = ep_type;
3839 urb->pipe_info.pipe_dir = ep_dir;
3840 urb->pipe_info.mps = mps;
3841}
3842
3843/*
3844 * NOTE: This function will be removed once the peripheral controller code
3845 * is integrated and the driver is stable
3846 */
3847void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
3848{
3849#ifdef DEBUG
3850 struct dwc2_host_chan *chan;
3851 struct dwc2_hcd_urb *urb;
3852 struct dwc2_qtd *qtd;
3853 int num_channels;
3854 u32 np_tx_status;
3855 u32 p_tx_status;
3856 int i;
3857
3858 num_channels = hsotg->params.host_channels;
3859 dev_dbg(hsotg->dev, "\n");
3860 dev_dbg(hsotg->dev,
3861 "************************************************************\n");
3862 dev_dbg(hsotg->dev, "HCD State:\n");
3863 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels);
3864
3865 for (i = 0; i < num_channels; i++) {
3866 chan = hsotg->hc_ptr_array[i];
3867 dev_dbg(hsotg->dev, " Channel %d:\n", i);
3868 dev_dbg(hsotg->dev,
3869 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3870 chan->dev_addr, chan->ep_num, chan->ep_is_in);
3871 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed);
3872 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
3873 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
3874 dev_dbg(hsotg->dev, " data_pid_start: %d\n",
3875 chan->data_pid_start);
3876 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count);
3877 dev_dbg(hsotg->dev, " xfer_started: %d\n",
3878 chan->xfer_started);
3879 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
3880 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
3881 (unsigned long)chan->xfer_dma);
3882 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
3883 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count);
3884 dev_dbg(hsotg->dev, " halt_on_queue: %d\n",
3885 chan->halt_on_queue);
3886 dev_dbg(hsotg->dev, " halt_pending: %d\n",
3887 chan->halt_pending);
3888 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
3889 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split);
3890 dev_dbg(hsotg->dev, " complete_split: %d\n",
3891 chan->complete_split);
3892 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr);
3893 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port);
3894 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos);
3895 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests);
3896 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
3897
3898 if (chan->xfer_started) {
3899 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
3900
3901 hfnum = dwc2_readl(hsotg->regs + HFNUM);
3902 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
3903 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i));
3904 hcint = dwc2_readl(hsotg->regs + HCINT(i));
3905 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i));
3906 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
3907 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
3908 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
3909 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint);
3910 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk);
3911 }
3912
3913 if (!(chan->xfer_started && chan->qh))
3914 continue;
3915
3916 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
3917 if (!qtd->in_process)
3918 break;
3919 urb = qtd->urb;
3920 dev_dbg(hsotg->dev, " URB Info:\n");
3921 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n",
3922 qtd, urb);
3923 if (urb) {
3924 dev_dbg(hsotg->dev,
3925 " Dev: %d, EP: %d %s\n",
3926 dwc2_hcd_get_dev_addr(&urb->pipe_info),
3927 dwc2_hcd_get_ep_num(&urb->pipe_info),
3928 dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
3929 "IN" : "OUT");
3930 dev_dbg(hsotg->dev,
3931 " Max packet size: %d\n",
3932 dwc2_hcd_get_mps(&urb->pipe_info));
3933 dev_dbg(hsotg->dev,
3934 " transfer_buffer: %p\n",
3935 urb->buf);
3936 dev_dbg(hsotg->dev,
3937 " transfer_dma: %08lx\n",
3938 (unsigned long)urb->dma);
3939 dev_dbg(hsotg->dev,
3940 " transfer_buffer_length: %d\n",
3941 urb->length);
3942 dev_dbg(hsotg->dev, " actual_length: %d\n",
3943 urb->actual_length);
3944 }
3945 }
3946 }
3947
3948 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n",
3949 hsotg->non_periodic_channels);
3950 dev_dbg(hsotg->dev, " periodic_channels: %d\n",
3951 hsotg->periodic_channels);
3952 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
3953 np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3954 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
3955 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
3956 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
3957 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
3958 p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
3959 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
3960 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
3961 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
3962 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
3963 dwc2_hcd_dump_frrem(hsotg);
3964 dwc2_dump_global_registers(hsotg);
3965 dwc2_dump_host_registers(hsotg);
3966 dev_dbg(hsotg->dev,
3967 "************************************************************\n");
3968 dev_dbg(hsotg->dev, "\n");
3969#endif
3970}
3971
3972/*
3973 * NOTE: This function will be removed once the peripheral controller code
3974 * is integrated and the driver is stable
3975 */
3976void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg)
3977{
3978#ifdef DWC2_DUMP_FRREM
3979 dev_dbg(hsotg->dev, "Frame remaining at SOF:\n");
3980 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
3981 hsotg->frrem_samples, hsotg->frrem_accum,
3982 hsotg->frrem_samples > 0 ?
3983 hsotg->frrem_accum / hsotg->frrem_samples : 0);
3984 dev_dbg(hsotg->dev, "\n");
3985 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n");
3986 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
3987 hsotg->hfnum_7_samples,
3988 hsotg->hfnum_7_frrem_accum,
3989 hsotg->hfnum_7_samples > 0 ?
3990 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0);
3991 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n");
3992 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
3993 hsotg->hfnum_0_samples,
3994 hsotg->hfnum_0_frrem_accum,
3995 hsotg->hfnum_0_samples > 0 ?
3996 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0);
3997 dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n");
3998 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
3999 hsotg->hfnum_other_samples,
4000 hsotg->hfnum_other_frrem_accum,
4001 hsotg->hfnum_other_samples > 0 ?
4002 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples :
4003 0);
4004 dev_dbg(hsotg->dev, "\n");
4005 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n");
4006 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4007 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a,
4008 hsotg->hfnum_7_samples_a > 0 ?
4009 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0);
4010 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n");
4011 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4012 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a,
4013 hsotg->hfnum_0_samples_a > 0 ?
4014 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0);
4015 dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n");
4016 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4017 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a,
4018 hsotg->hfnum_other_samples_a > 0 ?
4019 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a
4020 : 0);
4021 dev_dbg(hsotg->dev, "\n");
4022 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n");
4023 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4024 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b,
4025 hsotg->hfnum_7_samples_b > 0 ?
4026 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0);
4027 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n");
4028 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4029 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b,
4030 (hsotg->hfnum_0_samples_b > 0) ?
4031 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0);
4032 dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n");
4033 dev_dbg(hsotg->dev, " samples %u, accum %llu, avg %llu\n",
4034 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b,
4035 (hsotg->hfnum_other_samples_b > 0) ?
4036 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b
4037 : 0);
4038#endif
4039}
4040
4041struct wrapper_priv_data {
4042 struct dwc2_hsotg *hsotg;
4043};
4044
4045/* Gets the dwc2_hsotg from a usb_hcd */
4046static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
4047{
4048 struct wrapper_priv_data *p;
4049
4050 p = (struct wrapper_priv_data *) &hcd->hcd_priv;
4051 return p->hsotg;
4052}
4053
4054/**
4055 * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context
4056 *
4057 * This will get the dwc2_tt structure (and ttport) associated with the given
4058 * context (which is really just a struct urb pointer).
4059 *
4060 * The first time this is called for a given TT we allocate memory for our
4061 * structure. When everyone is done and has called dwc2_host_put_tt_info()
4062 * then the refcount for the structure will go to 0 and we'll free it.
4063 *
4064 * @hsotg: The HCD state structure for the DWC OTG controller.
4065 * @qh: The QH structure.
4066 * @context: The priv pointer from a struct dwc2_hcd_urb.
4067 * @mem_flags: Flags for allocating memory.
4068 * @ttport: We'll return this device's port number here. That's used to
4069 * reference into the bitmap if we're on a multi_tt hub.
4070 *
4071 * Return: a pointer to a struct dwc2_tt. Don't forget to call
4072 * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure.
4073 */
4074
4075struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context,
4076 gfp_t mem_flags, int *ttport)
4077{
4078 struct urb *urb = context;
4079 struct dwc2_tt *dwc_tt = NULL;
4080
4081 if (urb->dev->tt) {
4082 *ttport = urb->dev->ttport;
4083
4084 dwc_tt = urb->dev->tt->hcpriv;
4085 if (dwc_tt == NULL) {
4086 size_t bitmap_size;
4087
4088 /*
4089 * For single_tt we need one schedule. For multi_tt
4090 * we need one per port.
4091 */
4092 bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP *
4093 sizeof(dwc_tt->periodic_bitmaps[0]);
4094 if (urb->dev->tt->multi)
4095 bitmap_size *= urb->dev->tt->hub->maxchild;
4096
4097 dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size,
4098 mem_flags);
4099 if (dwc_tt == NULL)
4100 return NULL;
4101
4102 dwc_tt->usb_tt = urb->dev->tt;
4103 dwc_tt->usb_tt->hcpriv = dwc_tt;
4104 }
4105
4106 dwc_tt->refcount++;
4107 }
4108
4109 return dwc_tt;
4110}
4111
4112/**
4113 * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info()
4114 *
4115 * Frees resources allocated by dwc2_host_get_tt_info() if all current holders
4116 * of the structure are done.
4117 *
4118 * It's OK to call this with NULL.
4119 *
4120 * @hsotg: The HCD state structure for the DWC OTG controller.
4121 * @dwc_tt: The pointer returned by dwc2_host_get_tt_info.
4122 */
4123void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt)
4124{
4125 /* Model kfree and make put of NULL a no-op */
4126 if (dwc_tt == NULL)
4127 return;
4128
4129 WARN_ON(dwc_tt->refcount < 1);
4130
4131 dwc_tt->refcount--;
4132 if (!dwc_tt->refcount) {
4133 dwc_tt->usb_tt->hcpriv = NULL;
4134 kfree(dwc_tt);
4135 }
4136}
4137
4138int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
4139{
4140 struct urb *urb = context;
4141
4142 return urb->dev->speed;
4143}
4144
4145static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4146 struct urb *urb)
4147{
4148 struct usb_bus *bus = hcd_to_bus(hcd);
4149
4150 if (urb->interval)
4151 bus->bandwidth_allocated += bw / urb->interval;
4152 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4153 bus->bandwidth_isoc_reqs++;
4154 else
4155 bus->bandwidth_int_reqs++;
4156}
4157
4158static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4159 struct urb *urb)
4160{
4161 struct usb_bus *bus = hcd_to_bus(hcd);
4162
4163 if (urb->interval)
4164 bus->bandwidth_allocated -= bw / urb->interval;
4165 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4166 bus->bandwidth_isoc_reqs--;
4167 else
4168 bus->bandwidth_int_reqs--;
4169}
4170
4171/*
4172 * Sets the final status of an URB and returns it to the upper layer. Any
4173 * required cleanup of the URB is performed.
4174 *
4175 * Must be called with interrupt disabled and spinlock held
4176 */
4177void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
4178 int status)
4179{
4180 struct urb *urb;
4181 int i;
4182
4183 if (!qtd) {
4184 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
4185 return;
4186 }
4187
4188 if (!qtd->urb) {
4189 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
4190 return;
4191 }
4192
4193 urb = qtd->urb->priv;
4194 if (!urb) {
4195 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
4196 return;
4197 }
4198
4199 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
4200
4201 if (dbg_urb(urb))
4202 dev_vdbg(hsotg->dev,
4203 "%s: urb %p device %d ep %d-%s status %d actual %d\n",
4204 __func__, urb, usb_pipedevice(urb->pipe),
4205 usb_pipeendpoint(urb->pipe),
4206 usb_pipein(urb->pipe) ? "IN" : "OUT", status,
4207 urb->actual_length);
4208
4209
4210 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4211 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
4212 for (i = 0; i < urb->number_of_packets; ++i) {
4213 urb->iso_frame_desc[i].actual_length =
4214 dwc2_hcd_urb_get_iso_desc_actual_length(
4215 qtd->urb, i);
4216 urb->iso_frame_desc[i].status =
4217 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
4218 }
4219 }
4220
4221 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
4222 for (i = 0; i < urb->number_of_packets; i++)
4223 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
4224 i, urb->iso_frame_desc[i].status);
4225 }
4226
4227 urb->status = status;
4228 if (!status) {
4229 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
4230 urb->actual_length < urb->transfer_buffer_length)
4231 urb->status = -EREMOTEIO;
4232 }
4233
4234 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4235 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4236 struct usb_host_endpoint *ep = urb->ep;
4237
4238 if (ep)
4239 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
4240 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4241 urb);
4242 }
4243
4244 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
4245 urb->hcpriv = NULL;
4246 kfree(qtd->urb);
4247 qtd->urb = NULL;
4248
4249 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
4250}
4251
4252/*
4253 * Work queue function for starting the HCD when A-Cable is connected
4254 */
4255static void dwc2_hcd_start_func(struct work_struct *work)
4256{
4257 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4258 start_work.work);
4259
4260 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
4261 dwc2_host_start(hsotg);
4262}
4263
4264/*
4265 * Reset work queue function
4266 */
4267static void dwc2_hcd_reset_func(struct work_struct *work)
4268{
4269 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4270 reset_work.work);
4271 unsigned long flags;
4272 u32 hprt0;
4273
4274 dev_dbg(hsotg->dev, "USB RESET function called\n");
4275
4276 spin_lock_irqsave(&hsotg->lock, flags);
4277
4278 hprt0 = dwc2_read_hprt0(hsotg);
4279 hprt0 &= ~HPRT0_RST;
4280 dwc2_writel(hprt0, hsotg->regs + HPRT0);
4281 hsotg->flags.b.port_reset_change = 1;
4282
4283 spin_unlock_irqrestore(&hsotg->lock, flags);
4284}
4285
4286/*
4287 * =========================================================================
4288 * Linux HC Driver Functions
4289 * =========================================================================
4290 */
4291
4292/*
4293 * Initializes the DWC_otg controller and its root hub and prepares it for host
4294 * mode operation. Activates the root port. Returns 0 on success and a negative
4295 * error code on failure.
4296 */
4297static int _dwc2_hcd_start(struct usb_hcd *hcd)
4298{
4299 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4300 struct usb_bus *bus = hcd_to_bus(hcd);
4301 unsigned long flags;
4302
4303 dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
4304
4305 spin_lock_irqsave(&hsotg->lock, flags);
4306 hsotg->lx_state = DWC2_L0;
4307 hcd->state = HC_STATE_RUNNING;
4308 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4309
4310 if (dwc2_is_device_mode(hsotg)) {
4311 spin_unlock_irqrestore(&hsotg->lock, flags);
4312 return 0; /* why 0 ?? */
4313 }
4314
4315 dwc2_hcd_reinit(hsotg);
4316
4317 /* Initialize and connect root hub if one is not already attached */
4318 if (bus->root_hub) {
4319 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
4320 /* Inform the HUB driver to resume */
4321 usb_hcd_resume_root_hub(hcd);
4322 }
4323
4324 spin_unlock_irqrestore(&hsotg->lock, flags);
4325 return 0;
4326}
4327
4328/*
4329 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
4330 * stopped.
4331 */
4332static void _dwc2_hcd_stop(struct usb_hcd *hcd)
4333{
4334 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4335 unsigned long flags;
4336
4337 /* Turn off all host-specific interrupts */
4338 dwc2_disable_host_interrupts(hsotg);
4339
4340 /* Wait for interrupt processing to finish */
4341 synchronize_irq(hcd->irq);
4342
4343 spin_lock_irqsave(&hsotg->lock, flags);
4344 /* Ensure hcd is disconnected */
4345 dwc2_hcd_disconnect(hsotg, true);
4346 dwc2_hcd_stop(hsotg);
4347 hsotg->lx_state = DWC2_L3;
4348 hcd->state = HC_STATE_HALT;
4349 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4350 spin_unlock_irqrestore(&hsotg->lock, flags);
4351
4352 usleep_range(1000, 3000);
4353}
4354
4355static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
4356{
4357 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4358 unsigned long flags;
4359 int ret = 0;
4360 u32 hprt0;
4361
4362 spin_lock_irqsave(&hsotg->lock, flags);
4363
4364 if (hsotg->lx_state != DWC2_L0)
4365 goto unlock;
4366
4367 if (!HCD_HW_ACCESSIBLE(hcd))
4368 goto unlock;
4369
4370 if (hsotg->op_state == OTG_STATE_B_PERIPHERAL)
4371 goto unlock;
4372
4373 if (!hsotg->params.hibernation)
4374 goto skip_power_saving;
4375
4376 /*
4377 * Drive USB suspend and disable port Power
4378 * if usb bus is not suspended.
4379 */
4380 if (!hsotg->bus_suspended) {
4381 hprt0 = dwc2_read_hprt0(hsotg);
4382 hprt0 |= HPRT0_SUSP;
4383 hprt0 &= ~HPRT0_PWR;
4384 dwc2_writel(hprt0, hsotg->regs + HPRT0);
4385 }
4386
4387 /* Enter hibernation */
4388 ret = dwc2_enter_hibernation(hsotg);
4389 if (ret) {
4390 if (ret != -ENOTSUPP)
4391 dev_err(hsotg->dev,
4392 "enter hibernation failed\n");
4393 goto skip_power_saving;
4394 }
4395
4396 /* Ask phy to be suspended */
4397 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4398 spin_unlock_irqrestore(&hsotg->lock, flags);
4399 usb_phy_set_suspend(hsotg->uphy, true);
4400 spin_lock_irqsave(&hsotg->lock, flags);
4401 }
4402
4403 /* After entering hibernation, hardware is no more accessible */
4404 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4405
4406skip_power_saving:
4407 hsotg->lx_state = DWC2_L2;
4408unlock:
4409 spin_unlock_irqrestore(&hsotg->lock, flags);
4410
4411 return ret;
4412}
4413
4414static int _dwc2_hcd_resume(struct usb_hcd *hcd)
4415{
4416 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4417 unsigned long flags;
4418 int ret = 0;
4419
4420 spin_lock_irqsave(&hsotg->lock, flags);
4421
4422 if (hsotg->lx_state != DWC2_L2)
4423 goto unlock;
4424
4425 if (!hsotg->params.hibernation) {
4426 hsotg->lx_state = DWC2_L0;
4427 goto unlock;
4428 }
4429
4430 /*
4431 * Set HW accessible bit before powering on the controller
4432 * since an interrupt may rise.
4433 */
4434 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4435
4436 /*
4437 * Enable power if not already done.
4438 * This must not be spinlocked since duration
4439 * of this call is unknown.
4440 */
4441 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4442 spin_unlock_irqrestore(&hsotg->lock, flags);
4443 usb_phy_set_suspend(hsotg->uphy, false);
4444 spin_lock_irqsave(&hsotg->lock, flags);
4445 }
4446
4447 /* Exit hibernation */
4448 ret = dwc2_exit_hibernation(hsotg, true);
4449 if (ret && (ret != -ENOTSUPP))
4450 dev_err(hsotg->dev, "exit hibernation failed\n");
4451
4452 hsotg->lx_state = DWC2_L0;
4453
4454 spin_unlock_irqrestore(&hsotg->lock, flags);
4455
4456 if (hsotg->bus_suspended) {
4457 spin_lock_irqsave(&hsotg->lock, flags);
4458 hsotg->flags.b.port_suspend_change = 1;
4459 spin_unlock_irqrestore(&hsotg->lock, flags);
4460 dwc2_port_resume(hsotg);
4461 } else {
4462 /* Wait for controller to correctly update D+/D- level */
4463 usleep_range(3000, 5000);
4464
4465 /*
4466 * Clear Port Enable and Port Status changes.
4467 * Enable Port Power.
4468 */
4469 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET |
4470 HPRT0_ENACHG, hsotg->regs + HPRT0);
4471 /* Wait for controller to detect Port Connect */
4472 usleep_range(5000, 7000);
4473 }
4474
4475 return ret;
4476unlock:
4477 spin_unlock_irqrestore(&hsotg->lock, flags);
4478
4479 return ret;
4480}
4481
4482/* Returns the current frame number */
4483static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
4484{
4485 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4486
4487 return dwc2_hcd_get_frame_number(hsotg);
4488}
4489
4490static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
4491 char *fn_name)
4492{
4493#ifdef VERBOSE_DEBUG
4494 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4495 char *pipetype = NULL;
4496 char *speed = NULL;
4497
4498 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
4499 dev_vdbg(hsotg->dev, " Device address: %d\n",
4500 usb_pipedevice(urb->pipe));
4501 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n",
4502 usb_pipeendpoint(urb->pipe),
4503 usb_pipein(urb->pipe) ? "IN" : "OUT");
4504
4505 switch (usb_pipetype(urb->pipe)) {
4506 case PIPE_CONTROL:
4507 pipetype = "CONTROL";
4508 break;
4509 case PIPE_BULK:
4510 pipetype = "BULK";
4511 break;
4512 case PIPE_INTERRUPT:
4513 pipetype = "INTERRUPT";
4514 break;
4515 case PIPE_ISOCHRONOUS:
4516 pipetype = "ISOCHRONOUS";
4517 break;
4518 }
4519
4520 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype,
4521 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
4522 "IN" : "OUT");
4523
4524 switch (urb->dev->speed) {
4525 case USB_SPEED_HIGH:
4526 speed = "HIGH";
4527 break;
4528 case USB_SPEED_FULL:
4529 speed = "FULL";
4530 break;
4531 case USB_SPEED_LOW:
4532 speed = "LOW";
4533 break;
4534 default:
4535 speed = "UNKNOWN";
4536 break;
4537 }
4538
4539 dev_vdbg(hsotg->dev, " Speed: %s\n", speed);
4540 dev_vdbg(hsotg->dev, " Max packet size: %d\n",
4541 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
4542 dev_vdbg(hsotg->dev, " Data buffer length: %d\n",
4543 urb->transfer_buffer_length);
4544 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
4545 urb->transfer_buffer, (unsigned long)urb->transfer_dma);
4546 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
4547 urb->setup_packet, (unsigned long)urb->setup_dma);
4548 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval);
4549
4550 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4551 int i;
4552
4553 for (i = 0; i < urb->number_of_packets; i++) {
4554 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i);
4555 dev_vdbg(hsotg->dev, " offset: %d, length %d\n",
4556 urb->iso_frame_desc[i].offset,
4557 urb->iso_frame_desc[i].length);
4558 }
4559 }
4560#endif
4561}
4562
4563/*
4564 * Starts processing a USB transfer request specified by a USB Request Block
4565 * (URB). mem_flags indicates the type of memory allocation to use while
4566 * processing this URB.
4567 */
4568static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
4569 gfp_t mem_flags)
4570{
4571 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4572 struct usb_host_endpoint *ep = urb->ep;
4573 struct dwc2_hcd_urb *dwc2_urb;
4574 int i;
4575 int retval;
4576 int alloc_bandwidth = 0;
4577 u8 ep_type = 0;
4578 u32 tflags = 0;
4579 void *buf;
4580 unsigned long flags;
4581 struct dwc2_qh *qh;
4582 bool qh_allocated = false;
4583 struct dwc2_qtd *qtd;
4584
4585 if (dbg_urb(urb)) {
4586 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
4587 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
4588 }
4589
4590 if (ep == NULL)
4591 return -EINVAL;
4592
4593 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4594 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4595 spin_lock_irqsave(&hsotg->lock, flags);
4596 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
4597 alloc_bandwidth = 1;
4598 spin_unlock_irqrestore(&hsotg->lock, flags);
4599 }
4600
4601 switch (usb_pipetype(urb->pipe)) {
4602 case PIPE_CONTROL:
4603 ep_type = USB_ENDPOINT_XFER_CONTROL;
4604 break;
4605 case PIPE_ISOCHRONOUS:
4606 ep_type = USB_ENDPOINT_XFER_ISOC;
4607 break;
4608 case PIPE_BULK:
4609 ep_type = USB_ENDPOINT_XFER_BULK;
4610 break;
4611 case PIPE_INTERRUPT:
4612 ep_type = USB_ENDPOINT_XFER_INT;
4613 break;
4614 }
4615
4616 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
4617 mem_flags);
4618 if (!dwc2_urb)
4619 return -ENOMEM;
4620
4621 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
4622 usb_pipeendpoint(urb->pipe), ep_type,
4623 usb_pipein(urb->pipe),
4624 usb_maxpacket(urb->dev, urb->pipe,
4625 !(usb_pipein(urb->pipe))));
4626
4627 buf = urb->transfer_buffer;
4628
4629 if (hcd->self.uses_dma) {
4630 if (!buf && (urb->transfer_dma & 3)) {
4631 dev_err(hsotg->dev,
4632 "%s: unaligned transfer with no transfer_buffer",
4633 __func__);
4634 retval = -EINVAL;
4635 goto fail0;
4636 }
4637 }
4638
4639 if (!(urb->transfer_flags & URB_NO_INTERRUPT))
4640 tflags |= URB_GIVEBACK_ASAP;
4641 if (urb->transfer_flags & URB_ZERO_PACKET)
4642 tflags |= URB_SEND_ZERO_PACKET;
4643
4644 dwc2_urb->priv = urb;
4645 dwc2_urb->buf = buf;
4646 dwc2_urb->dma = urb->transfer_dma;
4647 dwc2_urb->length = urb->transfer_buffer_length;
4648 dwc2_urb->setup_packet = urb->setup_packet;
4649 dwc2_urb->setup_dma = urb->setup_dma;
4650 dwc2_urb->flags = tflags;
4651 dwc2_urb->interval = urb->interval;
4652 dwc2_urb->status = -EINPROGRESS;
4653
4654 for (i = 0; i < urb->number_of_packets; ++i)
4655 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
4656 urb->iso_frame_desc[i].offset,
4657 urb->iso_frame_desc[i].length);
4658
4659 urb->hcpriv = dwc2_urb;
4660 qh = (struct dwc2_qh *) ep->hcpriv;
4661 /* Create QH for the endpoint if it doesn't exist */
4662 if (!qh) {
4663 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
4664 if (!qh) {
4665 retval = -ENOMEM;
4666 goto fail0;
4667 }
4668 ep->hcpriv = qh;
4669 qh_allocated = true;
4670 }
4671
4672 qtd = kzalloc(sizeof(*qtd), mem_flags);
4673 if (!qtd) {
4674 retval = -ENOMEM;
4675 goto fail1;
4676 }
4677
4678 spin_lock_irqsave(&hsotg->lock, flags);
4679 retval = usb_hcd_link_urb_to_ep(hcd, urb);
4680 if (retval)
4681 goto fail2;
4682
4683 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
4684 if (retval)
4685 goto fail3;
4686
4687 if (alloc_bandwidth) {
4688 dwc2_allocate_bus_bandwidth(hcd,
4689 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4690 urb);
4691 }
4692
4693 spin_unlock_irqrestore(&hsotg->lock, flags);
4694
4695 return 0;
4696
4697fail3:
4698 dwc2_urb->priv = NULL;
4699 usb_hcd_unlink_urb_from_ep(hcd, urb);
4700 if (qh_allocated && qh->channel && qh->channel->qh == qh)
4701 qh->channel->qh = NULL;
4702fail2:
4703 spin_unlock_irqrestore(&hsotg->lock, flags);
4704 urb->hcpriv = NULL;
4705 kfree(qtd);
4706 qtd = NULL;
4707fail1:
4708 if (qh_allocated) {
4709 struct dwc2_qtd *qtd2, *qtd2_tmp;
4710
4711 ep->hcpriv = NULL;
4712 dwc2_hcd_qh_unlink(hsotg, qh);
4713 /* Free each QTD in the QH's QTD list */
4714 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list,
4715 qtd_list_entry)
4716 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
4717 dwc2_hcd_qh_free(hsotg, qh);
4718 }
4719fail0:
4720 kfree(dwc2_urb);
4721
4722 return retval;
4723}
4724
4725/*
4726 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
4727 */
4728static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
4729 int status)
4730{
4731 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4732 int rc;
4733 unsigned long flags;
4734
4735 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
4736 dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
4737
4738 spin_lock_irqsave(&hsotg->lock, flags);
4739
4740 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
4741 if (rc)
4742 goto out;
4743
4744 if (!urb->hcpriv) {
4745 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
4746 goto out;
4747 }
4748
4749 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
4750
4751 usb_hcd_unlink_urb_from_ep(hcd, urb);
4752
4753 kfree(urb->hcpriv);
4754 urb->hcpriv = NULL;
4755
4756 /* Higher layer software sets URB status */
4757 spin_unlock(&hsotg->lock);
4758 usb_hcd_giveback_urb(hcd, urb, status);
4759 spin_lock(&hsotg->lock);
4760
4761 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
4762 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status);
4763out:
4764 spin_unlock_irqrestore(&hsotg->lock, flags);
4765
4766 return rc;
4767}
4768
4769/*
4770 * Frees resources in the DWC_otg controller related to a given endpoint. Also
4771 * clears state in the HCD related to the endpoint. Any URBs for the endpoint
4772 * must already be dequeued.
4773 */
4774static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
4775 struct usb_host_endpoint *ep)
4776{
4777 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4778
4779 dev_dbg(hsotg->dev,
4780 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
4781 ep->desc.bEndpointAddress, ep->hcpriv);
4782 dwc2_hcd_endpoint_disable(hsotg, ep, 250);
4783}
4784
4785/*
4786 * Resets endpoint specific parameter values, in current version used to reset
4787 * the data toggle (as a WA). This function can be called from usb_clear_halt
4788 * routine.
4789 */
4790static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
4791 struct usb_host_endpoint *ep)
4792{
4793 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4794 unsigned long flags;
4795
4796 dev_dbg(hsotg->dev,
4797 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
4798 ep->desc.bEndpointAddress);
4799
4800 spin_lock_irqsave(&hsotg->lock, flags);
4801 dwc2_hcd_endpoint_reset(hsotg, ep);
4802 spin_unlock_irqrestore(&hsotg->lock, flags);
4803}
4804
4805/*
4806 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
4807 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
4808 * interrupt.
4809 *
4810 * This function is called by the USB core when an interrupt occurs
4811 */
4812static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
4813{
4814 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4815
4816 return dwc2_handle_hcd_intr(hsotg);
4817}
4818
4819/*
4820 * Creates Status Change bitmap for the root hub and root port. The bitmap is
4821 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
4822 * is the status change indicator for the single root port. Returns 1 if either
4823 * change indicator is 1, otherwise returns 0.
4824 */
4825static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
4826{
4827 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4828
4829 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
4830 return buf[0] != 0;
4831}
4832
4833/* Handles hub class-specific requests */
4834static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
4835 u16 windex, char *buf, u16 wlength)
4836{
4837 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
4838 wvalue, windex, buf, wlength);
4839 return retval;
4840}
4841
4842/* Handles hub TT buffer clear completions */
4843static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
4844 struct usb_host_endpoint *ep)
4845{
4846 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4847 struct dwc2_qh *qh;
4848 unsigned long flags;
4849
4850 qh = ep->hcpriv;
4851 if (!qh)
4852 return;
4853
4854 spin_lock_irqsave(&hsotg->lock, flags);
4855 qh->tt_buffer_dirty = 0;
4856
4857 if (hsotg->flags.b.port_connect_status)
4858 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
4859
4860 spin_unlock_irqrestore(&hsotg->lock, flags);
4861}
4862
4863static struct hc_driver dwc2_hc_driver = {
4864 .description = "dwc2_hsotg",
4865 .product_desc = "DWC OTG Controller",
4866 .hcd_priv_size = sizeof(struct wrapper_priv_data),
4867
4868 .irq = _dwc2_hcd_irq,
4869 .flags = HCD_MEMORY | HCD_USB2 | HCD_BH,
4870
4871 .start = _dwc2_hcd_start,
4872 .stop = _dwc2_hcd_stop,
4873 .urb_enqueue = _dwc2_hcd_urb_enqueue,
4874 .urb_dequeue = _dwc2_hcd_urb_dequeue,
4875 .endpoint_disable = _dwc2_hcd_endpoint_disable,
4876 .endpoint_reset = _dwc2_hcd_endpoint_reset,
4877 .get_frame_number = _dwc2_hcd_get_frame_number,
4878
4879 .hub_status_data = _dwc2_hcd_hub_status_data,
4880 .hub_control = _dwc2_hcd_hub_control,
4881 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
4882
4883 .bus_suspend = _dwc2_hcd_suspend,
4884 .bus_resume = _dwc2_hcd_resume,
4885
4886 .map_urb_for_dma = dwc2_map_urb_for_dma,
4887 .unmap_urb_for_dma = dwc2_unmap_urb_for_dma,
4888};
4889
4890/*
4891 * Frees secondary storage associated with the dwc2_hsotg structure contained
4892 * in the struct usb_hcd field
4893 */
4894static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
4895{
4896 u32 ahbcfg;
4897 u32 dctl;
4898 int i;
4899
4900 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
4901
4902 /* Free memory for QH/QTD lists */
4903 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
4904 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
4905 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
4906 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
4907 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
4908 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
4909
4910 /* Free memory for the host channels */
4911 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
4912 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
4913
4914 if (chan != NULL) {
4915 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
4916 i, chan);
4917 hsotg->hc_ptr_array[i] = NULL;
4918 kfree(chan);
4919 }
4920 }
4921
4922 if (hsotg->params.host_dma > 0) {
4923 if (hsotg->status_buf) {
4924 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
4925 hsotg->status_buf,
4926 hsotg->status_buf_dma);
4927 hsotg->status_buf = NULL;
4928 }
4929 } else {
4930 kfree(hsotg->status_buf);
4931 hsotg->status_buf = NULL;
4932 }
4933
4934 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
4935
4936 /* Disable all interrupts */
4937 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
4938 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
4939 dwc2_writel(0, hsotg->regs + GINTMSK);
4940
4941 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
4942 dctl = dwc2_readl(hsotg->regs + DCTL);
4943 dctl |= DCTL_SFTDISCON;
4944 dwc2_writel(dctl, hsotg->regs + DCTL);
4945 }
4946
4947 if (hsotg->wq_otg) {
4948 if (!cancel_work_sync(&hsotg->wf_otg))
4949 flush_workqueue(hsotg->wq_otg);
4950 destroy_workqueue(hsotg->wq_otg);
4951 }
4952
4953 del_timer(&hsotg->wkp_timer);
4954}
4955
4956static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
4957{
4958 /* Turn off all host-specific interrupts */
4959 dwc2_disable_host_interrupts(hsotg);
4960
4961 dwc2_hcd_free(hsotg);
4962}
4963
4964/*
4965 * Initializes the HCD. This function allocates memory for and initializes the
4966 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
4967 * USB bus with the core and calls the hc_driver->start() function. It returns
4968 * a negative error on failure.
4969 */
4970int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
4971{
4972 struct usb_hcd *hcd;
4973 struct dwc2_host_chan *channel;
4974 u32 hcfg;
4975 int i, num_channels;
4976 int retval;
4977
4978 if (usb_disabled())
4979 return -ENODEV;
4980
4981 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
4982
4983 retval = -ENOMEM;
4984
4985 hcfg = dwc2_readl(hsotg->regs + HCFG);
4986 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
4987
4988#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
4989 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) *
4990 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
4991 if (!hsotg->frame_num_array)
4992 goto error1;
4993 hsotg->last_frame_num_array = kzalloc(
4994 sizeof(*hsotg->last_frame_num_array) *
4995 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
4996 if (!hsotg->last_frame_num_array)
4997 goto error1;
4998#endif
4999 hsotg->last_frame_num = HFNUM_MAX_FRNUM;
5000
5001 /* Check if the bus driver or platform code has setup a dma_mask */
5002 if (hsotg->params.host_dma > 0 &&
5003 hsotg->dev->dma_mask == NULL) {
5004 dev_warn(hsotg->dev,
5005 "dma_mask not set, disabling DMA\n");
5006 hsotg->params.host_dma = 0;
5007 hsotg->params.dma_desc_enable = 0;
5008 }
5009
5010 /* Set device flags indicating whether the HCD supports DMA */
5011 if (hsotg->params.host_dma > 0) {
5012 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5013 dev_warn(hsotg->dev, "can't set DMA mask\n");
5014 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5015 dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
5016 }
5017
5018 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
5019 if (!hcd)
5020 goto error1;
5021
5022 if (hsotg->params.host_dma <= 0)
5023 hcd->self.uses_dma = 0;
5024
5025 hcd->has_tt = 1;
5026
5027 ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg;
5028 hsotg->priv = hcd;
5029
5030 /*
5031 * Disable the global interrupt until all the interrupt handlers are
5032 * installed
5033 */
5034 dwc2_disable_global_interrupts(hsotg);
5035
5036 /* Initialize the DWC_otg core, and select the Phy type */
5037 retval = dwc2_core_init(hsotg, true);
5038 if (retval)
5039 goto error2;
5040
5041 /* Create new workqueue and init work */
5042 retval = -ENOMEM;
5043 hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0);
5044 if (!hsotg->wq_otg) {
5045 dev_err(hsotg->dev, "Failed to create workqueue\n");
5046 goto error2;
5047 }
5048 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
5049
5050 setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected,
5051 (unsigned long)hsotg);
5052
5053 /* Initialize the non-periodic schedule */
5054 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
5055 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
5056
5057 /* Initialize the periodic schedule */
5058 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
5059 INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
5060 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
5061 INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
5062
5063 INIT_LIST_HEAD(&hsotg->split_order);
5064
5065 /*
5066 * Create a host channel descriptor for each host channel implemented
5067 * in the controller. Initialize the channel descriptor array.
5068 */
5069 INIT_LIST_HEAD(&hsotg->free_hc_list);
5070 num_channels = hsotg->params.host_channels;
5071 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
5072
5073 for (i = 0; i < num_channels; i++) {
5074 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
5075 if (channel == NULL)
5076 goto error3;
5077 channel->hc_num = i;
5078 INIT_LIST_HEAD(&channel->split_order_list_entry);
5079 hsotg->hc_ptr_array[i] = channel;
5080 }
5081
5082 /* Initialize hsotg start work */
5083 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
5084
5085 /* Initialize port reset work */
5086 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
5087
5088 /*
5089 * Allocate space for storing data on status transactions. Normally no
5090 * data is sent, but this space acts as a bit bucket. This must be
5091 * done after usb_add_hcd since that function allocates the DMA buffer
5092 * pool.
5093 */
5094 if (hsotg->params.host_dma > 0)
5095 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
5096 DWC2_HCD_STATUS_BUF_SIZE,
5097 &hsotg->status_buf_dma, GFP_KERNEL);
5098 else
5099 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
5100 GFP_KERNEL);
5101
5102 if (!hsotg->status_buf)
5103 goto error3;
5104
5105 /*
5106 * Create kmem caches to handle descriptor buffers in descriptor
5107 * DMA mode.
5108 * Alignment must be set to 512 bytes.
5109 */
5110 if (hsotg->params.dma_desc_enable ||
5111 hsotg->params.dma_desc_fs_enable) {
5112 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc",
5113 sizeof(struct dwc2_dma_desc) *
5114 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA,
5115 NULL);
5116 if (!hsotg->desc_gen_cache) {
5117 dev_err(hsotg->dev,
5118 "unable to create dwc2 generic desc cache\n");
5119
5120 /*
5121 * Disable descriptor dma mode since it will not be
5122 * usable.
5123 */
5124 hsotg->params.dma_desc_enable = 0;
5125 hsotg->params.dma_desc_fs_enable = 0;
5126 }
5127
5128 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc",
5129 sizeof(struct dwc2_dma_desc) *
5130 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL);
5131 if (!hsotg->desc_hsisoc_cache) {
5132 dev_err(hsotg->dev,
5133 "unable to create dwc2 hs isoc desc cache\n");
5134
5135 kmem_cache_destroy(hsotg->desc_gen_cache);
5136
5137 /*
5138 * Disable descriptor dma mode since it will not be
5139 * usable.
5140 */
5141 hsotg->params.dma_desc_enable = 0;
5142 hsotg->params.dma_desc_fs_enable = 0;
5143 }
5144 }
5145
5146 hsotg->otg_port = 1;
5147 hsotg->frame_list = NULL;
5148 hsotg->frame_list_dma = 0;
5149 hsotg->periodic_qh_count = 0;
5150
5151 /* Initiate lx_state to L3 disconnected state */
5152 hsotg->lx_state = DWC2_L3;
5153
5154 hcd->self.otg_port = hsotg->otg_port;
5155
5156 /* Don't support SG list at this point */
5157 hcd->self.sg_tablesize = 0;
5158
5159 if (!IS_ERR_OR_NULL(hsotg->uphy))
5160 otg_set_host(hsotg->uphy->otg, &hcd->self);
5161
5162 /*
5163 * Finish generic HCD initialization and start the HCD. This function
5164 * allocates the DMA buffer pool, registers the USB bus, requests the
5165 * IRQ line, and calls hcd_start method.
5166 */
5167 retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
5168 if (retval < 0)
5169 goto error4;
5170
5171 device_wakeup_enable(hcd->self.controller);
5172
5173 dwc2_hcd_dump_state(hsotg);
5174
5175 dwc2_enable_global_interrupts(hsotg);
5176
5177 return 0;
5178
5179error4:
5180 kmem_cache_destroy(hsotg->desc_gen_cache);
5181 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5182error3:
5183 dwc2_hcd_release(hsotg);
5184error2:
5185 usb_put_hcd(hcd);
5186error1:
5187
5188#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5189 kfree(hsotg->last_frame_num_array);
5190 kfree(hsotg->frame_num_array);
5191#endif
5192
5193 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
5194 return retval;
5195}
5196
5197/*
5198 * Removes the HCD.
5199 * Frees memory and resources associated with the HCD and deregisters the bus.
5200 */
5201void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
5202{
5203 struct usb_hcd *hcd;
5204
5205 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
5206
5207 hcd = dwc2_hsotg_to_hcd(hsotg);
5208 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
5209
5210 if (!hcd) {
5211 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
5212 __func__);
5213 return;
5214 }
5215
5216 if (!IS_ERR_OR_NULL(hsotg->uphy))
5217 otg_set_host(hsotg->uphy->otg, NULL);
5218
5219 usb_remove_hcd(hcd);
5220 hsotg->priv = NULL;
5221
5222 kmem_cache_destroy(hsotg->desc_gen_cache);
5223 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5224
5225 dwc2_hcd_release(hsotg);
5226 usb_put_hcd(hcd);
5227
5228#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5229 kfree(hsotg->last_frame_num_array);
5230 kfree(hsotg->frame_num_array);
5231#endif
5232}
5233
5234/**
5235 * dwc2_backup_host_registers() - Backup controller host registers.
5236 * When suspending usb bus, registers needs to be backuped
5237 * if controller power is disabled once suspended.
5238 *
5239 * @hsotg: Programming view of the DWC_otg controller
5240 */
5241int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
5242{
5243 struct dwc2_hregs_backup *hr;
5244 int i;
5245
5246 dev_dbg(hsotg->dev, "%s\n", __func__);
5247
5248 /* Backup Host regs */
5249 hr = &hsotg->hr_backup;
5250 hr->hcfg = dwc2_readl(hsotg->regs + HCFG);
5251 hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
5252 for (i = 0; i < hsotg->params.host_channels; ++i)
5253 hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i));
5254
5255 hr->hprt0 = dwc2_read_hprt0(hsotg);
5256 hr->hfir = dwc2_readl(hsotg->regs + HFIR);
5257 hr->valid = true;
5258
5259 return 0;
5260}
5261
5262/**
5263 * dwc2_restore_host_registers() - Restore controller host registers.
5264 * When resuming usb bus, device registers needs to be restored
5265 * if controller power were disabled.
5266 *
5267 * @hsotg: Programming view of the DWC_otg controller
5268 */
5269int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
5270{
5271 struct dwc2_hregs_backup *hr;
5272 int i;
5273
5274 dev_dbg(hsotg->dev, "%s\n", __func__);
5275
5276 /* Restore host regs */
5277 hr = &hsotg->hr_backup;
5278 if (!hr->valid) {
5279 dev_err(hsotg->dev, "%s: no host registers to restore\n",
5280 __func__);
5281 return -EINVAL;
5282 }
5283 hr->valid = false;
5284
5285 dwc2_writel(hr->hcfg, hsotg->regs + HCFG);
5286 dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK);
5287
5288 for (i = 0; i < hsotg->params.host_channels; ++i)
5289 dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i));
5290
5291 dwc2_writel(hr->hprt0, hsotg->regs + HPRT0);
5292 dwc2_writel(hr->hfir, hsotg->regs + HFIR);
5293 hsotg->frame_number = 0;
5294
5295 return 0;
5296}
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * hcd.c - DesignWare HS OTG Controller host-mode routines
4 *
5 * Copyright (C) 2004-2013 Synopsys, Inc.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
19 *
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
23 * later version.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 */
37
38/*
39 * This file contains the core HCD code, and implements the Linux hc_driver
40 * API
41 */
42#include <linux/kernel.h>
43#include <linux/module.h>
44#include <linux/spinlock.h>
45#include <linux/interrupt.h>
46#include <linux/platform_device.h>
47#include <linux/dma-mapping.h>
48#include <linux/delay.h>
49#include <linux/io.h>
50#include <linux/slab.h>
51#include <linux/usb.h>
52
53#include <linux/usb/hcd.h>
54#include <linux/usb/ch11.h>
55
56#include "core.h"
57#include "hcd.h"
58
59static void dwc2_port_resume(struct dwc2_hsotg *hsotg);
60
61/*
62 * =========================================================================
63 * Host Core Layer Functions
64 * =========================================================================
65 */
66
67/**
68 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
69 * used in both device and host modes
70 *
71 * @hsotg: Programming view of the DWC_otg controller
72 */
73static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
74{
75 u32 intmsk;
76
77 /* Clear any pending OTG Interrupts */
78 dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
79
80 /* Clear any pending interrupts */
81 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
82
83 /* Enable the interrupts in the GINTMSK */
84 intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
85
86 if (!hsotg->params.host_dma)
87 intmsk |= GINTSTS_RXFLVL;
88 if (!hsotg->params.external_id_pin_ctl)
89 intmsk |= GINTSTS_CONIDSTSCHNG;
90
91 intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP |
92 GINTSTS_SESSREQINT;
93
94 if (dwc2_is_device_mode(hsotg) && hsotg->params.lpm)
95 intmsk |= GINTSTS_LPMTRANRCVD;
96
97 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
98}
99
100/*
101 * Initializes the FSLSPClkSel field of the HCFG register depending on the
102 * PHY type
103 */
104static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
105{
106 u32 hcfg, val;
107
108 if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
109 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
110 hsotg->params.ulpi_fs_ls) ||
111 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
112 /* Full speed PHY */
113 val = HCFG_FSLSPCLKSEL_48_MHZ;
114 } else {
115 /* High speed PHY running at full speed or high speed */
116 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
117 }
118
119 dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
120 hcfg = dwc2_readl(hsotg->regs + HCFG);
121 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
122 hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
123 dwc2_writel(hcfg, hsotg->regs + HCFG);
124}
125
126static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
127{
128 u32 usbcfg, ggpio, i2cctl;
129 int retval = 0;
130
131 /*
132 * core_init() is now called on every switch so only call the
133 * following for the first time through
134 */
135 if (select_phy) {
136 dev_dbg(hsotg->dev, "FS PHY selected\n");
137
138 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
139 if (!(usbcfg & GUSBCFG_PHYSEL)) {
140 usbcfg |= GUSBCFG_PHYSEL;
141 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
142
143 /* Reset after a PHY select */
144 retval = dwc2_core_reset(hsotg, false);
145
146 if (retval) {
147 dev_err(hsotg->dev,
148 "%s: Reset failed, aborting", __func__);
149 return retval;
150 }
151 }
152
153 if (hsotg->params.activate_stm_fs_transceiver) {
154 ggpio = dwc2_readl(hsotg->regs + GGPIO);
155 if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
156 dev_dbg(hsotg->dev, "Activating transceiver\n");
157 /*
158 * STM32F4x9 uses the GGPIO register as general
159 * core configuration register.
160 */
161 ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
162 dwc2_writel(ggpio, hsotg->regs + GGPIO);
163 }
164 }
165 }
166
167 /*
168 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
169 * do this on HNP Dev/Host mode switches (done in dev_init and
170 * host_init).
171 */
172 if (dwc2_is_host_mode(hsotg))
173 dwc2_init_fs_ls_pclk_sel(hsotg);
174
175 if (hsotg->params.i2c_enable) {
176 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
177
178 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
179 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
180 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
181 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
182
183 /* Program GI2CCTL.I2CEn */
184 i2cctl = dwc2_readl(hsotg->regs + GI2CCTL);
185 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
186 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
187 i2cctl &= ~GI2CCTL_I2CEN;
188 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
189 i2cctl |= GI2CCTL_I2CEN;
190 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
191 }
192
193 return retval;
194}
195
196static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
197{
198 u32 usbcfg, usbcfg_old;
199 int retval = 0;
200
201 if (!select_phy)
202 return 0;
203
204 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
205 usbcfg_old = usbcfg;
206
207 /*
208 * HS PHY parameters. These parameters are preserved during soft reset
209 * so only program the first time. Do a soft reset immediately after
210 * setting phyif.
211 */
212 switch (hsotg->params.phy_type) {
213 case DWC2_PHY_TYPE_PARAM_ULPI:
214 /* ULPI interface */
215 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
216 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
217 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
218 if (hsotg->params.phy_ulpi_ddr)
219 usbcfg |= GUSBCFG_DDRSEL;
220
221 /* Set external VBUS indicator as needed. */
222 if (hsotg->params.oc_disable)
223 usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND |
224 GUSBCFG_INDICATORPASSTHROUGH);
225 break;
226 case DWC2_PHY_TYPE_PARAM_UTMI:
227 /* UTMI+ interface */
228 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
229 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
230 if (hsotg->params.phy_utmi_width == 16)
231 usbcfg |= GUSBCFG_PHYIF16;
232 break;
233 default:
234 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
235 break;
236 }
237
238 if (usbcfg != usbcfg_old) {
239 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
240
241 /* Reset after setting the PHY parameters */
242 retval = dwc2_core_reset(hsotg, false);
243 if (retval) {
244 dev_err(hsotg->dev,
245 "%s: Reset failed, aborting", __func__);
246 return retval;
247 }
248 }
249
250 return retval;
251}
252
253static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
254{
255 u32 usbcfg;
256 int retval = 0;
257
258 if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
259 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) &&
260 hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
261 /* If FS/LS mode with FS/LS PHY */
262 retval = dwc2_fs_phy_init(hsotg, select_phy);
263 if (retval)
264 return retval;
265 } else {
266 /* High speed PHY */
267 retval = dwc2_hs_phy_init(hsotg, select_phy);
268 if (retval)
269 return retval;
270 }
271
272 if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
273 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
274 hsotg->params.ulpi_fs_ls) {
275 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
276 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
277 usbcfg |= GUSBCFG_ULPI_FS_LS;
278 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
279 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
280 } else {
281 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
282 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
283 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
284 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
285 }
286
287 return retval;
288}
289
290static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
291{
292 u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
293
294 switch (hsotg->hw_params.arch) {
295 case GHWCFG2_EXT_DMA_ARCH:
296 dev_err(hsotg->dev, "External DMA Mode not supported\n");
297 return -EINVAL;
298
299 case GHWCFG2_INT_DMA_ARCH:
300 dev_dbg(hsotg->dev, "Internal DMA Mode\n");
301 if (hsotg->params.ahbcfg != -1) {
302 ahbcfg &= GAHBCFG_CTRL_MASK;
303 ahbcfg |= hsotg->params.ahbcfg &
304 ~GAHBCFG_CTRL_MASK;
305 }
306 break;
307
308 case GHWCFG2_SLAVE_ONLY_ARCH:
309 default:
310 dev_dbg(hsotg->dev, "Slave Only Mode\n");
311 break;
312 }
313
314 if (hsotg->params.host_dma)
315 ahbcfg |= GAHBCFG_DMA_EN;
316 else
317 hsotg->params.dma_desc_enable = false;
318
319 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
320
321 return 0;
322}
323
324static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
325{
326 u32 usbcfg;
327
328 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
329 usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
330
331 switch (hsotg->hw_params.op_mode) {
332 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
333 if (hsotg->params.otg_cap ==
334 DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
335 usbcfg |= GUSBCFG_HNPCAP;
336 if (hsotg->params.otg_cap !=
337 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
338 usbcfg |= GUSBCFG_SRPCAP;
339 break;
340
341 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
342 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
343 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
344 if (hsotg->params.otg_cap !=
345 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
346 usbcfg |= GUSBCFG_SRPCAP;
347 break;
348
349 case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE:
350 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE:
351 case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST:
352 default:
353 break;
354 }
355
356 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
357}
358
359static int dwc2_vbus_supply_init(struct dwc2_hsotg *hsotg)
360{
361 int ret;
362
363 hsotg->vbus_supply = devm_regulator_get_optional(hsotg->dev, "vbus");
364 if (IS_ERR(hsotg->vbus_supply)) {
365 ret = PTR_ERR(hsotg->vbus_supply);
366 hsotg->vbus_supply = NULL;
367 return ret == -ENODEV ? 0 : ret;
368 }
369
370 return regulator_enable(hsotg->vbus_supply);
371}
372
373static int dwc2_vbus_supply_exit(struct dwc2_hsotg *hsotg)
374{
375 if (hsotg->vbus_supply)
376 return regulator_disable(hsotg->vbus_supply);
377
378 return 0;
379}
380
381/**
382 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
383 *
384 * @hsotg: Programming view of DWC_otg controller
385 */
386static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
387{
388 u32 intmsk;
389
390 dev_dbg(hsotg->dev, "%s()\n", __func__);
391
392 /* Disable all interrupts */
393 dwc2_writel(0, hsotg->regs + GINTMSK);
394 dwc2_writel(0, hsotg->regs + HAINTMSK);
395
396 /* Enable the common interrupts */
397 dwc2_enable_common_interrupts(hsotg);
398
399 /* Enable host mode interrupts without disturbing common interrupts */
400 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
401 intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
402 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
403}
404
405/**
406 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
407 *
408 * @hsotg: Programming view of DWC_otg controller
409 */
410static void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
411{
412 u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
413
414 /* Disable host mode interrupts without disturbing common interrupts */
415 intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
416 GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT);
417 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
418}
419
420/*
421 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size
422 * For system that have a total fifo depth that is smaller than the default
423 * RX + TX fifo size.
424 *
425 * @hsotg: Programming view of DWC_otg controller
426 */
427static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)
428{
429 struct dwc2_core_params *params = &hsotg->params;
430 struct dwc2_hw_params *hw = &hsotg->hw_params;
431 u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size;
432
433 total_fifo_size = hw->total_fifo_size;
434 rxfsiz = params->host_rx_fifo_size;
435 nptxfsiz = params->host_nperio_tx_fifo_size;
436 ptxfsiz = params->host_perio_tx_fifo_size;
437
438 /*
439 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth
440 * allocation with support for high bandwidth endpoints. Synopsys
441 * defines MPS(Max Packet size) for a periodic EP=1024, and for
442 * non-periodic as 512.
443 */
444 if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) {
445 /*
446 * For Buffer DMA mode/Scatter Gather DMA mode
447 * 2 * ((Largest Packet size / 4) + 1 + 1) + n
448 * with n = number of host channel.
449 * 2 * ((1024/4) + 2) = 516
450 */
451 rxfsiz = 516 + hw->host_channels;
452
453 /*
454 * min non-periodic tx fifo depth
455 * 2 * (largest non-periodic USB packet used / 4)
456 * 2 * (512/4) = 256
457 */
458 nptxfsiz = 256;
459
460 /*
461 * min periodic tx fifo depth
462 * (largest packet size*MC)/4
463 * (1024 * 3)/4 = 768
464 */
465 ptxfsiz = 768;
466
467 params->host_rx_fifo_size = rxfsiz;
468 params->host_nperio_tx_fifo_size = nptxfsiz;
469 params->host_perio_tx_fifo_size = ptxfsiz;
470 }
471
472 /*
473 * If the summation of RX, NPTX and PTX fifo sizes is still
474 * bigger than the total_fifo_size, then we have a problem.
475 *
476 * We won't be able to allocate as many endpoints. Right now,
477 * we're just printing an error message, but ideally this FIFO
478 * allocation algorithm would be improved in the future.
479 *
480 * FIXME improve this FIFO allocation algorithm.
481 */
482 if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)))
483 dev_err(hsotg->dev, "invalid fifo sizes\n");
484}
485
486static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
487{
488 struct dwc2_core_params *params = &hsotg->params;
489 u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;
490
491 if (!params->enable_dynamic_fifo)
492 return;
493
494 dwc2_calculate_dynamic_fifo(hsotg);
495
496 /* Rx FIFO */
497 grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
498 dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
499 grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
500 grxfsiz |= params->host_rx_fifo_size <<
501 GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
502 dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ);
503 dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
504 dwc2_readl(hsotg->regs + GRXFSIZ));
505
506 /* Non-periodic Tx FIFO */
507 dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
508 dwc2_readl(hsotg->regs + GNPTXFSIZ));
509 nptxfsiz = params->host_nperio_tx_fifo_size <<
510 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
511 nptxfsiz |= params->host_rx_fifo_size <<
512 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
513 dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ);
514 dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
515 dwc2_readl(hsotg->regs + GNPTXFSIZ));
516
517 /* Periodic Tx FIFO */
518 dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
519 dwc2_readl(hsotg->regs + HPTXFSIZ));
520 hptxfsiz = params->host_perio_tx_fifo_size <<
521 FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
522 hptxfsiz |= (params->host_rx_fifo_size +
523 params->host_nperio_tx_fifo_size) <<
524 FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
525 dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ);
526 dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
527 dwc2_readl(hsotg->regs + HPTXFSIZ));
528
529 if (hsotg->params.en_multiple_tx_fifo &&
530 hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_91a) {
531 /*
532 * This feature was implemented in 2.91a version
533 * Global DFIFOCFG calculation for Host mode -
534 * include RxFIFO, NPTXFIFO and HPTXFIFO
535 */
536 dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
537 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
538 dfifocfg |= (params->host_rx_fifo_size +
539 params->host_nperio_tx_fifo_size +
540 params->host_perio_tx_fifo_size) <<
541 GDFIFOCFG_EPINFOBASE_SHIFT &
542 GDFIFOCFG_EPINFOBASE_MASK;
543 dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG);
544 }
545}
546
547/**
548 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
549 * the HFIR register according to PHY type and speed
550 *
551 * @hsotg: Programming view of DWC_otg controller
552 *
553 * NOTE: The caller can modify the value of the HFIR register only after the
554 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort)
555 * has been set
556 */
557u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
558{
559 u32 usbcfg;
560 u32 hprt0;
561 int clock = 60; /* default value */
562
563 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
564 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
565
566 if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
567 !(usbcfg & GUSBCFG_PHYIF16))
568 clock = 60;
569 if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type ==
570 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
571 clock = 48;
572 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
573 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
574 clock = 30;
575 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
576 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16))
577 clock = 60;
578 if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
579 !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
580 clock = 48;
581 if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
582 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
583 clock = 48;
584 if ((usbcfg & GUSBCFG_PHYSEL) &&
585 hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
586 clock = 48;
587
588 if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)
589 /* High speed case */
590 return 125 * clock - 1;
591
592 /* FS/LS case */
593 return 1000 * clock - 1;
594}
595
596/**
597 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
598 * buffer
599 *
600 * @core_if: Programming view of DWC_otg controller
601 * @dest: Destination buffer for the packet
602 * @bytes: Number of bytes to copy to the destination
603 */
604void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
605{
606 u32 __iomem *fifo = hsotg->regs + HCFIFO(0);
607 u32 *data_buf = (u32 *)dest;
608 int word_count = (bytes + 3) / 4;
609 int i;
610
611 /*
612 * Todo: Account for the case where dest is not dword aligned. This
613 * requires reading data from the FIFO into a u32 temp buffer, then
614 * moving it into the data buffer.
615 */
616
617 dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
618
619 for (i = 0; i < word_count; i++, data_buf++)
620 *data_buf = dwc2_readl(fifo);
621}
622
623/**
624 * dwc2_dump_channel_info() - Prints the state of a host channel
625 *
626 * @hsotg: Programming view of DWC_otg controller
627 * @chan: Pointer to the channel to dump
628 *
629 * Must be called with interrupt disabled and spinlock held
630 *
631 * NOTE: This function will be removed once the peripheral controller code
632 * is integrated and the driver is stable
633 */
634static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
635 struct dwc2_host_chan *chan)
636{
637#ifdef VERBOSE_DEBUG
638 int num_channels = hsotg->params.host_channels;
639 struct dwc2_qh *qh;
640 u32 hcchar;
641 u32 hcsplt;
642 u32 hctsiz;
643 u32 hc_dma;
644 int i;
645
646 if (!chan)
647 return;
648
649 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
650 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
651 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num));
652 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num));
653
654 dev_dbg(hsotg->dev, " Assigned to channel %p:\n", chan);
655 dev_dbg(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n",
656 hcchar, hcsplt);
657 dev_dbg(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n",
658 hctsiz, hc_dma);
659 dev_dbg(hsotg->dev, " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
660 chan->dev_addr, chan->ep_num, chan->ep_is_in);
661 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
662 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
663 dev_dbg(hsotg->dev, " data_pid_start: %d\n", chan->data_pid_start);
664 dev_dbg(hsotg->dev, " xfer_started: %d\n", chan->xfer_started);
665 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
666 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
667 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
668 (unsigned long)chan->xfer_dma);
669 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
670 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
671 dev_dbg(hsotg->dev, " NP inactive sched:\n");
672 list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
673 qh_list_entry)
674 dev_dbg(hsotg->dev, " %p\n", qh);
675 dev_dbg(hsotg->dev, " NP waiting sched:\n");
676 list_for_each_entry(qh, &hsotg->non_periodic_sched_waiting,
677 qh_list_entry)
678 dev_dbg(hsotg->dev, " %p\n", qh);
679 dev_dbg(hsotg->dev, " NP active sched:\n");
680 list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
681 qh_list_entry)
682 dev_dbg(hsotg->dev, " %p\n", qh);
683 dev_dbg(hsotg->dev, " Channels:\n");
684 for (i = 0; i < num_channels; i++) {
685 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
686
687 dev_dbg(hsotg->dev, " %2d: %p\n", i, chan);
688 }
689#endif /* VERBOSE_DEBUG */
690}
691
692static int _dwc2_hcd_start(struct usb_hcd *hcd);
693
694static void dwc2_host_start(struct dwc2_hsotg *hsotg)
695{
696 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
697
698 hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
699 _dwc2_hcd_start(hcd);
700}
701
702static void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
703{
704 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
705
706 hcd->self.is_b_host = 0;
707}
708
709static void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context,
710 int *hub_addr, int *hub_port)
711{
712 struct urb *urb = context;
713
714 if (urb->dev->tt)
715 *hub_addr = urb->dev->tt->hub->devnum;
716 else
717 *hub_addr = 0;
718 *hub_port = urb->dev->ttport;
719}
720
721/*
722 * =========================================================================
723 * Low Level Host Channel Access Functions
724 * =========================================================================
725 */
726
727static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
728 struct dwc2_host_chan *chan)
729{
730 u32 hcintmsk = HCINTMSK_CHHLTD;
731
732 switch (chan->ep_type) {
733 case USB_ENDPOINT_XFER_CONTROL:
734 case USB_ENDPOINT_XFER_BULK:
735 dev_vdbg(hsotg->dev, "control/bulk\n");
736 hcintmsk |= HCINTMSK_XFERCOMPL;
737 hcintmsk |= HCINTMSK_STALL;
738 hcintmsk |= HCINTMSK_XACTERR;
739 hcintmsk |= HCINTMSK_DATATGLERR;
740 if (chan->ep_is_in) {
741 hcintmsk |= HCINTMSK_BBLERR;
742 } else {
743 hcintmsk |= HCINTMSK_NAK;
744 hcintmsk |= HCINTMSK_NYET;
745 if (chan->do_ping)
746 hcintmsk |= HCINTMSK_ACK;
747 }
748
749 if (chan->do_split) {
750 hcintmsk |= HCINTMSK_NAK;
751 if (chan->complete_split)
752 hcintmsk |= HCINTMSK_NYET;
753 else
754 hcintmsk |= HCINTMSK_ACK;
755 }
756
757 if (chan->error_state)
758 hcintmsk |= HCINTMSK_ACK;
759 break;
760
761 case USB_ENDPOINT_XFER_INT:
762 if (dbg_perio())
763 dev_vdbg(hsotg->dev, "intr\n");
764 hcintmsk |= HCINTMSK_XFERCOMPL;
765 hcintmsk |= HCINTMSK_NAK;
766 hcintmsk |= HCINTMSK_STALL;
767 hcintmsk |= HCINTMSK_XACTERR;
768 hcintmsk |= HCINTMSK_DATATGLERR;
769 hcintmsk |= HCINTMSK_FRMOVRUN;
770
771 if (chan->ep_is_in)
772 hcintmsk |= HCINTMSK_BBLERR;
773 if (chan->error_state)
774 hcintmsk |= HCINTMSK_ACK;
775 if (chan->do_split) {
776 if (chan->complete_split)
777 hcintmsk |= HCINTMSK_NYET;
778 else
779 hcintmsk |= HCINTMSK_ACK;
780 }
781 break;
782
783 case USB_ENDPOINT_XFER_ISOC:
784 if (dbg_perio())
785 dev_vdbg(hsotg->dev, "isoc\n");
786 hcintmsk |= HCINTMSK_XFERCOMPL;
787 hcintmsk |= HCINTMSK_FRMOVRUN;
788 hcintmsk |= HCINTMSK_ACK;
789
790 if (chan->ep_is_in) {
791 hcintmsk |= HCINTMSK_XACTERR;
792 hcintmsk |= HCINTMSK_BBLERR;
793 }
794 break;
795 default:
796 dev_err(hsotg->dev, "## Unknown EP type ##\n");
797 break;
798 }
799
800 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
801 if (dbg_hc(chan))
802 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
803}
804
805static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
806 struct dwc2_host_chan *chan)
807{
808 u32 hcintmsk = HCINTMSK_CHHLTD;
809
810 /*
811 * For Descriptor DMA mode core halts the channel on AHB error.
812 * Interrupt is not required.
813 */
814 if (!hsotg->params.dma_desc_enable) {
815 if (dbg_hc(chan))
816 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
817 hcintmsk |= HCINTMSK_AHBERR;
818 } else {
819 if (dbg_hc(chan))
820 dev_vdbg(hsotg->dev, "desc DMA enabled\n");
821 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
822 hcintmsk |= HCINTMSK_XFERCOMPL;
823 }
824
825 if (chan->error_state && !chan->do_split &&
826 chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
827 if (dbg_hc(chan))
828 dev_vdbg(hsotg->dev, "setting ACK\n");
829 hcintmsk |= HCINTMSK_ACK;
830 if (chan->ep_is_in) {
831 hcintmsk |= HCINTMSK_DATATGLERR;
832 if (chan->ep_type != USB_ENDPOINT_XFER_INT)
833 hcintmsk |= HCINTMSK_NAK;
834 }
835 }
836
837 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
838 if (dbg_hc(chan))
839 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
840}
841
842static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
843 struct dwc2_host_chan *chan)
844{
845 u32 intmsk;
846
847 if (hsotg->params.host_dma) {
848 if (dbg_hc(chan))
849 dev_vdbg(hsotg->dev, "DMA enabled\n");
850 dwc2_hc_enable_dma_ints(hsotg, chan);
851 } else {
852 if (dbg_hc(chan))
853 dev_vdbg(hsotg->dev, "DMA disabled\n");
854 dwc2_hc_enable_slave_ints(hsotg, chan);
855 }
856
857 /* Enable the top level host channel interrupt */
858 intmsk = dwc2_readl(hsotg->regs + HAINTMSK);
859 intmsk |= 1 << chan->hc_num;
860 dwc2_writel(intmsk, hsotg->regs + HAINTMSK);
861 if (dbg_hc(chan))
862 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
863
864 /* Make sure host channel interrupts are enabled */
865 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
866 intmsk |= GINTSTS_HCHINT;
867 dwc2_writel(intmsk, hsotg->regs + GINTMSK);
868 if (dbg_hc(chan))
869 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
870}
871
872/**
873 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
874 * a specific endpoint
875 *
876 * @hsotg: Programming view of DWC_otg controller
877 * @chan: Information needed to initialize the host channel
878 *
879 * The HCCHARn register is set up with the characteristics specified in chan.
880 * Host channel interrupts that may need to be serviced while this transfer is
881 * in progress are enabled.
882 */
883static void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
884{
885 u8 hc_num = chan->hc_num;
886 u32 hcintmsk;
887 u32 hcchar;
888 u32 hcsplt = 0;
889
890 if (dbg_hc(chan))
891 dev_vdbg(hsotg->dev, "%s()\n", __func__);
892
893 /* Clear old interrupt conditions for this host channel */
894 hcintmsk = 0xffffffff;
895 hcintmsk &= ~HCINTMSK_RESERVED14_31;
896 dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num));
897
898 /* Enable channel interrupts required for this transfer */
899 dwc2_hc_enable_ints(hsotg, chan);
900
901 /*
902 * Program the HCCHARn register with the endpoint characteristics for
903 * the current transfer
904 */
905 hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK;
906 hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK;
907 if (chan->ep_is_in)
908 hcchar |= HCCHAR_EPDIR;
909 if (chan->speed == USB_SPEED_LOW)
910 hcchar |= HCCHAR_LSPDDEV;
911 hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
912 hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
913 dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num));
914 if (dbg_hc(chan)) {
915 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
916 hc_num, hcchar);
917
918 dev_vdbg(hsotg->dev, "%s: Channel %d\n",
919 __func__, hc_num);
920 dev_vdbg(hsotg->dev, " Dev Addr: %d\n",
921 chan->dev_addr);
922 dev_vdbg(hsotg->dev, " Ep Num: %d\n",
923 chan->ep_num);
924 dev_vdbg(hsotg->dev, " Is In: %d\n",
925 chan->ep_is_in);
926 dev_vdbg(hsotg->dev, " Is Low Speed: %d\n",
927 chan->speed == USB_SPEED_LOW);
928 dev_vdbg(hsotg->dev, " Ep Type: %d\n",
929 chan->ep_type);
930 dev_vdbg(hsotg->dev, " Max Pkt: %d\n",
931 chan->max_packet);
932 }
933
934 /* Program the HCSPLT register for SPLITs */
935 if (chan->do_split) {
936 if (dbg_hc(chan))
937 dev_vdbg(hsotg->dev,
938 "Programming HC %d with split --> %s\n",
939 hc_num,
940 chan->complete_split ? "CSPLIT" : "SSPLIT");
941 if (chan->complete_split)
942 hcsplt |= HCSPLT_COMPSPLT;
943 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT &
944 HCSPLT_XACTPOS_MASK;
945 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT &
946 HCSPLT_HUBADDR_MASK;
947 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT &
948 HCSPLT_PRTADDR_MASK;
949 if (dbg_hc(chan)) {
950 dev_vdbg(hsotg->dev, " comp split %d\n",
951 chan->complete_split);
952 dev_vdbg(hsotg->dev, " xact pos %d\n",
953 chan->xact_pos);
954 dev_vdbg(hsotg->dev, " hub addr %d\n",
955 chan->hub_addr);
956 dev_vdbg(hsotg->dev, " hub port %d\n",
957 chan->hub_port);
958 dev_vdbg(hsotg->dev, " is_in %d\n",
959 chan->ep_is_in);
960 dev_vdbg(hsotg->dev, " Max Pkt %d\n",
961 chan->max_packet);
962 dev_vdbg(hsotg->dev, " xferlen %d\n",
963 chan->xfer_len);
964 }
965 }
966
967 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num));
968}
969
970/**
971 * dwc2_hc_halt() - Attempts to halt a host channel
972 *
973 * @hsotg: Controller register interface
974 * @chan: Host channel to halt
975 * @halt_status: Reason for halting the channel
976 *
977 * This function should only be called in Slave mode or to abort a transfer in
978 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
979 * controller halts the channel when the transfer is complete or a condition
980 * occurs that requires application intervention.
981 *
982 * In slave mode, checks for a free request queue entry, then sets the Channel
983 * Enable and Channel Disable bits of the Host Channel Characteristics
984 * register of the specified channel to intiate the halt. If there is no free
985 * request queue entry, sets only the Channel Disable bit of the HCCHARn
986 * register to flush requests for this channel. In the latter case, sets a
987 * flag to indicate that the host channel needs to be halted when a request
988 * queue slot is open.
989 *
990 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
991 * HCCHARn register. The controller ensures there is space in the request
992 * queue before submitting the halt request.
993 *
994 * Some time may elapse before the core flushes any posted requests for this
995 * host channel and halts. The Channel Halted interrupt handler completes the
996 * deactivation of the host channel.
997 */
998void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
999 enum dwc2_halt_status halt_status)
1000{
1001 u32 nptxsts, hptxsts, hcchar;
1002
1003 if (dbg_hc(chan))
1004 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1005
1006 /*
1007 * In buffer DMA or external DMA mode channel can't be halted
1008 * for non-split periodic channels. At the end of the next
1009 * uframe/frame (in the worst case), the core generates a channel
1010 * halted and disables the channel automatically.
1011 */
1012 if ((hsotg->params.g_dma && !hsotg->params.g_dma_desc) ||
1013 hsotg->hw_params.arch == GHWCFG2_EXT_DMA_ARCH) {
1014 if (!chan->do_split &&
1015 (chan->ep_type == USB_ENDPOINT_XFER_ISOC ||
1016 chan->ep_type == USB_ENDPOINT_XFER_INT)) {
1017 dev_err(hsotg->dev, "%s() Channel can't be halted\n",
1018 __func__);
1019 return;
1020 }
1021 }
1022
1023 if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS)
1024 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
1025
1026 if (halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1027 halt_status == DWC2_HC_XFER_AHB_ERR) {
1028 /*
1029 * Disable all channel interrupts except Ch Halted. The QTD
1030 * and QH state associated with this transfer has been cleared
1031 * (in the case of URB_DEQUEUE), so the channel needs to be
1032 * shut down carefully to prevent crashes.
1033 */
1034 u32 hcintmsk = HCINTMSK_CHHLTD;
1035
1036 dev_vdbg(hsotg->dev, "dequeue/error\n");
1037 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
1038
1039 /*
1040 * Make sure no other interrupts besides halt are currently
1041 * pending. Handling another interrupt could cause a crash due
1042 * to the QTD and QH state.
1043 */
1044 dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1045
1046 /*
1047 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
1048 * even if the channel was already halted for some other
1049 * reason
1050 */
1051 chan->halt_status = halt_status;
1052
1053 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1054 if (!(hcchar & HCCHAR_CHENA)) {
1055 /*
1056 * The channel is either already halted or it hasn't
1057 * started yet. In DMA mode, the transfer may halt if
1058 * it finishes normally or a condition occurs that
1059 * requires driver intervention. Don't want to halt
1060 * the channel again. In either Slave or DMA mode,
1061 * it's possible that the transfer has been assigned
1062 * to a channel, but not started yet when an URB is
1063 * dequeued. Don't want to halt a channel that hasn't
1064 * started yet.
1065 */
1066 return;
1067 }
1068 }
1069 if (chan->halt_pending) {
1070 /*
1071 * A halt has already been issued for this channel. This might
1072 * happen when a transfer is aborted by a higher level in
1073 * the stack.
1074 */
1075 dev_vdbg(hsotg->dev,
1076 "*** %s: Channel %d, chan->halt_pending already set ***\n",
1077 __func__, chan->hc_num);
1078 return;
1079 }
1080
1081 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1082
1083 /* No need to set the bit in DDMA for disabling the channel */
1084 /* TODO check it everywhere channel is disabled */
1085 if (!hsotg->params.dma_desc_enable) {
1086 if (dbg_hc(chan))
1087 dev_vdbg(hsotg->dev, "desc DMA disabled\n");
1088 hcchar |= HCCHAR_CHENA;
1089 } else {
1090 if (dbg_hc(chan))
1091 dev_dbg(hsotg->dev, "desc DMA enabled\n");
1092 }
1093 hcchar |= HCCHAR_CHDIS;
1094
1095 if (!hsotg->params.host_dma) {
1096 if (dbg_hc(chan))
1097 dev_vdbg(hsotg->dev, "DMA not enabled\n");
1098 hcchar |= HCCHAR_CHENA;
1099
1100 /* Check for space in the request queue to issue the halt */
1101 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1102 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
1103 dev_vdbg(hsotg->dev, "control/bulk\n");
1104 nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
1105 if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
1106 dev_vdbg(hsotg->dev, "Disabling channel\n");
1107 hcchar &= ~HCCHAR_CHENA;
1108 }
1109 } else {
1110 if (dbg_perio())
1111 dev_vdbg(hsotg->dev, "isoc/intr\n");
1112 hptxsts = dwc2_readl(hsotg->regs + HPTXSTS);
1113 if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
1114 hsotg->queuing_high_bandwidth) {
1115 if (dbg_perio())
1116 dev_vdbg(hsotg->dev, "Disabling channel\n");
1117 hcchar &= ~HCCHAR_CHENA;
1118 }
1119 }
1120 } else {
1121 if (dbg_hc(chan))
1122 dev_vdbg(hsotg->dev, "DMA enabled\n");
1123 }
1124
1125 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1126 chan->halt_status = halt_status;
1127
1128 if (hcchar & HCCHAR_CHENA) {
1129 if (dbg_hc(chan))
1130 dev_vdbg(hsotg->dev, "Channel enabled\n");
1131 chan->halt_pending = 1;
1132 chan->halt_on_queue = 0;
1133 } else {
1134 if (dbg_hc(chan))
1135 dev_vdbg(hsotg->dev, "Channel disabled\n");
1136 chan->halt_on_queue = 1;
1137 }
1138
1139 if (dbg_hc(chan)) {
1140 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1141 chan->hc_num);
1142 dev_vdbg(hsotg->dev, " hcchar: 0x%08x\n",
1143 hcchar);
1144 dev_vdbg(hsotg->dev, " halt_pending: %d\n",
1145 chan->halt_pending);
1146 dev_vdbg(hsotg->dev, " halt_on_queue: %d\n",
1147 chan->halt_on_queue);
1148 dev_vdbg(hsotg->dev, " halt_status: %d\n",
1149 chan->halt_status);
1150 }
1151}
1152
1153/**
1154 * dwc2_hc_cleanup() - Clears the transfer state for a host channel
1155 *
1156 * @hsotg: Programming view of DWC_otg controller
1157 * @chan: Identifies the host channel to clean up
1158 *
1159 * This function is normally called after a transfer is done and the host
1160 * channel is being released
1161 */
1162void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1163{
1164 u32 hcintmsk;
1165
1166 chan->xfer_started = 0;
1167
1168 list_del_init(&chan->split_order_list_entry);
1169
1170 /*
1171 * Clear channel interrupt enables and any unhandled channel interrupt
1172 * conditions
1173 */
1174 dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num));
1175 hcintmsk = 0xffffffff;
1176 hcintmsk &= ~HCINTMSK_RESERVED14_31;
1177 dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1178}
1179
1180/**
1181 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
1182 * which frame a periodic transfer should occur
1183 *
1184 * @hsotg: Programming view of DWC_otg controller
1185 * @chan: Identifies the host channel to set up and its properties
1186 * @hcchar: Current value of the HCCHAR register for the specified host channel
1187 *
1188 * This function has no effect on non-periodic transfers
1189 */
1190static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
1191 struct dwc2_host_chan *chan, u32 *hcchar)
1192{
1193 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1194 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1195 int host_speed;
1196 int xfer_ns;
1197 int xfer_us;
1198 int bytes_in_fifo;
1199 u16 fifo_space;
1200 u16 frame_number;
1201 u16 wire_frame;
1202
1203 /*
1204 * Try to figure out if we're an even or odd frame. If we set
1205 * even and the current frame number is even the the transfer
1206 * will happen immediately. Similar if both are odd. If one is
1207 * even and the other is odd then the transfer will happen when
1208 * the frame number ticks.
1209 *
1210 * There's a bit of a balancing act to get this right.
1211 * Sometimes we may want to send data in the current frame (AK
1212 * right away). We might want to do this if the frame number
1213 * _just_ ticked, but we might also want to do this in order
1214 * to continue a split transaction that happened late in a
1215 * microframe (so we didn't know to queue the next transfer
1216 * until the frame number had ticked). The problem is that we
1217 * need a lot of knowledge to know if there's actually still
1218 * time to send things or if it would be better to wait until
1219 * the next frame.
1220 *
1221 * We can look at how much time is left in the current frame
1222 * and make a guess about whether we'll have time to transfer.
1223 * We'll do that.
1224 */
1225
1226 /* Get speed host is running at */
1227 host_speed = (chan->speed != USB_SPEED_HIGH &&
1228 !chan->do_split) ? chan->speed : USB_SPEED_HIGH;
1229
1230 /* See how many bytes are in the periodic FIFO right now */
1231 fifo_space = (dwc2_readl(hsotg->regs + HPTXSTS) &
1232 TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT;
1233 bytes_in_fifo = sizeof(u32) *
1234 (hsotg->params.host_perio_tx_fifo_size -
1235 fifo_space);
1236
1237 /*
1238 * Roughly estimate bus time for everything in the periodic
1239 * queue + our new transfer. This is "rough" because we're
1240 * using a function that makes takes into account IN/OUT
1241 * and INT/ISO and we're just slamming in one value for all
1242 * transfers. This should be an over-estimate and that should
1243 * be OK, but we can probably tighten it.
1244 */
1245 xfer_ns = usb_calc_bus_time(host_speed, false, false,
1246 chan->xfer_len + bytes_in_fifo);
1247 xfer_us = NS_TO_US(xfer_ns);
1248
1249 /* See what frame number we'll be at by the time we finish */
1250 frame_number = dwc2_hcd_get_future_frame_number(hsotg, xfer_us);
1251
1252 /* This is when we were scheduled to be on the wire */
1253 wire_frame = dwc2_frame_num_inc(chan->qh->next_active_frame, 1);
1254
1255 /*
1256 * If we'd finish _after_ the frame we're scheduled in then
1257 * it's hopeless. Just schedule right away and hope for the
1258 * best. Note that it _might_ be wise to call back into the
1259 * scheduler to pick a better frame, but this is better than
1260 * nothing.
1261 */
1262 if (dwc2_frame_num_gt(frame_number, wire_frame)) {
1263 dwc2_sch_vdbg(hsotg,
1264 "QH=%p EO MISS fr=%04x=>%04x (%+d)\n",
1265 chan->qh, wire_frame, frame_number,
1266 dwc2_frame_num_dec(frame_number,
1267 wire_frame));
1268 wire_frame = frame_number;
1269
1270 /*
1271 * We picked a different frame number; communicate this
1272 * back to the scheduler so it doesn't try to schedule
1273 * another in the same frame.
1274 *
1275 * Remember that next_active_frame is 1 before the wire
1276 * frame.
1277 */
1278 chan->qh->next_active_frame =
1279 dwc2_frame_num_dec(frame_number, 1);
1280 }
1281
1282 if (wire_frame & 1)
1283 *hcchar |= HCCHAR_ODDFRM;
1284 else
1285 *hcchar &= ~HCCHAR_ODDFRM;
1286 }
1287}
1288
1289static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan)
1290{
1291 /* Set up the initial PID for the transfer */
1292 if (chan->speed == USB_SPEED_HIGH) {
1293 if (chan->ep_is_in) {
1294 if (chan->multi_count == 1)
1295 chan->data_pid_start = DWC2_HC_PID_DATA0;
1296 else if (chan->multi_count == 2)
1297 chan->data_pid_start = DWC2_HC_PID_DATA1;
1298 else
1299 chan->data_pid_start = DWC2_HC_PID_DATA2;
1300 } else {
1301 if (chan->multi_count == 1)
1302 chan->data_pid_start = DWC2_HC_PID_DATA0;
1303 else
1304 chan->data_pid_start = DWC2_HC_PID_MDATA;
1305 }
1306 } else {
1307 chan->data_pid_start = DWC2_HC_PID_DATA0;
1308 }
1309}
1310
1311/**
1312 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
1313 * the Host Channel
1314 *
1315 * @hsotg: Programming view of DWC_otg controller
1316 * @chan: Information needed to initialize the host channel
1317 *
1318 * This function should only be called in Slave mode. For a channel associated
1319 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1320 * associated with a periodic EP, the periodic Tx FIFO is written.
1321 *
1322 * Upon return the xfer_buf and xfer_count fields in chan are incremented by
1323 * the number of bytes written to the Tx FIFO.
1324 */
1325static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1326 struct dwc2_host_chan *chan)
1327{
1328 u32 i;
1329 u32 remaining_count;
1330 u32 byte_count;
1331 u32 dword_count;
1332 u32 __iomem *data_fifo;
1333 u32 *data_buf = (u32 *)chan->xfer_buf;
1334
1335 if (dbg_hc(chan))
1336 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1337
1338 data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num));
1339
1340 remaining_count = chan->xfer_len - chan->xfer_count;
1341 if (remaining_count > chan->max_packet)
1342 byte_count = chan->max_packet;
1343 else
1344 byte_count = remaining_count;
1345
1346 dword_count = (byte_count + 3) / 4;
1347
1348 if (((unsigned long)data_buf & 0x3) == 0) {
1349 /* xfer_buf is DWORD aligned */
1350 for (i = 0; i < dword_count; i++, data_buf++)
1351 dwc2_writel(*data_buf, data_fifo);
1352 } else {
1353 /* xfer_buf is not DWORD aligned */
1354 for (i = 0; i < dword_count; i++, data_buf++) {
1355 u32 data = data_buf[0] | data_buf[1] << 8 |
1356 data_buf[2] << 16 | data_buf[3] << 24;
1357 dwc2_writel(data, data_fifo);
1358 }
1359 }
1360
1361 chan->xfer_count += byte_count;
1362 chan->xfer_buf += byte_count;
1363}
1364
1365/**
1366 * dwc2_hc_do_ping() - Starts a PING transfer
1367 *
1368 * @hsotg: Programming view of DWC_otg controller
1369 * @chan: Information needed to initialize the host channel
1370 *
1371 * This function should only be called in Slave mode. The Do Ping bit is set in
1372 * the HCTSIZ register, then the channel is enabled.
1373 */
1374static void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg,
1375 struct dwc2_host_chan *chan)
1376{
1377 u32 hcchar;
1378 u32 hctsiz;
1379
1380 if (dbg_hc(chan))
1381 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1382 chan->hc_num);
1383
1384 hctsiz = TSIZ_DOPNG;
1385 hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
1386 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1387
1388 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1389 hcchar |= HCCHAR_CHENA;
1390 hcchar &= ~HCCHAR_CHDIS;
1391 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1392}
1393
1394/**
1395 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1396 * channel and starts the transfer
1397 *
1398 * @hsotg: Programming view of DWC_otg controller
1399 * @chan: Information needed to initialize the host channel. The xfer_len value
1400 * may be reduced to accommodate the max widths of the XferSize and
1401 * PktCnt fields in the HCTSIZn register. The multi_count value may be
1402 * changed to reflect the final xfer_len value.
1403 *
1404 * This function may be called in either Slave mode or DMA mode. In Slave mode,
1405 * the caller must ensure that there is sufficient space in the request queue
1406 * and Tx Data FIFO.
1407 *
1408 * For an OUT transfer in Slave mode, it loads a data packet into the
1409 * appropriate FIFO. If necessary, additional data packets are loaded in the
1410 * Host ISR.
1411 *
1412 * For an IN transfer in Slave mode, a data packet is requested. The data
1413 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
1414 * additional data packets are requested in the Host ISR.
1415 *
1416 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1417 * register along with a packet count of 1 and the channel is enabled. This
1418 * causes a single PING transaction to occur. Other fields in HCTSIZ are
1419 * simply set to 0 since no data transfer occurs in this case.
1420 *
1421 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1422 * all the information required to perform the subsequent data transfer. In
1423 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
1424 * controller performs the entire PING protocol, then starts the data
1425 * transfer.
1426 */
1427static void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1428 struct dwc2_host_chan *chan)
1429{
1430 u32 max_hc_xfer_size = hsotg->params.max_transfer_size;
1431 u16 max_hc_pkt_count = hsotg->params.max_packet_count;
1432 u32 hcchar;
1433 u32 hctsiz = 0;
1434 u16 num_packets;
1435 u32 ec_mc;
1436
1437 if (dbg_hc(chan))
1438 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1439
1440 if (chan->do_ping) {
1441 if (!hsotg->params.host_dma) {
1442 if (dbg_hc(chan))
1443 dev_vdbg(hsotg->dev, "ping, no DMA\n");
1444 dwc2_hc_do_ping(hsotg, chan);
1445 chan->xfer_started = 1;
1446 return;
1447 }
1448
1449 if (dbg_hc(chan))
1450 dev_vdbg(hsotg->dev, "ping, DMA\n");
1451
1452 hctsiz |= TSIZ_DOPNG;
1453 }
1454
1455 if (chan->do_split) {
1456 if (dbg_hc(chan))
1457 dev_vdbg(hsotg->dev, "split\n");
1458 num_packets = 1;
1459
1460 if (chan->complete_split && !chan->ep_is_in)
1461 /*
1462 * For CSPLIT OUT Transfer, set the size to 0 so the
1463 * core doesn't expect any data written to the FIFO
1464 */
1465 chan->xfer_len = 0;
1466 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet)
1467 chan->xfer_len = chan->max_packet;
1468 else if (!chan->ep_is_in && chan->xfer_len > 188)
1469 chan->xfer_len = 188;
1470
1471 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1472 TSIZ_XFERSIZE_MASK;
1473
1474 /* For split set ec_mc for immediate retries */
1475 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1476 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1477 ec_mc = 3;
1478 else
1479 ec_mc = 1;
1480 } else {
1481 if (dbg_hc(chan))
1482 dev_vdbg(hsotg->dev, "no split\n");
1483 /*
1484 * Ensure that the transfer length and packet count will fit
1485 * in the widths allocated for them in the HCTSIZn register
1486 */
1487 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1488 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1489 /*
1490 * Make sure the transfer size is no larger than one
1491 * (micro)frame's worth of data. (A check was done
1492 * when the periodic transfer was accepted to ensure
1493 * that a (micro)frame's worth of data can be
1494 * programmed into a channel.)
1495 */
1496 u32 max_periodic_len =
1497 chan->multi_count * chan->max_packet;
1498
1499 if (chan->xfer_len > max_periodic_len)
1500 chan->xfer_len = max_periodic_len;
1501 } else if (chan->xfer_len > max_hc_xfer_size) {
1502 /*
1503 * Make sure that xfer_len is a multiple of max packet
1504 * size
1505 */
1506 chan->xfer_len =
1507 max_hc_xfer_size - chan->max_packet + 1;
1508 }
1509
1510 if (chan->xfer_len > 0) {
1511 num_packets = (chan->xfer_len + chan->max_packet - 1) /
1512 chan->max_packet;
1513 if (num_packets > max_hc_pkt_count) {
1514 num_packets = max_hc_pkt_count;
1515 chan->xfer_len = num_packets * chan->max_packet;
1516 }
1517 } else {
1518 /* Need 1 packet for transfer length of 0 */
1519 num_packets = 1;
1520 }
1521
1522 if (chan->ep_is_in)
1523 /*
1524 * Always program an integral # of max packets for IN
1525 * transfers
1526 */
1527 chan->xfer_len = num_packets * chan->max_packet;
1528
1529 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1530 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1531 /*
1532 * Make sure that the multi_count field matches the
1533 * actual transfer length
1534 */
1535 chan->multi_count = num_packets;
1536
1537 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1538 dwc2_set_pid_isoc(chan);
1539
1540 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1541 TSIZ_XFERSIZE_MASK;
1542
1543 /* The ec_mc gets the multi_count for non-split */
1544 ec_mc = chan->multi_count;
1545 }
1546
1547 chan->start_pkt_count = num_packets;
1548 hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
1549 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1550 TSIZ_SC_MC_PID_MASK;
1551 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1552 if (dbg_hc(chan)) {
1553 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1554 hctsiz, chan->hc_num);
1555
1556 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1557 chan->hc_num);
1558 dev_vdbg(hsotg->dev, " Xfer Size: %d\n",
1559 (hctsiz & TSIZ_XFERSIZE_MASK) >>
1560 TSIZ_XFERSIZE_SHIFT);
1561 dev_vdbg(hsotg->dev, " Num Pkts: %d\n",
1562 (hctsiz & TSIZ_PKTCNT_MASK) >>
1563 TSIZ_PKTCNT_SHIFT);
1564 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1565 (hctsiz & TSIZ_SC_MC_PID_MASK) >>
1566 TSIZ_SC_MC_PID_SHIFT);
1567 }
1568
1569 if (hsotg->params.host_dma) {
1570 dwc2_writel((u32)chan->xfer_dma,
1571 hsotg->regs + HCDMA(chan->hc_num));
1572 if (dbg_hc(chan))
1573 dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
1574 (unsigned long)chan->xfer_dma, chan->hc_num);
1575 }
1576
1577 /* Start the split */
1578 if (chan->do_split) {
1579 u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
1580
1581 hcsplt |= HCSPLT_SPLTENA;
1582 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num));
1583 }
1584
1585 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1586 hcchar &= ~HCCHAR_MULTICNT_MASK;
1587 hcchar |= (ec_mc << HCCHAR_MULTICNT_SHIFT) & HCCHAR_MULTICNT_MASK;
1588 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1589
1590 if (hcchar & HCCHAR_CHDIS)
1591 dev_warn(hsotg->dev,
1592 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1593 __func__, chan->hc_num, hcchar);
1594
1595 /* Set host channel enable after all other setup is complete */
1596 hcchar |= HCCHAR_CHENA;
1597 hcchar &= ~HCCHAR_CHDIS;
1598
1599 if (dbg_hc(chan))
1600 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1601 (hcchar & HCCHAR_MULTICNT_MASK) >>
1602 HCCHAR_MULTICNT_SHIFT);
1603
1604 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1605 if (dbg_hc(chan))
1606 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1607 chan->hc_num);
1608
1609 chan->xfer_started = 1;
1610 chan->requests++;
1611
1612 if (!hsotg->params.host_dma &&
1613 !chan->ep_is_in && chan->xfer_len > 0)
1614 /* Load OUT packet into the appropriate Tx FIFO */
1615 dwc2_hc_write_packet(hsotg, chan);
1616}
1617
1618/**
1619 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
1620 * host channel and starts the transfer in Descriptor DMA mode
1621 *
1622 * @hsotg: Programming view of DWC_otg controller
1623 * @chan: Information needed to initialize the host channel
1624 *
1625 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
1626 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field
1627 * with micro-frame bitmap.
1628 *
1629 * Initializes HCDMA register with descriptor list address and CTD value then
1630 * starts the transfer via enabling the channel.
1631 */
1632void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1633 struct dwc2_host_chan *chan)
1634{
1635 u32 hcchar;
1636 u32 hctsiz = 0;
1637
1638 if (chan->do_ping)
1639 hctsiz |= TSIZ_DOPNG;
1640
1641 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1642 dwc2_set_pid_isoc(chan);
1643
1644 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
1645 hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1646 TSIZ_SC_MC_PID_MASK;
1647
1648 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
1649 hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK;
1650
1651 /* Non-zero only for high-speed interrupt endpoints */
1652 hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;
1653
1654 if (dbg_hc(chan)) {
1655 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1656 chan->hc_num);
1657 dev_vdbg(hsotg->dev, " Start PID: %d\n",
1658 chan->data_pid_start);
1659 dev_vdbg(hsotg->dev, " NTD: %d\n", chan->ntd - 1);
1660 }
1661
1662 dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1663
1664 dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr,
1665 chan->desc_list_sz, DMA_TO_DEVICE);
1666
1667 dwc2_writel(chan->desc_list_addr, hsotg->regs + HCDMA(chan->hc_num));
1668
1669 if (dbg_hc(chan))
1670 dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n",
1671 &chan->desc_list_addr, chan->hc_num);
1672
1673 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1674 hcchar &= ~HCCHAR_MULTICNT_MASK;
1675 hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1676 HCCHAR_MULTICNT_MASK;
1677
1678 if (hcchar & HCCHAR_CHDIS)
1679 dev_warn(hsotg->dev,
1680 "%s: chdis set, channel %d, hcchar 0x%08x\n",
1681 __func__, chan->hc_num, hcchar);
1682
1683 /* Set host channel enable after all other setup is complete */
1684 hcchar |= HCCHAR_CHENA;
1685 hcchar &= ~HCCHAR_CHDIS;
1686
1687 if (dbg_hc(chan))
1688 dev_vdbg(hsotg->dev, " Multi Cnt: %d\n",
1689 (hcchar & HCCHAR_MULTICNT_MASK) >>
1690 HCCHAR_MULTICNT_SHIFT);
1691
1692 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1693 if (dbg_hc(chan))
1694 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1695 chan->hc_num);
1696
1697 chan->xfer_started = 1;
1698 chan->requests++;
1699}
1700
1701/**
1702 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
1703 * a previous call to dwc2_hc_start_transfer()
1704 *
1705 * @hsotg: Programming view of DWC_otg controller
1706 * @chan: Information needed to initialize the host channel
1707 *
1708 * The caller must ensure there is sufficient space in the request queue and Tx
1709 * Data FIFO. This function should only be called in Slave mode. In DMA mode,
1710 * the controller acts autonomously to complete transfers programmed to a host
1711 * channel.
1712 *
1713 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
1714 * if there is any data remaining to be queued. For an IN transfer, another
1715 * data packet is always requested. For the SETUP phase of a control transfer,
1716 * this function does nothing.
1717 *
1718 * Return: 1 if a new request is queued, 0 if no more requests are required
1719 * for this transfer
1720 */
1721static int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
1722 struct dwc2_host_chan *chan)
1723{
1724 if (dbg_hc(chan))
1725 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1726 chan->hc_num);
1727
1728 if (chan->do_split)
1729 /* SPLITs always queue just once per channel */
1730 return 0;
1731
1732 if (chan->data_pid_start == DWC2_HC_PID_SETUP)
1733 /* SETUPs are queued only once since they can't be NAK'd */
1734 return 0;
1735
1736 if (chan->ep_is_in) {
1737 /*
1738 * Always queue another request for other IN transfers. If
1739 * back-to-back INs are issued and NAKs are received for both,
1740 * the driver may still be processing the first NAK when the
1741 * second NAK is received. When the interrupt handler clears
1742 * the NAK interrupt for the first NAK, the second NAK will
1743 * not be seen. So we can't depend on the NAK interrupt
1744 * handler to requeue a NAK'd request. Instead, IN requests
1745 * are issued each time this function is called. When the
1746 * transfer completes, the extra requests for the channel will
1747 * be flushed.
1748 */
1749 u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1750
1751 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1752 hcchar |= HCCHAR_CHENA;
1753 hcchar &= ~HCCHAR_CHDIS;
1754 if (dbg_hc(chan))
1755 dev_vdbg(hsotg->dev, " IN xfer: hcchar = 0x%08x\n",
1756 hcchar);
1757 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1758 chan->requests++;
1759 return 1;
1760 }
1761
1762 /* OUT transfers */
1763
1764 if (chan->xfer_count < chan->xfer_len) {
1765 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1766 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1767 u32 hcchar = dwc2_readl(hsotg->regs +
1768 HCCHAR(chan->hc_num));
1769
1770 dwc2_hc_set_even_odd_frame(hsotg, chan,
1771 &hcchar);
1772 }
1773
1774 /* Load OUT packet into the appropriate Tx FIFO */
1775 dwc2_hc_write_packet(hsotg, chan);
1776 chan->requests++;
1777 return 1;
1778 }
1779
1780 return 0;
1781}
1782
1783/*
1784 * =========================================================================
1785 * HCD
1786 * =========================================================================
1787 */
1788
1789/*
1790 * Processes all the URBs in a single list of QHs. Completes them with
1791 * -ETIMEDOUT and frees the QTD.
1792 *
1793 * Must be called with interrupt disabled and spinlock held
1794 */
1795static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
1796 struct list_head *qh_list)
1797{
1798 struct dwc2_qh *qh, *qh_tmp;
1799 struct dwc2_qtd *qtd, *qtd_tmp;
1800
1801 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1802 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1803 qtd_list_entry) {
1804 dwc2_host_complete(hsotg, qtd, -ECONNRESET);
1805 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1806 }
1807 }
1808}
1809
1810static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
1811 struct list_head *qh_list)
1812{
1813 struct dwc2_qtd *qtd, *qtd_tmp;
1814 struct dwc2_qh *qh, *qh_tmp;
1815 unsigned long flags;
1816
1817 if (!qh_list->next)
1818 /* The list hasn't been initialized yet */
1819 return;
1820
1821 spin_lock_irqsave(&hsotg->lock, flags);
1822
1823 /* Ensure there are no QTDs or URBs left */
1824 dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
1825
1826 list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
1827 dwc2_hcd_qh_unlink(hsotg, qh);
1828
1829 /* Free each QTD in the QH's QTD list */
1830 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
1831 qtd_list_entry)
1832 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
1833
1834 if (qh->channel && qh->channel->qh == qh)
1835 qh->channel->qh = NULL;
1836
1837 spin_unlock_irqrestore(&hsotg->lock, flags);
1838 dwc2_hcd_qh_free(hsotg, qh);
1839 spin_lock_irqsave(&hsotg->lock, flags);
1840 }
1841
1842 spin_unlock_irqrestore(&hsotg->lock, flags);
1843}
1844
1845/*
1846 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
1847 * and periodic schedules. The QTD associated with each URB is removed from
1848 * the schedule and freed. This function may be called when a disconnect is
1849 * detected or when the HCD is being stopped.
1850 *
1851 * Must be called with interrupt disabled and spinlock held
1852 */
1853static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
1854{
1855 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
1856 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_waiting);
1857 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
1858 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
1859 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
1860 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
1861 dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
1862}
1863
1864/**
1865 * dwc2_hcd_start() - Starts the HCD when switching to Host mode
1866 *
1867 * @hsotg: Pointer to struct dwc2_hsotg
1868 */
1869void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
1870{
1871 u32 hprt0;
1872
1873 if (hsotg->op_state == OTG_STATE_B_HOST) {
1874 /*
1875 * Reset the port. During a HNP mode switch the reset
1876 * needs to occur within 1ms and have a duration of at
1877 * least 50ms.
1878 */
1879 hprt0 = dwc2_read_hprt0(hsotg);
1880 hprt0 |= HPRT0_RST;
1881 dwc2_writel(hprt0, hsotg->regs + HPRT0);
1882 }
1883
1884 queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
1885 msecs_to_jiffies(50));
1886}
1887
1888/* Must be called with interrupt disabled and spinlock held */
1889static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
1890{
1891 int num_channels = hsotg->params.host_channels;
1892 struct dwc2_host_chan *channel;
1893 u32 hcchar;
1894 int i;
1895
1896 if (!hsotg->params.host_dma) {
1897 /* Flush out any channel requests in slave mode */
1898 for (i = 0; i < num_channels; i++) {
1899 channel = hsotg->hc_ptr_array[i];
1900 if (!list_empty(&channel->hc_list_entry))
1901 continue;
1902 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1903 if (hcchar & HCCHAR_CHENA) {
1904 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
1905 hcchar |= HCCHAR_CHDIS;
1906 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1907 }
1908 }
1909 }
1910
1911 for (i = 0; i < num_channels; i++) {
1912 channel = hsotg->hc_ptr_array[i];
1913 if (!list_empty(&channel->hc_list_entry))
1914 continue;
1915 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1916 if (hcchar & HCCHAR_CHENA) {
1917 /* Halt the channel */
1918 hcchar |= HCCHAR_CHDIS;
1919 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1920 }
1921
1922 dwc2_hc_cleanup(hsotg, channel);
1923 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
1924 /*
1925 * Added for Descriptor DMA to prevent channel double cleanup in
1926 * release_channel_ddma(), which is called from ep_disable when
1927 * device disconnects
1928 */
1929 channel->qh = NULL;
1930 }
1931 /* All channels have been freed, mark them available */
1932 if (hsotg->params.uframe_sched) {
1933 hsotg->available_host_channels =
1934 hsotg->params.host_channels;
1935 } else {
1936 hsotg->non_periodic_channels = 0;
1937 hsotg->periodic_channels = 0;
1938 }
1939}
1940
1941/**
1942 * dwc2_hcd_connect() - Handles connect of the HCD
1943 *
1944 * @hsotg: Pointer to struct dwc2_hsotg
1945 *
1946 * Must be called with interrupt disabled and spinlock held
1947 */
1948void dwc2_hcd_connect(struct dwc2_hsotg *hsotg)
1949{
1950 if (hsotg->lx_state != DWC2_L0)
1951 usb_hcd_resume_root_hub(hsotg->priv);
1952
1953 hsotg->flags.b.port_connect_status_change = 1;
1954 hsotg->flags.b.port_connect_status = 1;
1955}
1956
1957/**
1958 * dwc2_hcd_disconnect() - Handles disconnect of the HCD
1959 *
1960 * @hsotg: Pointer to struct dwc2_hsotg
1961 * @force: If true, we won't try to reconnect even if we see device connected.
1962 *
1963 * Must be called with interrupt disabled and spinlock held
1964 */
1965void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force)
1966{
1967 u32 intr;
1968 u32 hprt0;
1969
1970 /* Set status flags for the hub driver */
1971 hsotg->flags.b.port_connect_status_change = 1;
1972 hsotg->flags.b.port_connect_status = 0;
1973
1974 /*
1975 * Shutdown any transfers in process by clearing the Tx FIFO Empty
1976 * interrupt mask and status bits and disabling subsequent host
1977 * channel interrupts.
1978 */
1979 intr = dwc2_readl(hsotg->regs + GINTMSK);
1980 intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
1981 dwc2_writel(intr, hsotg->regs + GINTMSK);
1982 intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
1983 dwc2_writel(intr, hsotg->regs + GINTSTS);
1984
1985 /*
1986 * Turn off the vbus power only if the core has transitioned to device
1987 * mode. If still in host mode, need to keep power on to detect a
1988 * reconnection.
1989 */
1990 if (dwc2_is_device_mode(hsotg)) {
1991 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
1992 dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
1993 dwc2_writel(0, hsotg->regs + HPRT0);
1994 }
1995
1996 dwc2_disable_host_interrupts(hsotg);
1997 }
1998
1999 /* Respond with an error status to all URBs in the schedule */
2000 dwc2_kill_all_urbs(hsotg);
2001
2002 if (dwc2_is_host_mode(hsotg))
2003 /* Clean up any host channels that were in use */
2004 dwc2_hcd_cleanup_channels(hsotg);
2005
2006 dwc2_host_disconnect(hsotg);
2007
2008 /*
2009 * Add an extra check here to see if we're actually connected but
2010 * we don't have a detection interrupt pending. This can happen if:
2011 * 1. hardware sees connect
2012 * 2. hardware sees disconnect
2013 * 3. hardware sees connect
2014 * 4. dwc2_port_intr() - clears connect interrupt
2015 * 5. dwc2_handle_common_intr() - calls here
2016 *
2017 * Without the extra check here we will end calling disconnect
2018 * and won't get any future interrupts to handle the connect.
2019 */
2020 if (!force) {
2021 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
2022 if (!(hprt0 & HPRT0_CONNDET) && (hprt0 & HPRT0_CONNSTS))
2023 dwc2_hcd_connect(hsotg);
2024 }
2025}
2026
2027/**
2028 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
2029 *
2030 * @hsotg: Pointer to struct dwc2_hsotg
2031 */
2032static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
2033{
2034 if (hsotg->bus_suspended) {
2035 hsotg->flags.b.port_suspend_change = 1;
2036 usb_hcd_resume_root_hub(hsotg->priv);
2037 }
2038
2039 if (hsotg->lx_state == DWC2_L1)
2040 hsotg->flags.b.port_l1_change = 1;
2041}
2042
2043/**
2044 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
2045 *
2046 * @hsotg: Pointer to struct dwc2_hsotg
2047 *
2048 * Must be called with interrupt disabled and spinlock held
2049 */
2050void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
2051{
2052 dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
2053
2054 /*
2055 * The root hub should be disconnected before this function is called.
2056 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
2057 * and the QH lists (via ..._hcd_endpoint_disable).
2058 */
2059
2060 /* Turn off all host-specific interrupts */
2061 dwc2_disable_host_interrupts(hsotg);
2062
2063 /* Turn off the vbus power */
2064 dev_dbg(hsotg->dev, "PortPower off\n");
2065 dwc2_writel(0, hsotg->regs + HPRT0);
2066}
2067
2068/* Caller must hold driver lock */
2069static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
2070 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh,
2071 struct dwc2_qtd *qtd)
2072{
2073 u32 intr_mask;
2074 int retval;
2075 int dev_speed;
2076
2077 if (!hsotg->flags.b.port_connect_status) {
2078 /* No longer connected */
2079 dev_err(hsotg->dev, "Not connected\n");
2080 return -ENODEV;
2081 }
2082
2083 dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
2084
2085 /* Some configurations cannot support LS traffic on a FS root port */
2086 if ((dev_speed == USB_SPEED_LOW) &&
2087 (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
2088 (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
2089 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
2090 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
2091
2092 if (prtspd == HPRT0_SPD_FULL_SPEED)
2093 return -ENODEV;
2094 }
2095
2096 if (!qtd)
2097 return -EINVAL;
2098
2099 dwc2_hcd_qtd_init(qtd, urb);
2100 retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
2101 if (retval) {
2102 dev_err(hsotg->dev,
2103 "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
2104 retval);
2105 return retval;
2106 }
2107
2108 intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
2109 if (!(intr_mask & GINTSTS_SOF)) {
2110 enum dwc2_transaction_type tr_type;
2111
2112 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
2113 !(qtd->urb->flags & URB_GIVEBACK_ASAP))
2114 /*
2115 * Do not schedule SG transactions until qtd has
2116 * URB_GIVEBACK_ASAP set
2117 */
2118 return 0;
2119
2120 tr_type = dwc2_hcd_select_transactions(hsotg);
2121 if (tr_type != DWC2_TRANSACTION_NONE)
2122 dwc2_hcd_queue_transactions(hsotg, tr_type);
2123 }
2124
2125 return 0;
2126}
2127
2128/* Must be called with interrupt disabled and spinlock held */
2129static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
2130 struct dwc2_hcd_urb *urb)
2131{
2132 struct dwc2_qh *qh;
2133 struct dwc2_qtd *urb_qtd;
2134
2135 urb_qtd = urb->qtd;
2136 if (!urb_qtd) {
2137 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
2138 return -EINVAL;
2139 }
2140
2141 qh = urb_qtd->qh;
2142 if (!qh) {
2143 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
2144 return -EINVAL;
2145 }
2146
2147 urb->priv = NULL;
2148
2149 if (urb_qtd->in_process && qh->channel) {
2150 dwc2_dump_channel_info(hsotg, qh->channel);
2151
2152 /* The QTD is in process (it has been assigned to a channel) */
2153 if (hsotg->flags.b.port_connect_status)
2154 /*
2155 * If still connected (i.e. in host mode), halt the
2156 * channel so it can be used for other transfers. If
2157 * no longer connected, the host registers can't be
2158 * written to halt the channel since the core is in
2159 * device mode.
2160 */
2161 dwc2_hc_halt(hsotg, qh->channel,
2162 DWC2_HC_XFER_URB_DEQUEUE);
2163 }
2164
2165 /*
2166 * Free the QTD and clean up the associated QH. Leave the QH in the
2167 * schedule if it has any remaining QTDs.
2168 */
2169 if (!hsotg->params.dma_desc_enable) {
2170 u8 in_process = urb_qtd->in_process;
2171
2172 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
2173 if (in_process) {
2174 dwc2_hcd_qh_deactivate(hsotg, qh, 0);
2175 qh->channel = NULL;
2176 } else if (list_empty(&qh->qtd_list)) {
2177 dwc2_hcd_qh_unlink(hsotg, qh);
2178 }
2179 } else {
2180 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
2181 }
2182
2183 return 0;
2184}
2185
2186/* Must NOT be called with interrupt disabled or spinlock held */
2187static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
2188 struct usb_host_endpoint *ep, int retry)
2189{
2190 struct dwc2_qtd *qtd, *qtd_tmp;
2191 struct dwc2_qh *qh;
2192 unsigned long flags;
2193 int rc;
2194
2195 spin_lock_irqsave(&hsotg->lock, flags);
2196
2197 qh = ep->hcpriv;
2198 if (!qh) {
2199 rc = -EINVAL;
2200 goto err;
2201 }
2202
2203 while (!list_empty(&qh->qtd_list) && retry--) {
2204 if (retry == 0) {
2205 dev_err(hsotg->dev,
2206 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
2207 rc = -EBUSY;
2208 goto err;
2209 }
2210
2211 spin_unlock_irqrestore(&hsotg->lock, flags);
2212 msleep(20);
2213 spin_lock_irqsave(&hsotg->lock, flags);
2214 qh = ep->hcpriv;
2215 if (!qh) {
2216 rc = -EINVAL;
2217 goto err;
2218 }
2219 }
2220
2221 dwc2_hcd_qh_unlink(hsotg, qh);
2222
2223 /* Free each QTD in the QH's QTD list */
2224 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
2225 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
2226
2227 ep->hcpriv = NULL;
2228
2229 if (qh->channel && qh->channel->qh == qh)
2230 qh->channel->qh = NULL;
2231
2232 spin_unlock_irqrestore(&hsotg->lock, flags);
2233
2234 dwc2_hcd_qh_free(hsotg, qh);
2235
2236 return 0;
2237
2238err:
2239 ep->hcpriv = NULL;
2240 spin_unlock_irqrestore(&hsotg->lock, flags);
2241
2242 return rc;
2243}
2244
2245/* Must be called with interrupt disabled and spinlock held */
2246static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
2247 struct usb_host_endpoint *ep)
2248{
2249 struct dwc2_qh *qh = ep->hcpriv;
2250
2251 if (!qh)
2252 return -EINVAL;
2253
2254 qh->data_toggle = DWC2_HC_PID_DATA0;
2255
2256 return 0;
2257}
2258
2259/**
2260 * dwc2_core_init() - Initializes the DWC_otg controller registers and
2261 * prepares the core for device mode or host mode operation
2262 *
2263 * @hsotg: Programming view of the DWC_otg controller
2264 * @initial_setup: If true then this is the first init for this instance.
2265 */
2266int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
2267{
2268 u32 usbcfg, otgctl;
2269 int retval;
2270
2271 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2272
2273 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2274
2275 /* Set ULPI External VBUS bit if needed */
2276 usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
2277 if (hsotg->params.phy_ulpi_ext_vbus)
2278 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;
2279
2280 /* Set external TS Dline pulsing bit if needed */
2281 usbcfg &= ~GUSBCFG_TERMSELDLPULSE;
2282 if (hsotg->params.ts_dline)
2283 usbcfg |= GUSBCFG_TERMSELDLPULSE;
2284
2285 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
2286
2287 /*
2288 * Reset the Controller
2289 *
2290 * We only need to reset the controller if this is a re-init.
2291 * For the first init we know for sure that earlier code reset us (it
2292 * needed to in order to properly detect various parameters).
2293 */
2294 if (!initial_setup) {
2295 retval = dwc2_core_reset(hsotg, false);
2296 if (retval) {
2297 dev_err(hsotg->dev, "%s(): Reset failed, aborting\n",
2298 __func__);
2299 return retval;
2300 }
2301 }
2302
2303 /*
2304 * This needs to happen in FS mode before any other programming occurs
2305 */
2306 retval = dwc2_phy_init(hsotg, initial_setup);
2307 if (retval)
2308 return retval;
2309
2310 /* Program the GAHBCFG Register */
2311 retval = dwc2_gahbcfg_init(hsotg);
2312 if (retval)
2313 return retval;
2314
2315 /* Program the GUSBCFG register */
2316 dwc2_gusbcfg_init(hsotg);
2317
2318 /* Program the GOTGCTL register */
2319 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2320 otgctl &= ~GOTGCTL_OTGVER;
2321 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2322
2323 /* Clear the SRP success bit for FS-I2c */
2324 hsotg->srp_success = 0;
2325
2326 /* Enable common interrupts */
2327 dwc2_enable_common_interrupts(hsotg);
2328
2329 /*
2330 * Do device or host initialization based on mode during PCD and
2331 * HCD initialization
2332 */
2333 if (dwc2_is_host_mode(hsotg)) {
2334 dev_dbg(hsotg->dev, "Host Mode\n");
2335 hsotg->op_state = OTG_STATE_A_HOST;
2336 } else {
2337 dev_dbg(hsotg->dev, "Device Mode\n");
2338 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
2339 }
2340
2341 return 0;
2342}
2343
2344/**
2345 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
2346 * Host mode
2347 *
2348 * @hsotg: Programming view of DWC_otg controller
2349 *
2350 * This function flushes the Tx and Rx FIFOs and flushes any entries in the
2351 * request queues. Host channels are reset to ensure that they are ready for
2352 * performing transfers.
2353 */
2354static void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
2355{
2356 u32 hcfg, hfir, otgctl, usbcfg;
2357
2358 dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
2359
2360 /* Set HS/FS Timeout Calibration to 7 (max available value).
2361 * The number of PHY clocks that the application programs in
2362 * this field is added to the high/full speed interpacket timeout
2363 * duration in the core to account for any additional delays
2364 * introduced by the PHY. This can be required, because the delay
2365 * introduced by the PHY in generating the linestate condition
2366 * can vary from one PHY to another.
2367 */
2368 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2369 usbcfg |= GUSBCFG_TOUTCAL(7);
2370 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
2371
2372 /* Restart the Phy Clock */
2373 dwc2_writel(0, hsotg->regs + PCGCTL);
2374
2375 /* Initialize Host Configuration Register */
2376 dwc2_init_fs_ls_pclk_sel(hsotg);
2377 if (hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
2378 hsotg->params.speed == DWC2_SPEED_PARAM_LOW) {
2379 hcfg = dwc2_readl(hsotg->regs + HCFG);
2380 hcfg |= HCFG_FSLSSUPP;
2381 dwc2_writel(hcfg, hsotg->regs + HCFG);
2382 }
2383
2384 /*
2385 * This bit allows dynamic reloading of the HFIR register during
2386 * runtime. This bit needs to be programmed during initial configuration
2387 * and its value must not be changed during runtime.
2388 */
2389 if (hsotg->params.reload_ctl) {
2390 hfir = dwc2_readl(hsotg->regs + HFIR);
2391 hfir |= HFIR_RLDCTRL;
2392 dwc2_writel(hfir, hsotg->regs + HFIR);
2393 }
2394
2395 if (hsotg->params.dma_desc_enable) {
2396 u32 op_mode = hsotg->hw_params.op_mode;
2397
2398 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
2399 !hsotg->hw_params.dma_desc_enable ||
2400 op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
2401 op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
2402 op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
2403 dev_err(hsotg->dev,
2404 "Hardware does not support descriptor DMA mode -\n");
2405 dev_err(hsotg->dev,
2406 "falling back to buffer DMA mode.\n");
2407 hsotg->params.dma_desc_enable = false;
2408 } else {
2409 hcfg = dwc2_readl(hsotg->regs + HCFG);
2410 hcfg |= HCFG_DESCDMA;
2411 dwc2_writel(hcfg, hsotg->regs + HCFG);
2412 }
2413 }
2414
2415 /* Configure data FIFO sizes */
2416 dwc2_config_fifos(hsotg);
2417
2418 /* TODO - check this */
2419 /* Clear Host Set HNP Enable in the OTG Control Register */
2420 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2421 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2422 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2423
2424 /* Make sure the FIFOs are flushed */
2425 dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
2426 dwc2_flush_rx_fifo(hsotg);
2427
2428 /* Clear Host Set HNP Enable in the OTG Control Register */
2429 otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
2430 otgctl &= ~GOTGCTL_HSTSETHNPEN;
2431 dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
2432
2433 if (!hsotg->params.dma_desc_enable) {
2434 int num_channels, i;
2435 u32 hcchar;
2436
2437 /* Flush out any leftover queued requests */
2438 num_channels = hsotg->params.host_channels;
2439 for (i = 0; i < num_channels; i++) {
2440 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2441 hcchar &= ~HCCHAR_CHENA;
2442 hcchar |= HCCHAR_CHDIS;
2443 hcchar &= ~HCCHAR_EPDIR;
2444 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
2445 }
2446
2447 /* Halt all channels to put them into a known state */
2448 for (i = 0; i < num_channels; i++) {
2449 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2450 hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
2451 hcchar &= ~HCCHAR_EPDIR;
2452 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
2453 dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
2454 __func__, i);
2455
2456 if (dwc2_hsotg_wait_bit_clear(hsotg, HCCHAR(i),
2457 HCCHAR_CHENA, 1000)) {
2458 dev_warn(hsotg->dev, "Unable to clear enable on channel %d\n",
2459 i);
2460 }
2461 }
2462 }
2463
2464 /* Enable ACG feature in host mode, if supported */
2465 dwc2_enable_acg(hsotg);
2466
2467 /* Turn on the vbus power */
2468 dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
2469 if (hsotg->op_state == OTG_STATE_A_HOST) {
2470 u32 hprt0 = dwc2_read_hprt0(hsotg);
2471
2472 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
2473 !!(hprt0 & HPRT0_PWR));
2474 if (!(hprt0 & HPRT0_PWR)) {
2475 hprt0 |= HPRT0_PWR;
2476 dwc2_writel(hprt0, hsotg->regs + HPRT0);
2477 }
2478 }
2479
2480 dwc2_enable_host_interrupts(hsotg);
2481}
2482
2483/*
2484 * Initializes dynamic portions of the DWC_otg HCD state
2485 *
2486 * Must be called with interrupt disabled and spinlock held
2487 */
2488static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
2489{
2490 struct dwc2_host_chan *chan, *chan_tmp;
2491 int num_channels;
2492 int i;
2493
2494 hsotg->flags.d32 = 0;
2495 hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
2496
2497 if (hsotg->params.uframe_sched) {
2498 hsotg->available_host_channels =
2499 hsotg->params.host_channels;
2500 } else {
2501 hsotg->non_periodic_channels = 0;
2502 hsotg->periodic_channels = 0;
2503 }
2504
2505 /*
2506 * Put all channels in the free channel list and clean up channel
2507 * states
2508 */
2509 list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
2510 hc_list_entry)
2511 list_del_init(&chan->hc_list_entry);
2512
2513 num_channels = hsotg->params.host_channels;
2514 for (i = 0; i < num_channels; i++) {
2515 chan = hsotg->hc_ptr_array[i];
2516 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
2517 dwc2_hc_cleanup(hsotg, chan);
2518 }
2519
2520 /* Initialize the DWC core for host mode operation */
2521 dwc2_core_host_init(hsotg);
2522}
2523
2524static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
2525 struct dwc2_host_chan *chan,
2526 struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
2527{
2528 int hub_addr, hub_port;
2529
2530 chan->do_split = 1;
2531 chan->xact_pos = qtd->isoc_split_pos;
2532 chan->complete_split = qtd->complete_split;
2533 dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
2534 chan->hub_addr = (u8)hub_addr;
2535 chan->hub_port = (u8)hub_port;
2536}
2537
2538static void dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
2539 struct dwc2_host_chan *chan,
2540 struct dwc2_qtd *qtd)
2541{
2542 struct dwc2_hcd_urb *urb = qtd->urb;
2543 struct dwc2_hcd_iso_packet_desc *frame_desc;
2544
2545 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
2546 case USB_ENDPOINT_XFER_CONTROL:
2547 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
2548
2549 switch (qtd->control_phase) {
2550 case DWC2_CONTROL_SETUP:
2551 dev_vdbg(hsotg->dev, " Control setup transaction\n");
2552 chan->do_ping = 0;
2553 chan->ep_is_in = 0;
2554 chan->data_pid_start = DWC2_HC_PID_SETUP;
2555 if (hsotg->params.host_dma)
2556 chan->xfer_dma = urb->setup_dma;
2557 else
2558 chan->xfer_buf = urb->setup_packet;
2559 chan->xfer_len = 8;
2560 break;
2561
2562 case DWC2_CONTROL_DATA:
2563 dev_vdbg(hsotg->dev, " Control data transaction\n");
2564 chan->data_pid_start = qtd->data_toggle;
2565 break;
2566
2567 case DWC2_CONTROL_STATUS:
2568 /*
2569 * Direction is opposite of data direction or IN if no
2570 * data
2571 */
2572 dev_vdbg(hsotg->dev, " Control status transaction\n");
2573 if (urb->length == 0)
2574 chan->ep_is_in = 1;
2575 else
2576 chan->ep_is_in =
2577 dwc2_hcd_is_pipe_out(&urb->pipe_info);
2578 if (chan->ep_is_in)
2579 chan->do_ping = 0;
2580 chan->data_pid_start = DWC2_HC_PID_DATA1;
2581 chan->xfer_len = 0;
2582 if (hsotg->params.host_dma)
2583 chan->xfer_dma = hsotg->status_buf_dma;
2584 else
2585 chan->xfer_buf = hsotg->status_buf;
2586 break;
2587 }
2588 break;
2589
2590 case USB_ENDPOINT_XFER_BULK:
2591 chan->ep_type = USB_ENDPOINT_XFER_BULK;
2592 break;
2593
2594 case USB_ENDPOINT_XFER_INT:
2595 chan->ep_type = USB_ENDPOINT_XFER_INT;
2596 break;
2597
2598 case USB_ENDPOINT_XFER_ISOC:
2599 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
2600 if (hsotg->params.dma_desc_enable)
2601 break;
2602
2603 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
2604 frame_desc->status = 0;
2605
2606 if (hsotg->params.host_dma) {
2607 chan->xfer_dma = urb->dma;
2608 chan->xfer_dma += frame_desc->offset +
2609 qtd->isoc_split_offset;
2610 } else {
2611 chan->xfer_buf = urb->buf;
2612 chan->xfer_buf += frame_desc->offset +
2613 qtd->isoc_split_offset;
2614 }
2615
2616 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
2617
2618 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
2619 if (chan->xfer_len <= 188)
2620 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
2621 else
2622 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
2623 }
2624 break;
2625 }
2626}
2627
2628#define DWC2_USB_DMA_ALIGN 4
2629
2630struct dma_aligned_buffer {
2631 void *kmalloc_ptr;
2632 void *old_xfer_buffer;
2633 u8 data[0];
2634};
2635
2636static void dwc2_free_dma_aligned_buffer(struct urb *urb)
2637{
2638 struct dma_aligned_buffer *temp;
2639
2640 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
2641 return;
2642
2643 temp = container_of(urb->transfer_buffer,
2644 struct dma_aligned_buffer, data);
2645
2646 if (usb_urb_dir_in(urb))
2647 memcpy(temp->old_xfer_buffer, temp->data,
2648 urb->transfer_buffer_length);
2649 urb->transfer_buffer = temp->old_xfer_buffer;
2650 kfree(temp->kmalloc_ptr);
2651
2652 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
2653}
2654
2655static int dwc2_alloc_dma_aligned_buffer(struct urb *urb, gfp_t mem_flags)
2656{
2657 struct dma_aligned_buffer *temp, *kmalloc_ptr;
2658 size_t kmalloc_size;
2659
2660 if (urb->num_sgs || urb->sg ||
2661 urb->transfer_buffer_length == 0 ||
2662 !((uintptr_t)urb->transfer_buffer & (DWC2_USB_DMA_ALIGN - 1)))
2663 return 0;
2664
2665 /* Allocate a buffer with enough padding for alignment */
2666 kmalloc_size = urb->transfer_buffer_length +
2667 sizeof(struct dma_aligned_buffer) + DWC2_USB_DMA_ALIGN - 1;
2668
2669 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
2670 if (!kmalloc_ptr)
2671 return -ENOMEM;
2672
2673 /* Position our struct dma_aligned_buffer such that data is aligned */
2674 temp = PTR_ALIGN(kmalloc_ptr + 1, DWC2_USB_DMA_ALIGN) - 1;
2675 temp->kmalloc_ptr = kmalloc_ptr;
2676 temp->old_xfer_buffer = urb->transfer_buffer;
2677 if (usb_urb_dir_out(urb))
2678 memcpy(temp->data, urb->transfer_buffer,
2679 urb->transfer_buffer_length);
2680 urb->transfer_buffer = temp->data;
2681
2682 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
2683
2684 return 0;
2685}
2686
2687static int dwc2_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
2688 gfp_t mem_flags)
2689{
2690 int ret;
2691
2692 /* We assume setup_dma is always aligned; warn if not */
2693 WARN_ON_ONCE(urb->setup_dma &&
2694 (urb->setup_dma & (DWC2_USB_DMA_ALIGN - 1)));
2695
2696 ret = dwc2_alloc_dma_aligned_buffer(urb, mem_flags);
2697 if (ret)
2698 return ret;
2699
2700 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2701 if (ret)
2702 dwc2_free_dma_aligned_buffer(urb);
2703
2704 return ret;
2705}
2706
2707static void dwc2_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
2708{
2709 usb_hcd_unmap_urb_for_dma(hcd, urb);
2710 dwc2_free_dma_aligned_buffer(urb);
2711}
2712
2713/**
2714 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
2715 * channel and initializes the host channel to perform the transactions. The
2716 * host channel is removed from the free list.
2717 *
2718 * @hsotg: The HCD state structure
2719 * @qh: Transactions from the first QTD for this QH are selected and assigned
2720 * to a free host channel
2721 */
2722static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
2723{
2724 struct dwc2_host_chan *chan;
2725 struct dwc2_hcd_urb *urb;
2726 struct dwc2_qtd *qtd;
2727
2728 if (dbg_qh(qh))
2729 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
2730
2731 if (list_empty(&qh->qtd_list)) {
2732 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
2733 return -ENOMEM;
2734 }
2735
2736 if (list_empty(&hsotg->free_hc_list)) {
2737 dev_dbg(hsotg->dev, "No free channel to assign\n");
2738 return -ENOMEM;
2739 }
2740
2741 chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
2742 hc_list_entry);
2743
2744 /* Remove host channel from free list */
2745 list_del_init(&chan->hc_list_entry);
2746
2747 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
2748 urb = qtd->urb;
2749 qh->channel = chan;
2750 qtd->in_process = 1;
2751
2752 /*
2753 * Use usb_pipedevice to determine device address. This address is
2754 * 0 before the SET_ADDRESS command and the correct address afterward.
2755 */
2756 chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
2757 chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
2758 chan->speed = qh->dev_speed;
2759 chan->max_packet = dwc2_max_packet(qh->maxp);
2760
2761 chan->xfer_started = 0;
2762 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2763 chan->error_state = (qtd->error_count > 0);
2764 chan->halt_on_queue = 0;
2765 chan->halt_pending = 0;
2766 chan->requests = 0;
2767
2768 /*
2769 * The following values may be modified in the transfer type section
2770 * below. The xfer_len value may be reduced when the transfer is
2771 * started to accommodate the max widths of the XferSize and PktCnt
2772 * fields in the HCTSIZn register.
2773 */
2774
2775 chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
2776 if (chan->ep_is_in)
2777 chan->do_ping = 0;
2778 else
2779 chan->do_ping = qh->ping_state;
2780
2781 chan->data_pid_start = qh->data_toggle;
2782 chan->multi_count = 1;
2783
2784 if (urb->actual_length > urb->length &&
2785 !dwc2_hcd_is_pipe_in(&urb->pipe_info))
2786 urb->actual_length = urb->length;
2787
2788 if (hsotg->params.host_dma)
2789 chan->xfer_dma = urb->dma + urb->actual_length;
2790 else
2791 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
2792
2793 chan->xfer_len = urb->length - urb->actual_length;
2794 chan->xfer_count = 0;
2795
2796 /* Set the split attributes if required */
2797 if (qh->do_split)
2798 dwc2_hc_init_split(hsotg, chan, qtd, urb);
2799 else
2800 chan->do_split = 0;
2801
2802 /* Set the transfer attributes */
2803 dwc2_hc_init_xfer(hsotg, chan, qtd);
2804
2805 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
2806 chan->ep_type == USB_ENDPOINT_XFER_ISOC)
2807 /*
2808 * This value may be modified when the transfer is started
2809 * to reflect the actual transfer length
2810 */
2811 chan->multi_count = dwc2_hb_mult(qh->maxp);
2812
2813 if (hsotg->params.dma_desc_enable) {
2814 chan->desc_list_addr = qh->desc_list_dma;
2815 chan->desc_list_sz = qh->desc_list_sz;
2816 }
2817
2818 dwc2_hc_init(hsotg, chan);
2819 chan->qh = qh;
2820
2821 return 0;
2822}
2823
2824/**
2825 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
2826 * schedule and assigns them to available host channels. Called from the HCD
2827 * interrupt handler functions.
2828 *
2829 * @hsotg: The HCD state structure
2830 *
2831 * Return: The types of new transactions that were assigned to host channels
2832 */
2833enum dwc2_transaction_type dwc2_hcd_select_transactions(
2834 struct dwc2_hsotg *hsotg)
2835{
2836 enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
2837 struct list_head *qh_ptr;
2838 struct dwc2_qh *qh;
2839 int num_channels;
2840
2841#ifdef DWC2_DEBUG_SOF
2842 dev_vdbg(hsotg->dev, " Select Transactions\n");
2843#endif
2844
2845 /* Process entries in the periodic ready list */
2846 qh_ptr = hsotg->periodic_sched_ready.next;
2847 while (qh_ptr != &hsotg->periodic_sched_ready) {
2848 if (list_empty(&hsotg->free_hc_list))
2849 break;
2850 if (hsotg->params.uframe_sched) {
2851 if (hsotg->available_host_channels <= 1)
2852 break;
2853 hsotg->available_host_channels--;
2854 }
2855 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2856 if (dwc2_assign_and_init_hc(hsotg, qh))
2857 break;
2858
2859 /*
2860 * Move the QH from the periodic ready schedule to the
2861 * periodic assigned schedule
2862 */
2863 qh_ptr = qh_ptr->next;
2864 list_move_tail(&qh->qh_list_entry,
2865 &hsotg->periodic_sched_assigned);
2866 ret_val = DWC2_TRANSACTION_PERIODIC;
2867 }
2868
2869 /*
2870 * Process entries in the inactive portion of the non-periodic
2871 * schedule. Some free host channels may not be used if they are
2872 * reserved for periodic transfers.
2873 */
2874 num_channels = hsotg->params.host_channels;
2875 qh_ptr = hsotg->non_periodic_sched_inactive.next;
2876 while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
2877 if (!hsotg->params.uframe_sched &&
2878 hsotg->non_periodic_channels >= num_channels -
2879 hsotg->periodic_channels)
2880 break;
2881 if (list_empty(&hsotg->free_hc_list))
2882 break;
2883 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
2884 if (hsotg->params.uframe_sched) {
2885 if (hsotg->available_host_channels < 1)
2886 break;
2887 hsotg->available_host_channels--;
2888 }
2889
2890 if (dwc2_assign_and_init_hc(hsotg, qh))
2891 break;
2892
2893 /*
2894 * Move the QH from the non-periodic inactive schedule to the
2895 * non-periodic active schedule
2896 */
2897 qh_ptr = qh_ptr->next;
2898 list_move_tail(&qh->qh_list_entry,
2899 &hsotg->non_periodic_sched_active);
2900
2901 if (ret_val == DWC2_TRANSACTION_NONE)
2902 ret_val = DWC2_TRANSACTION_NON_PERIODIC;
2903 else
2904 ret_val = DWC2_TRANSACTION_ALL;
2905
2906 if (!hsotg->params.uframe_sched)
2907 hsotg->non_periodic_channels++;
2908 }
2909
2910 return ret_val;
2911}
2912
2913/**
2914 * dwc2_queue_transaction() - Attempts to queue a single transaction request for
2915 * a host channel associated with either a periodic or non-periodic transfer
2916 *
2917 * @hsotg: The HCD state structure
2918 * @chan: Host channel descriptor associated with either a periodic or
2919 * non-periodic transfer
2920 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
2921 * for periodic transfers or the non-periodic Tx FIFO
2922 * for non-periodic transfers
2923 *
2924 * Return: 1 if a request is queued and more requests may be needed to
2925 * complete the transfer, 0 if no more requests are required for this
2926 * transfer, -1 if there is insufficient space in the Tx FIFO
2927 *
2928 * This function assumes that there is space available in the appropriate
2929 * request queue. For an OUT transfer or SETUP transaction in Slave mode,
2930 * it checks whether space is available in the appropriate Tx FIFO.
2931 *
2932 * Must be called with interrupt disabled and spinlock held
2933 */
2934static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
2935 struct dwc2_host_chan *chan,
2936 u16 fifo_dwords_avail)
2937{
2938 int retval = 0;
2939
2940 if (chan->do_split)
2941 /* Put ourselves on the list to keep order straight */
2942 list_move_tail(&chan->split_order_list_entry,
2943 &hsotg->split_order);
2944
2945 if (hsotg->params.host_dma) {
2946 if (hsotg->params.dma_desc_enable) {
2947 if (!chan->xfer_started ||
2948 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
2949 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
2950 chan->qh->ping_state = 0;
2951 }
2952 } else if (!chan->xfer_started) {
2953 dwc2_hc_start_transfer(hsotg, chan);
2954 chan->qh->ping_state = 0;
2955 }
2956 } else if (chan->halt_pending) {
2957 /* Don't queue a request if the channel has been halted */
2958 } else if (chan->halt_on_queue) {
2959 dwc2_hc_halt(hsotg, chan, chan->halt_status);
2960 } else if (chan->do_ping) {
2961 if (!chan->xfer_started)
2962 dwc2_hc_start_transfer(hsotg, chan);
2963 } else if (!chan->ep_is_in ||
2964 chan->data_pid_start == DWC2_HC_PID_SETUP) {
2965 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
2966 if (!chan->xfer_started) {
2967 dwc2_hc_start_transfer(hsotg, chan);
2968 retval = 1;
2969 } else {
2970 retval = dwc2_hc_continue_transfer(hsotg, chan);
2971 }
2972 } else {
2973 retval = -1;
2974 }
2975 } else {
2976 if (!chan->xfer_started) {
2977 dwc2_hc_start_transfer(hsotg, chan);
2978 retval = 1;
2979 } else {
2980 retval = dwc2_hc_continue_transfer(hsotg, chan);
2981 }
2982 }
2983
2984 return retval;
2985}
2986
2987/*
2988 * Processes periodic channels for the next frame and queues transactions for
2989 * these channels to the DWC_otg controller. After queueing transactions, the
2990 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
2991 * to queue as Periodic Tx FIFO or request queue space becomes available.
2992 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
2993 *
2994 * Must be called with interrupt disabled and spinlock held
2995 */
2996static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
2997{
2998 struct list_head *qh_ptr;
2999 struct dwc2_qh *qh;
3000 u32 tx_status;
3001 u32 fspcavail;
3002 u32 gintmsk;
3003 int status;
3004 bool no_queue_space = false;
3005 bool no_fifo_space = false;
3006 u32 qspcavail;
3007
3008 /* If empty list then just adjust interrupt enables */
3009 if (list_empty(&hsotg->periodic_sched_assigned))
3010 goto exit;
3011
3012 if (dbg_perio())
3013 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
3014
3015 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
3016 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3017 TXSTS_QSPCAVAIL_SHIFT;
3018 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3019 TXSTS_FSPCAVAIL_SHIFT;
3020
3021 if (dbg_perio()) {
3022 dev_vdbg(hsotg->dev, " P Tx Req Queue Space Avail (before queue): %d\n",
3023 qspcavail);
3024 dev_vdbg(hsotg->dev, " P Tx FIFO Space Avail (before queue): %d\n",
3025 fspcavail);
3026 }
3027
3028 qh_ptr = hsotg->periodic_sched_assigned.next;
3029 while (qh_ptr != &hsotg->periodic_sched_assigned) {
3030 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
3031 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3032 TXSTS_QSPCAVAIL_SHIFT;
3033 if (qspcavail == 0) {
3034 no_queue_space = true;
3035 break;
3036 }
3037
3038 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
3039 if (!qh->channel) {
3040 qh_ptr = qh_ptr->next;
3041 continue;
3042 }
3043
3044 /* Make sure EP's TT buffer is clean before queueing qtds */
3045 if (qh->tt_buffer_dirty) {
3046 qh_ptr = qh_ptr->next;
3047 continue;
3048 }
3049
3050 /*
3051 * Set a flag if we're queuing high-bandwidth in slave mode.
3052 * The flag prevents any halts to get into the request queue in
3053 * the middle of multiple high-bandwidth packets getting queued.
3054 */
3055 if (!hsotg->params.host_dma &&
3056 qh->channel->multi_count > 1)
3057 hsotg->queuing_high_bandwidth = 1;
3058
3059 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3060 TXSTS_FSPCAVAIL_SHIFT;
3061 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3062 if (status < 0) {
3063 no_fifo_space = true;
3064 break;
3065 }
3066
3067 /*
3068 * In Slave mode, stay on the current transfer until there is
3069 * nothing more to do or the high-bandwidth request count is
3070 * reached. In DMA mode, only need to queue one request. The
3071 * controller automatically handles multiple packets for
3072 * high-bandwidth transfers.
3073 */
3074 if (hsotg->params.host_dma || status == 0 ||
3075 qh->channel->requests == qh->channel->multi_count) {
3076 qh_ptr = qh_ptr->next;
3077 /*
3078 * Move the QH from the periodic assigned schedule to
3079 * the periodic queued schedule
3080 */
3081 list_move_tail(&qh->qh_list_entry,
3082 &hsotg->periodic_sched_queued);
3083
3084 /* done queuing high bandwidth */
3085 hsotg->queuing_high_bandwidth = 0;
3086 }
3087 }
3088
3089exit:
3090 if (no_queue_space || no_fifo_space ||
3091 (!hsotg->params.host_dma &&
3092 !list_empty(&hsotg->periodic_sched_assigned))) {
3093 /*
3094 * May need to queue more transactions as the request
3095 * queue or Tx FIFO empties. Enable the periodic Tx
3096 * FIFO empty interrupt. (Always use the half-empty
3097 * level to ensure that new requests are loaded as
3098 * soon as possible.)
3099 */
3100 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3101 if (!(gintmsk & GINTSTS_PTXFEMP)) {
3102 gintmsk |= GINTSTS_PTXFEMP;
3103 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3104 }
3105 } else {
3106 /*
3107 * Disable the Tx FIFO empty interrupt since there are
3108 * no more transactions that need to be queued right
3109 * now. This function is called from interrupt
3110 * handlers to queue more transactions as transfer
3111 * states change.
3112 */
3113 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3114 if (gintmsk & GINTSTS_PTXFEMP) {
3115 gintmsk &= ~GINTSTS_PTXFEMP;
3116 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3117 }
3118 }
3119}
3120
3121/*
3122 * Processes active non-periodic channels and queues transactions for these
3123 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
3124 * FIFO Empty interrupt is enabled if there are more transactions to queue as
3125 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
3126 * FIFO Empty interrupt is disabled.
3127 *
3128 * Must be called with interrupt disabled and spinlock held
3129 */
3130static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
3131{
3132 struct list_head *orig_qh_ptr;
3133 struct dwc2_qh *qh;
3134 u32 tx_status;
3135 u32 qspcavail;
3136 u32 fspcavail;
3137 u32 gintmsk;
3138 int status;
3139 int no_queue_space = 0;
3140 int no_fifo_space = 0;
3141 int more_to_do = 0;
3142
3143 dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
3144
3145 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3146 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3147 TXSTS_QSPCAVAIL_SHIFT;
3148 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3149 TXSTS_FSPCAVAIL_SHIFT;
3150 dev_vdbg(hsotg->dev, " NP Tx Req Queue Space Avail (before queue): %d\n",
3151 qspcavail);
3152 dev_vdbg(hsotg->dev, " NP Tx FIFO Space Avail (before queue): %d\n",
3153 fspcavail);
3154
3155 /*
3156 * Keep track of the starting point. Skip over the start-of-list
3157 * entry.
3158 */
3159 if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
3160 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3161 orig_qh_ptr = hsotg->non_periodic_qh_ptr;
3162
3163 /*
3164 * Process once through the active list or until no more space is
3165 * available in the request queue or the Tx FIFO
3166 */
3167 do {
3168 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3169 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3170 TXSTS_QSPCAVAIL_SHIFT;
3171 if (!hsotg->params.host_dma && qspcavail == 0) {
3172 no_queue_space = 1;
3173 break;
3174 }
3175
3176 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
3177 qh_list_entry);
3178 if (!qh->channel)
3179 goto next;
3180
3181 /* Make sure EP's TT buffer is clean before queueing qtds */
3182 if (qh->tt_buffer_dirty)
3183 goto next;
3184
3185 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3186 TXSTS_FSPCAVAIL_SHIFT;
3187 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
3188
3189 if (status > 0) {
3190 more_to_do = 1;
3191 } else if (status < 0) {
3192 no_fifo_space = 1;
3193 break;
3194 }
3195next:
3196 /* Advance to next QH, skipping start-of-list entry */
3197 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
3198 if (hsotg->non_periodic_qh_ptr ==
3199 &hsotg->non_periodic_sched_active)
3200 hsotg->non_periodic_qh_ptr =
3201 hsotg->non_periodic_qh_ptr->next;
3202 } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
3203
3204 if (!hsotg->params.host_dma) {
3205 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
3206 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
3207 TXSTS_QSPCAVAIL_SHIFT;
3208 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
3209 TXSTS_FSPCAVAIL_SHIFT;
3210 dev_vdbg(hsotg->dev,
3211 " NP Tx Req Queue Space Avail (after queue): %d\n",
3212 qspcavail);
3213 dev_vdbg(hsotg->dev,
3214 " NP Tx FIFO Space Avail (after queue): %d\n",
3215 fspcavail);
3216
3217 if (more_to_do || no_queue_space || no_fifo_space) {
3218 /*
3219 * May need to queue more transactions as the request
3220 * queue or Tx FIFO empties. Enable the non-periodic
3221 * Tx FIFO empty interrupt. (Always use the half-empty
3222 * level to ensure that new requests are loaded as
3223 * soon as possible.)
3224 */
3225 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3226 gintmsk |= GINTSTS_NPTXFEMP;
3227 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3228 } else {
3229 /*
3230 * Disable the Tx FIFO empty interrupt since there are
3231 * no more transactions that need to be queued right
3232 * now. This function is called from interrupt
3233 * handlers to queue more transactions as transfer
3234 * states change.
3235 */
3236 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3237 gintmsk &= ~GINTSTS_NPTXFEMP;
3238 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3239 }
3240 }
3241}
3242
3243/**
3244 * dwc2_hcd_queue_transactions() - Processes the currently active host channels
3245 * and queues transactions for these channels to the DWC_otg controller. Called
3246 * from the HCD interrupt handler functions.
3247 *
3248 * @hsotg: The HCD state structure
3249 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
3250 * or both)
3251 *
3252 * Must be called with interrupt disabled and spinlock held
3253 */
3254void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
3255 enum dwc2_transaction_type tr_type)
3256{
3257#ifdef DWC2_DEBUG_SOF
3258 dev_vdbg(hsotg->dev, "Queue Transactions\n");
3259#endif
3260 /* Process host channels associated with periodic transfers */
3261 if (tr_type == DWC2_TRANSACTION_PERIODIC ||
3262 tr_type == DWC2_TRANSACTION_ALL)
3263 dwc2_process_periodic_channels(hsotg);
3264
3265 /* Process host channels associated with non-periodic transfers */
3266 if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
3267 tr_type == DWC2_TRANSACTION_ALL) {
3268 if (!list_empty(&hsotg->non_periodic_sched_active)) {
3269 dwc2_process_non_periodic_channels(hsotg);
3270 } else {
3271 /*
3272 * Ensure NP Tx FIFO empty interrupt is disabled when
3273 * there are no non-periodic transfers to process
3274 */
3275 u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
3276
3277 gintmsk &= ~GINTSTS_NPTXFEMP;
3278 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
3279 }
3280 }
3281}
3282
3283static void dwc2_conn_id_status_change(struct work_struct *work)
3284{
3285 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
3286 wf_otg);
3287 u32 count = 0;
3288 u32 gotgctl;
3289 unsigned long flags;
3290
3291 dev_dbg(hsotg->dev, "%s()\n", __func__);
3292
3293 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
3294 dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
3295 dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
3296 !!(gotgctl & GOTGCTL_CONID_B));
3297
3298 /* B-Device connector (Device Mode) */
3299 if (gotgctl & GOTGCTL_CONID_B) {
3300 dwc2_vbus_supply_exit(hsotg);
3301 /* Wait for switch to device mode */
3302 dev_dbg(hsotg->dev, "connId B\n");
3303 if (hsotg->bus_suspended) {
3304 dev_info(hsotg->dev,
3305 "Do port resume before switching to device mode\n");
3306 dwc2_port_resume(hsotg);
3307 }
3308 while (!dwc2_is_device_mode(hsotg)) {
3309 dev_info(hsotg->dev,
3310 "Waiting for Peripheral Mode, Mode=%s\n",
3311 dwc2_is_host_mode(hsotg) ? "Host" :
3312 "Peripheral");
3313 msleep(20);
3314 /*
3315 * Sometimes the initial GOTGCTRL read is wrong, so
3316 * check it again and jump to host mode if that was
3317 * the case.
3318 */
3319 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
3320 if (!(gotgctl & GOTGCTL_CONID_B))
3321 goto host;
3322 if (++count > 250)
3323 break;
3324 }
3325 if (count > 250)
3326 dev_err(hsotg->dev,
3327 "Connection id status change timed out\n");
3328 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
3329 dwc2_core_init(hsotg, false);
3330 dwc2_enable_global_interrupts(hsotg);
3331 spin_lock_irqsave(&hsotg->lock, flags);
3332 dwc2_hsotg_core_init_disconnected(hsotg, false);
3333 spin_unlock_irqrestore(&hsotg->lock, flags);
3334 /* Enable ACG feature in device mode,if supported */
3335 dwc2_enable_acg(hsotg);
3336 dwc2_hsotg_core_connect(hsotg);
3337 } else {
3338host:
3339 /* A-Device connector (Host Mode) */
3340 dev_dbg(hsotg->dev, "connId A\n");
3341 while (!dwc2_is_host_mode(hsotg)) {
3342 dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
3343 dwc2_is_host_mode(hsotg) ?
3344 "Host" : "Peripheral");
3345 msleep(20);
3346 if (++count > 250)
3347 break;
3348 }
3349 if (count > 250)
3350 dev_err(hsotg->dev,
3351 "Connection id status change timed out\n");
3352
3353 spin_lock_irqsave(&hsotg->lock, flags);
3354 dwc2_hsotg_disconnect(hsotg);
3355 spin_unlock_irqrestore(&hsotg->lock, flags);
3356
3357 hsotg->op_state = OTG_STATE_A_HOST;
3358 /* Initialize the Core for Host mode */
3359 dwc2_core_init(hsotg, false);
3360 dwc2_enable_global_interrupts(hsotg);
3361 dwc2_hcd_start(hsotg);
3362 }
3363}
3364
3365static void dwc2_wakeup_detected(struct timer_list *t)
3366{
3367 struct dwc2_hsotg *hsotg = from_timer(hsotg, t, wkp_timer);
3368 u32 hprt0;
3369
3370 dev_dbg(hsotg->dev, "%s()\n", __func__);
3371
3372 /*
3373 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
3374 * so that OPT tests pass with all PHYs.)
3375 */
3376 hprt0 = dwc2_read_hprt0(hsotg);
3377 dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
3378 hprt0 &= ~HPRT0_RES;
3379 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3380 dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
3381 dwc2_readl(hsotg->regs + HPRT0));
3382
3383 dwc2_hcd_rem_wakeup(hsotg);
3384 hsotg->bus_suspended = false;
3385
3386 /* Change to L0 state */
3387 hsotg->lx_state = DWC2_L0;
3388}
3389
3390static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
3391{
3392 struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
3393
3394 return hcd->self.b_hnp_enable;
3395}
3396
3397/* Must NOT be called with interrupt disabled or spinlock held */
3398static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
3399{
3400 unsigned long flags;
3401 u32 hprt0;
3402 u32 pcgctl;
3403 u32 gotgctl;
3404
3405 dev_dbg(hsotg->dev, "%s()\n", __func__);
3406
3407 spin_lock_irqsave(&hsotg->lock, flags);
3408
3409 if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
3410 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
3411 gotgctl |= GOTGCTL_HSTSETHNPEN;
3412 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
3413 hsotg->op_state = OTG_STATE_A_SUSPEND;
3414 }
3415
3416 hprt0 = dwc2_read_hprt0(hsotg);
3417 hprt0 |= HPRT0_SUSP;
3418 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3419
3420 hsotg->bus_suspended = true;
3421
3422 /*
3423 * If power_down is supported, Phy clock will be suspended
3424 * after registers are backuped.
3425 */
3426 if (!hsotg->params.power_down) {
3427 /* Suspend the Phy Clock */
3428 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3429 pcgctl |= PCGCTL_STOPPCLK;
3430 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3431 udelay(10);
3432 }
3433
3434 /* For HNP the bus must be suspended for at least 200ms */
3435 if (dwc2_host_is_b_hnp_enabled(hsotg)) {
3436 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3437 pcgctl &= ~PCGCTL_STOPPCLK;
3438 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3439
3440 spin_unlock_irqrestore(&hsotg->lock, flags);
3441
3442 msleep(200);
3443 } else {
3444 spin_unlock_irqrestore(&hsotg->lock, flags);
3445 }
3446}
3447
3448/* Must NOT be called with interrupt disabled or spinlock held */
3449static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
3450{
3451 unsigned long flags;
3452 u32 hprt0;
3453 u32 pcgctl;
3454
3455 spin_lock_irqsave(&hsotg->lock, flags);
3456
3457 /*
3458 * If power_down is supported, Phy clock is already resumed
3459 * after registers restore.
3460 */
3461 if (!hsotg->params.power_down) {
3462 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3463 pcgctl &= ~PCGCTL_STOPPCLK;
3464 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3465 spin_unlock_irqrestore(&hsotg->lock, flags);
3466 msleep(20);
3467 spin_lock_irqsave(&hsotg->lock, flags);
3468 }
3469
3470 hprt0 = dwc2_read_hprt0(hsotg);
3471 hprt0 |= HPRT0_RES;
3472 hprt0 &= ~HPRT0_SUSP;
3473 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3474 spin_unlock_irqrestore(&hsotg->lock, flags);
3475
3476 msleep(USB_RESUME_TIMEOUT);
3477
3478 spin_lock_irqsave(&hsotg->lock, flags);
3479 hprt0 = dwc2_read_hprt0(hsotg);
3480 hprt0 &= ~(HPRT0_RES | HPRT0_SUSP);
3481 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3482 hsotg->bus_suspended = false;
3483 spin_unlock_irqrestore(&hsotg->lock, flags);
3484}
3485
3486/* Handles hub class-specific requests */
3487static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
3488 u16 wvalue, u16 windex, char *buf, u16 wlength)
3489{
3490 struct usb_hub_descriptor *hub_desc;
3491 int retval = 0;
3492 u32 hprt0;
3493 u32 port_status;
3494 u32 speed;
3495 u32 pcgctl;
3496
3497 switch (typereq) {
3498 case ClearHubFeature:
3499 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
3500
3501 switch (wvalue) {
3502 case C_HUB_LOCAL_POWER:
3503 case C_HUB_OVER_CURRENT:
3504 /* Nothing required here */
3505 break;
3506
3507 default:
3508 retval = -EINVAL;
3509 dev_err(hsotg->dev,
3510 "ClearHubFeature request %1xh unknown\n",
3511 wvalue);
3512 }
3513 break;
3514
3515 case ClearPortFeature:
3516 if (wvalue != USB_PORT_FEAT_L1)
3517 if (!windex || windex > 1)
3518 goto error;
3519 switch (wvalue) {
3520 case USB_PORT_FEAT_ENABLE:
3521 dev_dbg(hsotg->dev,
3522 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
3523 hprt0 = dwc2_read_hprt0(hsotg);
3524 hprt0 |= HPRT0_ENA;
3525 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3526 break;
3527
3528 case USB_PORT_FEAT_SUSPEND:
3529 dev_dbg(hsotg->dev,
3530 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
3531
3532 if (hsotg->bus_suspended) {
3533 if (hsotg->hibernated)
3534 dwc2_exit_hibernation(hsotg, 0, 0, 1);
3535 else
3536 dwc2_port_resume(hsotg);
3537 }
3538 break;
3539
3540 case USB_PORT_FEAT_POWER:
3541 dev_dbg(hsotg->dev,
3542 "ClearPortFeature USB_PORT_FEAT_POWER\n");
3543 hprt0 = dwc2_read_hprt0(hsotg);
3544 hprt0 &= ~HPRT0_PWR;
3545 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3546 break;
3547
3548 case USB_PORT_FEAT_INDICATOR:
3549 dev_dbg(hsotg->dev,
3550 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
3551 /* Port indicator not supported */
3552 break;
3553
3554 case USB_PORT_FEAT_C_CONNECTION:
3555 /*
3556 * Clears driver's internal Connect Status Change flag
3557 */
3558 dev_dbg(hsotg->dev,
3559 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
3560 hsotg->flags.b.port_connect_status_change = 0;
3561 break;
3562
3563 case USB_PORT_FEAT_C_RESET:
3564 /* Clears driver's internal Port Reset Change flag */
3565 dev_dbg(hsotg->dev,
3566 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
3567 hsotg->flags.b.port_reset_change = 0;
3568 break;
3569
3570 case USB_PORT_FEAT_C_ENABLE:
3571 /*
3572 * Clears the driver's internal Port Enable/Disable
3573 * Change flag
3574 */
3575 dev_dbg(hsotg->dev,
3576 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
3577 hsotg->flags.b.port_enable_change = 0;
3578 break;
3579
3580 case USB_PORT_FEAT_C_SUSPEND:
3581 /*
3582 * Clears the driver's internal Port Suspend Change
3583 * flag, which is set when resume signaling on the host
3584 * port is complete
3585 */
3586 dev_dbg(hsotg->dev,
3587 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
3588 hsotg->flags.b.port_suspend_change = 0;
3589 break;
3590
3591 case USB_PORT_FEAT_C_PORT_L1:
3592 dev_dbg(hsotg->dev,
3593 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
3594 hsotg->flags.b.port_l1_change = 0;
3595 break;
3596
3597 case USB_PORT_FEAT_C_OVER_CURRENT:
3598 dev_dbg(hsotg->dev,
3599 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
3600 hsotg->flags.b.port_over_current_change = 0;
3601 break;
3602
3603 default:
3604 retval = -EINVAL;
3605 dev_err(hsotg->dev,
3606 "ClearPortFeature request %1xh unknown or unsupported\n",
3607 wvalue);
3608 }
3609 break;
3610
3611 case GetHubDescriptor:
3612 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
3613 hub_desc = (struct usb_hub_descriptor *)buf;
3614 hub_desc->bDescLength = 9;
3615 hub_desc->bDescriptorType = USB_DT_HUB;
3616 hub_desc->bNbrPorts = 1;
3617 hub_desc->wHubCharacteristics =
3618 cpu_to_le16(HUB_CHAR_COMMON_LPSM |
3619 HUB_CHAR_INDV_PORT_OCPM);
3620 hub_desc->bPwrOn2PwrGood = 1;
3621 hub_desc->bHubContrCurrent = 0;
3622 hub_desc->u.hs.DeviceRemovable[0] = 0;
3623 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
3624 break;
3625
3626 case GetHubStatus:
3627 dev_dbg(hsotg->dev, "GetHubStatus\n");
3628 memset(buf, 0, 4);
3629 break;
3630
3631 case GetPortStatus:
3632 dev_vdbg(hsotg->dev,
3633 "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
3634 hsotg->flags.d32);
3635 if (!windex || windex > 1)
3636 goto error;
3637
3638 port_status = 0;
3639 if (hsotg->flags.b.port_connect_status_change)
3640 port_status |= USB_PORT_STAT_C_CONNECTION << 16;
3641 if (hsotg->flags.b.port_enable_change)
3642 port_status |= USB_PORT_STAT_C_ENABLE << 16;
3643 if (hsotg->flags.b.port_suspend_change)
3644 port_status |= USB_PORT_STAT_C_SUSPEND << 16;
3645 if (hsotg->flags.b.port_l1_change)
3646 port_status |= USB_PORT_STAT_C_L1 << 16;
3647 if (hsotg->flags.b.port_reset_change)
3648 port_status |= USB_PORT_STAT_C_RESET << 16;
3649 if (hsotg->flags.b.port_over_current_change) {
3650 dev_warn(hsotg->dev, "Overcurrent change detected\n");
3651 port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
3652 }
3653
3654 if (!hsotg->flags.b.port_connect_status) {
3655 /*
3656 * The port is disconnected, which means the core is
3657 * either in device mode or it soon will be. Just
3658 * return 0's for the remainder of the port status
3659 * since the port register can't be read if the core
3660 * is in device mode.
3661 */
3662 *(__le32 *)buf = cpu_to_le32(port_status);
3663 break;
3664 }
3665
3666 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
3667 dev_vdbg(hsotg->dev, " HPRT0: 0x%08x\n", hprt0);
3668
3669 if (hprt0 & HPRT0_CONNSTS)
3670 port_status |= USB_PORT_STAT_CONNECTION;
3671 if (hprt0 & HPRT0_ENA)
3672 port_status |= USB_PORT_STAT_ENABLE;
3673 if (hprt0 & HPRT0_SUSP)
3674 port_status |= USB_PORT_STAT_SUSPEND;
3675 if (hprt0 & HPRT0_OVRCURRACT)
3676 port_status |= USB_PORT_STAT_OVERCURRENT;
3677 if (hprt0 & HPRT0_RST)
3678 port_status |= USB_PORT_STAT_RESET;
3679 if (hprt0 & HPRT0_PWR)
3680 port_status |= USB_PORT_STAT_POWER;
3681
3682 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
3683 if (speed == HPRT0_SPD_HIGH_SPEED)
3684 port_status |= USB_PORT_STAT_HIGH_SPEED;
3685 else if (speed == HPRT0_SPD_LOW_SPEED)
3686 port_status |= USB_PORT_STAT_LOW_SPEED;
3687
3688 if (hprt0 & HPRT0_TSTCTL_MASK)
3689 port_status |= USB_PORT_STAT_TEST;
3690 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
3691
3692 if (hsotg->params.dma_desc_fs_enable) {
3693 /*
3694 * Enable descriptor DMA only if a full speed
3695 * device is connected.
3696 */
3697 if (hsotg->new_connection &&
3698 ((port_status &
3699 (USB_PORT_STAT_CONNECTION |
3700 USB_PORT_STAT_HIGH_SPEED |
3701 USB_PORT_STAT_LOW_SPEED)) ==
3702 USB_PORT_STAT_CONNECTION)) {
3703 u32 hcfg;
3704
3705 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");
3706 hsotg->params.dma_desc_enable = true;
3707 hcfg = dwc2_readl(hsotg->regs + HCFG);
3708 hcfg |= HCFG_DESCDMA;
3709 dwc2_writel(hcfg, hsotg->regs + HCFG);
3710 hsotg->new_connection = false;
3711 }
3712 }
3713
3714 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
3715 *(__le32 *)buf = cpu_to_le32(port_status);
3716 break;
3717
3718 case SetHubFeature:
3719 dev_dbg(hsotg->dev, "SetHubFeature\n");
3720 /* No HUB features supported */
3721 break;
3722
3723 case SetPortFeature:
3724 dev_dbg(hsotg->dev, "SetPortFeature\n");
3725 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
3726 goto error;
3727
3728 if (!hsotg->flags.b.port_connect_status) {
3729 /*
3730 * The port is disconnected, which means the core is
3731 * either in device mode or it soon will be. Just
3732 * return without doing anything since the port
3733 * register can't be written if the core is in device
3734 * mode.
3735 */
3736 break;
3737 }
3738
3739 switch (wvalue) {
3740 case USB_PORT_FEAT_SUSPEND:
3741 dev_dbg(hsotg->dev,
3742 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
3743 if (windex != hsotg->otg_port)
3744 goto error;
3745 if (hsotg->params.power_down == 2)
3746 dwc2_enter_hibernation(hsotg, 1);
3747 else
3748 dwc2_port_suspend(hsotg, windex);
3749 break;
3750
3751 case USB_PORT_FEAT_POWER:
3752 dev_dbg(hsotg->dev,
3753 "SetPortFeature - USB_PORT_FEAT_POWER\n");
3754 hprt0 = dwc2_read_hprt0(hsotg);
3755 hprt0 |= HPRT0_PWR;
3756 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3757 break;
3758
3759 case USB_PORT_FEAT_RESET:
3760 if (hsotg->params.power_down == 2 &&
3761 hsotg->hibernated)
3762 dwc2_exit_hibernation(hsotg, 0, 1, 1);
3763 hprt0 = dwc2_read_hprt0(hsotg);
3764 dev_dbg(hsotg->dev,
3765 "SetPortFeature - USB_PORT_FEAT_RESET\n");
3766 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
3767 pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
3768 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
3769 /* ??? Original driver does this */
3770 dwc2_writel(0, hsotg->regs + PCGCTL);
3771
3772 hprt0 = dwc2_read_hprt0(hsotg);
3773 /* Clear suspend bit if resetting from suspend state */
3774 hprt0 &= ~HPRT0_SUSP;
3775
3776 /*
3777 * When B-Host the Port reset bit is set in the Start
3778 * HCD Callback function, so that the reset is started
3779 * within 1ms of the HNP success interrupt
3780 */
3781 if (!dwc2_hcd_is_b_host(hsotg)) {
3782 hprt0 |= HPRT0_PWR | HPRT0_RST;
3783 dev_dbg(hsotg->dev,
3784 "In host mode, hprt0=%08x\n", hprt0);
3785 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3786 }
3787
3788 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
3789 msleep(50);
3790 hprt0 &= ~HPRT0_RST;
3791 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3792 hsotg->lx_state = DWC2_L0; /* Now back to On state */
3793 break;
3794
3795 case USB_PORT_FEAT_INDICATOR:
3796 dev_dbg(hsotg->dev,
3797 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
3798 /* Not supported */
3799 break;
3800
3801 case USB_PORT_FEAT_TEST:
3802 hprt0 = dwc2_read_hprt0(hsotg);
3803 dev_dbg(hsotg->dev,
3804 "SetPortFeature - USB_PORT_FEAT_TEST\n");
3805 hprt0 &= ~HPRT0_TSTCTL_MASK;
3806 hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
3807 dwc2_writel(hprt0, hsotg->regs + HPRT0);
3808 break;
3809
3810 default:
3811 retval = -EINVAL;
3812 dev_err(hsotg->dev,
3813 "SetPortFeature %1xh unknown or unsupported\n",
3814 wvalue);
3815 break;
3816 }
3817 break;
3818
3819 default:
3820error:
3821 retval = -EINVAL;
3822 dev_dbg(hsotg->dev,
3823 "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
3824 typereq, windex, wvalue);
3825 break;
3826 }
3827
3828 return retval;
3829}
3830
3831static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
3832{
3833 int retval;
3834
3835 if (port != 1)
3836 return -EINVAL;
3837
3838 retval = (hsotg->flags.b.port_connect_status_change ||
3839 hsotg->flags.b.port_reset_change ||
3840 hsotg->flags.b.port_enable_change ||
3841 hsotg->flags.b.port_suspend_change ||
3842 hsotg->flags.b.port_over_current_change);
3843
3844 if (retval) {
3845 dev_dbg(hsotg->dev,
3846 "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
3847 dev_dbg(hsotg->dev, " port_connect_status_change: %d\n",
3848 hsotg->flags.b.port_connect_status_change);
3849 dev_dbg(hsotg->dev, " port_reset_change: %d\n",
3850 hsotg->flags.b.port_reset_change);
3851 dev_dbg(hsotg->dev, " port_enable_change: %d\n",
3852 hsotg->flags.b.port_enable_change);
3853 dev_dbg(hsotg->dev, " port_suspend_change: %d\n",
3854 hsotg->flags.b.port_suspend_change);
3855 dev_dbg(hsotg->dev, " port_over_current_change: %d\n",
3856 hsotg->flags.b.port_over_current_change);
3857 }
3858
3859 return retval;
3860}
3861
3862int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
3863{
3864 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
3865
3866#ifdef DWC2_DEBUG_SOF
3867 dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
3868 (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
3869#endif
3870 return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3871}
3872
3873int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us)
3874{
3875 u32 hprt = dwc2_readl(hsotg->regs + HPRT0);
3876 u32 hfir = dwc2_readl(hsotg->regs + HFIR);
3877 u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
3878 unsigned int us_per_frame;
3879 unsigned int frame_number;
3880 unsigned int remaining;
3881 unsigned int interval;
3882 unsigned int phy_clks;
3883
3884 /* High speed has 125 us per (micro) frame; others are 1 ms per */
3885 us_per_frame = (hprt & HPRT0_SPD_MASK) ? 1000 : 125;
3886
3887 /* Extract fields */
3888 frame_number = (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
3889 remaining = (hfnum & HFNUM_FRREM_MASK) >> HFNUM_FRREM_SHIFT;
3890 interval = (hfir & HFIR_FRINT_MASK) >> HFIR_FRINT_SHIFT;
3891
3892 /*
3893 * Number of phy clocks since the last tick of the frame number after
3894 * "us" has passed.
3895 */
3896 phy_clks = (interval - remaining) +
3897 DIV_ROUND_UP(interval * us, us_per_frame);
3898
3899 return dwc2_frame_num_inc(frame_number, phy_clks / interval);
3900}
3901
3902int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
3903{
3904 return hsotg->op_state == OTG_STATE_B_HOST;
3905}
3906
3907static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
3908 int iso_desc_count,
3909 gfp_t mem_flags)
3910{
3911 struct dwc2_hcd_urb *urb;
3912 u32 size = sizeof(*urb) + iso_desc_count *
3913 sizeof(struct dwc2_hcd_iso_packet_desc);
3914
3915 urb = kzalloc(size, mem_flags);
3916 if (urb)
3917 urb->packet_count = iso_desc_count;
3918 return urb;
3919}
3920
3921static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
3922 struct dwc2_hcd_urb *urb, u8 dev_addr,
3923 u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
3924{
3925 if (dbg_perio() ||
3926 ep_type == USB_ENDPOINT_XFER_BULK ||
3927 ep_type == USB_ENDPOINT_XFER_CONTROL)
3928 dev_vdbg(hsotg->dev,
3929 "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
3930 dev_addr, ep_num, ep_dir, ep_type, mps);
3931 urb->pipe_info.dev_addr = dev_addr;
3932 urb->pipe_info.ep_num = ep_num;
3933 urb->pipe_info.pipe_type = ep_type;
3934 urb->pipe_info.pipe_dir = ep_dir;
3935 urb->pipe_info.mps = mps;
3936}
3937
3938/*
3939 * NOTE: This function will be removed once the peripheral controller code
3940 * is integrated and the driver is stable
3941 */
3942void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
3943{
3944#ifdef DEBUG
3945 struct dwc2_host_chan *chan;
3946 struct dwc2_hcd_urb *urb;
3947 struct dwc2_qtd *qtd;
3948 int num_channels;
3949 u32 np_tx_status;
3950 u32 p_tx_status;
3951 int i;
3952
3953 num_channels = hsotg->params.host_channels;
3954 dev_dbg(hsotg->dev, "\n");
3955 dev_dbg(hsotg->dev,
3956 "************************************************************\n");
3957 dev_dbg(hsotg->dev, "HCD State:\n");
3958 dev_dbg(hsotg->dev, " Num channels: %d\n", num_channels);
3959
3960 for (i = 0; i < num_channels; i++) {
3961 chan = hsotg->hc_ptr_array[i];
3962 dev_dbg(hsotg->dev, " Channel %d:\n", i);
3963 dev_dbg(hsotg->dev,
3964 " dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3965 chan->dev_addr, chan->ep_num, chan->ep_is_in);
3966 dev_dbg(hsotg->dev, " speed: %d\n", chan->speed);
3967 dev_dbg(hsotg->dev, " ep_type: %d\n", chan->ep_type);
3968 dev_dbg(hsotg->dev, " max_packet: %d\n", chan->max_packet);
3969 dev_dbg(hsotg->dev, " data_pid_start: %d\n",
3970 chan->data_pid_start);
3971 dev_dbg(hsotg->dev, " multi_count: %d\n", chan->multi_count);
3972 dev_dbg(hsotg->dev, " xfer_started: %d\n",
3973 chan->xfer_started);
3974 dev_dbg(hsotg->dev, " xfer_buf: %p\n", chan->xfer_buf);
3975 dev_dbg(hsotg->dev, " xfer_dma: %08lx\n",
3976 (unsigned long)chan->xfer_dma);
3977 dev_dbg(hsotg->dev, " xfer_len: %d\n", chan->xfer_len);
3978 dev_dbg(hsotg->dev, " xfer_count: %d\n", chan->xfer_count);
3979 dev_dbg(hsotg->dev, " halt_on_queue: %d\n",
3980 chan->halt_on_queue);
3981 dev_dbg(hsotg->dev, " halt_pending: %d\n",
3982 chan->halt_pending);
3983 dev_dbg(hsotg->dev, " halt_status: %d\n", chan->halt_status);
3984 dev_dbg(hsotg->dev, " do_split: %d\n", chan->do_split);
3985 dev_dbg(hsotg->dev, " complete_split: %d\n",
3986 chan->complete_split);
3987 dev_dbg(hsotg->dev, " hub_addr: %d\n", chan->hub_addr);
3988 dev_dbg(hsotg->dev, " hub_port: %d\n", chan->hub_port);
3989 dev_dbg(hsotg->dev, " xact_pos: %d\n", chan->xact_pos);
3990 dev_dbg(hsotg->dev, " requests: %d\n", chan->requests);
3991 dev_dbg(hsotg->dev, " qh: %p\n", chan->qh);
3992
3993 if (chan->xfer_started) {
3994 u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
3995
3996 hfnum = dwc2_readl(hsotg->regs + HFNUM);
3997 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
3998 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i));
3999 hcint = dwc2_readl(hsotg->regs + HCINT(i));
4000 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i));
4001 dev_dbg(hsotg->dev, " hfnum: 0x%08x\n", hfnum);
4002 dev_dbg(hsotg->dev, " hcchar: 0x%08x\n", hcchar);
4003 dev_dbg(hsotg->dev, " hctsiz: 0x%08x\n", hctsiz);
4004 dev_dbg(hsotg->dev, " hcint: 0x%08x\n", hcint);
4005 dev_dbg(hsotg->dev, " hcintmsk: 0x%08x\n", hcintmsk);
4006 }
4007
4008 if (!(chan->xfer_started && chan->qh))
4009 continue;
4010
4011 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
4012 if (!qtd->in_process)
4013 break;
4014 urb = qtd->urb;
4015 dev_dbg(hsotg->dev, " URB Info:\n");
4016 dev_dbg(hsotg->dev, " qtd: %p, urb: %p\n",
4017 qtd, urb);
4018 if (urb) {
4019 dev_dbg(hsotg->dev,
4020 " Dev: %d, EP: %d %s\n",
4021 dwc2_hcd_get_dev_addr(&urb->pipe_info),
4022 dwc2_hcd_get_ep_num(&urb->pipe_info),
4023 dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
4024 "IN" : "OUT");
4025 dev_dbg(hsotg->dev,
4026 " Max packet size: %d\n",
4027 dwc2_hcd_get_mps(&urb->pipe_info));
4028 dev_dbg(hsotg->dev,
4029 " transfer_buffer: %p\n",
4030 urb->buf);
4031 dev_dbg(hsotg->dev,
4032 " transfer_dma: %08lx\n",
4033 (unsigned long)urb->dma);
4034 dev_dbg(hsotg->dev,
4035 " transfer_buffer_length: %d\n",
4036 urb->length);
4037 dev_dbg(hsotg->dev, " actual_length: %d\n",
4038 urb->actual_length);
4039 }
4040 }
4041 }
4042
4043 dev_dbg(hsotg->dev, " non_periodic_channels: %d\n",
4044 hsotg->non_periodic_channels);
4045 dev_dbg(hsotg->dev, " periodic_channels: %d\n",
4046 hsotg->periodic_channels);
4047 dev_dbg(hsotg->dev, " periodic_usecs: %d\n", hsotg->periodic_usecs);
4048 np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
4049 dev_dbg(hsotg->dev, " NP Tx Req Queue Space Avail: %d\n",
4050 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
4051 dev_dbg(hsotg->dev, " NP Tx FIFO Space Avail: %d\n",
4052 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
4053 p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
4054 dev_dbg(hsotg->dev, " P Tx Req Queue Space Avail: %d\n",
4055 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
4056 dev_dbg(hsotg->dev, " P Tx FIFO Space Avail: %d\n",
4057 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
4058 dwc2_dump_global_registers(hsotg);
4059 dwc2_dump_host_registers(hsotg);
4060 dev_dbg(hsotg->dev,
4061 "************************************************************\n");
4062 dev_dbg(hsotg->dev, "\n");
4063#endif
4064}
4065
4066struct wrapper_priv_data {
4067 struct dwc2_hsotg *hsotg;
4068};
4069
4070/* Gets the dwc2_hsotg from a usb_hcd */
4071static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
4072{
4073 struct wrapper_priv_data *p;
4074
4075 p = (struct wrapper_priv_data *)&hcd->hcd_priv;
4076 return p->hsotg;
4077}
4078
4079/**
4080 * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context
4081 *
4082 * This will get the dwc2_tt structure (and ttport) associated with the given
4083 * context (which is really just a struct urb pointer).
4084 *
4085 * The first time this is called for a given TT we allocate memory for our
4086 * structure. When everyone is done and has called dwc2_host_put_tt_info()
4087 * then the refcount for the structure will go to 0 and we'll free it.
4088 *
4089 * @hsotg: The HCD state structure for the DWC OTG controller.
4090 * @qh: The QH structure.
4091 * @context: The priv pointer from a struct dwc2_hcd_urb.
4092 * @mem_flags: Flags for allocating memory.
4093 * @ttport: We'll return this device's port number here. That's used to
4094 * reference into the bitmap if we're on a multi_tt hub.
4095 *
4096 * Return: a pointer to a struct dwc2_tt. Don't forget to call
4097 * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure.
4098 */
4099
4100struct dwc2_tt *dwc2_host_get_tt_info(struct dwc2_hsotg *hsotg, void *context,
4101 gfp_t mem_flags, int *ttport)
4102{
4103 struct urb *urb = context;
4104 struct dwc2_tt *dwc_tt = NULL;
4105
4106 if (urb->dev->tt) {
4107 *ttport = urb->dev->ttport;
4108
4109 dwc_tt = urb->dev->tt->hcpriv;
4110 if (!dwc_tt) {
4111 size_t bitmap_size;
4112
4113 /*
4114 * For single_tt we need one schedule. For multi_tt
4115 * we need one per port.
4116 */
4117 bitmap_size = DWC2_ELEMENTS_PER_LS_BITMAP *
4118 sizeof(dwc_tt->periodic_bitmaps[0]);
4119 if (urb->dev->tt->multi)
4120 bitmap_size *= urb->dev->tt->hub->maxchild;
4121
4122 dwc_tt = kzalloc(sizeof(*dwc_tt) + bitmap_size,
4123 mem_flags);
4124 if (!dwc_tt)
4125 return NULL;
4126
4127 dwc_tt->usb_tt = urb->dev->tt;
4128 dwc_tt->usb_tt->hcpriv = dwc_tt;
4129 }
4130
4131 dwc_tt->refcount++;
4132 }
4133
4134 return dwc_tt;
4135}
4136
4137/**
4138 * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info()
4139 *
4140 * Frees resources allocated by dwc2_host_get_tt_info() if all current holders
4141 * of the structure are done.
4142 *
4143 * It's OK to call this with NULL.
4144 *
4145 * @hsotg: The HCD state structure for the DWC OTG controller.
4146 * @dwc_tt: The pointer returned by dwc2_host_get_tt_info.
4147 */
4148void dwc2_host_put_tt_info(struct dwc2_hsotg *hsotg, struct dwc2_tt *dwc_tt)
4149{
4150 /* Model kfree and make put of NULL a no-op */
4151 if (!dwc_tt)
4152 return;
4153
4154 WARN_ON(dwc_tt->refcount < 1);
4155
4156 dwc_tt->refcount--;
4157 if (!dwc_tt->refcount) {
4158 dwc_tt->usb_tt->hcpriv = NULL;
4159 kfree(dwc_tt);
4160 }
4161}
4162
4163int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
4164{
4165 struct urb *urb = context;
4166
4167 return urb->dev->speed;
4168}
4169
4170static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4171 struct urb *urb)
4172{
4173 struct usb_bus *bus = hcd_to_bus(hcd);
4174
4175 if (urb->interval)
4176 bus->bandwidth_allocated += bw / urb->interval;
4177 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4178 bus->bandwidth_isoc_reqs++;
4179 else
4180 bus->bandwidth_int_reqs++;
4181}
4182
4183static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
4184 struct urb *urb)
4185{
4186 struct usb_bus *bus = hcd_to_bus(hcd);
4187
4188 if (urb->interval)
4189 bus->bandwidth_allocated -= bw / urb->interval;
4190 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
4191 bus->bandwidth_isoc_reqs--;
4192 else
4193 bus->bandwidth_int_reqs--;
4194}
4195
4196/*
4197 * Sets the final status of an URB and returns it to the upper layer. Any
4198 * required cleanup of the URB is performed.
4199 *
4200 * Must be called with interrupt disabled and spinlock held
4201 */
4202void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
4203 int status)
4204{
4205 struct urb *urb;
4206 int i;
4207
4208 if (!qtd) {
4209 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
4210 return;
4211 }
4212
4213 if (!qtd->urb) {
4214 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
4215 return;
4216 }
4217
4218 urb = qtd->urb->priv;
4219 if (!urb) {
4220 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
4221 return;
4222 }
4223
4224 urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
4225
4226 if (dbg_urb(urb))
4227 dev_vdbg(hsotg->dev,
4228 "%s: urb %p device %d ep %d-%s status %d actual %d\n",
4229 __func__, urb, usb_pipedevice(urb->pipe),
4230 usb_pipeendpoint(urb->pipe),
4231 usb_pipein(urb->pipe) ? "IN" : "OUT", status,
4232 urb->actual_length);
4233
4234 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4235 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
4236 for (i = 0; i < urb->number_of_packets; ++i) {
4237 urb->iso_frame_desc[i].actual_length =
4238 dwc2_hcd_urb_get_iso_desc_actual_length(
4239 qtd->urb, i);
4240 urb->iso_frame_desc[i].status =
4241 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
4242 }
4243 }
4244
4245 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
4246 for (i = 0; i < urb->number_of_packets; i++)
4247 dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
4248 i, urb->iso_frame_desc[i].status);
4249 }
4250
4251 urb->status = status;
4252 if (!status) {
4253 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
4254 urb->actual_length < urb->transfer_buffer_length)
4255 urb->status = -EREMOTEIO;
4256 }
4257
4258 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4259 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4260 struct usb_host_endpoint *ep = urb->ep;
4261
4262 if (ep)
4263 dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
4264 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4265 urb);
4266 }
4267
4268 usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
4269 urb->hcpriv = NULL;
4270 kfree(qtd->urb);
4271 qtd->urb = NULL;
4272
4273 usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
4274}
4275
4276/*
4277 * Work queue function for starting the HCD when A-Cable is connected
4278 */
4279static void dwc2_hcd_start_func(struct work_struct *work)
4280{
4281 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4282 start_work.work);
4283
4284 dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
4285 dwc2_host_start(hsotg);
4286}
4287
4288/*
4289 * Reset work queue function
4290 */
4291static void dwc2_hcd_reset_func(struct work_struct *work)
4292{
4293 struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
4294 reset_work.work);
4295 unsigned long flags;
4296 u32 hprt0;
4297
4298 dev_dbg(hsotg->dev, "USB RESET function called\n");
4299
4300 spin_lock_irqsave(&hsotg->lock, flags);
4301
4302 hprt0 = dwc2_read_hprt0(hsotg);
4303 hprt0 &= ~HPRT0_RST;
4304 dwc2_writel(hprt0, hsotg->regs + HPRT0);
4305 hsotg->flags.b.port_reset_change = 1;
4306
4307 spin_unlock_irqrestore(&hsotg->lock, flags);
4308}
4309
4310/*
4311 * =========================================================================
4312 * Linux HC Driver Functions
4313 * =========================================================================
4314 */
4315
4316/*
4317 * Initializes the DWC_otg controller and its root hub and prepares it for host
4318 * mode operation. Activates the root port. Returns 0 on success and a negative
4319 * error code on failure.
4320 */
4321static int _dwc2_hcd_start(struct usb_hcd *hcd)
4322{
4323 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4324 struct usb_bus *bus = hcd_to_bus(hcd);
4325 unsigned long flags;
4326
4327 dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
4328
4329 spin_lock_irqsave(&hsotg->lock, flags);
4330 hsotg->lx_state = DWC2_L0;
4331 hcd->state = HC_STATE_RUNNING;
4332 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4333
4334 if (dwc2_is_device_mode(hsotg)) {
4335 spin_unlock_irqrestore(&hsotg->lock, flags);
4336 return 0; /* why 0 ?? */
4337 }
4338
4339 dwc2_hcd_reinit(hsotg);
4340
4341 /* Initialize and connect root hub if one is not already attached */
4342 if (bus->root_hub) {
4343 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
4344 /* Inform the HUB driver to resume */
4345 usb_hcd_resume_root_hub(hcd);
4346 }
4347
4348 spin_unlock_irqrestore(&hsotg->lock, flags);
4349
4350 return dwc2_vbus_supply_init(hsotg);
4351}
4352
4353/*
4354 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
4355 * stopped.
4356 */
4357static void _dwc2_hcd_stop(struct usb_hcd *hcd)
4358{
4359 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4360 unsigned long flags;
4361
4362 /* Turn off all host-specific interrupts */
4363 dwc2_disable_host_interrupts(hsotg);
4364
4365 /* Wait for interrupt processing to finish */
4366 synchronize_irq(hcd->irq);
4367
4368 spin_lock_irqsave(&hsotg->lock, flags);
4369 /* Ensure hcd is disconnected */
4370 dwc2_hcd_disconnect(hsotg, true);
4371 dwc2_hcd_stop(hsotg);
4372 hsotg->lx_state = DWC2_L3;
4373 hcd->state = HC_STATE_HALT;
4374 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4375 spin_unlock_irqrestore(&hsotg->lock, flags);
4376
4377 dwc2_vbus_supply_exit(hsotg);
4378
4379 usleep_range(1000, 3000);
4380}
4381
4382static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
4383{
4384 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4385 unsigned long flags;
4386 int ret = 0;
4387 u32 hprt0;
4388
4389 spin_lock_irqsave(&hsotg->lock, flags);
4390
4391 if (dwc2_is_device_mode(hsotg))
4392 goto unlock;
4393
4394 if (hsotg->lx_state != DWC2_L0)
4395 goto unlock;
4396
4397 if (!HCD_HW_ACCESSIBLE(hcd))
4398 goto unlock;
4399
4400 if (hsotg->op_state == OTG_STATE_B_PERIPHERAL)
4401 goto unlock;
4402
4403 if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL)
4404 goto skip_power_saving;
4405
4406 /*
4407 * Drive USB suspend and disable port Power
4408 * if usb bus is not suspended.
4409 */
4410 if (!hsotg->bus_suspended) {
4411 hprt0 = dwc2_read_hprt0(hsotg);
4412 hprt0 |= HPRT0_SUSP;
4413 hprt0 &= ~HPRT0_PWR;
4414 dwc2_writel(hprt0, hsotg->regs + HPRT0);
4415 dwc2_vbus_supply_exit(hsotg);
4416 }
4417
4418 /* Enter partial_power_down */
4419 ret = dwc2_enter_partial_power_down(hsotg);
4420 if (ret) {
4421 if (ret != -ENOTSUPP)
4422 dev_err(hsotg->dev,
4423 "enter partial_power_down failed\n");
4424 goto skip_power_saving;
4425 }
4426
4427 /* Ask phy to be suspended */
4428 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4429 spin_unlock_irqrestore(&hsotg->lock, flags);
4430 usb_phy_set_suspend(hsotg->uphy, true);
4431 spin_lock_irqsave(&hsotg->lock, flags);
4432 }
4433
4434 /* After entering partial_power_down, hardware is no more accessible */
4435 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4436
4437skip_power_saving:
4438 hsotg->lx_state = DWC2_L2;
4439unlock:
4440 spin_unlock_irqrestore(&hsotg->lock, flags);
4441
4442 return ret;
4443}
4444
4445static int _dwc2_hcd_resume(struct usb_hcd *hcd)
4446{
4447 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4448 unsigned long flags;
4449 int ret = 0;
4450
4451 spin_lock_irqsave(&hsotg->lock, flags);
4452
4453 if (dwc2_is_device_mode(hsotg))
4454 goto unlock;
4455
4456 if (hsotg->lx_state != DWC2_L2)
4457 goto unlock;
4458
4459 if (hsotg->params.power_down != DWC2_POWER_DOWN_PARAM_PARTIAL) {
4460 hsotg->lx_state = DWC2_L0;
4461 goto unlock;
4462 }
4463
4464 /*
4465 * Set HW accessible bit before powering on the controller
4466 * since an interrupt may rise.
4467 */
4468 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
4469
4470 /*
4471 * Enable power if not already done.
4472 * This must not be spinlocked since duration
4473 * of this call is unknown.
4474 */
4475 if (!IS_ERR_OR_NULL(hsotg->uphy)) {
4476 spin_unlock_irqrestore(&hsotg->lock, flags);
4477 usb_phy_set_suspend(hsotg->uphy, false);
4478 spin_lock_irqsave(&hsotg->lock, flags);
4479 }
4480
4481 /* Exit partial_power_down */
4482 ret = dwc2_exit_partial_power_down(hsotg, true);
4483 if (ret && (ret != -ENOTSUPP))
4484 dev_err(hsotg->dev, "exit partial_power_down failed\n");
4485
4486 hsotg->lx_state = DWC2_L0;
4487
4488 spin_unlock_irqrestore(&hsotg->lock, flags);
4489
4490 if (hsotg->bus_suspended) {
4491 spin_lock_irqsave(&hsotg->lock, flags);
4492 hsotg->flags.b.port_suspend_change = 1;
4493 spin_unlock_irqrestore(&hsotg->lock, flags);
4494 dwc2_port_resume(hsotg);
4495 } else {
4496 dwc2_vbus_supply_init(hsotg);
4497
4498 /* Wait for controller to correctly update D+/D- level */
4499 usleep_range(3000, 5000);
4500
4501 /*
4502 * Clear Port Enable and Port Status changes.
4503 * Enable Port Power.
4504 */
4505 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET |
4506 HPRT0_ENACHG, hsotg->regs + HPRT0);
4507 /* Wait for controller to detect Port Connect */
4508 usleep_range(5000, 7000);
4509 }
4510
4511 return ret;
4512unlock:
4513 spin_unlock_irqrestore(&hsotg->lock, flags);
4514
4515 return ret;
4516}
4517
4518/* Returns the current frame number */
4519static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
4520{
4521 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4522
4523 return dwc2_hcd_get_frame_number(hsotg);
4524}
4525
4526static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
4527 char *fn_name)
4528{
4529#ifdef VERBOSE_DEBUG
4530 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4531 char *pipetype = NULL;
4532 char *speed = NULL;
4533
4534 dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
4535 dev_vdbg(hsotg->dev, " Device address: %d\n",
4536 usb_pipedevice(urb->pipe));
4537 dev_vdbg(hsotg->dev, " Endpoint: %d, %s\n",
4538 usb_pipeendpoint(urb->pipe),
4539 usb_pipein(urb->pipe) ? "IN" : "OUT");
4540
4541 switch (usb_pipetype(urb->pipe)) {
4542 case PIPE_CONTROL:
4543 pipetype = "CONTROL";
4544 break;
4545 case PIPE_BULK:
4546 pipetype = "BULK";
4547 break;
4548 case PIPE_INTERRUPT:
4549 pipetype = "INTERRUPT";
4550 break;
4551 case PIPE_ISOCHRONOUS:
4552 pipetype = "ISOCHRONOUS";
4553 break;
4554 }
4555
4556 dev_vdbg(hsotg->dev, " Endpoint type: %s %s (%s)\n", pipetype,
4557 usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
4558 "IN" : "OUT");
4559
4560 switch (urb->dev->speed) {
4561 case USB_SPEED_HIGH:
4562 speed = "HIGH";
4563 break;
4564 case USB_SPEED_FULL:
4565 speed = "FULL";
4566 break;
4567 case USB_SPEED_LOW:
4568 speed = "LOW";
4569 break;
4570 default:
4571 speed = "UNKNOWN";
4572 break;
4573 }
4574
4575 dev_vdbg(hsotg->dev, " Speed: %s\n", speed);
4576 dev_vdbg(hsotg->dev, " Max packet size: %d\n",
4577 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
4578 dev_vdbg(hsotg->dev, " Data buffer length: %d\n",
4579 urb->transfer_buffer_length);
4580 dev_vdbg(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
4581 urb->transfer_buffer, (unsigned long)urb->transfer_dma);
4582 dev_vdbg(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
4583 urb->setup_packet, (unsigned long)urb->setup_dma);
4584 dev_vdbg(hsotg->dev, " Interval: %d\n", urb->interval);
4585
4586 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
4587 int i;
4588
4589 for (i = 0; i < urb->number_of_packets; i++) {
4590 dev_vdbg(hsotg->dev, " ISO Desc %d:\n", i);
4591 dev_vdbg(hsotg->dev, " offset: %d, length %d\n",
4592 urb->iso_frame_desc[i].offset,
4593 urb->iso_frame_desc[i].length);
4594 }
4595 }
4596#endif
4597}
4598
4599/*
4600 * Starts processing a USB transfer request specified by a USB Request Block
4601 * (URB). mem_flags indicates the type of memory allocation to use while
4602 * processing this URB.
4603 */
4604static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
4605 gfp_t mem_flags)
4606{
4607 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4608 struct usb_host_endpoint *ep = urb->ep;
4609 struct dwc2_hcd_urb *dwc2_urb;
4610 int i;
4611 int retval;
4612 int alloc_bandwidth = 0;
4613 u8 ep_type = 0;
4614 u32 tflags = 0;
4615 void *buf;
4616 unsigned long flags;
4617 struct dwc2_qh *qh;
4618 bool qh_allocated = false;
4619 struct dwc2_qtd *qtd;
4620
4621 if (dbg_urb(urb)) {
4622 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
4623 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
4624 }
4625
4626 if (!ep)
4627 return -EINVAL;
4628
4629 if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
4630 usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
4631 spin_lock_irqsave(&hsotg->lock, flags);
4632 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
4633 alloc_bandwidth = 1;
4634 spin_unlock_irqrestore(&hsotg->lock, flags);
4635 }
4636
4637 switch (usb_pipetype(urb->pipe)) {
4638 case PIPE_CONTROL:
4639 ep_type = USB_ENDPOINT_XFER_CONTROL;
4640 break;
4641 case PIPE_ISOCHRONOUS:
4642 ep_type = USB_ENDPOINT_XFER_ISOC;
4643 break;
4644 case PIPE_BULK:
4645 ep_type = USB_ENDPOINT_XFER_BULK;
4646 break;
4647 case PIPE_INTERRUPT:
4648 ep_type = USB_ENDPOINT_XFER_INT;
4649 break;
4650 }
4651
4652 dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
4653 mem_flags);
4654 if (!dwc2_urb)
4655 return -ENOMEM;
4656
4657 dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
4658 usb_pipeendpoint(urb->pipe), ep_type,
4659 usb_pipein(urb->pipe),
4660 usb_maxpacket(urb->dev, urb->pipe,
4661 !(usb_pipein(urb->pipe))));
4662
4663 buf = urb->transfer_buffer;
4664
4665 if (hcd->self.uses_dma) {
4666 if (!buf && (urb->transfer_dma & 3)) {
4667 dev_err(hsotg->dev,
4668 "%s: unaligned transfer with no transfer_buffer",
4669 __func__);
4670 retval = -EINVAL;
4671 goto fail0;
4672 }
4673 }
4674
4675 if (!(urb->transfer_flags & URB_NO_INTERRUPT))
4676 tflags |= URB_GIVEBACK_ASAP;
4677 if (urb->transfer_flags & URB_ZERO_PACKET)
4678 tflags |= URB_SEND_ZERO_PACKET;
4679
4680 dwc2_urb->priv = urb;
4681 dwc2_urb->buf = buf;
4682 dwc2_urb->dma = urb->transfer_dma;
4683 dwc2_urb->length = urb->transfer_buffer_length;
4684 dwc2_urb->setup_packet = urb->setup_packet;
4685 dwc2_urb->setup_dma = urb->setup_dma;
4686 dwc2_urb->flags = tflags;
4687 dwc2_urb->interval = urb->interval;
4688 dwc2_urb->status = -EINPROGRESS;
4689
4690 for (i = 0; i < urb->number_of_packets; ++i)
4691 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
4692 urb->iso_frame_desc[i].offset,
4693 urb->iso_frame_desc[i].length);
4694
4695 urb->hcpriv = dwc2_urb;
4696 qh = (struct dwc2_qh *)ep->hcpriv;
4697 /* Create QH for the endpoint if it doesn't exist */
4698 if (!qh) {
4699 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
4700 if (!qh) {
4701 retval = -ENOMEM;
4702 goto fail0;
4703 }
4704 ep->hcpriv = qh;
4705 qh_allocated = true;
4706 }
4707
4708 qtd = kzalloc(sizeof(*qtd), mem_flags);
4709 if (!qtd) {
4710 retval = -ENOMEM;
4711 goto fail1;
4712 }
4713
4714 spin_lock_irqsave(&hsotg->lock, flags);
4715 retval = usb_hcd_link_urb_to_ep(hcd, urb);
4716 if (retval)
4717 goto fail2;
4718
4719 retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
4720 if (retval)
4721 goto fail3;
4722
4723 if (alloc_bandwidth) {
4724 dwc2_allocate_bus_bandwidth(hcd,
4725 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
4726 urb);
4727 }
4728
4729 spin_unlock_irqrestore(&hsotg->lock, flags);
4730
4731 return 0;
4732
4733fail3:
4734 dwc2_urb->priv = NULL;
4735 usb_hcd_unlink_urb_from_ep(hcd, urb);
4736 if (qh_allocated && qh->channel && qh->channel->qh == qh)
4737 qh->channel->qh = NULL;
4738fail2:
4739 spin_unlock_irqrestore(&hsotg->lock, flags);
4740 urb->hcpriv = NULL;
4741 kfree(qtd);
4742 qtd = NULL;
4743fail1:
4744 if (qh_allocated) {
4745 struct dwc2_qtd *qtd2, *qtd2_tmp;
4746
4747 ep->hcpriv = NULL;
4748 dwc2_hcd_qh_unlink(hsotg, qh);
4749 /* Free each QTD in the QH's QTD list */
4750 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list,
4751 qtd_list_entry)
4752 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
4753 dwc2_hcd_qh_free(hsotg, qh);
4754 }
4755fail0:
4756 kfree(dwc2_urb);
4757
4758 return retval;
4759}
4760
4761/*
4762 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
4763 */
4764static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
4765 int status)
4766{
4767 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4768 int rc;
4769 unsigned long flags;
4770
4771 dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
4772 dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
4773
4774 spin_lock_irqsave(&hsotg->lock, flags);
4775
4776 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
4777 if (rc)
4778 goto out;
4779
4780 if (!urb->hcpriv) {
4781 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
4782 goto out;
4783 }
4784
4785 rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
4786
4787 usb_hcd_unlink_urb_from_ep(hcd, urb);
4788
4789 kfree(urb->hcpriv);
4790 urb->hcpriv = NULL;
4791
4792 /* Higher layer software sets URB status */
4793 spin_unlock(&hsotg->lock);
4794 usb_hcd_giveback_urb(hcd, urb, status);
4795 spin_lock(&hsotg->lock);
4796
4797 dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
4798 dev_dbg(hsotg->dev, " urb->status = %d\n", urb->status);
4799out:
4800 spin_unlock_irqrestore(&hsotg->lock, flags);
4801
4802 return rc;
4803}
4804
4805/*
4806 * Frees resources in the DWC_otg controller related to a given endpoint. Also
4807 * clears state in the HCD related to the endpoint. Any URBs for the endpoint
4808 * must already be dequeued.
4809 */
4810static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
4811 struct usb_host_endpoint *ep)
4812{
4813 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4814
4815 dev_dbg(hsotg->dev,
4816 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
4817 ep->desc.bEndpointAddress, ep->hcpriv);
4818 dwc2_hcd_endpoint_disable(hsotg, ep, 250);
4819}
4820
4821/*
4822 * Resets endpoint specific parameter values, in current version used to reset
4823 * the data toggle (as a WA). This function can be called from usb_clear_halt
4824 * routine.
4825 */
4826static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
4827 struct usb_host_endpoint *ep)
4828{
4829 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4830 unsigned long flags;
4831
4832 dev_dbg(hsotg->dev,
4833 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
4834 ep->desc.bEndpointAddress);
4835
4836 spin_lock_irqsave(&hsotg->lock, flags);
4837 dwc2_hcd_endpoint_reset(hsotg, ep);
4838 spin_unlock_irqrestore(&hsotg->lock, flags);
4839}
4840
4841/*
4842 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
4843 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
4844 * interrupt.
4845 *
4846 * This function is called by the USB core when an interrupt occurs
4847 */
4848static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
4849{
4850 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4851
4852 return dwc2_handle_hcd_intr(hsotg);
4853}
4854
4855/*
4856 * Creates Status Change bitmap for the root hub and root port. The bitmap is
4857 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
4858 * is the status change indicator for the single root port. Returns 1 if either
4859 * change indicator is 1, otherwise returns 0.
4860 */
4861static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
4862{
4863 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4864
4865 buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
4866 return buf[0] != 0;
4867}
4868
4869/* Handles hub class-specific requests */
4870static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
4871 u16 windex, char *buf, u16 wlength)
4872{
4873 int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
4874 wvalue, windex, buf, wlength);
4875 return retval;
4876}
4877
4878/* Handles hub TT buffer clear completions */
4879static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
4880 struct usb_host_endpoint *ep)
4881{
4882 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4883 struct dwc2_qh *qh;
4884 unsigned long flags;
4885
4886 qh = ep->hcpriv;
4887 if (!qh)
4888 return;
4889
4890 spin_lock_irqsave(&hsotg->lock, flags);
4891 qh->tt_buffer_dirty = 0;
4892
4893 if (hsotg->flags.b.port_connect_status)
4894 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
4895
4896 spin_unlock_irqrestore(&hsotg->lock, flags);
4897}
4898
4899/*
4900 * HPRT0_SPD_HIGH_SPEED: high speed
4901 * HPRT0_SPD_FULL_SPEED: full speed
4902 */
4903static void dwc2_change_bus_speed(struct usb_hcd *hcd, int speed)
4904{
4905 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4906
4907 if (hsotg->params.speed == speed)
4908 return;
4909
4910 hsotg->params.speed = speed;
4911 queue_work(hsotg->wq_otg, &hsotg->wf_otg);
4912}
4913
4914static void dwc2_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
4915{
4916 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4917
4918 if (!hsotg->params.change_speed_quirk)
4919 return;
4920
4921 /*
4922 * On removal, set speed to default high-speed.
4923 */
4924 if (udev->parent && udev->parent->speed > USB_SPEED_UNKNOWN &&
4925 udev->parent->speed < USB_SPEED_HIGH) {
4926 dev_info(hsotg->dev, "Set speed to default high-speed\n");
4927 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
4928 }
4929}
4930
4931static int dwc2_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
4932{
4933 struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
4934
4935 if (!hsotg->params.change_speed_quirk)
4936 return 0;
4937
4938 if (udev->speed == USB_SPEED_HIGH) {
4939 dev_info(hsotg->dev, "Set speed to high-speed\n");
4940 dwc2_change_bus_speed(hcd, HPRT0_SPD_HIGH_SPEED);
4941 } else if ((udev->speed == USB_SPEED_FULL ||
4942 udev->speed == USB_SPEED_LOW)) {
4943 /*
4944 * Change speed setting to full-speed if there's
4945 * a full-speed or low-speed device plugged in.
4946 */
4947 dev_info(hsotg->dev, "Set speed to full-speed\n");
4948 dwc2_change_bus_speed(hcd, HPRT0_SPD_FULL_SPEED);
4949 }
4950
4951 return 0;
4952}
4953
4954static struct hc_driver dwc2_hc_driver = {
4955 .description = "dwc2_hsotg",
4956 .product_desc = "DWC OTG Controller",
4957 .hcd_priv_size = sizeof(struct wrapper_priv_data),
4958
4959 .irq = _dwc2_hcd_irq,
4960 .flags = HCD_MEMORY | HCD_USB2 | HCD_BH,
4961
4962 .start = _dwc2_hcd_start,
4963 .stop = _dwc2_hcd_stop,
4964 .urb_enqueue = _dwc2_hcd_urb_enqueue,
4965 .urb_dequeue = _dwc2_hcd_urb_dequeue,
4966 .endpoint_disable = _dwc2_hcd_endpoint_disable,
4967 .endpoint_reset = _dwc2_hcd_endpoint_reset,
4968 .get_frame_number = _dwc2_hcd_get_frame_number,
4969
4970 .hub_status_data = _dwc2_hcd_hub_status_data,
4971 .hub_control = _dwc2_hcd_hub_control,
4972 .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
4973
4974 .bus_suspend = _dwc2_hcd_suspend,
4975 .bus_resume = _dwc2_hcd_resume,
4976
4977 .map_urb_for_dma = dwc2_map_urb_for_dma,
4978 .unmap_urb_for_dma = dwc2_unmap_urb_for_dma,
4979};
4980
4981/*
4982 * Frees secondary storage associated with the dwc2_hsotg structure contained
4983 * in the struct usb_hcd field
4984 */
4985static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
4986{
4987 u32 ahbcfg;
4988 u32 dctl;
4989 int i;
4990
4991 dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
4992
4993 /* Free memory for QH/QTD lists */
4994 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
4995 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_waiting);
4996 dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
4997 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
4998 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
4999 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
5000 dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
5001
5002 /* Free memory for the host channels */
5003 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
5004 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
5005
5006 if (chan) {
5007 dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
5008 i, chan);
5009 hsotg->hc_ptr_array[i] = NULL;
5010 kfree(chan);
5011 }
5012 }
5013
5014 if (hsotg->params.host_dma) {
5015 if (hsotg->status_buf) {
5016 dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
5017 hsotg->status_buf,
5018 hsotg->status_buf_dma);
5019 hsotg->status_buf = NULL;
5020 }
5021 } else {
5022 kfree(hsotg->status_buf);
5023 hsotg->status_buf = NULL;
5024 }
5025
5026 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
5027
5028 /* Disable all interrupts */
5029 ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
5030 dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
5031 dwc2_writel(0, hsotg->regs + GINTMSK);
5032
5033 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
5034 dctl = dwc2_readl(hsotg->regs + DCTL);
5035 dctl |= DCTL_SFTDISCON;
5036 dwc2_writel(dctl, hsotg->regs + DCTL);
5037 }
5038
5039 if (hsotg->wq_otg) {
5040 if (!cancel_work_sync(&hsotg->wf_otg))
5041 flush_workqueue(hsotg->wq_otg);
5042 destroy_workqueue(hsotg->wq_otg);
5043 }
5044
5045 del_timer(&hsotg->wkp_timer);
5046}
5047
5048static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
5049{
5050 /* Turn off all host-specific interrupts */
5051 dwc2_disable_host_interrupts(hsotg);
5052
5053 dwc2_hcd_free(hsotg);
5054}
5055
5056/*
5057 * Initializes the HCD. This function allocates memory for and initializes the
5058 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
5059 * USB bus with the core and calls the hc_driver->start() function. It returns
5060 * a negative error on failure.
5061 */
5062int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
5063{
5064 struct platform_device *pdev = to_platform_device(hsotg->dev);
5065 struct resource *res;
5066 struct usb_hcd *hcd;
5067 struct dwc2_host_chan *channel;
5068 u32 hcfg;
5069 int i, num_channels;
5070 int retval;
5071
5072 if (usb_disabled())
5073 return -ENODEV;
5074
5075 dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
5076
5077 retval = -ENOMEM;
5078
5079 hcfg = dwc2_readl(hsotg->regs + HCFG);
5080 dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
5081
5082#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5083 hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) *
5084 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
5085 if (!hsotg->frame_num_array)
5086 goto error1;
5087 hsotg->last_frame_num_array = kzalloc(
5088 sizeof(*hsotg->last_frame_num_array) *
5089 FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
5090 if (!hsotg->last_frame_num_array)
5091 goto error1;
5092#endif
5093 hsotg->last_frame_num = HFNUM_MAX_FRNUM;
5094
5095 /* Check if the bus driver or platform code has setup a dma_mask */
5096 if (hsotg->params.host_dma &&
5097 !hsotg->dev->dma_mask) {
5098 dev_warn(hsotg->dev,
5099 "dma_mask not set, disabling DMA\n");
5100 hsotg->params.host_dma = false;
5101 hsotg->params.dma_desc_enable = false;
5102 }
5103
5104 /* Set device flags indicating whether the HCD supports DMA */
5105 if (hsotg->params.host_dma) {
5106 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5107 dev_warn(hsotg->dev, "can't set DMA mask\n");
5108 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
5109 dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
5110 }
5111
5112 if (hsotg->params.change_speed_quirk) {
5113 dwc2_hc_driver.free_dev = dwc2_free_dev;
5114 dwc2_hc_driver.reset_device = dwc2_reset_device;
5115 }
5116
5117 hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
5118 if (!hcd)
5119 goto error1;
5120
5121 if (!hsotg->params.host_dma)
5122 hcd->self.uses_dma = 0;
5123
5124 hcd->has_tt = 1;
5125
5126 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5127 hcd->rsrc_start = res->start;
5128 hcd->rsrc_len = resource_size(res);
5129
5130 ((struct wrapper_priv_data *)&hcd->hcd_priv)->hsotg = hsotg;
5131 hsotg->priv = hcd;
5132
5133 /*
5134 * Disable the global interrupt until all the interrupt handlers are
5135 * installed
5136 */
5137 dwc2_disable_global_interrupts(hsotg);
5138
5139 /* Initialize the DWC_otg core, and select the Phy type */
5140 retval = dwc2_core_init(hsotg, true);
5141 if (retval)
5142 goto error2;
5143
5144 /* Create new workqueue and init work */
5145 retval = -ENOMEM;
5146 hsotg->wq_otg = alloc_ordered_workqueue("dwc2", 0);
5147 if (!hsotg->wq_otg) {
5148 dev_err(hsotg->dev, "Failed to create workqueue\n");
5149 goto error2;
5150 }
5151 INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
5152
5153 timer_setup(&hsotg->wkp_timer, dwc2_wakeup_detected, 0);
5154
5155 /* Initialize the non-periodic schedule */
5156 INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
5157 INIT_LIST_HEAD(&hsotg->non_periodic_sched_waiting);
5158 INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
5159
5160 /* Initialize the periodic schedule */
5161 INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
5162 INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
5163 INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
5164 INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
5165
5166 INIT_LIST_HEAD(&hsotg->split_order);
5167
5168 /*
5169 * Create a host channel descriptor for each host channel implemented
5170 * in the controller. Initialize the channel descriptor array.
5171 */
5172 INIT_LIST_HEAD(&hsotg->free_hc_list);
5173 num_channels = hsotg->params.host_channels;
5174 memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
5175
5176 for (i = 0; i < num_channels; i++) {
5177 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
5178 if (!channel)
5179 goto error3;
5180 channel->hc_num = i;
5181 INIT_LIST_HEAD(&channel->split_order_list_entry);
5182 hsotg->hc_ptr_array[i] = channel;
5183 }
5184
5185 /* Initialize hsotg start work */
5186 INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
5187
5188 /* Initialize port reset work */
5189 INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
5190
5191 /*
5192 * Allocate space for storing data on status transactions. Normally no
5193 * data is sent, but this space acts as a bit bucket. This must be
5194 * done after usb_add_hcd since that function allocates the DMA buffer
5195 * pool.
5196 */
5197 if (hsotg->params.host_dma)
5198 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
5199 DWC2_HCD_STATUS_BUF_SIZE,
5200 &hsotg->status_buf_dma, GFP_KERNEL);
5201 else
5202 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
5203 GFP_KERNEL);
5204
5205 if (!hsotg->status_buf)
5206 goto error3;
5207
5208 /*
5209 * Create kmem caches to handle descriptor buffers in descriptor
5210 * DMA mode.
5211 * Alignment must be set to 512 bytes.
5212 */
5213 if (hsotg->params.dma_desc_enable ||
5214 hsotg->params.dma_desc_fs_enable) {
5215 hsotg->desc_gen_cache = kmem_cache_create("dwc2-gen-desc",
5216 sizeof(struct dwc2_dma_desc) *
5217 MAX_DMA_DESC_NUM_GENERIC, 512, SLAB_CACHE_DMA,
5218 NULL);
5219 if (!hsotg->desc_gen_cache) {
5220 dev_err(hsotg->dev,
5221 "unable to create dwc2 generic desc cache\n");
5222
5223 /*
5224 * Disable descriptor dma mode since it will not be
5225 * usable.
5226 */
5227 hsotg->params.dma_desc_enable = false;
5228 hsotg->params.dma_desc_fs_enable = false;
5229 }
5230
5231 hsotg->desc_hsisoc_cache = kmem_cache_create("dwc2-hsisoc-desc",
5232 sizeof(struct dwc2_dma_desc) *
5233 MAX_DMA_DESC_NUM_HS_ISOC, 512, 0, NULL);
5234 if (!hsotg->desc_hsisoc_cache) {
5235 dev_err(hsotg->dev,
5236 "unable to create dwc2 hs isoc desc cache\n");
5237
5238 kmem_cache_destroy(hsotg->desc_gen_cache);
5239
5240 /*
5241 * Disable descriptor dma mode since it will not be
5242 * usable.
5243 */
5244 hsotg->params.dma_desc_enable = false;
5245 hsotg->params.dma_desc_fs_enable = false;
5246 }
5247 }
5248
5249 hsotg->otg_port = 1;
5250 hsotg->frame_list = NULL;
5251 hsotg->frame_list_dma = 0;
5252 hsotg->periodic_qh_count = 0;
5253
5254 /* Initiate lx_state to L3 disconnected state */
5255 hsotg->lx_state = DWC2_L3;
5256
5257 hcd->self.otg_port = hsotg->otg_port;
5258
5259 /* Don't support SG list at this point */
5260 hcd->self.sg_tablesize = 0;
5261
5262 if (!IS_ERR_OR_NULL(hsotg->uphy))
5263 otg_set_host(hsotg->uphy->otg, &hcd->self);
5264
5265 /*
5266 * Finish generic HCD initialization and start the HCD. This function
5267 * allocates the DMA buffer pool, registers the USB bus, requests the
5268 * IRQ line, and calls hcd_start method.
5269 */
5270 retval = usb_add_hcd(hcd, hsotg->irq, IRQF_SHARED);
5271 if (retval < 0)
5272 goto error4;
5273
5274 device_wakeup_enable(hcd->self.controller);
5275
5276 dwc2_hcd_dump_state(hsotg);
5277
5278 dwc2_enable_global_interrupts(hsotg);
5279
5280 return 0;
5281
5282error4:
5283 kmem_cache_destroy(hsotg->desc_gen_cache);
5284 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5285error3:
5286 dwc2_hcd_release(hsotg);
5287error2:
5288 usb_put_hcd(hcd);
5289error1:
5290
5291#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5292 kfree(hsotg->last_frame_num_array);
5293 kfree(hsotg->frame_num_array);
5294#endif
5295
5296 dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
5297 return retval;
5298}
5299
5300/*
5301 * Removes the HCD.
5302 * Frees memory and resources associated with the HCD and deregisters the bus.
5303 */
5304void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
5305{
5306 struct usb_hcd *hcd;
5307
5308 dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
5309
5310 hcd = dwc2_hsotg_to_hcd(hsotg);
5311 dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
5312
5313 if (!hcd) {
5314 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
5315 __func__);
5316 return;
5317 }
5318
5319 if (!IS_ERR_OR_NULL(hsotg->uphy))
5320 otg_set_host(hsotg->uphy->otg, NULL);
5321
5322 usb_remove_hcd(hcd);
5323 hsotg->priv = NULL;
5324
5325 kmem_cache_destroy(hsotg->desc_gen_cache);
5326 kmem_cache_destroy(hsotg->desc_hsisoc_cache);
5327
5328 dwc2_hcd_release(hsotg);
5329 usb_put_hcd(hcd);
5330
5331#ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5332 kfree(hsotg->last_frame_num_array);
5333 kfree(hsotg->frame_num_array);
5334#endif
5335}
5336
5337/**
5338 * dwc2_backup_host_registers() - Backup controller host registers.
5339 * When suspending usb bus, registers needs to be backuped
5340 * if controller power is disabled once suspended.
5341 *
5342 * @hsotg: Programming view of the DWC_otg controller
5343 */
5344int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
5345{
5346 struct dwc2_hregs_backup *hr;
5347 int i;
5348
5349 dev_dbg(hsotg->dev, "%s\n", __func__);
5350
5351 /* Backup Host regs */
5352 hr = &hsotg->hr_backup;
5353 hr->hcfg = dwc2_readl(hsotg->regs + HCFG);
5354 hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
5355 for (i = 0; i < hsotg->params.host_channels; ++i)
5356 hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i));
5357
5358 hr->hprt0 = dwc2_read_hprt0(hsotg);
5359 hr->hfir = dwc2_readl(hsotg->regs + HFIR);
5360 hr->hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
5361 hr->valid = true;
5362
5363 return 0;
5364}
5365
5366/**
5367 * dwc2_restore_host_registers() - Restore controller host registers.
5368 * When resuming usb bus, device registers needs to be restored
5369 * if controller power were disabled.
5370 *
5371 * @hsotg: Programming view of the DWC_otg controller
5372 */
5373int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
5374{
5375 struct dwc2_hregs_backup *hr;
5376 int i;
5377
5378 dev_dbg(hsotg->dev, "%s\n", __func__);
5379
5380 /* Restore host regs */
5381 hr = &hsotg->hr_backup;
5382 if (!hr->valid) {
5383 dev_err(hsotg->dev, "%s: no host registers to restore\n",
5384 __func__);
5385 return -EINVAL;
5386 }
5387 hr->valid = false;
5388
5389 dwc2_writel(hr->hcfg, hsotg->regs + HCFG);
5390 dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK);
5391
5392 for (i = 0; i < hsotg->params.host_channels; ++i)
5393 dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i));
5394
5395 dwc2_writel(hr->hprt0, hsotg->regs + HPRT0);
5396 dwc2_writel(hr->hfir, hsotg->regs + HFIR);
5397 dwc2_writel(hr->hptxfsiz, hsotg->regs + HPTXFSIZ);
5398 hsotg->frame_number = 0;
5399
5400 return 0;
5401}
5402
5403/**
5404 * dwc2_host_enter_hibernation() - Put controller in Hibernation.
5405 *
5406 * @hsotg: Programming view of the DWC_otg controller
5407 */
5408int dwc2_host_enter_hibernation(struct dwc2_hsotg *hsotg)
5409{
5410 unsigned long flags;
5411 int ret = 0;
5412 u32 hprt0;
5413 u32 pcgcctl;
5414 u32 gusbcfg;
5415 u32 gpwrdn;
5416
5417 dev_dbg(hsotg->dev, "Preparing host for hibernation\n");
5418 ret = dwc2_backup_global_registers(hsotg);
5419 if (ret) {
5420 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
5421 __func__);
5422 return ret;
5423 }
5424 ret = dwc2_backup_host_registers(hsotg);
5425 if (ret) {
5426 dev_err(hsotg->dev, "%s: failed to backup host registers\n",
5427 __func__);
5428 return ret;
5429 }
5430
5431 /* Enter USB Suspend Mode */
5432 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
5433 hprt0 |= HPRT0_SUSP;
5434 hprt0 &= ~HPRT0_ENA;
5435 dwc2_writel(hprt0, hsotg->regs + HPRT0);
5436
5437 /* Wait for the HPRT0.PrtSusp register field to be set */
5438 if (dwc2_hsotg_wait_bit_set(hsotg, HPRT0, HPRT0_SUSP, 300))
5439 dev_warn(hsotg->dev, "Suspend wasn't generated\n");
5440
5441 /*
5442 * We need to disable interrupts to prevent servicing of any IRQ
5443 * during going to hibernation
5444 */
5445 spin_lock_irqsave(&hsotg->lock, flags);
5446 hsotg->lx_state = DWC2_L2;
5447
5448 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
5449 if (gusbcfg & GUSBCFG_ULPI_UTMI_SEL) {
5450 /* ULPI interface */
5451 /* Suspend the Phy Clock */
5452 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
5453 pcgcctl |= PCGCTL_STOPPCLK;
5454 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
5455 udelay(10);
5456
5457 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5458 gpwrdn |= GPWRDN_PMUACTV;
5459 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5460 udelay(10);
5461 } else {
5462 /* UTMI+ Interface */
5463 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5464 gpwrdn |= GPWRDN_PMUACTV;
5465 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5466 udelay(10);
5467
5468 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
5469 pcgcctl |= PCGCTL_STOPPCLK;
5470 dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
5471 udelay(10);
5472 }
5473
5474 /* Enable interrupts from wake up logic */
5475 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5476 gpwrdn |= GPWRDN_PMUINTSEL;
5477 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5478 udelay(10);
5479
5480 /* Unmask host mode interrupts in GPWRDN */
5481 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5482 gpwrdn |= GPWRDN_DISCONN_DET_MSK;
5483 gpwrdn |= GPWRDN_LNSTSCHG_MSK;
5484 gpwrdn |= GPWRDN_STS_CHGINT_MSK;
5485 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5486 udelay(10);
5487
5488 /* Enable Power Down Clamp */
5489 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5490 gpwrdn |= GPWRDN_PWRDNCLMP;
5491 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5492 udelay(10);
5493
5494 /* Switch off VDD */
5495 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5496 gpwrdn |= GPWRDN_PWRDNSWTCH;
5497 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5498
5499 hsotg->hibernated = 1;
5500 hsotg->bus_suspended = 1;
5501 dev_dbg(hsotg->dev, "Host hibernation completed\n");
5502 spin_unlock_irqrestore(&hsotg->lock, flags);
5503 return ret;
5504}
5505
5506/*
5507 * dwc2_host_exit_hibernation()
5508 *
5509 * @hsotg: Programming view of the DWC_otg controller
5510 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5511 * @param reset: indicates whether resume is initiated by Reset.
5512 *
5513 * Return: non-zero if failed to enter to hibernation.
5514 *
5515 * This function is for exiting from Host mode hibernation by
5516 * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
5517 */
5518int dwc2_host_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
5519 int reset)
5520{
5521 u32 gpwrdn;
5522 u32 hprt0;
5523 int ret = 0;
5524 struct dwc2_gregs_backup *gr;
5525 struct dwc2_hregs_backup *hr;
5526
5527 gr = &hsotg->gr_backup;
5528 hr = &hsotg->hr_backup;
5529
5530 dev_dbg(hsotg->dev,
5531 "%s: called with rem_wakeup = %d reset = %d\n",
5532 __func__, rem_wakeup, reset);
5533
5534 dwc2_hib_restore_common(hsotg, rem_wakeup, 1);
5535 hsotg->hibernated = 0;
5536
5537 /*
5538 * This step is not described in functional spec but if not wait for
5539 * this delay, mismatch interrupts occurred because just after restore
5540 * core is in Device mode(gintsts.curmode == 0)
5541 */
5542 mdelay(100);
5543
5544 /* Clear all pending interupts */
5545 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
5546
5547 /* De-assert Restore */
5548 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5549 gpwrdn &= ~GPWRDN_RESTORE;
5550 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5551 udelay(10);
5552
5553 /* Restore GUSBCFG, HCFG */
5554 dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG);
5555 dwc2_writel(hr->hcfg, hsotg->regs + HCFG);
5556
5557 /* De-assert Wakeup Logic */
5558 gpwrdn = dwc2_readl(hsotg->regs + GPWRDN);
5559 gpwrdn &= ~GPWRDN_PMUACTV;
5560 dwc2_writel(gpwrdn, hsotg->regs + GPWRDN);
5561 udelay(10);
5562
5563 hprt0 = hr->hprt0;
5564 hprt0 |= HPRT0_PWR;
5565 hprt0 &= ~HPRT0_ENA;
5566 hprt0 &= ~HPRT0_SUSP;
5567 dwc2_writel(hprt0, hsotg->regs + HPRT0);
5568
5569 hprt0 = hr->hprt0;
5570 hprt0 |= HPRT0_PWR;
5571 hprt0 &= ~HPRT0_ENA;
5572 hprt0 &= ~HPRT0_SUSP;
5573
5574 if (reset) {
5575 hprt0 |= HPRT0_RST;
5576 dwc2_writel(hprt0, hsotg->regs + HPRT0);
5577
5578 /* Wait for Resume time and then program HPRT again */
5579 mdelay(60);
5580 hprt0 &= ~HPRT0_RST;
5581 dwc2_writel(hprt0, hsotg->regs + HPRT0);
5582 } else {
5583 hprt0 |= HPRT0_RES;
5584 dwc2_writel(hprt0, hsotg->regs + HPRT0);
5585
5586 /* Wait for Resume time and then program HPRT again */
5587 mdelay(100);
5588 hprt0 &= ~HPRT0_RES;
5589 dwc2_writel(hprt0, hsotg->regs + HPRT0);
5590 }
5591 /* Clear all interrupt status */
5592 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
5593 hprt0 |= HPRT0_CONNDET;
5594 hprt0 |= HPRT0_ENACHG;
5595 hprt0 &= ~HPRT0_ENA;
5596 dwc2_writel(hprt0, hsotg->regs + HPRT0);
5597
5598 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
5599
5600 /* Clear all pending interupts */
5601 dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
5602
5603 /* Restore global registers */
5604 ret = dwc2_restore_global_registers(hsotg);
5605 if (ret) {
5606 dev_err(hsotg->dev, "%s: failed to restore registers\n",
5607 __func__);
5608 return ret;
5609 }
5610
5611 /* Restore host registers */
5612 ret = dwc2_restore_host_registers(hsotg);
5613 if (ret) {
5614 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
5615 __func__);
5616 return ret;
5617 }
5618
5619 hsotg->hibernated = 0;
5620 hsotg->bus_suspended = 0;
5621 hsotg->lx_state = DWC2_L0;
5622 dev_dbg(hsotg->dev, "Host hibernation restore complete\n");
5623 return ret;
5624}