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1/*
2 * MPC83xx/85xx/86xx PCI/PCIE support routing.
3 *
4 * Copyright 2007-2012 Freescale Semiconductor, Inc.
5 * Copyright 2008-2009 MontaVista Software, Inc.
6 *
7 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
8 * Recode: ZHANG WEI <wei.zhang@freescale.com>
9 * Rewrite the routing for Frescale PCI and PCI Express
10 * Roy Zang <tie-fei.zang@freescale.com>
11 * MPC83xx PCI-Express support:
12 * Tony Li <tony.li@freescale.com>
13 * Anton Vorontsov <avorontsov@ru.mvista.com>
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20#include <linux/kernel.h>
21#include <linux/pci.h>
22#include <linux/delay.h>
23#include <linux/string.h>
24#include <linux/fsl/edac.h>
25#include <linux/init.h>
26#include <linux/interrupt.h>
27#include <linux/memblock.h>
28#include <linux/log2.h>
29#include <linux/platform_device.h>
30#include <linux/slab.h>
31#include <linux/suspend.h>
32#include <linux/syscore_ops.h>
33#include <linux/uaccess.h>
34
35#include <asm/io.h>
36#include <asm/prom.h>
37#include <asm/pci-bridge.h>
38#include <asm/ppc-pci.h>
39#include <asm/machdep.h>
40#include <asm/mpc85xx.h>
41#include <asm/disassemble.h>
42#include <asm/ppc-opcode.h>
43#include <sysdev/fsl_soc.h>
44#include <sysdev/fsl_pci.h>
45
46static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
47
48static void quirk_fsl_pcie_early(struct pci_dev *dev)
49{
50 u8 hdr_type;
51
52 /* if we aren't a PCIe don't bother */
53 if (!pci_is_pcie(dev))
54 return;
55
56 /* if we aren't in host mode don't bother */
57 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type);
58 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
59 return;
60
61 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
62 fsl_pcie_bus_fixup = 1;
63 return;
64}
65
66static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
67 int, int, u32 *);
68
69static int fsl_pcie_check_link(struct pci_controller *hose)
70{
71 u32 val = 0;
72
73 if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
74 if (hose->ops->read == fsl_indirect_read_config)
75 __indirect_read_config(hose, hose->first_busno, 0,
76 PCIE_LTSSM, 4, &val);
77 else
78 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
79 if (val < PCIE_LTSSM_L0)
80 return 1;
81 } else {
82 struct ccsr_pci __iomem *pci = hose->private_data;
83 /* for PCIe IP rev 3.0 or greater use CSR0 for link state */
84 val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
85 >> PEX_CSR0_LTSSM_SHIFT;
86 if (val != PEX_CSR0_LTSSM_L0)
87 return 1;
88 }
89
90 return 0;
91}
92
93static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
94 int offset, int len, u32 *val)
95{
96 struct pci_controller *hose = pci_bus_to_host(bus);
97
98 if (fsl_pcie_check_link(hose))
99 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
100 else
101 hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
102
103 return indirect_read_config(bus, devfn, offset, len, val);
104}
105
106#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
107
108static struct pci_ops fsl_indirect_pcie_ops =
109{
110 .read = fsl_indirect_read_config,
111 .write = indirect_write_config,
112};
113
114static u64 pci64_dma_offset;
115
116#ifdef CONFIG_SWIOTLB
117static void setup_swiotlb_ops(struct pci_controller *hose)
118{
119 if (ppc_swiotlb_enable) {
120 hose->controller_ops.dma_dev_setup = pci_dma_dev_setup_swiotlb;
121 set_pci_dma_ops(&swiotlb_dma_ops);
122 }
123}
124#else
125static inline void setup_swiotlb_ops(struct pci_controller *hose) {}
126#endif
127
128static int fsl_pci_dma_set_mask(struct device *dev, u64 dma_mask)
129{
130 if (!dev->dma_mask || !dma_supported(dev, dma_mask))
131 return -EIO;
132
133 /*
134 * Fix up PCI devices that are able to DMA to the large inbound
135 * mapping that allows addressing any RAM address from across PCI.
136 */
137 if (dev_is_pci(dev) && dma_mask >= pci64_dma_offset * 2 - 1) {
138 set_dma_ops(dev, &dma_direct_ops);
139 set_dma_offset(dev, pci64_dma_offset);
140 }
141
142 *dev->dma_mask = dma_mask;
143 return 0;
144}
145
146static int setup_one_atmu(struct ccsr_pci __iomem *pci,
147 unsigned int index, const struct resource *res,
148 resource_size_t offset)
149{
150 resource_size_t pci_addr = res->start - offset;
151 resource_size_t phys_addr = res->start;
152 resource_size_t size = resource_size(res);
153 u32 flags = 0x80044000; /* enable & mem R/W */
154 unsigned int i;
155
156 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
157 (u64)res->start, (u64)size);
158
159 if (res->flags & IORESOURCE_PREFETCH)
160 flags |= 0x10000000; /* enable relaxed ordering */
161
162 for (i = 0; size > 0; i++) {
163 unsigned int bits = min_t(u32, ilog2(size),
164 __ffs(pci_addr | phys_addr));
165
166 if (index + i >= 5)
167 return -1;
168
169 out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
170 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
171 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
172 out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
173
174 pci_addr += (resource_size_t)1U << bits;
175 phys_addr += (resource_size_t)1U << bits;
176 size -= (resource_size_t)1U << bits;
177 }
178
179 return i;
180}
181
182static bool is_kdump(void)
183{
184 struct device_node *node;
185
186 node = of_find_node_by_type(NULL, "memory");
187 if (!node) {
188 WARN_ON_ONCE(1);
189 return false;
190 }
191
192 return of_property_read_bool(node, "linux,usable-memory");
193}
194
195/* atmu setup for fsl pci/pcie controller */
196static void setup_pci_atmu(struct pci_controller *hose)
197{
198 struct ccsr_pci __iomem *pci = hose->private_data;
199 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
200 u64 mem, sz, paddr_hi = 0;
201 u64 offset = 0, paddr_lo = ULLONG_MAX;
202 u32 pcicsrbar = 0, pcicsrbar_sz;
203 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
204 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
205 const char *name = hose->dn->full_name;
206 const u64 *reg;
207 int len;
208 bool setup_inbound;
209
210 /*
211 * If this is kdump, we don't want to trigger a bunch of PCI
212 * errors by closing the window on in-flight DMA.
213 *
214 * We still run most of the function's logic so that things like
215 * hose->dma_window_size still get set.
216 */
217 setup_inbound = !is_kdump();
218
219 if (of_device_is_compatible(hose->dn, "fsl,bsc9132-pcie")) {
220 /*
221 * BSC9132 Rev1.0 has an issue where all the PEX inbound
222 * windows have implemented the default target value as 0xf
223 * for CCSR space.In all Freescale legacy devices the target
224 * of 0xf is reserved for local memory space. 9132 Rev1.0
225 * now has local mempry space mapped to target 0x0 instead of
226 * 0xf. Hence adding a workaround to remove the target 0xf
227 * defined for memory space from Inbound window attributes.
228 */
229 piwar &= ~PIWAR_TGI_LOCAL;
230 }
231
232 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
233 if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
234 win_idx = 2;
235 start_idx = 0;
236 end_idx = 3;
237 }
238 }
239
240 /* Disable all windows (except powar0 since it's ignored) */
241 for(i = 1; i < 5; i++)
242 out_be32(&pci->pow[i].powar, 0);
243
244 if (setup_inbound) {
245 for (i = start_idx; i < end_idx; i++)
246 out_be32(&pci->piw[i].piwar, 0);
247 }
248
249 /* Setup outbound MEM window */
250 for(i = 0, j = 1; i < 3; i++) {
251 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
252 continue;
253
254 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
255 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
256
257 /* We assume all memory resources have the same offset */
258 offset = hose->mem_offset[i];
259 n = setup_one_atmu(pci, j, &hose->mem_resources[i], offset);
260
261 if (n < 0 || j >= 5) {
262 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
263 hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
264 } else
265 j += n;
266 }
267
268 /* Setup outbound IO window */
269 if (hose->io_resource.flags & IORESOURCE_IO) {
270 if (j >= 5) {
271 pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
272 } else {
273 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
274 "phy base 0x%016llx.\n",
275 (u64)hose->io_resource.start,
276 (u64)resource_size(&hose->io_resource),
277 (u64)hose->io_base_phys);
278 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
279 out_be32(&pci->pow[j].potear, 0);
280 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
281 /* Enable, IO R/W */
282 out_be32(&pci->pow[j].powar, 0x80088000
283 | (ilog2(hose->io_resource.end
284 - hose->io_resource.start + 1) - 1));
285 }
286 }
287
288 /* convert to pci address space */
289 paddr_hi -= offset;
290 paddr_lo -= offset;
291
292 if (paddr_hi == paddr_lo) {
293 pr_err("%s: No outbound window space\n", name);
294 return;
295 }
296
297 if (paddr_lo == 0) {
298 pr_err("%s: No space for inbound window\n", name);
299 return;
300 }
301
302 /* setup PCSRBAR/PEXCSRBAR */
303 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
304 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
305 pcicsrbar_sz = ~pcicsrbar_sz + 1;
306
307 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
308 (paddr_lo > 0x100000000ull))
309 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
310 else
311 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
312 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
313
314 paddr_lo = min(paddr_lo, (u64)pcicsrbar);
315
316 pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
317
318 /* Setup inbound mem window */
319 mem = memblock_end_of_DRAM();
320 pr_info("%s: end of DRAM %llx\n", __func__, mem);
321
322 /*
323 * The msi-address-64 property, if it exists, indicates the physical
324 * address of the MSIIR register. Normally, this register is located
325 * inside CCSR, so the ATMU that covers all of CCSR is used. But if
326 * this property exists, then we normally need to create a new ATMU
327 * for it. For now, however, we cheat. The only entity that creates
328 * this property is the Freescale hypervisor, and the address is
329 * specified in the partition configuration. Typically, the address
330 * is located in the page immediately after the end of DDR. If so, we
331 * can avoid allocating a new ATMU by extending the DDR ATMU by one
332 * page.
333 */
334 reg = of_get_property(hose->dn, "msi-address-64", &len);
335 if (reg && (len == sizeof(u64))) {
336 u64 address = be64_to_cpup(reg);
337
338 if ((address >= mem) && (address < (mem + PAGE_SIZE))) {
339 pr_info("%s: extending DDR ATMU to cover MSIIR", name);
340 mem += PAGE_SIZE;
341 } else {
342 /* TODO: Create a new ATMU for MSIIR */
343 pr_warn("%s: msi-address-64 address of %llx is "
344 "unsupported\n", name, address);
345 }
346 }
347
348 sz = min(mem, paddr_lo);
349 mem_log = ilog2(sz);
350
351 /* PCIe can overmap inbound & outbound since RX & TX are separated */
352 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
353 /* Size window to exact size if power-of-two or one size up */
354 if ((1ull << mem_log) != mem) {
355 mem_log++;
356 if ((1ull << mem_log) > mem)
357 pr_info("%s: Setting PCI inbound window "
358 "greater than memory size\n", name);
359 }
360
361 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
362
363 if (setup_inbound) {
364 /* Setup inbound memory window */
365 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
366 out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
367 out_be32(&pci->piw[win_idx].piwar, piwar);
368 }
369
370 win_idx--;
371 hose->dma_window_base_cur = 0x00000000;
372 hose->dma_window_size = (resource_size_t)sz;
373
374 /*
375 * if we have >4G of memory setup second PCI inbound window to
376 * let devices that are 64-bit address capable to work w/o
377 * SWIOTLB and access the full range of memory
378 */
379 if (sz != mem) {
380 mem_log = ilog2(mem);
381
382 /* Size window up if we dont fit in exact power-of-2 */
383 if ((1ull << mem_log) != mem)
384 mem_log++;
385
386 piwar = (piwar & ~PIWAR_SZ_MASK) | (mem_log - 1);
387 pci64_dma_offset = 1ULL << mem_log;
388
389 if (setup_inbound) {
390 /* Setup inbound memory window */
391 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
392 out_be32(&pci->piw[win_idx].piwbear,
393 pci64_dma_offset >> 44);
394 out_be32(&pci->piw[win_idx].piwbar,
395 pci64_dma_offset >> 12);
396 out_be32(&pci->piw[win_idx].piwar, piwar);
397 }
398
399 /*
400 * install our own dma_set_mask handler to fixup dma_ops
401 * and dma_offset
402 */
403 ppc_md.dma_set_mask = fsl_pci_dma_set_mask;
404
405 pr_info("%s: Setup 64-bit PCI DMA window\n", name);
406 }
407 } else {
408 u64 paddr = 0;
409
410 if (setup_inbound) {
411 /* Setup inbound memory window */
412 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
413 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
414 out_be32(&pci->piw[win_idx].piwar,
415 (piwar | (mem_log - 1)));
416 }
417
418 win_idx--;
419 paddr += 1ull << mem_log;
420 sz -= 1ull << mem_log;
421
422 if (sz) {
423 mem_log = ilog2(sz);
424 piwar |= (mem_log - 1);
425
426 if (setup_inbound) {
427 out_be32(&pci->piw[win_idx].pitar,
428 paddr >> 12);
429 out_be32(&pci->piw[win_idx].piwbar,
430 paddr >> 12);
431 out_be32(&pci->piw[win_idx].piwar, piwar);
432 }
433
434 win_idx--;
435 paddr += 1ull << mem_log;
436 }
437
438 hose->dma_window_base_cur = 0x00000000;
439 hose->dma_window_size = (resource_size_t)paddr;
440 }
441
442 if (hose->dma_window_size < mem) {
443#ifdef CONFIG_SWIOTLB
444 ppc_swiotlb_enable = 1;
445#else
446 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
447 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
448 name);
449#endif
450 /* adjusting outbound windows could reclaim space in mem map */
451 if (paddr_hi < 0xffffffffull)
452 pr_warning("%s: WARNING: Outbound window cfg leaves "
453 "gaps in memory map. Adjusting the memory map "
454 "could reduce unnecessary bounce buffering.\n",
455 name);
456
457 pr_info("%s: DMA window size is 0x%llx\n", name,
458 (u64)hose->dma_window_size);
459 }
460}
461
462static void __init setup_pci_cmd(struct pci_controller *hose)
463{
464 u16 cmd;
465 int cap_x;
466
467 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
468 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
469 | PCI_COMMAND_IO;
470 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
471
472 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
473 if (cap_x) {
474 int pci_x_cmd = cap_x + PCI_X_CMD;
475 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
476 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
477 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
478 } else {
479 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
480 }
481}
482
483void fsl_pcibios_fixup_bus(struct pci_bus *bus)
484{
485 struct pci_controller *hose = pci_bus_to_host(bus);
486 int i, is_pcie = 0, no_link;
487
488 /* The root complex bridge comes up with bogus resources,
489 * we copy the PHB ones in.
490 *
491 * With the current generic PCI code, the PHB bus no longer
492 * has bus->resource[0..4] set, so things are a bit more
493 * tricky.
494 */
495
496 if (fsl_pcie_bus_fixup)
497 is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP);
498 no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK);
499
500 if (bus->parent == hose->bus && (is_pcie || no_link)) {
501 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) {
502 struct resource *res = bus->resource[i];
503 struct resource *par;
504
505 if (!res)
506 continue;
507 if (i == 0)
508 par = &hose->io_resource;
509 else if (i < 4)
510 par = &hose->mem_resources[i-1];
511 else par = NULL;
512
513 res->start = par ? par->start : 0;
514 res->end = par ? par->end : 0;
515 res->flags = par ? par->flags : 0;
516 }
517 }
518}
519
520int fsl_add_bridge(struct platform_device *pdev, int is_primary)
521{
522 int len;
523 struct pci_controller *hose;
524 struct resource rsrc;
525 const int *bus_range;
526 u8 hdr_type, progif;
527 struct device_node *dev;
528 struct ccsr_pci __iomem *pci;
529 u16 temp;
530 u32 svr = mfspr(SPRN_SVR);
531
532 dev = pdev->dev.of_node;
533
534 if (!of_device_is_available(dev)) {
535 pr_warning("%s: disabled\n", dev->full_name);
536 return -ENODEV;
537 }
538
539 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
540
541 /* Fetch host bridge registers address */
542 if (of_address_to_resource(dev, 0, &rsrc)) {
543 printk(KERN_WARNING "Can't get pci register base!");
544 return -ENOMEM;
545 }
546
547 /* Get bus range if any */
548 bus_range = of_get_property(dev, "bus-range", &len);
549 if (bus_range == NULL || len < 2 * sizeof(int))
550 printk(KERN_WARNING "Can't get bus-range for %s, assume"
551 " bus 0\n", dev->full_name);
552
553 pci_add_flags(PCI_REASSIGN_ALL_BUS);
554 hose = pcibios_alloc_controller(dev);
555 if (!hose)
556 return -ENOMEM;
557
558 /* set platform device as the parent */
559 hose->parent = &pdev->dev;
560 hose->first_busno = bus_range ? bus_range[0] : 0x0;
561 hose->last_busno = bus_range ? bus_range[1] : 0xff;
562
563 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
564 (u64)rsrc.start, (u64)resource_size(&rsrc));
565
566 pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
567 if (!hose->private_data)
568 goto no_bridge;
569
570 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
571 PPC_INDIRECT_TYPE_BIG_ENDIAN);
572
573 if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
574 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
575
576 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
577 /* use fsl_indirect_read_config for PCIe */
578 hose->ops = &fsl_indirect_pcie_ops;
579 /* For PCIE read HEADER_TYPE to identify controller mode */
580 early_read_config_byte(hose, 0, 0, PCI_HEADER_TYPE, &hdr_type);
581 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE)
582 goto no_bridge;
583
584 } else {
585 /* For PCI read PROG to identify controller mode */
586 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
587 if ((progif & 1) &&
588 !of_property_read_bool(dev, "fsl,pci-agent-force-enum"))
589 goto no_bridge;
590 }
591
592 setup_pci_cmd(hose);
593
594 /* check PCI express link status */
595 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
596 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
597 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
598 if (fsl_pcie_check_link(hose))
599 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
600 } else {
601 /*
602 * Set PBFR(PCI Bus Function Register)[10] = 1 to
603 * disable the combining of crossing cacheline
604 * boundary requests into one burst transaction.
605 * PCI-X operation is not affected.
606 * Fix erratum PCI 5 on MPC8548
607 */
608#define PCI_BUS_FUNCTION 0x44
609#define PCI_BUS_FUNCTION_MDS 0x400 /* Master disable streaming */
610 if (((SVR_SOC_VER(svr) == SVR_8543) ||
611 (SVR_SOC_VER(svr) == SVR_8545) ||
612 (SVR_SOC_VER(svr) == SVR_8547) ||
613 (SVR_SOC_VER(svr) == SVR_8548)) &&
614 !early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX)) {
615 early_read_config_word(hose, 0, 0,
616 PCI_BUS_FUNCTION, &temp);
617 temp |= PCI_BUS_FUNCTION_MDS;
618 early_write_config_word(hose, 0, 0,
619 PCI_BUS_FUNCTION, temp);
620 }
621 }
622
623 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
624 "Firmware bus number: %d->%d\n",
625 (unsigned long long)rsrc.start, hose->first_busno,
626 hose->last_busno);
627
628 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
629 hose, hose->cfg_addr, hose->cfg_data);
630
631 /* Interpret the "ranges" property */
632 /* This also maps the I/O region and sets isa_io/mem_base */
633 pci_process_bridge_OF_ranges(hose, dev, is_primary);
634
635 /* Setup PEX window registers */
636 setup_pci_atmu(hose);
637
638 /* Set up controller operations */
639 setup_swiotlb_ops(hose);
640
641 return 0;
642
643no_bridge:
644 iounmap(hose->private_data);
645 /* unmap cfg_data & cfg_addr separately if not on same page */
646 if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
647 ((unsigned long)hose->cfg_addr & PAGE_MASK))
648 iounmap(hose->cfg_data);
649 iounmap(hose->cfg_addr);
650 pcibios_free_controller(hose);
651 return -ENODEV;
652}
653#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
654
655DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID,
656 quirk_fsl_pcie_early);
657
658#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
659struct mpc83xx_pcie_priv {
660 void __iomem *cfg_type0;
661 void __iomem *cfg_type1;
662 u32 dev_base;
663};
664
665struct pex_inbound_window {
666 u32 ar;
667 u32 tar;
668 u32 barl;
669 u32 barh;
670};
671
672/*
673 * With the convention of u-boot, the PCIE outbound window 0 serves
674 * as configuration transactions outbound.
675 */
676#define PEX_OUTWIN0_BAR 0xCA4
677#define PEX_OUTWIN0_TAL 0xCA8
678#define PEX_OUTWIN0_TAH 0xCAC
679#define PEX_RC_INWIN_BASE 0xE60
680#define PEX_RCIWARn_EN 0x1
681
682static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
683{
684 struct pci_controller *hose = pci_bus_to_host(bus);
685
686 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
687 return PCIBIOS_DEVICE_NOT_FOUND;
688 /*
689 * Workaround for the HW bug: for Type 0 configure transactions the
690 * PCI-E controller does not check the device number bits and just
691 * assumes that the device number bits are 0.
692 */
693 if (bus->number == hose->first_busno ||
694 bus->primary == hose->first_busno) {
695 if (devfn & 0xf8)
696 return PCIBIOS_DEVICE_NOT_FOUND;
697 }
698
699 if (ppc_md.pci_exclude_device) {
700 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
701 return PCIBIOS_DEVICE_NOT_FOUND;
702 }
703
704 return PCIBIOS_SUCCESSFUL;
705}
706
707static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
708 unsigned int devfn, int offset)
709{
710 struct pci_controller *hose = pci_bus_to_host(bus);
711 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
712 u32 dev_base = bus->number << 24 | devfn << 16;
713 int ret;
714
715 ret = mpc83xx_pcie_exclude_device(bus, devfn);
716 if (ret)
717 return NULL;
718
719 offset &= 0xfff;
720
721 /* Type 0 */
722 if (bus->number == hose->first_busno)
723 return pcie->cfg_type0 + offset;
724
725 if (pcie->dev_base == dev_base)
726 goto mapped;
727
728 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
729
730 pcie->dev_base = dev_base;
731mapped:
732 return pcie->cfg_type1 + offset;
733}
734
735static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
736 int offset, int len, u32 val)
737{
738 struct pci_controller *hose = pci_bus_to_host(bus);
739
740 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
741 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
742 val &= 0xffffff00;
743
744 return pci_generic_config_write(bus, devfn, offset, len, val);
745}
746
747static struct pci_ops mpc83xx_pcie_ops = {
748 .map_bus = mpc83xx_pcie_remap_cfg,
749 .read = pci_generic_config_read,
750 .write = mpc83xx_pcie_write_config,
751};
752
753static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
754 struct resource *reg)
755{
756 struct mpc83xx_pcie_priv *pcie;
757 u32 cfg_bar;
758 int ret = -ENOMEM;
759
760 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
761 if (!pcie)
762 return ret;
763
764 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
765 if (!pcie->cfg_type0)
766 goto err0;
767
768 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
769 if (!cfg_bar) {
770 /* PCI-E isn't configured. */
771 ret = -ENODEV;
772 goto err1;
773 }
774
775 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
776 if (!pcie->cfg_type1)
777 goto err1;
778
779 WARN_ON(hose->dn->data);
780 hose->dn->data = pcie;
781 hose->ops = &mpc83xx_pcie_ops;
782 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
783
784 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
785 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
786
787 if (fsl_pcie_check_link(hose))
788 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
789
790 return 0;
791err1:
792 iounmap(pcie->cfg_type0);
793err0:
794 kfree(pcie);
795 return ret;
796
797}
798
799int __init mpc83xx_add_bridge(struct device_node *dev)
800{
801 int ret;
802 int len;
803 struct pci_controller *hose;
804 struct resource rsrc_reg;
805 struct resource rsrc_cfg;
806 const int *bus_range;
807 int primary;
808
809 is_mpc83xx_pci = 1;
810
811 if (!of_device_is_available(dev)) {
812 pr_warning("%s: disabled by the firmware.\n",
813 dev->full_name);
814 return -ENODEV;
815 }
816 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
817
818 /* Fetch host bridge registers address */
819 if (of_address_to_resource(dev, 0, &rsrc_reg)) {
820 printk(KERN_WARNING "Can't get pci register base!\n");
821 return -ENOMEM;
822 }
823
824 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
825
826 if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
827 printk(KERN_WARNING
828 "No pci config register base in dev tree, "
829 "using default\n");
830 /*
831 * MPC83xx supports up to two host controllers
832 * one at 0x8500 has config space registers at 0x8300
833 * one at 0x8600 has config space registers at 0x8380
834 */
835 if ((rsrc_reg.start & 0xfffff) == 0x8500)
836 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
837 else if ((rsrc_reg.start & 0xfffff) == 0x8600)
838 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
839 }
840 /*
841 * Controller at offset 0x8500 is primary
842 */
843 if ((rsrc_reg.start & 0xfffff) == 0x8500)
844 primary = 1;
845 else
846 primary = 0;
847
848 /* Get bus range if any */
849 bus_range = of_get_property(dev, "bus-range", &len);
850 if (bus_range == NULL || len < 2 * sizeof(int)) {
851 printk(KERN_WARNING "Can't get bus-range for %s, assume"
852 " bus 0\n", dev->full_name);
853 }
854
855 pci_add_flags(PCI_REASSIGN_ALL_BUS);
856 hose = pcibios_alloc_controller(dev);
857 if (!hose)
858 return -ENOMEM;
859
860 hose->first_busno = bus_range ? bus_range[0] : 0;
861 hose->last_busno = bus_range ? bus_range[1] : 0xff;
862
863 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
864 ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
865 if (ret)
866 goto err0;
867 } else {
868 setup_indirect_pci(hose, rsrc_cfg.start,
869 rsrc_cfg.start + 4, 0);
870 }
871
872 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
873 "Firmware bus number: %d->%d\n",
874 (unsigned long long)rsrc_reg.start, hose->first_busno,
875 hose->last_busno);
876
877 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
878 hose, hose->cfg_addr, hose->cfg_data);
879
880 /* Interpret the "ranges" property */
881 /* This also maps the I/O region and sets isa_io/mem_base */
882 pci_process_bridge_OF_ranges(hose, dev, primary);
883
884 return 0;
885err0:
886 pcibios_free_controller(hose);
887 return ret;
888}
889#endif /* CONFIG_PPC_83xx */
890
891u64 fsl_pci_immrbar_base(struct pci_controller *hose)
892{
893#ifdef CONFIG_PPC_83xx
894 if (is_mpc83xx_pci) {
895 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
896 struct pex_inbound_window *in;
897 int i;
898
899 /* Walk the Root Complex Inbound windows to match IMMR base */
900 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
901 for (i = 0; i < 4; i++) {
902 /* not enabled, skip */
903 if (!(in_le32(&in[i].ar) & PEX_RCIWARn_EN))
904 continue;
905
906 if (get_immrbase() == in_le32(&in[i].tar))
907 return (u64)in_le32(&in[i].barh) << 32 |
908 in_le32(&in[i].barl);
909 }
910
911 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
912 }
913#endif
914
915#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
916 if (!is_mpc83xx_pci) {
917 u32 base;
918
919 pci_bus_read_config_dword(hose->bus,
920 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
921
922 /*
923 * For PEXCSRBAR, bit 3-0 indicate prefetchable and
924 * address type. So when getting base address, these
925 * bits should be masked
926 */
927 base &= PCI_BASE_ADDRESS_MEM_MASK;
928
929 return base;
930 }
931#endif
932
933 return 0;
934}
935
936#ifdef CONFIG_E500
937static int mcheck_handle_load(struct pt_regs *regs, u32 inst)
938{
939 unsigned int rd, ra, rb, d;
940
941 rd = get_rt(inst);
942 ra = get_ra(inst);
943 rb = get_rb(inst);
944 d = get_d(inst);
945
946 switch (get_op(inst)) {
947 case 31:
948 switch (get_xop(inst)) {
949 case OP_31_XOP_LWZX:
950 case OP_31_XOP_LWBRX:
951 regs->gpr[rd] = 0xffffffff;
952 break;
953
954 case OP_31_XOP_LWZUX:
955 regs->gpr[rd] = 0xffffffff;
956 regs->gpr[ra] += regs->gpr[rb];
957 break;
958
959 case OP_31_XOP_LBZX:
960 regs->gpr[rd] = 0xff;
961 break;
962
963 case OP_31_XOP_LBZUX:
964 regs->gpr[rd] = 0xff;
965 regs->gpr[ra] += regs->gpr[rb];
966 break;
967
968 case OP_31_XOP_LHZX:
969 case OP_31_XOP_LHBRX:
970 regs->gpr[rd] = 0xffff;
971 break;
972
973 case OP_31_XOP_LHZUX:
974 regs->gpr[rd] = 0xffff;
975 regs->gpr[ra] += regs->gpr[rb];
976 break;
977
978 case OP_31_XOP_LHAX:
979 regs->gpr[rd] = ~0UL;
980 break;
981
982 case OP_31_XOP_LHAUX:
983 regs->gpr[rd] = ~0UL;
984 regs->gpr[ra] += regs->gpr[rb];
985 break;
986
987 default:
988 return 0;
989 }
990 break;
991
992 case OP_LWZ:
993 regs->gpr[rd] = 0xffffffff;
994 break;
995
996 case OP_LWZU:
997 regs->gpr[rd] = 0xffffffff;
998 regs->gpr[ra] += (s16)d;
999 break;
1000
1001 case OP_LBZ:
1002 regs->gpr[rd] = 0xff;
1003 break;
1004
1005 case OP_LBZU:
1006 regs->gpr[rd] = 0xff;
1007 regs->gpr[ra] += (s16)d;
1008 break;
1009
1010 case OP_LHZ:
1011 regs->gpr[rd] = 0xffff;
1012 break;
1013
1014 case OP_LHZU:
1015 regs->gpr[rd] = 0xffff;
1016 regs->gpr[ra] += (s16)d;
1017 break;
1018
1019 case OP_LHA:
1020 regs->gpr[rd] = ~0UL;
1021 break;
1022
1023 case OP_LHAU:
1024 regs->gpr[rd] = ~0UL;
1025 regs->gpr[ra] += (s16)d;
1026 break;
1027
1028 default:
1029 return 0;
1030 }
1031
1032 return 1;
1033}
1034
1035static int is_in_pci_mem_space(phys_addr_t addr)
1036{
1037 struct pci_controller *hose;
1038 struct resource *res;
1039 int i;
1040
1041 list_for_each_entry(hose, &hose_list, list_node) {
1042 if (!(hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG))
1043 continue;
1044
1045 for (i = 0; i < 3; i++) {
1046 res = &hose->mem_resources[i];
1047 if ((res->flags & IORESOURCE_MEM) &&
1048 addr >= res->start && addr <= res->end)
1049 return 1;
1050 }
1051 }
1052 return 0;
1053}
1054
1055int fsl_pci_mcheck_exception(struct pt_regs *regs)
1056{
1057 u32 inst;
1058 int ret;
1059 phys_addr_t addr = 0;
1060
1061 /* Let KVM/QEMU deal with the exception */
1062 if (regs->msr & MSR_GS)
1063 return 0;
1064
1065#ifdef CONFIG_PHYS_64BIT
1066 addr = mfspr(SPRN_MCARU);
1067 addr <<= 32;
1068#endif
1069 addr += mfspr(SPRN_MCAR);
1070
1071 if (is_in_pci_mem_space(addr)) {
1072 if (user_mode(regs)) {
1073 pagefault_disable();
1074 ret = get_user(regs->nip, &inst);
1075 pagefault_enable();
1076 } else {
1077 ret = probe_kernel_address((void *)regs->nip, inst);
1078 }
1079
1080 if (!ret && mcheck_handle_load(regs, inst)) {
1081 regs->nip += 4;
1082 return 1;
1083 }
1084 }
1085
1086 return 0;
1087}
1088#endif
1089
1090#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
1091static const struct of_device_id pci_ids[] = {
1092 { .compatible = "fsl,mpc8540-pci", },
1093 { .compatible = "fsl,mpc8548-pcie", },
1094 { .compatible = "fsl,mpc8610-pci", },
1095 { .compatible = "fsl,mpc8641-pcie", },
1096 { .compatible = "fsl,qoriq-pcie", },
1097 { .compatible = "fsl,qoriq-pcie-v2.1", },
1098 { .compatible = "fsl,qoriq-pcie-v2.2", },
1099 { .compatible = "fsl,qoriq-pcie-v2.3", },
1100 { .compatible = "fsl,qoriq-pcie-v2.4", },
1101 { .compatible = "fsl,qoriq-pcie-v3.0", },
1102
1103 /*
1104 * The following entries are for compatibility with older device
1105 * trees.
1106 */
1107 { .compatible = "fsl,p1022-pcie", },
1108 { .compatible = "fsl,p4080-pcie", },
1109
1110 {},
1111};
1112
1113struct device_node *fsl_pci_primary;
1114
1115void fsl_pci_assign_primary(void)
1116{
1117 struct device_node *np;
1118
1119 /* Callers can specify the primary bus using other means. */
1120 if (fsl_pci_primary)
1121 return;
1122
1123 /* If a PCI host bridge contains an ISA node, it's primary. */
1124 np = of_find_node_by_type(NULL, "isa");
1125 while ((fsl_pci_primary = of_get_parent(np))) {
1126 of_node_put(np);
1127 np = fsl_pci_primary;
1128
1129 if (of_match_node(pci_ids, np) && of_device_is_available(np))
1130 return;
1131 }
1132
1133 /*
1134 * If there's no PCI host bridge with ISA, arbitrarily
1135 * designate one as primary. This can go away once
1136 * various bugs with primary-less systems are fixed.
1137 */
1138 for_each_matching_node(np, pci_ids) {
1139 if (of_device_is_available(np)) {
1140 fsl_pci_primary = np;
1141 of_node_put(np);
1142 return;
1143 }
1144 }
1145}
1146
1147#ifdef CONFIG_PM_SLEEP
1148static irqreturn_t fsl_pci_pme_handle(int irq, void *dev_id)
1149{
1150 struct pci_controller *hose = dev_id;
1151 struct ccsr_pci __iomem *pci = hose->private_data;
1152 u32 dr;
1153
1154 dr = in_be32(&pci->pex_pme_mes_dr);
1155 if (!dr)
1156 return IRQ_NONE;
1157
1158 out_be32(&pci->pex_pme_mes_dr, dr);
1159
1160 return IRQ_HANDLED;
1161}
1162
1163static int fsl_pci_pme_probe(struct pci_controller *hose)
1164{
1165 struct ccsr_pci __iomem *pci;
1166 struct pci_dev *dev;
1167 int pme_irq;
1168 int res;
1169 u16 pms;
1170
1171 /* Get hose's pci_dev */
1172 dev = list_first_entry(&hose->bus->devices, typeof(*dev), bus_list);
1173
1174 /* PME Disable */
1175 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms);
1176 pms &= ~PCI_PM_CTRL_PME_ENABLE;
1177 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms);
1178
1179 pme_irq = irq_of_parse_and_map(hose->dn, 0);
1180 if (!pme_irq) {
1181 dev_err(&dev->dev, "Failed to map PME interrupt.\n");
1182
1183 return -ENXIO;
1184 }
1185
1186 res = devm_request_irq(hose->parent, pme_irq,
1187 fsl_pci_pme_handle,
1188 IRQF_SHARED,
1189 "[PCI] PME", hose);
1190 if (res < 0) {
1191 dev_err(&dev->dev, "Unable to request irq %d for PME\n", pme_irq);
1192 irq_dispose_mapping(pme_irq);
1193
1194 return -ENODEV;
1195 }
1196
1197 pci = hose->private_data;
1198
1199 /* Enable PTOD, ENL23D & EXL23D */
1200 clrbits32(&pci->pex_pme_mes_disr,
1201 PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
1202
1203 out_be32(&pci->pex_pme_mes_ier, 0);
1204 setbits32(&pci->pex_pme_mes_ier,
1205 PME_DISR_EN_PTOD | PME_DISR_EN_ENL23D | PME_DISR_EN_EXL23D);
1206
1207 /* PME Enable */
1208 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pms);
1209 pms |= PCI_PM_CTRL_PME_ENABLE;
1210 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pms);
1211
1212 return 0;
1213}
1214
1215static void send_pme_turnoff_message(struct pci_controller *hose)
1216{
1217 struct ccsr_pci __iomem *pci = hose->private_data;
1218 u32 dr;
1219 int i;
1220
1221 /* Send PME_Turn_Off Message Request */
1222 setbits32(&pci->pex_pmcr, PEX_PMCR_PTOMR);
1223
1224 /* Wait trun off done */
1225 for (i = 0; i < 150; i++) {
1226 dr = in_be32(&pci->pex_pme_mes_dr);
1227 if (dr) {
1228 out_be32(&pci->pex_pme_mes_dr, dr);
1229 break;
1230 }
1231
1232 udelay(1000);
1233 }
1234}
1235
1236static void fsl_pci_syscore_do_suspend(struct pci_controller *hose)
1237{
1238 send_pme_turnoff_message(hose);
1239}
1240
1241static int fsl_pci_syscore_suspend(void)
1242{
1243 struct pci_controller *hose, *tmp;
1244
1245 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1246 fsl_pci_syscore_do_suspend(hose);
1247
1248 return 0;
1249}
1250
1251static void fsl_pci_syscore_do_resume(struct pci_controller *hose)
1252{
1253 struct ccsr_pci __iomem *pci = hose->private_data;
1254 u32 dr;
1255 int i;
1256
1257 /* Send Exit L2 State Message */
1258 setbits32(&pci->pex_pmcr, PEX_PMCR_EXL2S);
1259
1260 /* Wait exit done */
1261 for (i = 0; i < 150; i++) {
1262 dr = in_be32(&pci->pex_pme_mes_dr);
1263 if (dr) {
1264 out_be32(&pci->pex_pme_mes_dr, dr);
1265 break;
1266 }
1267
1268 udelay(1000);
1269 }
1270
1271 setup_pci_atmu(hose);
1272}
1273
1274static void fsl_pci_syscore_resume(void)
1275{
1276 struct pci_controller *hose, *tmp;
1277
1278 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1279 fsl_pci_syscore_do_resume(hose);
1280}
1281
1282static struct syscore_ops pci_syscore_pm_ops = {
1283 .suspend = fsl_pci_syscore_suspend,
1284 .resume = fsl_pci_syscore_resume,
1285};
1286#endif
1287
1288void fsl_pcibios_fixup_phb(struct pci_controller *phb)
1289{
1290#ifdef CONFIG_PM_SLEEP
1291 fsl_pci_pme_probe(phb);
1292#endif
1293}
1294
1295static int add_err_dev(struct platform_device *pdev)
1296{
1297 struct platform_device *errdev;
1298 struct mpc85xx_edac_pci_plat_data pd = {
1299 .of_node = pdev->dev.of_node
1300 };
1301
1302 errdev = platform_device_register_resndata(&pdev->dev,
1303 "mpc85xx-pci-edac",
1304 PLATFORM_DEVID_AUTO,
1305 pdev->resource,
1306 pdev->num_resources,
1307 &pd, sizeof(pd));
1308 if (IS_ERR(errdev))
1309 return PTR_ERR(errdev);
1310
1311 return 0;
1312}
1313
1314static int fsl_pci_probe(struct platform_device *pdev)
1315{
1316 struct device_node *node;
1317 int ret;
1318
1319 node = pdev->dev.of_node;
1320 ret = fsl_add_bridge(pdev, fsl_pci_primary == node);
1321 if (ret)
1322 return ret;
1323
1324 ret = add_err_dev(pdev);
1325 if (ret)
1326 dev_err(&pdev->dev, "couldn't register error device: %d\n",
1327 ret);
1328
1329 return 0;
1330}
1331
1332static struct platform_driver fsl_pci_driver = {
1333 .driver = {
1334 .name = "fsl-pci",
1335 .of_match_table = pci_ids,
1336 },
1337 .probe = fsl_pci_probe,
1338};
1339
1340static int __init fsl_pci_init(void)
1341{
1342#ifdef CONFIG_PM_SLEEP
1343 register_syscore_ops(&pci_syscore_pm_ops);
1344#endif
1345 return platform_driver_register(&fsl_pci_driver);
1346}
1347arch_initcall(fsl_pci_init);
1348#endif
1/*
2 * MPC83xx/85xx/86xx PCI/PCIE support routing.
3 *
4 * Copyright 2007-2011 Freescale Semiconductor, Inc.
5 * Copyright 2008-2009 MontaVista Software, Inc.
6 *
7 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
8 * Recode: ZHANG WEI <wei.zhang@freescale.com>
9 * Rewrite the routing for Frescale PCI and PCI Express
10 * Roy Zang <tie-fei.zang@freescale.com>
11 * MPC83xx PCI-Express support:
12 * Tony Li <tony.li@freescale.com>
13 * Anton Vorontsov <avorontsov@ru.mvista.com>
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
19 */
20#include <linux/kernel.h>
21#include <linux/pci.h>
22#include <linux/delay.h>
23#include <linux/string.h>
24#include <linux/init.h>
25#include <linux/bootmem.h>
26#include <linux/memblock.h>
27#include <linux/log2.h>
28#include <linux/slab.h>
29
30#include <asm/io.h>
31#include <asm/prom.h>
32#include <asm/pci-bridge.h>
33#include <asm/machdep.h>
34#include <sysdev/fsl_soc.h>
35#include <sysdev/fsl_pci.h>
36
37static int fsl_pcie_bus_fixup, is_mpc83xx_pci;
38
39static void __init quirk_fsl_pcie_header(struct pci_dev *dev)
40{
41 u8 progif;
42
43 /* if we aren't a PCIe don't bother */
44 if (!pci_find_capability(dev, PCI_CAP_ID_EXP))
45 return;
46
47 /* if we aren't in host mode don't bother */
48 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
49 if (progif & 0x1)
50 return;
51
52 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
53 fsl_pcie_bus_fixup = 1;
54 return;
55}
56
57static int __init fsl_pcie_check_link(struct pci_controller *hose)
58{
59 u32 val;
60
61 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
62 if (val < PCIE_LTSSM_L0)
63 return 1;
64 return 0;
65}
66
67#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
68static int __init setup_one_atmu(struct ccsr_pci __iomem *pci,
69 unsigned int index, const struct resource *res,
70 resource_size_t offset)
71{
72 resource_size_t pci_addr = res->start - offset;
73 resource_size_t phys_addr = res->start;
74 resource_size_t size = resource_size(res);
75 u32 flags = 0x80044000; /* enable & mem R/W */
76 unsigned int i;
77
78 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
79 (u64)res->start, (u64)size);
80
81 if (res->flags & IORESOURCE_PREFETCH)
82 flags |= 0x10000000; /* enable relaxed ordering */
83
84 for (i = 0; size > 0; i++) {
85 unsigned int bits = min(__ilog2(size),
86 __ffs(pci_addr | phys_addr));
87
88 if (index + i >= 5)
89 return -1;
90
91 out_be32(&pci->pow[index + i].potar, pci_addr >> 12);
92 out_be32(&pci->pow[index + i].potear, (u64)pci_addr >> 44);
93 out_be32(&pci->pow[index + i].powbar, phys_addr >> 12);
94 out_be32(&pci->pow[index + i].powar, flags | (bits - 1));
95
96 pci_addr += (resource_size_t)1U << bits;
97 phys_addr += (resource_size_t)1U << bits;
98 size -= (resource_size_t)1U << bits;
99 }
100
101 return i;
102}
103
104/* atmu setup for fsl pci/pcie controller */
105static void __init setup_pci_atmu(struct pci_controller *hose,
106 struct resource *rsrc)
107{
108 struct ccsr_pci __iomem *pci;
109 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
110 u64 mem, sz, paddr_hi = 0;
111 u64 paddr_lo = ULLONG_MAX;
112 u32 pcicsrbar = 0, pcicsrbar_sz;
113 u32 piwar = PIWAR_EN | PIWAR_PF | PIWAR_TGI_LOCAL |
114 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
115 char *name = hose->dn->full_name;
116
117 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
118 (u64)rsrc->start, (u64)resource_size(rsrc));
119
120 if (of_device_is_compatible(hose->dn, "fsl,qoriq-pcie-v2.2")) {
121 win_idx = 2;
122 start_idx = 0;
123 end_idx = 3;
124 }
125
126 pci = ioremap(rsrc->start, resource_size(rsrc));
127 if (!pci) {
128 dev_err(hose->parent, "Unable to map ATMU registers\n");
129 return;
130 }
131
132 /* Disable all windows (except powar0 since it's ignored) */
133 for(i = 1; i < 5; i++)
134 out_be32(&pci->pow[i].powar, 0);
135 for (i = start_idx; i < end_idx; i++)
136 out_be32(&pci->piw[i].piwar, 0);
137
138 /* Setup outbound MEM window */
139 for(i = 0, j = 1; i < 3; i++) {
140 if (!(hose->mem_resources[i].flags & IORESOURCE_MEM))
141 continue;
142
143 paddr_lo = min(paddr_lo, (u64)hose->mem_resources[i].start);
144 paddr_hi = max(paddr_hi, (u64)hose->mem_resources[i].end);
145
146 n = setup_one_atmu(pci, j, &hose->mem_resources[i],
147 hose->pci_mem_offset);
148
149 if (n < 0 || j >= 5) {
150 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i);
151 hose->mem_resources[i].flags |= IORESOURCE_DISABLED;
152 } else
153 j += n;
154 }
155
156 /* Setup outbound IO window */
157 if (hose->io_resource.flags & IORESOURCE_IO) {
158 if (j >= 5) {
159 pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
160 } else {
161 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
162 "phy base 0x%016llx.\n",
163 (u64)hose->io_resource.start,
164 (u64)resource_size(&hose->io_resource),
165 (u64)hose->io_base_phys);
166 out_be32(&pci->pow[j].potar, (hose->io_resource.start >> 12));
167 out_be32(&pci->pow[j].potear, 0);
168 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
169 /* Enable, IO R/W */
170 out_be32(&pci->pow[j].powar, 0x80088000
171 | (__ilog2(hose->io_resource.end
172 - hose->io_resource.start + 1) - 1));
173 }
174 }
175
176 /* convert to pci address space */
177 paddr_hi -= hose->pci_mem_offset;
178 paddr_lo -= hose->pci_mem_offset;
179
180 if (paddr_hi == paddr_lo) {
181 pr_err("%s: No outbound window space\n", name);
182 return ;
183 }
184
185 if (paddr_lo == 0) {
186 pr_err("%s: No space for inbound window\n", name);
187 return ;
188 }
189
190 /* setup PCSRBAR/PEXCSRBAR */
191 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
192 early_read_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, &pcicsrbar_sz);
193 pcicsrbar_sz = ~pcicsrbar_sz + 1;
194
195 if (paddr_hi < (0x100000000ull - pcicsrbar_sz) ||
196 (paddr_lo > 0x100000000ull))
197 pcicsrbar = 0x100000000ull - pcicsrbar_sz;
198 else
199 pcicsrbar = (paddr_lo - pcicsrbar_sz) & -pcicsrbar_sz;
200 early_write_config_dword(hose, 0, 0, PCI_BASE_ADDRESS_0, pcicsrbar);
201
202 paddr_lo = min(paddr_lo, (u64)pcicsrbar);
203
204 pr_info("%s: PCICSRBAR @ 0x%x\n", name, pcicsrbar);
205
206 /* Setup inbound mem window */
207 mem = memblock_end_of_DRAM();
208 sz = min(mem, paddr_lo);
209 mem_log = __ilog2_u64(sz);
210
211 /* PCIe can overmap inbound & outbound since RX & TX are separated */
212 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
213 /* Size window to exact size if power-of-two or one size up */
214 if ((1ull << mem_log) != mem) {
215 if ((1ull << mem_log) > mem)
216 pr_info("%s: Setting PCI inbound window "
217 "greater than memory size\n", name);
218 mem_log++;
219 }
220
221 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
222
223 /* Setup inbound memory window */
224 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
225 out_be32(&pci->piw[win_idx].piwbar, 0x00000000);
226 out_be32(&pci->piw[win_idx].piwar, piwar);
227 win_idx--;
228
229 hose->dma_window_base_cur = 0x00000000;
230 hose->dma_window_size = (resource_size_t)sz;
231 } else {
232 u64 paddr = 0;
233
234 /* Setup inbound memory window */
235 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
236 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
237 out_be32(&pci->piw[win_idx].piwar, (piwar | (mem_log - 1)));
238 win_idx--;
239
240 paddr += 1ull << mem_log;
241 sz -= 1ull << mem_log;
242
243 if (sz) {
244 mem_log = __ilog2_u64(sz);
245 piwar |= (mem_log - 1);
246
247 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
248 out_be32(&pci->piw[win_idx].piwbar, paddr >> 12);
249 out_be32(&pci->piw[win_idx].piwar, piwar);
250 win_idx--;
251
252 paddr += 1ull << mem_log;
253 }
254
255 hose->dma_window_base_cur = 0x00000000;
256 hose->dma_window_size = (resource_size_t)paddr;
257 }
258
259 if (hose->dma_window_size < mem) {
260#ifndef CONFIG_SWIOTLB
261 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
262 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
263 name);
264#endif
265 /* adjusting outbound windows could reclaim space in mem map */
266 if (paddr_hi < 0xffffffffull)
267 pr_warning("%s: WARNING: Outbound window cfg leaves "
268 "gaps in memory map. Adjusting the memory map "
269 "could reduce unnecessary bounce buffering.\n",
270 name);
271
272 pr_info("%s: DMA window size is 0x%llx\n", name,
273 (u64)hose->dma_window_size);
274 }
275
276 iounmap(pci);
277}
278
279static void __init setup_pci_cmd(struct pci_controller *hose)
280{
281 u16 cmd;
282 int cap_x;
283
284 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
285 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
286 | PCI_COMMAND_IO;
287 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
288
289 cap_x = early_find_capability(hose, 0, 0, PCI_CAP_ID_PCIX);
290 if (cap_x) {
291 int pci_x_cmd = cap_x + PCI_X_CMD;
292 cmd = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
293 | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
294 early_write_config_word(hose, 0, 0, pci_x_cmd, cmd);
295 } else {
296 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
297 }
298}
299
300void fsl_pcibios_fixup_bus(struct pci_bus *bus)
301{
302 struct pci_controller *hose = pci_bus_to_host(bus);
303 int i;
304
305 if ((bus->parent == hose->bus) &&
306 ((fsl_pcie_bus_fixup &&
307 early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) ||
308 (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)))
309 {
310 for (i = 0; i < 4; ++i) {
311 struct resource *res = bus->resource[i];
312 struct resource *par = bus->parent->resource[i];
313 if (res) {
314 res->start = 0;
315 res->end = 0;
316 res->flags = 0;
317 }
318 if (res && par) {
319 res->start = par->start;
320 res->end = par->end;
321 res->flags = par->flags;
322 }
323 }
324 }
325}
326
327int __init fsl_add_bridge(struct device_node *dev, int is_primary)
328{
329 int len;
330 struct pci_controller *hose;
331 struct resource rsrc;
332 const int *bus_range;
333 u8 progif;
334
335 if (!of_device_is_available(dev)) {
336 pr_warning("%s: disabled\n", dev->full_name);
337 return -ENODEV;
338 }
339
340 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
341
342 /* Fetch host bridge registers address */
343 if (of_address_to_resource(dev, 0, &rsrc)) {
344 printk(KERN_WARNING "Can't get pci register base!");
345 return -ENOMEM;
346 }
347
348 /* Get bus range if any */
349 bus_range = of_get_property(dev, "bus-range", &len);
350 if (bus_range == NULL || len < 2 * sizeof(int))
351 printk(KERN_WARNING "Can't get bus-range for %s, assume"
352 " bus 0\n", dev->full_name);
353
354 pci_add_flags(PCI_REASSIGN_ALL_BUS);
355 hose = pcibios_alloc_controller(dev);
356 if (!hose)
357 return -ENOMEM;
358
359 hose->first_busno = bus_range ? bus_range[0] : 0x0;
360 hose->last_busno = bus_range ? bus_range[1] : 0xff;
361
362 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
363 PPC_INDIRECT_TYPE_BIG_ENDIAN);
364
365 early_read_config_byte(hose, 0, 0, PCI_CLASS_PROG, &progif);
366 if ((progif & 1) == 1) {
367 /* unmap cfg_data & cfg_addr separately if not on same page */
368 if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
369 ((unsigned long)hose->cfg_addr & PAGE_MASK))
370 iounmap(hose->cfg_data);
371 iounmap(hose->cfg_addr);
372 pcibios_free_controller(hose);
373 return 0;
374 }
375
376 setup_pci_cmd(hose);
377
378 /* check PCI express link status */
379 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
380 hose->indirect_type |= PPC_INDIRECT_TYPE_EXT_REG |
381 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
382 if (fsl_pcie_check_link(hose))
383 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
384 }
385
386 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
387 "Firmware bus number: %d->%d\n",
388 (unsigned long long)rsrc.start, hose->first_busno,
389 hose->last_busno);
390
391 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
392 hose, hose->cfg_addr, hose->cfg_data);
393
394 /* Interpret the "ranges" property */
395 /* This also maps the I/O region and sets isa_io/mem_base */
396 pci_process_bridge_OF_ranges(hose, dev, is_primary);
397
398 /* Setup PEX window registers */
399 setup_pci_atmu(hose, &rsrc);
400
401 return 0;
402}
403#endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
404
405DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_pcie_header);
406
407#if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
408struct mpc83xx_pcie_priv {
409 void __iomem *cfg_type0;
410 void __iomem *cfg_type1;
411 u32 dev_base;
412};
413
414struct pex_inbound_window {
415 u32 ar;
416 u32 tar;
417 u32 barl;
418 u32 barh;
419};
420
421/*
422 * With the convention of u-boot, the PCIE outbound window 0 serves
423 * as configuration transactions outbound.
424 */
425#define PEX_OUTWIN0_BAR 0xCA4
426#define PEX_OUTWIN0_TAL 0xCA8
427#define PEX_OUTWIN0_TAH 0xCAC
428#define PEX_RC_INWIN_BASE 0xE60
429#define PEX_RCIWARn_EN 0x1
430
431static int mpc83xx_pcie_exclude_device(struct pci_bus *bus, unsigned int devfn)
432{
433 struct pci_controller *hose = pci_bus_to_host(bus);
434
435 if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK)
436 return PCIBIOS_DEVICE_NOT_FOUND;
437 /*
438 * Workaround for the HW bug: for Type 0 configure transactions the
439 * PCI-E controller does not check the device number bits and just
440 * assumes that the device number bits are 0.
441 */
442 if (bus->number == hose->first_busno ||
443 bus->primary == hose->first_busno) {
444 if (devfn & 0xf8)
445 return PCIBIOS_DEVICE_NOT_FOUND;
446 }
447
448 if (ppc_md.pci_exclude_device) {
449 if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
450 return PCIBIOS_DEVICE_NOT_FOUND;
451 }
452
453 return PCIBIOS_SUCCESSFUL;
454}
455
456static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
457 unsigned int devfn, int offset)
458{
459 struct pci_controller *hose = pci_bus_to_host(bus);
460 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
461 u32 dev_base = bus->number << 24 | devfn << 16;
462 int ret;
463
464 ret = mpc83xx_pcie_exclude_device(bus, devfn);
465 if (ret)
466 return NULL;
467
468 offset &= 0xfff;
469
470 /* Type 0 */
471 if (bus->number == hose->first_busno)
472 return pcie->cfg_type0 + offset;
473
474 if (pcie->dev_base == dev_base)
475 goto mapped;
476
477 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, dev_base);
478
479 pcie->dev_base = dev_base;
480mapped:
481 return pcie->cfg_type1 + offset;
482}
483
484static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
485 int offset, int len, u32 *val)
486{
487 void __iomem *cfg_addr;
488
489 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
490 if (!cfg_addr)
491 return PCIBIOS_DEVICE_NOT_FOUND;
492
493 switch (len) {
494 case 1:
495 *val = in_8(cfg_addr);
496 break;
497 case 2:
498 *val = in_le16(cfg_addr);
499 break;
500 default:
501 *val = in_le32(cfg_addr);
502 break;
503 }
504
505 return PCIBIOS_SUCCESSFUL;
506}
507
508static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
509 int offset, int len, u32 val)
510{
511 struct pci_controller *hose = pci_bus_to_host(bus);
512 void __iomem *cfg_addr;
513
514 cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
515 if (!cfg_addr)
516 return PCIBIOS_DEVICE_NOT_FOUND;
517
518 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
519 if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
520 val &= 0xffffff00;
521
522 switch (len) {
523 case 1:
524 out_8(cfg_addr, val);
525 break;
526 case 2:
527 out_le16(cfg_addr, val);
528 break;
529 default:
530 out_le32(cfg_addr, val);
531 break;
532 }
533
534 return PCIBIOS_SUCCESSFUL;
535}
536
537static struct pci_ops mpc83xx_pcie_ops = {
538 .read = mpc83xx_pcie_read_config,
539 .write = mpc83xx_pcie_write_config,
540};
541
542static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
543 struct resource *reg)
544{
545 struct mpc83xx_pcie_priv *pcie;
546 u32 cfg_bar;
547 int ret = -ENOMEM;
548
549 pcie = zalloc_maybe_bootmem(sizeof(*pcie), GFP_KERNEL);
550 if (!pcie)
551 return ret;
552
553 pcie->cfg_type0 = ioremap(reg->start, resource_size(reg));
554 if (!pcie->cfg_type0)
555 goto err0;
556
557 cfg_bar = in_le32(pcie->cfg_type0 + PEX_OUTWIN0_BAR);
558 if (!cfg_bar) {
559 /* PCI-E isn't configured. */
560 ret = -ENODEV;
561 goto err1;
562 }
563
564 pcie->cfg_type1 = ioremap(cfg_bar, 0x1000);
565 if (!pcie->cfg_type1)
566 goto err1;
567
568 WARN_ON(hose->dn->data);
569 hose->dn->data = pcie;
570 hose->ops = &mpc83xx_pcie_ops;
571
572 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
573 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
574
575 if (fsl_pcie_check_link(hose))
576 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
577
578 return 0;
579err1:
580 iounmap(pcie->cfg_type0);
581err0:
582 kfree(pcie);
583 return ret;
584
585}
586
587int __init mpc83xx_add_bridge(struct device_node *dev)
588{
589 int ret;
590 int len;
591 struct pci_controller *hose;
592 struct resource rsrc_reg;
593 struct resource rsrc_cfg;
594 const int *bus_range;
595 int primary;
596
597 is_mpc83xx_pci = 1;
598
599 if (!of_device_is_available(dev)) {
600 pr_warning("%s: disabled by the firmware.\n",
601 dev->full_name);
602 return -ENODEV;
603 }
604 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
605
606 /* Fetch host bridge registers address */
607 if (of_address_to_resource(dev, 0, &rsrc_reg)) {
608 printk(KERN_WARNING "Can't get pci register base!\n");
609 return -ENOMEM;
610 }
611
612 memset(&rsrc_cfg, 0, sizeof(rsrc_cfg));
613
614 if (of_address_to_resource(dev, 1, &rsrc_cfg)) {
615 printk(KERN_WARNING
616 "No pci config register base in dev tree, "
617 "using default\n");
618 /*
619 * MPC83xx supports up to two host controllers
620 * one at 0x8500 has config space registers at 0x8300
621 * one at 0x8600 has config space registers at 0x8380
622 */
623 if ((rsrc_reg.start & 0xfffff) == 0x8500)
624 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8300;
625 else if ((rsrc_reg.start & 0xfffff) == 0x8600)
626 rsrc_cfg.start = (rsrc_reg.start & 0xfff00000) + 0x8380;
627 }
628 /*
629 * Controller at offset 0x8500 is primary
630 */
631 if ((rsrc_reg.start & 0xfffff) == 0x8500)
632 primary = 1;
633 else
634 primary = 0;
635
636 /* Get bus range if any */
637 bus_range = of_get_property(dev, "bus-range", &len);
638 if (bus_range == NULL || len < 2 * sizeof(int)) {
639 printk(KERN_WARNING "Can't get bus-range for %s, assume"
640 " bus 0\n", dev->full_name);
641 }
642
643 pci_add_flags(PCI_REASSIGN_ALL_BUS);
644 hose = pcibios_alloc_controller(dev);
645 if (!hose)
646 return -ENOMEM;
647
648 hose->first_busno = bus_range ? bus_range[0] : 0;
649 hose->last_busno = bus_range ? bus_range[1] : 0xff;
650
651 if (of_device_is_compatible(dev, "fsl,mpc8314-pcie")) {
652 ret = mpc83xx_pcie_setup(hose, &rsrc_reg);
653 if (ret)
654 goto err0;
655 } else {
656 setup_indirect_pci(hose, rsrc_cfg.start,
657 rsrc_cfg.start + 4, 0);
658 }
659
660 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
661 "Firmware bus number: %d->%d\n",
662 (unsigned long long)rsrc_reg.start, hose->first_busno,
663 hose->last_busno);
664
665 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
666 hose, hose->cfg_addr, hose->cfg_data);
667
668 /* Interpret the "ranges" property */
669 /* This also maps the I/O region and sets isa_io/mem_base */
670 pci_process_bridge_OF_ranges(hose, dev, primary);
671
672 return 0;
673err0:
674 pcibios_free_controller(hose);
675 return ret;
676}
677#endif /* CONFIG_PPC_83xx */
678
679u64 fsl_pci_immrbar_base(struct pci_controller *hose)
680{
681#ifdef CONFIG_PPC_83xx
682 if (is_mpc83xx_pci) {
683 struct mpc83xx_pcie_priv *pcie = hose->dn->data;
684 struct pex_inbound_window *in;
685 int i;
686
687 /* Walk the Root Complex Inbound windows to match IMMR base */
688 in = pcie->cfg_type0 + PEX_RC_INWIN_BASE;
689 for (i = 0; i < 4; i++) {
690 /* not enabled, skip */
691 if (!in_le32(&in[i].ar) & PEX_RCIWARn_EN)
692 continue;
693
694 if (get_immrbase() == in_le32(&in[i].tar))
695 return (u64)in_le32(&in[i].barh) << 32 |
696 in_le32(&in[i].barl);
697 }
698
699 printk(KERN_WARNING "could not find PCI BAR matching IMMR\n");
700 }
701#endif
702
703#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
704 if (!is_mpc83xx_pci) {
705 u32 base;
706
707 pci_bus_read_config_dword(hose->bus,
708 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0, &base);
709 return base;
710 }
711#endif
712
713 return 0;
714}