Loading...
1/* pci.c: UltraSparc PCI controller support.
2 *
3 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
6 *
7 * OF tree based PCI bus probing taken from the PowerPC port
8 * with minor modifications, see there for credits.
9 */
10
11#include <linux/export.h>
12#include <linux/kernel.h>
13#include <linux/string.h>
14#include <linux/sched.h>
15#include <linux/capability.h>
16#include <linux/errno.h>
17#include <linux/pci.h>
18#include <linux/msi.h>
19#include <linux/irq.h>
20#include <linux/init.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23
24#include <asm/uaccess.h>
25#include <asm/pgtable.h>
26#include <asm/irq.h>
27#include <asm/prom.h>
28#include <asm/apb.h>
29
30#include "pci_impl.h"
31
32/* List of all PCI controllers found in the system. */
33struct pci_pbm_info *pci_pbm_root = NULL;
34
35/* Each PBM found gets a unique index. */
36int pci_num_pbms = 0;
37
38volatile int pci_poke_in_progress;
39volatile int pci_poke_cpu = -1;
40volatile int pci_poke_faulted;
41
42static DEFINE_SPINLOCK(pci_poke_lock);
43
44void pci_config_read8(u8 *addr, u8 *ret)
45{
46 unsigned long flags;
47 u8 byte;
48
49 spin_lock_irqsave(&pci_poke_lock, flags);
50 pci_poke_cpu = smp_processor_id();
51 pci_poke_in_progress = 1;
52 pci_poke_faulted = 0;
53 __asm__ __volatile__("membar #Sync\n\t"
54 "lduba [%1] %2, %0\n\t"
55 "membar #Sync"
56 : "=r" (byte)
57 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
58 : "memory");
59 pci_poke_in_progress = 0;
60 pci_poke_cpu = -1;
61 if (!pci_poke_faulted)
62 *ret = byte;
63 spin_unlock_irqrestore(&pci_poke_lock, flags);
64}
65
66void pci_config_read16(u16 *addr, u16 *ret)
67{
68 unsigned long flags;
69 u16 word;
70
71 spin_lock_irqsave(&pci_poke_lock, flags);
72 pci_poke_cpu = smp_processor_id();
73 pci_poke_in_progress = 1;
74 pci_poke_faulted = 0;
75 __asm__ __volatile__("membar #Sync\n\t"
76 "lduha [%1] %2, %0\n\t"
77 "membar #Sync"
78 : "=r" (word)
79 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
80 : "memory");
81 pci_poke_in_progress = 0;
82 pci_poke_cpu = -1;
83 if (!pci_poke_faulted)
84 *ret = word;
85 spin_unlock_irqrestore(&pci_poke_lock, flags);
86}
87
88void pci_config_read32(u32 *addr, u32 *ret)
89{
90 unsigned long flags;
91 u32 dword;
92
93 spin_lock_irqsave(&pci_poke_lock, flags);
94 pci_poke_cpu = smp_processor_id();
95 pci_poke_in_progress = 1;
96 pci_poke_faulted = 0;
97 __asm__ __volatile__("membar #Sync\n\t"
98 "lduwa [%1] %2, %0\n\t"
99 "membar #Sync"
100 : "=r" (dword)
101 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
102 : "memory");
103 pci_poke_in_progress = 0;
104 pci_poke_cpu = -1;
105 if (!pci_poke_faulted)
106 *ret = dword;
107 spin_unlock_irqrestore(&pci_poke_lock, flags);
108}
109
110void pci_config_write8(u8 *addr, u8 val)
111{
112 unsigned long flags;
113
114 spin_lock_irqsave(&pci_poke_lock, flags);
115 pci_poke_cpu = smp_processor_id();
116 pci_poke_in_progress = 1;
117 pci_poke_faulted = 0;
118 __asm__ __volatile__("membar #Sync\n\t"
119 "stba %0, [%1] %2\n\t"
120 "membar #Sync"
121 : /* no outputs */
122 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
123 : "memory");
124 pci_poke_in_progress = 0;
125 pci_poke_cpu = -1;
126 spin_unlock_irqrestore(&pci_poke_lock, flags);
127}
128
129void pci_config_write16(u16 *addr, u16 val)
130{
131 unsigned long flags;
132
133 spin_lock_irqsave(&pci_poke_lock, flags);
134 pci_poke_cpu = smp_processor_id();
135 pci_poke_in_progress = 1;
136 pci_poke_faulted = 0;
137 __asm__ __volatile__("membar #Sync\n\t"
138 "stha %0, [%1] %2\n\t"
139 "membar #Sync"
140 : /* no outputs */
141 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
142 : "memory");
143 pci_poke_in_progress = 0;
144 pci_poke_cpu = -1;
145 spin_unlock_irqrestore(&pci_poke_lock, flags);
146}
147
148void pci_config_write32(u32 *addr, u32 val)
149{
150 unsigned long flags;
151
152 spin_lock_irqsave(&pci_poke_lock, flags);
153 pci_poke_cpu = smp_processor_id();
154 pci_poke_in_progress = 1;
155 pci_poke_faulted = 0;
156 __asm__ __volatile__("membar #Sync\n\t"
157 "stwa %0, [%1] %2\n\t"
158 "membar #Sync"
159 : /* no outputs */
160 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
161 : "memory");
162 pci_poke_in_progress = 0;
163 pci_poke_cpu = -1;
164 spin_unlock_irqrestore(&pci_poke_lock, flags);
165}
166
167static int ofpci_verbose;
168
169static int __init ofpci_debug(char *str)
170{
171 int val = 0;
172
173 get_option(&str, &val);
174 if (val)
175 ofpci_verbose = 1;
176 return 1;
177}
178
179__setup("ofpci_debug=", ofpci_debug);
180
181static unsigned long pci_parse_of_flags(u32 addr0)
182{
183 unsigned long flags = 0;
184
185 if (addr0 & 0x02000000) {
186 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
187 flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64;
188 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
189 if (addr0 & 0x40000000)
190 flags |= IORESOURCE_PREFETCH
191 | PCI_BASE_ADDRESS_MEM_PREFETCH;
192 } else if (addr0 & 0x01000000)
193 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
194 return flags;
195}
196
197/* The of_device layer has translated all of the assigned-address properties
198 * into physical address resources, we only have to figure out the register
199 * mapping.
200 */
201static void pci_parse_of_addrs(struct platform_device *op,
202 struct device_node *node,
203 struct pci_dev *dev)
204{
205 struct resource *op_res;
206 const u32 *addrs;
207 int proplen;
208
209 addrs = of_get_property(node, "assigned-addresses", &proplen);
210 if (!addrs)
211 return;
212 if (ofpci_verbose)
213 printk(" parse addresses (%d bytes) @ %p\n",
214 proplen, addrs);
215 op_res = &op->resource[0];
216 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
217 struct resource *res;
218 unsigned long flags;
219 int i;
220
221 flags = pci_parse_of_flags(addrs[0]);
222 if (!flags)
223 continue;
224 i = addrs[0] & 0xff;
225 if (ofpci_verbose)
226 printk(" start: %llx, end: %llx, i: %x\n",
227 op_res->start, op_res->end, i);
228
229 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
230 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
231 } else if (i == dev->rom_base_reg) {
232 res = &dev->resource[PCI_ROM_RESOURCE];
233 flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE
234 | IORESOURCE_SIZEALIGN;
235 } else {
236 printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
237 continue;
238 }
239 res->start = op_res->start;
240 res->end = op_res->end;
241 res->flags = flags;
242 res->name = pci_name(dev);
243 }
244}
245
246static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
247 struct device_node *node,
248 struct pci_bus *bus, int devfn)
249{
250 struct dev_archdata *sd;
251 struct pci_slot *slot;
252 struct platform_device *op;
253 struct pci_dev *dev;
254 const char *type;
255 u32 class;
256
257 dev = alloc_pci_dev();
258 if (!dev)
259 return NULL;
260
261 sd = &dev->dev.archdata;
262 sd->iommu = pbm->iommu;
263 sd->stc = &pbm->stc;
264 sd->host_controller = pbm;
265 sd->op = op = of_find_device_by_node(node);
266 sd->numa_node = pbm->numa_node;
267
268 sd = &op->dev.archdata;
269 sd->iommu = pbm->iommu;
270 sd->stc = &pbm->stc;
271 sd->numa_node = pbm->numa_node;
272
273 if (!strcmp(node->name, "ebus"))
274 of_propagate_archdata(op);
275
276 type = of_get_property(node, "device_type", NULL);
277 if (type == NULL)
278 type = "";
279
280 if (ofpci_verbose)
281 printk(" create device, devfn: %x, type: %s\n",
282 devfn, type);
283
284 dev->bus = bus;
285 dev->sysdata = node;
286 dev->dev.parent = bus->bridge;
287 dev->dev.bus = &pci_bus_type;
288 dev->dev.of_node = of_node_get(node);
289 dev->devfn = devfn;
290 dev->multifunction = 0; /* maybe a lie? */
291 set_pcie_port_type(dev);
292
293 list_for_each_entry(slot, &dev->bus->slots, list)
294 if (PCI_SLOT(dev->devfn) == slot->number)
295 dev->slot = slot;
296
297 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
298 dev->device = of_getintprop_default(node, "device-id", 0xffff);
299 dev->subsystem_vendor =
300 of_getintprop_default(node, "subsystem-vendor-id", 0);
301 dev->subsystem_device =
302 of_getintprop_default(node, "subsystem-id", 0);
303
304 dev->cfg_size = pci_cfg_space_size(dev);
305
306 /* We can't actually use the firmware value, we have
307 * to read what is in the register right now. One
308 * reason is that in the case of IDE interfaces the
309 * firmware can sample the value before the the IDE
310 * interface is programmed into native mode.
311 */
312 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
313 dev->class = class >> 8;
314 dev->revision = class & 0xff;
315
316 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
317 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
318
319 if (ofpci_verbose)
320 printk(" class: 0x%x device name: %s\n",
321 dev->class, pci_name(dev));
322
323 /* I have seen IDE devices which will not respond to
324 * the bmdma simplex check reads if bus mastering is
325 * disabled.
326 */
327 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
328 pci_set_master(dev);
329
330 dev->current_state = 4; /* unknown power state */
331 dev->error_state = pci_channel_io_normal;
332 dev->dma_mask = 0xffffffff;
333
334 if (!strcmp(node->name, "pci")) {
335 /* a PCI-PCI bridge */
336 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
337 dev->rom_base_reg = PCI_ROM_ADDRESS1;
338 } else if (!strcmp(type, "cardbus")) {
339 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
340 } else {
341 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
342 dev->rom_base_reg = PCI_ROM_ADDRESS;
343
344 dev->irq = sd->op->archdata.irqs[0];
345 if (dev->irq == 0xffffffff)
346 dev->irq = PCI_IRQ_NONE;
347 }
348
349 pci_parse_of_addrs(sd->op, node, dev);
350
351 if (ofpci_verbose)
352 printk(" adding to system ...\n");
353
354 pci_device_add(dev, bus);
355
356 return dev;
357}
358
359static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
360{
361 u32 idx, first, last;
362
363 first = 8;
364 last = 0;
365 for (idx = 0; idx < 8; idx++) {
366 if ((map & (1 << idx)) != 0) {
367 if (first > idx)
368 first = idx;
369 if (last < idx)
370 last = idx;
371 }
372 }
373
374 *first_p = first;
375 *last_p = last;
376}
377
378/* For PCI bus devices which lack a 'ranges' property we interrogate
379 * the config space values to set the resources, just like the generic
380 * Linux PCI probing code does.
381 */
382static void __devinit pci_cfg_fake_ranges(struct pci_dev *dev,
383 struct pci_bus *bus,
384 struct pci_pbm_info *pbm)
385{
386 struct pci_bus_region region;
387 struct resource *res, res2;
388 u8 io_base_lo, io_limit_lo;
389 u16 mem_base_lo, mem_limit_lo;
390 unsigned long base, limit;
391
392 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
393 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
394 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
395 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
396
397 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
398 u16 io_base_hi, io_limit_hi;
399
400 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
401 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
402 base |= (io_base_hi << 16);
403 limit |= (io_limit_hi << 16);
404 }
405
406 res = bus->resource[0];
407 if (base <= limit) {
408 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
409 res2.flags = res->flags;
410 region.start = base;
411 region.end = limit + 0xfff;
412 pcibios_bus_to_resource(dev, &res2, ®ion);
413 if (!res->start)
414 res->start = res2.start;
415 if (!res->end)
416 res->end = res2.end;
417 }
418
419 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
420 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
421 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
422 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
423
424 res = bus->resource[1];
425 if (base <= limit) {
426 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
427 IORESOURCE_MEM);
428 region.start = base;
429 region.end = limit + 0xfffff;
430 pcibios_bus_to_resource(dev, res, ®ion);
431 }
432
433 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
434 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
435 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
436 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
437
438 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
439 u32 mem_base_hi, mem_limit_hi;
440
441 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
442 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
443
444 /*
445 * Some bridges set the base > limit by default, and some
446 * (broken) BIOSes do not initialize them. If we find
447 * this, just assume they are not being used.
448 */
449 if (mem_base_hi <= mem_limit_hi) {
450 base |= ((long) mem_base_hi) << 32;
451 limit |= ((long) mem_limit_hi) << 32;
452 }
453 }
454
455 res = bus->resource[2];
456 if (base <= limit) {
457 res->flags = ((mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) |
458 IORESOURCE_MEM | IORESOURCE_PREFETCH);
459 region.start = base;
460 region.end = limit + 0xfffff;
461 pcibios_bus_to_resource(dev, res, ®ion);
462 }
463}
464
465/* Cook up fake bus resources for SUNW,simba PCI bridges which lack
466 * a proper 'ranges' property.
467 */
468static void __devinit apb_fake_ranges(struct pci_dev *dev,
469 struct pci_bus *bus,
470 struct pci_pbm_info *pbm)
471{
472 struct pci_bus_region region;
473 struct resource *res;
474 u32 first, last;
475 u8 map;
476
477 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
478 apb_calc_first_last(map, &first, &last);
479 res = bus->resource[0];
480 res->flags = IORESOURCE_IO;
481 region.start = (first << 21);
482 region.end = (last << 21) + ((1 << 21) - 1);
483 pcibios_bus_to_resource(dev, res, ®ion);
484
485 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
486 apb_calc_first_last(map, &first, &last);
487 res = bus->resource[1];
488 res->flags = IORESOURCE_MEM;
489 region.start = (first << 21);
490 region.end = (last << 21) + ((1 << 21) - 1);
491 pcibios_bus_to_resource(dev, res, ®ion);
492}
493
494static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
495 struct device_node *node,
496 struct pci_bus *bus);
497
498#define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
499
500static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm,
501 struct device_node *node,
502 struct pci_dev *dev)
503{
504 struct pci_bus *bus;
505 const u32 *busrange, *ranges;
506 int len, i, simba;
507 struct pci_bus_region region;
508 struct resource *res;
509 unsigned int flags;
510 u64 size;
511
512 if (ofpci_verbose)
513 printk("of_scan_pci_bridge(%s)\n", node->full_name);
514
515 /* parse bus-range property */
516 busrange = of_get_property(node, "bus-range", &len);
517 if (busrange == NULL || len != 8) {
518 printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n",
519 node->full_name);
520 return;
521 }
522 ranges = of_get_property(node, "ranges", &len);
523 simba = 0;
524 if (ranges == NULL) {
525 const char *model = of_get_property(node, "model", NULL);
526 if (model && !strcmp(model, "SUNW,simba"))
527 simba = 1;
528 }
529
530 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
531 if (!bus) {
532 printk(KERN_ERR "Failed to create pci bus for %s\n",
533 node->full_name);
534 return;
535 }
536
537 bus->primary = dev->bus->number;
538 bus->subordinate = busrange[1];
539 bus->bridge_ctl = 0;
540
541 /* parse ranges property, or cook one up by hand for Simba */
542 /* PCI #address-cells == 3 and #size-cells == 2 always */
543 res = &dev->resource[PCI_BRIDGE_RESOURCES];
544 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
545 res->flags = 0;
546 bus->resource[i] = res;
547 ++res;
548 }
549 if (simba) {
550 apb_fake_ranges(dev, bus, pbm);
551 goto after_ranges;
552 } else if (ranges == NULL) {
553 pci_cfg_fake_ranges(dev, bus, pbm);
554 goto after_ranges;
555 }
556 i = 1;
557 for (; len >= 32; len -= 32, ranges += 8) {
558 flags = pci_parse_of_flags(ranges[0]);
559 size = GET_64BIT(ranges, 6);
560 if (flags == 0 || size == 0)
561 continue;
562 if (flags & IORESOURCE_IO) {
563 res = bus->resource[0];
564 if (res->flags) {
565 printk(KERN_ERR "PCI: ignoring extra I/O range"
566 " for bridge %s\n", node->full_name);
567 continue;
568 }
569 } else {
570 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
571 printk(KERN_ERR "PCI: too many memory ranges"
572 " for bridge %s\n", node->full_name);
573 continue;
574 }
575 res = bus->resource[i];
576 ++i;
577 }
578
579 res->flags = flags;
580 region.start = GET_64BIT(ranges, 1);
581 region.end = region.start + size - 1;
582 pcibios_bus_to_resource(dev, res, ®ion);
583 }
584after_ranges:
585 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
586 bus->number);
587 if (ofpci_verbose)
588 printk(" bus name: %s\n", bus->name);
589
590 pci_of_scan_bus(pbm, node, bus);
591}
592
593static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm,
594 struct device_node *node,
595 struct pci_bus *bus)
596{
597 struct device_node *child;
598 const u32 *reg;
599 int reglen, devfn, prev_devfn;
600 struct pci_dev *dev;
601
602 if (ofpci_verbose)
603 printk("PCI: scan_bus[%s] bus no %d\n",
604 node->full_name, bus->number);
605
606 child = NULL;
607 prev_devfn = -1;
608 while ((child = of_get_next_child(node, child)) != NULL) {
609 if (ofpci_verbose)
610 printk(" * %s\n", child->full_name);
611 reg = of_get_property(child, "reg", ®len);
612 if (reg == NULL || reglen < 20)
613 continue;
614
615 devfn = (reg[0] >> 8) & 0xff;
616
617 /* This is a workaround for some device trees
618 * which list PCI devices twice. On the V100
619 * for example, device number 3 is listed twice.
620 * Once as "pm" and once again as "lomp".
621 */
622 if (devfn == prev_devfn)
623 continue;
624 prev_devfn = devfn;
625
626 /* create a new pci_dev for this device */
627 dev = of_create_pci_dev(pbm, child, bus, devfn);
628 if (!dev)
629 continue;
630 if (ofpci_verbose)
631 printk("PCI: dev header type: %x\n",
632 dev->hdr_type);
633
634 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
635 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
636 of_scan_pci_bridge(pbm, child, dev);
637 }
638}
639
640static ssize_t
641show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
642{
643 struct pci_dev *pdev;
644 struct device_node *dp;
645
646 pdev = to_pci_dev(dev);
647 dp = pdev->dev.of_node;
648
649 return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name);
650}
651
652static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
653
654static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus)
655{
656 struct pci_dev *dev;
657 struct pci_bus *child_bus;
658 int err;
659
660 list_for_each_entry(dev, &bus->devices, bus_list) {
661 /* we don't really care if we can create this file or
662 * not, but we need to assign the result of the call
663 * or the world will fall under alien invasion and
664 * everybody will be frozen on a spaceship ready to be
665 * eaten on alpha centauri by some green and jelly
666 * humanoid.
667 */
668 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
669 (void) err;
670 }
671 list_for_each_entry(child_bus, &bus->children, node)
672 pci_bus_register_of_sysfs(child_bus);
673}
674
675struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm,
676 struct device *parent)
677{
678 LIST_HEAD(resources);
679 struct device_node *node = pbm->op->dev.of_node;
680 struct pci_bus *bus;
681
682 printk("PCI: Scanning PBM %s\n", node->full_name);
683
684 pci_add_resource_offset(&resources, &pbm->io_space,
685 pbm->io_space.start);
686 pci_add_resource_offset(&resources, &pbm->mem_space,
687 pbm->mem_space.start);
688 bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops,
689 pbm, &resources);
690 if (!bus) {
691 printk(KERN_ERR "Failed to create bus for %s\n",
692 node->full_name);
693 pci_free_resource_list(&resources);
694 return NULL;
695 }
696 bus->secondary = pbm->pci_first_busno;
697 bus->subordinate = pbm->pci_last_busno;
698
699 pci_of_scan_bus(pbm, node, bus);
700 pci_bus_add_devices(bus);
701 pci_bus_register_of_sysfs(bus);
702
703 return bus;
704}
705
706void __devinit pcibios_fixup_bus(struct pci_bus *pbus)
707{
708}
709
710void pcibios_update_irq(struct pci_dev *pdev, int irq)
711{
712}
713
714resource_size_t pcibios_align_resource(void *data, const struct resource *res,
715 resource_size_t size, resource_size_t align)
716{
717 return res->start;
718}
719
720int pcibios_enable_device(struct pci_dev *dev, int mask)
721{
722 u16 cmd, oldcmd;
723 int i;
724
725 pci_read_config_word(dev, PCI_COMMAND, &cmd);
726 oldcmd = cmd;
727
728 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
729 struct resource *res = &dev->resource[i];
730
731 /* Only set up the requested stuff */
732 if (!(mask & (1<<i)))
733 continue;
734
735 if (res->flags & IORESOURCE_IO)
736 cmd |= PCI_COMMAND_IO;
737 if (res->flags & IORESOURCE_MEM)
738 cmd |= PCI_COMMAND_MEMORY;
739 }
740
741 if (cmd != oldcmd) {
742 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
743 pci_name(dev), cmd);
744 /* Enable the appropriate bits in the PCI command register. */
745 pci_write_config_word(dev, PCI_COMMAND, cmd);
746 }
747 return 0;
748}
749
750char * __devinit pcibios_setup(char *str)
751{
752 return str;
753}
754
755/* Platform support for /proc/bus/pci/X/Y mmap()s. */
756
757/* If the user uses a host-bridge as the PCI device, he may use
758 * this to perform a raw mmap() of the I/O or MEM space behind
759 * that controller.
760 *
761 * This can be useful for execution of x86 PCI bios initialization code
762 * on a PCI card, like the xfree86 int10 stuff does.
763 */
764static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma,
765 enum pci_mmap_state mmap_state)
766{
767 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
768 unsigned long space_size, user_offset, user_size;
769
770 if (mmap_state == pci_mmap_io) {
771 space_size = resource_size(&pbm->io_space);
772 } else {
773 space_size = resource_size(&pbm->mem_space);
774 }
775
776 /* Make sure the request is in range. */
777 user_offset = vma->vm_pgoff << PAGE_SHIFT;
778 user_size = vma->vm_end - vma->vm_start;
779
780 if (user_offset >= space_size ||
781 (user_offset + user_size) > space_size)
782 return -EINVAL;
783
784 if (mmap_state == pci_mmap_io) {
785 vma->vm_pgoff = (pbm->io_space.start +
786 user_offset) >> PAGE_SHIFT;
787 } else {
788 vma->vm_pgoff = (pbm->mem_space.start +
789 user_offset) >> PAGE_SHIFT;
790 }
791
792 return 0;
793}
794
795/* Adjust vm_pgoff of VMA such that it is the physical page offset
796 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
797 *
798 * Basically, the user finds the base address for his device which he wishes
799 * to mmap. They read the 32-bit value from the config space base register,
800 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
801 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
802 *
803 * Returns negative error code on failure, zero on success.
804 */
805static int __pci_mmap_make_offset(struct pci_dev *pdev,
806 struct vm_area_struct *vma,
807 enum pci_mmap_state mmap_state)
808{
809 unsigned long user_paddr, user_size;
810 int i, err;
811
812 /* First compute the physical address in vma->vm_pgoff,
813 * making sure the user offset is within range in the
814 * appropriate PCI space.
815 */
816 err = __pci_mmap_make_offset_bus(pdev, vma, mmap_state);
817 if (err)
818 return err;
819
820 /* If this is a mapping on a host bridge, any address
821 * is OK.
822 */
823 if ((pdev->class >> 8) == PCI_CLASS_BRIDGE_HOST)
824 return err;
825
826 /* Otherwise make sure it's in the range for one of the
827 * device's resources.
828 */
829 user_paddr = vma->vm_pgoff << PAGE_SHIFT;
830 user_size = vma->vm_end - vma->vm_start;
831
832 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
833 struct resource *rp = &pdev->resource[i];
834 resource_size_t aligned_end;
835
836 /* Active? */
837 if (!rp->flags)
838 continue;
839
840 /* Same type? */
841 if (i == PCI_ROM_RESOURCE) {
842 if (mmap_state != pci_mmap_mem)
843 continue;
844 } else {
845 if ((mmap_state == pci_mmap_io &&
846 (rp->flags & IORESOURCE_IO) == 0) ||
847 (mmap_state == pci_mmap_mem &&
848 (rp->flags & IORESOURCE_MEM) == 0))
849 continue;
850 }
851
852 /* Align the resource end to the next page address.
853 * PAGE_SIZE intentionally added instead of (PAGE_SIZE - 1),
854 * because actually we need the address of the next byte
855 * after rp->end.
856 */
857 aligned_end = (rp->end + PAGE_SIZE) & PAGE_MASK;
858
859 if ((rp->start <= user_paddr) &&
860 (user_paddr + user_size) <= aligned_end)
861 break;
862 }
863
864 if (i > PCI_ROM_RESOURCE)
865 return -EINVAL;
866
867 return 0;
868}
869
870/* Set vm_flags of VMA, as appropriate for this architecture, for a pci device
871 * mapping.
872 */
873static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
874 enum pci_mmap_state mmap_state)
875{
876 vma->vm_flags |= (VM_IO | VM_RESERVED);
877}
878
879/* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
880 * device mapping.
881 */
882static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
883 enum pci_mmap_state mmap_state)
884{
885 /* Our io_remap_pfn_range takes care of this, do nothing. */
886}
887
888/* Perform the actual remap of the pages for a PCI device mapping, as appropriate
889 * for this architecture. The region in the process to map is described by vm_start
890 * and vm_end members of VMA, the base physical address is found in vm_pgoff.
891 * The pci device structure is provided so that architectures may make mapping
892 * decisions on a per-device or per-bus basis.
893 *
894 * Returns a negative error code on failure, zero on success.
895 */
896int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
897 enum pci_mmap_state mmap_state,
898 int write_combine)
899{
900 int ret;
901
902 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
903 if (ret < 0)
904 return ret;
905
906 __pci_mmap_set_flags(dev, vma, mmap_state);
907 __pci_mmap_set_pgprot(dev, vma, mmap_state);
908
909 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
910 ret = io_remap_pfn_range(vma, vma->vm_start,
911 vma->vm_pgoff,
912 vma->vm_end - vma->vm_start,
913 vma->vm_page_prot);
914 if (ret)
915 return ret;
916
917 return 0;
918}
919
920#ifdef CONFIG_NUMA
921int pcibus_to_node(struct pci_bus *pbus)
922{
923 struct pci_pbm_info *pbm = pbus->sysdata;
924
925 return pbm->numa_node;
926}
927EXPORT_SYMBOL(pcibus_to_node);
928#endif
929
930/* Return the domain number for this pci bus */
931
932int pci_domain_nr(struct pci_bus *pbus)
933{
934 struct pci_pbm_info *pbm = pbus->sysdata;
935 int ret;
936
937 if (!pbm) {
938 ret = -ENXIO;
939 } else {
940 ret = pbm->index;
941 }
942
943 return ret;
944}
945EXPORT_SYMBOL(pci_domain_nr);
946
947#ifdef CONFIG_PCI_MSI
948int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
949{
950 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
951 unsigned int irq;
952
953 if (!pbm->setup_msi_irq)
954 return -EINVAL;
955
956 return pbm->setup_msi_irq(&irq, pdev, desc);
957}
958
959void arch_teardown_msi_irq(unsigned int irq)
960{
961 struct msi_desc *entry = irq_get_msi_desc(irq);
962 struct pci_dev *pdev = entry->dev;
963 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
964
965 if (pbm->teardown_msi_irq)
966 pbm->teardown_msi_irq(irq, pdev);
967}
968#endif /* !(CONFIG_PCI_MSI) */
969
970static void ali_sound_dma_hack(struct pci_dev *pdev, int set_bit)
971{
972 struct pci_dev *ali_isa_bridge;
973 u8 val;
974
975 /* ALI sound chips generate 31-bits of DMA, a special register
976 * determines what bit 31 is emitted as.
977 */
978 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
979 PCI_DEVICE_ID_AL_M1533,
980 NULL);
981
982 pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
983 if (set_bit)
984 val |= 0x01;
985 else
986 val &= ~0x01;
987 pci_write_config_byte(ali_isa_bridge, 0x7e, val);
988 pci_dev_put(ali_isa_bridge);
989}
990
991int pci64_dma_supported(struct pci_dev *pdev, u64 device_mask)
992{
993 u64 dma_addr_mask;
994
995 if (pdev == NULL) {
996 dma_addr_mask = 0xffffffff;
997 } else {
998 struct iommu *iommu = pdev->dev.archdata.iommu;
999
1000 dma_addr_mask = iommu->dma_addr_mask;
1001
1002 if (pdev->vendor == PCI_VENDOR_ID_AL &&
1003 pdev->device == PCI_DEVICE_ID_AL_M5451 &&
1004 device_mask == 0x7fffffff) {
1005 ali_sound_dma_hack(pdev,
1006 (dma_addr_mask & 0x80000000) != 0);
1007 return 1;
1008 }
1009 }
1010
1011 if (device_mask >= (1UL << 32UL))
1012 return 0;
1013
1014 return (device_mask & dma_addr_mask) == dma_addr_mask;
1015}
1016
1017void pci_resource_to_user(const struct pci_dev *pdev, int bar,
1018 const struct resource *rp, resource_size_t *start,
1019 resource_size_t *end)
1020{
1021 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
1022 unsigned long offset;
1023
1024 if (rp->flags & IORESOURCE_IO)
1025 offset = pbm->io_space.start;
1026 else
1027 offset = pbm->mem_space.start;
1028
1029 *start = rp->start - offset;
1030 *end = rp->end - offset;
1031}
1032
1033void pcibios_set_master(struct pci_dev *dev)
1034{
1035 /* No special bus mastering setup handling */
1036}
1037
1038static int __init pcibios_init(void)
1039{
1040 pci_dfl_cache_line_size = 64 >> 2;
1041 return 0;
1042}
1043subsys_initcall(pcibios_init);
1044
1045#ifdef CONFIG_SYSFS
1046static void __devinit pci_bus_slot_names(struct device_node *node,
1047 struct pci_bus *bus)
1048{
1049 const struct pci_slot_names {
1050 u32 slot_mask;
1051 char names[0];
1052 } *prop;
1053 const char *sp;
1054 int len, i;
1055 u32 mask;
1056
1057 prop = of_get_property(node, "slot-names", &len);
1058 if (!prop)
1059 return;
1060
1061 mask = prop->slot_mask;
1062 sp = prop->names;
1063
1064 if (ofpci_verbose)
1065 printk("PCI: Making slots for [%s] mask[0x%02x]\n",
1066 node->full_name, mask);
1067
1068 i = 0;
1069 while (mask) {
1070 struct pci_slot *pci_slot;
1071 u32 this_bit = 1 << i;
1072
1073 if (!(mask & this_bit)) {
1074 i++;
1075 continue;
1076 }
1077
1078 if (ofpci_verbose)
1079 printk("PCI: Making slot [%s]\n", sp);
1080
1081 pci_slot = pci_create_slot(bus, i, sp, NULL);
1082 if (IS_ERR(pci_slot))
1083 printk(KERN_ERR "PCI: pci_create_slot returned %ld\n",
1084 PTR_ERR(pci_slot));
1085
1086 sp += strlen(sp) + 1;
1087 mask &= ~this_bit;
1088 i++;
1089 }
1090}
1091
1092static int __init of_pci_slot_init(void)
1093{
1094 struct pci_bus *pbus = NULL;
1095
1096 while ((pbus = pci_find_next_bus(pbus)) != NULL) {
1097 struct device_node *node;
1098
1099 if (pbus->self) {
1100 /* PCI->PCI bridge */
1101 node = pbus->self->dev.of_node;
1102 } else {
1103 struct pci_pbm_info *pbm = pbus->sysdata;
1104
1105 /* Host PCI controller */
1106 node = pbm->op->dev.of_node;
1107 }
1108
1109 pci_bus_slot_names(node, pbus);
1110 }
1111
1112 return 0;
1113}
1114
1115module_init(of_pci_slot_init);
1116#endif
1// SPDX-License-Identifier: GPL-2.0
2/* pci.c: UltraSparc PCI controller support.
3 *
4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
5 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
7 *
8 * OF tree based PCI bus probing taken from the PowerPC port
9 * with minor modifications, see there for credits.
10 */
11
12#include <linux/export.h>
13#include <linux/kernel.h>
14#include <linux/string.h>
15#include <linux/sched.h>
16#include <linux/capability.h>
17#include <linux/errno.h>
18#include <linux/pci.h>
19#include <linux/msi.h>
20#include <linux/irq.h>
21#include <linux/init.h>
22#include <linux/of.h>
23#include <linux/of_platform.h>
24#include <linux/pgtable.h>
25#include <linux/platform_device.h>
26
27#include <linux/uaccess.h>
28#include <asm/irq.h>
29#include <asm/prom.h>
30#include <asm/apb.h>
31
32#include "pci_impl.h"
33#include "kernel.h"
34
35/* List of all PCI controllers found in the system. */
36struct pci_pbm_info *pci_pbm_root = NULL;
37
38/* Each PBM found gets a unique index. */
39int pci_num_pbms = 0;
40
41volatile int pci_poke_in_progress;
42volatile int pci_poke_cpu = -1;
43volatile int pci_poke_faulted;
44
45static DEFINE_SPINLOCK(pci_poke_lock);
46
47void pci_config_read8(u8 *addr, u8 *ret)
48{
49 unsigned long flags;
50 u8 byte;
51
52 spin_lock_irqsave(&pci_poke_lock, flags);
53 pci_poke_cpu = smp_processor_id();
54 pci_poke_in_progress = 1;
55 pci_poke_faulted = 0;
56 __asm__ __volatile__("membar #Sync\n\t"
57 "lduba [%1] %2, %0\n\t"
58 "membar #Sync"
59 : "=r" (byte)
60 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
61 : "memory");
62 pci_poke_in_progress = 0;
63 pci_poke_cpu = -1;
64 if (!pci_poke_faulted)
65 *ret = byte;
66 spin_unlock_irqrestore(&pci_poke_lock, flags);
67}
68
69void pci_config_read16(u16 *addr, u16 *ret)
70{
71 unsigned long flags;
72 u16 word;
73
74 spin_lock_irqsave(&pci_poke_lock, flags);
75 pci_poke_cpu = smp_processor_id();
76 pci_poke_in_progress = 1;
77 pci_poke_faulted = 0;
78 __asm__ __volatile__("membar #Sync\n\t"
79 "lduha [%1] %2, %0\n\t"
80 "membar #Sync"
81 : "=r" (word)
82 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
83 : "memory");
84 pci_poke_in_progress = 0;
85 pci_poke_cpu = -1;
86 if (!pci_poke_faulted)
87 *ret = word;
88 spin_unlock_irqrestore(&pci_poke_lock, flags);
89}
90
91void pci_config_read32(u32 *addr, u32 *ret)
92{
93 unsigned long flags;
94 u32 dword;
95
96 spin_lock_irqsave(&pci_poke_lock, flags);
97 pci_poke_cpu = smp_processor_id();
98 pci_poke_in_progress = 1;
99 pci_poke_faulted = 0;
100 __asm__ __volatile__("membar #Sync\n\t"
101 "lduwa [%1] %2, %0\n\t"
102 "membar #Sync"
103 : "=r" (dword)
104 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
105 : "memory");
106 pci_poke_in_progress = 0;
107 pci_poke_cpu = -1;
108 if (!pci_poke_faulted)
109 *ret = dword;
110 spin_unlock_irqrestore(&pci_poke_lock, flags);
111}
112
113void pci_config_write8(u8 *addr, u8 val)
114{
115 unsigned long flags;
116
117 spin_lock_irqsave(&pci_poke_lock, flags);
118 pci_poke_cpu = smp_processor_id();
119 pci_poke_in_progress = 1;
120 pci_poke_faulted = 0;
121 __asm__ __volatile__("membar #Sync\n\t"
122 "stba %0, [%1] %2\n\t"
123 "membar #Sync"
124 : /* no outputs */
125 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
126 : "memory");
127 pci_poke_in_progress = 0;
128 pci_poke_cpu = -1;
129 spin_unlock_irqrestore(&pci_poke_lock, flags);
130}
131
132void pci_config_write16(u16 *addr, u16 val)
133{
134 unsigned long flags;
135
136 spin_lock_irqsave(&pci_poke_lock, flags);
137 pci_poke_cpu = smp_processor_id();
138 pci_poke_in_progress = 1;
139 pci_poke_faulted = 0;
140 __asm__ __volatile__("membar #Sync\n\t"
141 "stha %0, [%1] %2\n\t"
142 "membar #Sync"
143 : /* no outputs */
144 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
145 : "memory");
146 pci_poke_in_progress = 0;
147 pci_poke_cpu = -1;
148 spin_unlock_irqrestore(&pci_poke_lock, flags);
149}
150
151void pci_config_write32(u32 *addr, u32 val)
152{
153 unsigned long flags;
154
155 spin_lock_irqsave(&pci_poke_lock, flags);
156 pci_poke_cpu = smp_processor_id();
157 pci_poke_in_progress = 1;
158 pci_poke_faulted = 0;
159 __asm__ __volatile__("membar #Sync\n\t"
160 "stwa %0, [%1] %2\n\t"
161 "membar #Sync"
162 : /* no outputs */
163 : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L)
164 : "memory");
165 pci_poke_in_progress = 0;
166 pci_poke_cpu = -1;
167 spin_unlock_irqrestore(&pci_poke_lock, flags);
168}
169
170static int ofpci_verbose;
171
172static int __init ofpci_debug(char *str)
173{
174 int val = 0;
175
176 get_option(&str, &val);
177 if (val)
178 ofpci_verbose = 1;
179 return 1;
180}
181
182__setup("ofpci_debug=", ofpci_debug);
183
184static unsigned long pci_parse_of_flags(u32 addr0)
185{
186 unsigned long flags = 0;
187
188 if (addr0 & 0x02000000) {
189 flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
190 flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M;
191 if (addr0 & 0x01000000)
192 flags |= IORESOURCE_MEM_64
193 | PCI_BASE_ADDRESS_MEM_TYPE_64;
194 if (addr0 & 0x40000000)
195 flags |= IORESOURCE_PREFETCH
196 | PCI_BASE_ADDRESS_MEM_PREFETCH;
197 } else if (addr0 & 0x01000000)
198 flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
199 return flags;
200}
201
202/* The of_device layer has translated all of the assigned-address properties
203 * into physical address resources, we only have to figure out the register
204 * mapping.
205 */
206static void pci_parse_of_addrs(struct platform_device *op,
207 struct device_node *node,
208 struct pci_dev *dev)
209{
210 struct resource *op_res;
211 const u32 *addrs;
212 int proplen;
213
214 addrs = of_get_property(node, "assigned-addresses", &proplen);
215 if (!addrs)
216 return;
217 if (ofpci_verbose)
218 pci_info(dev, " parse addresses (%d bytes) @ %p\n",
219 proplen, addrs);
220 op_res = &op->resource[0];
221 for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) {
222 struct resource *res;
223 unsigned long flags;
224 int i;
225
226 flags = pci_parse_of_flags(addrs[0]);
227 if (!flags)
228 continue;
229 i = addrs[0] & 0xff;
230 if (ofpci_verbose)
231 pci_info(dev, " start: %llx, end: %llx, i: %x\n",
232 op_res->start, op_res->end, i);
233
234 if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
235 res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
236 } else if (i == dev->rom_base_reg) {
237 res = &dev->resource[PCI_ROM_RESOURCE];
238 flags |= IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
239 } else {
240 pci_err(dev, "bad cfg reg num 0x%x\n", i);
241 continue;
242 }
243 res->start = op_res->start;
244 res->end = op_res->end;
245 res->flags = flags;
246 res->name = pci_name(dev);
247
248 pci_info(dev, "reg 0x%x: %pR\n", i, res);
249 }
250}
251
252static void pci_init_dev_archdata(struct dev_archdata *sd, void *iommu,
253 void *stc, void *host_controller,
254 struct platform_device *op,
255 int numa_node)
256{
257 sd->iommu = iommu;
258 sd->stc = stc;
259 sd->host_controller = host_controller;
260 sd->op = op;
261 sd->numa_node = numa_node;
262}
263
264static struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
265 struct device_node *node,
266 struct pci_bus *bus, int devfn)
267{
268 struct dev_archdata *sd;
269 struct platform_device *op;
270 struct pci_dev *dev;
271 u32 class;
272
273 dev = pci_alloc_dev(bus);
274 if (!dev)
275 return NULL;
276
277 op = of_find_device_by_node(node);
278 sd = &dev->dev.archdata;
279 pci_init_dev_archdata(sd, pbm->iommu, &pbm->stc, pbm, op,
280 pbm->numa_node);
281 sd = &op->dev.archdata;
282 sd->iommu = pbm->iommu;
283 sd->stc = &pbm->stc;
284 sd->numa_node = pbm->numa_node;
285
286 if (of_node_name_eq(node, "ebus"))
287 of_propagate_archdata(op);
288
289 if (ofpci_verbose)
290 pci_info(bus," create device, devfn: %x, type: %s\n",
291 devfn, of_node_get_device_type(node));
292
293 dev->sysdata = node;
294 dev->dev.parent = bus->bridge;
295 dev->dev.bus = &pci_bus_type;
296 dev->dev.of_node = of_node_get(node);
297 dev->devfn = devfn;
298 dev->multifunction = 0; /* maybe a lie? */
299 set_pcie_port_type(dev);
300
301 pci_dev_assign_slot(dev);
302 dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
303 dev->device = of_getintprop_default(node, "device-id", 0xffff);
304 dev->subsystem_vendor =
305 of_getintprop_default(node, "subsystem-vendor-id", 0);
306 dev->subsystem_device =
307 of_getintprop_default(node, "subsystem-id", 0);
308
309 dev->cfg_size = pci_cfg_space_size(dev);
310
311 /* We can't actually use the firmware value, we have
312 * to read what is in the register right now. One
313 * reason is that in the case of IDE interfaces the
314 * firmware can sample the value before the IDE
315 * interface is programmed into native mode.
316 */
317 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
318 dev->class = class >> 8;
319 dev->revision = class & 0xff;
320
321 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
322 dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
323
324 /* I have seen IDE devices which will not respond to
325 * the bmdma simplex check reads if bus mastering is
326 * disabled.
327 */
328 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
329 pci_set_master(dev);
330
331 dev->current_state = PCI_UNKNOWN; /* unknown power state */
332 dev->error_state = pci_channel_io_normal;
333 dev->dma_mask = 0xffffffff;
334
335 if (of_node_name_eq(node, "pci")) {
336 /* a PCI-PCI bridge */
337 dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
338 dev->rom_base_reg = PCI_ROM_ADDRESS1;
339 } else if (of_node_is_type(node, "cardbus")) {
340 dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
341 } else {
342 dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
343 dev->rom_base_reg = PCI_ROM_ADDRESS;
344
345 dev->irq = sd->op->archdata.irqs[0];
346 if (dev->irq == 0xffffffff)
347 dev->irq = PCI_IRQ_NONE;
348 }
349
350 pci_info(dev, "[%04x:%04x] type %02x class %#08x\n",
351 dev->vendor, dev->device, dev->hdr_type, dev->class);
352
353 pci_parse_of_addrs(sd->op, node, dev);
354
355 if (ofpci_verbose)
356 pci_info(dev, " adding to system ...\n");
357
358 pci_device_add(dev, bus);
359
360 return dev;
361}
362
363static void apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p)
364{
365 u32 idx, first, last;
366
367 first = 8;
368 last = 0;
369 for (idx = 0; idx < 8; idx++) {
370 if ((map & (1 << idx)) != 0) {
371 if (first > idx)
372 first = idx;
373 if (last < idx)
374 last = idx;
375 }
376 }
377
378 *first_p = first;
379 *last_p = last;
380}
381
382/* Cook up fake bus resources for SUNW,simba PCI bridges which lack
383 * a proper 'ranges' property.
384 */
385static void apb_fake_ranges(struct pci_dev *dev,
386 struct pci_bus *bus,
387 struct pci_pbm_info *pbm)
388{
389 struct pci_bus_region region;
390 struct resource *res;
391 u32 first, last;
392 u8 map;
393
394 pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map);
395 apb_calc_first_last(map, &first, &last);
396 res = bus->resource[0];
397 res->flags = IORESOURCE_IO;
398 region.start = (first << 21);
399 region.end = (last << 21) + ((1 << 21) - 1);
400 pcibios_bus_to_resource(dev->bus, res, ®ion);
401
402 pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map);
403 apb_calc_first_last(map, &first, &last);
404 res = bus->resource[1];
405 res->flags = IORESOURCE_MEM;
406 region.start = (first << 29);
407 region.end = (last << 29) + ((1 << 29) - 1);
408 pcibios_bus_to_resource(dev->bus, res, ®ion);
409}
410
411static void pci_of_scan_bus(struct pci_pbm_info *pbm,
412 struct device_node *node,
413 struct pci_bus *bus);
414
415#define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1])
416
417static void of_scan_pci_bridge(struct pci_pbm_info *pbm,
418 struct device_node *node,
419 struct pci_dev *dev)
420{
421 struct pci_bus *bus;
422 const u32 *busrange, *ranges;
423 int len, i, simba;
424 struct pci_bus_region region;
425 struct resource *res;
426 unsigned int flags;
427 u64 size;
428
429 if (ofpci_verbose)
430 pci_info(dev, "of_scan_pci_bridge(%pOF)\n", node);
431
432 /* parse bus-range property */
433 busrange = of_get_property(node, "bus-range", &len);
434 if (busrange == NULL || len != 8) {
435 pci_info(dev, "Can't get bus-range for PCI-PCI bridge %pOF\n",
436 node);
437 return;
438 }
439
440 if (ofpci_verbose)
441 pci_info(dev, " Bridge bus range [%u --> %u]\n",
442 busrange[0], busrange[1]);
443
444 ranges = of_get_property(node, "ranges", &len);
445 simba = 0;
446 if (ranges == NULL) {
447 const char *model = of_get_property(node, "model", NULL);
448 if (model && !strcmp(model, "SUNW,simba"))
449 simba = 1;
450 }
451
452 bus = pci_add_new_bus(dev->bus, dev, busrange[0]);
453 if (!bus) {
454 pci_err(dev, "Failed to create pci bus for %pOF\n",
455 node);
456 return;
457 }
458
459 bus->primary = dev->bus->number;
460 pci_bus_insert_busn_res(bus, busrange[0], busrange[1]);
461 bus->bridge_ctl = 0;
462
463 if (ofpci_verbose)
464 pci_info(dev, " Bridge ranges[%p] simba[%d]\n",
465 ranges, simba);
466
467 /* parse ranges property, or cook one up by hand for Simba */
468 /* PCI #address-cells == 3 and #size-cells == 2 always */
469 res = &dev->resource[PCI_BRIDGE_RESOURCES];
470 for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
471 res->flags = 0;
472 bus->resource[i] = res;
473 ++res;
474 }
475 if (simba) {
476 apb_fake_ranges(dev, bus, pbm);
477 goto after_ranges;
478 } else if (ranges == NULL) {
479 pci_read_bridge_bases(bus);
480 goto after_ranges;
481 }
482 i = 1;
483 for (; len >= 32; len -= 32, ranges += 8) {
484 u64 start;
485
486 if (ofpci_verbose)
487 pci_info(dev, " RAW Range[%08x:%08x:%08x:%08x:%08x:%08x:"
488 "%08x:%08x]\n",
489 ranges[0], ranges[1], ranges[2], ranges[3],
490 ranges[4], ranges[5], ranges[6], ranges[7]);
491
492 flags = pci_parse_of_flags(ranges[0]);
493 size = GET_64BIT(ranges, 6);
494 if (flags == 0 || size == 0)
495 continue;
496
497 /* On PCI-Express systems, PCI bridges that have no devices downstream
498 * have a bogus size value where the first 32-bit cell is 0xffffffff.
499 * This results in a bogus range where start + size overflows.
500 *
501 * Just skip these otherwise the kernel will complain when the resource
502 * tries to be claimed.
503 */
504 if (size >> 32 == 0xffffffff)
505 continue;
506
507 if (flags & IORESOURCE_IO) {
508 res = bus->resource[0];
509 if (res->flags) {
510 pci_err(dev, "ignoring extra I/O range"
511 " for bridge %pOF\n", node);
512 continue;
513 }
514 } else {
515 if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
516 pci_err(dev, "too many memory ranges"
517 " for bridge %pOF\n", node);
518 continue;
519 }
520 res = bus->resource[i];
521 ++i;
522 }
523
524 res->flags = flags;
525 region.start = start = GET_64BIT(ranges, 1);
526 region.end = region.start + size - 1;
527
528 if (ofpci_verbose)
529 pci_info(dev, " Using flags[%08x] start[%016llx] size[%016llx]\n",
530 flags, start, size);
531
532 pcibios_bus_to_resource(dev->bus, res, ®ion);
533 }
534after_ranges:
535 sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
536 bus->number);
537 if (ofpci_verbose)
538 pci_info(dev, " bus name: %s\n", bus->name);
539
540 pci_of_scan_bus(pbm, node, bus);
541}
542
543static void pci_of_scan_bus(struct pci_pbm_info *pbm,
544 struct device_node *node,
545 struct pci_bus *bus)
546{
547 struct device_node *child;
548 const u32 *reg;
549 int reglen, devfn, prev_devfn;
550 struct pci_dev *dev;
551
552 if (ofpci_verbose)
553 pci_info(bus, "scan_bus[%pOF] bus no %d\n",
554 node, bus->number);
555
556 prev_devfn = -1;
557 for_each_child_of_node(node, child) {
558 if (ofpci_verbose)
559 pci_info(bus, " * %pOF\n", child);
560 reg = of_get_property(child, "reg", ®len);
561 if (reg == NULL || reglen < 20)
562 continue;
563
564 devfn = (reg[0] >> 8) & 0xff;
565
566 /* This is a workaround for some device trees
567 * which list PCI devices twice. On the V100
568 * for example, device number 3 is listed twice.
569 * Once as "pm" and once again as "lomp".
570 */
571 if (devfn == prev_devfn)
572 continue;
573 prev_devfn = devfn;
574
575 /* create a new pci_dev for this device */
576 dev = of_create_pci_dev(pbm, child, bus, devfn);
577 if (!dev)
578 continue;
579 if (ofpci_verbose)
580 pci_info(dev, "dev header type: %x\n", dev->hdr_type);
581
582 if (pci_is_bridge(dev))
583 of_scan_pci_bridge(pbm, child, dev);
584 }
585}
586
587static ssize_t
588show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf)
589{
590 struct pci_dev *pdev;
591 struct device_node *dp;
592
593 pdev = to_pci_dev(dev);
594 dp = pdev->dev.of_node;
595
596 return scnprintf(buf, PAGE_SIZE, "%pOF\n", dp);
597}
598
599static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL);
600
601static void pci_bus_register_of_sysfs(struct pci_bus *bus)
602{
603 struct pci_dev *dev;
604 struct pci_bus *child_bus;
605 int err;
606
607 list_for_each_entry(dev, &bus->devices, bus_list) {
608 /* we don't really care if we can create this file or
609 * not, but we need to assign the result of the call
610 * or the world will fall under alien invasion and
611 * everybody will be frozen on a spaceship ready to be
612 * eaten on alpha centauri by some green and jelly
613 * humanoid.
614 */
615 err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr);
616 (void) err;
617 }
618 list_for_each_entry(child_bus, &bus->children, node)
619 pci_bus_register_of_sysfs(child_bus);
620}
621
622static void pci_claim_legacy_resources(struct pci_dev *dev)
623{
624 struct pci_bus_region region;
625 struct resource *p, *root, *conflict;
626
627 if ((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)
628 return;
629
630 p = kzalloc(sizeof(*p), GFP_KERNEL);
631 if (!p)
632 return;
633
634 p->name = "Video RAM area";
635 p->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
636
637 region.start = 0xa0000UL;
638 region.end = region.start + 0x1ffffUL;
639 pcibios_bus_to_resource(dev->bus, p, ®ion);
640
641 root = pci_find_parent_resource(dev, p);
642 if (!root) {
643 pci_info(dev, "can't claim VGA legacy %pR: no compatible bridge window\n", p);
644 goto err;
645 }
646
647 conflict = request_resource_conflict(root, p);
648 if (conflict) {
649 pci_info(dev, "can't claim VGA legacy %pR: address conflict with %s %pR\n",
650 p, conflict->name, conflict);
651 goto err;
652 }
653
654 pci_info(dev, "VGA legacy framebuffer %pR\n", p);
655 return;
656
657err:
658 kfree(p);
659}
660
661static void pci_claim_bus_resources(struct pci_bus *bus)
662{
663 struct pci_bus *child_bus;
664 struct pci_dev *dev;
665
666 list_for_each_entry(dev, &bus->devices, bus_list) {
667 struct resource *r;
668 int i;
669
670 pci_dev_for_each_resource(dev, r, i) {
671 if (r->parent || !r->start || !r->flags)
672 continue;
673
674 if (ofpci_verbose)
675 pci_info(dev, "Claiming Resource %d: %pR\n",
676 i, r);
677
678 pci_claim_resource(dev, i);
679 }
680
681 pci_claim_legacy_resources(dev);
682 }
683
684 list_for_each_entry(child_bus, &bus->children, node)
685 pci_claim_bus_resources(child_bus);
686}
687
688struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm,
689 struct device *parent)
690{
691 LIST_HEAD(resources);
692 struct device_node *node = pbm->op->dev.of_node;
693 struct pci_bus *bus;
694
695 printk("PCI: Scanning PBM %pOF\n", node);
696
697 pci_add_resource_offset(&resources, &pbm->io_space,
698 pbm->io_offset);
699 pci_add_resource_offset(&resources, &pbm->mem_space,
700 pbm->mem_offset);
701 if (pbm->mem64_space.flags)
702 pci_add_resource_offset(&resources, &pbm->mem64_space,
703 pbm->mem64_offset);
704 pbm->busn.start = pbm->pci_first_busno;
705 pbm->busn.end = pbm->pci_last_busno;
706 pbm->busn.flags = IORESOURCE_BUS;
707 pci_add_resource(&resources, &pbm->busn);
708 bus = pci_create_root_bus(parent, pbm->pci_first_busno, pbm->pci_ops,
709 pbm, &resources);
710 if (!bus) {
711 printk(KERN_ERR "Failed to create bus for %pOF\n", node);
712 pci_free_resource_list(&resources);
713 return NULL;
714 }
715
716 pci_of_scan_bus(pbm, node, bus);
717 pci_bus_register_of_sysfs(bus);
718
719 pci_claim_bus_resources(bus);
720
721 pci_bus_add_devices(bus);
722 return bus;
723}
724
725int pcibios_enable_device(struct pci_dev *dev, int mask)
726{
727 struct resource *res;
728 u16 cmd, oldcmd;
729 int i;
730
731 pci_read_config_word(dev, PCI_COMMAND, &cmd);
732 oldcmd = cmd;
733
734 pci_dev_for_each_resource(dev, res, i) {
735 /* Only set up the requested stuff */
736 if (!(mask & (1<<i)))
737 continue;
738
739 if (res->flags & IORESOURCE_IO)
740 cmd |= PCI_COMMAND_IO;
741 if (res->flags & IORESOURCE_MEM)
742 cmd |= PCI_COMMAND_MEMORY;
743 }
744
745 if (cmd != oldcmd) {
746 pci_info(dev, "enabling device (%04x -> %04x)\n", oldcmd, cmd);
747 pci_write_config_word(dev, PCI_COMMAND, cmd);
748 }
749 return 0;
750}
751
752/* Platform support for /proc/bus/pci/X/Y mmap()s. */
753int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
754{
755 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
756 resource_size_t ioaddr = pci_resource_start(pdev, bar);
757
758 if (!pbm)
759 return -EINVAL;
760
761 vma->vm_pgoff += (ioaddr + pbm->io_space.start) >> PAGE_SHIFT;
762
763 return 0;
764}
765
766#ifdef CONFIG_NUMA
767int pcibus_to_node(struct pci_bus *pbus)
768{
769 struct pci_pbm_info *pbm = pbus->sysdata;
770
771 return pbm->numa_node;
772}
773EXPORT_SYMBOL(pcibus_to_node);
774#endif
775
776/* Return the domain number for this pci bus */
777
778int pci_domain_nr(struct pci_bus *pbus)
779{
780 struct pci_pbm_info *pbm = pbus->sysdata;
781 int ret;
782
783 if (!pbm) {
784 ret = -ENXIO;
785 } else {
786 ret = pbm->index;
787 }
788
789 return ret;
790}
791EXPORT_SYMBOL(pci_domain_nr);
792
793#ifdef CONFIG_PCI_MSI
794int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
795{
796 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
797 unsigned int irq;
798
799 if (!pbm->setup_msi_irq)
800 return -EINVAL;
801
802 return pbm->setup_msi_irq(&irq, pdev, desc);
803}
804
805void arch_teardown_msi_irq(unsigned int irq)
806{
807 struct msi_desc *entry = irq_get_msi_desc(irq);
808 struct pci_dev *pdev = msi_desc_to_pci_dev(entry);
809 struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller;
810
811 if (pbm->teardown_msi_irq)
812 pbm->teardown_msi_irq(irq, pdev);
813}
814#endif /* !(CONFIG_PCI_MSI) */
815
816/* ALI sound chips generate 31-bits of DMA, a special register
817 * determines what bit 31 is emitted as.
818 */
819int ali_sound_dma_hack(struct device *dev, u64 device_mask)
820{
821 struct iommu *iommu = dev->archdata.iommu;
822 struct pci_dev *ali_isa_bridge;
823 u8 val;
824
825 if (!dev_is_pci(dev))
826 return 0;
827
828 if (to_pci_dev(dev)->vendor != PCI_VENDOR_ID_AL ||
829 to_pci_dev(dev)->device != PCI_DEVICE_ID_AL_M5451 ||
830 device_mask != 0x7fffffff)
831 return 0;
832
833 ali_isa_bridge = pci_get_device(PCI_VENDOR_ID_AL,
834 PCI_DEVICE_ID_AL_M1533,
835 NULL);
836
837 pci_read_config_byte(ali_isa_bridge, 0x7e, &val);
838 if (iommu->dma_addr_mask & 0x80000000)
839 val |= 0x01;
840 else
841 val &= ~0x01;
842 pci_write_config_byte(ali_isa_bridge, 0x7e, val);
843 pci_dev_put(ali_isa_bridge);
844 return 1;
845}
846
847void pci_resource_to_user(const struct pci_dev *pdev, int bar,
848 const struct resource *rp, resource_size_t *start,
849 resource_size_t *end)
850{
851 struct pci_bus_region region;
852
853 /*
854 * "User" addresses are shown in /sys/devices/pci.../.../resource
855 * and /proc/bus/pci/devices and used as mmap offsets for
856 * /proc/bus/pci/BB/DD.F files (see proc_bus_pci_mmap()).
857 *
858 * On sparc, these are PCI bus addresses, i.e., raw BAR values.
859 */
860 pcibios_resource_to_bus(pdev->bus, ®ion, (struct resource *) rp);
861 *start = region.start;
862 *end = region.end;
863}
864
865void pcibios_set_master(struct pci_dev *dev)
866{
867 /* No special bus mastering setup handling */
868}
869
870#ifdef CONFIG_PCI_IOV
871int pcibios_device_add(struct pci_dev *dev)
872{
873 struct pci_dev *pdev;
874
875 /* Add sriov arch specific initialization here.
876 * Copy dev_archdata from PF to VF
877 */
878 if (dev->is_virtfn) {
879 struct dev_archdata *psd;
880
881 pdev = dev->physfn;
882 psd = &pdev->dev.archdata;
883 pci_init_dev_archdata(&dev->dev.archdata, psd->iommu,
884 psd->stc, psd->host_controller, NULL,
885 psd->numa_node);
886 }
887 return 0;
888}
889#endif /* CONFIG_PCI_IOV */
890
891static int __init pcibios_init(void)
892{
893 pci_dfl_cache_line_size = 64 >> 2;
894 return 0;
895}
896subsys_initcall(pcibios_init);
897
898#ifdef CONFIG_SYSFS
899
900#define SLOT_NAME_SIZE 11 /* Max decimal digits + null in u32 */
901
902static void pcie_bus_slot_names(struct pci_bus *pbus)
903{
904 struct pci_dev *pdev;
905 struct pci_bus *bus;
906
907 list_for_each_entry(pdev, &pbus->devices, bus_list) {
908 char name[SLOT_NAME_SIZE];
909 struct pci_slot *pci_slot;
910 const u32 *slot_num;
911 int len;
912
913 slot_num = of_get_property(pdev->dev.of_node,
914 "physical-slot#", &len);
915
916 if (slot_num == NULL || len != 4)
917 continue;
918
919 snprintf(name, sizeof(name), "%u", slot_num[0]);
920 pci_slot = pci_create_slot(pbus, slot_num[0], name, NULL);
921
922 if (IS_ERR(pci_slot))
923 pr_err("PCI: pci_create_slot returned %ld.\n",
924 PTR_ERR(pci_slot));
925 }
926
927 list_for_each_entry(bus, &pbus->children, node)
928 pcie_bus_slot_names(bus);
929}
930
931static void pci_bus_slot_names(struct device_node *node, struct pci_bus *bus)
932{
933 const struct pci_slot_names {
934 u32 slot_mask;
935 char names[0];
936 } *prop;
937 const char *sp;
938 int len, i;
939 u32 mask;
940
941 prop = of_get_property(node, "slot-names", &len);
942 if (!prop)
943 return;
944
945 mask = prop->slot_mask;
946 sp = prop->names;
947
948 if (ofpci_verbose)
949 pci_info(bus, "Making slots for [%pOF] mask[0x%02x]\n",
950 node, mask);
951
952 i = 0;
953 while (mask) {
954 struct pci_slot *pci_slot;
955 u32 this_bit = 1 << i;
956
957 if (!(mask & this_bit)) {
958 i++;
959 continue;
960 }
961
962 if (ofpci_verbose)
963 pci_info(bus, "Making slot [%s]\n", sp);
964
965 pci_slot = pci_create_slot(bus, i, sp, NULL);
966 if (IS_ERR(pci_slot))
967 pci_err(bus, "pci_create_slot returned %ld\n",
968 PTR_ERR(pci_slot));
969
970 sp += strlen(sp) + 1;
971 mask &= ~this_bit;
972 i++;
973 }
974}
975
976static int __init of_pci_slot_init(void)
977{
978 struct pci_bus *pbus = NULL;
979
980 while ((pbus = pci_find_next_bus(pbus)) != NULL) {
981 struct device_node *node;
982 struct pci_dev *pdev;
983
984 pdev = list_first_entry(&pbus->devices, struct pci_dev,
985 bus_list);
986
987 if (pdev && pci_is_pcie(pdev)) {
988 pcie_bus_slot_names(pbus);
989 } else {
990
991 if (pbus->self) {
992
993 /* PCI->PCI bridge */
994 node = pbus->self->dev.of_node;
995
996 } else {
997 struct pci_pbm_info *pbm = pbus->sysdata;
998
999 /* Host PCI controller */
1000 node = pbm->op->dev.of_node;
1001 }
1002
1003 pci_bus_slot_names(node, pbus);
1004 }
1005 }
1006
1007 return 0;
1008}
1009device_initcall(of_pci_slot_init);
1010#endif